context.S 6.0 KB

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  1. #include "riscv_encoding.h"
  2. #ifndef __riscv_32e
  3. #define portRegNum 32
  4. #else
  5. #define portRegNum 14
  6. #endif
  7. #define portCONTEXT_SIZE ( portRegNum * REGBYTES )
  8. .extern _tx_thread_current_ptr
  9. .extern _tx_thread_execute_ptr
  10. .section .text
  11. /*
  12. * VOID _tx_thread_schedule(VOID);
  13. */
  14. .globl _tx_thread_schedule
  15. /* Start the first task. This also clears the bit that indicates the FPU is
  16. in use in case the FPU was used before the scheduler was started - which
  17. would otherwise result in the unnecessary leaving of space in the stack
  18. for lazy saving of FPU registers. */
  19. .align 3
  20. .type _tx_thread_schedule, @function
  21. _tx_thread_schedule:
  22. /* Setup Interrupt Stack using
  23. The stack that was used by main()
  24. before the scheduler is started is
  25. no longer required after the scheduler is started.
  26. Interrupt stack pointer is stored in CSR_MSCRATCH */
  27. la t0, _sp
  28. csrw CSR_MSCRATCH, t0
  29. /* Enable interrupt to wait _tx_thread_execute_ptr is not null */
  30. csrsi CSR_MSTATUS, MSTATUS_MIE
  31. _tx_thread_schedule_loop:
  32. la a0, _tx_thread_execute_ptr /* Pick current thread to a0 */
  33. LOAD a0, 0(a0)
  34. beqz a0, _tx_thread_schedule_loop
  35. _tx_thread_schedule_ready:
  36. /* Disable interrupt to load first thread */
  37. csrci CSR_MSTATUS, MSTATUS_MIE
  38. la a1, _tx_thread_current_ptr /* _tx_thread_current_ptr = _tx_thread_execute_ptr */
  39. STORE a0, 0(a1)
  40. /* Increment the run count for this thread. */
  41. /* _tx_thread_current_ptr -> tx_thread_run_count++; */
  42. LOAD t0, 1 * REGBYTES(a0)
  43. addi t0, t0, 1
  44. STORE t0, 1 * REGBYTES(a0)
  45. LOAD sp, 2 * REGBYTES(a0) /* Read sp from _tx_thread_execute_ptr -> tx_thread_stack_ptr */
  46. /* Pop PC from stack and set MEPC */
  47. LOAD t0, 0 * REGBYTES(sp)
  48. csrw CSR_MEPC, t0
  49. /* Pop mstatus from stack and set it */
  50. LOAD t0, (portRegNum - 1) * REGBYTES(sp)
  51. csrw CSR_MSTATUS, t0
  52. /* Interrupt still disable here */
  53. /* Restore Registers from Stack */
  54. LOAD x1, 1 * REGBYTES(sp) /* RA */
  55. LOAD x5, 2 * REGBYTES(sp)
  56. LOAD x6, 3 * REGBYTES(sp)
  57. LOAD x7, 4 * REGBYTES(sp)
  58. LOAD x8, 5 * REGBYTES(sp)
  59. LOAD x9, 6 * REGBYTES(sp)
  60. LOAD x10, 7 * REGBYTES(sp)
  61. LOAD x11, 8 * REGBYTES(sp)
  62. LOAD x12, 9 * REGBYTES(sp)
  63. LOAD x13, 10 * REGBYTES(sp)
  64. LOAD x14, 11 * REGBYTES(sp)
  65. LOAD x15, 12 * REGBYTES(sp)
  66. #ifndef __riscv_32e
  67. LOAD x16, 13 * REGBYTES(sp)
  68. LOAD x17, 14 * REGBYTES(sp)
  69. LOAD x18, 15 * REGBYTES(sp)
  70. LOAD x19, 16 * REGBYTES(sp)
  71. LOAD x20, 17 * REGBYTES(sp)
  72. LOAD x21, 18 * REGBYTES(sp)
  73. LOAD x22, 19 * REGBYTES(sp)
  74. LOAD x23, 20 * REGBYTES(sp)
  75. LOAD x24, 21 * REGBYTES(sp)
  76. LOAD x25, 22 * REGBYTES(sp)
  77. LOAD x26, 23 * REGBYTES(sp)
  78. LOAD x27, 24 * REGBYTES(sp)
  79. LOAD x28, 25 * REGBYTES(sp)
  80. LOAD x29, 26 * REGBYTES(sp)
  81. LOAD x30, 27 * REGBYTES(sp)
  82. LOAD x31, 28 * REGBYTES(sp)
  83. #endif
  84. addi sp, sp, portCONTEXT_SIZE
  85. mret
  86. .size _tx_thread_schedule, . - _tx_thread_schedule
  87. .align 2
  88. .global eclic_msip_handler
  89. .type eclic_msip_handler, @function
  90. eclic_msip_handler:
  91. addi sp, sp, -portCONTEXT_SIZE
  92. STORE x1, 1 * REGBYTES(sp) /* RA */
  93. STORE x5, 2 * REGBYTES(sp)
  94. STORE x6, 3 * REGBYTES(sp)
  95. STORE x7, 4 * REGBYTES(sp)
  96. STORE x8, 5 * REGBYTES(sp)
  97. STORE x9, 6 * REGBYTES(sp)
  98. STORE x10, 7 * REGBYTES(sp)
  99. STORE x11, 8 * REGBYTES(sp)
  100. STORE x12, 9 * REGBYTES(sp)
  101. STORE x13, 10 * REGBYTES(sp)
  102. STORE x14, 11 * REGBYTES(sp)
  103. STORE x15, 12 * REGBYTES(sp)
  104. #ifndef __riscv_32e
  105. STORE x16, 13 * REGBYTES(sp)
  106. STORE x17, 14 * REGBYTES(sp)
  107. STORE x18, 15 * REGBYTES(sp)
  108. STORE x19, 16 * REGBYTES(sp)
  109. STORE x20, 17 * REGBYTES(sp)
  110. STORE x21, 18 * REGBYTES(sp)
  111. STORE x22, 19 * REGBYTES(sp)
  112. STORE x23, 20 * REGBYTES(sp)
  113. STORE x24, 21 * REGBYTES(sp)
  114. STORE x25, 22 * REGBYTES(sp)
  115. STORE x26, 23 * REGBYTES(sp)
  116. STORE x27, 24 * REGBYTES(sp)
  117. STORE x28, 25 * REGBYTES(sp)
  118. STORE x29, 26 * REGBYTES(sp)
  119. STORE x30, 27 * REGBYTES(sp)
  120. STORE x31, 28 * REGBYTES(sp)
  121. #endif
  122. /* Push mstatus to stack */
  123. csrr t0, CSR_MSTATUS
  124. STORE t0, (portRegNum - 1) * REGBYTES(sp)
  125. /* Push additional registers */
  126. /* If _tx_thread_current_ptr is null, no sp need to be saved */
  127. la t0, _tx_thread_current_ptr
  128. LOAD t0, 0(t0)
  129. beqz t0, _tx_thread_switch
  130. /* Store sp to task stack to _tx_thread_current_ptr -> tx_thread_stack_ptr */
  131. STORE sp, 2 * REGBYTES(t0)
  132. /* Store last pc to thread stack */
  133. csrr t0, CSR_MEPC
  134. STORE t0, 0(sp)
  135. _tx_thread_switch:
  136. jal PortThreadSwitch
  137. /* Switch task context to _tx_thread_execute_ptr */
  138. la t0, _tx_thread_execute_ptr
  139. LOAD t0, 0(t0)
  140. LOAD sp, 2 * REGBYTES(t0)
  141. /* Pop PC from stack and set MEPC */
  142. LOAD t0, 0 * REGBYTES(sp)
  143. csrw CSR_MEPC, t0
  144. /* Pop additional registers */
  145. /* Pop mstatus from stack and set it */
  146. LOAD t0, (portRegNum - 1) * REGBYTES(sp)
  147. csrw CSR_MSTATUS, t0
  148. /* Interrupt still disable here */
  149. /* Restore Registers from Stack */
  150. LOAD x1, 1 * REGBYTES(sp) /* RA */
  151. LOAD x5, 2 * REGBYTES(sp)
  152. LOAD x6, 3 * REGBYTES(sp)
  153. LOAD x7, 4 * REGBYTES(sp)
  154. LOAD x8, 5 * REGBYTES(sp)
  155. LOAD x9, 6 * REGBYTES(sp)
  156. LOAD x10, 7 * REGBYTES(sp)
  157. LOAD x11, 8 * REGBYTES(sp)
  158. LOAD x12, 9 * REGBYTES(sp)
  159. LOAD x13, 10 * REGBYTES(sp)
  160. LOAD x14, 11 * REGBYTES(sp)
  161. LOAD x15, 12 * REGBYTES(sp)
  162. #ifndef __riscv_32e
  163. LOAD x16, 13 * REGBYTES(sp)
  164. LOAD x17, 14 * REGBYTES(sp)
  165. LOAD x18, 15 * REGBYTES(sp)
  166. LOAD x19, 16 * REGBYTES(sp)
  167. LOAD x20, 17 * REGBYTES(sp)
  168. LOAD x21, 18 * REGBYTES(sp)
  169. LOAD x22, 19 * REGBYTES(sp)
  170. LOAD x23, 20 * REGBYTES(sp)
  171. LOAD x24, 21 * REGBYTES(sp)
  172. LOAD x25, 22 * REGBYTES(sp)
  173. LOAD x26, 23 * REGBYTES(sp)
  174. LOAD x27, 24 * REGBYTES(sp)
  175. LOAD x28, 25 * REGBYTES(sp)
  176. LOAD x29, 26 * REGBYTES(sp)
  177. LOAD x30, 27 * REGBYTES(sp)
  178. LOAD x31, 28 * REGBYTES(sp)
  179. #endif
  180. addi sp, sp, portCONTEXT_SIZE
  181. mret
  182. .size eclic_msip_handler, . - eclic_msip_handler