main.c 4.0 KB

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  1. #include <stdio.h>
  2. #include <string.h>
  3. #include "cpuinfo.h"
  4. #include "nuclei_sdk_soc.h"
  5. #define BUFSIZE 2048
  6. int main(void)
  7. {
  8. static char cpufeatbuf[BUFSIZE];
  9. #ifdef CFG_CPU_NAME
  10. printf("CPU NAME: %s\n", CFG_CPU_NAME);
  11. #endif
  12. #ifdef CFG_CPU_VERSION
  13. printf("CPU VERSION: %s\n", CFG_CPU_VERSION);
  14. #endif
  15. #ifdef CPU_ISA
  16. printf("CPU ISA: %s\n", CPU_ISA);
  17. #endif
  18. CPU_INFO_Group cpuinfo;
  19. memset(&cpuinfo, 0, sizeof(cpuinfo)); // clear the struct
  20. cpuinfo.marchid.d = (uint32_t)__RV_CSR_READ(CSR_MARCHID);
  21. cpuinfo.mhartid = (uint32_t)__RV_CSR_READ(CSR_MHARTID);
  22. cpuinfo.mimpid.d = (uint32_t)__RV_CSR_READ(CSR_MIMPID);
  23. cpuinfo.misa.d = (uint32_t)__RV_CSR_READ(CSR_MISA);
  24. U32_CSR_MCFG_INFO_Type mcfg;
  25. if (cpuinfo.marchid.d == 0x80000022U && cpuinfo.mimpid.d == 0x100U) {
  26. cpuinfo.mcfg_exist = 0;
  27. mcfg.d = 0;
  28. } else {
  29. cpuinfo.mcfg_exist = 1;
  30. mcfg.d = (uint32_t)__RV_CSR_READ(CSR_MCFG_INFO);
  31. }
  32. // NOTE: workaround for n100, since the CSR mcfg_info not present in n100,
  33. // but eclic and iregion present
  34. #if defined(CPU_SERIES) && CPU_SERIES == 100
  35. mcfg.d = 0;
  36. #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
  37. // mirgb_info csr present for n100 with eclic, this csr will not be zero
  38. if (__RV_CSR_READ(CSR_MIRGB_INFO) != 0) {
  39. mcfg.b.iregion = 1;
  40. mcfg.b.eclic = 1;
  41. } else {
  42. cpuinfo.mcfg_exist = 0;
  43. }
  44. #endif
  45. #endif
  46. cpuinfo.mcfginfo = mcfg;
  47. if (__RISCV_XLEN == 32) {
  48. cpuinfo.xlen = 32;
  49. if (mcfg.b.plic) {
  50. cpuinfo.mtlbcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MTLBCFG_INFO);
  51. }
  52. } else {
  53. cpuinfo.xlen = 64;
  54. /**
  55. * mtlbcfginfo has a `mapping` field at the highest bit.
  56. * For RV64, move the bit 63 to bit 31 to use the common
  57. * struct as RV32.
  58. */
  59. if (mcfg.b.plic) {
  60. uint64_t mtlbcfginfo = __RV_CSR_READ(CSR_MTLBCFG_INFO);
  61. cpuinfo.mtlbcfginfo.d =
  62. (uint32_t)mtlbcfginfo | (uint32_t)((mtlbcfginfo >> 63) << 31);
  63. }
  64. }
  65. if (mcfg.b.icache || mcfg.b.ilm) {
  66. cpuinfo.micfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MICFG_INFO);
  67. }
  68. if (mcfg.b.dcache || mcfg.b.dlm) {
  69. cpuinfo.mdcfginfo.d = (uint32_t)__RV_CSR_READ(CSR_MDCFG_INFO);
  70. }
  71. if (mcfg.b.iregion) {
  72. cpuinfo.mirgbinfo.d = (uint64_t)__RV_CSR_READ(CSR_MIRGB_INFO);
  73. uint64_t iregion_base = cpuinfo.mirgbinfo.d & (~0x3FFULL);
  74. cpuinfo.iinfo = (IINFO_Type *)((unsigned long)iregion_base);
  75. cpuinfo.iregion_base = iregion_base;
  76. if (mcfg.b.smp) {
  77. cpuinfo.smpcfg.d = *(uint32_t *)((
  78. unsigned long)(iregion_base + CPUINFO_IRG_SMP_OFS + 0x4));
  79. }
  80. if (cpuinfo.smpcfg.b.cc) {
  81. cpuinfo.cccfg.d = *(uint32_t *)((
  82. unsigned long)(iregion_base + CPUINFO_IRG_SMP_OFS + 0x8));
  83. }
  84. if (mcfg.b.eclic) {
  85. cpuinfo.eclic = (ECLIC_Type *)((
  86. unsigned long)(iregion_base + CPUINFO_IRG_ECLIC_OFS));
  87. }
  88. }
  89. if (mcfg.b.ppi) {
  90. cpuinfo.mppicfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MPPICFG_INFO);
  91. }
  92. if (mcfg.b.fio) {
  93. cpuinfo.mfiocfginfo.d = (uint64_t)__RV_CSR_READ(CSR_MFIOCFG_INFO);
  94. }
  95. IINFO_ISA_SUPPORT0_Type isa_support0;
  96. isa_support0.d = cpuinfo.iinfo->isa_support0;
  97. /* The init value of vlenb is 0, indicating that the vector extension is not supported */
  98. cpuinfo.vlenb = 0;
  99. /* misa.V only valid when the full vector extension is supported.
  100. * Judge vector extension existence from isa_support0.vector is more reliable */
  101. if (cpuinfo.misa.b.V || (isa_support0.b.exist && isa_support0.b.vector)) {
  102. /* Set mstatus.vs to enable vector extension, then read vlenb */
  103. __RV_CSR_SET(CSR_MSTATUS, MSTATUS_VS_INITIAL);
  104. cpuinfo.vlenb = __RV_CSR_READ(CSR_VLENB);
  105. }
  106. if (get_basic_cpuinfo(&cpuinfo, cpufeatbuf, BUFSIZE) > 0) {
  107. printf("%s\r\n", cpufeatbuf);
  108. }
  109. show_cpuinfo(&cpuinfo);
  110. return 0;
  111. }