system_evalsoc.h 6.1 KB

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  1. /*
  2. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  3. * Copyright (c) 2019 Nuclei Limited. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Licensed under the Apache License, Version 2.0 (the License); you may
  8. * not use this file except in compliance with the License.
  9. * You may obtain a copy of the License at
  10. *
  11. * www.apache.org/licenses/LICENSE-2.0
  12. *
  13. * Unless required by applicable law or agreed to in writing, software
  14. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  15. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  16. * See the License for the specific language governing permissions and
  17. * limitations under the License.
  18. */
  19. /*******************************************************************************
  20. * @file system_evalsoc.h
  21. * @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
  22. * Device <Device>
  23. * @version V1.00
  24. * @date 17. Dec 2019
  25. ******************************************************************************/
  26. #ifndef __SYSTEM_EVALSOC_H__ /* ToDo: replace '<Device>' with your device name */
  27. #define __SYSTEM_EVALSOC_H__
  28. // NOTE: Should never directly include this header, you should include evalsoc.h
  29. #ifdef __cplusplus
  30. extern "C" {
  31. #endif
  32. #include <stdint.h>
  33. extern volatile uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
  34. typedef struct EXC_Frame {
  35. unsigned long ra; /* ra: x1, return address for jump */
  36. unsigned long tp; /* tp: x4, thread pointer */
  37. unsigned long t0; /* t0: x5, temporary register 0 */
  38. unsigned long t1; /* t1: x6, temporary register 1 */
  39. unsigned long t2; /* t2: x7, temporary register 2 */
  40. unsigned long a0; /* a0: x10, return value or function argument 0 */
  41. unsigned long a1; /* a1: x11, return value or function argument 1 */
  42. unsigned long a2; /* a2: x12, function argument 2 */
  43. unsigned long a3; /* a3: x13, function argument 3 */
  44. unsigned long a4; /* a4: x14, function argument 4 */
  45. unsigned long a5; /* a5: x15, function argument 5 */
  46. unsigned long cause; /* cause: machine/supervisor mode cause csr register */
  47. unsigned long epc; /* epc: machine/ supervisor mode exception program counter csr register */
  48. unsigned long msubm; /* msubm: machine sub-mode csr register, nuclei customized, exclusive to machine mode */
  49. #ifndef __riscv_32e
  50. unsigned long a6; /* a6: x16, function argument 6 */
  51. unsigned long a7; /* a7: x17, function argument 7 */
  52. unsigned long t3; /* t3: x28, temporary register 3 */
  53. unsigned long t4; /* t4: x29, temporary register 4 */
  54. unsigned long t5; /* t5: x30, temporary register 5 */
  55. unsigned long t6; /* t6: x31, temporary register 6 */
  56. #endif
  57. } EXC_Frame_Type;
  58. /**
  59. * \brief Setup the microcontroller system.
  60. * \details
  61. * Initialize the System and update the SystemCoreClock variable.
  62. */
  63. extern void SystemInit(void);
  64. /**
  65. * \brief Update SystemCoreClock variable.
  66. * \details
  67. * Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
  68. */
  69. extern void SystemCoreClockUpdate(void);
  70. /**
  71. * \brief Dump Exception Frame
  72. */
  73. void Exception_DumpFrame(unsigned long sp, uint8_t mode);
  74. /**
  75. * \brief Register an exception handler for exception code EXCn
  76. */
  77. extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler);
  78. /**
  79. * \brief Get current exception handler for exception code EXCn
  80. */
  81. extern unsigned long Exception_Get_EXC(uint32_t EXCn);
  82. /**
  83. * \brief Initialize Interrupt as Clint interrupt mode
  84. */
  85. extern void CLINT_Interrupt_Init(void);
  86. /**
  87. * \brief Initialize Interrupt
  88. */
  89. extern void Interrupt_Init(void);
  90. #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
  91. /**
  92. * \brief Do ECLIC Interrupt configuration
  93. */
  94. extern void ECLIC_Interrupt_Init(void);
  95. /**
  96. * \brief Initialize a specific IRQ and register the handler
  97. * \details
  98. * This function set vector mode, trigger mode and polarity, interrupt level and priority,
  99. * assign handler for specific IRQn.
  100. */
  101. extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
  102. #endif
  103. /**
  104. * \brief Register an core interrupt handler for clint/plic interrupt mode
  105. */
  106. extern void Interrupt_Register_CoreIRQ(uint32_t irqn, unsigned long int_handler);
  107. /**
  108. * \brief Register an plic external interrupt handler for clint/plic interrupt mode
  109. */
  110. extern void Interrupt_Register_ExtIRQ(uint32_t irqn, unsigned long int_handler);
  111. /**
  112. * \brief Register a riscv core interrupt and register the handler for clint/plic interrupt mode
  113. */
  114. extern int32_t Core_Register_IRQ(uint32_t irqn, void *handler);
  115. #if defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1)
  116. /**
  117. * \brief Do plic interrupt configuration for clint/plic interrupt mode
  118. */
  119. extern void PLIC_Interrupt_Init(void);
  120. /**
  121. * \brief Register a specific plic interrupt and register the handler
  122. */
  123. extern int32_t PLIC_Register_IRQ(uint32_t source, uint8_t priority, void *handler);
  124. #endif
  125. #if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
  126. /**
  127. * \brief Register an exception handler for exception code EXCn of supervisor mode
  128. */
  129. extern void Exception_Register_EXC_S(uint32_t EXCn, unsigned long exc_handler);
  130. /**
  131. * \brief Get current exception handler for exception code EXCn of supervisor mode
  132. */
  133. extern unsigned long Exception_Get_EXC_S(uint32_t EXCn);
  134. #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
  135. /**
  136. * \brief Initialize a specific IRQ and register the handler of supervisor mode
  137. * \details
  138. * This function set vector mode, trigger mode and polarity, interrupt level and priority,
  139. * assign handler for specific IRQn.
  140. */
  141. extern int32_t ECLIC_Register_IRQ_S(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
  142. #endif
  143. #endif
  144. #ifdef __cplusplus
  145. }
  146. #endif
  147. #endif /* __SYSTEM_EVALSOC_H__ */