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bench_n300.json

bench_n300.json 2.2 KB
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  1. {
    2. 

  2.     "build_config": {
    3. 

  3.         "SOC": "evalsoc",
    4. 

  4.         "CPU_SERIES": "300"
    5. 

  5.     },
    6. 

  6.     "build_configs": {
    7. 

  7.         "rv32imac": {"CORE":"n300"},
    8. 

  8.         "rv32imac_zicond": {"CORE":"n300", "ARCH_EXT":"_zicond"},
    9. 

  9.         "rv32imacb": {"CORE":"n300", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
    10. 

  10.         "rv32imacb_zicond": {"CORE":"n300", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond"},
    11. 

  11.         "rv32imab_zc_zicond": {"CORE":"n300", "ARCH_EXT":"_zca_zcb_zcmp_zcmt_zba_zbb_zbc_zbs_zicond"},
    12. 

  12.         "rv32imacbp": {"CORE":"n300", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
    13. 

  13.         "rv32imacbp_zicond": {"CORE":"n300", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
    14. 

  14.         "rv32imafc": {"CORE":"n300f", "ARCH_EXT":""},
    15. 

  15.         "rv32imafcb": {"CORE":"n300f", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
    16. 

  16.         "rv32imafcp": {"CORE":"n300f", "ARCH_EXT":"_xxldspn1x"},
    17. 

  17.         "rv32imafcbp": {"CORE":"n300f", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
    18. 

  18.         "rv32imafcbp_zicond": {"CORE":"n300f", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
    19. 

  19.         "rv32imafbp_zc": {"CORE":"n300f", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x"},
    20. 

  20.         "rv32imafbp_xxlcz": {"CORE":"n300f", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
    21. 

  21.         "rv32imafbp_zc_xxlcz": {"CORE":"n300f", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
    22. 

  22.         "rv32imafbp_zicond_zc_xxlcz": {"CORE":"n300f", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_zicond_xxldspn1x_xxlcz"},
    23. 

  23.         "rv32imafdc": {"CORE":"n300fd", "ARCH_EXT":""},
    24. 

  24.         "rv32imafdcb": {"CORE":"n300fd", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
    25. 

  25.         "rv32imafdcp": {"CORE":"n300fd", "ARCH_EXT":"_xxldspn1x"},
    26. 

  26.         "rv32imafdcbp": {"CORE":"n300fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
    27. 

  27.         "rv32imafdcbp_zicond": {"CORE":"n300fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
    28. 

  28.         "rv32imafdbp_zc": {"CORE":"n300fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x"},
    29. 

  29.         "rv32imafdbp_xxlcz": {"CORE":"n300fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
    30. 

  30.         "rv32imafdbp_zc_xxlcz": {"CORE":"n300fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
    31. 

  31.         "rv32imafdbp_zicond_zc_xxlcz": {"CORE":"n300fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_zicond_xxldspn1x_xxlcz"}
    32. 

  32.     }
    33. 

  33. }
    34.