nuclei-sdk/tools/scripts/misc/dobench/bench_n900.json

{
    "build_config": {
        "SOC": "evalsoc",
        "CPU_SERIES": "900"
    },
    "build_configs": {
        "rv32imac": {"CORE":"n900"},
        "rv32imac_zicond": {"CORE":"n900", "ARCH_EXT":"_zicond"},
        "rv32imacb": {"CORE":"n900", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
        "rv32imacb_zicond": {"CORE":"n900", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond"},
        "rv32imab_zc_zicond": {"CORE":"n900", "ARCH_EXT":"_zca_zcb_zcmp_zcmt_zba_zbb_zbc_zbs_zicond"},
        "rv32imacbp": {"CORE":"n900", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
        "rv32imacbp_zicond": {"CORE":"n900", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
        "rv32imafc": {"CORE":"n900f", "ARCH_EXT":""},
        "rv32imafcb": {"CORE":"n900f", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
        "rv32imafcp": {"CORE":"n900f", "ARCH_EXT":"_xxldspn1x"},
        "rv32imafcbp": {"CORE":"n900f", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
        "rv32imafcbp_zicond": {"CORE":"n900f", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
        "rv32imafbp_zc": {"CORE":"n900f", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x"},
        "rv32imafbp_xxlcz": {"CORE":"n900f", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
        "rv32imafbp_zc_xxlcz": {"CORE":"n900f", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
        "rv32imafdc": {"CORE":"n900fd", "ARCH_EXT":""},
        "rv32imafdcb": {"CORE":"n900fd", "ARCH_EXT":"_zba_zbb_zbc_zbs"},
        "rv32imafdcp": {"CORE":"n900fd", "ARCH_EXT":"_xxldspn1x"},
        "rv32imafdcbp": {"CORE":"n900fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x"},
        "rv32imafdcbp_zicond": {"CORE":"n900fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_zicond_xxldspn1x"},
        "rv32imafdbp_zc": {"CORE":"n900fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x"},
        "rv32imafdbp_xxlcz": {"CORE":"n900fd", "ARCH_EXT":"_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
        "rv32imafdbp_zc_xxlcz": {"CORE":"n900fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_xxldspn1x_xxlcz"},
        "rv32imafdbp_zc_zicond_xxlcz": {"CORE":"n900fd", "ARCH_EXT":"_zca_zcb_zcf_zcmp_zcmt_zba_zbb_zbc_zbs_zicond_xxldspn1x_xxlcz"}
    }
}