Merge pull request #1 from Guozhanxin/master

first version

.gitignore

@@ -0,0 +1,43 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+*.crf
+build
+Debug
+documentation/html
+*~
+*.o
+*.obj
+*.bak
+*.dep
+*.lib
+*.a
+*.i
+*.d
+tools/kconfig-frontends/kconfig-mconf
+dist
+dist_ide_project
+cconfig.h
+GPUCache
+
+#cscope files
+cscope.*
+ncscope.*
+
+#ctag files
+tags
+
+.idea
+.vscode
+.history
+CMakeLists.txt
+cmake-build-debug

libraries/HAL_Drivers/Kconfig

@@ -0,0 +1,20 @@
+config BSP_USING_GPIO
+    bool "Enable GPIO"
+    select RT_USING_PIN
+    default y
+
+config BSP_USING_ONCHIP_FLASH
+    bool "Enable Onchip FLASH"
+    default n
+
+config BSP_USING_WDT
+    bool "Enable Watchdog Timer"
+    select RT_USING_WDT
+    default n
+
+menuconfig BSP_USING_ONCHIP_RTC
+    bool "Enable RTC"
+    select RT_USING_RTC
+    default n
+    if BSP_USING_ONCHIP_RTC
+    endif

libraries/HAL_Drivers/SConscript

@@ -0,0 +1,61 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+    drv_common.c
+""")
+
+if GetDepend(['BSP_USING_UART']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        print("\nThe current project does not support serial-v1\n")
+        Return('group')
+
+if GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_I2C', 'BSP_USING_HW_I2C']): 
+        src += ['drv_i2c.c']
+
+if GetDepend(['BSP_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['BSP_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['BSP_USING_ONCHIP_FLASH']):
+    src += ['drv_flash.c']
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['BSP_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['BSP_USING_SDHI']):
+    src += ['drv_sdhi.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

libraries/HAL_Drivers/config/drv_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include "board.h"
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SOC_SERIES_R7FA6M4
+#include "ra6m4/uart_config.h"
+
+#ifdef BSP_USING_ADC
+#include "ra6m4/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra6m4/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra6m4/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_CAN
+#include "ra6m4/can_config.h"
+#endif
+#endif/* SOC_SERIES_R7FA6M4 */
+
+#ifdef SOC_SERIES_R7FA2L1
+#include "ra2l1/uart_config.h"
+
+#ifdef BSP_USING_ADC
+#include "ra2l1/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra2l1/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra2l1/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_CAN
+#include "ra2l1/can_config.h"
+#endif
+#endif/* SOC_SERIES_R7FA2L1 */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif/* __DRV_CONFIG_H__ */

libraries/HAL_Drivers/config/ra2l1/adc_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+struct ra_adc_map
+{
+    char name;
+    const adc_cfg_t *g_cfg;
+    const adc_instance_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+
+struct ra_dev
+{
+    rt_adc_device_t     ra_adc_device_t;
+    struct ra_adc_map  *ra_adc_dev;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

libraries/HAL_Drivers/config/ra2l1/can_config.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                                                 \
+    {                                                               \
+        .name = "can0",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0,             \
+        .p_api_ctrl = &g_can0_ctrl,                                \
+        .p_cfg = &g_can0_cfg,                                      \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                                 \
+    {                                                               \
+        .name = "can1",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1,             \
+        .p_api_ctrl = &g_can1_ctrl,                                \
+        .p_cfg = &g_can1_cfg,                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif

libraries/HAL_Drivers/config/ra2l1/dac_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

libraries/HAL_Drivers/config/ra2l1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-26     KevinXu           first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

libraries/HAL_Drivers/config/ra2l1/uart_config.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .p_api_ctrl = &g_uart0_ctrl,                                \
+        .p_cfg = &g_uart0_cfg,                                      \
+    }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .p_api_ctrl = &g_uart1_ctrl,                                \
+        .p_cfg = &g_uart1_cfg,                                      \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .p_api_ctrl = &g_uart2_ctrl,                                \
+        .p_cfg = &g_uart2_cfg,                                      \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .p_api_ctrl = &g_uart3_ctrl,                                \
+        .p_cfg = &g_uart3_cfg,                                      \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART9)
+#ifndef UART9_CONFIG
+#define UART9_CONFIG                                                \
+    {                                                               \
+        .name = "uart9",                                            \
+        .p_api_ctrl = &g_uart9_ctrl,                                \
+        .p_cfg = &g_uart9_cfg,                                      \
+    }
+#endif /* UART9_CONFIG */
+#endif /* BSP_USING_UART9 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/HAL_Drivers/drv_adc.c

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include "drv_config.h"
+#ifdef RT_USING_ADC
+
+// #define DRV_DEBUG
+#define DBG_TAG              "drv.adc"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_adc_map ra_adc[] =
+{
+#if defined(BSP_USING_ADC0)
+    {'0', &g_adc0_cfg, &g_adc0_ctrl, &g_adc0_channel_cfg},
+#endif
+
+#if defined(BSP_USING_ADC1)
+    {'1', &g_adc1_cfg, &g_adc1_ctrl, &g_adc1_channel_cfg},
+#endif
+};
+
+#if defined(BSP_USING_ADC0)
+struct rt_adc_device adc0_device;
+struct ra_dev _ra_adc0_device = {.ra_adc_device_t = &adc0_device, .ra_adc_dev = &ra_adc[0]};
+#endif
+
+#if defined(BSP_USING_ADC1)
+struct rt_adc_device adc1_device;
+struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]};
+#endif
+
+static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    /**< start adc*/
+    if (enabled)
+    {
+        if (FSP_SUCCESS != R_ADC_ScanStart((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("start adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    else
+    {
+        /**< stop adc*/
+        if (FSP_SUCCESS != R_ADC_ScanStop((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("stop adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_adc_close(struct rt_adc_device *device)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)(struct ra_adc_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_ADC_Close((adc_ctrl_t *)adc->g_ctrl))
+    {
+        LOG_E("close adc%c failed.", adc->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    if (RT_EOK != R_ADC_Read32((adc_ctrl_t *)adc->g_ctrl, channel, value))
+    {
+        LOG_E("get adc value failed.\n");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops ra_adc_ops =
+{
+    .enabled = ra_adc_enabled,
+    .convert = ra_get_adc_value,
+};
+
+static int ra_adc_init(void)
+{
+#if defined(BSP_USING_ADC0)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc0_device.ra_adc_device_t, "adc0", &ra_adc_ops, (void *)_ra_adc0_device.ra_adc_dev))
+    {
+        LOG_E("adc0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#if defined(BSP_USING_ADC1)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc1_device.ra_adc_device_t, "adc1", &ra_adc_ops, (void *)_ra_adc1_device.ra_adc_dev))
+    {
+        LOG_E("adc1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(ra_adc_init);
+#endif

libraries/HAL_Drivers/drv_can.c

@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#include "drv_can.h"
+
+static struct ra_can_config can_config[] =
+{
+#ifdef BSP_USING_CAN0
+    CAN0_CONFIG,
+#endif
+
+#ifdef BSP_USING_CAN1
+    CAN1_CONFIG
+#endif
+};
+
+enum
+{
+#ifdef BSP_USING_CAN0
+    CAN0_INDEX,
+#endif
+
+#ifdef BSP_USING_CAN1
+    CAN1_INDEX,
+#endif
+};
+
+static struct ra_can can_obj[sizeof(can_config) / sizeof(can_config[0])] = {0};
+
+static const struct ra_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, 3, 6, 3, 1 + 4},
+    {CAN800kBaud, 4, 15, 5, 1 + 2},
+    {CAN500kBaud, 4, 14, 5, 1 + 4},
+    {CAN250kBaud, 4, 14, 5, 1 + 9},
+    {CAN125kBaud, 4, 14, 5, 1 + 19},
+    {CAN100kBaud, 4, 14, 5, 1 + 24},
+    {CAN50kBaud, 4, 14, 5, 1 + 49},
+    {CAN20kBaud, 4, 14, 5, 1 + 124},
+    {CAN10kBaud, 4, 14, 5, 1 + 249}
+};
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+    rt_uint32_t len, index;
+
+    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+    for (index = 0; index < len; index++)
+    {
+        if (can_baud_rate_tab[index].baud_rate == baud)
+            return index;
+    }
+
+    return 0; /* default baud is CAN1MBaud */
+}
+
+static void ra_can_get_config(void)
+{
+    struct can_configure config = CANDEFAULTCONFIG;
+#ifdef BSP_USING_CAN0
+    can_obj[CAN0_INDEX].can_dev.config = config;
+    can_obj[CAN0_INDEX].can_dev.config.msgboxsz = CAN_NO_OF_MAILBOXES_g_can0;
+    can_obj[CAN0_INDEX].can_dev.config.sndboxnumber = 1;
+    can_obj[CAN0_INDEX].can_dev.config.ticks = 50;
+#endif
+#ifdef BSP_USING_CAN1
+    can_obj[CAN1_INDEX].can_dev.config = config;
+    can_obj[CAN1_INDEX].can_dev.config.msgboxsz = CAN_NO_OF_MAILBOXES_g_can1;
+    can_obj[CAN1_INDEX].can_dev.config.sndboxnumber = 1;
+    can_obj[CAN1_INDEX].can_dev.config.ticks = 50;
+#endif
+}
+rt_err_t ra_can_configure(struct rt_can_device *can_dev, struct can_configure *cfg)
+{
+    struct ra_can *can;
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    fsp_err_t err = FSP_SUCCESS;
+
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(can != RT_NULL);
+    err = R_CAN_Open(can->config->p_api_ctrl, can->config->p_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        return RT_ERROR;
+    }
+    return RT_EOK;
+}
+rt_err_t ra_can_control(struct rt_can_device *can_dev, int cmd, void *arg)
+{
+    struct ra_can *can;
+    can_info_t can_info;
+    rt_uint32_t argval;
+    RT_ASSERT(can_dev != RT_NULL);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        R_BSP_IrqStatusClear((IRQn_Type)arg);
+        break;
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud &&
+                argval != CAN800kBaud &&
+                argval != CAN500kBaud &&
+                argval != CAN250kBaud &&
+                argval != CAN125kBaud &&
+                argval != CAN100kBaud &&
+                argval != CAN50kBaud  &&
+                argval != CAN20kBaud  &&
+                argval != CAN10kBaud)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can->can_dev.config.baud_rate)
+        {
+            can->can_dev.config.baud_rate = argval;
+            uint32_t index = get_can_baud_index(argval);
+            can->config->p_cfg->p_bit_timing->baud_rate_prescaler = can_baud_rate_tab[index].prescaler;
+            can->config->p_cfg->p_bit_timing->synchronization_jump_width = can_baud_rate_tab[index].sjw;
+            can->config->p_cfg->p_bit_timing->time_segment_1 = can_baud_rate_tab[index].ts1;
+            can->config->p_cfg->p_bit_timing->time_segment_2 = can_baud_rate_tab[index].ts2;
+            return ra_can_configure(&can->can_dev, &can->can_dev.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL &&
+                argval != RT_CAN_MODE_LISTEN &&
+                argval != RT_CAN_MODE_LOOPBACK)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can->can_dev.config.mode)
+        {
+            can_test_mode_t mode_to_set;
+            can->can_dev.config.mode = argval;
+            switch (argval)
+            {
+            case RT_CAN_MODE_NORMAL:
+                mode_to_set = CAN_TEST_MODE_DISABLED;
+            case RT_CAN_MODE_LISTEN:
+                mode_to_set = CAN_TEST_MODE_LISTEN;
+            case RT_CAN_MODE_LOOPBACK:
+                mode_to_set = CAN_TEST_MODE_LOOPBACK_INTERNAL;
+            }
+            R_CAN_ModeTransition(can->config->p_api_ctrl, ((can_instance_ctrl_t *)(can->config->p_api_ctrl))->operation_mode, mode_to_set);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+        R_CAN_InfoGet(can->config->p_api_ctrl, &can_info);
+        can->can_dev.status.rcverrcnt = can_info.error_count_receive;
+        can->can_dev.status.snderrcnt = can_info.error_count_transmit;
+        can->can_dev.status.errcode = can_info.error_code;
+        rt_memcpy(arg, &can->can_dev.status, sizeof(can->can_dev.status));
+        break;
+    default:
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+int ra_can_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uint32_t boxno)
+{
+    struct ra_can *can;
+    can_frame_t g_can_tx_frame;
+    struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf;
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    g_can_tx_frame.id = msg_rt->id;
+    g_can_tx_frame.id_mode = msg_rt->ide;
+    g_can_tx_frame.type = msg_rt->rtr;
+    g_can_tx_frame.data_length_code = msg_rt->len;
+    g_can_tx_frame.options = 0;
+    memcpy(g_can_tx_frame.data, msg_rt->data, 8);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(boxno < can->config->num_of_mailboxs);
+
+    if (R_CAN_Write(can->config->p_api_ctrl, boxno, &g_can_tx_frame) != FSP_SUCCESS)
+    {
+        rt_exit_critical();
+        return RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int ra_can_recvmsg(struct rt_can_device *can_dev, void *buf, rt_uint32_t boxno)
+{
+    struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf;
+    can_frame_t *msg_ra;
+    struct ra_can *can;
+
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(boxno < can->config->num_of_mailboxs);
+    if (can->callback_args->mailbox != boxno)
+        return 0;
+    msg_ra = can->callback_args->p_frame;
+
+    msg_rt->id = msg_ra->id;
+    msg_rt->ide = msg_ra->id_mode;
+    msg_rt->rtr = msg_ra->type;
+    msg_rt->rsv = RT_NULL;
+    msg_rt->len = msg_ra->data_length_code;
+    msg_rt->priv = boxno;
+    msg_rt->hdr = RT_NULL;
+    memcpy(msg_rt->data, msg_ra->data, msg_ra->data_length_code);
+    return sizeof(struct rt_can_msg);
+}
+const struct rt_can_ops ra_can_ops =
+{
+    .configure = ra_can_configure,
+    .control = ra_can_control,
+    .sendmsg = ra_can_sendmsg,
+    .recvmsg = ra_can_recvmsg
+};
+
+#ifdef BSP_USING_CAN0
+void can0_callback(can_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    switch (p_args->event)
+    {
+    case CAN_EVENT_TX_COMPLETE:
+        rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_TX_DONE | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_RX_COMPLETE:
+        can_obj[CAN0_INDEX].callback_args = p_args;
+        if (p_args->event == CAN_EVENT_RX_COMPLETE)
+            rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_RX_IND | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_TX_ABORTED:
+        rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_TX_FAIL | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_MAILBOX_MESSAGE_LOST:    //overwrite/overrun error event
+    case CAN_EVENT_BUS_RECOVERY:            //Bus recovery error event
+    case CAN_EVENT_ERR_BUS_OFF:             //error Bus Off event
+    case CAN_EVENT_ERR_PASSIVE:             //error passive event
+    case CAN_EVENT_ERR_WARNING:             //error warning event
+    case CAN_EVENT_ERR_BUS_LOCK:            //error bus lock
+    case CAN_EVENT_ERR_CHANNEL:             //error channel
+    case CAN_EVENT_ERR_GLOBAL:              //error global
+    {
+        break;
+    }
+    }
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_CAN1
+void can1_callback(can_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    switch (p_args->event)
+    {
+    case CAN_EVENT_TX_COMPLETE:
+        rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_TX_DONE | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_RX_COMPLETE:
+        can_obj[CAN1_INDEX].callback_args = p_args;
+        if (p_args->event == CAN_EVENT_RX_COMPLETE)
+            rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_RX_IND | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_TX_ABORTED:
+        rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_TX_FAIL | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_MAILBOX_MESSAGE_LOST:    //overwrite/overrun error event
+    case CAN_EVENT_BUS_RECOVERY:            //Bus recovery error event
+    case CAN_EVENT_ERR_BUS_OFF:             //error Bus Off event
+    case CAN_EVENT_ERR_PASSIVE:             //error passive event
+    case CAN_EVENT_ERR_WARNING:             //error warning event
+    case CAN_EVENT_ERR_BUS_LOCK:            //error bus lock
+    case CAN_EVENT_ERR_CHANNEL:             //error channel
+    case CAN_EVENT_ERR_GLOBAL:              //error global
+    {
+        break;
+    }
+    }
+    rt_interrupt_leave();
+}
+#endif
+
+int rt_hw_can_init(void)
+{
+    rt_err_t result = 0;
+    rt_size_t obj_num = sizeof(can_obj) / sizeof(struct ra_can);
+    ra_can_get_config();
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init CAN object */
+        can_obj[i].config = &can_config[i];
+        can_obj[i].can_dev.ops = &ra_can_ops;
+        /* register CAN device */
+        result = rt_hw_can_register(&can_obj[i].can_dev, can_obj[i].config->name, can_obj[i].can_dev.ops, RT_NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);

libraries/HAL_Drivers/drv_can.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+/* renesas config class */
+struct ra_can_config
+{
+    const char *name;
+    int num_of_mailboxs;
+    can_ctrl_t *const p_api_ctrl;
+    can_cfg_t const *const p_cfg;
+};
+
+struct ra_can
+{
+    struct rt_can_device can_dev;
+    struct ra_can_config *config;
+    can_callback_args_t *callback_args;
+};
+
+struct ra_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t sjw;
+    rt_uint32_t ts1;
+    rt_uint32_t ts2;
+    rt_uint32_t prescaler;
+};
+
+int rt_hw_can_init(void);
+
+#endif

libraries/HAL_Drivers/drv_common.c

@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#include <drv_common.h>
+#include <bsp_api.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+    #include <drv_gpio.h>
+#endif
+
+#ifdef RT_USING_SERIAL
+    #ifdef RT_USING_SERIAL_V2
+        #include <drv_usart_v2.h>
+    #else
+    #error "Serial-v1 has been obsoleted, and please select serial-v2 as the default option"
+    #endif
+#endif
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    NVIC_SystemReset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    NVIC_SetPriority(SysTick_IRQn, 0xFF);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void _Error_Handler(char *s, int num)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+
+    rt_hw_systick_init();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+FSP_CPP_HEADER
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+FSP_CPP_FOOTER
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+        /* Enable reading from data flash. */
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+         * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+    }
+
+    if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment and system clocks are setup. */
+
+        /* Configure pins. */
+        R_IOPORT_Open(&g_ioport_ctrl, g_ioport.p_cfg);
+    }
+}
+
+#if BSP_TZ_SECURE_BUILD
+
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ();
+
+/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ()
+{
+
+}
+#endif

libraries/HAL_Drivers/drv_common.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/HAL_Drivers/drv_dac.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include "drv_config.h"
+#ifdef RT_USING_DAC
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.dac"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_dac_map ra_dac[] =
+{
+#ifdef BSP_USING_DAC0
+    {'0', &g_dac0_cfg, &g_dac0_ctrl},
+#endif
+#ifdef BSP_USING_DAC1
+    {'1', &g_dac1_cfg, &g_dac1_ctrl},
+#endif
+};
+
+#ifdef BSP_USING_DAC0
+struct rt_dac_device dac0_device;
+struct ra_dac_dev _ra_dac0_device = {.ra_dac_device_t = &dac0_device, .ra_dac_map_dev = &ra_dac[0]};
+#endif
+
+#ifdef BSP_USING_DAC1
+struct rt_dac_device dac1_device;
+struct ra_dac_dev _ra_dac1_device = {.ra_dac_device_t = &dac1_device, .ra_dac_map_dev = &ra_dac[1]};
+#endif
+
+rt_err_t ra_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Stop((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c stop failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Start((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c start failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_write(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Write((dac_ctrl_t *)dac->g_ctrl, *value))
+    {
+        LOG_E("dac%c set value failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+struct rt_dac_ops ra_dac_ops =
+{
+    .disabled = ra_dac_disabled,
+    .enabled  = ra_dac_enabled,
+    .convert  = ra_dac_write,
+};
+
+static int ra_dac_init(void)
+{
+#ifdef BSP_USING_DAC0
+    _ra_dac0_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac0_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *)_ra_dac0_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac0_device.ra_dac_device_t, "dac0", &ra_dac_ops, (void *)_ra_dac0_device.ra_dac_map_dev))
+    {
+        LOG_E("dac0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#ifdef BSP_USING_DAC1
+    _ra_dac1_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac1_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *) _ra_dac1_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac1_device.ra_dac_device_t, "dac1", &ra_dac_ops, (void *)_ra_dac1_device.ra_dac_map_dev))
+    {
+        LOG_E("dac1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(ra_dac_init);
+
+#endif

libraries/HAL_Drivers/drv_flash.c

@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-30     flybreak     first version
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "board.h"
+#include "hal_data.h"
+
+#include "drv_common.h"
+
+#if defined(RT_USING_FAL)
+    #include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+#if BSP_FEATURE_FLASH_HP_VERSION
+    /* FLASH API */
+    #define R_FLASH_Open    R_FLASH_HP_Open
+    #define R_FLASH_Reset   R_FLASH_HP_Reset
+    #define R_FLASH_Write   R_FLASH_HP_Write
+    #define R_FLASH_Erase   R_FLASH_HP_Erase
+    #define R_FLASH_StartUpAreaSelect   R_FLASH_HP_StartUpAreaSelect
+    /* BSP_FEATURE_FLASH */
+    #define FLASH_CF_WRITE_SIZE     BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE
+
+#else /* FLASH LP */
+    /* FLASH API */
+    #define R_FLASH_Open    R_FLASH_LP_Open
+    #define R_FLASH_Reset   R_FLASH_LP_Reset
+    #define R_FLASH_Write   R_FLASH_LP_Write
+    #define R_FLASH_Erase   R_FLASH_LP_Erase
+    #define R_FLASH_StartUpAreaSelect   R_FLASH_LP_StartUpAreaSelect
+    /* BSP_FEATURE_FLASH */
+    #define FLASH_CF_WRITE_SIZE     BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE
+
+#endif
+
+int _flash_init(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    /* Open Flash_HP */
+    err = R_FLASH_Open(&g_flash_ctrl, &g_flash_cfg);
+    /* Handle Error */
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("\r\n Flah_HP_Open API failed");
+    }
+    /* Setup Default  Block 0 as Startup Setup Block */
+    err = R_FLASH_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
+    }
+    return 0;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int _flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result      = RT_EOK;
+    rt_base_t level;
+    fsp_err_t err = FSP_SUCCESS;
+    size_t written_size = 0;
+
+    if (size % FLASH_CF_WRITE_SIZE)
+    {
+        LOG_E("Flash Write size must be an integer multiple of %d", FLASH_CF_WRITE_SIZE);
+        return -RT_EINVAL;
+    }
+
+    while (written_size < size)
+    {
+        level = rt_hw_interrupt_disable();
+        R_FLASH_Reset(&g_flash_ctrl);
+        /* Write code flash data*/
+        err = R_FLASH_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, FLASH_CF_WRITE_SIZE);
+        rt_hw_interrupt_enable(level);
+
+        /* Error Handle */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Write API failed");
+            return -RT_EIO;
+        }
+
+        written_size += FLASH_CF_WRITE_SIZE;
+    }
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+#if BSP_FEATURE_FLASH_HP_VERSION
+    int _flash_hp0_erase(rt_uint32_t addr, size_t size)
+#else
+    int _flash_lp_erase(rt_uint32_t addr, size_t size)
+#endif
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+#if BSP_FEATURE_FLASH_HP_VERSION
+    if ((addr + size) > BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE)
+#else
+    if ((addr + size) > BSP_ROM_SIZE_BYTES)
+#endif
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    R_FLASH_Reset(&g_flash_ctrl);
+    /* Erase Block */
+#if BSP_FEATURE_FLASH_HP_VERSION
+    err = R_FLASH_Erase(&g_flash_ctrl,
+                        RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE),
+                        ((size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1));
+#else
+    err = R_FLASH_Erase(&g_flash_ctrl,
+                        RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE),
+                        ((size - 1) / BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE + 1));
+#endif
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase failed:addr (0x%p), size %d", (void *)addr, size);
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if BSP_FEATURE_FLASH_HP_VERSION
+int _flash_hp1_erase(rt_uint32_t addr, size_t size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    R_FLASH_Reset(&g_flash_ctrl);
+    /* Erase Block */
+    err = R_FLASH_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase API failed");
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+#endif
+
+#if defined(RT_USING_FAL)
+
+#define FLASH_START_ADDRESS     0x00000000
+
+#if BSP_FEATURE_FLASH_HP_VERSION
+
+static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_hp0_erase(long offset, size_t size);
+
+static int fal_flash_hp1_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_hp1_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_hp1_erase(long offset, size_t size);
+
+const struct fal_flash_dev _onchip_flash_hp0 =
+{
+    "onchip_flash_hp0",
+    FLASH_START_ADDRESS,
+    BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE,
+    BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE,
+    {
+        _flash_init,
+        fal_flash_hp0_read,
+        fal_flash_hp0_write,
+        fal_flash_hp0_erase
+    },
+    (BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE * 8)
+};
+const struct fal_flash_dev _onchip_flash_hp1 =
+{
+    "onchip_flash_hp1",
+    BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE,
+    (BSP_ROM_SIZE_BYTES - BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE),
+    BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE,
+    {
+        _flash_init,
+        fal_flash_hp1_read,
+        fal_flash_hp1_write,
+        fal_flash_hp1_erase
+    },
+    (BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE * 8)
+};
+
+/* code flash region0 */
+static int fal_flash_hp0_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_hp0.addr + offset, buf, size);
+}
+
+static int fal_flash_hp0_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_hp0.addr + offset, buf, size);
+}
+
+static int fal_flash_hp0_erase(long offset, size_t size)
+{
+    return _flash_hp0_erase(_onchip_flash_hp0.addr + offset, size);
+}
+/* code flash region1 */
+static int fal_flash_hp1_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_hp1.addr + offset, buf, size);
+}
+
+static int fal_flash_hp1_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_hp1.addr + offset, buf, size);
+}
+
+static int fal_flash_hp1_erase(long offset, size_t size)
+{
+    return _flash_hp1_erase(_onchip_flash_hp1.addr + offset, size);
+}
+
+#else /* flash lp code flash */
+
+static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_lp_erase(long offset, size_t size);
+
+const struct fal_flash_dev _onchip_flash_lp =
+{
+    "onchip_flash_lp",
+    FLASH_START_ADDRESS,
+    BSP_ROM_SIZE_BYTES,
+    BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE,
+    {
+        _flash_init,
+        fal_flash_lp_read,
+        fal_flash_lp_write,
+        fal_flash_lp_erase
+    },
+    (BSP_FEATURE_FLASH_LP_CF_WRITE_SIZE * 8)
+};
+
+static int fal_flash_lp_read(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_lp.addr + offset, buf, size);
+}
+
+static int fal_flash_lp_write(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_lp.addr + offset, buf, size);
+}
+
+static int fal_flash_lp_erase(long offset, size_t size)
+{
+    return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
+}
+
+#endif
+
+int flash_test(void)
+{
+#if BSP_FEATURE_FLASH_HP_VERSION
+#define TEST_OFF (_onchip_flash_hp1.len - BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
+#else
+#define TEST_OFF (_onchip_flash_lp.len - BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE)
+#endif
+    const struct fal_partition *param;
+    uint8_t write_buffer[FLASH_CF_WRITE_SIZE] = {0};
+    uint8_t read_buffer[FLASH_CF_WRITE_SIZE] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint8_t index = 0; index < FLASH_CF_WRITE_SIZE; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    fal_init();
+#if BSP_FEATURE_FLASH_HP_VERSION
+    param = fal_partition_find("param");
+#else
+    param = fal_partition_find("app");
+#endif
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition param!");
+        return -1;
+    }
+    LOG_I("Erase Start...");
+#if BSP_FEATURE_FLASH_HP_VERSION
+    fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE);
+#else
+    fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_LP_CF_BLOCK_SIZE);
+#endif
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST_OFF, read_buffer, FLASH_CF_WRITE_SIZE);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < FLASH_CF_WRITE_SIZE; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash_test, "drv flash test.");
+
+#endif

libraries/HAL_Drivers/drv_flash.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-30     flybreak     first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Code Flash */
+#define FLASH_HP_CF_BLOCK_SIZE_32KB       (32*1024)    /* Block Size 32 KB */
+#define FLASH_HP_CF_BLOCK_SIZE_8KB        (8*1024)     /* Block Size 8KB */
+
+#define FLASH_HP_CF_BLCOK_0               0x00000000U  /*    8 KB:  0x00000000 - 0x00001FFF */
+#define FLASH_HP_CF_BLOCK_1               0x00002000U  /*    8 KB:  0x00002000 - 0x00003FFF */
+#define FLASH_HP_CF_BLOCK_2               0x00004000U  /*    8 KB:  0x00004000 - 0x00005FFF */
+#define FLASH_HP_CF_BLOCK_3               0x00006000U  /*    8 KB:  0x00006000 - 0x00007FFF */
+#define FLASH_HP_CF_BLOCK_4               0x00008000U  /*    8 KB:  0x00008000 - 0x00009FFF */
+#define FLASH_HP_CF_BLOCK_5               0x0000A000U  /*    8 KB:  0x0000A000 - 0x0000BFFF */
+#define FLASH_HP_CF_BLOCK_6               0x0000C000U  /*    8 KB:  0x0000C000 - 0x0000DFFF */
+#define FLASH_HP_CF_BLOCK_7               0x0000E000U  /*    8 KB:  0x0000E000 - 0x0000FFFF */
+#define FLASH_HP_CF_BLOCK_8               0x00010000U  /*   32 KB: 0x00010000 - 0x00017FFF */
+#define FLASH_HP_CF_BLOCK_9               0x00018000U  /*   32 KB: 0x00018000 - 0x0001FFFF */
+#define FLASH_HP_CF_BLCOK_10              0x00020000U  /*   32 KB: 0x00020000 - 0x0004FFFF */
+
+#define FLASH_HP_DF_BLOCK_SIZE            (64)
+/* Data Flash */
+#if (defined (BOARD_RA6M4_EK) || defined (BOARD_RA6M5_EK) || defined (BOARD_RA4M3_EK)||defined(BOARD_RA4M2_EK))
+
+#define FLASH_HP_DF_BLOCK_0               0x08000000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x08000040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x08000080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x080000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#else
+
+#define FLASH_HP_DF_BLOCK_0               0x40100000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x40100040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x40100080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x401000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#endif
+
+#define BLOCK_SIZE                        (128)
+#define BLOCK_NUM                         (2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

libraries/HAL_Drivers/drv_gpio.c

@@ -0,0 +1,354 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date             Author              Notes
+ * 2021-07-29       KyleChan            first version
+ * 2022-01-19       Sherman             add PIN2IRQX_TABLE
+ */
+
+#include <drv_gpio.h>
+
+#ifdef RT_USING_PIN
+
+#define DBG_TAG              "drv.gpio"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#ifdef R_ICU_H
+#include "gpio_cfg.h"
+
+static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
+{
+    PIN2IRQX_TABLE(pin)
+}
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_IRQ_MAX] = {0};
+struct ra_pin_irq_map pin_irq_map[RA_IRQ_MAX] = {0};
+
+static void ra_irq_tab_init(void)
+{
+    for (int i = 0; i < RA_IRQ_MAX; ++i)
+    {
+        pin_irq_hdr_tab[i].pin  = -1;
+        pin_irq_hdr_tab[i].mode = 0;
+        pin_irq_hdr_tab[i].args = RT_NULL;
+        pin_irq_hdr_tab[i].hdr  = RT_NULL;
+    }
+}
+
+static void ra_pin_map_init(void)
+{
+#ifdef VECTOR_NUMBER_ICU_IRQ0
+    pin_irq_map[0].irq_ctrl = &g_external_irq0_ctrl;
+    pin_irq_map[0].irq_cfg = &g_external_irq0_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ1
+    pin_irq_map[1].irq_ctrl = &g_external_irq1_ctrl;
+    pin_irq_map[1].irq_cfg = &g_external_irq1_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ2
+    pin_irq_map[2].irq_ctrl = &g_external_irq2_ctrl;
+    pin_irq_map[2].irq_cfg = &g_external_irq2_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ3
+    pin_irq_map[3].irq_ctrl = &g_external_irq3_ctrl;
+    pin_irq_map[3].irq_cfg = &g_external_irq3_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ4
+    pin_irq_map[4].irq_ctrl = &g_external_irq4_ctrl;
+    pin_irq_map[4].irq_cfg = &g_external_irq4_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ5
+    pin_irq_map[5].irq_ctrl = &g_external_irq5_ctrl;
+    pin_irq_map[5].irq_cfg = &g_external_irq5_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ6
+    pin_irq_map[6].irq_ctrl = &g_external_irq6_ctrl;
+    pin_irq_map[6].irq_cfg = &g_external_irq6_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ7
+    pin_irq_map[7].irq_ctrl = &g_external_irq7_ctrl;
+    pin_irq_map[7].irq_cfg = &g_external_irq7_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ8
+    pin_irq_map[8].irq_ctrl = &g_external_irq8_ctrl;
+    pin_irq_map[8].irq_cfg = &g_external_irq8_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ9
+    pin_irq_map[9].irq_ctrl = &g_external_irq9_ctrl;
+    pin_irq_map[9].irq_cfg = &g_external_irq9_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ10
+    pin_irq_map[10].irq_ctrl = &g_external_irq10_ctrl;
+    pin_irq_map[10].irq_cfg = &g_external_irq10_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ11
+    pin_irq_map[11].irq_ctrl = &g_external_irq11_ctrl;
+    pin_irq_map[11].irq_cfg = &g_external_irq11_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ12
+    pin_irq_map[12].irq_ctrl = &g_external_irq12_ctrl;
+    pin_irq_map[12].irq_cfg = &g_external_irq12_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ13
+    pin_irq_map[13].irq_ctrl = &g_external_irq13_ctrl;
+    pin_irq_map[13].irq_cfg = &g_external_irq13_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ14
+    pin_irq_map[14].irq_ctrl = &g_external_irq14_ctrl;
+    pin_irq_map[14].irq_cfg = &g_external_irq14_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ15
+    pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
+    pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
+#endif
+}
+#endif  /* R_ICU_H */
+
+static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    fsp_err_t err;
+    /* Initialize the IOPORT module and configure the pins */
+    err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("GPIO open failed");
+        return;
+    }
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_INPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_INPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_OUTPUT_OD:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
+            return;
+        }
+        break;
+    }
+}
+
+static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
+
+    if (value != level)
+    {
+        level = BSP_IO_LEVEL_LOW;
+    }
+
+    R_BSP_PinAccessEnable();
+    R_BSP_PinWrite(pin, level);
+    R_BSP_PinAccessDisable();
+}
+
+static int ra_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
+    {
+        LOG_E("GPIO pin value is illegal");
+        return -RT_ERROR;
+    }
+    return R_BSP_PinRead(pin);
+}
+
+static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+#ifdef R_ICU_H
+    rt_err_t err;
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (PIN_IRQ_ENABLE == enabled)
+    {
+        if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+        {
+            err = R_ICU_ExternalIrqOpen((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl,
+                                        (external_irq_cfg_t const * const)pin_irq_map[irqx].irq_cfg);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Open failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqOpen API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+
+            err = R_ICU_ExternalIrqEnable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Enable failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqEnable API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+        }
+    }
+    else if (PIN_IRQ_DISABLE == enabled)
+    {
+        err = R_ICU_ExternalIrqDisable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Disable failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqDisable API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+        err = R_ICU_ExternalIrqClose((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Close failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqClose API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                  rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < (sizeof(pin_irq_map) / sizeof(pin_irq_map[0])))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == irqx &&
+                pin_irq_hdr_tab[irqx].hdr == hdr &&
+                pin_irq_hdr_tab[irqx].mode == mode &&
+                pin_irq_hdr_tab[irqx].args == args)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        if (pin_irq_hdr_tab[irqx].pin != -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EBUSY;
+        }
+        pin_irq_hdr_tab[irqx].pin = irqx;
+        pin_irq_hdr_tab[irqx].hdr = hdr;
+        pin_irq_hdr_tab[irqx].mode = mode;
+        pin_irq_hdr_tab[irqx].args = args;
+        rt_hw_interrupt_enable(level);
+    }
+    else return -RT_ERROR;
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        pin_irq_hdr_tab[irqx].pin = -1;
+        pin_irq_hdr_tab[irqx].hdr = RT_NULL;
+        pin_irq_hdr_tab[irqx].mode = 0;
+        pin_irq_hdr_tab[irqx].args = RT_NULL;
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_base_t ra_pin_get(const char *name)
+{
+    int pin_number = -1, port = -1, pin = -1;
+    if (rt_strlen(name) != 4)
+        return -1;
+    if ((name[0] == 'P') || (name[0] == 'p'))
+    {
+        if ('0' <= (int)name[1] && (int)name[1] <= '9')
+        {
+            port = ((int)name[1] - 48) * 16 * 16;
+            if ('0' <= (int)name[2] && (int)name[2] <= '9')
+            {
+                if ('0' <= (int)name[3] && (int)name[3] <= '9')
+                {
+                    pin = ((int)name[2] - 48) * 10;
+                    pin += (int)name[3] - 48;
+                    pin_number = port + pin;
+                }
+                else return -1;
+            }
+            else return -1;
+        }
+        else return -1;
+    }
+    return pin_number;
+}
+
+const static struct rt_pin_ops _ra_pin_ops =
+{
+    .pin_mode       = ra_pin_mode,
+    .pin_write      = ra_pin_write,
+    .pin_read       = ra_pin_read,
+    .pin_attach_irq = ra_pin_attach_irq,
+    .pin_detach_irq = ra_pin_dettach_irq,
+    .pin_irq_enable = ra_pin_irq_enable,
+    .pin_get        = ra_pin_get,
+};
+
+int rt_hw_pin_init(void)
+{
+#ifdef R_ICU_H
+    ra_irq_tab_init();
+    ra_pin_map_init();
+#endif
+    return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
+}
+
+#ifdef R_ICU_H
+void irq_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (p_args->channel == pin_irq_hdr_tab[p_args->channel].pin)
+    {
+        pin_irq_hdr_tab[p_args->channel].hdr(pin_irq_hdr_tab[p_args->channel].args);
+    }
+    rt_interrupt_leave();
+};
+#endif /* R_ICU_H */
+
+#endif /* RT_USING_PIN */

libraries/HAL_Drivers/drv_gpio.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <board.h>
+#include <rthw.h>
+#include <rtdbg.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_common.h>
+#include <hal_data.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_00
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_11_PIN_15
+
+#ifdef R_ICU_H
+struct ra_pin_irq_map
+{
+    const icu_instance_ctrl_t     *irq_ctrl;
+    const external_irq_cfg_t      *irq_cfg;
+};
+#endif
+
+int rt_hw_pin_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+

libraries/HAL_Drivers/drv_i2c.c

@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-02-22     airm2m       first version
+ */
+
+#include <rtdevice.h>
+#include <rtthread.h>
+#include "board.h"
+
+#include <stdlib.h>
+
+#ifdef BSP_USING_HW_I2C
+
+#define DBG_TAG              "drv.hwi2c"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+#include <hal_data.h>
+
+static struct rt_i2c_bus_device prv_ra_i2c;
+static volatile i2c_master_event_t i2c_event = I2C_MASTER_EVENT_ABORTED;
+
+void i2c_master_callback(i2c_master_callback_args_t *p_args)
+{
+    if (NULL != p_args)
+    {
+        /* capture callback event for validating the i2c transfer event*/
+        i2c_event = p_args->event;
+    }
+}
+
+static fsp_err_t validate_i2c_event(void)
+{
+    uint16_t local_time_out = UINT16_MAX;
+
+    /* resetting call back event capture variable */
+    i2c_event = (i2c_master_event_t)0;
+
+    do
+    {
+        /* This is to avoid infinite loop */
+        --local_time_out;
+
+        if(0 == local_time_out)
+        {
+            return FSP_ERR_TRANSFER_ABORTED;
+        }
+
+    }while(i2c_event == 0);
+
+    if(i2c_event != I2C_MASTER_EVENT_ABORTED)
+    {
+        /* Make sure this is always Reset before return*/
+        i2c_event = (i2c_master_event_t)0;
+        return FSP_SUCCESS;
+    }
+
+    /* Make sure this is always Reset before return */
+    i2c_event = (i2c_master_event_t)0;
+    return FSP_ERR_TRANSFER_ABORTED;
+}
+
+static rt_size_t ra_i2c_mst_xfer(struct rt_i2c_bus_device *bus,
+                                struct rt_i2c_msg msgs[],
+                                rt_uint32_t num)
+{
+    rt_size_t i;
+    struct rt_i2c_msg *msg = msgs;
+    RT_ASSERT(bus != RT_NULL);
+    fsp_err_t err     = FSP_SUCCESS;
+    bool restart = false;
+
+    for (i = 0; i < num; i++)
+    {
+        if (msg[i].flags & RT_I2C_NO_START)
+        {
+            restart = true;
+        }
+        if (msg[i].flags & RT_I2C_ADDR_10BIT)
+        {
+            LOG_E("10Bit not support");
+            break;
+        }
+        else
+        {
+            g_i2c_master1_ctrl.slave = msg[i].addr;
+        }
+
+        if (msg[i].flags & RT_I2C_RD)
+        {
+            err = R_IIC_MASTER_Read(&g_i2c_master1_ctrl, msg[i].buf, msg[i].len, restart);
+            if (FSP_SUCCESS == err)
+            {
+                err = validate_i2c_event();
+                /* handle error */
+                if(FSP_ERR_TRANSFER_ABORTED == err)
+                {
+                    LOG_E("POWER_CTL reg I2C read failed");
+                    break;
+                }
+            }
+            /* handle error */
+            else
+            {
+                /* Write API returns itself is not successful */
+                LOG_E("R_IIC_MASTER_Write API failed");
+                break;
+            }
+        }
+        else
+        {
+            err = R_IIC_MASTER_Write(&g_i2c_master1_ctrl, msg[i].buf, msg[i].len, restart);
+            if (FSP_SUCCESS == err)
+            {
+                err = validate_i2c_event();
+                /* handle error */
+                if(FSP_ERR_TRANSFER_ABORTED == err)
+                {
+                    LOG_E("POWER_CTL reg I2C write failed");
+                    break;
+                }
+            }
+            /* handle error */
+            else
+            {
+                /* Write API returns itself is not successful */
+                LOG_E("R_IIC_MASTER_Write API failed");
+                break;
+            }
+        }
+    }
+    return i;
+}
+
+static const struct rt_i2c_bus_device_ops ra_i2c_ops =
+{
+    .master_xfer        = ra_i2c_mst_xfer,
+    .slave_xfer         = RT_NULL,
+    .i2c_bus_control    = RT_NULL
+};
+
+int ra_hw_i2c_init(void)
+{
+    fsp_err_t err     = FSP_SUCCESS;
+    prv_ra_i2c.ops = &ra_i2c_ops;
+    prv_ra_i2c.priv = 0;
+    /* opening IIC master module */
+    err = R_IIC_MASTER_Open(&g_i2c_master1_ctrl, &g_i2c_master1_cfg);
+    /* handle error */
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("R_IIC_MASTER_Open API failed");
+        return err;
+    }
+    rt_i2c_bus_device_register(&prv_ra_i2c, "i2c1");
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(ra_hw_i2c_init);
+
+#endif /* BSP_USING_I2C */

libraries/HAL_Drivers/drv_pwm.c

@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-25     KevinXu      first version
+ */
+
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+
+/* Declare the control function first */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
+static struct rt_pwm_ops drv_ops =
+{
+    drv_pwm_control
+};
+
+static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
+{
+#ifdef BSP_USING_PWM0
+    [BSP_PWM0_INDEX] = PWM_DRV_INITIALIZER(0),
+#endif
+#ifdef BSP_USING_PWM1
+    [BSP_PWM1_INDEX] = PWM_DRV_INITIALIZER(1),
+#endif
+#ifdef BSP_USING_PWM2
+    [BSP_PWM2_INDEX] = PWM_DRV_INITIALIZER(2),
+#endif
+#ifdef BSP_USING_PWM3
+    [BSP_PWM3_INDEX] = PWM_DRV_INITIALIZER(3),
+#endif
+#ifdef BSP_USING_PWM4
+    [BSP_PWM4_INDEX] = PWM_DRV_INITIALIZER(4),
+#endif
+#ifdef BSP_USING_PWM5
+    [BSP_PWM5_INDEX] = PWM_DRV_INITIALIZER(5),
+#endif
+#ifdef BSP_USING_PWM6
+    [BSP_PWM6_INDEX] = PWM_DRV_INITIALIZER(6),
+#endif
+#ifdef BSP_USING_PWM7
+    [BSP_PWM7_INDEX] = PWM_DRV_INITIALIZER(7),
+#endif
+#ifdef BSP_USING_PWM8
+    [BSP_PWM8_INDEX] = PWM_DRV_INITIALIZER(8),
+#endif
+#ifdef BSP_USING_PWM9
+    [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
+#endif
+};
+
+
+/* Convert the raw PWM period counts into ns */
+static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
+    return ns;
+}
+
+/* Convert ns into raw PWM period counts */
+static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
+    return counts;
+}
+
+
+/* PWM_CMD_ENABLE or PWM_CMD_DISABLE */
+static rt_err_t drv_pwm_enable(struct ra_pwm *device,
+                               struct rt_pwm_configuration *configuration,
+                               rt_bool_t enable)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    if (enable)
+    {
+        err = R_GPT_Start(device->g_ctrl);
+    }
+    else
+    {
+        err = R_GPT_Stop(device->g_ctrl);
+    }
+
+    return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
+}
+
+/* PWM_CMD_GET */
+static rt_err_t drv_pwm_get(struct ra_pwm *device,
+                            struct rt_pwm_configuration *configuration)
+{
+    timer_info_t info;
+    if (R_GPT_InfoGet(device->g_ctrl, &info) != FSP_SUCCESS)
+        return -RT_ERROR;
+
+    configuration->pulse =
+        _convert_counts_ns(device->g_cfg->source_div, device->g_cfg->duty_cycle_counts);
+    configuration->period =
+        _convert_counts_ns(device->g_cfg->source_div, info.period_counts);
+    configuration->channel = device->g_cfg->channel;
+
+    return RT_EOK;
+}
+
+/* PWM_CMD_SET */
+static rt_err_t drv_pwm_set(struct ra_pwm *device,
+                            struct rt_pwm_configuration *conf)
+{
+    uint32_t counts;
+    fsp_err_t fsp_erra;
+    fsp_err_t fsp_errb;
+    rt_err_t rt_err;
+    uint32_t pulse;
+    uint32_t period;
+    struct rt_pwm_configuration orig_conf;
+
+    rt_err = drv_pwm_get(device, &orig_conf);
+    if (rt_err != RT_EOK)
+    {
+        return rt_err;
+    }
+
+    /* Pulse cannot last longer than period. */
+    period = conf->period;
+    pulse = (period >= conf->pulse) ? conf->pulse : period;
+
+    /* Not to set period again if it's not changed. */
+    if (period != orig_conf.period)
+    {
+        counts = _convert_ns_counts(device->g_cfg->source_div, period);
+        fsp_erra = R_GPT_PeriodSet(device->g_ctrl, counts);
+        if (fsp_erra != FSP_SUCCESS)
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    /* Two pins of a channel will not be separated. */
+    counts = _convert_ns_counts(device->g_cfg->source_div, pulse);
+    fsp_erra = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCA);
+    fsp_errb = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCB);
+    if (fsp_erra != FSP_SUCCESS || fsp_errb != FSP_SUCCESS)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * Implement of control method in struct rt_pwm_ops.
+ */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    struct ra_pwm *pwm_device = (struct ra_pwm *)device->parent.user_data;
+
+    /**
+     * There's actually only one GPT timer with 10 channels. In this case, the
+     * timer is separated into 10 PWM devices, so each device has only one
+     * channel.
+     */
+    if (configuration->channel != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_FALSE);
+    case PWM_CMD_GET:
+        return drv_pwm_get(pwm_device, configuration);
+    case PWM_CMD_SET:
+        return drv_pwm_set(pwm_device, configuration);
+    default:
+        return -RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * This is to register the PWM device
+ *
+ * Note that the PWM driver only supports one fixed pin.
+ */
+int rt_hw_pwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    rt_err_t rt_err = RT_EOK;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    for (int i = 0; i < BSP_PWMS_NUM; i++)
+    {
+        fsp_err = R_GPT_Open(ra6m4_pwm_obj[i].g_ctrl,
+                             ra6m4_pwm_obj[i].g_cfg);
+
+        rt_err = rt_device_pwm_register(&ra6m4_pwm_obj[i].pwm_device,
+                                        ra6m4_pwm_obj[i].name,
+                                        &drv_ops,
+                                        &ra6m4_pwm_obj[i]);
+
+        if (fsp_err != FSP_SUCCESS || rt_err != RT_EOK)
+        {
+            ret = -RT_ERROR;
+        }
+    }
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
+#endif /* RT_USING_PWM */

libraries/HAL_Drivers/drv_pwm.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-25     KevinXu      first version
+ */
+
+#ifndef __DRV_PWM_H__
+#define __DRV_PWM_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+/* PWM device object structure */
+struct ra_pwm
+{
+    struct rt_device_pwm            pwm_device;
+    gpt_instance_ctrl_t             *g_ctrl;
+    timer_instance_t const *const   g_timer;
+    timer_cfg_t const *const        g_cfg;
+    char                            *name;
+};
+
+/* Get ra6m4 pwm device object from the general pwm device object */
+#define _GET_RA6M4_PWM_OBJ(ptr) rt_container_of(ptr, struct ra_pwm, pwm_device)
+
+#endif /* __DRV_PWM_H__ */

libraries/HAL_Drivers/drv_rtc.c

@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-14     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include <sys/time.h>
+#include "hal_data.h"
+
+#ifdef BSP_USING_ONCHIP_RTC
+
+#define DBG_TAG              "drv.rtc"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static rt_err_t ra_rtc_init(void)
+{
+    rt_err_t result = RT_EOK;
+
+    if (R_RTC_Open(&g_rtc_ctrl, &g_rtc_cfg) != RT_EOK)
+    {
+        LOG_E("rtc init failed.");
+        result = -RT_ERROR;
+    }
+
+    return result;
+}
+
+static time_t get_rtc_timestamp(void)
+{
+    struct tm tm_new = {0};
+    rtc_time_t g_current_time = {0};
+
+    R_RTC_CalendarTimeGet(&g_rtc_ctrl, &g_current_time);
+
+    tm_new.tm_year  = g_current_time.tm_year;
+    tm_new.tm_mon   = g_current_time.tm_mon;
+    tm_new.tm_mday  = g_current_time.tm_mday;
+
+    tm_new.tm_hour  = g_current_time.tm_hour;
+    tm_new.tm_min   = g_current_time.tm_min;
+    tm_new.tm_sec   = g_current_time.tm_sec;
+
+    tm_new.tm_wday  = g_current_time.tm_wday;
+    tm_new.tm_yday  = g_current_time.tm_yday;
+    tm_new.tm_isdst = g_current_time.tm_isdst;
+
+    return timegm(&tm_new);
+}
+
+static rt_err_t ra_get_secs(void *args)
+{
+    *(rt_uint32_t *)args = get_rtc_timestamp();
+    LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return RT_EOK;
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+    struct tm now;
+    rtc_time_t g_current_time = {0};
+    gmtime_r(&time_stamp, &now);
+    if (now.tm_year < 100)
+    {
+        return -RT_ERROR;
+    }
+
+    g_current_time.tm_sec    = now.tm_sec ;
+    g_current_time.tm_min    = now.tm_min ;
+    g_current_time.tm_hour   = now.tm_hour;
+    g_current_time.tm_mday   = now.tm_mday;
+    g_current_time.tm_mon    = now.tm_mon;
+    g_current_time.tm_year   = now.tm_year;
+    g_current_time.tm_wday   = now.tm_wday;
+    g_current_time.tm_yday   = now.tm_yday;
+
+    if (R_RTC_CalendarTimeSet(&g_rtc_ctrl, &g_current_time) != FSP_SUCCESS)
+    {
+        LOG_E("set rtc time failed.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ra_set_secs(void *args)
+{
+
+    rt_err_t result = RT_EOK;
+
+    if (set_rtc_time_stamp(*(rt_uint32_t *)args))
+    {
+        result = -RT_ERROR;
+    }
+    LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
+
+    return result;
+}
+
+#ifdef RT_USING_ALARM
+static rt_err_t ra_get_alarm(void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    rtc_alarm_time_t alarm_time_get =
+    {
+        .sec_match        =  RT_FALSE,
+        .min_match        =  RT_FALSE,
+        .hour_match       =  RT_FALSE,
+        .mday_match       =  RT_FALSE,
+        .mon_match        =  RT_FALSE,
+        .year_match       =  RT_FALSE,
+        .dayofweek_match  =  RT_FALSE,
+    };
+
+    if (RT_EOK == R_RTC_CalendarAlarmGet(&g_rtc_ctrl, &alarm_time_get))
+    {
+        wkalarm->tm_hour = alarm_time_get.time.tm_hour;
+        wkalarm->tm_min  = alarm_time_get.time.tm_min;
+        wkalarm->tm_sec  = alarm_time_get.time.tm_sec;
+    }
+    else
+    {
+        LOG_E("Calendar alarm Get failed.");
+    }
+
+    return result;
+}
+
+static rt_err_t ra_set_alarm(void *arg)
+{
+    rt_err_t result = RT_EOK;
+    struct rt_rtc_wkalarm *wkalarm = (struct rt_rtc_wkalarm *)arg;
+    rtc_alarm_time_t alarm_time_set =
+    {
+        .sec_match        =  RT_TRUE,
+        .min_match        =  RT_TRUE,
+        .hour_match       =  RT_TRUE,
+        .mday_match       =  RT_FALSE,
+        .mon_match        =  RT_FALSE,
+        .year_match       =  RT_FALSE,
+        .dayofweek_match  =  RT_FALSE,
+    };
+
+    alarm_time_set.time.tm_hour = wkalarm->tm_hour;
+    alarm_time_set.time.tm_min  = wkalarm->tm_min;
+    alarm_time_set.time.tm_sec  = wkalarm->tm_sec;
+    if (1 == wkalarm->enable)
+    {
+        if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
+        {
+            LOG_E("Calendar alarm Set failed.");
+            result = -RT_ERROR;
+        }
+    }
+    else
+    {
+        alarm_time_set.sec_match        =  RT_FALSE;
+        alarm_time_set.min_match        =  RT_FALSE;
+        alarm_time_set.hour_match       =  RT_FALSE;
+        if (RT_EOK != R_RTC_CalendarAlarmSet(&g_rtc_ctrl, &alarm_time_set))
+        {
+            LOG_E("Calendar alarm Stop failed.");
+            result = -RT_ERROR;
+        }
+    }
+    return result;
+}
+#endif /* RT_USING_ALARM */
+
+void rtc_callback(rtc_callback_args_t *p_args)
+{
+#ifdef RT_USING_ALARM
+    static rt_device_t ra_device;
+    if (RTC_EVENT_ALARM_IRQ == p_args->event)
+    {
+        rt_alarm_update(ra_device, 1);
+    }
+#endif
+}
+
+static const struct rt_rtc_ops ra_rtc_ops =
+{
+    .init      = ra_rtc_init,
+    .get_secs  = ra_get_secs,
+    .set_secs  = ra_set_secs,
+#ifdef RT_USING_ALARM
+    .set_alarm = ra_set_alarm,
+    .get_alarm = ra_get_alarm,
+#endif
+};
+
+static rt_rtc_dev_t ra_rtc_dev;
+
+static int rt_hw_rtc_init(void)
+{
+    rt_err_t result;
+
+    ra_rtc_dev.ops = &ra_rtc_ops;
+
+    result = rt_hw_rtc_register(&ra_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL);
+    if (result != RT_EOK)
+    {
+        LOG_E("rtc register err code: %d", result);
+        return result;
+    }
+    LOG_D("rtc init success");
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif

libraries/HAL_Drivers/drv_sdhi.c

@@ -0,0 +1,510 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-03     mazhiyuan    first version
+ */
+
+#include <drv_sdhi.h>
+struct ra_sdhi sdhi;
+
+#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&_sdio->mutex, RT_WAITING_FOREVER)
+#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&_sdio->mutex);
+
+struct rthw_sdio
+{
+    struct rt_mmcsd_host *host;
+    struct ra_sdhi sdhi_des;
+    struct rt_event event;
+    struct rt_mutex mutex;
+};
+
+static struct rt_mmcsd_host *host;
+
+ALIGN(SDIO_ALIGN_LEN)
+static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
+
+rt_err_t command_send(sdhi_instance_ctrl_t *p_ctrl, struct rt_mmcsd_cmd *cmd)
+{
+    uint32_t wait_bit;
+    uint32_t timeout = BUSY_TIMEOUT_US;
+    volatile sdhi_event_t event;
+    struct rt_mmcsd_data *data = cmd->data;
+    while (SD_INFO2_CBSY_SDD0MON_IDLE_VAL !=
+            (p_ctrl->p_reg->SD_INFO2 & SD_INFO2_CBSY_SDD0MON_IDLE_MASK))
+    {
+        if (timeout == 0)
+        {
+            return RT_ETIMEOUT;
+        }
+        R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS);
+        timeout--;
+    }
+    p_ctrl->p_reg->SD_INFO1 = 0U;
+    p_ctrl->p_reg->SD_INFO2 = 0U;
+    p_ctrl->sdhi_event.word = 0U;
+
+    /* Enable response end interrupt. */
+    /* Disable access end interrupt and enable response end interrupt. */
+    uint32_t mask = p_ctrl->p_reg->SD_INFO1_MASK;
+    mask &= (~SDHI_INFO1_RESPONSE_END);
+    mask |= SDHI_INFO1_ACCESS_END;
+    p_ctrl->p_reg->SD_INFO1_MASK = mask;
+    p_ctrl->p_reg->SD_INFO2_MASK = SDHI_INFO2_MASK_CMD_SEND;
+    /* Write argument, then command to the SDHI peripheral. */
+    p_ctrl->p_reg->SD_ARG = cmd->arg & UINT16_MAX;
+    p_ctrl->p_reg->SD_ARG1 = cmd->arg >> 16;
+
+    if ((cmd->flags & CMD_MASK) == CMD_ADTC)
+    {
+        cmd->cmd_code |= SDHI_CMD_ADTC_EN;
+        switch (cmd->flags & RESP_MASK)
+        {
+        case RESP_R1:
+        case RESP_R5:
+        case RESP_R6:
+        case RESP_R7:
+            cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R1_R5_R6_R7;
+            break;
+        case RESP_R1B:
+            cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R1B;
+            break;
+        case RESP_R2:
+            cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R2;
+            break;
+        case RESP_R3:
+        case RESP_R4:
+            cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_R3_R4;
+            break;
+        case RESP_NONE:
+            cmd->cmd_code |= SDHI_CMD_RESP_TYPE_EXT_NONE;
+            break;
+        }
+        if (data != RT_NULL)
+        {
+            if ((data->flags & 7) == DATA_DIR_WRITE)
+            {
+                cmd->cmd_code &= ~SDHI_CMD_DATA_DIR_READ;
+            }
+            else if ((data->flags & 7) == DATA_DIR_READ)
+            {
+                cmd->cmd_code |= SDHI_CMD_DATA_DIR_READ;
+            }
+        }
+    }
+    p_ctrl->p_reg->SD_CMD = cmd->cmd_code;
+
+    timeout = 100000;
+    while (true)
+    {
+        /* Check for updates to the event status. */
+        event.word = p_ctrl->sdhi_event.word;
+
+        /* Return an error if a hardware error occurred. */
+        if (event.bit.event_error)
+        {
+            cmd->err = -RT_ERROR;
+            if ((event.word & HW_SDHI_ERR_CRCE) && (resp_type(cmd) & (RESP_R3 | RESP_R4)))
+            {
+                if ((cmd->flags & RESP_MASK) == RESP_R2)
+                {
+                    cmd->resp[0] = (p_ctrl->p_reg->SD_RSP76 << 8) | (p_ctrl->p_reg->SD_RSP54 >> 24);
+                    cmd->resp[1] = (p_ctrl->p_reg->SD_RSP54 << 8) | (p_ctrl->p_reg->SD_RSP32 >> 24);
+                    cmd->resp[2] = (p_ctrl->p_reg->SD_RSP32 << 8) | (p_ctrl->p_reg->SD_RSP10 >> 24);
+                    cmd->resp[3] = (p_ctrl->p_reg->SD_RSP10 << 8);
+                }
+                else
+                {
+                    cmd->resp[0] = p_ctrl->p_reg->SD_RSP10;
+                }
+                cmd->err = RT_EOK;
+            }
+            if (event.word & HW_SDHI_ERR_RTIMEOUT)
+            {
+                cmd->err = -RT_ETIMEOUT;
+            }
+            if (event.word & HW_SDHI_ERR_DTIMEOUT)
+            {
+                data->err = -RT_ETIMEOUT;
+            }
+            return -RT_ERROR;
+        }
+        if (data != RT_NULL)
+        {
+            wait_bit = SDHI_WAIT_ACCESS_BIT;
+        }
+        else
+        {
+            wait_bit = SDHI_WAIT_RESPONSE_BIT;
+        }
+
+        /* If the requested bit is set, return success. */
+        if (event.word & (1U << wait_bit))
+        {
+            cmd->err = RT_EOK;
+            if ((cmd->flags & RESP_MASK) == RESP_R2)
+            {
+                cmd->resp[0] = (p_ctrl->p_reg->SD_RSP76 << 8) | (p_ctrl->p_reg->SD_RSP54 >> 24);
+                cmd->resp[1] = (p_ctrl->p_reg->SD_RSP54 << 8) | (p_ctrl->p_reg->SD_RSP32 >> 24);
+                cmd->resp[2] = (p_ctrl->p_reg->SD_RSP32 << 8) | (p_ctrl->p_reg->SD_RSP10 >> 24);
+                cmd->resp[3] = (p_ctrl->p_reg->SD_RSP10 << 8);
+            }
+            else
+            {
+                cmd->resp[0] = p_ctrl->p_reg->SD_RSP10;
+            }
+
+            return RT_EOK;
+        }
+
+        /* Check for timeout. */
+        timeout--;
+        if (0U == timeout)
+        {
+            cmd->err = -RT_ETIMEOUT;
+            return RT_ERROR;
+        }
+
+        /* Wait 1 us for consistent loop timing. */
+        R_BSP_SoftwareDelay(1U, BSP_DELAY_UNITS_MICROSECONDS);
+    }
+}
+
+rt_err_t transfer_write(sdhi_instance_ctrl_t *const p_ctrl,
+                        uint32_t block_count,
+                        uint32_t bytes,
+                        const uint8_t *p_data)
+{
+    transfer_info_t *p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info;
+
+    /* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */
+    p_ctrl->p_reg->SD_INFO2_MASK |= 0x300U;
+    p_ctrl->p_reg->SD_DMAEN = 0x2U;
+
+    uint32_t transfer_settings = (uint32_t)TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS;
+    transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS;
+    transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS;
+
+#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE
+    if ((0U != ((uint32_t)p_data & 0x3U)) || (0U != (bytes & 3U)))
+    {
+        transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS;
+        transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS;
+
+        /* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer.
+         * Transfer the first block to the temporary buffer before enabling the transfer.  Subsequent blocks will be
+         * transferred from the user buffer to the temporary buffer in an interrupt after each block transfer. */
+        rt_memcpy((void *)&p_ctrl->aligned_buff[0], p_data, bytes);
+        p_info->p_src = &p_ctrl->aligned_buff[0];
+
+        p_ctrl->transfer_block_current = 1U;
+        p_ctrl->transfer_blocks_total = block_count;
+        p_ctrl->p_transfer_data = (uint8_t *)&p_data[bytes];
+        p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_WRITE;
+        p_ctrl->transfer_block_size = bytes;
+    }
+    else
+#endif
+    {
+        p_info->p_src = p_data;
+    }
+
+    p_info->transfer_settings_word = transfer_settings;
+    p_info->p_dest = (uint32_t *)(&p_ctrl->p_reg->SD_BUF0);
+    p_info->num_blocks = (uint16_t)block_count;
+
+    /* Round up to the nearest multiple of 4 bytes for the transfer. */
+    uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t);
+    p_info->length = (uint16_t)words;
+    /* Configure the transfer driver to write to the SD buffer. */
+    fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl,
+                    p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info);
+    if (FSP_SUCCESS != err)
+        return RT_ERROR;
+    return RT_EOK;
+}
+
+rt_err_t transfer_read(sdhi_instance_ctrl_t *const p_ctrl,
+                       uint32_t block_count,
+                       uint32_t bytes,
+                       void *p_data)
+{
+    transfer_info_t *p_info = p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info;
+
+    /* When the SD_DMAEN.DMAEN bit is 1, set the SD_INFO2_MASK.BWEM bit to 1 and the SD_INFO2_MASK.BREM bit to 1. */
+    p_ctrl->p_reg->SD_INFO2_MASK |= 0X300U;
+    p_ctrl->p_reg->SD_DMAEN = 0x2U;
+
+    uint32_t transfer_settings = (uint32_t)TRANSFER_MODE_BLOCK << TRANSFER_SETTINGS_MODE_BITS;
+    transfer_settings |= TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS;
+    transfer_settings |= TRANSFER_SIZE_4_BYTE << TRANSFER_SETTINGS_SIZE_BITS;
+
+#if SDMMC_CFG_UNALIGNED_ACCESS_ENABLE
+
+    /* If the pointer is not 4-byte aligned or the number of bytes is not a multiple of 4, use a temporary buffer.
+     * Data will be transferred from the temporary buffer into the user buffer in an interrupt after each block transfer. */
+    if ((0U != ((uint32_t)p_data & 0x3U)) || (0U != (bytes & 3U)))
+    {
+        transfer_settings |= TRANSFER_IRQ_EACH << TRANSFER_SETTINGS_IRQ_BITS;
+        p_info->p_dest = &p_ctrl->aligned_buff[0];
+
+        p_ctrl->transfer_block_current = 0U;
+        p_ctrl->transfer_blocks_total = block_count;
+        p_ctrl->p_transfer_data = (uint8_t *)p_data;
+        p_ctrl->transfer_dir = SDHI_TRANSFER_DIR_READ;
+        p_ctrl->transfer_block_size = bytes;
+    }
+    else
+#endif
+    {
+        transfer_settings |= TRANSFER_REPEAT_AREA_SOURCE << TRANSFER_SETTINGS_REPEAT_AREA_BITS;
+        p_info->p_dest = p_data;
+    }
+
+    p_info->transfer_settings_word = transfer_settings;
+    p_info->p_src = (uint32_t *)(&p_ctrl->p_reg->SD_BUF0);
+    p_info->num_blocks = (uint16_t)block_count;
+
+    /* Round up to the nearest multiple of 4 bytes for the transfer. */
+    uint32_t words = (bytes + (sizeof(uint32_t) - 1U)) / sizeof(uint32_t);
+    p_info->length = (uint16_t)words;
+
+    /* Configure the transfer driver to read from the SD buffer. */
+    fsp_err_t err = p_ctrl->p_cfg->p_lower_lvl_transfer->p_api->reconfigure(p_ctrl->p_cfg->p_lower_lvl_transfer->p_ctrl,
+                    p_ctrl->p_cfg->p_lower_lvl_transfer->p_cfg->p_info);
+    if (err != FSP_SUCCESS)
+        return RT_ERROR;
+
+    return RT_EOK;
+}
+
+void ra_sdhi_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    struct rt_mmcsd_data *data;
+    static rt_uint8_t *buffer;
+
+    RTHW_SDIO_LOCK(sdio);
+
+    if (req->cmd != RT_NULL)
+    {
+        data = req->cmd->data;
+        if (data != RT_NULL)
+        {
+            rt_uint32_t size = data->blks * data->blksize;
+
+            RT_ASSERT(size <= SDIO_BUFF_SIZE);
+
+            buffer = (rt_uint8_t *)data->buf;
+            if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
+            {
+                buffer = cache_buf;
+                if (data->flags & DATA_DIR_WRITE)
+                {
+                    rt_memcpy(cache_buf, data->buf, size);
+                }
+            }
+            if (data->flags & DATA_DIR_WRITE)
+            {
+                transfer_write(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer);
+            }
+            else if (data->flags & DATA_DIR_READ)
+            {
+                transfer_read(sdio->sdhi_des.instance->p_ctrl, data->blks, data->blksize, buffer);
+            }
+            /* Set the sector count. */
+            if (data->blks > 1U)
+            {
+                ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_STOP = 0x100U;
+                ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_SECCNT = data->blks;
+            }
+            else
+            {
+                ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_STOP = 0U;
+            }
+            ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_SIZE = data->blksize;
+        }
+        rt_enter_critical();
+        command_send(sdio->sdhi_des.instance->p_ctrl, req->cmd);
+        rt_exit_critical();
+        if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
+        {
+            rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
+        }
+    }
+
+    if (req->stop != RT_NULL)
+    {
+        rt_enter_critical();
+        command_send(sdio->sdhi_des.instance->p_ctrl, req->stop);
+        rt_exit_critical();
+    }
+    RTHW_SDIO_UNLOCK(sdio);
+    mmcsd_req_complete(sdio->host);
+}
+
+static rt_err_t clock_rate_set(sdhi_instance_ctrl_t *p_ctrl, uint32_t max_rate)
+{
+    uint32_t setting = 0xFFU;
+
+    /* Get the runtime frequency of the source of the SD clock */
+    uint32_t frequency = R_FSP_SystemClockHzGet(BSP_FEATURE_SDHI_CLOCK);
+
+    /* Iterate over all possible divisors, starting with the smallest, until the resulting clock rate is less than
+     * or equal to the requested maximum rate. */
+    for (uint32_t divisor_shift = BSP_FEATURE_SDHI_MIN_CLOCK_DIVISION_SHIFT;
+            divisor_shift <= 9U;
+            divisor_shift++)
+    {
+        if ((frequency >> divisor_shift) <= max_rate)
+        {
+            /* If the calculated frequency is less than or equal to the maximum supported by the device,
+             * select this frequency. The register setting is the divisor value divided by 4, or 0xFF for no divider. */
+            setting = divisor_shift ? ((1U << divisor_shift) >> 2U) : UINT8_MAX;
+
+            /* Set the clock setting. */
+
+            /* The clock register is accessible 8 SD clock counts after the last command completes.  Each register access
+             * requires at least one PCLK count, so check the register up to 8 times the maximum PCLK divisor value (512). */
+            uint32_t timeout = 8U * 512U;
+
+            while (timeout > 0U)
+            {
+                /* Do not write to clock control register until this bit is set. */
+                if (p_ctrl->p_reg->SD_INFO2_b.SD_CLK_CTRLEN)
+                {
+                    /* Set the calculated divider and enable clock output to start the 74 clocks required before
+                     * initialization. Do not change the automatic clock control setting. */
+                    uint32_t clkctrlen = p_ctrl->p_reg->SD_CLK_CTRL & (1U << 9);
+                    p_ctrl->p_reg->SD_CLK_CTRL = setting | clkctrlen | (1U << 8);
+                    p_ctrl->device.clock_rate = frequency >> divisor_shift;
+
+                    return RT_EOK;
+                }
+
+                timeout--;
+            }
+
+            /* Valid setting already found, stop looking. */
+            break;
+        }
+    }
+
+    return RT_ERROR;
+}
+
+void ra_sdhi_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    RTHW_SDIO_LOCK(sdio);
+    if (io_cfg->bus_width == MMCSD_BUS_WIDTH_1)
+    {
+        ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 1;
+    }
+    else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
+    {
+        ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 0;
+        ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH8 = 0;
+    }
+    else if (io_cfg->bus_width == MMCSD_BUS_WIDTH_8)
+    {
+        ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH = 0;
+        ((sdhi_instance_ctrl_t *)sdio->sdhi_des.instance->p_ctrl)->p_reg->SD_OPTION_b.WIDTH8 = 1;
+    }
+    clock_rate_set(sdio->sdhi_des.instance->p_ctrl, io_cfg->clock);
+    RTHW_SDIO_UNLOCK(sdio);
+}
+
+rt_int32_t ra_sdhi_get_card_status(struct rt_mmcsd_host *host)
+{
+    sdmmc_status_t status;
+    struct rthw_sdio *sdio = host->private_data;
+    sdio->sdhi_des.instance->p_api->statusGet(sdio->sdhi_des.instance->p_ctrl, &status);
+    return status.card_inserted;
+}
+
+void ra_sdhi_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t en)
+{
+    struct rthw_sdio *sdio = host->private_data;
+    sdio->sdhi_des.instance->p_api->ioIntEnable(sdio->sdhi_des.instance->p_ctrl, en);
+}
+
+struct rt_mmcsd_host_ops ra_sdhi_ops =
+{
+    .request = ra_sdhi_request,
+    .set_iocfg = ra_sdhi_set_iocfg,
+    .get_card_status = ra_sdhi_get_card_status,
+    .enable_sdio_irq = ra_sdhi_enable_sdio_irq
+};
+
+void sdhi_callback(sdmmc_callback_args_t *p_args)
+{
+}
+
+struct rt_mmcsd_host *sdio_host_create(struct ra_sdhi *sdhi_des)
+{
+    struct rt_mmcsd_host *host;
+    struct rthw_sdio *sdio = RT_NULL;
+
+    if (sdhi_des == RT_NULL)
+        return RT_NULL;
+
+    sdio = rt_malloc(sizeof(struct rthw_sdio));
+    if (sdio == RT_NULL)
+        return RT_NULL;
+    rt_memset(sdio, 0, sizeof(struct rthw_sdio));
+
+    host = mmcsd_alloc_host();
+    if (host == RT_NULL)
+    {
+        rt_free(sdio);
+        return RT_NULL;
+    }
+
+    rt_memcpy(&sdio->sdhi_des, sdhi_des, sizeof(struct ra_sdhi));
+
+    rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
+    rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
+
+    /* set host defautl attributes */
+    host->ops = &ra_sdhi_ops;
+    host->freq_min = 400 * 1000;
+    host->freq_max = SDIO_MAX_FREQ;
+    host->valid_ocr = 0X00FFFF80; /* The voltage range supported is 1.65v-3.6v */
+#ifndef SDHI_USING_1_BIT
+    host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
+#else
+    host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
+#endif
+    host->max_seg_size = SDIO_BUFF_SIZE;
+    host->max_dma_segs = 1;
+    host->max_blk_size = 512;
+    host->max_blk_count = 512;
+
+    /* link up host and sdio */
+    sdio->host = host;
+    host->private_data = sdio;
+
+    ra_sdhi_enable_sdio_irq(host, 1);
+
+    /* ready to change */
+    mmcsd_change(host);
+
+    return host;
+}
+
+int rt_hw_sdhi_init(void)
+{
+    sdhi.instance = &g_sdmmc0;
+    sdhi.instance->p_api->open(sdhi.instance->p_ctrl, sdhi.instance->p_cfg);
+    host = sdio_host_create(&sdhi);
+    if (host == RT_NULL)
+    {
+        return -1;
+    }
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_sdhi_init);

libraries/HAL_Drivers/drv_sdhi.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-03     mazhiyuan    first version
+ */
+
+#ifndef __DRV_SDHI_H__
+#define __DRV_SDHI_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+#ifndef SDIO_BUFF_SIZE
+    #define SDIO_BUFF_SIZE 4096
+#endif
+
+#ifndef SDIO_ALIGN_LEN
+    #define SDIO_ALIGN_LEN (32)
+#endif
+
+#define SD_INFO2_CBSY_SDD0MON_IDLE_VAL 0x80
+#define SD_INFO2_CBSY_SDD0MON_IDLE_MASK 0x4080
+#define BUSY_TIMEOUT_US 5000000
+
+#define SDHI_INFO1_RESPONSE_END 1
+#define SDHI_INFO1_ACCESS_END (1 << 2)
+#define SDHI_INFO2_MASK_CMD_SEND 0x00007C80U
+#define SDHI_INFO2_BRE (1 << 8)
+#define SDHI_INFO2_BWE (1 << 9)
+
+#define SDHI_CMD_RESP_TYPE_EXT_NONE (0 << 8)
+#define SDHI_CMD_RESP_TYPE_EXT_R1_R5_R6_R7 (4 << 8)
+#define SDHI_CMD_RESP_TYPE_EXT_R1B (5 << 8)
+#define SDHI_CMD_RESP_TYPE_EXT_R2 (6 << 8)
+#define SDHI_CMD_RESP_TYPE_EXT_R3_R4 (7 << 8)
+#define SDHI_CMD_ADTC_EN (1 << 11)
+#define SDHI_CMD_DATA_DIR_READ (1 << 12)
+#define SDHI_BLK_TRANSFER (1 << 13)
+
+#define SDIO_MAX_FREQ 25000000
+
+#define HW_SDHI_ERR_CRCE (0x01U << 17)
+#define HW_SDHI_ERR_RTIMEOUT (0x01U << 22)
+#define HW_SDHI_ERR_DTIMEOUT (0x01U << 19)
+
+#define SDHI_WAIT_ACCESS_BIT 2
+#define SDHI_WAIT_RESPONSE_BIT 0
+
+#define SDIO_TX_RX_COMPLETE_TIMEOUT_LOOPS (1000000U)
+
+struct ra_sdhi
+{
+    const sdmmc_instance_t *instance;
+    sdmmc_device_t *media_device;
+};
+
+#endif

libraries/HAL_Drivers/drv_soft_i2c.c

@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#include "board.h"
+#include "drv_soft_i2c.h"
+#include "drv_config.h"
+
+#ifdef RT_USING_I2C
+
+#define DBG_TAG              "drv.i2c"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#if !defined(BSP_USING_I2C0) && !defined(BSP_USING_I2C1)
+    #error "Please define at least one BSP_USING_I2Cx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+static const struct ra_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_I2C0
+    I2C0_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_I2C1
+    I2C1_BUS_CONFIG,
+#endif
+};
+
+static struct ra_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param ra i2c dirver class.
+ */
+static void ra_i2c_gpio_init(struct ra_i2c *i2c)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param ra config class.
+ * @param The sda pin state.
+ */
+static void ra_set_sda(void *data, rt_int32_t state)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param ra config class.
+ * @param The scl pin state.
+ */
+static void ra_set_scl(void *data, rt_int32_t state)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t ra_get_sda(void *data)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t ra_get_scl(void *data)
+{
+    struct ra_soft_i2c_config *cfg = (struct ra_soft_i2c_config *)data;
+    return rt_pin_read(cfg->scl);
+}
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void ra_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops ra_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = ra_set_sda,
+    .set_scl  = ra_set_scl,
+    .get_sda  = ra_get_sda,
+    .get_scl  = ra_get_scl,
+    .udelay   = ra_udelay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param ra config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t ra_i2c_bus_unlock(const struct ra_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            ra_udelay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            ra_udelay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ra_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = ra_bit_ops_default;
+        i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        ra_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        ra_i2c_bus_unlock(&soft_i2c_config[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              soft_i2c_config[i].bus_name,
+              soft_i2c_config[i].scl,
+              soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */

libraries/HAL_Drivers/drv_soft_i2c.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+/* ra config class */
+struct ra_soft_i2c_config
+{
+    rt_uint32_t scl;
+    rt_uint32_t sda;
+    const char *bus_name;
+};
+/* ra i2c dirver class */
+struct ra_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C1_SCL_PIN,                         \
+        .sda = BSP_I2C1_SDA_PIN,                         \
+        .bus_name = "i2c1",                              \
+    }
+#endif
+
+#ifdef BSP_USING_I2C2
+#define I2C2_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C2_SCL_PIN,                         \
+        .sda = BSP_I2C2_SDA_PIN,                         \
+        .bus_name = "i2c2",                              \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif

libraries/HAL_Drivers/drv_spi.c

@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     Mr.Tiger     first version
+ * 2021-11-04     Sherman      ADD complete_event
+ */
+/**< Note : Turn on any DMA mode and all SPIs will turn on DMA */
+
+#include "drv_spi.h"
+
+#ifdef RT_USING_SPI
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.spi"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+#define RA_SPI0_EVENT 0x00
+#define RA_SPI1_EVENT 0x01
+static struct rt_event complete_event = {0};
+
+static struct ra_spi_handle spi_handle[] =
+{
+#ifdef BSP_USING_SPI0
+    {.bus_name = "spi0", .spi_ctrl_t = &g_spi0_ctrl, .spi_cfg_t = &g_spi0_cfg,},
+#endif
+
+#ifdef BSP_USING_SPI1
+    {.bus_name = "spi1", .spi_ctrl_t = &g_spi1_ctrl, .spi_cfg_t = &g_spi1_cfg,},
+#endif
+};
+
+static struct ra_spi spi_config[sizeof(spi_handle) / sizeof(spi_handle[0])] = {0};
+
+void spi0_callback(spi_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
+    {
+        rt_event_send(&complete_event, RA_SPI0_EVENT);
+    }
+    rt_interrupt_leave();
+}
+
+void spi1_callback(spi_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
+    {
+        rt_event_send(&complete_event, RA_SPI1_EVENT);
+    }
+    rt_interrupt_leave();
+}
+
+static rt_err_t ra_wait_complete(rt_event_t event, const char bus_name[RT_NAME_MAX])
+{
+    rt_uint32_t recved = 0x00;
+
+    if (bus_name[3] == '0')
+    {
+        return rt_event_recv(event,
+                             RA_SPI0_EVENT,
+                             RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                             RT_WAITING_FOREVER,
+                             &recved);
+    }
+    else if (bus_name[3] == '1')
+    {
+        return rt_event_recv(event,
+                             RA_SPI1_EVENT,
+                             RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                             RT_WAITING_FOREVER,
+                             &recved);
+    }
+    return -RT_EINVAL;
+}
+
+static spi_bit_width_t ra_width_shift(rt_uint8_t data_width)
+{
+    spi_bit_width_t bit_width = SPI_BIT_WIDTH_8_BITS;
+    if(data_width == 1)
+        bit_width = SPI_BIT_WIDTH_8_BITS;
+    else if(data_width == 2)
+        bit_width = SPI_BIT_WIDTH_16_BITS;
+    else if(data_width == 4)
+        bit_width = SPI_BIT_WIDTH_32_BITS;
+
+    return bit_width;
+}
+
+static rt_err_t ra_write_message(struct rt_spi_device *device, const void *send_buf, const rt_size_t len)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device->parent.user_data != NULL);
+    RT_ASSERT(send_buf != NULL);
+    RT_ASSERT(len > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+
+    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
+    /**< send msessage */
+    err = R_SPI_Write((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, send_buf, len, bit_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s write failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
+    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
+    return len;
+}
+
+static rt_err_t ra_read_message(struct rt_spi_device *device, void *recv_buf, const rt_size_t len)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device->parent.user_data != NULL);
+    RT_ASSERT(recv_buf != NULL);
+    RT_ASSERT(len > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+
+    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
+    /**< receive message */
+    err = R_SPI_Read((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, recv_buf, len, bit_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("\n%s write failed.\n", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
+    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
+    return len;
+}
+
+static rt_err_t ra_write_read_message(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+    RT_ASSERT(message->length > 0);
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+
+    spi_bit_width_t bit_width = ra_width_shift(spi_dev->rt_spi_cfg_t->data_width);
+    /**< write and receive message */
+    err = R_SPI_WriteRead((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, message->send_buf, message->recv_buf, message->length, bit_width);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s write and read failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
+    ra_wait_complete(&complete_event, spi_dev->ra_spi_handle_t->bus_name);
+    return message->length;
+}
+
+/**< init spi TODO : MSB does not support modification */
+static rt_err_t ra_hw_spi_configure(struct rt_spi_device *device,
+                                    struct rt_spi_configuration *configuration)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(configuration != NULL);
+    rt_err_t err = RT_EOK;
+
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+    spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
+
+    /**< data_width : 1 -> 8 bits , 2 -> 16 bits, 4 -> 32 bits, default 32 bits*/
+    rt_uint8_t data_width = configuration->data_width / 8;
+    RT_ASSERT(data_width == 1 || data_width == 2 || data_width == 4);
+    configuration->data_width = configuration->data_width / 8;
+    spi_dev->rt_spi_cfg_t = configuration;
+
+    spi_extended_cfg_t *spi_cfg = (spi_extended_cfg_t *)spi_dev->ra_spi_handle_t->spi_cfg_t->p_extend;
+
+    /**< Configure Select Line */
+    rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
+
+    /**< config bitrate */
+    R_SPI_CalculateBitrate(spi_dev->rt_spi_cfg_t->max_hz, &spi_cfg->spck_div);
+
+    /**< init */
+    err = R_SPI_Open((spi_ctrl_t *)spi_dev->ra_spi_handle_t->spi_ctrl_t, (spi_cfg_t const * const)spi_dev->ra_spi_handle_t->spi_cfg_t);
+    /* handle error */
+    if (RT_EOK != err)
+    {
+        LOG_E("%s init failed.", spi_dev->ra_spi_handle_t->bus_name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_uint32_t ra_spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+
+    rt_err_t err = RT_EOK;
+    struct ra_spi *spi_dev =  rt_container_of(device->bus, struct ra_spi, bus);
+    spi_dev->cs_pin = (rt_uint32_t)device->parent.user_data;
+
+    if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+            rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
+        else
+            rt_pin_write(spi_dev->cs_pin, PIN_LOW);
+    }
+
+    if (message->length > 0)
+    {
+        if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< receive message */
+            err = ra_read_message(device, (void *)message->recv_buf, (const rt_size_t)message->length);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
+        {
+            /**< send message */
+            err = ra_write_message(device, (const void *)message->send_buf, (const rt_size_t)message->length);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< send and receive message */
+            err =  ra_write_read_message(device, message);
+        }
+    }
+
+    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+            rt_pin_write(spi_dev->cs_pin, PIN_LOW);
+        else
+            rt_pin_write(spi_dev->cs_pin, PIN_HIGH);
+    }
+    return err;
+}
+
+static const struct rt_spi_ops ra_spi_ops =
+{
+    .configure = ra_hw_spi_configure,
+    .xfer = ra_spixfer,
+};
+
+void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(device_name != NULL);
+    RT_ASSERT(bus_name != NULL);
+    RT_ASSERT(user_data != NULL);
+
+    rt_err_t err = rt_spi_bus_attach_device(device, device_name, bus_name, user_data);
+    if (RT_EOK != err)
+    {
+        LOG_E("%s attach failed.", bus_name);
+    }
+}
+
+int ra_hw_spi_init(void)
+{
+    for (rt_uint8_t spi_index = 0; spi_index < sizeof(spi_handle) / sizeof(spi_handle[0]); spi_index++)
+    {
+        spi_config[spi_index].ra_spi_handle_t = &spi_handle[spi_index];
+
+        /**< register spi bus */
+        rt_err_t err = rt_spi_bus_register(&spi_config[spi_index].bus, spi_handle[spi_index].bus_name, &ra_spi_ops);
+        if (RT_EOK != err)
+        {
+            LOG_E("%s bus register failed.", spi_config[spi_index].ra_spi_handle_t->bus_name);
+            return -RT_ERROR;
+        }
+    }
+
+    if (RT_EOK != rt_event_init(&complete_event, "ra_spi", RT_IPC_FLAG_PRIO))
+    {
+        LOG_E("SPI transfer event init fail!");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(ra_hw_spi_init);
+#endif /* RT_USING_SPI */

libraries/HAL_Drivers/drv_spi.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     Mr.Tiger   first version
+ */
+
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#include "board.h"
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef R_SPI_H
+struct ra_spi_handle
+{
+    const char bus_name[RT_NAME_MAX];
+    const spi_cfg_t           *spi_cfg_t;
+    const spi_instance_ctrl_t *spi_ctrl_t;
+};
+
+struct ra_spi
+{
+    rt_uint32_t                  cs_pin;
+    struct ra_spi_handle        *ra_spi_handle_t;
+    struct rt_spi_configuration *rt_spi_cfg_t;
+    struct rt_spi_bus            bus;
+};
+#endif
+
+void rt_hw_spi_device_attach(struct rt_spi_device *device, const char *device_name, const char *bus_name, void *user_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+/* stm32 spi dirver class */
+
+#endif /*__DRV_SPI_H__ */

libraries/HAL_Drivers/drv_usart_v2.c

@@ -0,0 +1,517 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#include <drv_usart_v2.h>
+
+#ifdef RT_USING_SERIAL_V2
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.usart"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+static struct ra_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    UART0_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART5
+    UART5_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART6
+    UART6_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART7
+    UART7_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART8
+    UART8_CONFIG,
+#endif
+
+#ifdef BSP_USING_UART9
+    UART9_CONFIG,
+#endif
+};
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+
+#ifdef BSP_USING_UART5
+    UART5_INDEX,
+#endif
+
+#ifdef BSP_USING_UART6
+    UART6_INDEX,
+#endif
+
+#ifdef BSP_USING_UART7
+    UART7_INDEX,
+#endif
+
+#ifdef BSP_USING_UART8
+    UART8_INDEX,
+#endif
+
+#ifdef BSP_USING_UART9
+    UART9_INDEX,
+#endif
+};
+
+static struct ra_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static void ra_uart_get_config(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    uart_obj[UART0_INDEX].serial.config = config;
+    uart_obj[UART0_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART0_INDEX].serial.config.rx_bufsz = BSP_UART0_RX_BUFSIZE;
+    uart_obj[UART0_INDEX].serial.config.tx_bufsz = BSP_UART0_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART1
+    uart_obj[UART1_INDEX].serial.config = config;
+    uart_obj[UART1_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
+    uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART2
+    uart_obj[UART2_INDEX].serial.config = config;
+    uart_obj[UART2_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
+    uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART3
+    uart_obj[UART3_INDEX].serial.config = config;
+    uart_obj[UART3_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
+    uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART0_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART4
+    uart_obj[UART4_INDEX].serial.config = config;
+    uart_obj[UART4_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
+    uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART6
+    uart_obj[UART6_INDEX].serial.config = config;
+    uart_obj[UART6_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
+    uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART7
+    uart_obj[UART7_INDEX].serial.config = config;
+    uart_obj[UART7_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
+    uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART8
+    uart_obj[UART8_INDEX].serial.config = config;
+    uart_obj[UART8_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
+    uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
+#endif
+
+#ifdef BSP_USING_UART9
+    uart_obj[UART9_INDEX].serial.config = config;
+    uart_obj[UART9_INDEX].uart_dma_flag = 0;
+
+    uart_obj[UART9_INDEX].serial.config.rx_bufsz = BSP_UART9_RX_BUFSIZE;
+    uart_obj[UART9_INDEX].serial.config.tx_bufsz = BSP_UART9_TX_BUFSIZE;
+#endif
+}
+
+
+/*
+ * UART interface
+ */
+static rt_err_t ra_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct ra_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    fsp_err_t err = FSP_SUCCESS;
+
+    uart = rt_container_of(serial, struct ra_uart, serial);
+    RT_ASSERT(uart != RT_NULL);
+
+    err = R_SCI_UART_Open(uart->config->p_api_ctrl, uart->config->p_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        return RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ra_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    return RT_EOK;
+}
+
+static int ra_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct ra_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct ra_uart, serial);
+    RT_ASSERT(uart != RT_NULL);
+
+    sci_uart_instance_ctrl_t *p_ctrl = (sci_uart_instance_ctrl_t *)uart->config->p_api_ctrl;
+
+    p_ctrl->p_reg->TDR = c;
+    while ((p_ctrl->p_reg->SSR_b.TEND) == 0);
+
+    return RT_EOK;
+}
+
+static int ra_uart_getc(struct rt_serial_device *serial)
+{
+    return RT_EOK;
+}
+
+static rt_size_t ra_uart_transmit(struct rt_serial_device     *serial,
+                                  rt_uint8_t           *buf,
+                                  rt_size_t             size,
+                                  rt_uint32_t           tx_flag)
+{
+    struct ra_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+    uart = rt_container_of(serial, struct ra_uart, serial);
+
+    ra_uart_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)tx_flag);
+
+    return size;
+}
+
+#ifdef BSP_USING_UART0
+void user_uart0_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART0_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART1
+void user_uart1_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART1_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART2
+void user_uart2_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART2_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART3
+void user_uart3_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART3_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART4
+void user_uart4_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART4_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART5
+void user_uart5_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART5_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART6
+void user_uart6_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART6_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART7
+void user_uart7_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART7_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART8
+void user_uart8_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART8_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_UART9
+void user_uart9_callback(uart_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+
+    struct rt_serial_device *serial = &uart_obj[UART9_INDEX].serial;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (UART_EVENT_RX_CHAR == p_args->event)
+    {
+        struct rt_serial_rx_fifo *rx_fifo;
+        rx_fifo = (struct rt_serial_rx_fifo *) serial->serial_rx;
+        RT_ASSERT(rx_fifo != RT_NULL);
+
+        rt_ringbuffer_putchar(&(rx_fifo->rb), (rt_uint8_t)p_args->data);
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    rt_interrupt_leave();
+}
+#endif
+
+static const struct rt_uart_ops ra_uart_ops =
+{
+    .configure = ra_uart_configure,
+    .control = ra_uart_control,
+    .putc = ra_uart_putc,
+    .getc = ra_uart_getc,
+    .transmit = ra_uart_transmit
+};
+
+
+int rt_hw_usart_init(void)
+{
+    rt_err_t result = 0;
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ra_uart);
+
+    ra_uart_get_config();
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config = &uart_config[i];
+        uart_obj[i].serial.ops = &ra_uart_ops;
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial,
+                                       uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR,
+                                       NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL_V2 */

libraries/HAL_Drivers/drv_usart_v2.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-07-29     KyleChan     first version
+ */
+
+#ifndef __DRV_USART_V2_H__
+#define __DRV_USART_V2_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+/* renesas config class */
+struct ra_uart_config
+{
+    const char *name;
+    uart_ctrl_t *const p_api_ctrl;
+    uart_cfg_t const *const p_cfg;
+};
+
+struct ra_uart
+{
+    struct rt_serial_device serial;
+
+    rt_uint16_t uart_dma_flag;
+
+    struct ra_uart_config *config;
+};
+
+int rt_hw_usart_init(void);
+
+#endif  /* __DRV_USART_H__ */

libraries/HAL_Drivers/drv_wdt.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-20     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+#ifdef RT_USING_WDT
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.wdt"
+#include <rtdbg.h>
+
+static struct rt_watchdog_device ra_wdt_dev;
+static struct rt_watchdog_ops ops;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
+{
+    rt_err_t ret = -RT_ERROR;
+    struct st_wdt_timeout_values *wdt_value = {0};
+    switch (cmd)
+    {
+    /* feed the watchdog */
+    case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+        if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
+        {
+            LOG_E("watch dog keepalive fail.");
+            ret =  -RT_ERROR;
+        }
+        else
+        {
+            ret = RT_EOK;
+        }
+        break;
+    /* set watchdog timeout */
+    case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        /**< set*/
+        LOG_W("Use the FSP tool to modify the configuration parameters!");
+        ret = -RT_EINVAL;
+        break;
+    case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+        wdt_value = (struct st_wdt_timeout_values *)arg;
+        if (R_WDT_TimeoutGet(&g_wdt_ctrl, wdt_value) != FSP_SUCCESS)
+        {
+            LOG_E("wdt get timeout failed.");
+            ret =  -RT_ERROR;
+        }
+        else
+        {
+            ret = RT_EOK;
+        }
+        break;
+    case RT_DEVICE_CTRL_WDT_START:
+        if (R_WDT_Open(&g_wdt_ctrl, &g_wdt_cfg) == FSP_SUCCESS)
+        {
+            if (R_WDT_Refresh(&g_wdt_ctrl) != FSP_SUCCESS)
+            {
+                LOG_E("wdt start failed.");
+                ret =  -RT_ERROR;
+            }
+            else
+            {
+                ret = RT_EOK;
+            }
+        }
+        else
+        {
+            LOG_E("wdt start failed.");
+            ret =  -RT_ERROR;
+        }
+        break;
+    default:
+        LOG_W("This command is not supported.");
+        ret =  -RT_ERROR;
+    }
+    return ret;
+}
+
+int rt_wdt_init(void)
+{
+    ops.init = &wdt_init;
+    ops.control = &wdt_control;
+    ra_wdt_dev.ops = &ops;
+    /* register watchdog device */
+    if (rt_hw_watchdog_register(&ra_wdt_dev, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_wdt_init);
+
+#endif /* RT_USING_WDT */

libraries/Kconfig

@@ -0,0 +1,16 @@
+
+config SOC_FAMILY_RENESAS
+    bool
+    default n
+
+config SOC_SERIES_R7FA6M4
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_RENESAS
+    default n
+
+config SOC_SERIES_R7FA2L1
+    bool
+    select ARCH_ARM_CORTEX_M23
+    select SOC_FAMILY_RENESAS
+    default n

project_0/.config

@@ -0,0 +1,810 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart9"
+CONFIG_RT_VER_NUM=0x40101
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+# CONFIG_RT_USING_DFS_DEVFS is not set
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_SERIAL_V1 is not set
+CONFIG_RT_USING_SERIAL_V2=y
+CONFIG_RT_SERIAL_USING_DMA=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+
+#
+# Device Control
+#
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_FAMILY_RENESAS=y
+# CONFIG_SOC_SERIES_R7FA6M4 is not set
+CONFIG_SOC_SERIES_R7FA2L1=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_CPK_R7FA2L1AB=y
+CONFIG_SOC_R7FA2L1AB=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+# CONFIG_BSP_USING_ONCHIP_FLASH is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART9=y
+# CONFIG_BSP_UART9_RX_USING_DMA is not set
+# CONFIG_BSP_UART9_TX_USING_DMA is not set
+CONFIG_BSP_UART9_RX_BUFSIZE=256
+CONFIG_BSP_UART9_TX_BUFSIZE=0
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_LPM is not set
+
+#
+# Board extended module Drivers
+#

project_0/.gitignore

@@ -0,0 +1,5 @@
+/RTE
+/Listings
+/Objects
+ra_cfg.txt
+

project_0/.ignore_format.yml

@@ -0,0 +1,9 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- ra
+- ra_gen
+- ra_cfg
+- RTE

project_0/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>__project_name_flag__</name>
+  <comment />
+  <projects>
+    </projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+            </arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+            </arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

project_0/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin

project_0/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1820729025223469141" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

project_0/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

project_0/.settings/projcfg.ini

@@ -0,0 +1,21 @@
+#RT-Thread Studio Project Configuration
+# Mon Oct 31 09:20:18 2022
+cfg_version=v3.0
+
+board_name=
+bsp_version=
+bsp_path=
+chip_name=R7FA2L1AB2DFM
+dvendor_name=RENESAS
+project_base_rtt_bsp=true
+is_use_scons_build=true
+hardware_adapter=J-Link
+selected_rtt_version=latest
+board_base_nano_proj=false
+is_base_example_project=false
+example_name=
+project_type=rt-thread
+os_branch=master
+os_version=latest
+project_name=None
+output_project_path=D:\workspace\Sherman\rt-thread\bsp\renesas\ra2l1-cpk\dist\ra2l1-cpk

project_0/.settings/project0.JLink.Debug.rttlaunch

@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.adapterName" value="J-Link"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="false"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDeviceName" value="unknown"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.flashDownloadHex" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="R7FA2L1AB"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="4000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${studio_install_path}/repo/Extract/Debugger_Support_Packages/SEGGER/J-Link/v7.50a/JLinkGDBServerCL.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerRunAfterStopDebug" value="true"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.jlinkExecutable" value="${studio_install_path}/repo/Extract/Debugger_Support_Packages/SEGGER/J-Link/v7.50a/JLink.exe"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${studio_install_path}/repo/Extract/ToolChain_Support_Packages/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="ra6m4"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/ra6m4"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+</launchConfiguration>

project_0/.settings/standalone.prefs

@@ -0,0 +1,21 @@
+#Mon Oct 31 09:16:14 CST 2022
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/all=2918861270,ra/board/ra2l1_cpk/board_leds.c|1521504391,ra/board/ra2l1_cpk/board_init.c|586415029,ra/board/ra2l1_cpk/board.h|2985489297,ra/board/ra2l1_cpk/board_init.h|2104808665,ra/board/ra2l1_cpk/board_leds.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2425160085,ra/fsp/inc/api/bsp_api.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|3297195641,ra/fsp/inc/fsp_version.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|1728953905,ra/fsp/inc/fsp_features.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2208590403,ra/fsp/inc/instances/r_ioport.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#R7FA2L1AB2DFM\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/all=3050420323,ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h|3828286676,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h|4234922905,ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h|4018024988,ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h|286820788,ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c|3229315956,ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra2l1_cpk\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#device\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=3254285722,ra/fsp/src/r_ioport/r_ioport.c|1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra2l1\#\#fsp\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c|1906465970,ra/fsp/inc/api/r_external_irq_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|3916852077,ra/fsp/inc/api/r_uart_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.629312687=false
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=

project_0/Kconfig

@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+    
+# you can change the RTT_ROOT default "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+    
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "$BSP_DIR/board/Kconfig"

project_0/QE-Touch/SConscript

@@ -0,0 +1,24 @@
+import glob
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+group = []
+CPPPATH = []
+
+file = glob.glob('*.tifcfg')
+if len(file):
+    if rtconfig.PLATFORM in ['iccarm']:
+        print("\nThe current project does not support IAR build\n")
+        Return('group')
+    elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+        src += ['qe_touch_config.c']
+        src += ['qe_sample_rtthread.c']
+        CPPPATH = [cwd]
+
+    CPPDEFINES = ['QE_TOUCH_CONFIGURATION']
+    group = DefineGroup('QE-Touch', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

project_0/QE-Touch/qe_sample_rtthread.c

@@ -0,0 +1,70 @@
+#include "qe_touch_config.h"
+#include <rtthread.h>
+#include <rtdevice.h>
+#define TOUCH_SCAN_INTERVAL_EXAMPLE (20)    /* milliseconds */
+
+uint64_t button_status;
+#if (TOUCH_CFG_NUM_SLIDERS != 0)
+    uint16_t slider_position[TOUCH_CFG_NUM_SLIDERS];
+#endif
+#if (TOUCH_CFG_NUM_WHEELS != 0)
+    uint16_t wheel_position[TOUCH_CFG_NUM_WHEELS];
+#endif
+
+void qe_touch_main(void *parameter)
+{
+    fsp_err_t err;
+    rt_uint32_t led_blu = rt_pin_get("P501");
+
+    /* Open Touch middleware */
+    rt_kprintf("TOUCH Open\n");
+    err = RM_TOUCH_Open(g_qe_touch_instance_config01.p_ctrl, g_qe_touch_instance_config01.p_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        rt_kprintf("RM_TOUCH_Open fail\n");
+        return;
+    }
+
+    rt_kprintf("TOUCH ScanStart\n");
+    /* Main loop */
+    while (true)
+    {
+        /* for [CONFIG01] configuration */
+        err = RM_TOUCH_ScanStart(g_qe_touch_instance_config01.p_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            rt_kprintf("RM_TOUCH_Open fail\n");
+            return;
+        }
+        while (0 == g_qe_touch_flag) {}
+        g_qe_touch_flag = 0;
+
+        err = RM_TOUCH_DataGet(g_qe_touch_instance_config01.p_ctrl, &button_status, NULL, NULL);
+        if (FSP_SUCCESS == err)
+        {
+            if (button_status)
+            {
+                rt_pin_write(led_blu, PIN_HIGH);
+            }
+            else
+            {
+                rt_pin_write(led_blu, PIN_LOW);
+            }
+        }
+
+        /* FIXME: Since this is a temporary process, so re-create a waiting process yourself. */
+        rt_thread_mdelay(TOUCH_SCAN_INTERVAL_EXAMPLE);
+    }
+}
+
+int touch_init(void)
+{
+    rt_thread_t tid = rt_thread_create("touch", qe_touch_main, RT_NULL, 512, 10, 50);
+    if (tid)
+    {
+        rt_thread_startup(tid);
+    }
+    return 0;
+}
+INIT_APP_EXPORT(touch_init);
+//MSH_CMD_EXPORT(touch_init, touch_init);

project_0/R7FA2L1AB2DFM.pincfg

@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="utf-8"?>
+<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
+  <v1:pinMappingsRef version="2.05" file="" />
+  <v1:deviceSetting id="renesas.ra2l1_fm" pattern="R7FA2L1****FM">
+    <v1:packageSetting id="renesas.64lqfp" />
+  </v1:deviceSetting>
+  <v1:configSetting configurationId="debug0.mode" altId="debug0.mode.swd" />
+  <v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p108" altId="p108.debug0.swdio">
+    <v1:connectionSetting altId="debug0.swdio.p108" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.swdio" altId="debug0.swdio.p108">
+    <v1:connectionSetting altId="p108.debug0.swdio" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p300" altId="p300.debug0.swclk">
+    <v1:connectionSetting altId="debug0.swclk.p300" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.swclk" altId="debug0.swclk.p300">
+    <v1:connectionSetting altId="p300.debug0.swclk" />
+  </v1:configSetting>
+</v1:pinSettings>

project_0/README.md

@@ -0,0 +1,168 @@
+# 瑞萨 CPK-RA2L1 开发板
+
+## 简介
+
+本文档为瑞萨 CPK-RA2L1 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+主要内容如下：
+
+- 开发板介绍
+- BSP 快速上手指南
+
+## 开发板介绍
+
+CPK-RA2L1 评估板可通过灵活配置软件包和 IDE，可帮助用户对[RA2L1 MCU 群组](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra2l1-48mhz-arm-cortex-m23-ultra-low-power-general-purpose-microcontroller)的特性轻松进行评估，并对嵌入系统应用程序进行开发。
+
+开发板正面外观如下图：
+
+![image-20220707141215644](docs/picture/ra2l1-cpk.png) 
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：R7FA2L1AB2DFM，48MHz，Arm Cortex®-M23 内核，256kB 代码闪存, 32kB SRAM
+- 调试接口：板载 J-Link 接口
+- 扩展接口：两个 PMOD 连接器
+
+**更多详细资料及工具**
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+**硬件连接**
+
+使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART9：P109(TXD)、P110(RXD)。
+
+![image-20220707144056181](docs/picture/ra2l1-cpk1.png) 
+
+**编译下载**
+
+- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
+
+> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
+
+- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA2L1AB，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
+
+![image-20211011182434519](docs/picture/jflash.png) 
+
+![image-20220707115828323](docs/picture/jflash1.png) 
+
+![image-20220707144644438](docs/picture/jflash2.png) 
+
+![image-20220707144752679](docs/picture/jflash3.png) 
+
+**查看运行结果**
+
+下载程序成功之后，系统会自动运行并打印系统信息。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.0 build Jul  7 2022 14:44:40
+ 2006 - 2022 Copyright by RT-Thread team
+
+Hello RT-Thread!
+msh >
+msh >
+RT-Thread shell commands:
+reboot           - Reboot System
+help             - RT - Thread shell help.
+ps               - List threads in the system.
+free             - Show the memory usage in the system.
+hello            - say hello world
+clear            - clear the terminal screen
+version          - show RT - Thread version information
+list_thread      - list thread
+list_sem         - list semaphore in system
+list_event       - list event in system
+list_mutex       - list mutex in system
+list_mailbox     - list mail box in system
+list_msgqueue    - list message queue in system
+list_timer       - list timer in system
+list_device      - list device in system
+list             - list all commands in system
+icu_sample       - icu sample
+
+msh >
+```
+
+**应用入口函数**
+
+应用层的入口函数在 **bsp\ra6m4-cpk\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
+
+```c
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+
+    while (1)
+    {
+        rt_pin_write(LED3_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED3_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
+
+### 进阶使用
+
+**资料及文档**
+
+- [开发板官网主页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra2l1-evaluation-board#overview)
+- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
+- [datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra2l1-group-datasheet?language=en&r=1596841)
+- [User’s Manual: Hardware](https://www2.renesas.cn/jp/zh/document/mah/ra2l1-group-users-manual-hardware?language=en&r=1398061)
+
+**FSP 配置**
+
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
+
+1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 3.5.0 版本
+2. 下载安装完成后，需要添加 CPK-RA6M4 开发板的官方板级支持包
+> 打开[ 开发板详情页](https://www2.renesas.cn/cn/zh/products/microcontrollers-microprocessors/ra-cortex-m-mcus/cpk-ra2l1-evaluation-board#overview)，在**“软件下载”**列表中找到 **CPK-RA2L1板级支持包**，点击链接即可下载
+3. 如何将 **板级支持包**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/cn/zh/document/gde/1596896?language=zh&r=1596841)
+4. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+
+**ENV 配置**
+
+- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+
+此 BSP 默认只开启了UART和IRQ3外设功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
+
+步骤如下：
+1. 在 bsp 下打开 env 工具。
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+3. 输入`pkgs --update`命令更新软件包。
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+
+## FAQ
+
+### 使用 MDK 的 DEBUG 时如果遇到提示  “Error: Flash Download failed Cortex-M23” 怎么办？
+
+可按照下图操作，修改 Utilities 中的选项：
+
+![image-20211214102231248](docs/picture/readme_faq1.png) 
+
+## 联系人信息
+
+在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们  [RT-Thread 社区论坛](https://club.rt-thread.org/)
+
+## 贡献代码
+
+如果您对此BSP感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

project_0/SConscript

@@ -0,0 +1,27 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = []
+list = os.listdir(cwd)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    print("\nThe current project does not support IAR build\n")
+    Return('group')
+elif rtconfig.PLATFORM in ['gcc', 'armclang']:
+    if GetOption('target') != 'mdk5':
+        CPPPATH = [cwd + './src']
+        src = Glob('./src/*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')

project_0/SConstruct

@@ -0,0 +1,58 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+# set RTT_ROOT
+if not os.getenv("RTT_ROOT"): 
+    RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+rtconfig.BSP_LIBRARY_TYPE = None
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

project_0/board/Kconfig

@@ -0,0 +1,313 @@
+menu "Hardware Drivers Config"
+    config CPK_R7FA2L1AB
+        bool
+        default y
+
+    config SOC_R7FA2L1AB
+        bool
+        select SOC_SERIES_R7FA2L1
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+        source "libraries/HAL_Drivers/Kconfig"
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+            if BSP_USING_UART
+
+                menuconfig BSP_USING_UART0
+                    bool "Enable UART0"
+                    default n
+                    if BSP_USING_UART0
+                        config BSP_UART0_RX_USING_DMA
+                            bool "Enable UART0 RX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_TX_USING_DMA
+                            bool "Enable UART0 TX DMA"
+                            depends on BSP_USING_UART0 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART0_RX_BUFSIZE
+                            int "Set UART0 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART0_TX_BUFSIZE
+                            int "Set UART0 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+
+                menuconfig BSP_USING_UART1
+                    bool "Enable UART1"
+                    default n
+                    if BSP_USING_UART1
+                        config BSP_UART1_RX_USING_DMA
+                            bool "Enable UART1 RX DMA"
+                            depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART1_TX_USING_DMA
+                            bool "Enable UART1 TX DMA"
+                            depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART1_RX_BUFSIZE
+                            int "Set UART1 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART1_TX_BUFSIZE
+                            int "Set UART1 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+
+                menuconfig BSP_USING_UART2
+                    bool "Enable UART2"
+                    default n
+                    if BSP_USING_UART2
+                        config BSP_UART2_RX_USING_DMA
+                            bool "Enable UART2 RX DMA"
+                            depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART2_TX_USING_DMA
+                            bool "Enable UART2 TX DMA"
+                            depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART2_RX_BUFSIZE
+                            int "Set UART2 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART2_TX_BUFSIZE
+                            int "Set UART2 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+
+                menuconfig BSP_USING_UART3
+                    bool "Enable UART3"
+                    default n
+                    if BSP_USING_UART3
+                        config BSP_UART3_RX_USING_DMA
+                            bool "Enable UART3 RX DMA"
+                            depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART3_TX_USING_DMA
+                            bool "Enable UART3 TX DMA"
+                            depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART3_RX_BUFSIZE
+                            int "Set UART3 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART3_TX_BUFSIZE
+                            int "Set UART3 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+
+                menuconfig BSP_USING_UART9
+                    bool "Enable UART9"
+                    default n
+                    if BSP_USING_UART9
+                        config BSP_UART9_RX_USING_DMA
+                            bool "Enable UART9 RX DMA"
+                            depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART9_TX_USING_DMA
+                            bool "Enable UART9 TX DMA"
+                            depends on BSP_USING_UART9 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART9_RX_BUFSIZE
+                            int "Set UART9 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART9_TX_BUFSIZE
+                            int "Set UART9 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+            endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                config BSP_USING_HW_I2C
+                    bool "Enable Hardware I2C BUS"
+                    default n
+                if BSP_USING_HW_I2C
+                    config BSP_USING_HW_I2C1
+                        bool "Enable Hardware I2C1 BUS"
+                        default n
+                endif
+                if !BSP_USING_HW_I2C
+                    menuconfig BSP_USING_I2C1
+                        bool "Enable I2C1 BUS (software simulation)"
+                        default y
+                        if BSP_USING_I2C1
+                            config BSP_I2C1_SCL_PIN
+                                hex "i2c1 scl pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050C
+                            config BSP_I2C1_SDA_PIN
+                                hex "I2C1 sda pin number"
+                                range 0x0000 0x0B0F
+                                default 0x050B
+                        endif
+                endif
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI 
+                config BSP_SPI_USING_DTC_DMA
+                    bool "Enable SPI DTC transfers data without using the CPU."
+                    default n
+
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+        
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+            endif
+
+        menuconfig BSP_USING_DAC
+            bool "Enable DAC"
+            default n
+            select RT_USING_DAC
+            if BSP_USING_DAC
+                config BSP_USING_DAC0
+                    bool "Enable DAC0"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM0
+                    bool "Enable GPT0 (32-Bits) output PWM"
+                    default n
+                
+                config BSP_USING_PWM1
+                    bool "Enable GPT1 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM2
+                    bool "Enable GPT2 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM3
+                    bool "Enable GPT3 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM4
+                    bool "Enable GPT4 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM6
+                    bool "Enable GPT6 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM7
+                    bool "Enable GPT7 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM8
+                    bool "Enable GPT8 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM9
+                    bool "Enable GPT9 (16-Bits) output PWM"
+                    default n
+            endif
+
+        menuconfig BSP_USING_CAN
+            bool "Enable CAN"
+            default n
+            select RT_USING_CAN
+            if BSP_USING_CAN
+                config BSP_USING_CAN0
+                    bool "Enable CAN0"
+                    default n
+            endif
+
+        config BSP_USING_LPM
+            bool "Enable LPM"
+            select RT_USING_PM
+            default n
+            if BSP_USING_LPM
+                config BSP_LPM_SLEEP
+                    bool "Enable LPM sleep mode"
+                    default n
+
+                config BSP_LPM_SNOOZE
+                    bool "Enable LPM snooze mode"
+                    default n
+
+                config BSP_LPM_STANDBY
+                    bool "Enable LPM standby mode"
+                    default n
+            endif
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+    endmenu
+endmenu

project_0/board/SConscript

@@ -0,0 +1,19 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+src = []
+
+if GetDepend(['BSP_USING_LPM']):
+    src += ['drv_pm.c']
+
+objs = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

project_0/board/board.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-10      Sherman      first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_SRAM_SIZE           32
+#define RA_SRAM_END            (0x20000000 + RA_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RAM_END$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __RAM_segment_used_end__;
+#define HEAP_BEGIN      (&__RAM_segment_used_end__)
+#endif
+
+#define HEAP_END        RA_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/board/drv_pm.c

@@ -0,0 +1,761 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-22     Sherman      first version
+ */
+
+// #define DRV_DEBUG
+#define DBG_TAG              "drv.pm"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <hal_data.h>
+
+#include <drivers/pm.h>
+
+#define RESET_VALUE     (0x00)
+#define CLOCK_START     (0U)
+#define CLOCK_STOP      (1U)
+
+/* Control block configuration in LPM mode */
+#ifdef BSP_LPM_SLEEP
+    #define LPM_SLEEP_CTRL  (lpm_instance_ctrl_t *)&g_lpm_sleep_ctrl
+    #define LPM_SLEEP_CFG   (lpm_cfg_t *)&g_lpm_sleep_cfg
+#else
+    #define LPM_SLEEP_CTRL  RT_NULL
+    #define LPM_SLEEP_CFG   RT_NULL
+#endif
+
+#ifdef BSP_LPM_STANDBY
+    #define LPM_SW_STANDBY_CTRL  (lpm_instance_ctrl_t *)&g_lpm_sw_standby_ctrl
+    #define LPM_SW_STANDBY_CFG  (lpm_cfg_t *)&g_lpm_sw_standby_cfg
+#else
+    #define LPM_SW_STANDBY_CTRL  RT_NULL
+    #define LPM_SW_STANDBY_CFG  RT_NULL
+#endif
+
+#ifdef BSP_LPM_SNOOZE
+    #define LPM_SW_SNOOZE_CTRL  (lpm_instance_ctrl_t *)&g_lpm_sw_standby_with_snooze_ctrl
+    #define LPM_SW_SNOOZE_CFG   (lpm_cfg_t *)&g_lpm_sw_standby_with_snooze_cfg
+#else
+    #define LPM_SW_SNOOZE_CFG   RT_NULL
+    #define LPM_SW_SNOOZE_CTRL  RT_NULL
+#endif
+
+/**
+ * These are LPM Mode instances for Sleep, Software Standby, Snooze and Deep
+ * Software Standby Modes.These instances are created by the FSP. We need these
+ * at the Application level to take the MCU to different LPM modes with configured
+ * trigger/cancel sources
+ */
+lpm_instance_ctrl_t *g_lpm_ctrl_instance_ctrls[] =
+{
+    LPM_SLEEP_CTRL,
+    LPM_SW_STANDBY_CTRL,
+    LPM_SW_SNOOZE_CTRL,
+};
+
+lpm_cfg_t   *g_lpm_ctrl_instance_cfgs[]  =
+{
+    LPM_SLEEP_CFG,
+    LPM_SW_STANDBY_CFG,
+    LPM_SW_SNOOZE_CFG,
+};
+
+/**
+ * Low Power Mode Definitions for LPM app
+ * Since there are no Normal mode definition in LPM driver, use this enum to keep LPM app state including:
+ * Sleep, SW Standby, SW Standby with Snooze enabled, Deep SW Standby, Normal.
+ * Power consumption: NORMAL_STATE > SLEEP_STATE > SW_STANDBY_SNOOZE_STATE > SW_STANDBY_STATE > DEEP_SW_STANDBY_STATE
+ */
+enum
+{
+    SLEEP_STATE = 0,             /* Sleep mode */
+    SW_STANDBY_STATE,            /* SW Standby mode */
+    SW_STANDBY_SNOOZE_STATE,     /* SW Standby mode with Snooze enabled */
+    DEEP_SW_STANDBY_STATE,       /* Deep SW Standby mode */
+    NORMAL_STATE                 /* Normal mode */
+};
+
+#ifdef DRV_DEBUG
+static char *lpmstate_to_string(rt_uint8_t state)
+{
+    switch (state)
+    {
+    case SLEEP_STATE:
+        return "SLEEP";
+    case SW_STANDBY_STATE:
+        return "SW STANDBY";
+    case SW_STANDBY_SNOOZE_STATE:
+        return "SW STANDBY SNOOZE";
+    case DEEP_SW_STANDBY_STATE:
+        return "DEEP SW STANDBY";
+    case NORMAL_STATE:
+        return "NORMAL";
+    default:
+        return "UNKNOWN";
+    }
+    return "UNKNOWN";
+}
+
+static char *clk_to_string(cgc_clock_t cstate)
+{
+    switch (cstate)
+    {
+    case CGC_CLOCK_HOCO:
+        return "HOCO CLOCK";
+    case CGC_CLOCK_MOCO:
+        return "MOCO CLOCK";
+    case CGC_CLOCK_LOCO:
+        return "LOCO CLOCK";
+    case CGC_CLOCK_MAIN_OSC:
+        return "MAIN OSC CLOCK";
+    case CGC_CLOCK_SUBCLOCK:
+        return "SUB OSC CLOCK";
+    case CGC_CLOCK_PLL:
+        return "PLL OSC CLOCK";
+    default:
+        return "UNKNOWN";
+    }
+    return "UNKNOWN";
+}
+#endif
+
+/**
+ * @brief       This function enables and puts the MCU in sleep mode.
+ * @param[IN]   Requested LPM Mode and the pointer to it's instance
+ * @retval      FSP_SUCCESS:    Upon successful entering sleep mode
+ * @retval      Any Other Error code apart from FSP_SUCCESS
+ */
+static fsp_err_t lpm_mode_enter(uint8_t lpm_mode, lpm_instance_ctrl_t *const p_current_ctrl)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    switch (lpm_mode)
+    {
+
+    case SW_STANDBY_STATE:
+        /* Enter SW Standby mode */
+        err = R_LPM_LowPowerModeEnter(p_current_ctrl);
+        break;
+
+    case SLEEP_STATE:
+        /* Enter Sleep mode */
+        err = R_LPM_LowPowerModeEnter(p_current_ctrl);
+        break;
+
+    case SW_STANDBY_SNOOZE_STATE:
+        /* Enter SW Standby with Snooze enabled mode */
+        err = R_LPM_LowPowerModeEnter(p_current_ctrl);
+        break;
+
+    default:
+        /* return error */
+        err = FSP_ERR_INVALID_MODE;
+        break;
+    }
+    return err;
+}
+
+/**
+ * @brief       Start the LPM mode based on the incoming state
+ * @param[IN]   state: This is requested LPM state
+ * @retval      None.
+ */
+static void entry_lpm(uint8_t state)
+{
+    if (RT_NULL == g_lpm_ctrl_instance_ctrls[state])
+    {
+        return;
+    }
+
+    fsp_err_t err = FSP_SUCCESS;
+    /* Disable IO port if it's not in Deep SW Standby mode */
+    if (DEEP_SW_STANDBY_STATE != state)
+    {
+        /* Disable IO port before going to LPM mode*/
+        err = R_IOPORT_PinsCfg(&g_ioport_ctrl, &g_bsp_pin_cfg);
+        /* Handle error */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+
+    /* Open LPM instance*/
+    err = R_LPM_Open(g_lpm_ctrl_instance_ctrls[state], g_lpm_ctrl_instance_cfgs[state]);
+    /* Handle error */
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+    /* Enter LPM mode. Function will return after waking from low power mode. */
+    err = lpm_mode_enter(state, g_lpm_ctrl_instance_ctrls[state]);
+
+    /* Handle error */
+    if (FSP_SUCCESS == err)
+    {
+        /* Close LPM instance.*/
+        err = R_LPM_Close(g_lpm_ctrl_instance_ctrls[state]);
+        /* Handle error */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        /* Put IO port configuration back to user's selections */
+        err = R_IOPORT_PinsCfg(&g_ioport_ctrl, &g_bsp_pin_cfg);
+        /* Handle error */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+    else
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+}
+
+/**********************************************************************************************************************
+ * @brief       This function does necessary setups before entering SW Standby with Snooze enabled.
+ * @retval      FSP_SUCCESS Upon successful checking and starting LOCO clock, AGT1 timer
+ * @retval      Any Other Error code apart from FSP_SUCCESS
+ **********************************************************************************************************************/
+static fsp_err_t standby_snooze_set(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    agt_extended_cfg_t const *p_agt0_extend = agt1_timer_cascade_trigger_cfg.p_extend;
+
+    /* Turn off part of the clock before entering Snooze */
+    err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MAIN_OSC);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    /*
+     * Check and start LOCO clock. LOCO is needed since it is selected as AGT1 timer counter source
+     * CGC module is opened in user_clocks_set function
+     */
+    if (AGT_CLOCK_LOCO == p_agt0_extend->count_source)
+    {
+        if (CLOCK_STOP == R_SYSTEM->LOCOCR_b.LCSTP)
+        {
+            /* Start LOCO clock */
+            err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, NULL);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                return err;
+            }
+            /* LOCO does not have Oscillation Stabilization Flag, wait for its stabilization by adding delay */
+            R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+        }
+    }
+
+    return err;
+}
+
+static void ra_sleep(struct rt_pm *pm, rt_uint8_t mode)
+{
+    switch (mode)
+    {
+    case PM_SLEEP_MODE_NONE:
+        break;
+
+    case PM_SLEEP_MODE_IDLE:
+#ifdef BSP_LPM_SLEEP
+        /* enrty sleep mode */
+        entry_lpm(SLEEP_STATE);
+#else
+        LOG_W("Disable mode:%s", lpmstate_to_string(SLEEP_STATE));
+#endif
+        break;
+
+    case PM_SLEEP_MODE_LIGHT:
+        LOG_W("PM_SLEEP_MODE_LIGHT:This mode is not supported!");
+        break;
+
+    case PM_SLEEP_MODE_DEEP:
+#ifdef BSP_LPM_SNOOZE
+        /* enrty standby snooze mode */
+        standby_snooze_set();
+        entry_lpm(SW_STANDBY_SNOOZE_STATE);
+#else
+        LOG_W("Disable mode:%s", lpmstate_to_string(SW_STANDBY_SNOOZE_STATE));
+#endif
+        break;
+
+    case PM_SLEEP_MODE_STANDBY:
+#ifdef BSP_LPM_STANDBY
+        /* enrty standby mode */
+        entry_lpm(SW_STANDBY_STATE);
+#else
+        LOG_W("Disable mode:%s", lpmstate_to_string(SW_STANDBY_STATE));
+#endif
+        break;
+
+    case PM_SLEEP_MODE_SHUTDOWN:
+        LOG_W("PM_SLEEP_MODE_SHUTDOWN:This mode is not supported!");
+        break;
+
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+}
+
+/**
+ * @brief This function changes the System Clock. Currently MOSC and SOSC are not connected on RA2L1 board.
+ *        So these needs to be turned OFF
+ */
+static void preffered_ra_clock_setting(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    /* Stop the Main Oscillator as it is not available on RA2L1-EK Board */
+    err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MAIN_OSC);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    /* Stop the Sub Oscillator as it is not available on RA2L1-EK Board */
+    err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+}
+
+#ifdef R_CGC_H
+void uart_update(rt_uint8_t clockmode)
+{
+    baud_setting_t baud_setting;
+    uint32_t       baud_rate                 = BAUD_RATE_115200;
+    bool           enable_bitrate_modulation = false;
+    uint32_t       error_rate_x_1000         = 5000;
+
+    switch (clockmode)
+    {
+    case CGC_CLOCK_HOCO:
+        baud_rate = BAUD_RATE_115200;
+        break;
+    case CGC_CLOCK_MOCO:
+        baud_rate = BAUD_RATE_38400;
+        break;
+    case CGC_CLOCK_LOCO:
+    case CGC_CLOCK_SUBCLOCK:
+        baud_rate = 600;
+        break;
+    default:
+        baud_rate = BAUD_RATE_115200;
+        break;
+    }
+
+    fsp_err_t err = R_SCI_UART_BaudCalculate(baud_rate,
+                    enable_bitrate_modulation,
+                    error_rate_x_1000,
+                    &baud_setting);
+    err = R_SCI_UART_BaudSet(&g_uart9_ctrl, (void *) &baud_setting);
+    assert(FSP_SUCCESS == err);
+}
+
+/**
+ * @brief This function is used to changes the System Clock.
+ */
+static void change_system_clock(rt_uint8_t clockmode)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    cgc_divider_cfg_t sys_divider_cf = { RESET_VALUE };
+    cgc_clock_t  sys_clock_source    = { RESET_VALUE };
+    cgc_clocks_cfg_t sys_clk_cfg     = { RESET_VALUE };
+    cgc_pll_cfg_t new_clk            = { RESET_VALUE };
+
+#if defined (CPK_R7FA2L1AB)
+    preffered_ra_clock_setting();
+    sys_clk_cfg.mainosc_state = CGC_CLOCK_CHANGE_STOP;
+#endif
+
+    err = R_CGC_SystemClockGet(&g_cgc0_ctrl, &sys_clock_source, &sys_divider_cf);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    LOG_D("MCU Running with Clock Source = %s.", clk_to_string(sys_clock_source));
+    switch (clockmode)
+    {
+    case CGC_CLOCK_HOCO:
+    case CGC_CLOCK_MOCO:
+    {
+        sys_clock_source = clockmode;
+        sys_clk_cfg.hoco_state = CGC_CLOCK_CHANGE_START;
+
+        sys_clk_cfg.pll_cfg.source_clock = sys_clock_source;
+        sys_clk_cfg.pll_cfg.divider = CGC_PLL_DIV_1;
+        sys_clk_cfg.pll_cfg.multiplier = 0;
+
+        sys_clk_cfg.pll2_cfg.source_clock = sys_clock_source;
+        sys_clk_cfg.pll2_cfg.divider = CGC_PLL_DIV_1;
+        sys_clk_cfg.pll2_cfg.multiplier = 0;
+
+        sys_clk_cfg.divider_cfg.pclka_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.pclkb_div = CGC_SYS_CLOCK_DIV_2;
+        sys_clk_cfg.divider_cfg.pclkc_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.pclkd_div = CGC_SYS_CLOCK_DIV_1;
+
+        sys_clk_cfg.divider_cfg.iclk_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.bclk_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.fclk_div = CGC_SYS_CLOCK_DIV_1;
+        break;
+    }
+
+    case CGC_CLOCK_LOCO:
+    case CGC_CLOCK_SUBCLOCK:
+    {
+        sys_clock_source = clockmode;
+        sys_clk_cfg.hoco_state = CGC_CLOCK_CHANGE_START;
+
+        sys_clk_cfg.pll_cfg.source_clock = sys_clock_source;
+        sys_clk_cfg.pll_cfg.divider = CGC_PLL_DIV_1;
+        sys_clk_cfg.pll_cfg.multiplier = 0;
+
+        sys_clk_cfg.pll2_cfg.source_clock = sys_clock_source;
+        sys_clk_cfg.pll2_cfg.divider = CGC_PLL_DIV_1;
+        sys_clk_cfg.pll2_cfg.multiplier = 0;
+
+        sys_clk_cfg.divider_cfg.pclka_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.pclkb_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.pclkc_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.pclkd_div = CGC_SYS_CLOCK_DIV_1;
+
+        sys_clk_cfg.divider_cfg.iclk_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.bclk_div = CGC_SYS_CLOCK_DIV_1;
+        sys_clk_cfg.divider_cfg.fclk_div = CGC_SYS_CLOCK_DIV_1;
+        break;
+    }
+
+    default:
+    {
+        sys_clock_source = CGC_CLOCK_PLL;
+        sys_clk_cfg.pll_state = CGC_CLOCK_CHANGE_NONE;
+        break;
+    }
+    }
+
+    sys_clk_cfg.system_clock = sys_clock_source;
+
+    err = R_CGC_ClocksCfg(&g_cgc0_ctrl, &sys_clk_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+
+    err = R_CGC_SystemClockSet(&g_cgc0_ctrl, sys_clock_source, &sys_clk_cfg.divider_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("Returned Error Code: 0x%x", err);
+    }
+    LOG_D("Requested Clock Source for MCU = %s.", clk_to_string(sys_clock_source));
+
+    if (CGC_CLOCK_SUBCLOCK == sys_clock_source)
+    {
+        new_clk.source_clock = CGC_CLOCK_SUBCLOCK;
+        err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_SUBCLOCK, &new_clk);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_LOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+    else if (CGC_CLOCK_LOCO == sys_clock_source)
+    {
+        new_clk.source_clock = CGC_CLOCK_LOCO;
+        err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_LOCO, &new_clk);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+    else if (CGC_CLOCK_MOCO == sys_clock_source)
+    {
+        new_clk.source_clock = CGC_CLOCK_MOCO;
+        err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_MOCO, &new_clk);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_HOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+    else if (CGC_CLOCK_HOCO == sys_clock_source)
+    {
+        new_clk.source_clock = CGC_CLOCK_HOCO;
+
+        err = R_CGC_ClockStart(&g_cgc0_ctrl, CGC_CLOCK_HOCO, &new_clk);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+
+        err = R_CGC_ClockStop(&g_cgc0_ctrl, CGC_CLOCK_MOCO);
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Returned Error Code: 0x%x", err);
+        }
+    }
+
+    /* Clock  Oscillation Stabilization, wait for its stabilization by adding delay */
+    R_BSP_SoftwareDelay(BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US, BSP_DELAY_UNITS_MICROSECONDS);
+
+    extern void rt_hw_systick_init(void);
+    rt_hw_systick_init();
+    uart_update(clockmode);
+}
+
+static void ra_run(struct rt_pm *pm, rt_uint8_t mode)
+{
+    switch (mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        change_system_clock(CGC_CLOCK_HOCO);
+        break;
+    case PM_RUN_MODE_MEDIUM_SPEED:
+        change_system_clock(CGC_CLOCK_MOCO);
+        break;
+    case PM_RUN_MODE_LOW_SPEED:
+        change_system_clock(CGC_CLOCK_LOCO);
+        break;
+    default:
+        break;
+    }
+}
+#endif
+
+/* Agt1 serves as a low-power timer */
+/**
+ * @brief       This function opens AGT modules
+ */
+static fsp_err_t agt_timer_init(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    /* Open AGT1 Timer in Periodic mode */
+    err = R_AGT_Open(&agt1_timer_cascade_trigger_ctrl, &agt1_timer_cascade_trigger_cfg);
+    return err;
+}
+
+/**
+ * @brief       This function starts AGT modules
+ */
+#define AGT_SECOND_COUNT   512 /* clock_frequency / clock_divider */
+#define PERIOD_MAX   0xFFFF
+static fsp_err_t agt_timer_start(rt_uint32_t timeout)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_uint32_t tick = timeout * AGT_SECOND_COUNT / RT_TICK_PER_SECOND;
+    rt_uint32_t period1 = tick > PERIOD_MAX ? PERIOD_MAX : tick;
+    if (period1)
+    {
+        /* PeriodSet AGT1 timer */
+        err = R_AGT_PeriodSet(&agt1_timer_cascade_trigger_ctrl, period1);
+        if (FSP_SUCCESS == err)
+        {
+            /* Start AGT1 timer */
+            err = R_AGT_Start(&agt1_timer_cascade_trigger_ctrl);
+        }
+    }
+
+    return err;
+}
+
+/**
+ * @brief       This function stops AGT modules
+ */
+static fsp_err_t agt_timer_stop(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    timer_status_t agt_status = {0};
+
+    err =  R_AGT_StatusGet(&agt1_timer_cascade_trigger_ctrl, &agt_status);
+    if (FSP_SUCCESS == err)
+    {
+        if (agt_status.state)
+        {
+            /* Stop Timer */
+            err = R_AGT_Stop(&agt1_timer_cascade_trigger_ctrl);
+            if (FSP_SUCCESS == err)
+            {
+                /* Reset counter */
+                err = R_AGT_PeriodSet(&agt1_timer_cascade_trigger_ctrl, 0);
+                err = R_AGT_Reset(&agt1_timer_cascade_trigger_ctrl);
+            }
+        }
+    }
+    return err;
+}
+
+static rt_uint32_t agt_timer_get(void)
+{
+    rt_uint32_t tick = 0;
+    rt_uint32_t counter = 0;
+
+    timer_status_t agt1_status = {0};
+    timer_info_t agt1_info = {RESET_VALUE};
+    /* Stop AGT timers if they are counting */
+    R_AGT_InfoGet(&agt1_timer_cascade_trigger_ctrl, &agt1_info);
+    R_AGT_StatusGet(&agt1_timer_cascade_trigger_ctrl, &agt1_status);
+    counter = agt1_status.counter < agt1_info.period_counts ?
+              agt1_info.period_counts : (agt1_info.period_counts - agt1_status.counter);
+
+    tick = counter * RT_TICK_PER_SECOND / AGT_SECOND_COUNT;
+    LOG_D("get tick %u counter %u", tick, counter);
+    return tick;
+}
+
+static void ra_timer_start(struct rt_pm *pm, rt_uint32_t timeout)
+{
+    agt_timer_start(timeout);
+}
+
+static void ra_timer_stop(struct rt_pm *pm)
+{
+    agt_timer_stop();
+}
+
+static rt_tick_t ra_timer_get_tick(struct rt_pm *pm)
+{
+    return agt_timer_get();
+}
+
+static const struct rt_pm_ops _ops =
+{
+    ra_sleep,
+#ifdef R_CGC_H
+    ra_run,
+#else
+    RT_NULL,
+#endif
+    ra_timer_start,
+    ra_timer_stop,
+    ra_timer_get_tick
+};
+
+/**
+ * @brief       This function initializes clock module by opening the CGC Module and Changes the System Clock to MOSC
+ * @param[IN]   None
+ * @retval      FSP_SUCCESS:     Upon successful initialization.
+ * @retval      Any Other Error code apart from FSP_SUCCESS
+ */
+static fsp_err_t init_cgc(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    cgc_clock_t       lsys_clock_source = {RESET_VALUE};
+    cgc_divider_cfg_t sys_divider_cf    = {RESET_VALUE};
+
+    /* Open CGC module */
+    err = R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
+    /* Handle error */
+    if (FSP_SUCCESS == err)
+    {
+        /* Get system clock source */
+        err =  R_CGC_SystemClockGet(&g_cgc0_ctrl, &lsys_clock_source, &sys_divider_cf);
+        /* Handle error */
+        if (FSP_SUCCESS == err)
+        {
+            LOG_D("MCU Running with Clock Source = %s.", clk_to_string(lsys_clock_source));
+        }
+    }
+    return err;
+}
+
+/**
+ * @brief   This function initialize the power manager
+ */
+int drv_pm_hw_init(void)
+{
+    rt_uint8_t timer_mask = 0;
+    fsp_err_t err = FSP_SUCCESS;
+    /* Initialize the CGC(Clock Generation Circuit) module.
+     * The CGC module API is used to dynamically change the required clock source */
+    err = init_cgc();
+    if (FSP_SUCCESS != err)
+    {
+        LOG_D("CGC Initialization Failed \r\n");
+        LOG_E("Returned Error Code: 0x%x", err);
+        return -1;
+    }
+
+    err = agt_timer_init();
+    if (FSP_SUCCESS != err)
+    {
+        LOG_D("AGT Initialization Failed \r\n");
+        LOG_E("Returned Error Code: 0x%x", err);
+        return -1;
+    }
+
+    /* initialize timer mask */
+    timer_mask = (1UL << PM_SLEEP_MODE_DEEP) | (1UL << PM_SLEEP_MODE_STANDBY);
+
+    /* initialize system pm module */
+    rt_system_pm_init(&_ops, timer_mask, RT_NULL);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(drv_pm_hw_init);

project_0/board/ports/SConscript

@@ -0,0 +1,24 @@
+
+from building import *
+import rtconfig
+
+cwd     = GetCurrentDir()
+
+src = []
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('drv_rw007.c')
+
+CPPPATH = [cwd]
+LOCAL_CCFLAGS = ''
+
+if rtconfig.PLATFORM in ['gcc']:
+    LOCAL_CCFLAGS += ' -std=c99'
+elif rtconfig.PLATFORM in ['armcc']:
+    LOCAL_CCFLAGS += ' --c99'
+elif rtconfig.PLATFORM in ['armclang']:
+    LOCAL_CCFLAGS += ' -std=c99'
+
+group = DefineGroup('Drivers', src, depend = [], CPPPATH = CPPPATH, LOCAL_CCFLAGS = LOCAL_CCFLAGS)
+
+Return('group')

project_0/board/ports/gpio_cfg.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-01-19     Sherman           first version
+ */
+
+/* Number of IRQ channels on the device */
+#define RA_IRQ_MAX  8
+
+/* PIN to IRQx table */
+#define PIN2IRQX_TABLE(pin)                 \
+{                                           \
+    switch (pin)                            \
+    {                                       \
+    case BSP_IO_PORT_04_PIN_00:             \
+    case BSP_IO_PORT_02_PIN_06:             \
+    case BSP_IO_PORT_01_PIN_05:             \
+        return 0;                           \
+    case BSP_IO_PORT_02_PIN_05:             \
+    case BSP_IO_PORT_01_PIN_01:             \
+    case BSP_IO_PORT_01_PIN_04:             \
+        return 1;                           \
+    case BSP_IO_PORT_01_PIN_00:             \
+    case BSP_IO_PORT_00_PIN_02:             \
+    case BSP_IO_PORT_02_PIN_13:             \
+        return 2;                           \
+    case BSP_IO_PORT_00_PIN_04:             \
+    case BSP_IO_PORT_01_PIN_10:             \
+    case BSP_IO_PORT_02_PIN_12:             \
+        return 3;                           \
+    case BSP_IO_PORT_04_PIN_02:             \
+    case BSP_IO_PORT_01_PIN_11:             \
+    case BSP_IO_PORT_04_PIN_11:             \
+        return 4;                           \
+    case BSP_IO_PORT_04_PIN_01:             \
+    case BSP_IO_PORT_03_PIN_02:             \
+    case BSP_IO_PORT_04_PIN_10:             \
+        return 5;                           \
+    case BSP_IO_PORT_03_PIN_01:             \
+    case BSP_IO_PORT_00_PIN_00:             \
+    case BSP_IO_PORT_04_PIN_09:             \
+        return 6;                           \
+    case BSP_IO_PORT_00_PIN_15:             \
+    case BSP_IO_PORT_00_PIN_01:             \
+    case BSP_IO_PORT_04_PIN_08:             \
+        return 7;                           \
+    default  :                              \
+        return -1;                          \
+    }                                       \
+}

project_0/buildinfo.gpdsc

@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+  <vendor>Renesas</vendor>
+  <name>Project Content</name>
+  <description>Project content managed by the Renesas Smart Configurator</description>
+  <url/>
+  <releases>
+    <release version="1.0.0"/>
+  </releases>
+  <generators>
+    <generator id="Renesas RA Smart Configurator">
+      <project_files>
+        <file category="include" name="src/"/>
+        <file category="source" name="src/hal_entry.c"/>
+      </project_files>
+    </generator>
+  </generators>
+  <components generator="Renesas RA Smart Configurator">
+    <component Cclass="Flex Software" Cgroup="Components" Csub="ra">
+      <files>
+        <file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
+        <file category="include" name="ra/fsp/inc/"/>
+        <file category="include" name="ra/fsp/inc/api/"/>
+        <file category="include" name="ra/fsp/inc/instances/"/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
+        <file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
+        <file category="header" name="ra/board/ra2l1_cpk/board.h" path=""/>
+        <file category="source" name="ra/board/ra2l1_cpk/board_init.c"/>
+        <file category="header" name="ra/board/ra2l1_cpk/board_init.h" path=""/>
+        <file category="source" name="ra/board/ra2l1_cpk/board_leds.c"/>
+        <file category="header" name="ra/board/ra2l1_cpk/board_leds.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_external_irq_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_icu.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o"/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="other" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_common.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_delay.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_guard.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_io.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_irq.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.o"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="other" name="ra/fsp/src/bsp/mcu/all/bsp_security.o"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_elc.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_icu.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_mcu_info.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra2l1/bsp_power.h" path=""/>
+        <file category="source" name="ra/fsp/src/r_icu/r_icu.c"/>
+        <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
+        <file category="other" name="ra/fsp/src/r_ioport/r_ioport.o"/>
+        <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
+        <file category="other" name="ra/fsp/src/r_sci_uart/r_sci_uart.o"/>
+        <file category="other" name="ra/SConscript"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Build Configuration">
+      <files>
+        <file category="include" name="ra_cfg/fsp_cfg/"/>
+        <file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_icu_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
+        <file category="other" name="ra_cfg/SConscript"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Generated Data">
+      <files>
+        <file category="include" name="ra_gen/"/>
+        <file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
+        <file category="source" name="ra_gen/common_data.c"/>
+        <file category="header" name="ra_gen/common_data.h" path=""/>
+        <file category="source" name="ra_gen/hal_data.c"/>
+        <file category="header" name="ra_gen/hal_data.h" path=""/>
+        <file category="source" name="ra_gen/main.c"/>
+        <file category="source" name="ra_gen/pin_data.c"/>
+        <file category="other" name="ra_gen/SConscript"/>
+        <file category="source" name="ra_gen/vector_data.c"/>
+        <file category="header" name="ra_gen/vector_data.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Linker Script">
+      <files>
+        <file category="linkerScript" name="script/fsp.scat"/>
+        <file category="other" name="script/ac6/fsp_keep.via"/>
+      </files>
+    </component>
+  </components>
+</package>

project_0/cconfig.h

@@ -0,0 +1,21 @@
+#ifndef CCONFIG_H__
+#define CCONFIG_H__
+/* Automatically generated file; DO NOT EDIT. */
+/* compiler configure file for RT-Thread in GCC*/
+
+#define HAVE_NEWLIB_H 1
+#define LIBC_VERSION "newlib 3.3.0"
+
+#define HAVE_SYS_SIGNAL_H 1
+#define HAVE_SYS_SELECT_H 1
+#define HAVE_PTHREAD_H 1
+
+#define HAVE_FDSET 1
+#define HAVE_SIGACTION 1
+#define HAVE_SIGEVENT 1
+#define HAVE_SIGINFO 1
+#define HAVE_SIGVAL 1
+#define GCC_VERSION_STR "10.2.1 20201103 (release)"
+#define STDC "2011"
+
+#endif

project_0/configuration.xml

@@ -0,0 +1,403 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<raConfiguration version="7">
+  <generalSettings>
+    <option key="#Board#" value="board.ra2l1cpk"/>
+    <option key="CPU" value="RA2L1"/>
+    <option key="#TargetName#" value="R7FA2L1AB2DFM"/>
+    <option key="#TargetARCHITECTURE#" value="cortex-m23"/>
+    <option key="#DeviceCommand#" value="R7FA2L1AB"/>
+    <option key="#RTOS#" value="_none"/>
+    <option key="#pinconfiguration#" value="R7FA2L1AB2DFM.pincfg"/>
+    <option key="#FSPVersion#" value="3.5.0"/>
+    <option key="#ConfigurationFragments#" value="Renesas##BSP##Board##ra2l1_cpk##"/>
+    <option key="#SELECTED_TOOLCHAIN#" value="com.arm.toolchain"/>
+  </generalSettings>
+  <raBspConfiguration>
+    <config id="config.bsp.ra2l1.R7FA2L1AB2DFM">
+      <property id="config.bsp.part_number" value="config.bsp.part_number.value"/>
+      <property id="config.bsp.rom_size_bytes" value="config.bsp.rom_size_bytes.value"/>
+      <property id="config.bsp.rom_size_bytes_hidden" value="262144"/>
+      <property id="config.bsp.ram_size_bytes" value="config.bsp.ram_size_bytes.value"/>
+      <property id="config.bsp.data_flash_size_bytes" value="config.bsp.data_flash_size_bytes.value"/>
+      <property id="config.bsp.package_style" value="config.bsp.package_style.value"/>
+      <property id="config.bsp.package_pins" value="config.bsp.package_pins.value"/>
+    </config>
+    <config id="config.bsp.ra2l1">
+      <property id="config.bsp.series" value="config.bsp.series.value"/>
+    </config>
+    <config id="config.bsp.ra2l1.fsp">
+      <property id="config.bsp.fsp.OFS0.iwdt_start_mode" value="config.bsp.fsp.OFS0.iwdt_start_mode.disabled"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_timeout" value="config.bsp.fsp.OFS0.iwdt_timeout.2048"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_divisor" value="config.bsp.fsp.OFS0.iwdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_end" value="config.bsp.fsp.OFS0.iwdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_window_start" value="config.bsp.fsp.OFS0.iwdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_reset_interrupt" value="config.bsp.fsp.OFS0.iwdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.iwdt_stop_control" value="config.bsp.fsp.OFS0.iwdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS0.wdt_start_mode" value="config.bsp.fsp.OFS0.wdt_start_mode.register"/>
+      <property id="config.bsp.fsp.OFS0.wdt_timeout" value="config.bsp.fsp.OFS0.wdt_timeout.16384"/>
+      <property id="config.bsp.fsp.OFS0.wdt_divisor" value="config.bsp.fsp.OFS0.wdt_divisor.128"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_end" value="config.bsp.fsp.OFS0.wdt_window_end.0"/>
+      <property id="config.bsp.fsp.OFS0.wdt_window_start" value="config.bsp.fsp.OFS0.wdt_window_start.100"/>
+      <property id="config.bsp.fsp.OFS0.wdt_reset_interrupt" value="config.bsp.fsp.OFS0.wdt_reset_interrupt.Reset"/>
+      <property id="config.bsp.fsp.OFS0.wdt_stop_control" value="config.bsp.fsp.OFS0.wdt_stop_control.stops"/>
+      <property id="config.bsp.fsp.OFS1.internal_clock_supply" value="config.bsp.fsp.OFS1.internal_clock_supply.type_a"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0.start" value="config.bsp.fsp.OFS1.voltage_detection0.start.disabled"/>
+      <property id="config.bsp.fsp.OFS1.voltage_detection0_level" value="config.bsp.fsp.OFS1.voltage_detection0_level.190"/>
+      <property id="config.bsp.fsp.OFS1.hoco_osc" value="config.bsp.fsp.OFS1.hoco_osc.enabled"/>
+      <property id="config.bsp.low_voltage_mode" value="config.bsp.low_voltage_mode.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_enable" value="config.bsp.fsp.mpu_pc0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc0_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc0_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_pc1_enable" value="config.bsp.fsp.mpu_pc1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_pc1_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_pc1_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg0_enable" value="config.bsp.fsp.mpu_reg0_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg0_start" value="0x000FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg0_end" value="0x000FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg1_enable" value="config.bsp.fsp.mpu_reg1_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg1_start" value="0x200FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg1_end" value="0x200FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg2_enable" value="config.bsp.fsp.mpu_reg2_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg2_start" value="0x407FFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg2_end" value="0x407FFFFF"/>
+      <property id="config.bsp.fsp.mpu_reg3_enable" value="config.bsp.fsp.mpu_reg3_enable.disabled"/>
+      <property id="config.bsp.fsp.mpu_reg3_start" value="0x400DFFFC"/>
+      <property id="config.bsp.fsp.mpu_reg3_end" value="0x400DFFFF"/>
+      <property id="config.bsp.fsp.dcdc" value="config.bsp.fsp.dcdc.disabled"/>
+      <property id="config.bsp.fsp.dcdc_range" value="config.bsp.fsp.dcdc_range.2v7_3v6"/>
+      <property id="config.bsp.common.main_osc_wait" value="config.bsp.common.main_osc_wait.wait_8163"/>
+      <property id="config.bsp.fsp.mcu.adc.max_freq_hz" value="64000000"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.max_baud" value="3333333"/>
+      <property id="config.bsp.fsp.mcu.adc.sample_and_hold" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_spi.max_bitrate" value="8000000"/>
+      <property id="config.bsp.fsp.mcu.spi.max_bitrate" value="16000000"/>
+      <property id="config.bsp.fsp.mcu.iic_master.rate.rate_fastplus" value="0"/>
+      <property id="config.bsp.fsp.mcu.sci_uart.cstpen_channels" value="0x0"/>
+      <property id="config.bsp.fsp.mcu.gpt.pin_count_source_channels" value="0xFFFF"/>
+      <property id="config.bsp.common.id_mode" value="config.bsp.common.id_mode.unlocked"/>
+      <property id="config.bsp.common.id_code" value="FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"/>
+      <property id="config.bsp.common.id1" value=""/>
+      <property id="config.bsp.common.id2" value=""/>
+      <property id="config.bsp.common.id3" value=""/>
+      <property id="config.bsp.common.id4" value=""/>
+      <property id="config.bsp.common.id_fixed" value=""/>
+    </config>
+    <config id="config.bsp.ra">
+      <property id="config.bsp.common.main" value="0x400"/>
+      <property id="config.bsp.common.heap" value="0"/>
+      <property id="config.bsp.common.vcc" value="3300"/>
+      <property id="config.bsp.common.checking" value="config.bsp.common.checking.disabled"/>
+      <property id="config.bsp.common.assert" value="config.bsp.common.assert.none"/>
+      <property id="config.bsp.common.error_log" value="config.bsp.common.error_log.none"/>
+      <property id="config.bsp.common.soft_reset" value="config.bsp.common.soft_reset.disabled"/>
+      <property id="config.bsp.common.main_osc_populated" value="config.bsp.common.main_osc_populated.disabled"/>
+      <property id="config.bsp.common.pfs_protect" value="config.bsp.common.pfs_protect.enabled"/>
+      <property id="config.bsp.common.c_runtime_init" value="config.bsp.common.c_runtime_init.enabled"/>
+      <property id="config.bsp.common.early_init" value="config.bsp.common.early_init.disabled"/>
+      <property id="config.bsp.common.main_osc_clock_source" value="config.bsp.common.main_osc_clock_source.crystal"/>
+      <property id="config.bsp.common.subclock_populated" value="config.bsp.common.subclock_populated.disabled"/>
+      <property id="config.bsp.common.subclock_drive" value="config.bsp.common.subclock_drive.standard"/>
+      <property id="config.bsp.common.subclock_stabilization_ms" value="1000"/>
+    </config>
+  </raBspConfiguration>
+  <raClockConfiguration>
+    <node id="board.clock.xtal.freq" mul="20000000" option="_edit"/>
+    <node id="board.clock.hoco.freq" option="board.clock.hoco.freq.48m"/>
+    <node id="board.clock.loco.freq" option="board.clock.loco.freq.32768"/>
+    <node id="board.clock.moco.freq" option="board.clock.moco.freq.8m"/>
+    <node id="board.clock.subclk.freq" option="board.clock.subclk.freq.32768"/>
+    <node id="board.clock.clock.source" option="board.clock.clock.source.hoco"/>
+    <node id="board.clock.iclk.div" option="board.clock.iclk.div.1"/>
+    <node id="board.clock.iclk.display" option="board.clock.iclk.display.value"/>
+    <node id="board.clock.pclkb.div" option="board.clock.pclkb.div.2"/>
+    <node id="board.clock.pclkb.display" option="board.clock.pclkb.display.value"/>
+    <node id="board.clock.pclkd.div" option="board.clock.pclkd.div.1"/>
+    <node id="board.clock.pclkd.display" option="board.clock.pclkd.display.value"/>
+    <node id="board.clock.clkout.source" option="board.clock.clkout.source.disabled"/>
+    <node id="board.clock.clkout.div" option="board.clock.clkout.div.1"/>
+    <node id="board.clock.clkout.display" option="board.clock.clkout.display.value"/>
+  </raClockConfiguration>
+  <raComponentSelection>
+    <component apiversion="" class="Common" condition="" group="all" subgroup="fsp_common" variant="" vendor="Renesas" version="3.5.0">
+      <description>Board Support Package Common Files</description>
+      <originalPack>Renesas.RA.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_ioport" variant="" vendor="Renesas" version="3.5.0">
+      <description>I/O Port</description>
+      <originalPack>Renesas.RA.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="CMSIS" condition="" group="CMSIS5" subgroup="CoreM" variant="" vendor="Arm" version="5.8.0+renesas.0.fsp.3.5.0">
+      <description>Arm CMSIS Version 5 - Core (M)</description>
+      <originalPack>Arm.CMSIS5.5.8.0+renesas.0.fsp.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="device" variant="R7FA2L1AB2DFM" vendor="Renesas" version="3.5.0">
+      <description>Board support package for R7FA2L1AB2DFM</description>
+      <originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="device" variant="" vendor="Renesas" version="3.5.0">
+      <description>Board support package for RA2L1</description>
+      <originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="ra2l1" subgroup="fsp" variant="" vendor="Renesas" version="3.5.0">
+      <description>Board support package for RA2L1 - FSP Data</description>
+      <originalPack>Renesas.RA_mcu_ra2l1.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="BSP" condition="" group="Board" subgroup="ra2l1_cpk" variant="" vendor="Renesas" version="3.5.0">
+      <description>RA2L1-CPK Board Support Files</description>
+      <originalPack>Renesas.RA_board_ra2l1_cpk.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_sci_uart" variant="" vendor="Renesas" version="3.5.0">
+      <description>SCI UART</description>
+      <originalPack>Renesas.RA.3.5.0.pack</originalPack>
+    </component>
+    <component apiversion="" class="HAL Drivers" condition="" group="all" subgroup="r_icu" variant="" vendor="Renesas" version="3.5.0">
+      <description>External Interrupt</description>
+      <originalPack>Renesas.RA.3.5.0.pack</originalPack>
+    </component>
+  </raComponentSelection>
+  <raElcConfiguration/>
+  <raIcuConfiguration/>
+  <raModuleConfiguration>
+    <module id="module.driver.ioport_on_ioport.0">
+      <property id="module.driver.ioport.name" value="g_ioport"/>
+      <property id="module.driver.ioport.elc_trigger_ioport1" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport2" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport3" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioport4" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioportb" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioportc" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioportd" value="_disabled"/>
+      <property id="module.driver.ioport.elc_trigger_ioporte" value="_disabled"/>
+      <property id="module.driver.ioport.pincfg" value="g_bsp_pin_cfg"/>
+    </module>
+    <module id="module.driver.uart_on_sci_uart.629312687">
+      <property id="module.driver.uart.name" value="g_uart9"/>
+      <property id="module.driver.uart.channel" value="9"/>
+      <property id="module.driver.uart.data_bits" value="module.driver.uart.data_bits.data_bits_8"/>
+      <property id="module.driver.uart.parity" value="module.driver.uart.parity.parity_off"/>
+      <property id="module.driver.uart.stop_bits" value="module.driver.uart.stop_bits.stop_bits_1"/>
+      <property id="module.driver.uart.baud" value="115200"/>
+      <property id="module.driver.uart.baudrate_modulation" value="module.driver.uart.baudrate_modulation.disabled"/>
+      <property id="module.driver.uart.baudrate_max_err" value="5"/>
+      <property id="module.driver.uart.flow_control" value="module.driver.uart.flow_control.rts"/>
+      <property id="module.driver.uart.pin_control_port" value="module.driver.uart.pin_control_port.PORT_DISABLE"/>
+      <property id="module.driver.uart.pin_control_pin" value="module.driver.uart.pin_control_pin.PIN_DISABLE"/>
+      <property id="module.driver.uart.clk_src" value="module.driver.uart.clk_src.int_clk"/>
+      <property id="module.driver.uart.rx_edge_start" value="module.driver.uart.rx_edge_start.falling_edge"/>
+      <property id="module.driver.uart.noisecancel_en" value="module.driver.uart.noisecancel_en.disabled"/>
+      <property id="module.driver.uart.rx_fifo_trigger" value="module.driver.uart.rx_fifo_trigger.max"/>
+      <property id="module.driver.uart.callback" value="user_uart9_callback"/>
+      <property id="module.driver.uart.rxi_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.txi_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.tei_ipl" value="board.icu.common.irq.priority2"/>
+      <property id="module.driver.uart.eri_ipl" value="board.icu.common.irq.priority2"/>
+    </module>
+    <module id="module.driver.external_irq_on_icu.832378872">
+      <property id="module.driver.external_irq.name" value="g_external_irq3"/>
+      <property id="module.driver.external_irq.channel" value="3"/>
+      <property id="module.driver.external_irq.trigger" value="module.driver.external_irq.trigger.trig_rising"/>
+      <property id="module.driver.external_irq.filter_enable" value="module.driver.external_irq.filter_enable.false"/>
+      <property id="module.driver.external_irq.pclk_div" value="module.driver.external_irq.pclk_div.pclk_div_by_64"/>
+      <property id="module.driver.external_irq.p_callback" value="irq_callback"/>
+      <property id="module.driver.external_irq.ipl" value="board.icu.common.irq.priority2"/>
+    </module>
+    <context id="_hal.0">
+      <stack module="module.driver.ioport_on_ioport.0"/>
+      <stack module="module.driver.uart_on_sci_uart.629312687"/>
+      <stack module="module.driver.external_irq_on_icu.832378872"/>
+    </context>
+    <config id="config.driver.ioport">
+      <property id="config.driver.ioport.checking" value="config.driver.ioport.checking.system"/>
+    </config>
+    <config id="config.driver.icu">
+      <property id="config.driver.icu.param_checking_enable" value="config.driver.icu.param_checking_enable.bsp"/>
+    </config>
+    <config id="config.driver.sci_uart">
+      <property id="config.driver.sci_uart.param_checking_enable" value="config.driver.sci_uart.param_checking_enable.bsp"/>
+      <property id="config.driver.sci_uart.fifo_support" value="config.driver.sci_uart.fifo_support.disabled"/>
+      <property id="config.driver.sci_uart.dtc_support" value="config.driver.sci_uart.dtc_support.disabled"/>
+      <property id="config.driver.sci_uart.flow_control" value="config.driver.sci_uart.flow_control.disabled"/>
+    </config>
+  </raModuleConfiguration>
+  <raPinConfiguration>
+    <symbolicName propertyId="p000.symbolic_name" value="ARDUINO_AN00"/>
+    <symbolicName propertyId="p004.symbolic_name" value="SW1"/>
+    <symbolicName propertyId="p012.symbolic_name" value="CTSU_TS1"/>
+    <symbolicName propertyId="p013.symbolic_name" value="CTSU_TS2"/>
+    <symbolicName propertyId="p015.symbolic_name" value="CTSU_TS3"/>
+    <symbolicName propertyId="p100.symbolic_name" value="PMODA_MISOA_RXD0"/>
+    <symbolicName propertyId="p101.symbolic_name" value="PMODA_MOSIA_TXD0"/>
+    <symbolicName propertyId="p102.symbolic_name" value="PMODA_RSPCKA_SCK0"/>
+    <symbolicName propertyId="p103.symbolic_name" value="PMODA_SSLA0_CTS0"/>
+    <symbolicName propertyId="p104.symbolic_name" value="ARDUINO_GPIO_IRQ01"/>
+    <symbolicName propertyId="p105.symbolic_name" value="PMODA_IO2"/>
+    <symbolicName propertyId="p106.symbolic_name" value="PMODA_IO3"/>
+    <symbolicName propertyId="p107.symbolic_name" value="ARDUINO_GPIO_KRM07"/>
+    <symbolicName propertyId="p108.symbolic_name" value="DEBUG_SWDIO_TMS"/>
+    <symbolicName propertyId="p109.symbolic_name" value="DEBUG_TDO"/>
+    <symbolicName propertyId="p110.symbolic_name" value="DEBUG_TDI"/>
+    <symbolicName propertyId="p111.symbolic_name" value="ARDUINO_GPIO_GTIOC6"/>
+    <symbolicName propertyId="p112.symbolic_name" value="ARDUINO_GPIO_CLK"/>
+    <symbolicName propertyId="p113.symbolic_name" value="ARDUINO_GPIO"/>
+    <symbolicName propertyId="p201.symbolic_name" value="MD"/>
+    <symbolicName propertyId="p205.symbolic_name" value="ARDUINO_TXD"/>
+    <symbolicName propertyId="p207.symbolic_name" value="ARDUINO_RST"/>
+    <symbolicName propertyId="p208.symbolic_name" value="PMODA_IO1"/>
+    <symbolicName propertyId="p212.symbolic_name" value="EXTAL"/>
+    <symbolicName propertyId="p213.symbolic_name" value="XTAL"/>
+    <symbolicName propertyId="p214.symbolic_name" value="XCOUT"/>
+    <symbolicName propertyId="p215.symbolic_name" value="XCIN"/>
+    <symbolicName propertyId="p300.symbolic_name" value="DEBUG_SWDCLK_TCK"/>
+    <symbolicName propertyId="p301.symbolic_name" value="GROVE_SCL"/>
+    <symbolicName propertyId="p302.symbolic_name" value="GROVE_SDA"/>
+    <symbolicName propertyId="p303.symbolic_name" value="PMODB_IO1"/>
+    <symbolicName propertyId="p304.symbolic_name" value="PMODB_IO3"/>
+    <symbolicName propertyId="p400.symbolic_name" value="PMODB_SCK1"/>
+    <symbolicName propertyId="p401.symbolic_name" value="PMODB_MOSI_TXD1"/>
+    <symbolicName propertyId="p402.symbolic_name" value="PMODB_MISO_RXD1"/>
+    <symbolicName propertyId="p403.symbolic_name" value="PMODB_SSL_CTS1"/>
+    <symbolicName propertyId="p407.symbolic_name" value="ARDUINO_SDA"/>
+    <symbolicName propertyId="p408.symbolic_name" value="ARDUINO_SCL"/>
+    <symbolicName propertyId="p409.symbolic_name" value="PMODB_IRQ06"/>
+    <symbolicName propertyId="p410.symbolic_name" value="PMODB_IO2"/>
+    <symbolicName propertyId="p411.symbolic_name" value="PMODA_IRQ04"/>
+    <symbolicName propertyId="p500.symbolic_name" value="ARDUINO_GPIO_GTIOC5"/>
+    <symbolicName propertyId="p501.symbolic_name" value="LED2"/>
+    <symbolicName propertyId="p502.symbolic_name" value="LED1"/>
+    <pincfg active="true" name="RA2L1 CPK" selected="true" symbol="g_bsp_pin_cfg">
+      <configSetting altId="adc0.an00.p000" configurationId="adc0.an00"/>
+      <configSetting altId="adc0.an01.p001" configurationId="adc0.an01"/>
+      <configSetting altId="adc0.an02.p002" configurationId="adc0.an02"/>
+      <configSetting altId="adc0.an03.p003" configurationId="adc0.an03"/>
+      <configSetting altId="adc0.mode.custom" configurationId="adc0.mode"/>
+      <configSetting altId="ctsu0.cfcts28.p015" configurationId="ctsu0.cfcts28"/>
+      <configSetting altId="ctsu0.cfcts32.p012" configurationId="ctsu0.cfcts32"/>
+      <configSetting altId="ctsu0.cfcts33.p013" configurationId="ctsu0.cfcts33"/>
+      <configSetting altId="ctsu0.mode.enabled" configurationId="ctsu0.mode"/>
+      <configSetting altId="ctsu0.tscap.p112" configurationId="ctsu0.tscap"/>
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="iic0.mode.enabled.free" configurationId="iic0.mode"/>
+      <configSetting altId="iic0.pairing.free" configurationId="iic0.pairing"/>
+      <configSetting altId="iic0.scl.p408" configurationId="iic0.scl"/>
+      <configSetting altId="iic0.sda.p407" configurationId="iic0.sda"/>
+      <configSetting altId="irq0.irq01.p104" configurationId="irq0.irq01"/>
+      <configSetting altId="irq0.irq03.p004" configurationId="irq0.irq03"/>
+      <configSetting altId="irq0.irq04.p411" configurationId="irq0.irq04"/>
+      <configSetting altId="irq0.irq06.p409" configurationId="irq0.irq06"/>
+      <configSetting altId="irq0.mode.enabled" configurationId="irq0.mode"/>
+      <configSetting altId="p000.adc0.an00" configurationId="p000"/>
+      <configSetting altId="p000.gpio_mode.gpio_mode_an" configurationId="p000.gpio_mode"/>
+      <configSetting altId="p001.adc0.an01" configurationId="p001"/>
+      <configSetting altId="p001.gpio_mode.gpio_mode_an" configurationId="p001.gpio_mode"/>
+      <configSetting altId="p002.adc0.an02" configurationId="p002"/>
+      <configSetting altId="p002.gpio_mode.gpio_mode_an" configurationId="p002.gpio_mode"/>
+      <configSetting altId="p003.adc0.an03" configurationId="p003"/>
+      <configSetting altId="p003.gpio_mode.gpio_mode_an" configurationId="p003.gpio_mode"/>
+      <configSetting altId="p004.irq0.irq03" configurationId="p004"/>
+      <configSetting altId="p004.gpio_irq.gpio_irq_enabled" configurationId="p004.gpio_irq"/>
+      <configSetting altId="p004.gpio_mode.gpio_mode_irq" configurationId="p004.gpio_mode"/>
+      <configSetting altId="p012.ctsu0.cfcts32" configurationId="p012"/>
+      <configSetting altId="p012.gpio_mode.gpio_mode_peripheral" configurationId="p012.gpio_mode"/>
+      <configSetting altId="p013.ctsu0.cfcts33" configurationId="p013"/>
+      <configSetting altId="p013.gpio_mode.gpio_mode_peripheral" configurationId="p013.gpio_mode"/>
+      <configSetting altId="p015.ctsu0.cfcts28" configurationId="p015"/>
+      <configSetting altId="p015.gpio_mode.gpio_mode_peripheral" configurationId="p015.gpio_mode"/>
+      <configSetting altId="p100.sci0.rxd" configurationId="p100"/>
+      <configSetting altId="p100.gpio_mode.gpio_mode_peripheral" configurationId="p100.gpio_mode"/>
+      <configSetting altId="p101.sci0.txd" configurationId="p101"/>
+      <configSetting altId="p101.gpio_mode.gpio_mode_peripheral" configurationId="p101.gpio_mode"/>
+      <configSetting altId="p102.sci0.sck" configurationId="p102"/>
+      <configSetting altId="p102.gpio_mode.gpio_mode_peripheral" configurationId="p102.gpio_mode"/>
+      <configSetting altId="p103.sci0.cts" configurationId="p103"/>
+      <configSetting altId="p103.gpio_mode.gpio_mode_peripheral" configurationId="p103.gpio_mode"/>
+      <configSetting altId="p104.irq0.irq01" configurationId="p104"/>
+      <configSetting altId="p104.gpio_irq.gpio_irq_enabled" configurationId="p104.gpio_irq"/>
+      <configSetting altId="p104.gpio_mode.gpio_mode_irq" configurationId="p104.gpio_mode"/>
+      <configSetting altId="p105.output.low" configurationId="p105"/>
+      <configSetting altId="p105.gpio_mode.gpio_mode_out.low" configurationId="p105.gpio_mode"/>
+      <configSetting altId="p106.output.low" configurationId="p106"/>
+      <configSetting altId="p106.gpio_mode.gpio_mode_out.low" configurationId="p106.gpio_mode"/>
+      <configSetting altId="p107.output.low" configurationId="p107"/>
+      <configSetting altId="p107.gpio_mode.gpio_mode_out.low" configurationId="p107.gpio_mode"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p109.sci9.txd" configurationId="p109"/>
+      <configSetting altId="p109.gpio_mode.gpio_mode_peripheral" configurationId="p109.gpio_mode"/>
+      <configSetting altId="p110.sci9.rxd" configurationId="p110"/>
+      <configSetting altId="p110.gpio_mode.gpio_mode_peripheral" configurationId="p110.gpio_mode"/>
+      <configSetting altId="p111.output.low" configurationId="p111"/>
+      <configSetting altId="p111.gpio_mode.gpio_mode_out.low" configurationId="p111.gpio_mode"/>
+      <configSetting altId="p112.ctsu0.tscap" configurationId="p112"/>
+      <configSetting altId="p112.gpio_mode.gpio_mode_peripheral" configurationId="p112.gpio_mode"/>
+      <configSetting altId="p113.output.low" configurationId="p113"/>
+      <configSetting altId="p113.gpio_mode.gpio_mode_out.low" configurationId="p113.gpio_mode"/>
+      <configSetting altId="p207.output.low" configurationId="p207"/>
+      <configSetting altId="p207.gpio_mode.gpio_mode_out.low" configurationId="p207.gpio_mode"/>
+      <configSetting altId="p208.output.low" configurationId="p208"/>
+      <configSetting altId="p208.gpio_mode.gpio_mode_out.low" configurationId="p208.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+      <configSetting altId="p301.sci2.scl" configurationId="p301"/>
+      <configSetting altId="p301.gpio_mode.gpio_mode_peripheral" configurationId="p301.gpio_mode"/>
+      <configSetting altId="p301.gpio_otype.gpio_otype_n_ch_od" configurationId="p301.gpio_otype"/>
+      <configSetting altId="p302.sci2.sda" configurationId="p302"/>
+      <configSetting altId="p302.gpio_mode.gpio_mode_peripheral" configurationId="p302.gpio_mode"/>
+      <configSetting altId="p302.gpio_otype.gpio_otype_n_ch_od" configurationId="p302.gpio_otype"/>
+      <configSetting altId="p303.output.low" configurationId="p303"/>
+      <configSetting altId="p303.gpio_mode.gpio_mode_out.low" configurationId="p303.gpio_mode"/>
+      <configSetting altId="p304.output.low" configurationId="p304"/>
+      <configSetting altId="p304.gpio_mode.gpio_mode_out.low" configurationId="p304.gpio_mode"/>
+      <configSetting altId="p400.sci1.sck" configurationId="p400"/>
+      <configSetting altId="p400.gpio_mode.gpio_mode_peripheral" configurationId="p400.gpio_mode"/>
+      <configSetting altId="p401.sci1.txd" configurationId="p401"/>
+      <configSetting altId="p401.gpio_mode.gpio_mode_peripheral" configurationId="p401.gpio_mode"/>
+      <configSetting altId="p402.sci1.rxd" configurationId="p402"/>
+      <configSetting altId="p402.gpio_mode.gpio_mode_peripheral" configurationId="p402.gpio_mode"/>
+      <configSetting altId="p403.sci1.cts" configurationId="p403"/>
+      <configSetting altId="p403.gpio_mode.gpio_mode_peripheral" configurationId="p403.gpio_mode"/>
+      <configSetting altId="p407.iic0.sda" configurationId="p407"/>
+      <configSetting altId="p407.gpio_mode.gpio_mode_peripheral" configurationId="p407.gpio_mode"/>
+      <configSetting altId="p408.iic0.scl" configurationId="p408"/>
+      <configSetting altId="p408.gpio_mode.gpio_mode_peripheral" configurationId="p408.gpio_mode"/>
+      <configSetting altId="p409.irq0.irq06" configurationId="p409"/>
+      <configSetting altId="p409.gpio_irq.gpio_irq_enabled" configurationId="p409.gpio_irq"/>
+      <configSetting altId="p409.gpio_mode.gpio_mode_irq" configurationId="p409.gpio_mode"/>
+      <configSetting altId="p410.output.low" configurationId="p410"/>
+      <configSetting altId="p410.gpio_mode.gpio_mode_out.low" configurationId="p410.gpio_mode"/>
+      <configSetting altId="p411.irq0.irq04" configurationId="p411"/>
+      <configSetting altId="p411.gpio_irq.gpio_irq_enabled" configurationId="p411.gpio_irq"/>
+      <configSetting altId="p411.gpio_mode.gpio_mode_irq" configurationId="p411.gpio_mode"/>
+      <configSetting altId="p501.output.low" configurationId="p501"/>
+      <configSetting altId="p501.gpio_mode.gpio_mode_out.low" configurationId="p501.gpio_mode"/>
+      <configSetting altId="p502.output.low" configurationId="p502"/>
+      <configSetting altId="p502.gpio_mode.gpio_mode_out.low" configurationId="p502.gpio_mode"/>
+      <configSetting altId="sci0.cts.p103" configurationId="sci0.cts"/>
+      <configSetting altId="sci0.mode.spi.free" configurationId="sci0.mode"/>
+      <configSetting altId="sci0.rxd.p100" configurationId="sci0.rxd"/>
+      <configSetting altId="sci0.sck.p102" configurationId="sci0.sck"/>
+      <configSetting altId="sci0.txd.p101" configurationId="sci0.txd"/>
+      <configSetting altId="sci1.cts.p403" configurationId="sci1.cts"/>
+      <configSetting altId="sci1.mode.spi.free" configurationId="sci1.mode"/>
+      <configSetting altId="sci1.rxd.p402" configurationId="sci1.rxd"/>
+      <configSetting altId="sci1.sck.p400" configurationId="sci1.sck"/>
+      <configSetting altId="sci1.txd.p401" configurationId="sci1.txd"/>
+      <configSetting altId="sci2.mode.iic.free" configurationId="sci2.mode"/>
+      <configSetting altId="sci2.scl.p301" configurationId="sci2.scl"/>
+      <configSetting altId="sci2.sda.p302" configurationId="sci2.sda"/>
+      <configSetting altId="sci9.mode.asynchronous.free" configurationId="sci9.mode"/>
+      <configSetting altId="sci9.rxd.p110" configurationId="sci9.rxd"/>
+      <configSetting altId="sci9.txd.p109" configurationId="sci9.txd"/>
+    </pincfg>
+    <pincfg active="false" name="R7FA2L1AB2DFM.pincfg" selected="false" symbol="">
+      <configSetting altId="debug0.mode.swd" configurationId="debug0.mode"/>
+      <configSetting altId="debug0.swclk.p300" configurationId="debug0.swclk"/>
+      <configSetting altId="debug0.swdio.p108" configurationId="debug0.swdio"/>
+      <configSetting altId="p108.debug0.swdio" configurationId="p108"/>
+      <configSetting altId="p108.gpio_mode.gpio_mode_peripheral" configurationId="p108.gpio_mode"/>
+      <configSetting altId="p300.debug0.swclk" configurationId="p300"/>
+      <configSetting altId="p300.gpio_mode.gpio_mode_peripheral" configurationId="p300.gpio_mode"/>
+    </pincfg>
+  </raPinConfiguration>
+</raConfiguration>

project_0/docs/Captouch板载触摸按键配置说明.md

@@ -0,0 +1,205 @@
+# Captouch板载触摸按键配置说明
+
+## 基础知识
+
+电容式感应单元(CTSU2)测量传感器的静电电容。静电电容的变化由软件来确定，使CTSU能够检测手指是否与传感器接触。传感器的电极表面通常包裹有电介质薄膜，这样手指就不会直接接触电极。
+
+如图所示，电极与周围导体之间存在静电电容(寄生电容)。由于人体是电导体，当手指靠近电极时，静电电容值会增大。
+
+![image-20220802110717583](picture/captouch1.png) 
+
+静电电容的检测采用自电容法和互电容法。在自电容法中，CTSU检测手指和单电极之间产生的静电电容。在互容法中，使用两个电极，一个作为传输电极，另一个作为接收电极，CTSU检测当手指靠近这两个电极时产生的静电电容的变化。
+
+![image-20220802111936905](picture/captouch2.png) 
+
+接下来一起尝试在CPK-RA2L1这块开发板上如何使用触摸按键。
+
+## FSP配置
+
+首先是FSP配置。打开MDK的project工程，通过阅读README的FSP配置部分已经安装了FSP配置工具，并且在MDK中也添加了FSP的打开方式。
+
+先打开FSP配置工具，移至“**Pins**”选项卡并打开 “**Peripherals**”条目。 在外围设备列表中，滚动到“**Input: CTSU**” 。打开配置并确保CTSU0 如下所示。 
+
+![image-20220802113049978](picture/captouch3.png) 
+
+### 创建CapTouch
+
+然后，转到“**Stacks**”选项卡。首先，我们需要添加用于连接到触摸按键的模块。在“**HAL/Common Stacks**”窗格上，单击“**New Stack**”，然后选择“**CapTouch**”->“**Touch (rm_touch)**”。
+
+![image-20220802114613066](picture/captouch4.png) 
+
+选中创建出的rm_touch，在配置中开启UART的Tuning和monitoring功能。
+
+![image-20220802115356241](picture/captouch5.png) 
+
+添加UART端口用于调制过程。
+
+![image-20220803110210310](picture/captouch6.png) 
+
+### 添加UART端口
+
+选中创建出的UART，这里使用UART 0来作为调制串口，如果需要使用其他串口可手动修改channel数值。
+
+![image-20220803114356569](picture/captouch7.png) 
+
+默认的SCI0可能是SPI，需要将SCI0使用的模式修改为UART。
+
+![image-20220803114511416](picture/captouch8.png) 
+
+回到stacks标签页，打开UART端口的DTC功能，并添加DTC。
+
+![image-20220803114731495](picture/captouch9.png) 
+
+为UART的rx和tx添加DTC支持。
+
+![image-20220803114819813](picture/captouch10.png) 
+
+添加完成的效果如图所示。
+
+![image-20220803114919483](picture/captouch11.png) 
+
+### 配置r_ctsu
+
+接着选中r_ctsu，同样打开DTC功能，并添加DTC配置。
+
+![image-20220803115033965](picture/captouch12.png) 
+
+![image-20220803115133548](picture/captouch13.png) 
+
+配置完成后点击生成配置代码并将库文件加入工程。
+
+![image-20220803115205206](picture/captouch14.png) 
+
+### 编译工程
+
+关闭FSP 编译MDK工程，第一次编译出现弹窗确认后再次编译即可。编译通过可进行后续步骤。
+
+![image-20220803134930532](picture/captouch15.png) 
+
+此时FSP的配置就完成了，接下来需要使用到瑞萨 QE for Capacitive Touch 工具。
+
+## QE for Capacitive Touch配置
+
+[QE工具下载地址](https://www.renesas.com/cn/zh/software-tool/qe-capacitive-touch-development-assistance-tool-capacitive-touch-sensors) 下载最新版本的QE for Capacitive Touch。
+
+![image-20220803142500065](picture/captouch16.png) 
+
+下载完成后解压，注意解压的路径不能有中文。解压出的文件如下所示。
+
+![image-20220803143218409](picture/captouch17.png) 
+
+进入目录 eclipse，找到qe-touch.exe双击打开。
+
+![image-20220803143307233](picture/captouch18.png) 
+
+主窗口如图所示，这里显示了QE工具使用的操作步骤，我们跟着这些步骤完成触摸按键的调制过程。最终可以实时监控按键的运行状态。
+
+![image-20220803144721954](picture/captouch19.png) 
+
+### 第一步准备工作
+
+选择工程目录，这里选择ra2l1-cpk的BSP工程目录。
+
+![image-20220803145816770](picture/captouch20.png) 
+
+![image-20220803145832333](picture/captouch21.png) 
+
+然后选择芯片信号，注意看清楚使用的芯片型号和工具中选择的型号要对应。
+
+![image-20220803150443690](picture/captouch22.png) 
+
+### 第二步创建配置
+
+选择*“**Create a new configuration**”*（创建新配置）来创建新的触摸配置。
+
+![image-20220803150603024](picture/captouch23.png) 
+
+这将打开一个新菜单窗口，显示用于创建触摸界面的默认空白画布。从画布右侧选择 *“**Button**”*（按钮）菜单项并将光标移动到画布上，将按钮添加到画布。单击鼠标左键放下按钮图标。通过向画布添加另外两个按钮来完成配置。 添加所有三个按钮后，按 ESC 键退出。 画布将类似于下图。
+
+此时，画布下方会显示 RED X 及文本*“**There are some problems with setting**”*（设置存在一些问题）。这表明画布上的按钮没有绑定到任何 MCU 传感器引脚。 按钮（以及其他已添加了的组件）也将显示为红色，这表明它们的配置存在问题。
+
+要在传感器焊盘和物理触摸通道引脚之间建立连接，需双击 Button00，此时将出现一个对话框。通过下拉菜单和鼠标选择 TS32 作为 MCU 传感器以分配给该按钮。 
+
+![	](picture/captouch24.png) 
+
+触摸按钮配置完成后需要修改下文件名称，默认的文件名称存在不支持的字符。完成这些步骤就可以单击对话框中的*“**Create**”*（创建）配置。
+
+![image-20220803152119579](picture/captouch25.png) 
+
+接着选择输出配置文件，输出路径请选择`ra2l1-cpk/QE-Touch`目录。弹出的弹窗根据实际的情况选择配置。
+
+![image-20220803152648669](picture/captouch26.png) 
+
+![image-20220803152701419](picture/captouch27.png) 
+
+![image-20220803152715716](picture/captouch28.png) 
+
+完成此步配置后将输出如中所示的配置文件和sample代码文件。
+
+![image-20220803154102544](picture/captouch29.png) 
+
+在此目录中已经准备了一份能在RT-Thread系统中运行sample代码。在ENV工具中执行`scons --target=mdk5`命令生成MDK工程并将刚刚的配置文件和sample文件加入到工程中。
+
+![image-20220803154630457](picture/captouch30.png) 
+
+打开创建的MDK工程并编译，然后进入debug。jlink可能会弹出选择芯片信号的窗口，输入`r7fa2l1ab`选中点击OK即可进入。
+
+![image-20220803155646859](picture/captouch_jlink.png) 
+
+在MDK的debug中点击run按钮全速运行程序。
+
+![image-20220804141317303](picture/captouch_dbg.png) 
+
+可以看到命令行打印出日志信息，touch功能的sample已启动。
+
+![image-20220803155821105](picture/captouch_msh.png) 
+
+### 第三步Tuning
+
+回到QE工具启动Tuning过程。使用了UART0端口(P100、P101)，需要使用到USB-TTL工具连接电脑。
+
+![image-20220804140317043](picture/captouch_tuning0.png) 
+
+ ![image-20220803152701419](picture/captouch27.png)
+
+![image-20220803152715716](picture/captouch28.png) 
+
+等待自动调节过程，此过程时间可能较长请勿触碰触摸按键。
+
+![image-20220804104724939](picture/captouch_tuning.png) 
+
+注意：经过几个自动化步骤后，您将看到包含如下所示信息的对话框。 这是 Tuning（调节）过程的触摸灵敏度测试步骤。您可以看到传入的“触摸计数”，即在传感器上看到的电容。 如果触摸板上的传感器（此时为 BTN3、TS28），将会使条形图和触摸计数增加，这是因为我们正在更改/增加触摸传感器的电容而导致的计数上升。且 Tuning（调节）总是从最低传感器编号到最高传感器编号进行。
+
+您需要在电极板 （BTN3/TS28）上的传感器上使用**一般的触摸力度**。当按下板上 BTN1 位置时，便会看到进度条向右进展，同时触摸计数也在增加。保持按压并点击电脑键盘上的任意键(如空格)以记录测量结果。示例如下所示。 测量结果将因显示的计数而异。对按钮 BTN1 和 BTN2 重复此过程。
+
+![image-20220804105539784](picture/captouch_tuning1.png) 
+
+完成后，您将看到如下所示的界面。理想情况下，使用此硬件应该会看到 1000 次或更多计数的触摸阈值。这是中间件用来确定是否发生触摸事件的检测阈值。
+
+注意：在 Tuning（调节）过程中您可能会收到“寄生电容< 10pF”的警告。如果发生这种情况，请选中选择目标框并单击重试以尝试重新 Tuning（调节）该传感器。要注意的是，要使 CTSU/CTSU2 IP 实现最佳性能，至少需要 10pF 的负载电容。低于 10pF 的负载会导致该传感器通道上的噪声敏感。
+
+![image-20220804105830232](picture/captouch_tuning2.png) 
+
+单击对话框中的*“**Continue the Tuning Process**”*（继续调节）按钮。 这将退出 Tuning（调节）过程并与目标上的调试会话断开连接。
+
+![image-20220804110018273](picture/captouch_tuning3.png) 
+
+按钮调试完成输出Tuning（调节）参数文件。单击按钮*“**Output Parameter Files**”*（输出参数文件）。部分配置代码有更新，**需要重新编译工程。然后再次更新固件**。
+
+![image-20220804110107072](picture/captouch_tuning4.png) 
+
+### 第四步连接并监控状态
+
+使用UART连接开发板监控触摸按键状态。
+
+![image-20220804113515382](picture/captouch_tuning5.png) 
+
+连接成功的界面如下所示，可以点击左上角的*“**Enable Monitoring**”*开始监测。
+
+在主窗口切换视图到 CapTouch Status Chart (QE) 可以监控图形触摸灵敏度，看到所选触摸传感器的当前计数值、参考值、阈值以及触摸传感器是打开还是关闭状态。
+
+左下的窗口可以通过下拉菜单选择按键名称，可以通过 CapTouch Multi Status Chart (QE) 视图同时查看多个传感器以评估串扰等性能。
+
+![image-20220804114016844](picture/captouch_monitoring.png) 
+
+同时在按下按钮时开发板上的蓝色LED灯会常亮，抬起则熄灭。

project_0/docs/LPM低功耗配置说明.md

@@ -0,0 +1,324 @@
+# LPM低功耗配置说明
+
+## 基础知识
+
+低功耗的本质是系统空闲时 CPU 停止工作，中断或事件唤醒后继续工作。在 RTOS 中，通常包含一个 IDLE 任务，该任务的优先级最低且一直保持就绪状态，当高优先级任务未就绪时，OS 执行 IDLE 任务。一般地，未进行低功耗处理时，CPU 在 IDLE 任务中循环执行空指令。RT-Thread 的电源管理组件在 IDLE 任务中，通过对 CPU 、时钟和设备等进行管理，从而有效降低系统的功耗。
+
+![PM工作原理](picture/pm_ostick.png) 
+
+在上图所示，当高优先级任务运行结束或被挂起时，系统将进入 IDLE 任务中。在 IDLE 任务执行后，它将判断系统是否可以进入到休眠状态（以节省功耗）。如果可以进入休眠， 将根据芯片情况关闭部分硬件模块，OS Tick 也非常有可能进入暂停状态。此时电源管理框架会根据系统定时器情况，计算出下一个超时时间点，并设置低功耗定时器，让设备能够在这个时刻点唤醒，并进行后续的工作。当系统被（低功耗定时器中断或其他唤醒中断源）唤醒后，系统也需要知道睡眠时间长度是多少，并对OS Tick 进行补偿，让系统的OS tick值调整为一个正确的值。
+
+### [PM组件](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/pm/pm)
+
+PM组件是RT-Thread系统中针对电源管理而设计的基础功能组件， 组件采用分层设计思想，分离架构和芯片相关的部分，提取公共部分作为核心。支持多种运行模式和休眠模式的管理切换，以及低功耗定时器的管理。
+
+PM 组件有以下特点：
+
+- PM 组件是基于模式来管理功耗
+- PM 组件可以根据模式自动更新设备的频率配置，确保在不同的运行模式都可以正常工作
+- PM 组件可以根据模式自动管理设备的挂起和恢复，确保在不同的休眠模式下可以正确的挂起和恢复
+- PM 组件支持可选的休眠时间补偿，让依赖 OS Tick 的应用可以透明使用
+- PM 组件向上层提供设备接口，如果使用了设备文件系统组件，那么也可以用文件系统接口来访问
+
+PM组件支持的休眠模式有：
+
+| 模式                   |             描述                     |
+| -------------------- | ---------------------------------- |
+| PM_SLEEP_MODE_NONE     | 系统处于活跃状态，未采取任何的降低功耗状态  |
+| PM_SLEEP_MODE_IDLE     | **空闲模式**，该模式在系统空闲时停止 CPU 和部分时钟，任意事件或中断均可以唤醒 |
+| PM_SLEEP_MODE_LIGHT    | **轻度睡眠模式**，CPU 停止，多数时钟和外设停止，唤醒后需要进行时间补偿 |
+| PM_SLEEP_MODE_DEEP     | **深度睡眠模式**，CPU 停止，仅少数低功耗外设工作，可被特殊中断唤醒 |
+| PM_SLEEP_MODE_STANDBY  | **待机模式**，CPU 停止，设备上下文丢失(可保存至特殊外设)，唤醒后通常复位 |
+| PM_SLEEP_MODE_SHUTDOWN | **关断模式**，比 Standby 模式功耗更低， 上下文通常不可恢复， 唤醒后复位 |
+
+### RA系列LPM功能
+
+RA2 MCU支持的LPM类型有:
+
+- Sleep mode
+- Software Standby mode 
+- Snooze mode 
+
+| 休眠模式                | 描述                                                         |
+| ----------------------- | ------------------------------------------------------------ |
+| LPM_MODE_SLEEP          | **睡眠模式**，CPU停止工作，但其内部寄存器的内容被保留。其他外围功能在单片机中不停止。休眠模式下可用的复位或中断会导致MCU取消休眠模式。在这种模式下，所有的中断源都可用来取消Sleep模式。 |
+| LPM_MODE_STANDBY        | **软件待机模式**，CPU、大部分片上外设功能和振荡器停止运行。但是，CPU内部寄存器的内容和SRAM数据、芯片上外围功能的状态和I/O端口状态都被保留。软件待机模式可以显著降低功耗，因为大多数振荡器在这种模式下停止。 |
+| LPM_MODE_STANDBY_SNOOZE | **小睡模式**，是软件待机模式的扩展，在这种模式下，有限的外设模块可以在不唤醒CPU的情况下运行。通过配置中断源，可以通过软件待机模式进入小睡模式。类似地，系统可以通过snooze模式支持的中断从snooze模式中唤醒。 |
+
+低功耗模式转换和触发源如图所示。
+
+![image-20220705161631226](picture/lpm_mode.png)
+
+不同模式间的切换如图所示，从图中也可以看出三种模式的功耗关系是Sleep>Snooze>Standby。
+
+RA2芯片的休眠模式对应PM组件的模式关系：
+
+| RA2芯片                 | PM组件                |
+| ----------------------- | --------------------- |
+| LPM_MODE_SLEEP          | PM_SLEEP_MODE_IDLE    |
+| LPM_MODE_STANDBY        | PM_SLEEP_MODE_DEEP    |
+| LPM_MODE_STANDBY_SNOOZE | PM_SLEEP_MODE_STANDBY |
+
+
+## 配置LPM功能
+
+要使用RA2系列芯片的LPM功能，需要进入bsp\renesas\ra2l1-cpk目录。
+
+- 在menuconfig中使能LPM驱动，并勾选要开启的休眠模式，然后保存配置，生成MDK5工程。
+
+![image-20220705172537997](picture/lpm_config.png)
+
+- 打开PM组件和驱动后，需要增加idle的线程栈大小，可改为1024。
+
+![image-20220708183500091](picture/lpm_idle.png) 
+
+- 打开生成的MDK5工程project.uvprojx，然后打开FSP配置工具添加LPM相关配置。下图是需要添加的stack，包括三种LPM模式的配置以及低功耗定时器AGT1。
+
+![image-20220705183404587](picture/lpm_config1.png)
+
+- 创建LPM如下图所示新建r_lpm，**需要根据使用的模式进行配置且不同模式要创建不同的r_lpm**。下面将分别介绍三种不同模式的配置，创建步骤就不再赘述。
+
+![image-20220705185012409](picture/lpm_config2.png) 
+
+### Sleep mode休眠模式
+
+创建出r_lpm后需要修改Name和Low Power Mode这两个配置项。Name需要改为g_lpm_sleep，因为在驱动文件中已经定义了sleep模式对应的stack名称。Low Power Mode选择Sleep mode即可。
+
+![image-20220705185611562](picture/lpm_config3.png) 
+
+### Standby mode软件待机模式
+
+Name需要改为g_lpm_sw_standby。Low Power Mode选择Software Standby mode即可。
+
+另外在此模式下还需要配置唤醒MCU的中断源，因为会使用到AGT1做为低功耗定时器所以AGT1的中断需要勾选。如果在应用中还需要其他中断源在此模式下唤醒MCU，则勾选对应选项即可。
+
+![image-20220705185734682](picture/lpm_config4.png) 
+
+### Snooze mode小睡模式
+
+Name需要改为g_lpm_sw_standby_with_snooze。Low Power Mode选择Snooze mode即可。
+
+另外在此模式下同样要配置唤醒MCU的中断源，因为会使用到AGT1做为低功耗定时器所以AGT1的中断需要勾选。如果在应用中还需要其他中断源在此模式下唤醒MCU，则勾选对应选项即可。
+
+![image-20220705185903034](picture/lpm_config5.png) 
+
+### AGT1低功耗定时器
+
+在驱动中使用了MCU的AGT1做为PM组件的低功耗定时器，用于在休眠状态下的系统时钟补偿。
+
+![image-20220706140137904](picture/lpm_config6.png) 
+
+完成上述配置步骤就已经把LPM低功耗模式的相关配置做完了。然后再根据应用要实现的功能配置其他外设。
+
+
+## 低功耗DEMO
+
+上文介绍了在RT-Thread的RA2L1上怎么配置LPM的不同模式，接下来就用一个小DEMO来验证下MCU在各种模式下的工作情况。
+
+低功耗DEMO要实现的功能是，在CPK-RA2L1开发板上用S1按钮切换不同的低功耗模式，并在msh中打印出模式切换的提示信息。要实现这个功能需要在刚才的基础上添加一个低功耗的唤醒源。
+
+### 添加配置
+
+- 创建IRQ中断，IRQ中断选择通道3，详细配置如下。
+
+![image-20220706180228630](picture/lpm_demo1.png) 
+
+![image-20220706180613033](picture/lpm_demo3.png) 
+
+![image-20220706180438089](picture/lpm_demo2.png) 
+
+- 在刚才的Snooze和Standby模式的配置里添加IRQ3的唤醒源
+
+![image-20220706181018705](picture/lpm_demo5.png) 
+
+![image-20220706180846002](picture/lpm_demo4.png) 
+
+- 然后保存并生成配置代码。
+
+### 添加测试代码
+
+```c
+#include <rtthread.h>
+
+#ifdef BSP_USING_LPM
+#include <rtdevice.h>
+#include <board.h>
+#include <drivers/pm.h>
+
+#define WAKEUP_APP_THREAD_STACK_SIZE        512
+#define WAKEUP_APP__THREAD_PRIORITY         RT_THREAD_PRIORITY_MAX / 3
+#define WAKEUP_EVENT_BUTTON                 (1 << 0)
+
+static rt_event_t wakeup_event;
+
+#define USER_INPUT  "P004"
+#define LED2_PIN    "P501" /* Onboard LED pins */
+
+void rt_lptimer_init(rt_lptimer_t  timer,
+                   const char *name,
+                   void (*timeout)(void *parameter),
+                   void       *parameter,
+                   rt_tick_t   time,
+                   rt_uint8_t  flag);
+
+rt_err_t rt_lptimer_detach(rt_lptimer_t timer);
+rt_err_t rt_lptimer_start(rt_lptimer_t timer);
+rt_err_t rt_lptimer_stop(rt_lptimer_t timer);
+
+rt_err_t rt_lptimer_control(rt_lptimer_t timer, int cmd, void *arg);
+
+static struct rt_lptimer lptimer; 
+
+static void timeout_cb(void *parameter)
+{
+    rt_interrupt_enter();
+    rt_kprintf("\n lptimer callback \n");
+    rt_interrupt_leave();
+}
+
+static void lptimer_init(void)
+{
+    rt_lptimer_init(&lptimer,
+                    "lpm",
+                    timeout_cb,
+                    (void*)&wakeup_event,
+                    1000,
+                    RT_TIMER_FLAG_PERIODIC);
+}
+
+static void lptimer_stop(void)
+{
+    rt_lptimer_stop(&lptimer);
+}
+
+static void lptimer_start(void)
+{
+    rt_lptimer_start(&lptimer);
+}
+
+static void led_app(void)
+{
+    static uint8_t key_status = 0x00;
+    rt_uint32_t led2_pin = rt_pin_get(LED2_PIN);
+
+    rt_pin_write(led2_pin, PIN_HIGH);
+    switch(key_status%4)
+    {
+    case 0:/* IDLE */
+		lptimer_stop();
+        rt_pm_release(PM_SLEEP_MODE_NONE);
+        rt_kprintf("\trequest:IDLE\n");
+        rt_pm_request(PM_SLEEP_MODE_IDLE);
+        break;
+    case 1:/* DEEP */
+		lptimer_stop();
+		lptimer_start();
+        rt_pm_release(PM_SLEEP_MODE_IDLE);
+        rt_kprintf("\trequest:DEEP\n");
+        rt_pm_request(PM_SLEEP_MODE_DEEP);
+        break;
+    case 2:/* STANDBY */
+		lptimer_stop();
+		lptimer_start();
+        rt_pm_release(PM_SLEEP_MODE_DEEP);
+        rt_kprintf("\trequest:STANDBY\n");
+        rt_pm_request(PM_SLEEP_MODE_STANDBY);
+        break;
+    case 3:/* NONE */
+		lptimer_stop();
+        rt_pm_release(PM_SLEEP_MODE_STANDBY);
+        rt_kprintf("\trequest:NONE\n");
+        rt_pm_request(PM_SLEEP_MODE_NONE);
+        break;
+    default:
+        break;
+    }
+
+    key_status++;
+    rt_pin_write(led2_pin, PIN_LOW);
+}
+
+static void wakeup_callback(void* p)
+{
+    rt_event_send(wakeup_event, WAKEUP_EVENT_BUTTON);
+}
+
+void wakeup_sample(void)
+{
+    /* init */
+    rt_uint32_t pin = rt_pin_get(USER_INPUT);
+    rt_kprintf("\n pin number : 0x%04X \n", pin);
+    rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, wakeup_callback, RT_NULL);
+    if (RT_EOK != err)
+    {
+        rt_kprintf("\n attach irq failed. \n");
+    }
+    err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
+    if (RT_EOK != err)
+    {
+        rt_kprintf("\n enable irq failed. \n");
+    }
+}
+
+static void wakeup_init(void)
+{
+    wakeup_event = rt_event_create("wakup", RT_IPC_FLAG_FIFO);
+    RT_ASSERT(wakeup_event != RT_NULL);
+    wakeup_sample();
+}
+
+static void pm_mode_init(void)
+{
+    rt_pm_release_all(RT_PM_DEFAULT_SLEEP_MODE);
+    rt_pm_request(PM_SLEEP_MODE_NONE);
+}
+
+void pm_test_entry(void* para)
+{
+    /* 唤醒回调函数初始化 */
+	wakeup_init();
+
+    /* 电源管理初始化 */
+    pm_mode_init();
+
+	lptimer_init();
+	
+    while (1)
+    {
+        /* 等待唤醒事件 */
+        if (rt_event_recv(wakeup_event,
+                            WAKEUP_EVENT_BUTTON,
+                            RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR,
+                            RT_WAITING_FOREVER, RT_NULL) == RT_EOK)
+        {
+            led_app();
+        }
+    }
+}
+
+int pm_test(void)
+{
+
+    rt_thread_t tid = rt_thread_create(
+            "pmtest",pm_test_entry,RT_NULL,512,10,10);
+    if(tid)
+        rt_thread_startup(tid);
+
+    return 0;
+}
+MSH_CMD_EXPORT(pm_test, pm_test);
+// INIT_APP_EXPORT(pm_test);
+#endif
+```
+
+将DEMO代码加入到工程中，可以直接添加到hal_entry.c或新建一个源文件。
+
+
+### 测试验证
+
+然后编译下载。开发板连接串口工具，输入`pm_test`命令启动测试DEMO。
+
+按下S1按钮切换工作模式，在DEEP、STANDBY模式下会启动低功耗定时器，当定时唤醒后会打印出回调接口的提示信息。
+
+![image-20220706183705384](picture/lpm_demo6.png) 
+