修复wifi示例使用硬件i2c出现hardfault

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S

@@ -113,7 +113,7 @@ __Vectors:
     .equ    __VectorsSize, . - __Vectors
 
     .section .ram_vectors
-    .align 2
+    .align 3
     .globl __ramVectors
 __ramVectors:
     .space  __VectorsSize
@@ -228,10 +228,10 @@ Reset_Handler:
 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
 /*  Multiple sections scheme.
  *
- *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  Between symbol address __zero_table_start__ and __zero_table_end__,
  *  there are array of tuples specifying:
  *    offset 0: Start of a BSS section
- *    offset 4: Size of this BSS section. Must be multiply of 4
+ *    offset 4: Size of this BSS section. Must be multiple of 4
  */
     ldr    r3, =__zero_table_start__
     ldr    r4, =__zero_table_end__

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/COMPONENT_CM0P/system_psoc6_cm0plus.c

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm0plus.c
-* \version 2.95.1
+* \version 2.100
 *
 * The device system-source file.
 *
@@ -30,6 +30,587 @@
 #include "cy_sysclk.h"
 #include "cy_wdt.h"
 
+#if (defined(CY_DEVICE_TVIIBE))
+#include "cmsis_compiler.h"
+
+#include "tviibe_partition.h"
+
+#define CY_SYS_CM4_PWR_CTL_KEY_OPEN  (0x05FAUL)
+#define CY_SYS_CM4_PWR_CTL_KEY_CLOSE (0xFA05UL)
+#define CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR  (0x000003FFUL)
+
+static void EnableEcc(void);
+static void PrepareSystemCallInfrastructure(void);
+
+extern uint32_t Cy_u32StartupStackStartAddress;
+extern uint32_t Cy_u32StartupStackEndAddress;
+extern cy_israddress __ramVectors[];
+
+/* Interrupt Logic */
+
+static void SystemIrqInit(void);
+void Cy_DefaultUserHandler(void);
+
+#define DEFAULT_HANDLER_NAME Cy_DefaultUserHandler
+
+CY_NOINIT cy_israddress Cy_SystemIrqUserTable[CPUSS_SYSTEM_INT_NR] ;
+CY_NOINIT cy_israddress * Cy_SysInt_SystemIrqUserTableRamPointer ;
+__STATIC_FORCEINLINE void CM0_CpuIntr_Handler(uint8_t intrNum);
+
+/*******************************************************************************
+* SystemCoreClockUpdate()
+*******************************************************************************/
+
+/** Default HFClk frequency in Hz */
+#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT       (8000000UL)
+
+/** Default PeriClk frequency in Hz */
+#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT      (8000000UL)
+
+/** Default system core frequency in Hz */
+#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT       (100000000UL)
+
+/** Holds the CLK_SLOW(Cortex-M0+) or CLK_FAST0(Cortex-M7_0) or CLK_FAST(Cortex-M7_1) system core clock */
+CY_NOINIT uint32_t SystemCoreClock ;
+
+/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_Hfclk0FreqHz ;
+
+/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_PeriClkFreqHz ;
+
+/** Holds the AHB frequency. Updated by \ref SystemCoreClockUpdate(). */
+CY_NOINIT uint32_t cy_AhbFreqHz ;
+
+/*******************************************************************************
+* SystemCoreClockUpdate (void)
+*******************************************************************************/
+
+/* Do not use these definitions directly in your application */
+#define CY_DELAY_MS_OVERFLOW_THRESHOLD  (0x8000u)
+#define CY_DELAY_1K_THRESHOLD           (1000u)
+#define CY_DELAY_1K_MINUS_1_THRESHOLD   (CY_DELAY_1K_THRESHOLD - 1u)
+#define CY_DELAY_1M_THRESHOLD           (1000000u)
+#define CY_DELAY_1M_MINUS_1_THRESHOLD   (CY_DELAY_1M_THRESHOLD - 1u)
+
+CY_NOINIT uint32_t cy_delayFreqKhz ;
+CY_NOINIT uint8_t  cy_delayFreqMhz ;
+
+
+/*****************************************************************************
+* Global variable definitions (declared in header file with 'extern')
+*****************************************************************************/
+// CAUTION: Static or global initialized and non-const variables will not have their init value yet!
+
+
+#define SRAM_BEGIN_ADDR                     (BASE_SRAM_CM0P)
+#define SRAM_END_ADDR                       (CY_SRAM_BASE + CY_SRAM_SIZE)
+#define STARTUP_STACK_OFFSEST               (0x100) /* 32 2-words are cleaned by startup */
+
+#define ECC_INIT_WIDTH_BYTES                8
+#define SROM_VECTOR_TABLE_BASE_ADDRESS      0x00000000
+#define VECTOR_TABLE_OFFSET_IRQ0            0x40
+#define VECTOR_TABLE_OFFSET_IRQ1            0x44
+
+#if defined(__ARMCC_VERSION)
+extern unsigned int Image$$ARM_LIB_STACK$$ZI$$Limit;            /* for (default) One Region model */
+extern void __main(void);
+#elif defined (__GNUC__)
+extern unsigned int __StackTop;
+#elif defined (__ICCARM__)
+extern unsigned int CSTACK$$Limit;                      /* for (default) One Region model */
+#endif
+
+/******************************************************************************/
+
+/*******************************************************************************
+* Function Name: Cy_DefaultUserHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU attempts to call IRQ that has not been mapped to user functions.
+*
+*******************************************************************************/
+void Cy_DefaultUserHandler(void)
+{
+    // This IRQ occurred because CPU attempted to call IRQ that has not been mapped to user function
+    while(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux0_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux0_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(0);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux1_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt0 occurs.
+*
+*******************************************************************************/
+void NvicMux1_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(1);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux2_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt2 occurs.
+*
+*******************************************************************************/
+void NvicMux2_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(2);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux3_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt3 occurs.
+*
+*******************************************************************************/
+void NvicMux3_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(3);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux4_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt4 occurs.
+*
+*******************************************************************************/
+void NvicMux4_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(4);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux5_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt5 occurs.
+*
+*******************************************************************************/
+void NvicMux5_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(5);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux6_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt6 occurs.
+*
+*******************************************************************************/
+void NvicMux6_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(6);
+}
+
+/*******************************************************************************
+* Function Name: NvicMux7_IRQHandler
+****************************************************************************//**
+*
+* The Handler is called when the CPU interrupt7 occurs.
+*
+*******************************************************************************/
+void NvicMux7_IRQHandler(void)
+{
+    CM0_CpuIntr_Handler(7);
+}
+
+/*******************************************************************************
+* Function Name: CM0_CpuIntr_Handler
+****************************************************************************//**
+*
+* The Inline handler for CPU interrupt.
+* The system interrupt mapped to CPU interrupt will be fetched and executed
+*
+*******************************************************************************/
+__STATIC_FORCEINLINE void CM0_CpuIntr_Handler(uint8_t intrNum)
+{
+    uint32_t system_int_idx;
+    cy_israddress handler;
+
+    if((_FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID, CPUSS_CM0_INT_STATUS[intrNum])))
+    {
+        system_int_idx = _FLD2VAL(CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX, CPUSS_CM0_INT_STATUS[intrNum]);
+        handler = Cy_SystemIrqUserTable[system_int_idx];
+        if(handler != NULL)
+        {
+            handler(); // jump to system interrupt handler
+        }
+    }
+    else
+    {
+        // Triggered by software or because software cleared a peripheral interrupt flag but did not clear the pending flag at NVIC
+    }
+    NVIC_ClearPendingIRQ((IRQn_Type)intrNum);
+}
+
+/*******************************************************************************
+* Function Name: SystemIrqInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void SystemIrqInit(void)
+{
+    for (int i=0; i<(int)CPUSS_SYSTEM_INT_NR; i++)
+    {
+        Cy_SystemIrqUserTable[i] = DEFAULT_HANDLER_NAME;
+    }
+
+    Cy_SysInt_SystemIrqUserTableRamPointer = Cy_SystemIrqUserTable;
+}
+
+/** Define an abstract type for the chosen ECC initialization granularity */
+typedef uint64_t ecc_init_width_t;
+
+/* Provide empty __WEAK implementation for the low-level initialization
+   routine required by the RTOS-enabled applications.
+   clib-support library provides FreeRTOS-specific implementation:
+   https://github.com/Infineon/clib-support */
+void cy_toolchain_init(void);
+__WEAK void cy_toolchain_init(void)
+{
+}
+
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+/* GCC: newlib crt0 _start executes software_init_hook.
+   The cy_toolchain_init hook provided by clib-support library must execute
+   after static data initialization and before static constructors. */
+void software_init_hook();
+void software_init_hook()
+{
+    cy_toolchain_init();
+}
+#elif defined(__ICCARM__)
+/* Initialize data section */
+void __iar_data_init3(void);
+
+/* Call the constructors of all global objects */
+void __iar_dynamic_initialization(void);
+
+#else
+/**/
+#endif /* defined(__GNUC__) && !defined(__ARMCC_VERSION) */
+
+
+void CyMain(void)
+{
+#if defined(__ICCARM__)
+    /* Initialize data section */
+    __iar_data_init3();
+
+    /* Initialization hook for RTOS environment  */
+    cy_toolchain_init();
+
+    /* Call the constructors of all global objects */
+    __iar_dynamic_initialization();
+#endif
+
+    __PROGRAM_START();
+}
+
+
+/******************************************************************************/
+// TVIIBE SystemInit
+void SystemInit(void)
+{
+    /* Startup Init */
+    EnableEcc();
+    PrepareSystemCallInfrastructure();
+    /* Startup Init Done */
+
+    Cy_PDL_Init(CY_DEVICE_CFG);
+    Cy_WDT_Unlock();
+    Cy_WDT_Disable();
+
+    // Call custom user system init function (assuming weak ref was overridden by user)
+    Cy_SystemInit();
+    SystemCoreClockUpdate();
+
+    SystemIrqInit();
+}
+
+
+/*******************************************************************************
+* Function Name: EnableEcc
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+static void EnableEcc(void)
+{
+    /* Enable ECC checking in SRAM controllers again (had been switched off by assembly startup code) */
+    CPUSS->RAM0_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#if (CPUSS_RAMC1_PRESENT == 1u)
+    CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+#if (CPUSS_RAMC2_PRESENT == 1u)
+    CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */
+#endif
+}
+
+
+/**
+ *****************************************************************************
+ ** Prepares necessary settings to get SROM system calls working
+ **
+ ** \return none
+ *****************************************************************************/
+static void PrepareSystemCallInfrastructure(void)
+{
+    const uint8_t u8Irq0Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ0 / 4);
+    const uint8_t u8Irq1Index = (uint8_t) (VECTOR_TABLE_OFFSET_IRQ1 / 4);
+    uint32_t * const pu32RamTable   = (uint32_t *) __ramVectors;
+    uint32_t * const pu32SromTable  = (uint32_t *) SROM_VECTOR_TABLE_BASE_ADDRESS;
+
+    // Use IRQ0 and IRQ1 handlers from SROM vector table
+    pu32RamTable[u8Irq0Index] = pu32SromTable[u8Irq0Index];
+    pu32RamTable[u8Irq1Index] = pu32SromTable[u8Irq1Index];
+
+    NVIC_SetPriority(NvicMux0_IRQn, 1);
+    NVIC_SetPriority(NvicMux1_IRQn, 0);
+    NVIC_EnableIRQ(NvicMux0_IRQn);
+    NVIC_EnableIRQ(NvicMux1_IRQn);
+
+    // Only item left is clearing of PRIMASK:
+    // This should be done by the application at a later point in time (e.g. in main())
+}
+
+/*******************************************************************************
+* Function Name: Cy_SystemInit
+****************************************************************************//**
+*
+* The function is called during device startup.
+*
+*******************************************************************************/
+__WEAK void Cy_SystemInit(void)
+{
+     /* Empty weak function. The actual implementation to be in the app
+      * generated strong function.
+     */
+}
+
+/*******************************************************************************
+* Function Name: SystemCoreClockUpdate
+****************************************************************************//**
+*
+* Gets core clock frequency and updates \ref SystemCoreClock.
+*
+* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref
+* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles().
+*
+*******************************************************************************/
+void SystemCoreClockUpdate (void)
+{
+    /* Get frequency for the high-frequency clock*/
+    cy_Hfclk0FreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_CORE_HF_PATH_NUM);
+
+    /* The CM0P core's clock source is the slow clock. */
+    SystemCoreClock = Cy_SysClk_ClkSlowGetFrequency();
+
+    /* Get Peripheral clock Frequency*/
+    cy_PeriClkFreqHz = Cy_SysClk_ClkHfGetFrequency(CY_SYSCLK_CLK_PERI_HF_PATH_NUM);
+
+    /* Sets clock frequency for Delay API */
+    cy_delayFreqMhz = (uint32_t)((SystemCoreClock + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD);
+    cy_delayFreqKhz = (SystemCoreClock + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD;
+
+    /* Get the frequency of AHB source, CLK HF0 is the source for AHB*/
+    cy_AhbFreqHz = Cy_SysClk_ClkHfGetFrequency(0UL);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysGetCM4Status
+****************************************************************************//**
+*
+* Returns the Cortex-M4 core power mode.
+*
+* \return \ref group_system_config_cm4_status_macro
+*
+*******************************************************************************/
+uint32_t Cy_SysGetCM4Status(void)
+{
+    uint32_t regValue;
+
+    /* Get current power mode */
+    regValue = CPUSS->CM4_PWR_CTL & CPUSS_CM4_PWR_CTL_PWR_MODE_Msk;
+
+    return (regValue);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysEnableCM4
+****************************************************************************//**
+*
+* Sets vector table base address and enables the Cortex-M4 core.
+*
+* \note If the CPU is already enabled, it is reset and then enabled.
+*
+* \param vectorTableOffset The offset of the vector table base address from
+* memory address 0x00000000. The offset should be multiple to 1024 bytes.
+*
+*******************************************************************************/
+void Cy_SysEnableCM4(uint32_t vectorTableOffset)
+{
+    uint32_t regValue;
+    uint32_t interruptState;
+    uint32_t cpuState;
+
+    CY_ASSERT_L2((vectorTableOffset & CY_SYS_CM4_VECTOR_TABLE_VALID_ADDR) == 0UL);
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    cpuState = Cy_SysGetCM4Status();
+    if (CY_SYS_CM4_STATUS_ENABLED == cpuState)
+    {
+        Cy_SysResetCM4();
+    }
+
+    CPUSS->CM4_VECTOR_TABLE_BASE = vectorTableOffset;
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_ENABLED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysDisableCM4
+****************************************************************************//**
+*
+* Disables the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the
+* CPU.
+*
+*******************************************************************************/
+void Cy_SysDisableCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_DISABLED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysRetainCM4
+****************************************************************************//**
+*
+* Retains the Cortex-M4 core and exists without waiting for the mode to take
+* effect.
+*
+* \note The retained mode can be entered only from the enabled mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysRetainCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_RETAINED;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: Cy_SysResetCM4
+****************************************************************************//**
+*
+* Resets the Cortex-M4 core and waits for the mode to take the effect.
+*
+* \note The reset mode can not be entered from the retained mode.
+*
+* \warning Do not call the function while the Cortex-M4 is executing because
+* such a call may corrupt/abort a pending bus-transaction by the CPU and cause
+* unexpected behavior in the system including a deadlock. Call the function
+* while the Cortex-M4 core is in the Sleep or Deep Sleep low-power mode. Use
+* the \ref group_syspm Power Management (syspm) API to put the CPU into the
+* low-power modes. Use the \ref Cy_SysPm_ReadStatus() to get a status of the CPU.
+*
+*******************************************************************************/
+void Cy_SysResetCM4(void)
+{
+    uint32_t interruptState;
+    uint32_t regValue;
+
+    interruptState = Cy_SysLib_EnterCriticalSection();
+
+    regValue = CPUSS->CM4_PWR_CTL & ~(CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk | CPUSS_CM4_PWR_CTL_PWR_MODE_Msk);
+    regValue |= _VAL2FLD(CPUSS_CM4_PWR_CTL_VECTKEYSTAT, CY_SYS_CM4_PWR_CTL_KEY_OPEN);
+    regValue |= CY_SYS_CM4_STATUS_RESET;
+    CPUSS->CM4_PWR_CTL = regValue;
+
+    while((CPUSS->CM4_STATUS & CPUSS_CM4_STATUS_PWR_DONE_Msk) == 0UL)
+    {
+        /* Wait for the power mode to take effect */
+    }
+
+    Cy_SysLib_ExitCriticalSection(interruptState);
+}
+
+
+#else /* End of TVIIBE section, start of PSoC 6 section */
+
 #if !defined(CY_IPC_DEFAULT_CFG_DISABLE)
     #include "cy_ipc_sema.h"
     #include "cy_ipc_pipe.h"
@@ -215,7 +796,7 @@ void SystemInit(void)
 #endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */
 
     #if defined(CY_DEVICE_SECURE)
-        /* Initialize Protected Regsiter Access driver. */
+        /* Initialize Protected Register Access driver. */
         Cy_PRA_Init();
     #endif /* defined(CY_DEVICE_SECURE) */
 }
@@ -513,5 +1094,6 @@ __cy_memory_4_row_size  EQU __cpp(1)
 }
 #endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */
 
+#endif /* (defined(CY_DEVICE_TVIIBE)) */
 
 /* [] END OF FILE */

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/COMPONENT_CM4/TOOLCHAIN_A_Clang/linker.mk

@@ -0,0 +1,89 @@
+################################################################################
+# \file cy8c6xxa_cm4_dual.mk
+# \version 2.95.1
+#
+# \brief
+# Specifies the starting address and the size of the segments in the output
+# file.
+#
+# \note The section definitions in this file are generic and handle all common
+# use cases.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2021 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+### CM0P ###
+export HEAP_SIZE_CM0P     := 0x400
+export VECT_BASE_CM0P     := 0x10000000
+export RAM_VECT_BASE_CM0P := 0x08000000
+export VECT_SIZE_CM0P     := 0x00000080
+export TEXT_BASE_CM0P     := 0x10000080
+export TEXT_SIZE_CM0P     := 0x00002000
+export RAM_BASE_CM0P      := 0x08000080
+export RAM_SIZE_CM0P      := 0x00002000
+export CYMETA_BASE_CM0P   := 0x90500000
+export STACK_SIZE_CM0P    := 0x2000
+
+STACK_ADDRESS_TOP_CM0P    := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM0P) + $(RAM_SIZE_CM0P))))
+STACK_ADDRESS_BOTTOM_CM0P := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM0P) - $(STACK_SIZE_CM0P))))
+TOOLCHAIN_VECT_BASE_CM0   := $(VECT_BASE_CM0P)
+
+SECTIONS_CM0P := \
+    -segaddr __VECT $(VECT_BASE_CM0P) \
+    -segaddr __TEXT $(TEXT_BASE_CM0P) \
+    -segaddr __DATA $(RAM_BASE_CM0P) \
+    -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM0P) \
+    -segaddr __CYMETA $(CYMETA_BASE_CM0P) \
+    -segaddr __STACK $(STACK_ADDRESS_TOP_CM0P)
+
+### CM4 ###
+export HEAP_SIZE_CM4     := 0x400
+export VECT_BASE_CM4     := 0x10002000
+export RAM_VECT_BASE_CM4 := 0x08002000
+export VECT_SIZE_CM4     := 0x000002E0
+export TEXT_BASE_CM4     := 0x100022E0
+export TEXT_SIZE_CM4     := 0x001FE000
+export RAM_BASE_CM4      := 0x080022E0
+export RAM_SIZE_CM4      := 0x000FD800
+export CYMETA_BASE_CM4   := 0x90500000
+export STACK_SIZE_CM4    := 0x2000
+STACK_ADDRESS_TOP_CM4    := $(shell printf "0x%x" $$(($(RAM_VECT_BASE_CM4) + $(RAM_SIZE_CM4))))
+STACK_ADDRESS_BOTTOM_CM4 := $(shell printf "0x%x" $$(($(STACK_ADDRESS_TOP_CM4) - $(STACK_SIZE_CM4))))
+TOOLCHAIN_VECT_BASE_CM4  := $(VECT_BASE_CM4)
+
+SECTIONS_CM4 := \
+    -segaddr __CY_M0P_IMAGE $(VECT_BASE_CM0P) \
+    -segaddr __VECT $(VECT_BASE_CM4) \
+    -segaddr __TEXT $(TEXT_BASE_CM4) \
+    -segaddr __DATA $(RAM_BASE_CM4) \
+    -segaddr __RAMVECTORS $(RAM_VECT_BASE_CM4) \
+    -segaddr __CYMETA $(CYMETA_BASE_CM4) \
+    -segaddr __STACK $(STACK_ADDRESS_TOP_CM4)
+
+# Pass section addresses to the linker
+ifeq ($(MTB_RECIPE__CORE),CM4)
+ACLANG_MEM_LDFLAGS += \
+    -segalign 4 \
+    $(SECTIONS_CM4)
+else ifeq ($(MTB_RECIPE__CORE),CM0P)
+ACLANG_MEM_LDFLAGS += \
+    -segalign 4 \
+    $(SECTIONS_CM0P)
+endif
+
+# EOF

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/COMPONENT_CM4/system_psoc6_cm4.c

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6_cm4.c
-* \version 2.95.1
+* \version 2.100
 *
 * The device system-source file.
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/README.md

@@ -1,8 +1,10 @@
-# CY8CKIT-062S2-43012 BSP
+# CY8CEVAL-062S2 BSP
 
 ## Overview
 
-The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
+The CY8CEVAL-062S2 PSoC™ 62S2 Evaluation Kit enables you to evaluate and develop applications using PSoC™ 62 MCU. The PSoC™ 62S2 evaluation kit features an M.2 interface that enables you to connect the supported M.2 radio cards based on AIROC™ Wi-Fi/Bluetooth combo devices. It comes with industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface, mikroBUS add-on board interface for peripheral expansion, OPTIGA Trust M device.     
+**Note:**
+This BSP does not support Wi-Fi/BT Connectivity examples. To run Wi-Fi/Bluetooth Connectivity examples on this kit, choose a BSP with the appropriate connectivity M.2 module.
 
 ![](docs/html/board.png)
 
@@ -13,21 +15,22 @@ To use code from the BSP, simply include a reference to `cybsp.h`.
 ### Kit Features:
 
 * Support of up to 2MB Flash and 1MB SRAM
-* Dedicated SDHC to interface with WICED wireless devices.
+* Dedicated M.2 interface to connect with M.2 radio modules based on AIROC™ Wi-Fi/Bluetooth combo devices.
+* mikroBUS add-on board interface for peripheral expansion.
 * Delivers dual-cores, with a 150-MHz Arm® Cortex®-M4 as the primary application processor and a 100-MHz Arm® Cortex®-M0+ as the secondary processor for low-power operations.
 * Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM digital microphone interface, a Quad- SPI interface, 13 serial communication blocks, 7 programmable analog blocks, and 56 programmable digital blocks.
 
 ### Kit Contents:
 
-* PSoC™ 6S2 Wi-Fi BT Pioneer Board
+* PSoC™ 62S2 Evaluation Board
 * USB Type-A to Micro-B cable
-* Quick Start Guide
 * Four jumper wires (4 inches each)
 * Two jumper wires (5 inches each)
+* Quick start guide
 
 ## BSP Configuration
 
-The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CKIT-062S2-43012.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
+The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CEVAL-062S2.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.
 
 Components:
 * Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
@@ -56,19 +59,19 @@ See the [BSP Setttings][settings] for additional board specific configuration se
 
 ## API Reference Manual
 
-The CY8CKIT-062S2-43012 Board Support Package provides a set of APIs to configure, initialize and use the board resources.
+The CY8CEVAL-062S2 Board Support Package provides a set of APIs to configure, initialize and use the board resources.
 
 See the [BSP API Reference Manual][api] for the complete list of the provided interfaces.
 
 ## More information
-* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
-* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
+* [CY8CEVAL-062S2 BSP API Reference Manual][api]
+* [CY8CEVAL-062S2 Documentation](https://www.cypress.com/documentation/development-kitsboards/psoc-62s2-evaluation-kit-cy8ceval-062s2)
 * [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
 * [Infineon GitHub](https://github.com/infineon)
 * [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
 
-[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
-[settings]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/md_bsp_settings.html
+[api]: https://infineon.github.io/TARGET_CY8CEVAL-062S2/html/modules.html
+[settings]: https://infineon.github.io/TARGET_CY8CEVAL-062S2/html/md_bsp_settings.html
 
 ---
 © Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/RELEASE.md

@@ -1,10 +1,12 @@
-# CY8CKIT-062S2-43012 BSP Release Notes
-The CY8CKIT-062S2-43012 PSoC™ 6S2 Wi-Fi BT Pioneer Kit is a low-cost hardware platform that enables design and debug of PSoC™ 6 MCUs. It comes with a Murata 1LV Module (CYW43012 Wi-Fi + Bluetooth Combo Chip), industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface.
+# CY8CEVAL-062S2 BSP Release Notes
+The CY8CEVAL-062S2 PSoC™ 62S2 Evaluation Kit enables you to evaluate and develop applications using PSoC™ 62 MCU. The PSoC™ 62S2 evaluation kit features an M.2 interface that enables you to connect the supported M.2 radio cards based on AIROC™ Wi-Fi/Bluetooth combo devices. It comes with industry-leading CAPSENSE™ for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone interface, mikroBUS add-on board interface for peripheral expansion, OPTIGA Trust M device.     
+**Note:**
+This BSP does not support Wi-Fi/BT Connectivity examples. To run Wi-Fi/Bluetooth Connectivity examples on this kit, choose a BSP with the appropriate connectivity M.2 module.
 
 NOTE: BSPs are versioned by family. This means that version 1.2.0 of any BSP in a family (eg: PSoC™ 6) will have the same software maturity level. However, not all updates are necessarily applicable for each BSP in the family so not all version numbers will exist for each board. Additionally, new BSPs may not start at version 1.0.0. In the event of adding a common feature across all BSPs, the libraries are assigned the same version number. For example if BSP_A is at v1.3.0 and BSP_B is at v1.2.0, the event will trigger a version update to v1.4.0 for both BSP_A and BSP_B. This allows the common feature to be tracked in a consistent way.
 
 ### What's Included?
-The CY8CKIT-062S2-43012 library includes the following:
+The CY8CEVAL-062S2 library includes the following:
 * BSP specific makefile to configure the build process for the board
 * cybsp.c/h files to initialize the board and any system peripherals
 * cybsp_types.h file describing basic board setup
@@ -15,6 +17,11 @@ The CY8CKIT-062S2-43012 library includes the following:
 * API documentation
 
 ### What Changed?
+#### v4.3.1
+Updated the README file for CY8CEVAL-062S2-MUR-43439M2.
+#### v4.3.0
+* Update companion device pin configuration to align with requirements of MUR-43439 and LAI-43439 M.2 module.
+* Updated the README file for CY8CEVAL-062S2, CY8CEVAL-062S2-LAI-43439M2, CY8CEVAL-062S2-LAI-4373M2, CY8CEVAL-062S2-MUR-4373M2, and CY8CEVAL-062S2-MUR-4373EM2 BSPs to remove the M.2 radio module detail from kit contents section.
 #### v4.2.0
 * Updated linker scripts and startup code to align with mtb-pdl-cat1 v3.4.0
 * Added functionality to enable BSP Assistant chip flow
@@ -82,25 +89,25 @@ NOTE: This requires psoc6hal 1.2.0 or later
 * Initial release
 
 ### Supported Software and Tools
-This version of the CY8CKIT-062S2-43012 BSP was validated for compatibility with the following Software and Tools:
+This version of the CY8CEVAL-062S2 BSP was validated for compatibility with the following Software and Tools:
 
 | Software and Tools                        | Version |
 | :---                                      | :----:  |
-| ModusToolbox™ Software Environment        | 3.1.0   |
-| GCC Compiler                              | 12.2.1  |
+| ModusToolbox™ Software Environment        | 3.0.0   |
+| GCC Compiler                              | 11.3.1  |
 | IAR Compiler                              | 9.30.1  |
 | ARM Compiler                              | 6.16    |
 
 Minimum required ModusToolbox™ Software Environment: v3.0.0
 
 ### More information
-* [CY8CKIT-062S2-43012 BSP API Reference Manual][api]
-* [CY8CKIT-062S2-43012 Documentation](http://www.cypress.com/CY8CKIT-062S2-43012)
+* [CY8CEVAL-062S2 BSP API Reference Manual][api]
+* [CY8CEVAL-062S2 Documentation](https://www.cypress.com/documentation/development-kitsboards/psoc-62s2-evaluation-kit-cy8ceval-062s2)
 * [Cypress Semiconductor, an Infineon Technologies Company](http://www.cypress.com)
 * [Infineon GitHub](https://github.com/infineon)
 * [ModusToolbox™](https://www.cypress.com/products/modustoolbox-software-environment)
 
-[api]: https://infineon.github.io/TARGET_CY8CKIT-062S2-43012/html/modules.html
+[api]: https://infineon.github.io/TARGET_CY8CEVAL-062S2/html/modules.html
 
 ---
 © Cypress Semiconductor Corporation (an Infineon company) or an affiliate of Cypress Semiconductor Corporation, 2019-2022.

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/bsp.mk

@@ -0,0 +1,60 @@
+################################################################################
+# \file bsp.mk
+#
+# \brief
+# Define the CY8CEVAL-062S2 target.
+#
+################################################################################
+# \copyright
+# Copyright 2018-2022 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+ifeq ($(WHICHFILE),true)
+$(info Processing $(lastword $(MAKEFILE_LIST)))
+endif
+
+# Any additional components to apply when using this board.
+# Use a default CM0+ image (CM0P_SLEEP). This can be swapped for a different
+# pre-built image or removed if custom built project.
+BSP_COMPONENTS:=CM0P_SLEEP
+
+# Any additional defines to apply when using this board.
+BSP_DEFINES:=CY_USING_HAL
+
+################################################################################
+# ALL ITEMS BELOW THIS POINT ARE AUTO GENERATED BY THE BSP ASSISTANT TOOL.
+# DO NOT MODIFY DIRECTLY. CHANGES SHOULD BE MADE THROUGH THE BSP ASSISTANT.
+################################################################################
+
+# Board device selection. MPN_LIST tracks what was selected in the BSP Assistant
+# All other variables are derived by BSP Assistant based on the MPN_LIST.
+MPN_LIST:=CY8C624ALQI-S2D42 LBEE59B1LV
+DEVICE:=CY8C624ALQI-S2D42
+DEVICE_COMPONENTS:=43012 CAT1 CAT1A HCI-UART MURATA-1LV PSOC6_02
+DEVICE_CY8C624ABZI-S2D44_SRAM_KB:=1024
+DEVICE_LIST:=CY8C624ALQI-S2D42 CYW43012C0WKWBG
+DEVICE_TOOL_IDS:=bsp-assistant bt-configurator capsense-configurator capsense-tuner device-configurator dfuh-tool library-manager lin-configurator ml-configurator motor-suite-gui project-creator qspi-configurator seglcd-configurator smartio-configurator usbdev-configurator
+RECIPE_DIR:=$(SEARCH_recipe-make-cat1a)
+ADDITIONAL_DEVICES:=CYW43012C0WKWBG
+DEVICE_CY8C624ALQI-S2D42_CORES:=CORE_NAME_CM0P_0 CORE_NAME_CM4_0
+DEVICE_CY8C624ALQI-S2D42_DIE:=PSoC6A2M
+DEVICE_CY8C624ALQI-S2D42_FEATURES:=NA
+DEVICE_CY8C624ALQI-S2D42_FLASH_KB:=2048
+DEVICE_CYW43012C0WKWBG_CORES:=CORE_NAME_CM4_0
+DEVICE_CYW43012C0WKWBG_DIE:=43012C0
+DEVICE_CYW43012C0WKWBG_FLASH_KB:=0

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg.c

@@ -5,11 +5,11 @@
 * Wrapper function to initialize all generated code.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg.h

@@ -5,11 +5,11 @@
 * Simple wrapper header containing all generated files.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg.timestamp

@@ -5,11 +5,11 @@
 * Sentinel file for determining if generated source is up to date.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_capsense.c

@@ -4,10 +4,10 @@
 * Description:
 * CAPSENSE Middleware configuration
 * This file should not be modified. It was automatically generated by
-* CAPSENSE Configurator 6.10.0.3796
+* CAPSENSE Configurator 5.0.0.2684
 *
 ********************************************************************************
-* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company) 
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) 
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -80,10 +80,6 @@ static cy_stc_capsense_internal_context_t cy_capsense_internalContext;
     static uint16_t cy_capsense_rawFilterHistory[CY_CAPSENSE_RAW_HISTORY_SIZE] = {0};
 #endif
 
-#if (CY_CAPSENSE_RAW_ALP_HISTORY_SIZE > 0)
-    static uint16_t cy_capsense_rawAlpFilterHistory[CY_CAPSENSE_RAW_ALP_HISTORY_SIZE] = {0};
-#endif
-
 #if (CY_CAPSENSE_IIR_HISTORY_LOW_SIZE > 0)
     static uint8_t cy_capsense_iirHistoryLow[CY_CAPSENSE_IIR_HISTORY_LOW_SIZE] = {0};
 #endif
@@ -142,7 +138,6 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
     .numPin = CY_CAPSENSE_PIN_COUNT,
     .numSns = CY_CAPSENSE_SENSOR_COUNT,
     .numWd = CY_CAPSENSE_TOTAL_WIDGET_COUNT,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdEn = CY_CAPSENSE_ENABLE,
     .csxEn = CY_CAPSENSE_DISABLE,
     #if (CY_CAPSENSE_MW_VERSION < 300)
@@ -152,7 +147,6 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
         .bistEn = CY_CAPSENSE_DISABLE,
     #endif
     .positionFilterEn = CY_CAPSENSE_DISABLE,
-#endif
     .periDividerType = (uint8_t)CY_CAPSENSE_PERI_DIV_TYPE,
     .periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX,
     .analogWakeupDelay = 25u,
@@ -188,46 +182,34 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
     .pinCsh = 0u,
     .pinCintA = 0u,
     .pinCintB = 0u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdShieldEn = CY_CAPSENSE_DISABLE,
-#endif
     .csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
-#if (CY_CAPSENSE_MW_VERSION >= 300)
-    .csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
-#endif
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        .csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
+    #endif
     .csdShieldDelay = CY_CAPSENSE_SH_DELAY_0NS,
     .csdVref = 0u,
     .csdRConst = 1000u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdCTankShieldEn = CY_CAPSENSE_DISABLE,
-#endif
     .csdShieldNumPin = 0u,
     .csdShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
     .csdInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
     .csdChargeTransfer = CY_CAPSENSE_IDAC_SOURCING,
     .csdRawTarget = 85u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdAutotuneEn = CY_CAPSENSE_CSD_SS_HWTH_EN,
     .csdIdacAutocalEn = CY_CAPSENSE_ENABLE,
     .csdIdacAutoGainEn = CY_CAPSENSE_ENABLE,
-#endif
     .csdCalibrationError = 10u,
     .csdIdacGainInitIndex = 4u,
     .csdIdacMin = 20u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdIdacCompEn = CY_CAPSENSE_ENABLE,
-#endif
     .csdFineInitTime = 10u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csdIdacRowColAlignEn = CY_CAPSENSE_ENABLE,
-#endif
     .csdMfsDividerOffsetF1 = 1u,
     .csdMfsDividerOffsetF2 = 2u,
     .csxRawTarget = 40u,
-#if (CY_CAPSENSE_MW_VERSION < 400)
     .csxIdacGainInitIndex = 2u,
     .csxIdacAutocalEn = CY_CAPSENSE_DISABLE,
-#endif
     .csxCalibrationError = 20u,
     .csxFineInitTime = 10u,
     .csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
@@ -403,14 +385,6 @@ static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
 
 static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_COUNT] =
 {
-    { /* Button0_Sns0 */
-        Button0_Sns0_PORT,
-        Button0_Sns0_PIN,
-    },
-    { /* Button1_Sns0 */
-        Button1_Sns0_PORT,
-        Button1_Sns0_PIN,
-    },
     { /* LinearSlider0_Sns0 */
         LinearSlider0_Sns0_PORT,
         LinearSlider0_Sns0_PIN,
@@ -442,38 +416,28 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
 #if (CY_CAPSENSE_ELTD_COUNT > 0)
     static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] =
     {
-        { /* Button0_Sns0 */
-            .ptrPin = &cy_capsense_pinConfig[0u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
-            .numPins = 1u,
-        },
-        { /* Button1_Sns0 */
-            .ptrPin = &cy_capsense_pinConfig[1u],
-            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
-            .numPins = 1u,
-        },
         { /* LinearSlider0_Sns0 */
-            .ptrPin = &cy_capsense_pinConfig[2u],
+            .ptrPin = &cy_capsense_pinConfig[0u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns1 */
-            .ptrPin = &cy_capsense_pinConfig[3u],
+            .ptrPin = &cy_capsense_pinConfig[1u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns2 */
-            .ptrPin = &cy_capsense_pinConfig[4u],
+            .ptrPin = &cy_capsense_pinConfig[2u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns3 */
-            .ptrPin = &cy_capsense_pinConfig[5u],
+            .ptrPin = &cy_capsense_pinConfig[3u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
         { /* LinearSlider0_Sns4 */
-            .ptrPin = &cy_capsense_pinConfig[6u],
+            .ptrPin = &cy_capsense_pinConfig[4u],
             .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
             .numPins = 1u,
         },
@@ -482,7 +446,7 @@ static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_
 
 static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] =
 {
-    { /* Button0 */
+    { /* LinearSlider0 */
         .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
         .ptrSnsContext = &cy_capsense_tuner.sensorContext[0u],
         .ptrEltdConfig = &cy_capsense_electrodeConfig[0u],
@@ -496,126 +460,6 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
         .iirCoeff = 128u,
         .ptrDebounceArr = &cy_capsense_debounce[0u],
         .ptrDiplexTable = NULL,
-        .centroidConfig = 0u,
-        .xResolution = 0u,
-        .yResolution = 0u,
-        .numSns = 1u,
-        .numCols = 1u,
-        .numRows = 0u,
-        .ptrPosFilterHistory = NULL,
-        .ptrCsxTouchHistory = NULL,
-        .ptrCsxTouchBuffer = NULL,
-        .ptrCsdTouchBuffer = NULL,
-        .ptrGestureConfig = NULL,
-        .ptrGestureContext = NULL,
-        .ballisticConfig = {
-            .accelCoeff = 9u,
-            .speedCoeff = 2u,
-            .divisorValue = 4u,
-            .speedThresholdX = 3u,
-            .speedThresholdY = 4u,
-        },
-        .ptrBallisticContext = NULL,
-        .aiirConfig = {
-            .maxK = 60u,
-            .minK = 1u,
-            .noMovTh = 3u,
-            .littleMovTh = 7u,
-            .largeMovTh = 12u,
-            .divVal = 64u,
-        },
-        .advConfig = {
-            .penultimateTh = 100u,
-            .virtualSnsTh = 100u,
-            .crossCouplingTh = 5u,
-        },
-        .posFilterConfig = 0u,
-        .rawFilterConfig = 0u,
-#if (CY_CAPSENSE_MW_VERSION >= 400)
-        .alpOnThreshold = 15u,
-        .alpOffThreshold = 5u,
-#endif
-        #if (CY_CAPSENSE_MW_VERSION >= 300)
-            .senseMethod = CY_CAPSENSE_CSD_GROUP,
-        #else
-            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
-        #endif
-        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
-    },
-    { /* Button1 */
-        .ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
-        .ptrSnsContext = &cy_capsense_tuner.sensorContext[1u],
-        .ptrEltdConfig = &cy_capsense_electrodeConfig[1u],
-#if (CY_CAPSENSE_BIST_SUPPORTED)
-        .ptrEltdCapacitance = NULL,
-        .ptrBslnInv = NULL,
-#endif
-        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[1u],
-        .ptrRawFilterHistory = NULL,
-        .ptrRawFilterHistoryLow = NULL,
-        .iirCoeff = 128u,
-        .ptrDebounceArr = &cy_capsense_debounce[1u],
-        .ptrDiplexTable = NULL,
-        .centroidConfig = 0u,
-        .xResolution = 0u,
-        .yResolution = 0u,
-        .numSns = 1u,
-        .numCols = 1u,
-        .numRows = 0u,
-        .ptrPosFilterHistory = NULL,
-        .ptrCsxTouchHistory = NULL,
-        .ptrCsxTouchBuffer = NULL,
-        .ptrCsdTouchBuffer = NULL,
-        .ptrGestureConfig = NULL,
-        .ptrGestureContext = NULL,
-        .ballisticConfig = {
-            .accelCoeff = 9u,
-            .speedCoeff = 2u,
-            .divisorValue = 4u,
-            .speedThresholdX = 3u,
-            .speedThresholdY = 4u,
-        },
-        .ptrBallisticContext = NULL,
-        .aiirConfig = {
-            .maxK = 60u,
-            .minK = 1u,
-            .noMovTh = 3u,
-            .littleMovTh = 7u,
-            .largeMovTh = 12u,
-            .divVal = 64u,
-        },
-        .advConfig = {
-            .penultimateTh = 100u,
-            .virtualSnsTh = 100u,
-            .crossCouplingTh = 5u,
-        },
-        .posFilterConfig = 0u,
-        .rawFilterConfig = 0u,
-#if (CY_CAPSENSE_MW_VERSION >= 400)
-        .alpOnThreshold = 15u,
-        .alpOffThreshold = 5u,
-#endif
-        #if (CY_CAPSENSE_MW_VERSION >= 300)
-            .senseMethod = CY_CAPSENSE_CSD_GROUP,
-        #else
-            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
-        #endif
-        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
-    },
-    { /* LinearSlider0 */
-        .ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
-        .ptrSnsContext = &cy_capsense_tuner.sensorContext[2u],
-        .ptrEltdConfig = &cy_capsense_electrodeConfig[2u],
-#if (CY_CAPSENSE_BIST_SUPPORTED)
-        .ptrEltdCapacitance = NULL,
-        .ptrBslnInv = NULL,
-#endif
-        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[2u],
-        .ptrRawFilterHistory = NULL,
-        .ptrRawFilterHistoryLow = NULL,
-        .iirCoeff = 128u,
-        .ptrDebounceArr = &cy_capsense_debounce[2u],
-        .ptrDiplexTable = NULL,
         .centroidConfig = 1u,
         .xResolution = 300u,
         .yResolution = 0u,
@@ -651,10 +495,6 @@ static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENS
         },
         .posFilterConfig = 0u,
         .rawFilterConfig = 0u,
-#if (CY_CAPSENSE_MW_VERSION >= 400)
-        .alpOnThreshold = 15u,
-        .alpOffThreshold = 5u,
-#endif
         #if (CY_CAPSENSE_MW_VERSION >= 300)
             .senseMethod = CY_CAPSENSE_CSD_GROUP,
         #else
@@ -668,11 +508,11 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
 {
     .commonContext = {
         #if (CY_CAPSENSE_MW_VERSION < 300)
-            .configId = 0xa368,
+            .configId = 0xcb38,
         #elif (CY_CAPSENSE_MW_VERSION < 400)
-            .configId = 0xa369,
+            .configId = 0xcb39,
         #else
-            .configId = 0xa36a,
+            .configId = 0xcb3a,
         #endif
 
         .tunerCmd = 0u,
@@ -693,70 +533,6 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
         .tunerCnt = 0u,
     },
     .widgetContext = {
-        { /* Button0 */
-            .fingerCap = 160u,
-            .sigPFC = 0u,
-            .resolution = 12u,
-            .maxRawCount = 0u,
-            #if (CY_CAPSENSE_MW_VERSION >= 300)
-                .maxRawCountRow = 0u,
-            #endif
-            .fingerTh = 100u,
-            .proxTh = 200u,
-            .lowBslnRst = 30u,
-            .snsClk = 4u,
-            .rowSnsClk = 4u,
-            .gestureDetected = 0u,
-            .gestureDirection = 0u,
-            .xDelta = 0,
-            .yDelta = 0,
-            .noiseTh = 40u,
-            .nNoiseTh = 40u,
-            .hysteresis = 10u,
-            .onDebounce = 3u,
-            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
-            .idacMod = { 32u, 32u, 32u, },
-            .idacGainIndex = 4u,
-            .rowIdacMod = { 32u, 32u, 32u, },
-            .bslnCoeff = 1u,
-            .status = 0u,
-            .wdTouch = {
-                .ptrPosition = NULL,
-                .numPosition = 0,
-            },
-        },
-        { /* Button1 */
-            .fingerCap = 160u,
-            .sigPFC = 0u,
-            .resolution = 12u,
-            .maxRawCount = 0u,
-            #if (CY_CAPSENSE_MW_VERSION >= 300)
-                .maxRawCountRow = 0u,
-            #endif
-            .fingerTh = 100u,
-            .proxTh = 200u,
-            .lowBslnRst = 30u,
-            .snsClk = 4u,
-            .rowSnsClk = 4u,
-            .gestureDetected = 0u,
-            .gestureDirection = 0u,
-            .xDelta = 0,
-            .yDelta = 0,
-            .noiseTh = 40u,
-            .nNoiseTh = 40u,
-            .hysteresis = 10u,
-            .onDebounce = 3u,
-            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
-            .idacMod = { 32u, 32u, 32u, },
-            .idacGainIndex = 4u,
-            .rowIdacMod = { 32u, 32u, 32u, },
-            .bslnCoeff = 1u,
-            .status = 0u,
-            .wdTouch = {
-                .ptrPosition = NULL,
-                .numPosition = 0,
-            },
-        },
         { /* LinearSlider0 */
             .fingerCap = 160u,
             .sigPFC = 0u,
@@ -791,24 +567,6 @@ cy_stc_capsense_tuner_t cy_capsense_tuner =
         },
     },
     .sensorContext = {
-        { /* Button0_Sns0 */
-            .raw = 0u,
-            .bsln = 0u,
-            .diff = 0u,
-            .status = 0u,
-            .negBslnRstCnt = 0u,
-            .idacComp = 32u,
-            .bslnExt = 0u,
-        },
-        { /* Button1_Sns0 */
-            .raw = 0u,
-            .bsln = 0u,
-            .diff = 0u,
-            .status = 0u,
-            .negBslnRstCnt = 0u,
-            .idacComp = 32u,
-            .bslnExt = 0u,
-        },
         { /* LinearSlider0_Sns0 */
             .raw = 0u,
             .bsln = 0u,

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_capsense.timestamp

@@ -1,26 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_capsense.timestamp
-*
-* Description:
-* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
-* CAPSENSE Configurator 6.10.0.3796
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_capsense_defines.h

@@ -8,10 +8,10 @@
 * successfully.
 *
 * This file should not be modified. It was automatically generated by
-* CAPSENSE Configurator 6.10.0.3796
+* CAPSENSE Configurator 5.0.0.2684
 *
 ********************************************************************************
-* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company) 
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) 
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -34,21 +34,20 @@
 #include <stddef.h>
 
 /* General */
-#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (1u)
 #define CY_CAPSENSE_ACTIVE_WIDGET_COUNT                                          (CY_CAPSENSE_WIDGET_COUNT)
 #define CY_CAPSENSE_LP_WIDGET_COUNT                                              (0u)
 #define CY_CAPSENSE_TOTAL_WIDGET_COUNT                                           (CY_CAPSENSE_WIDGET_COUNT)
-#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
-#define CY_CAPSENSE_ELTD_COUNT                                                   (7u)
-#define CY_CAPSENSE_PIN_COUNT                                                    (7u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (5u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (5u)
+#define CY_CAPSENSE_PIN_COUNT                                                    (5u)
 #define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
 #define CY_CAPSENSE_POSITION_SIZE                                                (1u)
-#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
-#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (7u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (1u)
+#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (5u)
 #define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
 #define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
 #define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE                                         (0u)
-#define CY_CAPSENSE_RAW_ALP_HISTORY_SIZE                                         (0u)
 #define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE                                 (0u)
 #define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE                                    (0u)
 #define CY_CAPSENSE_DIPLEX_SIZE                                                  (0u)
@@ -67,7 +66,7 @@
 #define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
 #define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
 #define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)
-#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN | CY_CAPSENSE_SMARTSENSE_HW_EN)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
 #define CY_CAPSENSE_CSD_SHIELD_EN                                                (0u)
 #define CY_CAPSENSE_CSD_SHIELD_CAP_EN                                            (0u)
 #define CY_CAPSENSE_CSD_CHARGE_TRANSFER                                          (0u)
@@ -82,17 +81,14 @@
 #define CY_CAPSENSE_ADAPTIVE_FILTER_EN                                           (0u)
 #define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN                                      (0u)
 #define CY_CAPSENSE_RAWCOUNT_FILTER_EN                                           (0u)
-#define CY_CAPSENSE_RC_ALP_FILTER_EN                                             (0u)
 #define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN                                     (0u)
 #define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN                                  (0u)
 #define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN                                 (0u)
-#define CY_CAPSENSE_REGULAR_RC_ALP_FILTER_EN                                     (0u)
-#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN | CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN | CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN | CY_CAPSENSE_REGULAR_RC_ALP_FILTER_EN)
+#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
 #define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN                                        (0u)
 #define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN                                     (0u)
 #define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN                                    (0u)
-#define CY_CAPSENSE_PROX_RC_ALP_FILTER_EN                                        (0u)
-#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN | CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN | CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN | CY_CAPSENSE_PROX_RC_ALP_FILTER_EN)
+#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
 #define CY_CAPSENSE_POSITION_FILTER_EN                                           (0u)
 #define CY_CAPSENSE_CSD_POSITION_FILTER_EN                                       (0u)
 #define CY_CAPSENSE_CSX_POSITION_FILTER_EN                                       (0u)
@@ -102,7 +98,7 @@
 #define CY_CAPSENSE_POS_JITTER_FILTER_EN                                         (0u)
 
 /* Widgets */
-#define CY_CAPSENSE_CSD_BUTTON_EN                                                (1u)
+#define CY_CAPSENSE_CSD_BUTTON_EN                                                (0u)
 #define CY_CAPSENSE_CSD_MATRIX_EN                                                (0u)
 #define CY_CAPSENSE_CSD_SLIDER_EN                                                (1u)
 #define CY_CAPSENSE_CSD_TOUCHPAD_EN                                              (0u)
@@ -124,7 +120,7 @@
 #define CY_CAPSENSE_GANGED_SNS_EN                                                (0u)
 #define CY_CAPSENSE_CSD_GANGED_SNS_EN                                            (0u)
 #define CY_CAPSENSE_CSX_GANGED_SNS_EN                                            (0u)
-#define CY_CAPSENSE_BUTTON_EN                                                    (1u)
+#define CY_CAPSENSE_BUTTON_EN                                                    (0u)
 #define CY_CAPSENSE_MATRIX_EN                                                    (0u)
 #define CY_CAPSENSE_SLIDER_EN                                                    (1u)
 #define CY_CAPSENSE_LINEAR_SLIDER_EN                                             (1u)

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_capsense_tuner_regmap.h

@@ -4,10 +4,10 @@
 * Description:
 * CAPSENSE Tuner register map configuration.
 * This file should not be modified. It was automatically generated by
-* CAPSENSE Configurator 6.10.0.3796
+* CAPSENSE Configurator 5.0.0.2684
 *
 ********************************************************************************
-* Copyright 2023, Cypress Semiconductor Corporation (an Infineon company) 
+* Copyright 2025, Cypress Semiconductor Corporation (an Infineon company) 
 * or an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -82,424 +82,208 @@
 #define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (38u)
 #define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
 
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (40u)
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (42u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_OFFSET                                    (44u)
-#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_MAX_RAW_COUNT_OFFSET                                 (46u)
-#define CY_CAPSENSE_TUNER_BUTTON0_MAX_RAW_COUNT_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (48u)
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (50u)
-#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (52u)
-#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_OFFSET                                       (54u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SIZE                                         (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (56u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (58u)
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (60u)
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (62u)
-#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (64u)
-#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (66u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (67u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (68u)
-#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (69u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (70u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (71u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (72u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (73u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (74u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (75u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (76u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (77u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (78u)
-#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (79u)
-#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (80u)
-#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (84u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (88u)
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (90u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_OFFSET                                    (92u)
-#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_MAX_RAW_COUNT_OFFSET                                 (94u)
-#define CY_CAPSENSE_TUNER_BUTTON1_MAX_RAW_COUNT_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (96u)
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (98u)
-#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (100u)
-#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_OFFSET                                       (102u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SIZE                                         (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (104u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (106u)
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (108u)
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (110u)
-#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (112u)
-#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (114u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (115u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (116u)
-#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (117u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (118u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (119u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (120u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (121u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (122u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (123u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (124u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (125u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (126u)
-#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (127u)
-#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
-#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (40u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (42u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (44u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_OFFSET                           (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_OFFSET                           (46u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_SIZE                             (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (48u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (50u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (52u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (54u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (56u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (58u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (60u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (62u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (64u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (66u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (163u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (67u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (68u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (165u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (69u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (70u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (167u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (71u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (72u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (169u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (73u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (74u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (75u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (76u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (77u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (78u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (79u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (80u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (84u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_OFFSET                                     (184u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_OFFSET                                    (186u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_OFFSET                                    (188u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_OFFSET                                  (190u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (191u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_OFFSET                                    (192u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (193u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_OFFSET                                     (194u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_OFFSET                                    (196u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_OFFSET                                    (198u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_OFFSET                                  (200u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (201u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_OFFSET                                    (202u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (203u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (204u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (88u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (206u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (90u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (208u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (92u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (210u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (94u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (211u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (95u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (96u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (213u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (97u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (98u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (100u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (102u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (104u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (105u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (106u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (223u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (107u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (108u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (110u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (112u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (114u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (115u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (116u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (233u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (117u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (118u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (120u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (122u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (124u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (125u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (126u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (243u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (127u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (128u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (130u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (132u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (134u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (135u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (136u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (253u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (137u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (138u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (140u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (142u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (144u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
 
 #else /* CY_CAPSENSE_TUNER_MW_VERSION >= 300 */
@@ -536,433 +320,211 @@
 #define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (22u)
 #define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
 
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (24u)
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (26u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_OFFSET                                    (28u)
-#define CY_CAPSENSE_TUNER_BUTTON0_RESOLUTION_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_MAX_RAW_COUNT_OFFSET                                 (30u)
-#define CY_CAPSENSE_TUNER_BUTTON0_MAX_RAW_COUNT_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_MAX_RAW_COUNT_OFFSET                             (32u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_MAX_RAW_COUNT_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (34u)
-#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (36u)
-#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (38u)
-#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_OFFSET                                       (40u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SIZE                                         (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (42u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (44u)
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (46u)
-#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (48u)
-#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (50u)
-#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (52u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (54u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (56u)
-#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (58u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_OFFSET                                (59u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS_CLK_SOURCE_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (60u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (61u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (62u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (63u)
-#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (64u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (65u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (66u)
-#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (67u)
-#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (68u)
-#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (72u)
-#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (76u)
-#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (80u)
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (82u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_OFFSET                                    (84u)
-#define CY_CAPSENSE_TUNER_BUTTON1_RESOLUTION_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_MAX_RAW_COUNT_OFFSET                                 (86u)
-#define CY_CAPSENSE_TUNER_BUTTON1_MAX_RAW_COUNT_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_MAX_RAW_COUNT_OFFSET                             (88u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_MAX_RAW_COUNT_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (90u)
-#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (92u)
-#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (94u)
-#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_OFFSET                                       (96u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SIZE                                         (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (98u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (100u)
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (102u)
-#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (104u)
-#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (106u)
-#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (108u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (110u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (112u)
-#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (114u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_OFFSET                                (115u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS_CLK_SOURCE_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (116u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (117u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (118u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (119u)
-#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (120u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (121u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (122u)
-#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (123u)
-#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (124u)
-#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
-#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
-#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
-
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (24u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (26u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (28u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_OFFSET                           (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_OFFSET                           (30u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAX_RAW_COUNT_SIZE                             (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_MAX_RAW_COUNT_OFFSET                       (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_MAX_RAW_COUNT_OFFSET                       (32u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_MAX_RAW_COUNT_SIZE                         (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (34u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (36u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (38u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (40u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (42u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (44u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (46u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (48u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (50u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (52u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (54u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (56u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (58u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (59u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (60u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (61u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (62u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (63u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (64u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (177u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (65u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (178u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (66u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (179u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (67u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (68u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (184u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (72u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (188u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (76u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
 
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_OFFSET                                     (192u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_RAW0_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_OFFSET                                    (194u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_OFFSET                                    (196u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_DIFF0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_OFFSET                                  (198u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_STATUS0_SIZE                                    (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (199u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_OFFSET                                    (200u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_IDAC0_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_OFFSET                                (201u)
-#define CY_CAPSENSE_TUNER_BUTTON0_SNS0_BSLN_EXT0_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_OFFSET                                     (202u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_RAW0_SIZE                                       (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_OFFSET                                    (204u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_OFFSET                                    (206u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_DIFF0_SIZE                                      (2u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_OFFSET                                  (208u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_STATUS0_SIZE                                    (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_OFFSET                        (209u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_NEG_BSLN_RST_CNT0_SIZE                          (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_OFFSET                                    (210u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_IDAC0_SIZE                                      (1u)
-
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_OFFSET                                (211u)
-#define CY_CAPSENSE_TUNER_BUTTON1_SNS0_BSLN_EXT0_SIZE                                  (1u)
-
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (80u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (82u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (84u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (86u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (219u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (87u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (88u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (89u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (90u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (92u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (94u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (96u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (229u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (97u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (98u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (99u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (100u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (102u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (104u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (106u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (239u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (107u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (108u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (109u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (110u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (112u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (114u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (116u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (249u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (117u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (118u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (119u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (120u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (122u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (124u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (126u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (259u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (127u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (128u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (261u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (129u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (262u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (130u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (264u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (132u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (266u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (134u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
 
-#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (268u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (136u)
 #define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
 
 #endif

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_clocks.c

@@ -5,11 +5,11 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_clocks.h

@@ -5,11 +5,11 @@
 * Clock configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_connectivity_bt.c

@@ -5,11 +5,11 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_connectivity_bt.h

@@ -5,11 +5,11 @@
 * Connectivity BT configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_notices.h

@@ -6,11 +6,11 @@
 * design.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_peripherals.c

@@ -5,11 +5,11 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_peripherals.h

@@ -5,11 +5,11 @@
 * Peripheral Hardware Block configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -45,21 +45,17 @@ extern "C" {
 #define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
 #define CY_CAPSENSE_PERI_DIV_INDEX 0u
 #define Cmod_PORT GPIO_PRT7
-#define Button0_Sns0_PORT GPIO_PRT7
-#define Button1_Sns0_PORT GPIO_PRT9
-#define LinearSlider0_Sns0_PORT GPIO_PRT9
+#define LinearSlider0_Sns0_PORT GPIO_PRT7
 #define LinearSlider0_Sns1_PORT GPIO_PRT9
 #define LinearSlider0_Sns2_PORT GPIO_PRT9
 #define LinearSlider0_Sns3_PORT GPIO_PRT9
 #define LinearSlider0_Sns4_PORT GPIO_PRT9
 #define Cmod_PIN 7u
-#define Button0_Sns0_PIN 3u
-#define Button1_Sns0_PIN 0u
-#define LinearSlider0_Sns0_PIN 1u
-#define LinearSlider0_Sns1_PIN 2u
-#define LinearSlider0_Sns2_PIN 3u
-#define LinearSlider0_Sns3_PIN 0u
-#define LinearSlider0_Sns4_PIN 1u
+#define LinearSlider0_Sns0_PIN 3u
+#define LinearSlider0_Sns1_PIN 0u
+#define LinearSlider0_Sns2_PIN 1u
+#define LinearSlider0_Sns3_PIN 2u
+#define LinearSlider0_Sns4_PIN 3u
 #define Cmod_PORT_NUM 7u
 #define CYBSP_CSD_HW CSD0
 #define CYBSP_CSD_IRQ csd_interrupt_IRQn

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_pins.c

@@ -5,11 +5,11 @@
 * Pin configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -124,11 +124,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
         .channel_num = CYBSP_CINB_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config = 
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config = 
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_LED_RGB_BLUE_HSIOM,
+    .hsiom = CYBSP_CSD_SLD0_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -141,11 +141,11 @@ const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_LED_RGB_BLUE_obj = 
+    const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj = 
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_LED_RGB_BLUE_PORT_NUM,
-        .channel_num = CYBSP_LED_RGB_BLUE_PIN,
+        .block_num = CYBSP_CSD_SLD0_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD0_PIN,
     };
 #endif //defined (CY_USING_HAL)
 const cy_stc_gpio_pin_config_t CYBSP_CMOD_config = 
@@ -172,11 +172,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
         .channel_num = CYBSP_CMOD_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config = 
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config = 
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_CSD_BTN0_HSIOM,
+    .hsiom = CYBSP_CSD_SLD1_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -189,18 +189,18 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj = 
+    const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj = 
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_CSD_BTN0_PORT_NUM,
-        .channel_num = CYBSP_CSD_BTN0_PIN,
+        .block_num = CYBSP_CSD_SLD1_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD1_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_A8_config = 
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config = 
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_A8_HSIOM,
+    .hsiom = CYBSP_CSD_SLD2_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -213,18 +213,18 @@ const cy_stc_gpio_pin_config_t CYBSP_A8_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_A8_obj = 
+    const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj = 
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_A8_PORT_NUM,
-        .channel_num = CYBSP_A8_PIN,
+        .block_num = CYBSP_CSD_SLD2_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD2_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_A9_config = 
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config = 
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_A9_HSIOM,
+    .hsiom = CYBSP_CSD_SLD3_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -237,18 +237,18 @@ const cy_stc_gpio_pin_config_t CYBSP_A9_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_A9_obj = 
+    const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj = 
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_A9_PORT_NUM,
-        .channel_num = CYBSP_A9_PIN,
+        .block_num = CYBSP_CSD_SLD3_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD3_PIN,
     };
 #endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_A10_config = 
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config = 
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_A10_HSIOM,
+    .hsiom = CYBSP_CSD_SLD4_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -261,35 +261,11 @@ const cy_stc_gpio_pin_config_t CYBSP_A10_config =
     .vohSel = 0UL,
 };
 #if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_A10_obj = 
+    const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj = 
     {
         .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_A10_PORT_NUM,
-        .channel_num = CYBSP_A10_PIN,
-    };
-#endif //defined (CY_USING_HAL)
-const cy_stc_gpio_pin_config_t CYBSP_A11_config = 
-{
-    .outVal = 1,
-    .driveMode = CY_GPIO_DM_ANALOG,
-    .hsiom = CYBSP_A11_HSIOM,
-    .intEdge = CY_GPIO_INTR_DISABLE,
-    .intMask = 0UL,
-    .vtrip = CY_GPIO_VTRIP_CMOS,
-    .slewRate = CY_GPIO_SLEW_FAST,
-    .driveSel = CY_GPIO_DRIVE_1_2,
-    .vregEn = 0UL,
-    .ibufMode = 0UL,
-    .vtripSel = 0UL,
-    .vrefSel = 0UL,
-    .vohSel = 0UL,
-};
-#if defined (CY_USING_HAL)
-    const cyhal_resource_inst_t CYBSP_A11_obj = 
-    {
-        .type = CYHAL_RSC_GPIO,
-        .block_num = CYBSP_A11_PORT_NUM,
-        .channel_num = CYBSP_A11_PIN,
+        .block_num = CYBSP_CSD_SLD4_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD4_PIN,
     };
 #endif //defined (CY_USING_HAL)
 
@@ -300,7 +276,6 @@ void init_cycfg_pins(void)
     Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
     Cy_GPIO_Pin_Init(CYBSP_CINA_PORT, CYBSP_CINA_PIN, &CYBSP_CINA_config);
     Cy_GPIO_Pin_Init(CYBSP_CINB_PORT, CYBSP_CINB_PIN, &CYBSP_CINB_config);
-    Cy_GPIO_Pin_Init(CYBSP_CSD_BTN0_PORT, CYBSP_CSD_BTN0_PIN, &CYBSP_CSD_BTN0_config);
 }
 
 void reserve_cycfg_pins(void)
@@ -310,12 +285,11 @@ void reserve_cycfg_pins(void)
     cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
     cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
     cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
-    cyhal_hwmgr_reserve(&CYBSP_LED_RGB_BLUE_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
     cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
-    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
-    cyhal_hwmgr_reserve(&CYBSP_A8_obj);
-    cyhal_hwmgr_reserve(&CYBSP_A9_obj);
-    cyhal_hwmgr_reserve(&CYBSP_A10_obj);
-    cyhal_hwmgr_reserve(&CYBSP_A11_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
 #endif //defined (CY_USING_HAL)
 }

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_pins.h

@@ -5,11 +5,11 @@
 * Pin configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -45,7 +45,7 @@ extern "C" {
     #define CYBSP_USER_LED2 (P0_1)
     #define CYBSP_SW2 (P0_4)
     #define CYBSP_USER_BTN1 CYBSP_SW2
-    #define CYBSP_LED_RGB_GREEN (P0_5)
+    #define CYBSP_D8 (P0_5)
     #define CYBSP_A0 (P10_0)
     #define CYBSP_J2_1 CYBSP_A0
     #define CYBSP_A1 (P10_1)
@@ -158,38 +158,38 @@ extern "C" {
     #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT 
     #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
-#define CYBSP_LED_RGB_BLUE_ENABLED 1U
-#define CYBSP_USER_LED5_ENABLED CYBSP_LED_RGB_BLUE_ENABLED
-#define CYBSP_LED_RGB_BLUE_PORT GPIO_PRT7
-#define CYBSP_USER_LED5_PORT CYBSP_LED_RGB_BLUE_PORT
-#define CYBSP_LED_RGB_BLUE_PORT_NUM 7U
-#define CYBSP_USER_LED5_PORT_NUM CYBSP_LED_RGB_BLUE_PORT_NUM
-#define CYBSP_LED_RGB_BLUE_PIN 3U
-#define CYBSP_USER_LED5_PIN CYBSP_LED_RGB_BLUE_PIN
-#define CYBSP_LED_RGB_BLUE_NUM 3U
-#define CYBSP_USER_LED5_NUM CYBSP_LED_RGB_BLUE_NUM
-#define CYBSP_LED_RGB_BLUE_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_USER_LED5_DRIVEMODE CYBSP_LED_RGB_BLUE_DRIVEMODE
-#define CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE 1
-#define CYBSP_USER_LED5_INIT_DRIVESTATE CYBSP_LED_RGB_BLUE_INIT_DRIVESTATE
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT7
+#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
+#define CYBSP_CSD_SLD0_PORT_NUM 7U
+#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
 #ifndef ioss_0_port_7_pin_3_HSIOM
     #define ioss_0_port_7_pin_3_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_LED_RGB_BLUE_HSIOM ioss_0_port_7_pin_3_HSIOM
-#define CYBSP_USER_LED5_HSIOM CYBSP_LED_RGB_BLUE_HSIOM
-#define CYBSP_LED_RGB_BLUE_IRQ ioss_interrupts_gpio_7_IRQn
-#define CYBSP_USER_LED5_IRQ CYBSP_LED_RGB_BLUE_IRQ
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_7_pin_3_HSIOM
+#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_7_IRQn
+#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_LED_RGB_BLUE_HAL_PORT_PIN P7_3
-    #define CYBSP_USER_LED5_HAL_PORT_PIN CYBSP_LED_RGB_BLUE_HAL_PORT_PIN
-    #define CYBSP_LED_RGB_BLUE P7_3
-    #define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE
-    #define CYBSP_LED_RGB_BLUE_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_USER_LED5_HAL_IRQ CYBSP_LED_RGB_BLUE_HAL_IRQ
-    #define CYBSP_LED_RGB_BLUE_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_USER_LED5_HAL_DIR CYBSP_LED_RGB_BLUE_HAL_DIR
-    #define CYBSP_LED_RGB_BLUE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_USER_LED5_HAL_DRIVEMODE CYBSP_LED_RGB_BLUE_HAL_DRIVEMODE
+    #define CYBSP_CSD_SLD0_HAL_PORT_PIN P7_3
+    #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
+    #define CYBSP_CSD_SLD0 P7_3
+    #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
+    #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
+    #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
+    #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
 #define CYBSP_CMOD_ENABLED 1U
 #define CYBSP_CMOD_PORT GPIO_PRT7
@@ -210,184 +210,137 @@ extern "C" {
     #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT 
     #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
 #endif //defined (CY_USING_HAL)
-#define CYBSP_CSD_BTN0_ENABLED 1U
-#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
-#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
-#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
-#define CYBSP_CSD_BTN0_PORT_NUM 8U
-#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
-#define CYBSP_CSD_BTN0_PIN 1U
-#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
-#define CYBSP_CSD_BTN0_NUM 1U
-#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
-#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
-#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
-#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
-#ifndef ioss_0_port_8_pin_1_HSIOM
-    #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
-#endif
-#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
-#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
-#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
-#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
-#if defined (CY_USING_HAL)
-    #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
-    #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
-    #define CYBSP_CSD_BTN0 P8_1
-    #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
-    #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
-    #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
-    #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
-#endif //defined (CY_USING_HAL)
-#define CYBSP_A8_ENABLED 1U
-#define CYBSP_J2_2_ENABLED CYBSP_A8_ENABLED
-#define CYBSP_A8_PORT GPIO_PRT9
-#define CYBSP_J2_2_PORT CYBSP_A8_PORT
-#define CYBSP_A8_PORT_NUM 9U
-#define CYBSP_J2_2_PORT_NUM CYBSP_A8_PORT_NUM
-#define CYBSP_A8_PIN 0U
-#define CYBSP_J2_2_PIN CYBSP_A8_PIN
-#define CYBSP_A8_NUM 0U
-#define CYBSP_J2_2_NUM CYBSP_A8_NUM
-#define CYBSP_A8_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_J2_2_DRIVEMODE CYBSP_A8_DRIVEMODE
-#define CYBSP_A8_INIT_DRIVESTATE 1
-#define CYBSP_J2_2_INIT_DRIVESTATE CYBSP_A8_INIT_DRIVESTATE
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT9
+#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
+#define CYBSP_CSD_SLD1_PORT_NUM 9U
+#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
+#define CYBSP_CSD_SLD1_PIN 0U
+#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
+#define CYBSP_CSD_SLD1_NUM 0U
+#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
 #ifndef ioss_0_port_9_pin_0_HSIOM
     #define ioss_0_port_9_pin_0_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_A8_HSIOM ioss_0_port_9_pin_0_HSIOM
-#define CYBSP_J2_2_HSIOM CYBSP_A8_HSIOM
-#define CYBSP_A8_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_J2_2_IRQ CYBSP_A8_IRQ
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_9_pin_0_HSIOM
+#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_A8_HAL_PORT_PIN P9_0
-    #define CYBSP_J2_2_HAL_PORT_PIN CYBSP_A8_HAL_PORT_PIN
-    #define CYBSP_A8 P9_0
-    #define CYBSP_J2_2 CYBSP_A8
-    #define CYBSP_A8_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_J2_2_HAL_IRQ CYBSP_A8_HAL_IRQ
-    #define CYBSP_A8_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_J2_2_HAL_DIR CYBSP_A8_HAL_DIR
-    #define CYBSP_A8_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_J2_2_HAL_DRIVEMODE CYBSP_A8_HAL_DRIVEMODE
+    #define CYBSP_CSD_SLD1_HAL_PORT_PIN P9_0
+    #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
+    #define CYBSP_CSD_SLD1 P9_0
+    #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
+    #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
+    #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
+    #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
-#define CYBSP_A9_ENABLED 1U
-#define CYBSP_J2_4_ENABLED CYBSP_A9_ENABLED
-#define CYBSP_A9_PORT GPIO_PRT9
-#define CYBSP_J2_4_PORT CYBSP_A9_PORT
-#define CYBSP_A9_PORT_NUM 9U
-#define CYBSP_J2_4_PORT_NUM CYBSP_A9_PORT_NUM
-#define CYBSP_A9_PIN 1U
-#define CYBSP_J2_4_PIN CYBSP_A9_PIN
-#define CYBSP_A9_NUM 1U
-#define CYBSP_J2_4_NUM CYBSP_A9_NUM
-#define CYBSP_A9_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_J2_4_DRIVEMODE CYBSP_A9_DRIVEMODE
-#define CYBSP_A9_INIT_DRIVESTATE 1
-#define CYBSP_J2_4_INIT_DRIVESTATE CYBSP_A9_INIT_DRIVESTATE
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT9
+#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
+#define CYBSP_CSD_SLD2_PORT_NUM 9U
+#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
+#define CYBSP_CSD_SLD2_PIN 1U
+#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
+#define CYBSP_CSD_SLD2_NUM 1U
+#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
 #ifndef ioss_0_port_9_pin_1_HSIOM
     #define ioss_0_port_9_pin_1_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_A9_HSIOM ioss_0_port_9_pin_1_HSIOM
-#define CYBSP_J2_4_HSIOM CYBSP_A9_HSIOM
-#define CYBSP_A9_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_J2_4_IRQ CYBSP_A9_IRQ
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_9_pin_1_HSIOM
+#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_A9_HAL_PORT_PIN P9_1
-    #define CYBSP_J2_4_HAL_PORT_PIN CYBSP_A9_HAL_PORT_PIN
-    #define CYBSP_A9 P9_1
-    #define CYBSP_J2_4 CYBSP_A9
-    #define CYBSP_A9_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_J2_4_HAL_IRQ CYBSP_A9_HAL_IRQ
-    #define CYBSP_A9_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_J2_4_HAL_DIR CYBSP_A9_HAL_DIR
-    #define CYBSP_A9_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_J2_4_HAL_DRIVEMODE CYBSP_A9_HAL_DRIVEMODE
+    #define CYBSP_CSD_SLD2_HAL_PORT_PIN P9_1
+    #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
+    #define CYBSP_CSD_SLD2 P9_1
+    #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
+    #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
+    #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
+    #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
-#define CYBSP_A10_ENABLED 1U
-#define CYBSP_J2_6_ENABLED CYBSP_A10_ENABLED
-#define CYBSP_A10_PORT GPIO_PRT9
-#define CYBSP_J2_6_PORT CYBSP_A10_PORT
-#define CYBSP_A10_PORT_NUM 9U
-#define CYBSP_J2_6_PORT_NUM CYBSP_A10_PORT_NUM
-#define CYBSP_A10_PIN 2U
-#define CYBSP_J2_6_PIN CYBSP_A10_PIN
-#define CYBSP_A10_NUM 2U
-#define CYBSP_J2_6_NUM CYBSP_A10_NUM
-#define CYBSP_A10_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_J2_6_DRIVEMODE CYBSP_A10_DRIVEMODE
-#define CYBSP_A10_INIT_DRIVESTATE 1
-#define CYBSP_J2_6_INIT_DRIVESTATE CYBSP_A10_INIT_DRIVESTATE
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT9
+#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
+#define CYBSP_CSD_SLD3_PORT_NUM 9U
+#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
+#define CYBSP_CSD_SLD3_PIN 2U
+#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
+#define CYBSP_CSD_SLD3_NUM 2U
+#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
 #ifndef ioss_0_port_9_pin_2_HSIOM
     #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_A10_HSIOM ioss_0_port_9_pin_2_HSIOM
-#define CYBSP_J2_6_HSIOM CYBSP_A10_HSIOM
-#define CYBSP_A10_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_J2_6_IRQ CYBSP_A10_IRQ
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_9_pin_2_HSIOM
+#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_A10_HAL_PORT_PIN P9_2
-    #define CYBSP_J2_6_HAL_PORT_PIN CYBSP_A10_HAL_PORT_PIN
-    #define CYBSP_A10 P9_2
-    #define CYBSP_J2_6 CYBSP_A10
-    #define CYBSP_A10_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_J2_6_HAL_IRQ CYBSP_A10_HAL_IRQ
-    #define CYBSP_A10_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_J2_6_HAL_DIR CYBSP_A10_HAL_DIR
-    #define CYBSP_A10_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_J2_6_HAL_DRIVEMODE CYBSP_A10_HAL_DRIVEMODE
+    #define CYBSP_CSD_SLD3_HAL_PORT_PIN P9_2
+    #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
+    #define CYBSP_CSD_SLD3 P9_2
+    #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
+    #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
+    #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
+    #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
-#define CYBSP_A11_ENABLED 1U
-#define CYBSP_J2_8_ENABLED CYBSP_A11_ENABLED
-#define CYBSP_TRACE_DATA0_ENABLED CYBSP_A11_ENABLED
-#define CYBSP_A11_PORT GPIO_PRT9
-#define CYBSP_J2_8_PORT CYBSP_A11_PORT
-#define CYBSP_TRACE_DATA0_PORT CYBSP_A11_PORT
-#define CYBSP_A11_PORT_NUM 9U
-#define CYBSP_J2_8_PORT_NUM CYBSP_A11_PORT_NUM
-#define CYBSP_TRACE_DATA0_PORT_NUM CYBSP_A11_PORT_NUM
-#define CYBSP_A11_PIN 3U
-#define CYBSP_J2_8_PIN CYBSP_A11_PIN
-#define CYBSP_TRACE_DATA0_PIN CYBSP_A11_PIN
-#define CYBSP_A11_NUM 3U
-#define CYBSP_J2_8_NUM CYBSP_A11_NUM
-#define CYBSP_TRACE_DATA0_NUM CYBSP_A11_NUM
-#define CYBSP_A11_DRIVEMODE CY_GPIO_DM_ANALOG
-#define CYBSP_J2_8_DRIVEMODE CYBSP_A11_DRIVEMODE
-#define CYBSP_TRACE_DATA0_DRIVEMODE CYBSP_A11_DRIVEMODE
-#define CYBSP_A11_INIT_DRIVESTATE 1
-#define CYBSP_J2_8_INIT_DRIVESTATE CYBSP_A11_INIT_DRIVESTATE
-#define CYBSP_TRACE_DATA0_INIT_DRIVESTATE CYBSP_A11_INIT_DRIVESTATE
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT9
+#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
+#define CYBSP_CSD_SLD4_PORT_NUM 9U
+#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
+#define CYBSP_CSD_SLD4_PIN 3U
+#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
+#define CYBSP_CSD_SLD4_NUM 3U
+#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
 #ifndef ioss_0_port_9_pin_3_HSIOM
     #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_A11_HSIOM ioss_0_port_9_pin_3_HSIOM
-#define CYBSP_J2_8_HSIOM CYBSP_A11_HSIOM
-#define CYBSP_TRACE_DATA0_HSIOM CYBSP_A11_HSIOM
-#define CYBSP_A11_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_J2_8_IRQ CYBSP_A11_IRQ
-#define CYBSP_TRACE_DATA0_IRQ CYBSP_A11_IRQ
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_9_pin_3_HSIOM
+#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
 #if defined (CY_USING_HAL)
-    #define CYBSP_A11_HAL_PORT_PIN P9_3
-    #define CYBSP_J2_8_HAL_PORT_PIN CYBSP_A11_HAL_PORT_PIN
-    #define CYBSP_TRACE_DATA0_HAL_PORT_PIN CYBSP_A11_HAL_PORT_PIN
-    #define CYBSP_A11 P9_3
-    #define CYBSP_J2_8 CYBSP_A11
-    #define CYBSP_TRACE_DATA0 CYBSP_A11
-    #define CYBSP_A11_HAL_IRQ CYHAL_GPIO_IRQ_NONE
-    #define CYBSP_J2_8_HAL_IRQ CYBSP_A11_HAL_IRQ
-    #define CYBSP_TRACE_DATA0_HAL_IRQ CYBSP_A11_HAL_IRQ
-    #define CYBSP_A11_HAL_DIR CYHAL_GPIO_DIR_INPUT 
-    #define CYBSP_J2_8_HAL_DIR CYBSP_A11_HAL_DIR
-    #define CYBSP_TRACE_DATA0_HAL_DIR CYBSP_A11_HAL_DIR
-    #define CYBSP_A11_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
-    #define CYBSP_J2_8_HAL_DRIVEMODE CYBSP_A11_HAL_DRIVEMODE
-    #define CYBSP_TRACE_DATA0_HAL_DRIVEMODE CYBSP_A11_HAL_DRIVEMODE
+    #define CYBSP_CSD_SLD4_HAL_PORT_PIN P9_3
+    #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
+    #define CYBSP_CSD_SLD4 P9_3
+    #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
+    #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
+    #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT 
+    #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
+    #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
 #endif //defined (CY_USING_HAL)
 
 extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
@@ -406,47 +359,39 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
 #if defined (CY_USING_HAL)
     extern const cyhal_resource_inst_t CYBSP_CINB_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_LED_RGB_BLUE_config;
-#define CYBSP_USER_LED5_config CYBSP_LED_RGB_BLUE_config
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_LED_RGB_BLUE_obj;
-    #define CYBSP_USER_LED5_obj CYBSP_LED_RGB_BLUE_obj
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+    #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
 #endif //defined (CY_USING_HAL)
 extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
 #if defined (CY_USING_HAL)
     extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
-#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
-#if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
-    #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
-#endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_A8_config;
-#define CYBSP_J2_2_config CYBSP_A8_config
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_A8_obj;
-    #define CYBSP_J2_2_obj CYBSP_A8_obj
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+    #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_A9_config;
-#define CYBSP_J2_4_config CYBSP_A9_config
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_A9_obj;
-    #define CYBSP_J2_4_obj CYBSP_A9_obj
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+    #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_A10_config;
-#define CYBSP_J2_6_config CYBSP_A10_config
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_A10_obj;
-    #define CYBSP_J2_6_obj CYBSP_A10_obj
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+    #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
 #endif //defined (CY_USING_HAL)
-extern const cy_stc_gpio_pin_config_t CYBSP_A11_config;
-#define CYBSP_J2_8_config CYBSP_A11_config
-#define CYBSP_TRACE_DATA0_config CYBSP_A11_config
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
 #if defined (CY_USING_HAL)
-    extern const cyhal_resource_inst_t CYBSP_A11_obj;
-    #define CYBSP_J2_8_obj CYBSP_A11_obj
-    #define CYBSP_TRACE_DATA0_obj CYBSP_A11_obj
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+    #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
 #endif //defined (CY_USING_HAL)
 
 void init_cycfg_pins(void);

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_qspi_memslot.c

@@ -4,10 +4,10 @@
 * Description:
 * Provides definitions of the SMIF-driver memory configuration.
 * This file was automatically generated and should not be modified.
-* QSPI Configurator 4.10.0.1343
+* QSPI Configurator 4.0.0.985
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -60,7 +60,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -98,7 +98,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -136,7 +136,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -174,7 +174,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -212,7 +212,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -250,7 +250,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -288,7 +288,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -326,7 +326,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -364,7 +364,7 @@ const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
     /* The high byte of a 16-bit command. This value is 0x0 when there is no higher byte command present */
     .commandH = 0x00,
     /* The Data rate of command */
-    .cmdRate = CY_SMIF_SDR,
+    .cmdRate = CY_SMIF_SDR
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
@@ -409,29 +409,7 @@ const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
 #if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
     /* Points to NULL or to structure with info about sectors for hybrid memory. */
     .hybridRegionCount = 0U,
-    .hybridRegionInfo = 0,
-#endif
-    /* Specifies the command to read variable latency cycles configuration register */
-    .readLatencyCmd = 0,
-    /* Specifies the command to write variable latency cycles configuration register */
-    .writeLatencyCmd = 0,
-    /* Specifies the address for variable latency cycle address */
-    .latencyCyclesRegAddr = 0x00U,
-    /* Specifies variable latency cycles Mask */
-    .latencyCyclesMask = 0x00U,
-#if (CY_IP_MXSMIF_VERSION >= 2)
-    /* Specifies data for memory with hybrid sectors */
-    .octalDDREnableSeq = 0,
-    /* Specifies the command to read the OE-containing status register. */
-    .readStsRegOeCmd = 0,
-    /* Specifies the command to write the OE-containing status register. */
-    .writeStsRegOeCmd = 0,
-    /* QE mask for the status registers */
-    .stsRegOctalEnableMask = 0x00U,
-    /* Octal enable register address */
-    .octalEnableRegAddr = 0x00U,
-    /* Frequency of operation used in Octal mode */
-    .freq_of_operation = CY_SMIF_100MHZ_OPERATION,
+    .hybridRegionInfo = NULL
 #endif
 };
 
@@ -463,12 +441,12 @@ const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
      * After this period the memory device is deselected. A later transfer, even from a
      * continuous address, starts with the overhead phases (command, address, mode, dummy cycles).
      * This configuration parameter is available for CAT1B devices. */
-    .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE,
+    .mergeTimeout = CY_SMIF_MERGE_TIMEOUT_1_CYCLE
 #endif /* CY_IP_MXSMIF_VERSION */
 };
 
 const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM] = {
-   &S25FL512S_SlaveSlot_0,
+   &S25FL512S_SlaveSlot_0
 };
 
 const cy_stc_smif_block_config_t smifBlockConfig =
@@ -480,5 +458,5 @@ const cy_stc_smif_block_config_t smifBlockConfig =
     /* The version of the SMIF driver. */
     .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
     /* The version of the SMIF driver. */
-    .minorVersion = CY_SMIF_DRV_VERSION_MINOR,
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
 };

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_qspi_memslot.h

@@ -4,10 +4,10 @@
 * Description:
 * Provides declarations of the SMIF-driver memory configuration.
 * This file was automatically generated and should not be modified.
-* QSPI Configurator 4.10.0.1343
+* QSPI Configurator 4.0.0.985
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -28,7 +28,7 @@
 #define CYCFG_QSPI_MEMSLOT_H
 #include "cy_smif_memslot.h"
 
-#define CY_SMIF_CFG_TOOL_VERSION           (410)
+#define CY_SMIF_CFG_TOOL_VERSION           (400)
 
 /* Supported QSPI Driver version */
 #define CY_SMIF_DRV_VERSION_REQUIRED       (100)
@@ -42,9 +42,6 @@
    #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
 #endif
 
-typedef cy_stc_smif_mem_config_t cy_serial_flash_mem_config_t;
-typedef cy_stc_smif_block_config_t cy_serial_flash_block_config_t;
-
 #define CY_SMIF_DEVICE_NUM 1
 
 extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_qspi_memslot.timestamp

@@ -1,26 +0,0 @@
-/*******************************************************************************
-* File Name: cycfg_qspi_memslot.timestamp
-*
-* Description:
-* Sentinel file for determining if generated source is up to date.
-* This file was automatically generated and should not be modified.
-* QSPI Configurator 4.10.0.1343
-*
-********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
-* an affiliate of Cypress Semiconductor Corporation.
-* SPDX-License-Identifier: Apache-2.0
-*
-* Licensed under the Apache License, Version 2.0 (the "License");
-* you may not use this file except in compliance with the License.
-* You may obtain a copy of the License at
-*
-*     http://www.apache.org/licenses/LICENSE-2.0
-*
-* Unless required by applicable law or agreed to in writing, software
-* distributed under the License is distributed on an "AS IS" BASIS,
-* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-* See the License for the specific language governing permissions and
-* limitations under the License.
-********************************************************************************/
-

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_routing.c

@@ -5,11 +5,11 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_routing.h

@@ -5,11 +5,11 @@
 * Establishes all necessary connections between hardware elements.
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_system.c

@@ -5,11 +5,11 @@
 * System configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -58,6 +58,18 @@
 #define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
 #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF1_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF3_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_CLKHF4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF4_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
 #define CY_CFG_SYSCLK_ILO_ENABLED 1
 #define CY_CFG_SYSCLK_ILO_HIBERNATE true
 #define CY_CFG_SYSCLK_IMO_ENABLED 1
@@ -89,6 +101,13 @@
 #define CY_CFG_SYSCLK_PLL0_LF_MODE false
 #define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
 #define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
+#define CY_CFG_SYSCLK_PLL1_ENABLED 1
+#define CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV 25
+#define CY_CFG_SYSCLK_PLL1_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_DIV 2
+#define CY_CFG_SYSCLK_PLL1_LF_MODE false
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ 100000000
 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
 #define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
@@ -168,6 +187,14 @@
         .lfMode = false,
         .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
     };
+    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig = 
+    {
+        .feedbackDiv = 25,
+        .referenceDiv = 1,
+        .outputDiv = 2,
+        .lfMode = false,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    };
 #endif //(!defined(CY_DEVICE_SECURE))
 
 __WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
@@ -682,6 +709,24 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
         Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
         Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
     }
+    __STATIC_INLINE void Cy_SysClk_ClkHf1Init()
+    {
+        Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF1, CY_CFG_SYSCLK_CLKHF1_CLKPATH);
+        Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF1, CY_SYSCLK_CLKHF_NO_DIVIDE);
+        Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF1);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkHf3Init()
+    {
+        Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF3, CY_CFG_SYSCLK_CLKHF3_CLKPATH);
+        Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF3, CY_SYSCLK_CLKHF_NO_DIVIDE);
+        Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF3);
+    }
+    __STATIC_INLINE void Cy_SysClk_ClkHf4Init()
+    {
+        Cy_SysClk_ClkHfSetSource(CY_CFG_SYSCLK_CLKHF4, CY_CFG_SYSCLK_CLKHF4_CLKPATH);
+        Cy_SysClk_ClkHfSetDivider(CY_CFG_SYSCLK_CLKHF4, CY_SYSCLK_CLKHF_NO_DIVIDE);
+        Cy_SysClk_ClkHfEnable(CY_CFG_SYSCLK_CLKHF4);
+    }
     __STATIC_INLINE void Cy_SysClk_IloInit()
     {
         /* The WDT is unlocked in the default startup code */
@@ -732,6 +777,17 @@ __STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
             cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
         }
     }
+    __STATIC_INLINE void Cy_SysClk_Pll1Init()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(2U, &srss_0_clock_0_pll_1_pllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(2U, 10000u))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+    }
     __STATIC_INLINE void Cy_SysClk_ClkSlowInit()
     {
         Cy_SysClk_ClkSlowSetDivider(0U);

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/cycfg_system.h

@@ -5,11 +5,11 @@
 * System configuration
 * This file was automatically generated and should not be modified.
 * Configurator Backend 3.0.0
-* device-db 4.3.0.3855
-* mtb-pdl-cat1 3.4.0.24948
+* device-db 4.26.0.8600
+* mtb-pdl-cat1 3.16.0.40964
 *
 ********************************************************************************
-* Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+* Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 * an affiliate of Cypress Semiconductor Corporation.
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -52,6 +52,15 @@ extern "C" {
 #define srss_0_clock_0_hfclk_0_ENABLED 1U
 #define CY_CFG_SYSCLK_CLKHF0 0UL
 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_1_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF1 1UL
+#define CY_CFG_SYSCLK_CLKHF1_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_3_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF3 3UL
+#define CY_CFG_SYSCLK_CLKHF3_CLKPATH_NUM 0UL
+#define srss_0_clock_0_hfclk_4_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF4 4UL
+#define CY_CFG_SYSCLK_CLKHF4_CLKPATH_NUM 0UL
 #define srss_0_clock_0_ilo_0_ENABLED 1U
 #define srss_0_clock_0_imo_0_ENABLED 1U
 #define srss_0_clock_0_lfclk_0_ENABLED 1U
@@ -65,6 +74,7 @@ extern "C" {
 #define srss_0_clock_0_pathmux_5_ENABLED 1U
 #define srss_0_clock_0_periclk_0_ENABLED 1U
 #define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_pll_1_ENABLED 1U
 #define srss_0_clock_0_slowclk_0_ENABLED 1U
 #define srss_0_clock_0_timerclk_0_ENABLED 1U
 #define srss_0_power_0_ENABLED 1U

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/GeneratedSource/qspi_config.cfg

@@ -4,10 +4,10 @@
 # Description:
 # This file contains a SMIF Bank layout for use with OpenOCD.
 # This file was automatically generated and should not be modified.
-# QSPI Configurator: 4.10.0.1343
+# QSPI Configurator: 4.0.0.985
 #
 ################################################################################
-# Copyright 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# Copyright 2025 Cypress Semiconductor Corporation (an Infineon company) or
 # an affiliate of Cypress Semiconductor Corporation.
 # SPDX-License-Identifier: Apache-2.0
 #

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/design.cycapsense

@@ -95,198 +95,6 @@
         <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
     </CsxProperties>
     <Widgets>
-        <Widget id="Button0" type="CSD_BUTTON">
-            <WidgetProperties>
-                <Property id="DIPLEXING" value="false"/>
-                <Property id="MAX_POS_X" value="100"/>
-                <Property id="MAX_POS_Y" value="100"/>
-                <Property id="FINGER_CP" value="0.16"/>
-                <Property id="SNS_CLK" value="4"/>
-                <Property id="ROW_SNS_CLK" value="4"/>
-                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
-                <Property id="TX_CLK" value="4"/>
-                <Property id="TX_CLK_SOURCE" value="AUTO"/>
-                <Property id="RESOLUTION" value="RES12BIT"/>
-                <Property id="NUM_CONV" value="100"/>
-                <Property id="IDAC_MOD0" value="32"/>
-                <Property id="IDAC_MOD1" value="32"/>
-                <Property id="IDAC_MOD2" value="32"/>
-                <Property id="ROW_IDAC_MOD0" value="32"/>
-                <Property id="ROW_IDAC_MOD1" value="32"/>
-                <Property id="ROW_IDAC_MOD2" value="32"/>
-                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
-                <Property id="MAX_RAW_COUNT" value="0"/>
-                <Property id="ROW_MAX_RAW_COUNT" value="0"/>
-                <Property id="FINGER_TH" value="100"/>
-                <Property id="PROX_TOUCH_TH" value="200"/>
-                <Property id="NOISE_TH" value="40"/>
-                <Property id="NNOISE_TH" value="40"/>
-                <Property id="LOW_BSLN_RST" value="30"/>
-                <Property id="HYSTERESIS" value="10"/>
-                <Property id="ON_DEBOUNCE" value="3"/>
-                <Property id="VELOCITY" value="2500"/>
-                <Property id="IIR_FILTER" value="false"/>
-                <Property id="IIR_FILTER_COEFF" value="128"/>
-                <Property id="MEDIAN_FILTER" value="false"/>
-                <Property id="AVG_FILTER" value="false"/>
-                <Property id="JITTER_FILTER" value="false"/>
-                <Property id="AIIR_FILTER" value="false"/>
-                <Property id="AIIR_NO_MOV_TH" value="3"/>
-                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
-                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
-                <Property id="AIIR_MAXK" value="60"/>
-                <Property id="AIIR_MINK" value="1"/>
-                <Property id="AIIR_DIV_VAL" value="64"/>
-                <Property id="CENTROID_TYPE" value="CSD3X3"/>
-                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
-                <Property id="EDGE_CORRECTION" value="true"/>
-                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
-                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
-                <Property id="TWO_FINGER_DETECTION" value="false"/>
-                <Property id="BALLISTIC_MULT" value="false"/>
-                <Property id="ACCEL_COEFF" value="9"/>
-                <Property id="SPEED_COEFF" value="2"/>
-                <Property id="DIVISOR" value="4"/>
-                <Property id="SPEED_TH_X" value="3"/>
-                <Property id="SPEED_TH_Y" value="4"/>
-                <Property id="GESTURE_ENABLE" value="false"/>
-                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
-                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
-                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
-                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
-                <Property id="CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
-                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
-                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SCROLL_DEBOUNCE" value="3"/>
-                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
-                <Property id="ROTATE_DEBOUNCE" value="10"/>
-                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
-                <Property id="ZOOM_DEBOUNCE" value="3"/>
-                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
-                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
-                <Property id="FLICK_DISTANCE_MIN" value="100"/>
-                <Property id="EDGE_EDGE_SIZE" value="200"/>
-                <Property id="EDGE_DISTANCE_MIN" value="200"/>
-                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
-                <Property id="EDGE_ANGLE_MAX" value="45"/>
-            </WidgetProperties>
-            <Electrodes>
-                <Electrode id="Sns0" kind="Sensor">
-                    <ElectrodeProperties>
-                        <Property id="IDAC0" value="32"/>
-                        <Property id="IDAC1" value="32"/>
-                        <Property id="IDAC2" value="32"/>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-            </Electrodes>
-        </Widget>
-        <Widget id="Button1" type="CSD_BUTTON">
-            <WidgetProperties>
-                <Property id="DIPLEXING" value="false"/>
-                <Property id="MAX_POS_X" value="100"/>
-                <Property id="MAX_POS_Y" value="100"/>
-                <Property id="FINGER_CP" value="0.16"/>
-                <Property id="SNS_CLK" value="4"/>
-                <Property id="ROW_SNS_CLK" value="4"/>
-                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
-                <Property id="TX_CLK" value="4"/>
-                <Property id="TX_CLK_SOURCE" value="AUTO"/>
-                <Property id="RESOLUTION" value="RES12BIT"/>
-                <Property id="NUM_CONV" value="100"/>
-                <Property id="IDAC_MOD0" value="32"/>
-                <Property id="IDAC_MOD1" value="32"/>
-                <Property id="IDAC_MOD2" value="32"/>
-                <Property id="ROW_IDAC_MOD0" value="32"/>
-                <Property id="ROW_IDAC_MOD1" value="32"/>
-                <Property id="ROW_IDAC_MOD2" value="32"/>
-                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
-                <Property id="MAX_RAW_COUNT" value="0"/>
-                <Property id="ROW_MAX_RAW_COUNT" value="0"/>
-                <Property id="FINGER_TH" value="100"/>
-                <Property id="PROX_TOUCH_TH" value="200"/>
-                <Property id="NOISE_TH" value="40"/>
-                <Property id="NNOISE_TH" value="40"/>
-                <Property id="LOW_BSLN_RST" value="30"/>
-                <Property id="HYSTERESIS" value="10"/>
-                <Property id="ON_DEBOUNCE" value="3"/>
-                <Property id="VELOCITY" value="2500"/>
-                <Property id="IIR_FILTER" value="false"/>
-                <Property id="IIR_FILTER_COEFF" value="128"/>
-                <Property id="MEDIAN_FILTER" value="false"/>
-                <Property id="AVG_FILTER" value="false"/>
-                <Property id="JITTER_FILTER" value="false"/>
-                <Property id="AIIR_FILTER" value="false"/>
-                <Property id="AIIR_NO_MOV_TH" value="3"/>
-                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
-                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
-                <Property id="AIIR_MAXK" value="60"/>
-                <Property id="AIIR_MINK" value="1"/>
-                <Property id="AIIR_DIV_VAL" value="64"/>
-                <Property id="CENTROID_TYPE" value="CSD3X3"/>
-                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
-                <Property id="EDGE_CORRECTION" value="true"/>
-                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
-                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
-                <Property id="TWO_FINGER_DETECTION" value="false"/>
-                <Property id="BALLISTIC_MULT" value="false"/>
-                <Property id="ACCEL_COEFF" value="9"/>
-                <Property id="SPEED_COEFF" value="2"/>
-                <Property id="DIVISOR" value="4"/>
-                <Property id="SPEED_TH_X" value="3"/>
-                <Property id="SPEED_TH_Y" value="4"/>
-                <Property id="GESTURE_ENABLE" value="false"/>
-                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
-                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
-                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
-                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
-                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
-                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
-                <Property id="CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
-                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
-                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
-                <Property id="SCROLL_DEBOUNCE" value="3"/>
-                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
-                <Property id="ROTATE_DEBOUNCE" value="10"/>
-                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
-                <Property id="ZOOM_DEBOUNCE" value="3"/>
-                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
-                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
-                <Property id="FLICK_DISTANCE_MIN" value="100"/>
-                <Property id="EDGE_EDGE_SIZE" value="200"/>
-                <Property id="EDGE_DISTANCE_MIN" value="200"/>
-                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
-                <Property id="EDGE_ANGLE_MAX" value="45"/>
-            </WidgetProperties>
-            <Electrodes>
-                <Electrode id="Sns0" kind="Sensor">
-                    <ElectrodeProperties>
-                        <Property id="IDAC0" value="32"/>
-                        <Property id="IDAC1" value="32"/>
-                        <Property id="IDAC2" value="32"/>
-                        <Property id="PINS" value="Dedicated pin"/>
-                    </ElectrodeProperties>
-                </Electrode>
-            </Electrodes>
-        </Widget>
         <Widget id="LinearSlider0" type="LINEAR_SLIDER">
             <WidgetProperties>
                 <Property id="DIPLEXING" value="false"/>

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/design.cyqspi

@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
-<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.3018-->
 <Configuration app="QSPI" major="2" minor="20">
     <DevicePath>PSoC 6.xml</DevicePath>
     <SlotConfigs>

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/config/design.modus

@@ -15,16 +15,14 @@
                     <Personality template="mxs40csd" version="3.0">
                         <Param id="CapSenseEnable" value="true"/>
                         <Param id="CapSenseCore" value="4"/>
-                        <Param id="SensorCount" value="8"/>
+                        <Param id="SensorCount" value="6"/>
                         <Param id="CapacitorCount" value="1"/>
                         <Param id="SensorName0" value="Cmod"/>
-                        <Param id="SensorName1" value="Button0_Sns0"/>
-                        <Param id="SensorName2" value="Button1_Sns0"/>
-                        <Param id="SensorName3" value="LinearSlider0_Sns0"/>
-                        <Param id="SensorName4" value="LinearSlider0_Sns1"/>
-                        <Param id="SensorName5" value="LinearSlider0_Sns2"/>
-                        <Param id="SensorName6" value="LinearSlider0_Sns3"/>
-                        <Param id="SensorName7" value="LinearSlider0_Sns4"/>
+                        <Param id="SensorName1" value="LinearSlider0_Sns0"/>
+                        <Param id="SensorName2" value="LinearSlider0_Sns1"/>
+                        <Param id="SensorName3" value="LinearSlider0_Sns2"/>
+                        <Param id="SensorName4" value="LinearSlider0_Sns3"/>
+                        <Param id="SensorName5" value="LinearSlider0_Sns4"/>
                         <Param id="CapSenseConfigurator" value="0"/>
                         <Param id="CapSenseTuner" value="0"/>
                         <Param id="CsdAdcEnable" value="false"/>
@@ -51,12 +49,14 @@
                 <Block location="ioss[0].port[0].pin[1]">
                     <Alias value="CYBSP_USER_LED2"/>
                 </Block>
+                <Block location="ioss[0].port[0].pin[2]"/>
+                <Block location="ioss[0].port[0].pin[3]"/>
                 <Block location="ioss[0].port[0].pin[4]">
                     <Alias value="CYBSP_SW2"/>
                     <Alias value="CYBSP_USER_BTN1"/>
                 </Block>
                 <Block location="ioss[0].port[0].pin[5]">
-                    <Alias value="CYBSP_LED_RGB_GREEN"/>
+                    <Alias value="CYBSP_D8"/>
                 </Block>
                 <Block location="ioss[0].port[10].pin[0]">
                     <Alias value="CYBSP_A0"/>
@@ -90,10 +90,12 @@
                 <Block location="ioss[0].port[10].pin[7]">
                     <Alias value="CYBSP_A7"/>
                     <Alias value="CYBSP_J2_15"/>
+                    <Alias value="CYBSP_MIKROBUS_AN"/>
                 </Block>
                 <Block location="ioss[0].port[11].pin[0]">
                     <Alias value="CYBSP_QSPI_FRAM_SSEL"/>
                 </Block>
+                <Block location="ioss[0].port[11].pin[1]"/>
                 <Block location="ioss[0].port[11].pin[2]">
                     <Alias value="CYBSP_QSPI_SS"/>
                     <Alias value="CYBSP_QSPI_FLASH_SSEL"/>
@@ -150,26 +152,38 @@
                 <Block location="ioss[0].port[13].pin[3]">
                     <Alias value="CYBSP_SDHC_IO3"/>
                 </Block>
+                <Block location="ioss[0].port[13].pin[4]">
+                    <Alias value="CYBSP_MIKROBUS_UART_RX"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[5]">
+                    <Alias value="CYBSP_MIKROBUS_UART_TX"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[6]">
+                    <Alias value="CYBSP_USER_LED2"/>
+                </Block>
                 <Block location="ioss[0].port[13].pin[7]">
                     <Alias value="CYBSP_SDHC_DETECT"/>
                 </Block>
                 <Block location="ioss[0].port[1].pin[0]">
-                    <Alias value="CYBSP_CSD_RX"/>
-                    <Alias value="CYBSP_CS_RX"/>
-                    <Alias value="CYBSP_CS_TX_RX"/>
+                    <Alias value="CYBSP_MIKROBUS_SPI_MOSI"/>
                 </Block>
                 <Block location="ioss[0].port[1].pin[1]">
-                    <Alias value="CYBSP_LED_RGB_RED"/>
-                    <Alias value="CYBSP_USER_LED3"/>
+                    <Alias value="CYBSP_MIKROBUS_SPI_MISO"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[2]">
+                    <Alias value="CYBSP_MIKROBUS_SPI_SCK"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[3]">
+                    <Alias value="CYBSP_MIKROBUS_SPI_CS"/>
                 </Block>
                 <Block location="ioss[0].port[1].pin[4]">
                     <Alias value="CYBSP_SW4"/>
                     <Alias value="CYBSP_USER_BTN2"/>
                 </Block>
                 <Block location="ioss[0].port[1].pin[5]">
-                    <Alias value="CYBSP_LED8"/>
-                    <Alias value="CYBSP_USER_LED1"/>
-                    <Alias value="CYBSP_USER_LED"/>
+                    <Alias value="CYBSP_CSD_RX"/>
+                    <Alias value="CYBSP_CS_RX"/>
+                    <Alias value="CYBSP_CS_TX_RX"/>
                 </Block>
                 <Block location="ioss[0].port[2].pin[0]">
                     <Alias value="CYBSP_WIFI_SDIO_D0"/>
@@ -189,9 +203,16 @@
                 <Block location="ioss[0].port[2].pin[5]">
                     <Alias value="CYBSP_WIFI_SDIO_CLK"/>
                 </Block>
+                <Block location="ioss[0].port[2].pin[6]"/>
                 <Block location="ioss[0].port[2].pin[7]">
                     <Alias value="CYBSP_WIFI_WL_REG_ON"/>
                 </Block>
+                <Block location="ioss[0].port[3].pin[0]">
+                    <Alias value="CYBSP_BT_UART_RX"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[1]">
+                    <Alias value="CYBSP_BT_UART_TX"/>
+                </Block>
                 <Block location="ioss[0].port[3].pin[2]">
                     <Alias value="CYBSP_BT_UART_RTS"/>
                 </Block>
@@ -217,11 +238,9 @@
                     <Alias value="CYBSP_D1"/>
                 </Block>
                 <Block location="ioss[0].port[5].pin[2]">
-                    <Alias value="CYBSP_DEBUG_UART_RTS"/>
                     <Alias value="CYBSP_D2"/>
                 </Block>
                 <Block location="ioss[0].port[5].pin[3]">
-                    <Alias value="CYBSP_DEBUG_UART_CTS"/>
                     <Alias value="CYBSP_D3"/>
                 </Block>
                 <Block location="ioss[0].port[5].pin[4]">
@@ -239,14 +258,19 @@
                 <Block location="ioss[0].port[6].pin[0]">
                     <Alias value="CYBSP_I2C_SCL"/>
                     <Alias value="CYBSP_D15"/>
+                    <Alias value="CYBSP_MIKROBUS_I2C_SCL"/>
+                    <Alias value="CYBSP_TRUSTM_I2C_SCL"/>
                 </Block>
                 <Block location="ioss[0].port[6].pin[1]">
                     <Alias value="CYBSP_I2C_SDA"/>
                     <Alias value="CYBSP_D14"/>
+                    <Alias value="CYBSP_MIKROBUS_I2C_SDA"/>
+                    <Alias value="CYBSP_TRUSTM_I2C_SDA"/>
                 </Block>
                 <Block location="ioss[0].port[6].pin[2]">
                     <Alias value="CYBSP_USER_BTN"/>
                 </Block>
+                <Block location="ioss[0].port[6].pin[3]"/>
                 <Block location="ioss[0].port[6].pin[4]">
                     <Alias value="CYBSP_DEBUG_UART_RX"/>
                 </Block>
@@ -317,8 +341,8 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[7].pin[3]">
-                    <Alias value="CYBSP_LED_RGB_BLUE"/>
-                    <Alias value="CYBSP_USER_LED5"/>
+                    <Alias value="CYBSP_CSD_SLD0"/>
+                    <Alias value="CYBSP_CS_SLD0"/>
                     <Personality template="pin" version="3.0">
                         <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                         <Param id="initialState" value="1"/>
@@ -332,16 +356,11 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[7].pin[4]">
-                    <Alias value="CYBSP_TRACE_DATA3"/>
-                </Block>
                 <Block location="ioss[0].port[7].pin[5]">
-                    <Alias value="CYBSP_D8"/>
-                    <Alias value="CYBSP_TRACE_DATA2"/>
+                    <Alias value="CYBSP_MIKROBUS_RST"/>
                 </Block>
                 <Block location="ioss[0].port[7].pin[6]">
                     <Alias value="CYBSP_D9"/>
-                    <Alias value="CYBSP_TRACE_DATA1"/>
                 </Block>
                 <Block location="ioss[0].port[7].pin[7]">
                     <Alias value="CYBSP_CMOD"/>
@@ -358,22 +377,6 @@
                         <Param id="inFlash" value="true"/>
                     </Personality>
                 </Block>
-                <Block location="ioss[0].port[8].pin[1]">
-                    <Alias value="CYBSP_CSD_BTN0"/>
-                    <Alias value="CYBSP_CS_BTN0"/>
-                    <Personality template="pin" version="3.0">
-                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
-                        <Param id="initialState" value="1"/>
-                        <Param id="nonSec" value="1"/>
-                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
-                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
-                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
-                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
-                        <Param id="sioOutputBuffer" value="true"/>
-                        <Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
-                        <Param id="inFlash" value="true"/>
-                    </Personality>
-                </Block>
                 <Block location="ioss[0].port[8].pin[2]">
                     <Alias value="CYBSP_CSD_BTN1"/>
                     <Alias value="CYBSP_CS_BTN1"/>
@@ -399,8 +402,8 @@
                     <Alias value="CYBSP_CS_SLD4"/>
                 </Block>
                 <Block location="ioss[0].port[9].pin[0]">
-                    <Alias value="CYBSP_A8"/>
-                    <Alias value="CYBSP_J2_2"/>
+                    <Alias value="CYBSP_CSD_SLD1"/>
+                    <Alias value="CYBSP_CS_SLD1"/>
                     <Personality template="pin" version="3.0">
                         <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                         <Param id="initialState" value="1"/>
@@ -415,8 +418,8 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[9].pin[1]">
-                    <Alias value="CYBSP_A9"/>
-                    <Alias value="CYBSP_J2_4"/>
+                    <Alias value="CYBSP_CSD_SLD2"/>
+                    <Alias value="CYBSP_CS_SLD2"/>
                     <Personality template="pin" version="3.0">
                         <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                         <Param id="initialState" value="1"/>
@@ -431,8 +434,8 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[9].pin[2]">
-                    <Alias value="CYBSP_A10"/>
-                    <Alias value="CYBSP_J2_6"/>
+                    <Alias value="CYBSP_CSD_SLD3"/>
+                    <Alias value="CYBSP_CS_SLD3"/>
                     <Personality template="pin" version="3.0">
                         <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                         <Param id="initialState" value="1"/>
@@ -447,9 +450,8 @@
                     </Personality>
                 </Block>
                 <Block location="ioss[0].port[9].pin[3]">
-                    <Alias value="CYBSP_A11"/>
-                    <Alias value="CYBSP_J2_8"/>
-                    <Alias value="CYBSP_TRACE_DATA0"/>
+                    <Alias value="CYBSP_CSD_SLD4"/>
+                    <Alias value="CYBSP_CS_SLD4"/>
                     <Personality template="pin" version="3.0">
                         <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
                         <Param id="initialState" value="1"/>
@@ -474,10 +476,13 @@
                 <Block location="ioss[0].port[9].pin[6]">
                     <Alias value="CYBSP_A14"/>
                     <Alias value="CYBSP_J2_14"/>
+                    <Alias value="CYBSP_TRUSTM_VDD"/>
                 </Block>
                 <Block location="ioss[0].port[9].pin[7]">
                     <Alias value="CYBSP_A15"/>
                     <Alias value="CYBSP_J2_16"/>
+                    <Alias value="CYBSP_LED_RGB_GREEN"/>
+                    <Alias value="CYBSP_USER_LED4"/>
                 </Block>
                 <Block location="peri[0].div_16[15]">
                     <Personality template="pclk" version="3.0">
@@ -537,6 +542,24 @@
                         <Param id="divider" value="1"/>
                     </Personality>
                 </Block>
+                <Block location="srss[0].clock[0].hfclk[1]">
+                    <Personality template="hfclk" version="3.0">
+                        <Param id="sourceClockNumber" value="0"/>
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[3]">
+                    <Personality template="hfclk" version="3.0">
+                        <Param id="sourceClockNumber" value="0"/>
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[4]">
+                    <Personality template="hfclk" version="3.0">
+                        <Param id="sourceClockNumber" value="0"/>
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
                 <Block location="srss[0].clock[0].ilo[0]">
                     <Personality template="ilo" version="3.0">
                         <Param id="hibernate" value="true"/>
@@ -656,12 +679,6 @@
                     <Arm>
                         <Port name="ioss[0].port[9].pin[3].analog[0]"/>
                     </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[9].pin[0].analog[0]"/>
-                    </Arm>
-                    <Arm>
-                        <Port name="ioss[0].port[9].pin[1].analog[0]"/>
-                    </Arm>
                 </Mux>
             </Netlist>
         </Device>

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/cybsp.c

@@ -32,7 +32,7 @@
 #if defined(CY_USING_HAL)
 #include "cyhal_hwmgr.h"
 #include "cyhal_syspm.h"
-
+#include "cyhal_system.h"
 #if defined(CYBSP_WIFI_CAPABLE) && defined(CYHAL_UDB_SIO)
 #include "SDIO_HOST.h"
 #endif
@@ -89,26 +89,32 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void)
 //--------------------------------------------------------------------------------------------------
 cy_rslt_t cybsp_init(void)
 {
+    #if defined(CY_USING_HAL)
     // Setup hardware manager to track resource usage then initialize all system (clock/power) board
     // configuration
-    #if defined(CY_USING_HAL)
     cy_rslt_t result = cyhal_hwmgr_init();
 
     if (CY_RSLT_SUCCESS == result)
     {
         result = cyhal_syspm_init();
     }
+    #else // if defined(CY_USING_HAL)
+    cy_rslt_t result = CY_RSLT_SUCCESS;
+    #endif /* defined(CY_USING_HAL) */
 
     #ifdef CY_CFG_PWR_VDDA_MV
     if (CY_RSLT_SUCCESS == result)
     {
+        #if defined(CY_USING_HAL)
+        // Old versions of classic HAL have this API in the Syspm HAL. In versions of HAL which
+        // support HAL-Lite configuration, this is moved to the System HAL, with compatibility
+        // macros that exist in classic HAL configuration only (HAL-Lite configuration does
+        // not include SysPm HAL)
         cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV);
+        #endif
     }
-    #endif
+    #endif // ifdef CY_CFG_PWR_VDDA_MV
 
-    #else // if defined(CY_USING_HAL)
-    cy_rslt_t result = CY_RSLT_SUCCESS;
-    #endif // if defined(CY_USING_HAL)
 
     // By default, the peripheral configuration will be done on the first core running user code.
     // This is the CM0+ if it is available and not running a pre-built image, and the CM4 otherwise.

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/cybsp_doc.h

@@ -357,11 +357,15 @@ extern "C" {
 /** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE
  */
 
+#ifndef CYBSP_WIFI_HOST_WAKE_GPIO_DM
 /** WiFi host-wake GPIO drive mode */
 #define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG)
+#endif
+#ifndef CYBSP_WIFI_HOST_WAKE_IRQ_EVENT
 /** WiFi host-wake IRQ event */
 #define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE)
 #endif
+#endif // ifdef CYBSP_WIFI_HOST_WAKE
 #ifdef CYBSP_BT_UART_RX
 /** Pin: BT UART RX \def CYBSP_BT_UART_RX
  */

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/cybsp_types.h

@@ -20,6 +20,7 @@
 
 #pragma once
 
+#include "cybsp_hw_config.h"
 #include "cybsp_doc.h"
 
 #if defined(__cplusplus)

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/cat1cm0p.mtbx

@@ -1 +1 @@
-https://github.com/Infineon/cat1cm0p#release-v1.1.0#$$ASSET_REPO$$/cat1cm0p/release-v1.1.0
+https://github.com/Infineon/cat1cm0p#release-v1.8.0#$$ASSET_REPO$$/cat1cm0p/release-v1.8.0

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/core-lib.mtbx

@@ -1 +1 @@
-https://github.com/cypresssemiconductorco/core-lib#release-v1.4.0#$$ASSET_REPO$$/core-lib/release-v1.4.0
+https://github.com/cypresssemiconductorco/core-lib#release-v1.4.4#$$ASSET_REPO$$/core-lib/release-v1.4.4

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/core-make.mtbx

@@ -1 +1 @@
-https://github.com/cypresssemiconductorco/core-make#release-v3.2.1#$$ASSET_REPO$$/core-make/release-v3.2.1
+https://github.com/cypresssemiconductorco/core-make#release-v3.4.1#$$ASSET_REPO$$/core-make/release-v3.4.1

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/mtb-hal-cat1.mtbx

@@ -1 +1 @@
-https://github.com/cypresssemiconductorco/mtb-hal-cat1#release-v2.3.0#$$ASSET_REPO$$/mtb-hal-cat1/release-v2.3.0
+https://github.com/cypresssemiconductorco/mtb-hal-cat1#release-v2.7.1#$$ASSET_REPO$$/mtb-hal-cat1/release-v2.7.1

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/mtb-pdl-cat1.mtbx

@@ -1 +1 @@
-https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.4.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.4.0
+https://github.com/cypresssemiconductorco/mtb-pdl-cat1#release-v3.16.0#$$ASSET_REPO$$/mtb-pdl-cat1/release-v3.16.0

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/deps/recipe-make-cat1a.mtbx

@@ -1 +1 @@
-https://github.com/cypresssemiconductorco/recipe-make-cat1a#release-v2.1.1#$$ASSET_REPO$$/recipe-make-cat1a/release-v2.1.1
+https://github.com/cypresssemiconductorco/recipe-make-cat1a#release-v2.3.1#$$ASSET_REPO$$/recipe-make-cat1a/release-v2.3.1

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/props.json

@@ -1,15 +1,13 @@
 {
     "core": {
-        "version": "4.2.0.33410"
+        "version": "4.3.0.37540"
     },
     "opt": {
         "props": {
             "capabilities": [
                 "adc",
-                "anycloud",
                 "arduino",
                 "bsp_gen4",
-                "bt",
                 "capsense",
                 "capsense_button",
                 "capsense_linear_slider",
@@ -17,9 +15,7 @@
                 "cat1a",
                 "comp",
                 "csd",
-                "cy8ckit_062s2_43012",
-                "cyw43012",
-                "cyw43xxx",
+                "cy8ceval_062s2",
                 "dma",
                 "flash_2048k",
                 "fram",
@@ -35,8 +31,8 @@
                 "memory_qspi",
                 "multi_core",
                 "nor_flash",
+                "optiga_trust_m",
                 "pdm",
-                "pot",
                 "psoc6",
                 "qspi",
                 "rgb_led",
@@ -49,23 +45,22 @@
                 "switch",
                 "uart",
                 "usb_device",
-                "usb_host",
-                "wifi"
+                "usb_host"
             ],
             "dependencies": {
-                "cat1cm0p": "release-v1.1.0",
-                "core-lib": "release-v1.4.0",
-                "core-make": "release-v3.2.1",
-                "mtb-hal-cat1": "release-v2.3.0",
-                "mtb-pdl-cat1": "release-v3.4.0",
-                "recipe-make-cat1a": "release-v2.1.1"
+                "cat1cm0p": "release-v1.8.0",
+                "core-lib": "release-v1.4.4",
+                "core-make": "release-v3.4.1",
+                "mtb-hal-cat1": "release-v2.7.1",
+                "mtb-pdl-cat1": "release-v3.16.0",
+                "recipe-make-cat1a": "release-v2.3.1"
             },
             "docs_dir": "docs",
             "flow_version": "2.0",
             "min_tools": "3.0.0",
             "template": {
                 "id": "mtb-template-cat1",
-                "version": "release-v1.2.1"
+                "version": "release-v1.0.0"
             }
         }
     }

projects/cyw43012_wifi_demo/libs/TARGET_RTT-062S2/system_psoc6.h

@@ -1,6 +1,6 @@
 /***************************************************************************//**
 * \file system_psoc6.h
-* \version 2.95.1
+* \version 2.100
 *
 * \brief Device system header file.
 *
@@ -334,6 +334,11 @@
 *       <th>Reason for Change</th>
 *   </tr>
 *   <tr>
+*       <td rowspan="1">2.100</td>
+*       <td>Added support for TRAVEO&trade; II Body Entry devices.</td>
+*       <td>Code enhancement and support for new devices.</td>
+*   </tr> 
+*   <tr>
 *       <td rowspan="1">2.95.1</td>
 *       <td>Restructured documentation.</td>
 *       <td>Documentation update.</td>
@@ -341,7 +346,7 @@
 *   <tr>
 *       <td rowspan="1">2.95</td>
 *       <td>Update FPU enable function with CMSIS macros to disable/enable interrupts</td>
-*       <td>Move to stadnard inline CMSIS ARM macros</td>
+*       <td>Move to standard inline CMSIS ARM macros</td>
 *   </tr>
 *   <tr>
 *       <td rowspan="2">2.91</td>