first version.

project_0/.config

@@ -0,0 +1,935 @@
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# end of kservice optimization
+
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart5"
+# end of Kernel Device Object
+
+CONFIG_RT_VER_NUM=0x50000
+# end of RT-Thread Kernel
+
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M4=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# end of Interprocess Communication (IPC)
+# end of POSIX (Portable Operating System Interface) layer
+
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C/C++ and POSIX layer
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+# end of Network
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# end of Utilities
+
+# CONFIG_RT_USING_VBUS is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+# end of JSON: JavaScript Object Notation, a lightweight data-interchange format
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# end of XML: Extensible Markup Language
+
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+# end of LVGL: powerful and easy-to-use embedded GUI library
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# end of u8g2: a monochrome graphic library
+
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# end of PainterEngine: A cross-platform graphics application framework written in C language
+
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+# end of tools packages
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+# end of enhanced kernel services
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+# end of acceleration: Assembly language or algorithmic acceleration packages
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# end of Kendryte SDK
+
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# end of peripheral libraries and drivers
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+# end of AI packages
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+# end of project laboratory
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# end of entertainment: terminal games and other interesting software packages
+
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# end of miscellaneous packages
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+# end of Projects
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# end of Sensors
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# end of Display
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+# end of Timing
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+# end of Data Processing
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+# end of Communication
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# end of Device Control
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+# end of Signal IO
+
+#
+# Uncategorized
+#
+# end of Arduino libraries
+# end of RT-Thread online packages
+
+CONFIG_SOC_FAMILY_IFX=y
+CONFIG_SOC_SERIES_IFX_PSOC6=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_IFX_PSOC6_43012=y
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_USB_TO_USART=y
+# end of Onboard Peripheral Drivers
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+CONFIG_BSP_USING_UART5=y
+# CONFIG_BSP_USING_PWM is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_SDMMC is not set
+# CONFIG_BSP_USING_QSPI_FLASH is not set
+# CONFIG_BSP_USING_HW_I2C is not set
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_TIM is not set
+# end of On-chip Peripheral Drivers
+
+#
+# Board extended module Drivers
+#
+# CONFIG_BSP_USING_SLIDER is not set
+# CONFIG_BSP_USING_RW007 is not set
+# end of Board extended module Drivers
+# end of Hardware Drivers Config

project_0/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

project_0/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>psoc6</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>com.cypress.studio.app.cymodusnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

project_0/.settings/dist_ide_project.DAPLink.Debug.rttlaunch

@@ -0,0 +1,65 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.pyocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.adapterName" value="DAP-LINK"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.binFlashStartAddress" value=""/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doFirstReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbClientOtherOptions" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerBusSpeed" value="12000000"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerConnectionAddress" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerDeviceName" value="cy8c64xA_cm4"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerEnableSemihosting" value="false"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerExecutable" value="E:\software\RT-ThreadStudio\repo\Extract\Debugger_Support_Packages\openocd\bin\openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerFlashMode" value="0"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerOther" value=""/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.otherRunCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.programMode" value="HEX"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.pyocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU PyOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/dist_ide_project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

project_0/.settings/dist_ide_project.OpenOCD.Debug.rttlaunch

@@ -0,0 +1,58 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateConsole" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doGdbServerAllocateTelnetConsole" value="false"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doSecondReset" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbCLient" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doStartGdbServer" value="true"/>
+<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.enableSemihosting" value="true"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.firstResetType" value="init"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherCommands" value="set mem inaccessible-by-default off&#13;&#10;set remotetimeout 15"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbClientOtherOptions" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerExecutable" value="${debugger_install_path}/${openocd-infineon_debugger_relative_path}/bin/openocd.exe"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerGdbPortNumber" value="3333"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerOther" value="-s ../scripts -f interface/kitprog3.cfg -f target/psoc6_2m.cfg -c &quot;psoc6.cpu.cm4 configure -rtos auto -rtos-wipe-on-reset-halt 1&quot; -c &quot;gdb_port 3332&quot; -c &quot;psoc6 sflash_restrictions 1&quot; -c &quot;init; reset init&quot;"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTclPortNumber" value="6666"/>
+<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.gdbServerTelnetPortNumber" value="4444"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value="mon psoc6 reset_halt sysresetreq&#13;&#10;flushregs&#13;&#10;mon gdb_sync&#13;&#10;stepi"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="run"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU OpenOCD"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value="${workspace_loc:\dist_ide_project\Debug\rtthread.elf}"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${rtt_gnu_gcc}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="dist_ide_project"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/dist_ide_project"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="GBK"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;memoryBlockExpressionList context=&quot;Context string&quot;/&gt;&#13;&#10;"/>
+<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
+</launchConfiguration>

project_0/.settings/ilg.gnumcueclipse.managedbuild.cross.arm.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+toolchain.path.1287942917=${toolchain_install_path}/ARM/GNU_Tools_for_ARM_Embedded_Processors/10.2.1/bin

project_0/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094" name="Debug">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1836229373180626533" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT ARM Cross GCC Built-in Compiler Settings " parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

project_0/.settings/local_temp_storage.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+temp.toolchain.exec.path=D\:\\IDE\\RT-ThreadStudio\\repo\\Extract\\ToolChain_Support_Packages\\ARM\\GNU_Tools_for_ARM_Embedded_Processors\\10.2.1/bin

project_0/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

project_0/.settings/projcfg.ini

@@ -0,0 +1,19 @@
+#RT-Thread Studio Project Configuration
+#Tue Oct 18 20:53:52 CST 2022
+cfg_version=v3.0
+board_name=psoc6-cy8ckit-062S2-43012
+example_name=
+hardware_adapter=KitProg3
+board_base_nano_proj=false
+project_type=rt-thread
+chip_name=CY8C624ABZI-S2D44
+selected_rtt_version=latest
+bsp_version=
+os_branch=master
+project_base_rtt_bsp=true
+output_project_path=D\:IDERT-ThreadStudioworkspacepsoc6
+is_base_example_project=false
+is_use_scons_build=true
+project_name=psoc6
+os_version=latest
+bsp_path=

project_0/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "board/Kconfig"

project_0/LICENSE

@@ -0,0 +1,210 @@
+CYPRESS END USER LICENSE AGREEMENT
+
+PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
+DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
+DOCUMENTATION.  BY DOWNLOADING, INSTALLING, COPYING OR USING THE SOFTWARE,
+YOU ARE AGREEING TO BE BOUND BY THIS AGREEMENT.  IF YOU DO NOT AGREE TO ALL
+OF THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN AND DO NOT USE THE SOFTWARE.
+IF YOU HAVE PURCHASED THIS LICENSE TO THE SOFTWARE, YOUR RIGHT TO RETURN THE
+SOFTWARE EXPIRES 30 DAYS AFTER YOUR PURCHASE AND APPLIES ONLY TO THE ORIGINAL
+PURCHASER.
+
+1. Definitions.
+
+    "Software" means this software and any accompanying documentation,
+      including any upgrades, updates, bug fixes or modified versions provided
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+Semiconductor Corporation, ATTN: Chief Legal Officer, 198 Champion Court, San
+Jose, CA 95134 USA.

project_0/README.md

@@ -0,0 +1,119 @@
+# Cypress Psoc6-CY8CKIT-062S2-43012 说明
+
+## 简介
+
+本文档为 `RT-Thread` 为 `PSoC6 CY8CKIT-062S2-43012`开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 `RT-Thread` 驱动更多板载资源。
+
+## 开发板介绍
+
+`PSoC6 CY8CKIT-062S2-43012` 是英飞凌推出的一款32位双核CPU子系统（ ARM Cortex-M4 和 ARM Cortex-M0）的开发板，具有单周期乘法的150-MHz Arm Cortex-M4F CPU (浮点和存储器保护单元)，100-MHz Cortex M0+ CPU，带单周期乘法和MPU，可以充分发挥 PSoC6 双核芯片性能。
+
+开发板外观详细信息：[CY8CPROTO-062-4343W - Infineon Technologies](https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/)
+
+该开发板核心 **板载资源** 如下：
+
+- MCU：CY8C624ABZI-S2D44，Cortex-M4主频 150MHz，Cortex-M0主频 100MHz，2MB Flash 和 1MB SRAM
+	    MCU手册更多详细信息请参考文档 [PSoC 6 MCU: CY8C62x8, CY8C62xA Datasheet (infineon.com)](https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C62X8_CY8C62XA-DataSheet-v17_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee7d03a70b1)
+- 板载资源：microSD card , 64-Mb Quad-SPI NOR flash， CYW43012 Wi-Fi + Bluetooth Combo Chip
+- 开发环境：ModusToolbox 2.0/MDK V5
+		PSoC® Creator™ 下载链接 [ModusToolbox™ Software - Infineon Technologies](https://www.infineon.com/cms/en/design-support/tools/sdk/modustoolbox-software/)
+- 开发板：CY8CKIT-062-BLE PSoC 6 BLE Pioneer Kit
+		开发板更多详细信息请参考文档 https://www.cypress.com/file/390496/download
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** |   **备注**    |
+| :----------: | :----------: | :-----------: |
+|  USB 转串口  |     支持     |     UART5     |
+|     GPIO     |     支持     |       —       |
+|     UART     |     支持     |    UART0-5    |
+|     I2C      |     支持     | 软件+硬件 I2C |
+|     RTC      |     支持     |       —       |
+|     WDT      |     支持     |       —       |
+|     PWM      |     支持     |       —       |
+|     SPI      |     支持     |       —       |
+|  HardTimer   |     支持     |       —       |
+|     DAC      |     支持     |     IDAC      |
+|    Flash     |     支持     |  片内 Falsh   |
+|    Touch     |     支持     |   触摸滑条    |
+|     SDIO     |   暂不支持   |       —       |
+|  USB Device  |   暂不支持   |       —       |
+|   USB Host   |   暂不支持   |       —       |
+
+## 快速上手
+
+本 BSP 是以 `MDK V5` 和 `RT-Thread Studio` 为开发环境（编译器：ARMClang / GCC），接下来介绍如何将系统运行起来。
+
+### 使用 MDK V5 开发
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC。
+
+#### 编译下载
+
+1、配置工程：
+
+首先打开 MDK ，若没有安装 `Cypress-PSoC6` 的芯片支持包会提示在线安装，根据提示安装即可。若受网络问题，可以进入 [keil](https://www.keil.com/dd2/pack) 官网下载安装包，离线安装。
+
+![mdk_package](./figures/mdk_package.png)
+
+2、 编译此工程：在安装好芯片支持包后，在 `MDK`工程中进行编译。
+
+3、下载此工程：
+
+工程默认配置使用板载 `DAP-LINK` 使用 `SWD` 方式下载程序，使用数据线连接开发板，编译之后直接点击下载按钮即可。
+
+### 使用 RT-Thread Studio 开发
+
+#### 导入工程
+
+* 首先打开  `RT-Thread Studio` 开发工具，点加左上角文件—>导入—> RT-Thread Studio项目到工作空间中。
+
+![](./figures/studio1.png)
+
+* 接着选择 `PSoC6 CY8CKIT-062S2-43012` 开发板支持包的目录，进行导入。
+
+![](./figures/studio2.png)
+
+#### 编译下载
+
+* 点击 IDE 左上角的构建选项进行工程的编译。
+
+![](./figures/studio3-build.png)
+
+* 当编译无错误警告时，点击 `Debug` 或 `Download` 选项进行调试/下载。
+
+  注：若点击下载并下载成功后串口终端无显示信息，请手动按下复位按键进行重启运行。
+
+  ![](./figures/studio4-download.png)
+
+## 运行结果
+
+下载程序成功之后，系统会自动运行。打开终端工具串口助手，选择波特率为 115200。复位设备后，LED 将会以 500HZ 的频率闪烁，而且在终端上可以看到 `RT-Thread` 的输出信息：
+
+注：推荐使用串口调试助手如：`MobaXterm`
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.1 build Jul 25 2022 18:03:35
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+## 联系人
+
+维护人:
+
+- [Rbb666](https://github.com/Rbb666)

project_0/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

project_0/SConstruct

@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+# set RTT_ROOT
+if not os.getenv("RTT_ROOT"): 
+    RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+IFX_library = 'IFX_PSOC6_HAL'
+rtconfig.BSP_LIBRARY_TYPE = IFX_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, IFX_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

project_0/applications/SConscript

@@ -0,0 +1,16 @@
+import rtconfig
+from building import *
+import os
+
+cwd  = GetCurrentDir()
+path = [cwd]
+src  = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

project_0/applications/main.c

@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "drv_gpio.h"
+
+#define LED_PIN     GET_PIN(13, 7)
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    for (;;)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}

project_0/board/Kconfig

@@ -0,0 +1,323 @@
+menu "Hardware Drivers Config"
+
+config SOC_IFX_PSOC6_43012
+    bool
+    select SOC_SERIES_IFX_PSOC6
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USB_TO_USART
+        bool "Enable USB TO USART (uart5)"
+        select BSP_USING_UART
+        select BSP_USING_UART5
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+            config BSP_USING_UART5
+                bool "Enable UART5"
+                default y                
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+        menuconfig BSP_USING_PWM0
+            bool "Enable timer0 output pwm"
+            default n
+            if BSP_USING_PWM0
+                menuconfig BSP_USING_PWM0_CH3
+                    bool "Enable PWM0 channel3"
+                    default n
+                    if BSP_USING_PWM0_CH3
+                        config BSP_USING_PWM0_PORT13
+                        bool "Enable PWM0-PORT13 output pwm"
+                        default n
+                    endif
+                menuconfig BSP_USING_PWM0_CH7
+                    bool "Enable PWM0 channel7"
+                    default n
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT2
+                        bool "Enable PWM0-PORT2 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT5
+                        bool "Enable PWM0-PORT5 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT7
+                        bool "Enable PWM0-PORT7 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT9
+                        bool "Enable PWM0-PORT9 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT10
+                        bool "Enable PWM0-PORT10 output pwm"
+                        default n
+                    endif
+                    if BSP_USING_PWM0_CH7
+                        config BSP_USING_PWM0_PORT12
+                        bool "Enable PWM0-PORT12 output pwm"
+                        default n
+                    endif
+            endif
+        endif
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        select RT_USING_SPI
+        default n
+        if BSP_USING_SPI
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_USING_SPI3_SAMPLE
+                        bool "Enable SPI3 BUS Sample"
+                        default n                
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+        endif
+
+    config BSP_USING_SDMMC
+        bool "Enable SDMMC (sd card)"
+        default n
+        select RT_USING_SDIO
+        select RT_USING_DFS
+        select RT_USING_DFS_ELMFAT
+        if BSP_USING_SDMMC
+            config BSP_USING_SDIO1
+                bool "Enable SDIO1 (sd card)"
+                default n
+        endif
+
+    config BSP_USING_QSPI_FLASH
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SFUD
+        select RT_SFUD_USING_QSPI
+        default n
+
+    menuconfig BSP_USING_HW_I2C
+        bool "Enable Hardware I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_PIN
+        if BSP_USING_HW_I2C
+            config BSP_USING_HW_I2C3
+                bool "Enable I2C3 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C3
+                    comment "Notice: P6_0 --> 48; P6_1 --> 49"
+                    config BSP_I2C3_SCL_PIN
+                        int "i2c3 SCL pin number"
+                        range 1 113
+                        default 48
+                    config BSP_I2C3_SDA_PIN
+                        int "i2c3 SDA pin number"
+                        range 1 113
+                        default 49
+                endif
+            config BSP_USING_HW_I2C6
+                bool "Enable I2C6 Bus (User I2C)"
+                default n
+                if BSP_USING_HW_I2C6
+                    comment "Notice: P13_0 --> 48; P13_1 --> 49"
+                    config BSP_I2C6_SCL_PIN
+                        int "i2c6 SCL pin number"
+                        range 1 113
+                        default 104
+                    config BSP_I2C6_SDA_PIN
+                        int "i2c6 SDA pin number"
+                        range 1 113
+                        default 105
+                endif                
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable Software I2C Bus"
+        default n
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        select RT_USING_PIN
+        if BSP_USING_I2C
+            config BSP_USING_I2C1
+                bool "Enable I2C1 Bus (User I2C)"
+                default n
+                if BSP_USING_I2C1
+                    comment "Notice: P13_1 --> 105; P13_2 --> 106"
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 SCL pin number"
+                        range 1 113
+                        default 105
+                    config BSP_I2C1_SDA_PIN
+                        int "i2c1 SDA pin number"
+                        range 1 113
+                        default 106
+                endif
+        endif
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB_DEVICE
+        default n
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_LSE
+
+                config BSP_RTC_USING_LSE
+                    bool "RTC USING LSE"
+
+                config BSP_RTC_USING_LSI
+                    bool "RTC USING LSI"
+            endchoice
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    config BSP_USING_WDT
+        bool "Enable Watchdog Timer"
+        select RT_USING_WDT
+        default n
+    
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "Enable DAC1"
+                default n
+            config BSP_USING_DAC2
+                bool "Enable DAC2"
+                default n
+        endif
+
+    menuconfig BSP_USING_TIM
+        bool "Enable timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_TIM
+            config BSP_USING_TIM1
+                bool "Enable TIM1"
+                default n
+            config BSP_USING_TIM2
+                bool "Enable TIM2"
+                default n
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+    config BSP_USING_SLIDER
+        bool "Enable Slider Demo"
+        select BSP_USING_PWM
+        select BSP_USING_PWM0
+        select BSP_USING_PWM0_CH3
+        select BSP_USING_PWM0_PORT13
+        default n
+
+        menuconfig BSP_USING_RW007
+            bool "Enable RW007"
+            default n
+            select PKG_USING_RW007
+            select BSP_USING_SPI
+            select RW007_NOT_USE_EXAMPLE_DRIVERS
+            
+        if BSP_USING_RW007
+            comment "Notice: P5_7 --> 47; P6_2 -->50; P6_5 --> 53; P12_0 --> 96"
+            config IFX_RW007_SPI_BUS_NAME
+                string "RW007 BUS NAME"
+                default "spi3"
+
+            config IFX_RW007_WIFI_SSID
+                string "Wi-Fi SSID"
+                default "realthread_VIP"
+
+            config IFX_RW007_WIFI_PASSWORD
+                string "Wi-Fi Password"
+                default "your wifi password"
+
+            config IFX_RW007_CS_PIN
+                int "(INT)CS pin index"
+                range 1 113
+                default 96
+
+            config IFX_RW007_BOOT0_PIN
+                int "(INT)BOOT0 pin index (same as spi clk pin)"
+                range 1 113
+                default 50
+
+            config IFX_RW007_BOOT1_PIN
+                int "(INT)BOOT1 pin index (same as spi cs pin)"
+                range 1 113
+                default 96
+
+            config IFX_RW007_INT_BUSY_PIN
+                int "(INT)INT/BUSY pin index"
+                range 1 113
+                default 47
+
+            config IFX_RW007_RST_PIN
+                int "(INT)RESET pin index"
+                range 1 113
+                default 53
+        endif
+endmenu
+
+endmenu

project_0/board/SConscript

@@ -0,0 +1,44 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+objs = []
+cwd = GetCurrentDir()
+list = os.listdir(cwd)
+
+# add general drivers
+src = Split('''
+board.c
+''')
+
+if GetDepend(['BSP_USING_SPI3_SAMPLE']):
+    src += Glob('ports/spi_sample.c')
+
+if GetDepend(['BSP_USING_RW007']):
+    src += Glob('ports/drv_rw007.c')
+
+if GetDepend(['BSP_USING_SLIDER']):
+    src += Glob('ports/slider_sample.c')
+
+path = [cwd]
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S']
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S']
+    src += [startup_path_prefix +
+            '/IFX_PSOC6_HAL/mtb-pdl-cat1/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S']
+
+CPPDEFINES = ['CY8C624ABZI_S2D44', 'IFX_PSOC6_43012', 'CY_USING_HAL', 'COMPONENT_CAT1A', 'COMPONENT_CAT1', 'COMPONENT_BSP_DESIGN_MODUS']
+group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path, CPPDEFINES=CPPDEFINES)
+
+Return('group')

project_0/board/board.c

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include "board.h"
+
+void cy_bsp_all_init(void)
+{
+    cy_rslt_t result;
+
+    /* Initialize the device and board peripherals */
+    result = cybsp_init();
+
+    /* Board init failed. Stop program execution */
+    if (result != CY_RSLT_SUCCESS)
+    {
+        CY_ASSERT(0);
+    }
+}

project_0/board/board.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ * 2022-07-26     Rbb666       Add Flash Config
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#include "cy_result.h"
+#include "cybsp_types.h"
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef BSP_USING_USBD
+    #include "cy_usb_dev.h"
+    #include "cy_usb_dev_hid.h"
+    #include "cycfg_usbdev.h"
+#endif
+
+/*FLASH CONFIG*/
+#define IFX_FLASH_START_ADRESS          ((uint32_t)0x10000000)
+#define IFX_FLASH_PAGE_SIZE             (256 * 1024)
+#define IFX_FLASH_SIZE                  (2 * 1024 * 1024)
+#define IFX_FLASH_END_ADDRESS           ((uint32_t)(IFX_FLASH_START_ADRESS + IFX_FLASH_SIZE))
+
+/*EFLASH CONFIG*/
+#define IFX_EFLASH_START_ADRESS         ((uint32_t)0x14000000)
+#define IFX_EFLASH_PAGE_SIZE            (32 * 1024)
+#define IFX_EFLASH_SIZE                 (32 * 1024)
+#define IFX_EFLASH_END_ADDRESS          ((uint32_t)(IFX_EFLASH_START_ADRESS + IFX_EFLASH_SIZE))
+
+/*SRAM CONFIG*/
+#define IFX_SRAM_SIZE                   (1014)
+#define IFX_SRAM_END                    (0x08002000 + IFX_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+    #define HEAP_END        IFX_SRAM_END
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN    (__segment_end("HEAP"))
+#else
+    extern unsigned int __end__;
+    extern unsigned int __HeapLimit;
+    #define HEAP_BEGIN    (void*)&__end__
+    #define HEAP_END      (void*)&__HeapLimit
+#endif
+
+void cy_bsp_all_init(void);
+
+#endif
+

project_0/board/linker_scripts/link.icf

@@ -0,0 +1,247 @@
+/*******************************************************************************
+* \file cy8c6xxa_cm4_dual.icf
+* \version 2.91
+*
+* Linker file for the IAR compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point is fixed and starts at 0x10000000. The valid application
+* image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+
+/* The symbols below define the location and size of blocks of memory in the target.
+ * Use these symbols to specify the memory regions available for allocation.
+ */
+
+/* The following symbols control RAM and flash memory allocation for the CM4 core.
+ * You can change the memory allocation by editing RAM and Flash symbols.
+ * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+ * Using this memory region for other purposes will lead to unexpected behavior.
+ * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
+ * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
+ */
+/* RAM */
+define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
+define symbol __ICFEDIT_region_IRAM1_end__   = 0x080FF7FF;
+
+/* Flash */
+define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
+define symbol __ICFEDIT_region_IROM1_end__   = 0x101FFFFF;
+
+/* The following symbols define a 32K flash region used for EEPROM emulation.
+ * This region can also be used as the general purpose flash.
+ * You can assign sections to this memory region for only one of the cores.
+ * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+ * Therefore, repurposing this memory region will prevent such middleware from operation.
+ */
+define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
+define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
+
+/* The following symbols define device specific memory regions and must not be changed. */
+/* Supervisory FLASH - User Data */
+define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
+define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
+
+/* Supervisory FLASH - Normal Access Restrictions (NAR) */
+define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
+define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
+
+/* Supervisory FLASH - Public Key */
+define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
+define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
+
+/* Supervisory FLASH - Table of Content # 2 */
+define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
+define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
+
+/* Supervisory FLASH - Table of Content # 2 Copy */
+define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
+define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
+
+/* eFuse */
+define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
+define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
+
+/* XIP */
+define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
+
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+
+
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+/*-Sizes-*/
+if (!isdefinedsymbol(__STACK_SIZE)) {
+  define symbol __ICFEDIT_size_cstack__ = 0x1000;
+} else {
+  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
+}
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+
+/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
+if (!isdefinedsymbol(__HEAP_SIZE)) {
+    define symbol __ICFEDIT_size_heap__ = 0x0400;
+} else {
+  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
+}
+/**** End of ICF editor section. ###ICF###*/
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+ * More about CM0+ prebuilt images, see here:
+ * https://github.com/cypresssemiconductorco/psoc6cm0p
+ */
+/* The size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
+define memory mem with size = 4G;
+define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
+define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
+define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
+define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
+define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
+define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
+define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
+define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
+define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
+define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
+
+define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
+define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
+define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
+define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
+define block RO     {first section .intvec, readonly};
+
+define block cy_xip { section .cy_xip };
+
+/*-Initializations-*/
+initialize by copy { readwrite };
+do not initialize  { section .noinit, section .intvec_ram };
+
+/*-Placement-*/
+
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application */
+place in          IROM1_region  { block RO };
+
+/* Used for the digital signature of the secure application and the Bootloader SDK application. */
+".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
+
+/* Emulated EEPROM Flash area */
+".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
+
+/* Supervisory Flash - User Data */
+".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
+
+/* Supervisory Flash - NAR */
+".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
+
+/* Supervisory Flash - Public Key */
+".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
+
+/* Supervisory Flash - TOC2 */
+".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
+
+/* Supervisory Flash - RTOC2 */
+".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
+
+/* eFuse */
+".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
+
+/* Execute in Place (XIP). See the smif driver documentation for details. */
+"cy_xip" : place at start of EROM1_region  { block cy_xip };
+
+/* RAM */
+place at start of IRAM1_region  { readwrite section .intvec_ram};
+place in          IRAM1_region  { readwrite };
+place at end   of IRAM1_region  { block HSTACK };
+
+/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
+
+
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
+        section .cy_em_eeprom,
+        section .cy_sflash_user_data,
+        section .cy_sflash_nar,
+        section .cy_sflash_public_key,
+        section .cy_toc_part2,
+        section .cy_rtoc_part2,
+        section .cy_efuse,
+        section .cy_xip,
+        section .cymeta,
+         };
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+define exported symbol __cy_memory_0_start    = 0x10000000;
+define exported symbol __cy_memory_0_length   = 0x00200000;
+define exported symbol __cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+define exported symbol __cy_memory_1_start    = 0x14000000;
+define exported symbol __cy_memory_1_length   = 0x8000;
+define exported symbol __cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+define exported symbol __cy_memory_2_start    = 0x16000000;
+define exported symbol __cy_memory_2_length   = 0x8000;
+define exported symbol __cy_memory_2_row_size = 0x200;
+
+/* XIP */
+define exported symbol __cy_memory_3_start    = 0x18000000;
+define exported symbol __cy_memory_3_length   = 0x08000000;
+define exported symbol __cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+define exported symbol __cy_memory_4_start    = 0x90700000;
+define exported symbol __cy_memory_4_length   = 0x100000;
+define exported symbol __cy_memory_4_row_size = 1;
+
+/* EOF */

project_0/board/linker_scripts/link.ld

@@ -0,0 +1,487 @@
+/***************************************************************************//**
+* \file cy8c6xxa_cm4_dual.ld
+* \version 2.91
+*
+* Linker file for the GNU C compiler.
+*
+* The main purpose of the linker script is to describe how the sections in the
+* input files should be mapped into the output file, and to control the memory
+* layout of the output file.
+*
+* \note The entry point location is fixed and starts at 0x10000000. The valid
+* application image should be placed there.
+*
+* \note The linker files included with the PDL template projects must be generic
+* and handle all common use cases. Your project may not use every section
+* defined in the linker files. In that case you may see warnings during the
+* build process. In your project, you can simply comment out or remove the
+* relevant code in the linker file.
+*
+********************************************************************************
+* \copyright
+* Copyright 2016-2021 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lnosys)
+ENTRY(Reset_Handler)
+
+/* The size of the stack section at the end of CM4 SRAM */
+STACK_SIZE = 0x1000;
+
+/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+* More about CM0+ prebuilt images, see here:
+* https://github.com/cypresssemiconductorco/psoc6cm0p
+*/
+/* The size of the Cortex-M0+ application image at the start of FLASH */
+FLASH_CM0P_SIZE  = 0x2000;
+
+/* Force symbol to be entered in the output file as an undefined symbol. Doing
+* this may, for example, trigger linking of additional modules from standard
+* libraries. You may list several symbols for each EXTERN, and you may use
+* EXTERN multiple times. This command has the same effect as the -u command-line
+* option.
+*/
+EXTERN(Reset_Handler)
+
+/* The MEMORY section below describes the location and size of blocks of memory in the target.
+* Use this section to specify the memory regions available for allocation.
+*/
+MEMORY
+{
+    /* The ram and flash regions control RAM and flash memory allocation for the CM4 core.
+     * You can change the memory allocation by editing the 'ram' and 'flash' regions.
+     * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+     * Using this memory region for other purposes will lead to unexpected behavior.
+     * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld',
+     * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'.
+     */
+    ram               (rwx)   : ORIGIN = 0x08002000, LENGTH = 0xFD800
+    flash             (rx)    : ORIGIN = 0x10000000, LENGTH = 0x200000
+
+    /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash.
+     * You can assign sections to this memory region for only one of the cores.
+     * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+     * Therefore, repurposing this memory region will prevent such middleware from operation.
+     */
+    em_eeprom         (rx)    : ORIGIN = 0x14000000, LENGTH = 0x8000       /*  32 KB */
+
+    /* The following regions define device specific memory regions and must not be changed. */
+    sflash_user_data  (rx)    : ORIGIN = 0x16000800, LENGTH = 0x800        /* Supervisory flash: User data */
+    sflash_nar        (rx)    : ORIGIN = 0x16001A00, LENGTH = 0x200        /* Supervisory flash: Normal Access Restrictions (NAR) */
+    sflash_public_key (rx)    : ORIGIN = 0x16005A00, LENGTH = 0xC00        /* Supervisory flash: Public Key */
+    sflash_toc_2      (rx)    : ORIGIN = 0x16007C00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 */
+    sflash_rtoc_2     (rx)    : ORIGIN = 0x16007E00, LENGTH = 0x200        /* Supervisory flash: Table of Content # 2 Copy */
+    xip               (rx)    : ORIGIN = 0x18000000, LENGTH = 0x8000000    /* 128 MB */
+    efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+
+
+SECTIONS
+{
+     /* Cortex-M0+ application flash image area */
+    .cy_m0p_image ORIGIN(flash) :
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > flash
+
+    /* Check if .cy_m0p_image size exceeds FLASH_CM0P_SIZE */
+    ASSERT(__cy_m0p_code_end <= ORIGIN(flash) + FLASH_CM0P_SIZE, "CM0+ flash image overflows with CM4, increase FLASH_CM0P_SIZE")
+
+    /* Cortex-M4 application flash area */
+    .text ORIGIN(flash) + FLASH_CM0P_SIZE :
+    {
+        . = ALIGN(4);
+        __Vectors = . ;
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+        __Vectors_End = .;
+        __Vectors_Size = __Vectors_End - __Vectors;
+        __end__ = .;
+
+        . = ALIGN(4);
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        . = ALIGN(4);
+        /* Read-only code (constants). */
+        *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
+        KEEP(*(.eh_frame*))
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+    } > flash
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > flash
+
+    __exidx_start = .;
+
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > flash
+    __exidx_end = .;
+
+
+    /* To copy multiple ROM to RAM sections,
+     * uncomment .copy.table section and,
+     * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */
+    .copy.table :
+    {
+        . = ALIGN(4);
+        __copy_table_start__ = .;
+
+        /* Copy interrupt vectors from flash to RAM */
+        LONG (__Vectors)                                    /* From */
+        LONG (__ram_vectors_start__)                        /* To   */
+        LONG (__Vectors_End - __Vectors)                    /* Size */
+
+        /* Copy data section to RAM */
+        LONG (__etext)                                      /* From */
+        LONG (__data_start__)                               /* To   */
+        LONG (__data_end__ - __data_start__)                /* Size */
+
+        __copy_table_end__ = .;
+    } > flash
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    } > flash
+
+    . = ALIGN(4);
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    } > flash
+
+    /* To clear multiple BSS sections,
+     * uncomment .zero.table section and,
+     * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */
+    .zero.table :
+    {
+        . = ALIGN(4);
+        __zero_table_start__ = .;
+        LONG (__bss_start__)
+        LONG (__bss_end__ - __bss_start__)
+        __zero_table_end__ = .;
+    } > flash
+
+    __etext =  . ;
+
+    .ramVectors (NOLOAD) : ALIGN(8)
+    {
+        __ram_vectors_start__ = .;
+        KEEP(*(.ram_vectors))
+        __ram_vectors_end__   = .;
+    } > ram
+
+
+    .data __ram_vectors_end__ :
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+
+        KEEP(*(.cy_ramfunc*))
+        . = ALIGN(4);
+
+        __data_end__ = .;
+
+    } > ram AT>flash
+
+
+    /* Place variables in the section that should not be initialized during the
+    *  device startup.
+    */
+    .noinit (NOLOAD) : ALIGN(8)
+    {
+      KEEP(*(.noinit))
+    } > ram
+
+
+    /* The uninitialized global or static variables are placed in this section.
+    *
+    * The NOLOAD attribute tells linker that .bss section does not consume
+    * any space in the image. The NOLOAD attribute changes the .bss type to
+    * NOBITS, and that  makes linker to A) not allocate section in memory, and
+    * A) put information to clear the section with all zeros during application
+    * loading.
+    *
+    * Without the NOLOAD attribute, the .bss section might get PROGBITS type.
+    * This  makes linker to A) allocate zeroed section in memory, and B) copy
+    * this section to RAM during application loading.
+    */
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram
+
+
+    .heap (NOLOAD):
+    {
+        __HeapBase = .;
+        __end__ = .;
+        end = __end__;
+        KEEP(*(.heap*))
+        . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
+        __HeapLimit = .;
+    } > ram
+
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        KEEP(*(.stack*))
+    } > ram
+
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(ram) + LENGTH(ram);
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
+
+    /* Used for the digital signature of the secure application and the Bootloader SDK application.
+    * The size of the section depends on the required data size. */
+    .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 :
+    {
+        KEEP(*(.cy_app_signature))
+    } > flash
+
+
+    /* Emulated EEPROM Flash area */
+    .cy_em_eeprom :
+    {
+        KEEP(*(.cy_em_eeprom))
+    } > em_eeprom
+
+
+    /* Supervisory Flash: User data */
+    .cy_sflash_user_data :
+    {
+        KEEP(*(.cy_sflash_user_data))
+    } > sflash_user_data
+
+    /* Supervisory Flash: Normal Access Restrictions (NAR) */
+    .cy_sflash_nar :
+    {
+        KEEP(*(.cy_sflash_nar))
+    } > sflash_nar
+
+
+    /* Supervisory Flash: Public Key */
+    .cy_sflash_public_key :
+    {
+        KEEP(*(.cy_sflash_public_key))
+    } > sflash_public_key
+
+
+    /* Supervisory Flash: Table of Content # 2 */
+    .cy_toc_part2 :
+    {
+        KEEP(*(.cy_toc_part2))
+    } > sflash_toc_2
+
+
+    /* Supervisory Flash: Table of Content # 2 Copy */
+    .cy_rtoc_part2 :
+    {
+        KEEP(*(.cy_rtoc_part2))
+    } > sflash_rtoc_2
+
+
+    /* Places the code in the Execute in Place (XIP) section. See the smif driver
+    *  documentation for details.
+    */
+    cy_xip :
+    {
+        __cy_xip_start = .;
+        KEEP(*(.cy_xip))
+        __cy_xip_end = .;
+    } > xip
+
+
+    /* eFuse */
+    .cy_efuse :
+    {
+        KEEP(*(.cy_efuse))
+    } > efuse
+
+
+    /* These sections are used for additional metadata (silicon revision,
+    *  Silicon/JTAG ID, etc.) storage.
+    */
+    .cymeta         0x90500000 : { KEEP(*(.cymeta)) } :NONE
+}
+
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+__cy_memory_0_start    = 0x10000000;
+__cy_memory_0_length   = 0x00200000;
+__cy_memory_0_row_size = 0x200;
+
+/* Emulated EEPROM Flash area */
+__cy_memory_1_start    = 0x14000000;
+__cy_memory_1_length   = 0x8000;
+__cy_memory_1_row_size = 0x200;
+
+/* Supervisory Flash */
+__cy_memory_2_start    = 0x16000000;
+__cy_memory_2_length   = 0x8000;
+__cy_memory_2_row_size = 0x200;
+
+/* XIP */
+__cy_memory_3_start    = 0x18000000;
+__cy_memory_3_length   = 0x08000000;
+__cy_memory_3_row_size = 0x200;
+
+/* eFuse */
+__cy_memory_4_start    = 0x90700000;
+__cy_memory_4_length   = 0x100000;
+__cy_memory_4_row_size = 1;
+
+/* EOF */

project_0/board/linker_scripts/link.sct

@@ -0,0 +1,277 @@
+#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
+; The first line specifies a preprocessor command that the linker invokes
+; to pass a scatter file through a C preprocessor.
+
+;*******************************************************************************
+;* \file cy8c6xxa_cm4_dual.sct
+;* \version 2.91
+;*
+;* Linker file for the ARMCC.
+;*
+;* The main purpose of the linker script is to describe how the sections in the
+;* input files should be mapped into the output file, and to control the memory
+;* layout of the output file.
+;*
+;* \note The entry point location is fixed and starts at 0x10000000. The valid
+;* application image should be placed there.
+;*
+;* \note The linker files included with the PDL template projects must be
+;* generic and handle all common use cases. Your project may not use every
+;* section defined in the linker files. In that case you may see the warnings
+;* during the build process: L6314W (no section matches pattern) and/or L6329W
+;* (pattern only matches removed unused sections). In your project, you can
+;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
+;* the linker, simply comment out or remove the relevant code in the linker
+;* file.
+;*
+;*******************************************************************************
+;* \copyright
+;* Copyright 2016-2021 Cypress Semiconductor Corporation
+;* SPDX-License-Identifier: Apache-2.0
+;*
+;* Licensed under the Apache License, Version 2.0 (the "License");
+;* you may not use this file except in compliance with the License.
+;* You may obtain a copy of the License at
+;*
+;*     http://www.apache.org/licenses/LICENSE-2.0
+;*
+;* Unless required by applicable law or agreed to in writing, software
+;* distributed under the License is distributed on an "AS IS" BASIS,
+;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;* See the License for the specific language governing permissions and
+;* limitations under the License.
+;******************************************************************************/
+
+; The defines below describe the location and size of blocks of memory in the target.
+; Use these defines to specify the memory regions available for allocation.
+
+; The following defines control RAM and flash memory allocation for the CM4 core.
+; You can change the memory allocation by editing RAM and Flash defines.
+; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
+; Using this memory region for other purposes will lead to unexpected behavior.
+; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
+; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
+; RAM
+#define RAM_START               0x08002000
+#define RAM_SIZE                0x000FD800
+; Flash
+#define FLASH_START             0x10000000
+#define FLASH_SIZE              0x00200000
+
+; The size of the stack section at the end of CM4 SRAM
+#define STACK_SIZE              0x00001000
+
+; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
+; More about CM0+ prebuilt images, see here:
+; https://github.com/cypresssemiconductorco/psoc6cm0p
+; The size of the Cortex-M0+ application flash image
+#define FLASH_CM0P_SIZE         0x2000
+
+; The following defines describe a 32K flash region used for EEPROM emulation.
+; This region can also be used as the general purpose flash.
+; You can assign sections to this memory region for only one of the cores.
+; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
+; Therefore, repurposing this memory region will prevent such middleware from operation.
+#define EM_EEPROM_START         0x14000000
+#define EM_EEPROM_SIZE          0x8000
+
+; The following defines describe device specific memory regions and must not be changed.
+; Supervisory flash: User data
+#define SFLASH_USER_DATA_START  0x16000800
+#define SFLASH_USER_DATA_SIZE   0x00000800
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+#define SFLASH_NAR_START        0x16001A00
+#define SFLASH_NAR_SIZE         0x00000200
+
+; Supervisory flash: Public Key
+#define SFLASH_PUBLIC_KEY_START 0x16005A00
+#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
+
+; Supervisory flash: Table of Content # 2
+#define SFLASH_TOC_2_START      0x16007C00
+#define SFLASH_TOC_2_SIZE       0x00000200
+
+; Supervisory flash: Table of Content # 2 Copy
+#define SFLASH_RTOC_2_START     0x16007E00
+#define SFLASH_RTOC_2_SIZE      0x00000200
+
+; External memory
+#define XIP_START               0x18000000
+#define XIP_SIZE                0x08000000
+
+; eFuse
+#define EFUSE_START             0x90700000
+#define EFUSE_SIZE              0x100000
+
+
+; Cortex-M0+ application flash image area
+LR_IROM FLASH_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application flash area
+LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
+{
+    ER_FLASH_VECTORS +0
+    {
+        * (RESET, +FIRST)
+    }
+
+    ER_FLASH_CODE +0 FIXED
+    {
+        * (InRoot$$Sections)
+        * (+RO)
+    }
+
+    ER_RAM_VECTORS RAM_START UNINIT
+    {
+        * (RESET_RAM, +FIRST)
+    }
+
+    RW_RAM_DATA +0
+    {
+        * (.cy_ramfunc)
+        * (+RW, +ZI)
+    }
+
+    ; Place variables in the section that should not be initialized during the
+    ; device startup.
+    RW_IRAM1 +0 UNINIT
+    {
+        * (.noinit)
+    }
+
+    ; Application heap area (HEAP)
+    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
+    { 
+    }
+
+    ; Stack region growing down
+    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
+    {
+    }
+
+    ; Used for the digital signature of the secure application and the
+    ; Bootloader SDK application. The size of the section depends on the required
+    ; data size.
+    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
+    {
+        * (.cy_app_signature)
+    }
+}
+
+
+; Emulated EEPROM Flash area
+LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
+{
+    .cy_em_eeprom +0
+    {
+        * (.cy_em_eeprom)
+    }
+}
+
+; Supervisory flash: User data
+LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
+{
+    .cy_sflash_user_data +0
+    {
+        * (.cy_sflash_user_data)
+    }
+}
+
+; Supervisory flash: Normal Access Restrictions (NAR)
+LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
+{
+    .cy_sflash_nar +0
+    {
+        * (.cy_sflash_nar)
+    }
+}
+
+; Supervisory flash: Public Key
+LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
+{
+    .cy_sflash_public_key +0
+    {
+        * (.cy_sflash_public_key)
+    }
+}
+
+; Supervisory flash: Table of Content # 2
+LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
+{
+    .cy_toc_part2 +0
+    {
+        * (.cy_toc_part2)
+    }
+}
+
+; Supervisory flash: Table of Content # 2 Copy
+LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
+{
+    .cy_rtoc_part2 +0
+    {
+        * (.cy_rtoc_part2)
+    }
+}
+
+
+; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
+LR_EROM XIP_START XIP_SIZE
+{
+    cy_xip +0
+    {
+        * (.cy_xip)
+    }
+}
+
+
+; eFuse
+LR_EFUSE EFUSE_START EFUSE_SIZE
+{
+    .cy_efuse +0
+    {
+        * (.cy_efuse)
+    }
+}
+
+
+; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
+CYMETA 0x90500000
+{
+    .cymeta +0 { * (.cymeta) }
+}
+
+/* The following symbols used by the cymcuelftool. */
+/* Flash */
+#define __cy_memory_0_start 0x10000000
+#define __cy_memory_0_length  0x00200000
+#define __cy_memory_0_row_size 0x200
+
+/* Emulated EEPROM Flash area */
+#define __cy_memory_1_start    0x14000000
+#define __cy_memory_1_length   0x8000
+#define __cy_memory_1_row_size 0x200
+
+/* Supervisory Flash */
+#define __cy_memory_2_start    0x16000000
+#define __cy_memory_2_length   0x8000
+#define __cy_memory_2_row_size 0x200
+
+/* XIP */
+#define __cy_memory_3_start    0x18000000
+#define __cy_memory_3_length   0x08000000
+#define __cy_memory_3_row_size 0x200
+
+/* eFuse */
+#define __cy_memory_4_start    0x90700000
+#define __cy_memory_4_length   0x100000
+#define __cy_memory_4_row_size 1
+
+
+/* [] END OF FILE */

project_0/board/ports/drv_rw007.c

@@ -0,0 +1,67 @@
+#include <rtthread.h>
+#include <rtdbg.h>
+#ifdef BSP_USING_RW007
+#include <rtdevice.h>
+#include <drv_spi.h>
+#include <board.h>
+#include <spi_wifi_rw007.h>
+
+extern void spi_wifi_isr(int vector);
+
+static void rw007_gpio_init(void)
+{
+    /* Configure IO */
+    rt_pin_mode(IFX_RW007_RST_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLDOWN);
+
+    /* Reset rw007 and config mode */
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_LOW);
+    rt_thread_delay(rt_tick_from_millisecond(100));
+    rt_pin_write(IFX_RW007_RST_PIN, PIN_HIGH);
+
+    /* Wait rw007 ready(exit busy stat) */
+    while (!rt_pin_read(IFX_RW007_INT_BUSY_PIN))
+    {
+        rt_thread_delay(5);
+    }
+
+    rt_thread_delay(rt_tick_from_millisecond(200));
+    rt_pin_mode(IFX_RW007_INT_BUSY_PIN, PIN_MODE_INPUT_PULLUP);
+}
+
+static struct rt_spi_device rw007_dev;
+
+int wifi_spi_device_init(void)
+{
+    char sn_version[32];
+    uint32_t cs_pin = IFX_RW007_CS_PIN;
+
+    rw007_gpio_init();
+    rt_hw_spi_device_attach(IFX_RW007_SPI_BUS_NAME, "wspi", cs_pin);
+    rt_hw_wifi_init("wspi");
+
+    rt_wlan_set_mode(RT_WLAN_DEVICE_STA_NAME, RT_WLAN_STATION);
+    rt_wlan_set_mode(RT_WLAN_DEVICE_AP_NAME, RT_WLAN_AP);
+
+    rw007_sn_get(sn_version);
+    rt_kprintf("\nrw007  sn: [%s]\n", sn_version);
+    rw007_version_get(sn_version);
+    rt_kprintf("rw007 ver: [%s]\n\n", sn_version);
+
+    return 0;
+}
+INIT_APP_EXPORT(wifi_spi_device_init);
+
+static void int_wifi_irq(void *p)
+{
+    ((void)p);
+    spi_wifi_isr(0);
+}
+
+void spi_wifi_hw_init(void)
+{
+    rt_pin_attach_irq(IFX_RW007_INT_BUSY_PIN, PIN_IRQ_MODE_FALLING, int_wifi_irq, 0);
+    rt_pin_irq_enable(IFX_RW007_INT_BUSY_PIN, RT_TRUE);
+}
+
+#endif /* BSP_USING_RW007 */

project_0/board/ports/fal_cfg.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-27     Rbb666       first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+extern const struct fal_flash_dev ifx_onchip_flash_32k;
+extern const struct fal_flash_dev ifx_onchip_flash_256k;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE         \
+    {                               \
+        &ifx_onchip_flash_32k,      \
+        &ifx_onchip_flash_256k,     \
+    }
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+
+/* partition table */
+#define FAL_PART_TABLE                                                                  \
+    {                                                                                   \
+        {FAL_PART_MAGIC_WROD, "param", "onchip_flash_32k", 0, IFX_EFLASH_SIZE, 0},      \
+        {FAL_PART_MAGIC_WROD, "app", "onchip_flash_256k", 0, IFX_FLASH_SIZE, 0},        \
+    }
+
+#endif /* FAL_PART_HAS_TABLE_CFG */
+#endif /* _FAL_CFG_H_ */

project_0/board/ports/slider_sample.c

@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-28     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_SLIDER
+#include "cycfg_capsense.h"
+
+#define CAPSENSE_INTR_PRIORITY      (7u)
+#define EZI2C_INTR_PRIORITY         (6u)
+
+/* Allowed duty cycle for maximum brightness */
+#define LED_MAX_BRIGHTNESS      (100u)
+
+/* Allowed duty cycle for minimum brightness*/
+#define LED_MIN_BRIGHTNESS      (0u)
+
+#define GET_DUTY_CYCLE(x)       (1 * 1000 * 1000 - x * 10 * 1000)
+
+typedef enum
+{
+    LED_OFF,
+    LED_ON
+} led_state_t;
+
+typedef struct
+{
+    led_state_t state;
+    uint32_t brightness;
+} led_data_t;
+
+static rt_sem_t trans_done_semphr = RT_NULL;
+
+#ifndef RT_USING_PWM
+    #error You need enable PWM to use this sample
+#else
+    #define PWM_DEV_NAME "pwm0"
+    #define PWM_DEV_CHANNEL 3
+    static struct rt_device_pwm *pwm_dev;
+#endif
+
+static void capsense_isr(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    Cy_CapSense_InterruptHandler(CYBSP_CSD_HW, &cy_capsense_context);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void capsense_callback(cy_stc_active_scan_sns_t *ptrActiveScan)
+{
+    rt_sem_release(trans_done_semphr);
+}
+
+static uint32_t initialize_capsense(void)
+{
+    uint32_t status = CYRET_SUCCESS;
+
+    /* CapSense interrupt configuration parameters */
+    static const cy_stc_sysint_t capSense_intr_config =
+    {
+        .intrSrc = csd_interrupt_IRQn,
+        .intrPriority = CAPSENSE_INTR_PRIORITY,
+    };
+
+    /* Capture the CSD HW block and initialize it to the default state. */
+    status = Cy_CapSense_Init(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Initialize CapSense interrupt */
+    cyhal_system_set_isr(csd_interrupt_IRQn, csd_interrupt_IRQn, CAPSENSE_INTR_PRIORITY, &capsense_isr);
+    NVIC_ClearPendingIRQ(capSense_intr_config.intrSrc);
+    NVIC_EnableIRQ(capSense_intr_config.intrSrc);
+
+    /* Initialize the CapSense firmware modules. */
+    status = Cy_CapSense_Enable(&cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    /* Assign a callback function to indicate end of CapSense scan. */
+    status = Cy_CapSense_RegisterCallback(CY_CAPSENSE_END_OF_SCAN_E,
+                                          capsense_callback, &cy_capsense_context);
+    if (CYRET_SUCCESS != status)
+    {
+        return status;
+    }
+
+    return status;
+}
+
+void Slider_Init(void)
+{
+    cy_rslt_t result;
+
+    result = initialize_capsense();
+
+    if (CYRET_SUCCESS != result)
+    {
+        /* Halt the CPU if CapSense initialization failed */
+        RT_ASSERT(0);
+    }
+
+    /* Initiate first scan */
+    Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+    trans_done_semphr = rt_sem_create("slider_sem", 1, RT_IPC_FLAG_PRIO);
+    if (trans_done_semphr == RT_NULL)
+    {
+        rt_kprintf("create transform done semphr failed.\n");
+        RT_ASSERT(0);
+        return;
+    }
+
+#ifdef BSP_USING_PWM0_PORT13
+    /* Initiate PWM*/
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("PWM init failed! can't find %s device!\n", PWM_DEV_NAME);
+        RT_ASSERT(0);
+    }
+
+    /*default   period:1ms    pulse:0*/
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, 1 * 1000 * 1000);
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+#endif
+}
+
+void update_led_state(led_data_t *ledData)
+{
+    if (ledData->brightness >= 0)
+    {
+        uint32_t brightness = (ledData->brightness < LED_MIN_BRIGHTNESS) ? LED_MIN_BRIGHTNESS : ledData->brightness;
+
+        /* Drive the LED with brightness */
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, 1 * 1000 * 1000, GET_DUTY_CYCLE(brightness));
+    }
+}
+
+static void process_touch(void)
+{
+    cy_stc_capsense_touch_t *slider_touch_info;
+    uint16_t slider_pos;
+    uint8_t slider_touch_status;
+    bool led_update_req = false;
+
+    static uint16_t slider_pos_prev;
+    static led_data_t led_data = {LED_ON, LED_MAX_BRIGHTNESS};
+
+    /* Get slider status */
+    slider_touch_info = Cy_CapSense_GetTouchInfo(
+                            CY_CAPSENSE_LINEARSLIDER0_WDGT_ID, &cy_capsense_context);
+    slider_touch_status = slider_touch_info->numPosition;
+    slider_pos = slider_touch_info->ptrPosition->x;
+
+    /* Detect the new touch on slider */
+    if ((RT_NULL != slider_touch_status) &&
+            (slider_pos != slider_pos_prev))
+    {
+        led_data.brightness = (slider_pos * 100)
+                              / cy_capsense_context.ptrWdConfig[CY_CAPSENSE_LINEARSLIDER0_WDGT_ID].xResolution;
+
+        led_update_req = true;
+    }
+
+#ifndef RT_USING_PWM
+#error You need enable PWM to use this sample
+#else
+    /* Update the LED state if requested */
+    if (led_update_req)
+    {
+        update_led_state(&led_data);
+    }
+#endif
+    slider_pos_prev = slider_pos;
+}
+
+static void Slider_thread_entry(void *parameter)
+{
+    Slider_Init();
+
+    for (;;)
+    {
+        rt_sem_take(trans_done_semphr, RT_WAITING_FOREVER);
+
+        /* Process all widgets */
+        Cy_CapSense_ProcessAllWidgets(&cy_capsense_context);
+
+        /* Process touch input */
+        process_touch();
+
+        /* Establishes synchronized operation between the CapSense
+         * middleware and the CapSense Tuner tool.
+         */
+        Cy_CapSense_RunTuner(&cy_capsense_context);
+
+        /* Initiate next scan */
+        Cy_CapSense_ScanAllWidgets(&cy_capsense_context);
+
+        rt_thread_mdelay(50);
+    }
+}
+
+int Slider_ctrl_sample(void)
+{
+    rt_err_t ret = RT_EOK;
+
+    rt_thread_t thread = rt_thread_create("slider_th",
+                                          Slider_thread_entry,
+                                          RT_NULL,
+                                          1024,
+                                          25,
+                                          10);
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+
+    return ret;
+}
+MSH_CMD_EXPORT(Slider_ctrl_sample, Slider sample to ctrl led);
+#endif

project_0/board/ports/spi_sample.c

@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-19     Rbbb666      first version
+ */
+
+#include "board.h"
+
+#if defined(BSP_USING_SPI3_SAMPLE)
+#include <drv_spi.h>
+
+#define SPI_NAME     "spi30"
+static struct rt_spi_device *spi_dev = RT_NULL;
+
+/* attach spi5 device */
+static int rt_spi_device_init(void)
+{
+    struct rt_spi_configuration cfg;
+
+    rt_hw_spi_device_attach("spi3", "spi30", NULL);
+
+    cfg.data_width = 8;
+    cfg.mode   = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB | RT_SPI_NO_CS;
+    cfg.max_hz = 1 *1000 *1000;
+
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_NAME);
+
+    if (RT_NULL == spi_dev)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_NAME);
+        return RT_ERROR;
+    }
+
+    rt_spi_configure(spi_dev, &cfg);
+
+    return RT_EOK;
+}
+INIT_APP_EXPORT(rt_spi_device_init);
+
+/* spi5 loopback mode test case */
+static int spi_sample(int argc, char **argv)
+{
+    rt_uint8_t t_buf[8], r_buf[8];
+    int i = 0;
+    static struct rt_spi_message msg1;
+
+    if (argc != 9)
+    {
+        rt_kprintf("Please Usage:\n");
+        rt_kprintf("spi_sample 1 2 3 4 5 6 7 8\n");
+        return -RT_ERROR;
+    }
+
+    for (i = 0; i < 8; i++)
+    {
+        t_buf[i] = atoi(argv[i+1]);
+    }
+
+    msg1.send_buf   = &t_buf;
+    msg1.recv_buf   = &r_buf;
+    msg1.length     = sizeof(t_buf);
+    msg1.cs_take    = 1;
+    msg1.cs_release = 0;
+    msg1.next       = RT_NULL;
+
+    rt_spi_transfer_message(spi_dev, &msg1);
+
+    rt_kprintf("spi rbuf : ");
+    for (i = 0; i < sizeof(t_buf); i++)
+    {
+        rt_kprintf("%x ", r_buf[i]);
+    }
+
+    rt_kprintf("\nspi loopback mode test over!\n");
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(spi_sample, spi loopback test);
+
+#endif /* BSP_USING_SPI3 */

project_0/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,64 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+drv_common.c
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        src += ['drv_uart.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['RT_USING_I2C']):
+    if GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C6'):
+        src += ['drv_i2c.c']
+
+if GetDepend(['BSP_USING_SDIO1']):
+    src += Glob('drv_sdio.c')
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['BSP_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['BSP_USING_USBD']):
+    src += ['drv_usbd.c']
+
+if GetDepend('BSP_USING_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['drv_flash.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['drv_wdt.c']
+	
+if GetDepend(['RT_USING_DAC']):
+    src += ['drv_dac.c']	
+    
+if GetDepend(['BSP_USING_TIM']):
+    src += ['drv_hwtimer.c']    
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

project_0/libraries/HAL_Drivers/config/Pre_Include_Global.h

@@ -0,0 +1,37 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'mtb-example-psoc6-rtthread'
+ * Target:  'Target 1'
+ */
+
+#ifndef PRE_INCLUDE_GLOBAL_H
+#define PRE_INCLUDE_GLOBAL_H
+
+/* Cypress::TARGET_CY8CKIT-062S2-43012:ModusToolbox */
+#define HAVE_SIGVAL
+#define HAVE_SIGEVENT
+#define HAVE_SIGINFO
+#define RT_USING_NEWLIB
+#define CY_USING_HAL
+#define CY_APPNAME_mtb_example_psoc6_rtthread
+#define CY_TARGET_DEVICE CY8C624ABZI_S2D44
+#define TARGET_CY8CKIT_062S2_43012
+#define CY_TARGET_BOARD CY8CKIT_062S2_43012
+#define COMPONENT_43012
+#define COMPONENT_BSP_DESIGN_MODUS
+#define COMPONENT_CAT1
+#define COMPONENT_CAT1A
+#define COMPONENT_CM0P_SLEEP
+#define COMPONENT_CM4
+#define COMPONENT_CY8CKIT_062S2_43012
+#define COMPONENT_HCI_UART
+#define COMPONENT_MURATA_1LV
+#define COMPONENT_PSOC6HAL
+#define COMPONENT_SOFTFP
+#define DEBUG
+#define CY_SUPPORTS_DEVICE_VALIDATION
+
+#endif /* PRE_INCLUDE_GLOBAL_H */

project_0/libraries/HAL_Drivers/config/RTE_Components.h

@@ -0,0 +1,13 @@
+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'mtb-example-psoc6-rtthread'
+ * Target:  'Target 1'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#endif /* RTE_COMPONENTS_H */

project_0/libraries/HAL_Drivers/drv_adc.c

@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-04     Rbb666       first version
+ */
+#include "drv_common.h"
+#include "drv_adc.h"
+
+#include "cyhal.h"
+#include "cybsp.h"
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+
+//#define DRV_DEBUG
+#define LOG_TAG             "drv.adc"
+#include <drv_log.h>
+
+#define VPLUS_CHANNEL_0     (P10_0)
+
+struct ifx_adc
+{
+    struct rt_adc_device ifx_adc_device;
+    cyhal_adc_channel_t *adc_ch;
+    char *name;
+};
+
+static struct ifx_adc ifx_adc_obj[] =
+{
+    #ifdef BSP_USING_ADC1
+    ADC1_CONFIG,
+    #endif
+};
+
+static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    cyhal_adc_channel_t *adc_ch;
+    cy_rslt_t result;
+
+    RT_ASSERT(device != RT_NULL);
+    adc_ch = device->parent.user_data;
+
+    const cyhal_adc_channel_config_t channel_config =
+    {
+        .enable_averaging = false,      // Disable averaging for channel
+        .min_acquisition_ns = 1000,     // Minimum acquisition time set to 1us
+        .enabled = enabled              // Sample this channel when ADC performs a scan
+    };
+
+    if (enabled)
+    {
+        /* Initialize ADC. The ADC block which can connect to pin 10[0] is selected */
+        result = cyhal_adc_init(&adc_obj, VPLUS_CHANNEL_0, NULL);
+
+        if (result != RT_EOK)
+        {
+            LOG_E("ADC initialization failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+
+        /* Initialize a channel 0 and configure it to scan P10_0 in single ended mode. */
+        result  = cyhal_adc_channel_init_diff(adc_ch, &adc_obj, VPLUS_CHANNEL_0,
+                                              CYHAL_ADC_VNEG, &channel_config);
+
+        if (result != RT_EOK)
+        {
+            LOG_E("ADC single ended channel initialization failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+
+        /* Update ADC configuration */
+        result = cyhal_adc_configure(&adc_obj, &adc_config);
+
+        if (result != RT_EOK)
+        {
+            printf("ADC configuration update failed. Error: %ld\n", (long unsigned int)result);
+            return -RT_ENOSYS;
+        }
+    }
+    else
+    {
+        cyhal_adc_free(&adc_obj);
+        cyhal_adc_channel_free(adc_ch);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    cyhal_adc_channel_t *adc_ch;
+
+    RT_ASSERT(device != RT_NULL);
+    adc_ch = device->parent.user_data;
+
+    channel = adc_ch->channel_idx;
+
+    *value = cyhal_adc_read(adc_ch);
+
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops at_adc_ops =
+{
+    .enabled = ifx_adc_enabled,
+    .convert = ifx_get_adc_value,
+};
+
+static int rt_hw_adc_init(void)
+{
+    int result = RT_EOK;
+    int i = 0;
+
+    for (i = 0; i < sizeof(ifx_adc_obj) / sizeof(ifx_adc_obj[0]); i++)
+    {
+        /* register ADC device */
+        if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device, ifx_adc_obj[i].name, &at_adc_ops, ifx_adc_obj[i].adc_ch) == RT_EOK)
+        {
+            LOG_D("%s register success", at32_adc_obj[i].name);
+        }
+        else
+        {
+            LOG_E("%s register failed", ifx_adc_obj[i].name);
+            result = -RT_ERROR;
+        }
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_adc_init);
+
+#endif /* BSP_USING_ADC */

project_0/libraries/HAL_Drivers/drv_adc.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-03-28     shelton      first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#include "cyhal.h"
+#include "cybsp.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+
+cyhal_adc_t adc_obj;
+cyhal_adc_channel_t adc_chan_obj;
+
+const cyhal_adc_config_t adc_config =
+{
+    .continuous_scanning = false,   // Continuous Scanning is disabled
+    .average_count = 1,             // Average count disabled
+    .vref = CYHAL_ADC_REF_VDDA,     // VREF for Single ended channel set to VDDA
+    .vneg = CYHAL_ADC_VNEG_VSSA,    // VNEG for Single ended channel set to VSSA
+    .resolution = 12u,              // 12-bit resolution
+    .ext_vref = NC,                 // No connection
+    .bypass_pin = NC                // No connection
+};
+
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                 \
+    {                               \
+        .adc_ch = &adc_chan_obj,    \
+        .name = "adc1",             \
+    }
+#endif /* ADC1_CONFIG */
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/drv_common.c

@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-1      Rbb666       first version
+ */
+
+#include "drv_common.h"
+
+#ifdef RT_USING_SERIAL
+    #include "drv_uart.h"
+#endif
+
+#define DBG_TAG "drv_common"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+/**
+ * this is the timer interrupt service routine.
+ */
+void SysTick_Handler_CB(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* systick configuration */
+void rt_hw_systick_init(void)
+{
+    Cy_SysTick_Init(CY_SYSTICK_CLOCK_SOURCE_CLK_CPU, SystemCoreClock / RT_TICK_PER_SECOND);
+    Cy_SysTick_SetCallback(0, SysTick_Handler_CB);
+    Cy_SysTick_EnableInterrupt();
+}
+
+/**
+ * @brief  this function is executed in case of error occurrence.
+ * @param  none
+ * @retval none
+ */
+void _Error_Handler(char *s, int num)
+{
+    /* User can add his own implementation to report the HAL error return state */
+    LOG_E("Error_Handler at file:%s num:%d", s, num);
+
+    while (1)
+    {
+    }
+}
+
+/**
+ * this function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = SystemCoreClock / 1000000UL;
+
+    do
+    {
+        now = SysTick->VAL;
+        delta = start > now ? start - now : reload + start - now;
+    }
+    while(delta < us_tick * us);
+}
+
+/**
+ * this function will initial ifx board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+    cy_bsp_all_init();
+
+    /* systick init */
+    rt_hw_systick_init();
+
+    /* heap initialization */
+    #if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+    #endif
+
+    /* pin driver initialization is open by default */
+    #ifdef RT_USING_PIN
+    rt_hw_pin_init();
+    #endif
+
+    /* usart driver initialization is open by default */
+    #ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+    #endif
+
+    /* set the shell console output device */
+    #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    #endif
+
+    /* board underlying hardware initialization */
+    #ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+    #endif
+}

project_0/libraries/HAL_Drivers/drv_common.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-1      Rbb666       first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/drv_dac.c

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author                 Notes
+ * 2022-07-28     rtthread qiu       first version
+ */
+#include "drv_dac.h"
+#include "drv_common.h"
+#include <rtthread.h>
+
+#if defined(BSP_USING_DAC1) || defined(BSP_USING_DAC2)
+
+#define LOG_TAG "drv.dac"
+#include <drv_log.h>
+
+struct cyp_dac
+{
+    cy_stc_csdidac_config_t cyhal_dac_device;
+    struct rt_dac_device cyp_dac_device;
+    char *name;
+};
+
+static struct cyp_dac dac_config[] =
+    {
+#ifdef BSP_USING_DAC1
+        DAC1_CONFIG,
+#endif
+#ifdef BSP_USING_DAC2
+        DAC2_CONFIG,
+#endif
+
+};
+
+/*get dac channel*/
+static rt_uint32_t cyp_dac_get_channel(rt_uint32_t channel)
+{
+    rt_uint32_t cyp_dac_channel = 0;
+
+    switch (channel)
+    {
+    case 1:
+        cyp_dac_channel = CY_CSDIDAC_A;
+        break;
+    case 2:
+        cyp_dac_channel = CY_CSDIDAC_B;
+        break;
+    default:
+        RT_ASSERT(0);
+        break;
+    }
+
+    return cyp_dac_channel;
+}
+
+struct cyp_dac cyp_adc_obj[sizeof(dac_config) / sizeof(dac_config[0])];
+
+cy_stc_csdidac_context_t csdidac_context;
+
+/*dac device enable*/
+static rt_err_t cyp_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    cy_rslt_t result;
+
+    rt_uint32_t cyp_channel;
+
+    RT_ASSERT(device != RT_NULL);
+
+    cyhal_dac_t *dac_device;
+
+    dac_device = device->parent.user_data;
+
+    /* get current dac channel*/
+    cyp_channel = cyp_dac_get_channel(channel);
+
+    /*DAC device init*/
+    result = Cy_CSDIDAC_Init(&CSDIDAC_csdidac_config, &csdidac_context);
+
+    if (result != RT_EOK)
+    {
+        LOG_E("Cy_CSDIDAC_Init fail = %d\n", result);
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+/*dac device disable*/
+static rt_err_t cyp_dac_disable(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    rt_uint32_t cyp_channel;
+
+    cy_rslt_t result;
+
+    RT_ASSERT(device != RT_NULL);
+
+    cyhal_dac_t *dac_device;
+
+    dac_device = device->parent.user_data;
+
+    cyp_channel = cyp_dac_get_channel(channel);
+
+    /*DAC free device*/
+    result = Cy_CSDIDAC_OutputDisable(cyp_channel, &csdidac_context);
+    if (result != RT_EOK)
+    {
+        LOG_E("DAC Outputdisable failed. Error: %d\n", result);
+        return -RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+/*set dac output value*/
+static rt_err_t cyp_adc_convert(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    cy_rslt_t result;
+
+    rt_uint32_t cyp_channel;
+
+    cyp_channel = cyp_dac_get_channel(channel);
+
+    result = Cy_CSDIDAC_OutputEnable(cyp_channel, *value, &csdidac_context);
+    if (result != RT_EOK)
+    {
+        LOG_E("DAC  channel initialization failed. Error: %d\n", result);
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+static const struct rt_dac_ops cyp_dac_ops =
+{
+    .disabled = cyp_dac_disable,
+    .enabled = cyp_dac_enabled,
+    .convert = cyp_adc_convert,
+};
+
+/*dac device init*/
+static int rt_hw_dac_init(void)
+{
+    int result = RT_EOK;
+
+    /* save dac name */
+    char name_buf[5] = {'d', 'a', 'c', '0', 0};
+
+    int i = 0;
+
+    i = sizeof(dac_config) / sizeof(dac_config[0]);
+
+    for (i = 0; i < sizeof(dac_config) / sizeof(dac_config[0]); i++)
+    {
+
+#ifdef BSP_USING_DAC1
+        name_buf[3] = '1';
+#endif
+
+#ifdef BSP_USING_DAC2
+        name_buf[3] = '2';
+#endif
+        /* register DAC device */
+        if (rt_hw_dac_register(&cyp_adc_obj[i].cyp_dac_device, name_buf, &cyp_dac_ops, RT_NULL) == RT_EOK)
+        {
+            LOG_E("dac device register success\n");
+        }
+        else
+        {
+            LOG_E("dac device register fail\n");
+            result = -RT_ERROR;
+        }
+    }
+    return result;
+}
+
+INIT_BOARD_EXPORT(rt_hw_dac_init);
+
+#endif /* BSP_USING_DAC1 /BSP_USING_DAC2 */

project_0/libraries/HAL_Drivers/drv_dac.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author                 Notes
+ * 2022-07-28     rtthread qiu       first version
+ */
+#ifndef __DRV__DAC_H__
+#define __DRV__DAC_H__
+#include "rtconfig.h"
+#include "cycfg.h"
+#include <rtthread.h>
+#include "cy_csdidac.h"
+#include "cycfg_peripherals.h"
+
+static const cy_stc_csdidac_pin_t CSDIDAC_csdidac_a_pin =
+{
+    .ioPcPtr = GPIO_PRT10,
+    .pin = 0u,
+};
+static const cy_stc_csdidac_pin_t CSDIDAC_csdidac_b_pin =
+{
+    .ioPcPtr = GPIO_PRT10,
+    .pin = 0u,
+};
+
+const cy_stc_csdidac_config_t CSDIDAC_csdidac_config =
+{
+    .base = CSD0,
+    .csdCxtPtr = &cy_csd_0_context,
+    .configA = CY_CSDIDAC_GPIO,
+    .configB = CY_CSDIDAC_GPIO,
+    .ptrPinA = (const cy_stc_csdidac_pin_t *)&CSDIDAC_csdidac_a_pin,
+    .ptrPinB = (const cy_stc_csdidac_pin_t *)&CSDIDAC_csdidac_b_pin,
+    .cpuClk = 100000000u,
+    .csdInitTime = 25u,
+};
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG     \
+    {                   \
+        .name = "dac1", \
+    }
+#endif /* DAC1_CONFIG */
+#endif /*BSP_USING_DAC2*/
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG     \
+    {                   \
+        .name = "dac2", \
+    }
+#endif /* DAC2_CONFIG */
+#endif /*BSP_USING_DAC2*/
+
+#endif /*__DRV__DAC_H__*/

project_0/libraries/HAL_Drivers/drv_flash.c

@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-26     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_ON_CHIP_FLASH
+#include "drv_flash.h"
+
+#if defined(RT_USING_FAL)
+    #include "fal.h"
+#endif
+
+#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#include <drv_log.h>
+
+static cyhal_flash_t flash_obj;
+static cyhal_flash_block_info_t block_info;
+static cyhal_flash_info_t flash_info;
+
+int _flash_init(void)
+{
+    cy_rslt_t err = CY_RSLT_SUCCESS;
+    /* Init Flash */
+    err = cyhal_flash_init(&flash_obj);
+
+    /* Handle Error */
+    if (CY_RSLT_SUCCESS != err)
+    {
+        LOG_E("\r\n Flash Init failed");
+    }
+
+    cyhal_flash_get_info(&flash_obj, &flash_info);
+
+    block_info = flash_info.blocks[flash_info.block_count - 1u];
+
+    return 0;
+}
+
+static rt_uint32_t get_page_32k(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, IFX_EFLASH_PAGE_SIZE);
+
+    return page;
+}
+
+/**
+  * @brief  gets the page of a given address
+  * @param  addr: address of the flash memory
+  * @retval the page of a given address
+  */
+static rt_uint32_t get_page_256k(uint32_t addr)
+{
+    rt_uint32_t page = 0;
+
+    page = RT_ALIGN_DOWN(addr, IFX_FLASH_PAGE_SIZE);
+
+    return page;
+}
+
+int ifx_flash_read_32k(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_uint32_t i;
+
+    if ((addr + size) > IFX_EFLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * @brief read data from flash.
+ * @note this operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int ifx_flash_read_256k(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_uint32_t i;
+
+    if ((addr + size) > IFX_FLASH_END_ADDRESS)
+    {
+        LOG_E("read outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * @brief write data to flash.
+ * @note this operation's units is word.
+ * @note this operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int ifx_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_base_t level;
+    cy_rslt_t err = CY_RSLT_SUCCESS;
+    size_t written_size = 0;
+
+#define BSP_FEATURE_FLASH_WRITE_SIZE 512U
+
+    if (size % BSP_FEATURE_FLASH_WRITE_SIZE)
+    {
+        LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_WRITE_SIZE);
+        return -RT_EINVAL;
+    }
+
+    while (written_size < size)
+    {
+        level = rt_hw_interrupt_disable();
+        /* Write code flash data*/
+        err = cyhal_flash_write(&flash_obj, addr + written_size, (rt_uint32_t *)(buf + written_size));
+        rt_hw_interrupt_enable(level);
+
+        /* Error Handle */
+        if (CY_RSLT_SUCCESS != err)
+        {
+            LOG_E("Write API failed");
+            return -RT_EIO;
+        }
+
+        written_size += BSP_FEATURE_FLASH_WRITE_SIZE;
+    }
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+int ifx_flash_erase_32k(rt_uint32_t addr, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    if ((end_addr) > IFX_EFLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while (addr < end_addr)
+    {
+        page_addr = get_page_32k(addr);
+
+        if (cyhal_flash_erase(&flash_obj, page_addr) != CY_RSLT_SUCCESS)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += IFX_FLASH_PAGE_SIZE;
+    }
+
+    rt_hw_interrupt_enable(level);
+
+__exit:
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * @brief erase data on flash .
+ * @note this operation is irreversible.
+ * @note this operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int ifx_flash_erase_256k(rt_uint32_t addr, rt_uint32_t size)
+{
+    rt_err_t result = RT_EOK;
+    rt_uint32_t end_addr = addr + size;
+    rt_uint32_t page_addr = 0;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    if ((end_addr) > IFX_FLASH_END_ADDRESS)
+    {
+        LOG_E("erase outrange flash size! addr is (0x%p)", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    while (addr < end_addr)
+    {
+        page_addr = get_page_256k(addr);
+
+        if (cyhal_flash_erase(&flash_obj, page_addr) != CY_RSLT_SUCCESS)
+        {
+            result = -RT_ERROR;
+            goto __exit;
+        }
+
+        addr += IFX_FLASH_PAGE_SIZE;
+    }
+
+    rt_hw_interrupt_enable(level);
+
+__exit:
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+#if defined(RT_USING_FAL)
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size);
+
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size);
+
+static int fal_flash_erase_32k(long offset, size_t size);
+static int fal_flash_erase_256k(long offset, size_t size);
+
+const struct fal_flash_dev ifx_onchip_flash_32k =
+{
+    "onchip_flash_32k",
+    IFX_EFLASH_START_ADRESS,
+    IFX_EFLASH_SIZE,
+    IFX_EFLASH_PAGE_SIZE,
+    {
+        NULL,
+        fal_flash_read_32k,
+        fal_flash_write_32k,
+        fal_flash_erase_32k
+    }
+};
+
+const struct fal_flash_dev ifx_onchip_flash_256k =
+{
+    "onchip_flash_256k",
+    IFX_FLASH_START_ADRESS,
+    IFX_FLASH_SIZE,
+    IFX_FLASH_PAGE_SIZE,
+    {
+        _flash_init,
+        fal_flash_read_256k,
+        fal_flash_write_256k,
+        fal_flash_erase_256k
+    }
+};
+
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_read_32k(ifx_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_read_256k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_read_256k(ifx_onchip_flash_256k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_write(ifx_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_256k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return ifx_flash_write(ifx_onchip_flash_256k.addr + offset, buf, size);
+}
+
+static int fal_flash_erase_32k(long offset, size_t size)
+{
+    return ifx_flash_erase_32k(ifx_onchip_flash_32k.addr + offset, size);
+}
+
+static int fal_flash_erase_256k(long offset, size_t size)
+{
+    return ifx_flash_erase_256k(ifx_onchip_flash_256k.addr + offset, size);
+}
+
+#if defined(BSP_USING_ON_CHIP_FLASH)
+static int rt_hw_on_chip_flash_init(void)
+{
+    fal_init();
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(rt_hw_on_chip_flash_init);
+
+int flash64k_test(void)
+{
+#define TEST_OFF (ifx_onchip_flash_256k.len - 0x40000)
+    const struct fal_partition *param;
+    uint8_t write_buffer[512U] = {0};
+    uint8_t read_buffer[512U] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint16_t index = 0; index < 512U; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    param = fal_partition_find("app");
+
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition app!");
+        return -1;
+    }
+
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST_OFF, 0x40000);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST_OFF, read_buffer, 128U);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < 128U; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash64k_test, "drv flash64k test.");
+
+int flash32k_test(void)
+{
+#define TEST32_OFF (ifx_onchip_flash_32k.len - 0x8000)
+    const struct fal_partition *param;
+    uint8_t write_buffer[512U] = {0};
+    uint8_t read_buffer[512U] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint16_t index = 0; index < 512U; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    param = fal_partition_find("param");
+
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition param!");
+        return -1;
+    }
+
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST32_OFF, 0x8000);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST32_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST32_OFF, read_buffer, 128U);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < 128U; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash32k_test, "drv flash32k test.");
+#endif
+#endif
+#endif /* BSP_USING_ON_CHIP_FLASH */

project_0/libraries/HAL_Drivers/drv_flash.h

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-26     Rbb666       first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int ifx_flash_read(rt_uint32_t addr, rt_uint8_t *buf, rt_uint32_t size);
+int ifx_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, rt_uint32_t size);
+int ifx_flash_erase(rt_uint32_t addr, rt_uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

project_0/libraries/HAL_Drivers/drv_gpio.c

@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-07-1      Rbb666            first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+#define PIN_GET(pin)        ((uint8_t)(((uint8_t)pin) & 0x07U))
+#define PORT_GET(pin)       ((uint8_t)(((uint8_t)pin) >> 3U))
+
+#define __IFX_PORT_MAX      15u
+
+#define PIN_IFXPORT_MAX     __IFX_PORT_MAX
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {CYHAL_PORT_0,  ioss_interrupts_gpio_0_IRQn},
+    {CYHAL_PORT_1,  ioss_interrupts_gpio_1_IRQn},
+    {CYHAL_PORT_2,  ioss_interrupts_gpio_2_IRQn},
+    {CYHAL_PORT_3,  ioss_interrupts_gpio_3_IRQn},
+    {CYHAL_PORT_4,  ioss_interrupts_gpio_4_IRQn},
+    {CYHAL_PORT_5,  ioss_interrupts_gpio_5_IRQn},
+    {CYHAL_PORT_6,  ioss_interrupts_gpio_6_IRQn},
+    {CYHAL_PORT_7,  ioss_interrupts_gpio_7_IRQn},
+    {CYHAL_PORT_8,  ioss_interrupts_gpio_8_IRQn},
+    {CYHAL_PORT_9,  ioss_interrupts_gpio_9_IRQn},
+    {CYHAL_PORT_10,  ioss_interrupts_gpio_10_IRQn},
+    {CYHAL_PORT_11,  ioss_interrupts_gpio_11_IRQn},
+    {CYHAL_PORT_12,  ioss_interrupts_gpio_12_IRQn},
+    {CYHAL_PORT_13,  ioss_interrupts_gpio_13_IRQn},
+    {CYHAL_PORT_14,  ioss_interrupts_gpio_14_IRQn},
+};
+
+static struct rt_pin_irq_hdr pin_irq_handler_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+rt_inline void pin_irq_handler(int irqno)
+{
+    if (pin_irq_handler_tab[irqno].hdr)
+    {
+        pin_irq_handler_tab[irqno].hdr(pin_irq_handler_tab[irqno].args);
+    }
+}
+
+void gpio_exint_handler(uint16_t GPIO_Port)
+{
+    pin_irq_handler(GPIO_Port);
+}
+
+/* interrupt callback definition*/
+static void irq_callback(void *callback_arg, cyhal_gpio_event_t event)
+{
+    /* To avoid compiler warnings */
+    (void) callback_arg;
+    (void) event;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    gpio_exint_handler(*(rt_uint16_t *)callback_arg);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+cyhal_gpio_callback_data_t irq_cb_data;
+
+static void ifx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    rt_uint16_t gpio_pin;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_pin = pin;
+    }
+    else
+    {
+        return;
+    }
+
+    switch (mode)
+    {
+        case PIN_MODE_OUTPUT:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true);
+            break;
+
+        case PIN_MODE_INPUT:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_INPUT, CYHAL_GPIO_DRIVE_NONE, false);
+            break;
+
+        case PIN_MODE_INPUT_PULLUP:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
+            break;
+
+        case PIN_MODE_INPUT_PULLDOWN:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLDOWN, false);
+            break;
+
+        case PIN_MODE_OUTPUT_OD:
+            cyhal_gpio_init(gpio_pin, CYHAL_GPIO_DIR_BIDIRECTIONAL, CYHAL_GPIO_DRIVE_PULLUP, true);
+            break;
+    }
+}
+
+static void ifx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    rt_uint16_t gpio_pin;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_pin = pin;
+    }
+    else
+    {
+        return;
+    }
+
+    cyhal_gpio_write(gpio_pin, value);
+}
+
+static int ifx_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    rt_uint16_t gpio_pin;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_pin = pin;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    return cyhal_gpio_read(gpio_pin);
+}
+
+static rt_err_t ifx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                   rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    rt_uint16_t gpio_port;
+    rt_uint16_t gpio_pin;
+    rt_base_t level;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_port = PORT_GET(pin);
+        gpio_pin = pin;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    level = rt_hw_interrupt_disable();
+
+    if (pin_irq_handler_tab[gpio_port].pin == pin &&
+            pin_irq_handler_tab[gpio_port].hdr == hdr &&
+            pin_irq_handler_tab[gpio_port].mode == mode &&
+            pin_irq_handler_tab[gpio_port].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if (pin_irq_handler_tab[gpio_port].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+
+    pin_irq_handler_tab[gpio_port].pin = pin;
+    pin_irq_handler_tab[gpio_port].hdr = hdr;
+    pin_irq_handler_tab[gpio_port].mode = mode;
+    pin_irq_handler_tab[gpio_port].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_uint16_t gpio_port;
+    rt_uint16_t gpio_pin;
+    rt_base_t level;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_port = PORT_GET(pin);
+        gpio_pin = pin;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    level = rt_hw_interrupt_disable();
+
+    if (pin_irq_handler_tab[gpio_port].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    pin_irq_handler_tab[gpio_port].pin = -1;
+    pin_irq_handler_tab[gpio_port].hdr = RT_NULL;
+    pin_irq_handler_tab[gpio_port].mode = 0;
+    pin_irq_handler_tab[gpio_port].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                   rt_uint32_t enabled)
+{
+    rt_uint16_t gpio_port;
+    rt_uint16_t gpio_pin;
+    rt_base_t level;
+    rt_uint8_t pin_irq_mode;
+
+    const struct pin_irq_map *irqmap;
+
+    if (PORT_GET(pin) < PIN_IFXPORT_MAX)
+    {
+        gpio_port = PORT_GET(pin);
+        gpio_pin = pin;
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_handler_tab[gpio_port].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return -RT_EINVAL;
+        }
+
+        irqmap = &pin_irq_map[gpio_port];
+
+        irq_cb_data.callback = irq_callback;
+        irq_cb_data.callback_arg = (rt_uint16_t *)&pin_irq_map[gpio_port].port;
+
+        cyhal_gpio_register_callback(gpio_pin, &irq_cb_data);
+
+        Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(gpio_pin), CYHAL_GET_PIN(gpio_pin));
+
+        switch (pin_irq_handler_tab[gpio_port].mode)
+        {
+            case PIN_IRQ_MODE_RISING:
+                pin_irq_mode = CYHAL_GPIO_IRQ_RISE;
+                break;
+
+            case PIN_IRQ_MODE_FALLING:
+                pin_irq_mode = CYHAL_GPIO_IRQ_FALL;
+                break;
+
+            case PIN_IRQ_MODE_RISING_FALLING:
+                pin_irq_mode = CYHAL_GPIO_IRQ_BOTH;
+                break;
+
+            default:
+                break;
+        }
+
+        cyhal_gpio_enable_event(gpio_pin, pin_irq_mode, GPIO_INTERRUPT_PRIORITY, RT_TRUE);
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        Cy_GPIO_Port_Deinit(CYHAL_GET_PORTADDR(gpio_pin));
+
+        #if !defined(COMPONENT_CAT1C)
+        IRQn_Type irqn = (IRQn_Type)(irqmap->irqno + PORT_GET(irqmap->port));
+        #endif
+        _cyhal_irq_disable(irqn);
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _ifx_pin_ops =
+{
+    ifx_pin_mode,
+    ifx_pin_write,
+    ifx_pin_read,
+    ifx_pin_attach_irq,
+    ifx_pin_dettach_irq,
+    ifx_pin_irq_enable,
+    RT_NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_ifx_pin_ops, RT_NULL);
+}
+
+#endif /* RT_USING_PIN */

project_0/libraries/HAL_Drivers/drv_gpio.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-07-1      Rbb666            first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "drv_common.h"
+
+#include "cyhal_irq_psoc.h"
+
+#define GPIO_INTERRUPT_PRIORITY (7u)
+
+#define GET_PIN(PORTx,PIN)      ((((uint8_t)(PORTx)) << 3U) + ((uint8_t)(PIN)))
+
+struct pin_irq_map
+{
+    rt_uint16_t port;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */

project_0/libraries/HAL_Drivers/drv_hwtimer.c

@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author                   Notes
+ * 2022-07-29     rtthread qiu       first version
+ */
+#include "drv_common.h"
+#include "drv_hwtimer.h"
+
+#include <board.h>
+#ifdef BSP_USING_TIM
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.hwtimer"
+#include <drv_log.h>
+static void isr_timer(void *callback_arg, cyhal_timer_event_t event);
+
+#ifdef RT_USING_HWTIMER
+enum
+{
+#ifdef BSP_USING_TIM1
+    TIM1_INDEX,
+#endif
+#ifdef BSP_USING_TIM2
+    TIM2_INDEX,
+#endif
+};
+
+struct cyp_hwtimer
+{
+    rt_hwtimer_t time_device;
+    cyhal_timer_t tim_handle;
+    IRQn_Type tim_irqn;
+    char *name;
+};
+
+static struct cyp_hwtimer cyp_hwtimer_obj[] =
+{
+#ifdef BSP_USING_TIM1
+    TIM1_CONFIG,
+#endif
+#ifdef BSP_USING_TIM2
+    TIM2_CONFIG,
+#endif
+};
+
+static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
+{
+    RT_ASSERT(timer != RT_NULL);
+
+    cy_rslt_t result = RT_EOK;
+
+    cyhal_timer_t *tim = RT_NULL;
+
+    tim = (cyhal_timer_t *)timer->parent.user_data;
+
+    const cyhal_timer_cfg_t init_timer_cfg =
+        {
+            .compare_value = 0,              /* Timer compare value, not used */
+            .period = 9999,                  /* Defines the timer period */
+            .direction = CYHAL_TIMER_DIR_UP, /* Timer counts up */
+            .is_compare = false,             /* Don't use compare mode */
+            .is_continuous = true,           /* Run timer indefinitely */
+            .value = 0                       /* Initial value of counter */
+        };
+
+    if (state)
+    {
+        /* Initialize the timer object. Does not use input pin ('pin' is NC) and
+         * does not use a pre-configured clock source ('clk' is NULL). */
+        result = cyhal_timer_init(tim, NC, NULL);
+
+        if (result != CY_RSLT_SUCCESS)
+        {
+            LOG_E("timer init error \r\n");
+            return;
+        }
+        else
+        {
+            /* Configure timer period and operation mode such as count direction,
+                duration */
+            cyhal_timer_configure(tim, &init_timer_cfg);
+
+            /* Set the frequency of timer's clock source */
+            cyhal_timer_set_frequency(tim, 10000);
+
+            cyhal_timer_start(tim);
+        }
+    }
+    else
+    {
+        cyhal_timer_free(tim);
+        LOG_E("free time \r\n");
+    }
+}
+
+static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
+{
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(opmode != RT_NULL);
+
+    cy_rslt_t result = RT_EOK;
+
+    cyhal_timer_t *tim = RT_NULL;
+
+    tim = (cyhal_timer_t *)timer->parent.user_data;
+
+    const cyhal_timer_cfg_t init_timer_cfg =
+        {
+            .compare_value = 0,              /* Timer compare value, not used */
+            .period = t - 1,                 /* Defines the timer period */
+            .direction = CYHAL_TIMER_DIR_UP, /* Timer counts up */
+            .is_compare = false,             /* Don't use compare mode */
+            .is_continuous = true,           /* Run timer indefinitely */
+            .value = 0                       /* Initial value of counter */
+        };
+    /* Configure timer period and operation mode such as count direction,
+   duration */
+    cyhal_timer_configure(tim, &init_timer_cfg);
+
+    if (opmode == HWTIMER_MODE_ONESHOT)
+    {
+        /* set timer to single mode */
+        cyhal_timer_stop(tim);
+    }
+    else
+    {
+        cyhal_timer_reset(tim);
+    }
+
+    result = cyhal_timer_start(tim);
+    if (result != CY_RSLT_SUCCESS)
+    {
+        LOG_E("time start error\r\n");
+        cyhal_timer_free(tim);
+    }
+
+    /* Assign the ISR to execute on timer interrupt */
+    cyhal_timer_register_callback(tim, isr_timer, NULL);
+    /* Set the event on which timer interrupt occurs and enable it */
+    cyhal_timer_enable_event(tim, CYHAL_TIMER_IRQ_TERMINAL_COUNT, 1, true);
+
+    return result;
+}
+
+static void timer_stop(rt_hwtimer_t *timer)
+{
+
+    RT_ASSERT(timer != RT_NULL);
+
+    cyhal_timer_t *tim = RT_NULL;
+
+    tim = (cyhal_timer_t *)timer->parent.user_data;
+
+    cyhal_timer_stop(tim);
+}
+
+static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
+{
+    cyhal_timer_t *tim = RT_NULL;
+
+    rt_uint32_t count;
+
+    RT_ASSERT(timer != RT_NULL);
+
+    tim = (cyhal_timer_t *)timer->parent.user_data;
+
+    count = cyhal_timer_read(tim);
+
+    return count;
+}
+
+static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
+{
+    RT_ASSERT(timer != RT_NULL);
+    RT_ASSERT(arg != RT_NULL);
+
+    cyhal_timer_t *tim = RT_NULL;
+
+    rt_err_t result = -RT_ERROR;
+
+    tim = (cyhal_timer_t *)timer->parent.user_data;
+
+    switch (cmd)
+    {
+    case HWTIMER_CTRL_FREQ_SET:
+    {
+        rt_uint32_t freq;
+        rt_uint16_t val;
+
+        freq = *((rt_uint32_t *)arg);
+
+        result = cyhal_timer_set_frequency(tim, freq);
+
+        if (result != CY_RSLT_SUCCESS)
+        {
+            LOG_E("cyhal_timer_set_frequency error\r\n");
+            return RT_ERROR;
+        }
+    }
+    break;
+    default:
+    {
+        result = -RT_EINVAL;
+    }
+    break;
+    }
+    return result;
+}
+
+static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
+
+static const struct rt_hwtimer_ops _ops =
+    {
+        .init = timer_init,
+        .start = timer_start,
+        .stop = timer_stop,
+        .count_get = timer_counter_get,
+        .control = timer_ctrl,
+};
+
+#ifdef BSP_USING_TIM1
+static void isr_timer(void *callback_arg, cyhal_timer_event_t event)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    (void)callback_arg;
+    (void)event;
+
+    rt_device_hwtimer_isr(&cyp_hwtimer_obj[TIM1_INDEX].time_device);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_TIM2
+static void isr_timer(void *callback_arg, cyhal_timer_event_t event)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    (void)callback_arg;
+    (void)event;
+
+    rt_device_hwtimer_isr(&cyp_hwtimer_obj[TIM2_INDEX].time_device);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+int cyp_hwtimer_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(cyp_hwtimer_obj) / sizeof(cyp_hwtimer_obj[0]); i++)
+    {
+        cyp_hwtimer_obj[i].time_device.info = &_info;
+        cyp_hwtimer_obj[i].time_device.ops = &_ops;
+        if (rt_device_hwtimer_register(&cyp_hwtimer_obj[i].time_device, cyp_hwtimer_obj[i].name, &cyp_hwtimer_obj[i].tim_handle) != RT_EOK)
+        {
+            LOG_E("%s register failed", cyp_hwtimer_obj[i].name);
+            result = -RT_ERROR;
+        }
+    }
+    return result;
+}
+INIT_BOARD_EXPORT(cyp_hwtimer_init);
+
+#endif /*RT_USING_HWTIMER*/
+#endif /*BSP_USING_TIM*/
+
+/* this is a hwtimer test demo*/
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define HWTIMER_DEV_NAME "time2" /* device name */
+
+static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("this is hwtimer timeout callback fucntion!\n");
+    rt_kprintf("tick is :%d !\n", rt_tick_get());
+
+    return 0;
+}
+
+int hwtimer_sample()
+{
+    rt_err_t ret = RT_EOK;
+    rt_hwtimerval_t timeout_s;
+    rt_device_t hw_dev = RT_NULL;
+    rt_hwtimer_mode_t mode;
+    rt_uint32_t freq = 10000;
+
+    hw_dev = rt_device_find(HWTIMER_DEV_NAME);
+    if (hw_dev == RT_NULL)
+    {
+        rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
+        return ret;
+    }
+
+    rt_device_set_rx_indicate(hw_dev, timeout_cb);
+
+    rt_device_control(hw_dev, HWTIMER_CTRL_FREQ_SET, &freq);
+
+    mode = HWTIMER_MODE_PERIOD;
+    ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set mode failed! ret is :%d\n", ret);
+        return ret;
+    }
+
+    /* Example Set the timeout period of the timer */
+    timeout_s.sec = 3;  /* secend */
+    timeout_s.usec = 0; /* microsecend */
+    if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
+    {
+        rt_kprintf("set timeout value failed\n");
+        return RT_ERROR;
+    }
+
+    while (1)
+    {
+        rt_thread_mdelay(1500);
+
+        rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
+        rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
+    }
+    return ret;
+}
+MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);

project_0/libraries/HAL_Drivers/drv_hwtimer.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2022-07-29     rtthread qiu      first version
+ */
+
+#ifndef __DRV_HWTIMER_H__
+#define __DRV_HWTIMER_H__
+
+#include <rtthread.h>
+
+#include "cy_pdl.h"
+#include "cyhal.h"
+#include "cybsp.h"
+#include "cy_retarget_io.h"
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG            \
+    {                                  \
+        .maxfreq = 1000000,            \
+        .minfreq = 2000,               \
+        .maxcnt = 0xFFFF,              \
+        .cntmode = HWTIMER_CNTMODE_UP, \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM1
+#ifndef TIM1_CONFIG
+#define TIM1_CONFIG                            \
+    {                                          \
+        .tim_irqn = tcpwm_0_interrupts_0_IRQn, \
+        .name = "time1",                       \
+    }
+#endif /*TIM1_CONFIG*/
+#endif /* BSP_USING_TIM1 */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                            \
+    {                                          \
+        .tim_irqn = tcpwm_1_interrupts_0_IRQn, \
+        .name = "time2",                       \
+    }
+#endif /*TIM2_CONFIG*/
+#endif /* BSP_USING_TIM2 */
+
+#endif /* __DRV_HWTIMER_H__ */

project_0/libraries/HAL_Drivers/drv_i2c.c

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-08     Rbb666       first implementation.
+ */
+
+#include "board.h"
+
+#if defined(RT_USING_I2C)
+#if defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C6)
+#include <rtdevice.h>
+
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                  \
+    {                                \
+        .name = "i2c3",              \
+        .scl_pin = BSP_I2C3_SCL_PIN, \
+        .sda_pin = BSP_I2C3_SDA_PIN, \
+    }
+#endif /* I2C3_CONFIG */
+#endif
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                  \
+    {                                \
+        .name = "i2c6",              \
+        .scl_pin = BSP_I2C6_SCL_PIN, \
+        .sda_pin = BSP_I2C6_SDA_PIN, \
+    }
+#endif /* I2C6_CONFIG */
+
+enum
+{
+#ifdef BSP_USING_HW_I2C3
+    I2C3_INDEX,
+#endif
+#ifdef BSP_USING_HW_I2C6
+    I2C6_INDEX,
+#endif
+};
+
+struct ifx_i2c_config
+{
+    char *name;
+    rt_uint32_t scl_pin;
+    rt_uint32_t sda_pin;
+};
+
+struct ifx_i2c
+{
+    cyhal_i2c_t mI2C;
+    cyhal_i2c_cfg_t mI2C_cfg;
+    struct ifx_i2c_config *config;
+    struct rt_i2c_bus_device i2c_bus;
+};
+
+static struct ifx_i2c_config i2c_config[] =
+    {
+#ifdef BSP_USING_HW_I2C3
+        I2C3_CONFIG,
+#endif
+
+#ifdef BSP_USING_HW_I2C6
+        I2C6_CONFIG,
+#endif
+};
+
+static struct ifx_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0};
+
+static int ifx_i2c_read(struct ifx_i2c *hi2c, rt_uint16_t slave_address, rt_uint8_t *p_buffer, rt_uint16_t data_byte)
+{
+    if (cyhal_i2c_master_read(&hi2c->mI2C, slave_address, p_buffer, data_byte, 10, true) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+
+    return 0;
+}
+
+static int ifx_i2c_write(struct ifx_i2c *hi2c, uint16_t slave_address, uint8_t *p_buffer, uint16_t data_byte)
+{
+    if (cyhal_i2c_master_write(&hi2c->mI2C, slave_address, p_buffer, data_byte, 10, true) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+
+    return 0;
+}
+
+static rt_size_t _i2c_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    struct ifx_i2c *i2c_obj;
+
+    RT_ASSERT(bus != RT_NULL);
+    RT_ASSERT(msgs != RT_NULL);
+
+    i2c_obj = rt_container_of(bus, struct ifx_i2c, i2c_bus);
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (ifx_i2c_read(i2c_obj, msg->addr, msg->buf, msg->len) != 0)
+            {
+                goto out;
+            }
+        }
+        else
+        {
+            if (ifx_i2c_write(i2c_obj, msg->addr, msg->buf, msg->len) != 0)
+            {
+                goto out;
+            }
+        }
+    }
+
+out:
+
+    return i;
+}
+
+static const struct rt_i2c_bus_device_ops i2c_ops =
+    {
+        _i2c_xfer,
+        RT_NULL,
+        RT_NULL};
+
+void HAL_I2C_Init(struct ifx_i2c *obj)
+{
+    rt_uint8_t result = RT_EOK;
+
+    result = cyhal_i2c_init(&obj->mI2C, obj->config->sda_pin, obj->config->scl_pin, NULL);
+    RT_ASSERT(result == RT_EOK);
+
+    result = cyhal_i2c_configure(&obj->mI2C, &obj->mI2C_cfg);
+    RT_ASSERT(result == RT_EOK);
+}
+
+int rt_hw_i2c_init(void)
+{
+    rt_err_t result;
+    cyhal_i2c_t mI2C;
+
+    for (int i = 0; i < sizeof(i2c_config) / sizeof(i2c_config[0]); i++)
+    {
+        i2c_objs[i].config = &i2c_config[i];
+        i2c_objs[i].i2c_bus.parent.user_data = &i2c_config[i];
+
+        i2c_objs[i].mI2C_cfg.is_slave = false;
+        i2c_objs[i].mI2C_cfg.address = 0;
+        i2c_objs[i].mI2C_cfg.frequencyhal_hz = (400000UL);
+
+        i2c_objs[i].mI2C = mI2C;
+
+        i2c_objs[i].i2c_bus.ops = &i2c_ops;
+
+        HAL_I2C_Init(&i2c_objs[i]);
+
+        result = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_config[i].name);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif /* defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) */

project_0/libraries/HAL_Drivers/drv_log.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+    #define DBG_TAG               "drv"
+#else
+    #define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

project_0/libraries/HAL_Drivers/drv_pwm.c

@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-13     Rbb666       first version
+ */
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+
+#include <drivers/rt_drv_pwm.h>
+#include "drv_gpio.h"
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.pwm"
+#include <drv_log.h>
+
+struct rt_device_pwm pwm_device;
+
+struct ifx_pwm
+{
+    struct rt_device_pwm pwm_device;
+    cyhal_pwm_t *pwm_obj;
+    rt_uint8_t channel;
+    char *name;
+    rt_uint8_t gpio;
+};
+
+static struct ifx_pwm ifx_pwm_obj[] =
+{
+#ifdef BSP_USING_PWM0_PORT13
+    PWM0_CH3_PORT13_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT2
+    PWM0_CH7_PORT2_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT5
+    PWM0_CH7_PORT5_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT7
+    PWM0_CH7_PORT7_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT9
+    PWM0_CH7_PORT9_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT10
+    PWM0_CH7_PORT10_CONFIG,
+#endif
+
+#ifdef BSP_USING_PWM0_PORT12
+    PWM0_CH7_PORT12_CONFIG,
+#endif
+};
+
+static rt_err_t drv_pwm_enable(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
+{
+    /* get the value of channel */
+    rt_uint32_t channel = configuration->channel;
+
+    if (!configuration->complementary || configuration->complementary)
+    {
+        if (!enable)
+        {
+            if (channel == 3)
+            {
+                htim->tcpwm.resource.channel_num = channel;
+            }
+            else if (channel == 7)
+            {
+                htim->tcpwm.resource.channel_num = channel;
+            }
+            cyhal_pwm_stop(htim);
+        }
+        else
+        {
+            if (channel == 3)
+            {
+                htim->tcpwm.resource.channel_num = channel;
+            }
+            else if (channel == 7)
+            {
+                htim->tcpwm.resource.channel_num = channel;
+            }
+            cyhal_pwm_start(htim);
+        }
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_set(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration)
+{
+    rt_uint64_t tim_clock;
+    rt_uint32_t period, pulse;
+
+    tim_clock = (rt_uint32_t)(htim->tcpwm.clock_hz);
+
+    htim->tcpwm.resource.channel_num = configuration->channel;
+
+    period = (unsigned long long)configuration->period / 1000ULL;
+
+    pulse = (unsigned long long)configuration->pulse / 1000ULL;
+
+    cyhal_pwm_set_period(htim, period, pulse);
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_get(cyhal_pwm_t *htim, struct rt_pwm_configuration *configuration)
+{
+    uint32_t Period = Cy_TCPWM_PWM_GetPeriod0(htim->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(htim->tcpwm.resource));
+
+    uint32_t Compare = Cy_TCPWM_PWM_GetCounter(htim->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(htim->tcpwm.resource));
+
+    configuration->period = Period;
+
+    configuration->pulse = Compare;
+
+    return RT_EOK;
+}
+
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    cyhal_pwm_t *htim = (cyhal_pwm_t *)device->parent.user_data;
+
+    switch (cmd)
+    {
+    case PWMN_CMD_ENABLE:
+        configuration->complementary = RT_TRUE;
+
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(htim, configuration, RT_TRUE);
+
+    case PWMN_CMD_DISABLE:
+        configuration->complementary = RT_FALSE;
+
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(htim, configuration, RT_FALSE);
+
+    case PWM_CMD_SET:
+        return drv_pwm_set(htim, configuration);
+
+    case PWM_CMD_GET:
+        return drv_pwm_get(htim, configuration);
+
+    default:
+        return RT_EINVAL;
+    }
+}
+
+static struct rt_pwm_ops drv_ops = {drv_pwm_control};
+
+static rt_err_t ifx_hw_pwm_init(struct ifx_pwm *device)
+{
+    rt_err_t result = RT_EOK;
+
+    RT_ASSERT(device != RT_NULL);
+
+    /* config pwm channel */
+    if (device->channel == 0x03)
+    {
+        if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
+        {
+            LOG_E("%s channel3 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+    /* config pwm channel */
+    if (device->channel == 0x07)
+    {
+        if (cyhal_pwm_init_adv(device->pwm_obj, device->gpio, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, false, RT_NULL) != RT_EOK)
+        {
+            LOG_E("%s channel7 config failed", device->name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+    }
+__exit:
+    return result;
+}
+
+static int rt_hw_pwm_init(void)
+{
+    int i;
+    int result = RT_EOK;
+
+    for (i = 0; i < sizeof(ifx_pwm_obj) / sizeof(ifx_pwm_obj[0]); i++)
+    {
+        ifx_pwm_obj[i].pwm_obj = rt_malloc(sizeof(cyhal_pwm_t));
+        RT_ASSERT(ifx_pwm_obj[i].pwm_obj != RT_NULL);
+
+        /* pwm init */
+        if (ifx_hw_pwm_init(&ifx_pwm_obj[i]) != RT_EOK)
+        {
+            LOG_E("%s init failed", ifx_pwm_obj[i].name);
+            result = -RT_ERROR;
+            goto __exit;
+        }
+        else
+        {
+            if (rt_device_pwm_register(&ifx_pwm_obj[i].pwm_device, ifx_pwm_obj[i].name, &drv_ops, ifx_pwm_obj[i].pwm_obj) == RT_EOK)
+            {
+                LOG_D("%s register success", ifx_pwm_obj[i].name);
+            }
+            else
+            {
+                LOG_D("%s register failed", ifx_pwm_obj[i].name);
+                result = -RT_ERROR;
+            }
+        }
+    }
+
+__exit:
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
+
+#define PWM_DEV_NAME "pwm0"
+#define PWM_DEV_CHANNEL 7
+
+struct rt_device_pwm *pwm_dev;
+
+static int pwm_sample(int argc, char *argv[])
+{
+    rt_uint32_t period, pulse, dir;
+
+    period = 1 * 1000 * 1000;
+    dir = 1;
+    pulse = 0;
+
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+
+    rt_kprintf("Now PWM[%s] Channel[%d] Period[%d] Pulse[%d]\n", PWM_DEV_NAME, PWM_DEV_CHANNEL, period, pulse);
+
+    while (1)
+    {
+        rt_thread_mdelay(50);
+
+        if (dir)
+        {
+            pulse += 100000;
+        }
+        else
+        {
+            pulse -= 100000;
+        }
+
+        if (pulse >= period)
+        {
+            dir = 0;
+        }
+
+        if (0 == pulse)
+        {
+            dir = 1;
+        }
+
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    }
+}
+MSH_CMD_EXPORT(pwm_sample, <pwm0> channel7 sample);
+#endif

project_0/libraries/HAL_Drivers/drv_pwm.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-13     Rbb666       first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <board.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define MAX_PERIOD 65535
+
+#ifdef BSP_USING_PWM0
+#ifndef PWM0_CH3_PORT13_CONFIG
+#define PWM0_CH3_PORT13_CONFIG      \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 3,               \
+        .gpio = GET_PIN(13, 7),     \
+    }
+#endif /* PWM0_CH7_PORT2_CONFIG */
+
+#ifndef PWM0_CH7_PORT2_CONFIG
+#define PWM0_CH7_PORT2_CONFIG       \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(2, 2),      \
+    }
+#endif /* PWM0_CH7_PORT2_CONFIG */
+
+#ifndef PWM0_CH7_PORT5_CONFIG
+#define PWM0_CH7_PORT5_CONFIG       \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(5, 6),      \
+    }
+#endif /* PWM0_CH7_PORT5_CONFIG */
+
+#ifndef PWM0_CH7_PORT7_CONFIG
+#define PWM0_CH7_PORT7_CONFIG       \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(7, 7),      \
+    }
+#endif /* PWM0_CH7_PORT7_CONFIG */
+
+#ifndef PWM0_CH7_PORT9_CONFIG
+#define PWM0_CH7_PORT9_CONFIG       \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(9, 4),      \
+    }
+#endif /* PWM0_CH7_PORT9_CONFIG */
+
+#ifndef PWM0_CH7_PORT10_CONFIG
+#define PWM0_CH7_PORT10_CONFIG      \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(10, 2),     \
+    }
+#endif /* PWM0_CH7_PORT10_CONFIG */
+
+#ifndef PWM0_CH7_PORT12_CONFIG
+#define PWM0_CH7_PORT12_CONFIG      \
+    {                               \
+        .name = "pwm0",             \
+        .channel = 7,               \
+        .gpio = GET_PIN(12, 6),     \
+    }
+#endif /* PWM0_CH7_PORT12_CONFIG */
+#endif /* BSP_USING_PWM0 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/drv_rtc.c

@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date         Author         Notes
+ * 2022-07-25   Rbb666         first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <sys/time.h>
+#include "drv_common.h"
+
+#ifdef BSP_USING_RTC
+
+//#define DRV_DEBUG
+#define LOG_TAG                         "drv.rtc"
+#include <drv_log.h>
+
+cyhal_rtc_t rtc_obj;
+
+static rt_rtc_dev_t ifx32_rtc_dev;
+
+static int get_day_of_week(int day, int month, int year)
+{
+    int ret;
+    int k = 0;
+    int j = 0;
+
+    if (month < CY_RTC_MARCH)
+    {
+        month += CY_RTC_MONTHS_PER_YEAR;
+        year--;
+    }
+
+    k = (year % 100);
+    j = (year / 100);
+    ret = (day + (13 * (month + 1) / 5) + k + (k / 4) + (j / 4) + (5 * j)) % 7;
+    ret = ((ret + 6) % 7);
+
+    return ret;
+}
+
+static rt_err_t set_rtc_time_stamp(time_t time_stamp)
+{
+    struct tm tm = {0};
+    struct tm new_time = {0};
+
+    gmtime_r(&time_stamp, &tm);
+
+    if (tm.tm_year < 100)
+    {
+        return -RT_ERROR;
+    }
+
+    new_time.tm_sec     = tm.tm_sec ;
+    new_time.tm_min     = tm.tm_min ;
+    new_time.tm_hour    = tm.tm_hour;
+    new_time.tm_mday    = tm.tm_mday;
+    new_time.tm_mon     = tm.tm_mon;
+    new_time.tm_year    = tm.tm_year;
+    new_time.tm_wday    = get_day_of_week(tm.tm_mday, tm.tm_mon, tm.tm_year);
+
+    if (cyhal_rtc_write(&rtc_obj, &new_time) != RT_EOK)
+    {
+        return -RT_ERROR;
+    }
+
+    LOG_D("set rtc time.");
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_rtc_get_timeval(struct timeval *tv)
+{
+    struct tm tm_new = {0};
+    struct tm date_time = {0};
+
+    cyhal_rtc_read(&rtc_obj, &date_time);
+
+    tm_new.tm_sec  = date_time.tm_sec;
+    tm_new.tm_min  = date_time.tm_min;
+    tm_new.tm_hour = date_time.tm_hour;
+    tm_new.tm_mday = date_time.tm_mday;
+    tm_new.tm_mon  = date_time.tm_mon;
+    tm_new.tm_year = date_time.tm_year;
+
+    tv->tv_sec = timegm(&tm_new);
+
+    return RT_EOK;
+}
+
+static rt_err_t _rtc_init(void)
+{
+    if (cyhal_rtc_init(&rtc_obj) != RT_EOK)
+    {
+        LOG_E("rtc init failed.");
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t _rtc_get_secs(time_t *sec)
+{
+    struct timeval tv;
+
+    ifx_rtc_get_timeval(&tv);
+    *(time_t *) sec = tv.tv_sec;
+    LOG_D("RTC: get rtc_time %d", *sec);
+
+    return RT_EOK;
+}
+
+static rt_err_t _rtc_set_secs(time_t *sec)
+{
+    rt_err_t result = RT_EOK;
+
+    if (set_rtc_time_stamp(*sec))
+    {
+        result = -RT_ERROR;
+    }
+
+    LOG_D("RTC: set rtc_time %d", *sec);
+
+    return result;
+}
+
+static const struct rt_rtc_ops _rtc_ops =
+{
+    _rtc_init,
+    _rtc_get_secs,
+    _rtc_set_secs,
+    RT_NULL,
+    RT_NULL,
+    ifx_rtc_get_timeval,
+    RT_NULL,
+};
+
+/**
+ * @brief    RTC initialization function.
+ *
+ * @return   RT_EOK indicates successful initialization, other value indicates failed;
+ */
+static int rt_hw_rtc_init(void)
+{
+    rt_err_t result = RT_EOK;
+
+    ifx32_rtc_dev.ops = &_rtc_ops;
+
+    if (rt_hw_rtc_register(&ifx32_rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK)
+    {
+        LOG_E("rtc init failed");
+        result = RT_ERROR;
+    }
+    else
+    {
+        LOG_D("rtc init success");
+    }
+
+    return result;
+}
+
+INIT_DEVICE_EXPORT(rt_hw_rtc_init);
+#endif

project_0/libraries/HAL_Drivers/drv_soft_i2c.c

@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Rbb666       first version
+ */
+
+#include <board.h>
+#include "drv_soft_i2c.h"
+
+#ifdef RT_USING_I2C
+
+//#define DRV_DEBUG
+#define LOG_TAG              "drv.i2c"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_I2C1)
+    #error "Please define at least one BSP_USING_I2Cx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+static const struct ifx_soft_i2c_config soft_i2c_config[] =
+{
+    #ifdef BSP_USING_I2C1
+    I2C1_BUS_CONFIG,
+    #endif
+};
+
+static struct ifx_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param ifx i2c dirver class.
+ */
+static void ifx_i2c_gpio_init(struct ifx_i2c *i2c)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)i2c->ops.data;
+
+    rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD);
+    rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD);
+
+    rt_pin_write(cfg->scl, PIN_HIGH);
+    rt_pin_write(cfg->sda, PIN_HIGH);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param ifx config class.
+ * @param The sda pin state.
+ */
+static void ifx_set_sda(void *data, rt_int32_t state)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+
+    if (state)
+    {
+        rt_pin_write(cfg->sda, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->sda, PIN_LOW);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param ifx config class.
+ * @param The scl pin state.
+ */
+static void ifx_set_scl(void *data, rt_int32_t state)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+
+    if (state)
+    {
+        rt_pin_write(cfg->scl, PIN_HIGH);
+    }
+    else
+    {
+        rt_pin_write(cfg->scl, PIN_LOW);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t ifx_get_sda(void *data)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    return rt_pin_read(cfg->sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t ifx_get_scl(void *data)
+{
+    struct ifx_soft_i2c_config *cfg = (struct ifx_soft_i2c_config *)data;
+    return rt_pin_read(cfg->scl);
+}
+
+static const struct rt_i2c_bit_ops ifx_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = ifx_set_sda,
+    .set_scl  = ifx_set_scl,
+    .get_sda  = ifx_get_sda,
+    .get_scl  = ifx_get_scl,
+    .udelay   = rt_hw_us_delay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param ifx config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t ifx_i2c_bus_unlock(const struct ifx_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            rt_hw_us_delay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            rt_hw_us_delay(100);
+        }
+    }
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_hw_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ifx_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = ifx_bit_ops_default;
+        i2c_obj[i].ops.data = (void *)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        ifx_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        ifx_i2c_bus_unlock(&soft_i2c_config[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+              soft_i2c_config[i].bus_name,
+              soft_i2c_config[i].scl,
+              soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+
+#endif /* RT_USING_I2C */

project_0/libraries/HAL_Drivers/drv_soft_i2c.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-20     Rbb666       first version
+ */
+
+#ifndef __DRV_I2C__
+#define __DRV_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+/* ifx config class */
+struct ifx_soft_i2c_config
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *bus_name;
+};
+/* ifx i2c dirver class */
+struct ifx_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = BSP_I2C1_SCL_PIN,                         \
+        .sda = BSP_I2C1_SDA_PIN,                         \
+        .bus_name = "i2c1",                              \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif

project_0/libraries/HAL_Drivers/drv_spi.c

@@ -0,0 +1,231 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-18     Rbb666       first version
+ */
+
+#include <drv_spi.h>
+
+#ifdef RT_USING_SPI
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.spi"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ifx_sw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+#ifdef BSP_USING_SPI3
+    static struct rt_spi_bus spi_bus3;
+#endif
+
+static struct ifx_spi spi_bus_obj[] =
+{
+    #ifdef BSP_USING_SPI3
+    {
+        .bus_name = "spi3",
+        .spi_bus = &spi_bus3,
+        .sck_pin = GET_PIN(6, 2),
+        .miso_pin = GET_PIN(6, 1),
+        .mosi_pin = GET_PIN(6, 0),
+    },
+    #endif
+};
+
+/* private rt-thread spi ops function */
+static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message);
+
+static struct rt_spi_ops ifx_spi_ops =
+{
+    .configure = spi_configure,
+    .xfer = spixfer,
+};
+
+static void ifx_spi_init(struct ifx_spi *ifx_spi)
+{
+    int result = RT_EOK;
+
+    result = cyhal_spi_init(ifx_spi->spi_obj, ifx_spi->mosi_pin, ifx_spi->miso_pin, ifx_spi->sck_pin,
+                            NC, NULL, ifx_spi->spi_obj->data_bits, ifx_spi->spi_obj->mode, false);
+
+    RT_ASSERT(result != RT_ERROR);
+
+    rt_kprintf("[%s] Freq:[%d]HZ\n", ifx_spi->bus_name, ifx_spi->freq);
+
+    result = cyhal_spi_set_frequency(ifx_spi->spi_obj, ifx_spi->freq);
+
+    RT_ASSERT(result != CYHAL_SPI_RSLT_CLOCK_ERROR);
+}
+
+static rt_err_t spi_configure(struct rt_spi_device *device,
+                              struct rt_spi_configuration *configuration)
+{
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+
+    /* data_width */
+    if (configuration->data_width <= 8)
+    {
+        spi_device->spi_obj->data_bits = 8;
+    }
+    else if (configuration->data_width <= 16)
+    {
+        spi_device->spi_obj->data_bits = 16;
+    }
+    else
+    {
+        return RT_EIO;
+    }
+
+    uint32_t max_hz;
+    max_hz = configuration->max_hz;
+
+    spi_device->freq = max_hz;
+
+    /* MSB or LSB */
+    switch (configuration->mode & RT_SPI_MODE_3)
+    {
+        case RT_SPI_MODE_0:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_00_MSB;
+            break;
+
+        case RT_SPI_MODE_1:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_01_MSB;
+            break;
+
+        case RT_SPI_MODE_2:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_10_MSB;
+            break;
+
+        case RT_SPI_MODE_3:
+            spi_device->spi_obj->mode = CYHAL_SPI_MODE_11_MSB;
+            break;
+    }
+
+    ifx_spi_init(spi_device);
+
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != NULL);
+    RT_ASSERT(message != NULL);
+
+    struct rt_spi_bus *spi_bus = (struct rt_spi_bus *)device->bus;
+    struct ifx_spi *spi_device = (struct ifx_spi *)spi_bus->parent.user_data;
+
+    struct rt_spi_configuration *config = &device->config;
+    struct ifx_sw_spi_cs *cs = device->parent.user_data;
+
+    /* take CS */
+    if (message->cs_take)
+    {
+        cyhal_gpio_write(cs->pin, PIN_LOW);
+        LOG_D("spi take cs\n");
+    }
+
+    int result = RT_EOK;
+
+    if (message->length > 0)
+    {
+        if (message->send_buf == RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< receive message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, RT_NULL, 0x00, message->recv_buf, message->length, 0x00);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf == RT_NULL)
+        {
+            /**< send message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, RT_NULL, 0x00, 0x00);
+        }
+        else if (message->send_buf != RT_NULL && message->recv_buf != RT_NULL)
+        {
+            /**< send and receive message */
+            result = cyhal_spi_transfer(spi_device->spi_obj, message->send_buf, message->length, message->recv_buf, message->length, 0x00);
+        }
+    }
+
+    if (message->cs_release && !(device->config.mode & RT_SPI_NO_CS))
+    {
+        if (device->config.mode & RT_SPI_CS_HIGH)
+            cyhal_gpio_write(cs->pin, PIN_LOW);
+        else
+            cyhal_gpio_write(cs->pin, PIN_HIGH);
+    }
+
+    return message->length;
+}
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin)
+{
+    RT_ASSERT(bus_name != RT_NULL);
+    RT_ASSERT(device_name != RT_NULL);
+
+    rt_err_t result;
+    struct rt_spi_device *spi_device;
+
+    /* attach the device to spi bus */
+    spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct ifx_sw_spi_cs *cs_pin = (struct ifx_sw_spi_cs *)rt_malloc(sizeof(struct ifx_sw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+
+    cs_pin->pin = cs_gpio_pin;
+
+    if (cs_pin->pin != 0x00)
+    {
+        /* initialize the cs pin & select the slave*/
+        cyhal_gpio_init(cs_pin->pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, 1);
+        cyhal_gpio_write(cs_pin->pin, PIN_HIGH);
+    }
+
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+
+    RT_ASSERT(spi_device != RT_NULL);
+
+    return result;
+}
+
+int rt_hw_spi_init(void)
+{
+    int result = RT_EOK;
+
+    for (int i = 0; i < sizeof(spi_bus_obj) / sizeof(spi_bus_obj[0]); i++)
+    {
+        spi_bus_obj[i].spi_obj = rt_malloc(sizeof(cyhal_spi_t));
+
+        RT_ASSERT(spi_bus_obj[i].spi_obj != RT_NULL);
+
+        spi_bus_obj[i].spi_bus->parent.user_data = (void *)&spi_bus_obj[i];
+
+        result = rt_spi_bus_register(spi_bus_obj[i].spi_bus, spi_bus_obj[i].bus_name, &ifx_spi_ops);
+
+        RT_ASSERT(result == RT_EOK);
+
+        LOG_D("%s bus init done", spi_bus_obj[i].bus_name);
+
+        LOG_D("MOSI PIN:[%d], MISO PIN[%d], CLK PIN[%d]\n",
+              spi_bus_obj[i].mosi_pin, spi_bus_obj[i].miso_pin,
+              spi_bus_obj[i].sck_pin);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+#endif /* RT_USING_SPI */

project_0/libraries/HAL_Drivers/drv_spi.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-18     Rbb666       first version
+ */
+
+#ifndef __DRV_SPI__
+#define __DRV_SPI__
+
+#include <rtthread.h>
+#include <drivers/spi.h>
+
+#include "drv_gpio.h"
+
+#define SPI_FREQ_HZ         (10000000UL)
+
+/* gd32 spi dirver class */
+struct ifx_spi
+{
+    char *bus_name;
+    struct rt_spi_bus *spi_bus;
+    cyhal_spi_t *spi_obj;
+
+    uint16_t sck_pin;
+    uint16_t miso_pin;
+    uint16_t mosi_pin;
+    uint32_t freq;
+};
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, uint16_t cs_gpio_pin);
+
+#endif

project_0/libraries/HAL_Drivers/drv_uart.c

@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "drv_uart.h"
+
+#include "uart_config.h"
+#include "cyhal_scb_common.h"
+
+enum
+{
+#ifdef BSP_USING_UART0
+    UART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+#ifdef BSP_USING_UART5
+    UART5_INDEX,
+#endif
+};
+
+static struct ifx_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    UART0_CONFIG,
+#endif
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+#ifdef BSP_USING_UART5
+    UART5_CONFIG,
+#endif
+};
+
+static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+    RT_ASSERT(serial != RT_NULL);
+    struct ifx_uart *uart = (struct ifx_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    if ((uart->config->usart_x->INTR_RX_MASKED & SCB_INTR_RX_MASKED_NOT_EMPTY_Msk) != 0)
+    {
+        /* Clear UART "RX fifo not empty interrupt" */
+        uart->config->usart_x->INTR_RX = uart->config->usart_x->INTR_RX & SCB_INTR_RX_NOT_EMPTY_Msk;
+
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+}
+
+#ifdef BSP_USING_UART0
+/* UART0 Interrupt Hanlder */
+void uart0_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART0_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_UART1
+/* UART1 Interrupt Hanlder */
+void uart1_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART1_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_UART2
+/* UART2 Interrupt Hanlder */
+void uart2_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART2_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_UART3
+/* UART3 Interrupt Hanlder */
+void uart3_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART3_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_UART4
+/* UART4 Interrupt Hanlder */
+void uart4_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART4_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+#ifdef BSP_USING_UART5
+/* UART5 Interrupt Hanlder */
+void uart5_isr_callback(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART5_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+/*
+ * UARTHS interface
+ */
+static rt_err_t ifx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    RT_ASSERT(serial != RT_NULL);
+    struct ifx_uart *uart = (struct ifx_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    cy_en_scb_uart_status_t result;
+
+    const cyhal_uart_cfg_t uart_config =
+    {
+        .data_bits          = 8,
+        .stop_bits          = 1,
+        .parity             = CYHAL_UART_PARITY_NONE,
+        .rx_buffer          = NULL,
+        .rx_buffer_size     = 0
+    };
+
+    /* Initialize retarget-io to use the debug UART port */
+    result = cyhal_uart_init(uart->config->uart_obj, uart->config->tx_pin, uart->config->rx_pin, NC, NC, NULL, &uart_config);
+
+    if (result == CY_RSLT_SUCCESS)
+    {
+        result = cyhal_uart_set_baud(uart->config->uart_obj, cfg->baud_rate, NULL);
+    }
+
+    RT_ASSERT(result != RT_ERROR);
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    RT_ASSERT(serial != RT_NULL);
+    struct ifx_uart *uart = (struct ifx_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Unmasking only the RX fifo not empty interrupt bit */
+        uart->config->usart_x->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+
+        /* Interrupt Settings for UART */
+        Cy_SysInt_Init(uart->config->UART_SCB_IRQ_cfg, uart->config->userIsr);
+
+        /* Enable the interrupt */
+        NVIC_EnableIRQ(uart->config->intrSrc);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int ifx_uarths_putc(struct rt_serial_device *serial, char c)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    struct ifx_uart *uart = (struct ifx_uart *) serial->parent.user_data;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    if (_cyhal_scb_pm_transition_pending())
+        return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
+
+    uint32_t count = 0;
+
+    while (count == 0)
+    {
+        count = Cy_SCB_UART_Put(uart->config->usart_x, c);
+    }
+
+    return (1);
+}
+
+static int ifx_uarths_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    rt_uint8_t read_data;
+
+    RT_ASSERT(serial != RT_NULL);
+    struct ifx_uart *uart = (struct ifx_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    ch = -1;
+
+    if (RT_EOK == cyhal_uart_getc(uart->config->uart_obj, (uint8_t *)&read_data, 10))
+    {
+        ch = read_data & 0xff;
+    }
+    else
+    {
+        ch = -1;
+    }
+
+    return ch;
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    ifx_configure,
+    ifx_control,
+    ifx_uarths_putc,
+    ifx_uarths_getc,
+    RT_NULL
+};
+
+void rt_hw_uart_init(void)
+{
+    int index;
+
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ifx_uart);
+    struct serial_configure serial_config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++)
+    {
+        uart_obj[index].config = &uart_config[index];
+        uart_obj[index].serial.ops = &_uart_ops;
+        uart_obj[index].serial.config = serial_config;
+
+        uart_obj[index].config->uart_obj = rt_malloc(sizeof(cyhal_uart_t));
+        RT_ASSERT(uart_obj[index].config->uart_obj != RT_NULL);
+        /* register uart device */
+        result = rt_hw_serial_register(&uart_obj[index].serial,
+                                       uart_obj[index].config->name,
+                                       RT_DEVICE_FLAG_RDWR |
+                                       RT_DEVICE_FLAG_INT_RX,
+                                       &uart_obj[index]);
+
+        RT_ASSERT(result == RT_EOK);
+    }
+}

project_0/libraries/HAL_Drivers/drv_uart.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-06-29     Rbb666       first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include "board.h"
+
+#define  uart_isr_callback(name) name##_isr_callback
+
+struct ifx_uart_config
+{
+    cyhal_uart_t *uart_obj;
+
+    const char *name;
+    rt_uint32_t tx_pin;
+    rt_uint32_t rx_pin;
+    CySCB_Type *usart_x;
+    IRQn_Type intrSrc;
+    cy_israddress userIsr;
+    cy_stc_sysint_t *UART_SCB_IRQ_cfg;
+};
+
+struct ifx_uart
+{
+    struct ifx_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+void rt_hw_uart_init(void);
+
+#endif

project_0/libraries/HAL_Drivers/drv_wdt.c

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2022-07-21     Rbb666            first version
+ */
+
+#include "drv_wdt.h"
+
+#ifdef RT_USING_WDT
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.wdt"
+#include <drv_log.h>
+
+cyhal_wdt_t WDT;
+
+static struct ifx_wdt_cfg wdt_cfg =
+{
+    .name = "wdt",
+    .WDTx = &WDT,
+};
+
+static struct ifx_wdt wdt_drv;
+
+static rt_err_t wdt_init(rt_watchdog_t *wdt)
+{
+    return RT_EOK;
+}
+
+static rt_err_t wdt_control(rt_watchdog_t *wdt_device, int cmd, void *arg)
+{
+    RT_ASSERT(wdt_device != RT_NULL);
+
+    struct ifx_wdt_cfg *cfg;
+    cfg = wdt_device->parent.user_data;
+
+    rt_uint32_t timeout_ms = 0;
+
+    switch (cmd)
+    {
+        /* feed the watchdog */
+        case RT_DEVICE_CTRL_WDT_KEEPALIVE:
+            cyhal_wdt_kick(cfg->WDTx);
+            break;
+
+        /* set watchdog timeout */
+        case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
+        {
+            timeout_ms = *((rt_uint32_t *)arg) * 1000;
+
+            rt_uint32_t max_timeout_ms = cyhal_wdt_get_max_timeout_ms();
+
+            if (timeout_ms >= max_timeout_ms)
+                timeout_ms = max_timeout_ms;
+
+            /* Initialize the WDT */
+            int result = cyhal_wdt_init(cfg->WDTx, (rt_uint32_t)timeout_ms);
+            /* WDT initialization failed. Stop program execution */
+            RT_ASSERT(result != RT_ERROR);
+        }
+        break;
+
+        case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
+            timeout_ms = cyhal_wdt_get_timeout_ms(cfg->WDTx);
+            *(rt_uint32_t *)arg = timeout_ms / 1000;
+            break;
+
+        case RT_DEVICE_CTRL_WDT_START:
+            cyhal_wdt_start(cfg->WDTx);
+            break;
+
+        case RT_DEVICE_CTRL_WDT_STOP:
+            cyhal_wdt_stop(cfg->WDTx);
+            break;
+
+        default:
+            LOG_W("This command is not supported.");
+            return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_watchdog_ops ifx_wdt_ops =
+{
+    wdt_init,
+    wdt_control
+};
+
+int rt_hw_wdt_init(void)
+{
+    wdt_drv.cfg = &wdt_cfg;
+    wdt_drv.wdt_device.ops = &ifx_wdt_ops;
+
+    if (rt_hw_watchdog_register(&wdt_drv.wdt_device, wdt_drv.cfg->name, RT_DEVICE_FLAG_RDWR, wdt_drv.cfg) != RT_EOK)
+    {
+        LOG_E("wdt device register failed.");
+        return -RT_ERROR;
+    }
+
+    LOG_D("wdt device register success.");
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_hw_wdt_init);
+
+#endif /* RT_USING_WDT */

project_0/libraries/HAL_Drivers/drv_wdt.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2022, Synwit Technology Co.,Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-7-21      Rbb666       first version
+ */
+
+#ifndef __DRV_WDT_H__
+#define __DRV_WDT_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+struct ifx_wdt_cfg
+{
+    const char *name;
+    cyhal_wdt_t *WDTx;
+};
+
+struct ifx_wdt
+{
+    struct ifx_wdt_cfg *cfg;
+    struct rt_watchdog_device wdt_device;
+};
+
+int rt_hw_wdt_init(void);
+
+#endif /* __DRV_WDT_H__ */

project_0/libraries/HAL_Drivers/uart_config.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-07-08     Rbb666       first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#ifdef BSP_USING_UART0
+/* UART0 device driver structure */
+cy_stc_sysint_t UART0_SCB_IRQ_cfg =
+{
+    .intrSrc = (IRQn_Type) scb_0_interrupt_IRQn,
+    .intrPriority = (7u),
+};
+#endif
+#ifdef BSP_USING_UART1
+    /* UART1 device driver structure */
+    cy_stc_sysint_t UART1_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_1_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
+#endif
+#ifdef BSP_USING_UART2
+    /* UART2 device driver structure */
+    cy_stc_sysint_t UART2_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_2_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
+#endif
+#ifdef BSP_USING_UART3
+    /* UART3 device driver structure */
+    cy_stc_sysint_t UART3_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_3_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
+#endif
+#ifdef BSP_USING_UART4
+    /* UART4 device driver structure */
+    cy_stc_sysint_t UART4_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_4_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
+#endif
+#ifdef BSP_USING_UART5
+    /* UART5 device driver structure */
+    cy_stc_sysint_t UART5_SCB_IRQ_cfg =
+        {
+            .intrSrc = (IRQn_Type)scb_5_interrupt_IRQn,
+            .intrPriority = (7u),
+    };
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                            \
+    {                                           \
+        .name = "uart0",                        \
+        .tx_pin = P0_3,                         \
+        .rx_pin = P0_2,                         \
+        .usart_x = SCB0,                        \
+        .intrSrc = scb_0_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart0),    \
+        .UART_SCB_IRQ_cfg = &UART0_SCB_IRQ_cfg, \
+    }
+    void uart0_isr_callback(void);
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                            \
+    {                                           \
+        .name = "uart1",                        \
+        .tx_pin = P10_1,                        \
+        .rx_pin = P10_0,                        \
+        .usart_x = SCB1,                        \
+        .intrSrc = scb_1_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart1),    \
+        .UART_SCB_IRQ_cfg = &UART1_SCB_IRQ_cfg, \
+    }
+    void uart1_isr_callback(void);
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                            \
+    {                                           \
+        .name = "uart2",                        \
+        .tx_pin = P9_1,                         \
+        .rx_pin = P9_0,                         \
+        .usart_x = SCB2,                        \
+        .intrSrc = scb_2_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart2),    \
+        .UART_SCB_IRQ_cfg = &UART2_SCB_IRQ_cfg, \
+    }
+    void uart2_isr_callback(void);
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                            \
+    {                                           \
+        .name = "uart3",                        \
+        .tx_pin = P6_1,                         \
+        .rx_pin = P6_0,                         \
+        .usart_x = SCB3,                        \
+        .intrSrc = scb_3_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart3),    \
+        .UART_SCB_IRQ_cfg = &UART3_SCB_IRQ_cfg, \
+    }
+    void uart3_isr_callback(void);
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                            \
+    {                                           \
+        .name = "uart4",                        \
+        .tx_pin = P7_1,                         \
+        .rx_pin = P7_0,                         \
+        .usart_x = SCB4,                        \
+        .intrSrc = scb_4_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart4),    \
+        .UART_SCB_IRQ_cfg = &UART4_SCB_IRQ_cfg, \
+    }
+    void uart4_isr_callback(void);
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                            \
+    {                                           \
+        .name = "uart5",                        \
+        .tx_pin = P5_1,                         \
+        .rx_pin = P5_0,                         \
+        .usart_x = SCB5,                        \
+        .intrSrc = scb_5_interrupt_IRQn,        \
+        .userIsr = uart_isr_callback(uart5),    \
+        .UART_SCB_IRQ_cfg = &UART5_SCB_IRQ_cfg, \
+    }
+    void uart5_isr_callback(void);
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/IFX_PSOC6_HAL/SConscript

@@ -0,0 +1,156 @@
+from building import *
+import rtconfig
+Import('RTT_ROOT')
+
+# get current directory
+cwd = GetCurrentDir()
+src = []
+
+# The set of source files associated with this SConscript file.
+src = Split('''
+            mtb-hal-cat1/source/cyhal_clock.c
+            mtb-hal-cat1/source/cyhal_hwmgr.c
+            mtb-hal-cat1/source/cyhal_syspm.c
+            mtb-hal-cat1/source/cyhal_system.c
+            mtb-hal-cat1/source/cyhal_uart.c
+            mtb-hal-cat1/source/cyhal_gpio.c
+            mtb-hal-cat1/source/cyhal_scb_common.c
+            mtb-hal-cat1/source/cyhal_interconnect.c
+            mtb-hal-cat1/source/cyhal_utils_psoc.c
+            mtb-hal-cat1/source/cyhal_utils.c
+            mtb-hal-cat1/source/cyhal_lptimer.c
+            mtb-hal-cat1/source/cyhal_irq_psoc.c   
+            mtb-hal-cat1/COMPONENT_CAT1A/source/triggers/cyhal_triggers_psoc6_02.c
+            mtb-hal-cat1/COMPONENT_CAT1A/source/pin_packages/cyhal_psoc6_02_124_bga.c
+            mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/cy_device.c
+            mtb-pdl-cat1/drivers/source/cy_scb_common.c
+            mtb-pdl-cat1/drivers/source/cy_sysclk.c
+            mtb-pdl-cat1/drivers/source/cy_systick.c
+            mtb-pdl-cat1/drivers/source/cy_gpio.c
+            mtb-pdl-cat1/drivers/source/cy_sysint.c
+            mtb-pdl-cat1/drivers/source/cy_syslib.c
+            mtb-pdl-cat1/drivers/source/cy_scb_i2c.c
+            mtb-pdl-cat1/drivers/source/cy_syspm.c
+            mtb-pdl-cat1/drivers/source/cy_mcwdt.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_pipe.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_sema.c
+            mtb-pdl-cat1/drivers/source/cy_ipc_drv.c
+            mtb-pdl-cat1/drivers/source/cy_trigmux.c
+            mtb-pdl-cat1/drivers/source/cy_prot.c           
+            TARGET_CY8CKIT-062S2-43012/cybsp.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_CM4/system_psoc6_cm4.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c
+            TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c            
+            lib/cy_capsense.lib
+            ''')
+
+src += Glob(cwd + '/psoc6cm0p/COMPONENT_CM0P_SLEEP/*.c')
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['retarget-io/cy_retarget_io.c']
+    src += ['mtb-hal-cat1/source/cyhal_uart.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_scb_uart.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += ['mtb-hal-cat1/source/cyhal_dma_dw.c']
+    src += ['mtb-hal-cat1/source/cyhal_dma_dmac.c']
+    src += ['mtb-hal-cat1/source/cyhal_dma.c']
+    src += ['mtb-hal-cat1/source/cyhal_analog_common.c']
+    src += ['mtb-hal-cat1/source/cyhal_adc_sar.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_sar.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dmac.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_sysanalog.c']
+
+if GetDepend(['RT_USING_SDIO']):
+    src += ['mtb-hal-cat1/source/cyhal_sdhc.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_sd_host.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['mtb-hal-cat1/source/cyhal_qspi.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_smif.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_smif_sfdp.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_smif_memslot.c']
+    src += ['mtb_shared/serial-flash/cy_serial_flash_qspi.c']
+    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['mtb-hal-cat1/source/cyhal_pwm.c']
+    src += ['mtb-hal-cat1/source/cyhal_timer.c']
+    src += ['mtb-hal-cat1/source/cyhal_tcpwm_common.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_tcpwm_pwm.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_tcpwm_counter.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['mtb-hal-cat1/source/cyhal_spi.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_scb_spi.c']
+
+if GetDepend(['RT_USING_I2C']):
+    src += ['mtb-hal-cat1/source/cyhal_i2c.c']
+
+if GetDepend('BSP_USING_USBD'):
+    src += ['mtb_shared/usbdev/cy_usb_dev.c']
+    src += ['mtb_shared/usbdev/cy_usb_dev_hid.c']
+    src += ['mtb-hal-cat1/source/cyhal_usb_dev.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_dma.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_usbfs_dev_drv_io_dma.c']
+    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_usbdev.c']
+
+if GetDepend('BSP_USING_RTC'):
+    src += ['mtb-pdl-cat1/drivers/source/cy_rtc.c']
+    src += ['mtb-hal-cat1/source/cyhal_rtc.c']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    src += ['mtb-pdl-cat1/drivers/source/cy_flash.c']
+    src += ['mtb-hal-cat1/source/cyhal_flash.c']
+
+if GetDepend(['BSP_USING_SLIDER']):
+    src += ['capsense/cy_capsense_control.c']
+    src += ['capsense/cy_capsense_sensing.c']
+    src += ['capsense/cy_capsense_sensing_v2.c']
+    src += ['capsense/cy_capsense_csx_v2.c']
+    src += ['capsense/cy_capsense_csd_v2.c']
+    src += ['capsense/cy_capsense_processing.c']
+    src += ['capsense/cy_capsense_tuner.c']
+    src += ['capsense/cy_capsense_structure.c']
+    src += ['capsense/cy_capsense_centroid.c']
+    src += ['capsense/cy_capsense_filter.c']
+    src += ['mtb-pdl-cat1/drivers/source/cy_csd.c']
+    src += ['TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c']
+
+if GetDepend(['RT_USING_WDT']):
+    src += ['mtb-pdl-cat1/drivers/source/cy_wdt.c']
+    src += ['mtb-hal-cat1/source/cyhal_wdt.c']
+
+if GetDepend(['RT_USING_DAC']):
+    src += ['mtb_shared/csdidac/cy_csdidac.c']	
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['mtb-hal-cat1/source/cyhal_timer.c']    
+
+path = [cwd + '/capsense',
+        cwd + '/psoc6cm0p',
+        cwd + '/retarget-io',
+        cwd + '/core-lib/include',
+        cwd + '/mtb_shared/serial-flash',
+        cwd + '/mtb_shared/usbdev',
+        cwd + '/mtb_shared/csdidac',
+        cwd + '/mtb-pdl-cat1/cmsis/include',
+        cwd + '/mtb-pdl-cat1/drivers/include',
+        cwd + '/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include',
+        cwd + '/mtb-hal-cat1/include_pvt',
+        cwd + '/mtb-hal-cat1/include',
+        cwd + '/mtb-hal-cat1/COMPONENT_CAT1A/include',
+        cwd + '/TARGET_CY8CKIT-062S2-43012',
+        cwd + '/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource']
+
+group = DefineGroup('Libraries', src, depend=[''], CPPPATH=path)
+
+Return('group')

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/.gitignore

@@ -0,0 +1,9 @@
+docs
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2)
+$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/
+$(SEARCH_bluetooth-freertos)/firmware_deprecated/
+
+# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1)
+../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/
+../bluetooth-freertos/firmware_deprecated/

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

@@ -0,0 +1,39 @@
+/*******************************************************************************
+* File Name: cycfg.c
+*
+* Description:
+* Wrapper function to initialize all generated code.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg.h"
+
+void init_cycfg_all(void)
+{
+    init_cycfg_system();
+    init_cycfg_clocks();
+    init_cycfg_routing();
+    init_cycfg_peripherals();
+    init_cycfg_pins();
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

@@ -0,0 +1,53 @@
+/*******************************************************************************
+* File Name: cycfg.h
+*
+* Description:
+* Simple wrapper header containing all generated files.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_H)
+#define CYCFG_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+#include "cycfg_system.h"
+#include "cycfg_connectivity_bt.h"
+#include "cycfg_clocks.h"
+#include "cycfg_routing.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_pins.h"
+
+void init_cycfg_all(void);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

@@ -0,0 +1,29 @@
+/*******************************************************************************
+* File Name: cycfg.timestamp
+*
+* Description:
+* Sentinel file for determining if generated source is up to date.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c

@@ -0,0 +1,877 @@
+/*******************************************************************************
+* File Name: cycfg_capsense.c
+*
+* Description:
+* CAPSENSE Middleware configuration
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.6195
+*
+********************************************************************************
+* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#include "cycfg_capsense.h"
+
+#if !defined(CY_DISABLE_CAPSENSE)
+
+#if (CY_CAPSENSE_CORE == __CORTEX_M)
+
+#ifndef CSD_CMODPADS_PORT
+#define CSD_CMODPADS_PORT 0xFF
+#endif
+#ifndef CSD_CMODPADS_PIN
+#define CSD_CMODPADS_PIN 0xFF
+#endif
+#ifndef CSD_CSH_TANKPADS_PORT
+#define CSD_CSH_TANKPADS_PORT 0xFF
+#endif
+#ifndef CSD_CSH_TANKPADS_PIN
+#define CSD_CSH_TANKPADS_PIN 0xFF
+#endif
+#ifndef CSD_CSHIELDPADS_PORT
+#define CSD_CSHIELDPADS_PORT 0xFF
+#endif
+#ifndef CSD_CSHIELDPADS_PIN
+#define CSD_CSHIELDPADS_PIN 0xFF
+#endif
+#ifndef CSD_VREF_EXT_PORT
+#define CSD_VREF_EXT_PORT 0xFF
+#endif
+#ifndef CSD_VREF_EXT_PIN
+#define CSD_VREF_EXT_PIN 0xFF
+#endif
+
+static cy_stc_capsense_internal_context_t cy_capsense_internalContext;
+static cy_stc_active_scan_sns_t cy_capsense_activeScanSns;
+
+#if (CY_CAPSENSE_DEBOUNCE_SIZE > 0)
+    static uint8_t cy_capsense_debounce[CY_CAPSENSE_DEBOUNCE_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_NOISE_ENVELOPE_SIZE > 0)
+    static cy_stc_capsense_smartsense_csd_noise_envelope_t cy_capsense_noiseEnvelope[CY_CAPSENSE_NOISE_ENVELOPE_SIZE];
+#endif
+
+#if (CY_CAPSENSE_RAW_HISTORY_SIZE > 0)
+    static uint16_t cy_capsense_rawFilterHistory[CY_CAPSENSE_RAW_HISTORY_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_IIR_HISTORY_LOW_SIZE > 0)
+    static uint8_t cy_capsense_iirHistoryLow[CY_CAPSENSE_IIR_HISTORY_LOW_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE > 0)
+    static cy_stc_capsense_position_t cy_capsense_positionFilterHistory[CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE];
+#endif
+
+#if (CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE > 0)
+    static cy_stc_capsense_touch_t cy_capsense_touchFilterHistory[CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_DIPLEX_SIZE > 0)
+    static const uint8_t cy_capsense_diplexTable[CY_CAPSENSE_DIPLEX_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE > 0)
+    static uint16_t cy_capsense_csdTouchBuffer[CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE] = {0};
+#endif
+
+#if (CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE > 0)
+    static cy_stc_capsense_csx_touch_buffer_t cy_capsense_csxTouchBuffer;
+#endif
+
+#if (CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE > 0)
+    static cy_stc_capsense_csx_touch_history_t cy_capsense_csxTouchHistory[CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_BALLISTIC_WIDGET_COUNT > 0)
+    static cy_stc_capsense_ballistic_context_t cy_capsense_ballisticContext[CY_CAPSENSE_BALLISTIC_WIDGET_COUNT];
+#endif
+
+#if (CY_CAPSENSE_GESTURE_WIDGET_COUNT > 0)
+    static cy_stc_capsense_gesture_context_t cy_capsense_gestureContext[CY_CAPSENSE_GESTURE_WIDGET_COUNT];
+#endif
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+    uint16_t cy_capsense_bslnInv[CY_CAPSENSE_SENSOR_COUNT * CY_CAPSENSE_MFS_CH_NUMBER];
+    uint32_t cy_capsense_eltdCap[CY_CAPSENSE_ELTD_COUNT];
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        uint32_t cy_capsense_snsCap[CY_CAPSENSE_SENSOR_COUNT];
+    #endif
+    uint16_t cy_capsense_wdgtCrc[CY_CAPSENSE_WIDGET_COUNT];
+#endif
+#endif
+
+static const cy_stc_capsense_common_config_t cy_capsense_commonConfig =
+{
+    .cpuClkHz = CY_CAPSENSE_CPU_CLK,
+    .periClkHz = CY_CAPSENSE_PERI_CLK,
+    .vdda = CY_CAPSENSE_VDDA_MV,
+    .numPin = CY_CAPSENSE_PIN_COUNT,
+    .numSns = CY_CAPSENSE_SENSOR_COUNT,
+    .numWd = CY_CAPSENSE_WIDGET_COUNT,
+    .csdEn = CY_CAPSENSE_ENABLE,
+    .csxEn = CY_CAPSENSE_ENABLE,
+    #if (CY_CAPSENSE_MW_VERSION < 300)
+        .mfsEn = CY_CAPSENSE_DISABLE,
+    #endif
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+        .bistEn = CY_CAPSENSE_DISABLE,
+    #endif
+    .positionFilterEn = CY_CAPSENSE_DISABLE,
+    .periDividerType = (uint8_t)CY_CAPSENSE_PERI_DIV_TYPE,
+    .periDividerIndex = CY_CAPSENSE_PERI_DIV_INDEX,
+    .analogWakeupDelay = 25u,
+    .ssIrefSource = CY_CAPSENSE_IREF_SRSS,
+    .ssVrefSource = CY_CAPSENSE_VREF_SRSS,
+    .proxTouchCoeff = 300u,
+    .swSensorAutoResetEn = CY_CAPSENSE_DISABLE,
+    .portCmodPadNum = CSD_CMODPADS_PORT,
+    .pinCmodPad = CSD_CMODPADS_PIN,
+    .portCshPadNum = CSD_CSH_TANKPADS_PORT,
+    .pinCshPad = CSD_CSH_TANKPADS_PIN,
+    .portShieldPadNum = CSD_CSHIELDPADS_PORT,
+    .pinShieldPad = CSD_CSHIELDPADS_PIN,
+    .portVrefExtPadNum = CSD_VREF_EXT_PORT,
+    .pinVrefExtPad = CSD_VREF_EXT_PIN,
+    .portCmodNum = Cmod_PORT_NUM,
+    .idacGainTable = {
+        {0x01000000u,   37500u},
+        {0x03000000u,   75000u},
+        {0x01400000u,  300000u},
+        {0x03400000u,  600000u},
+        {0x01800000u, 2400000u},
+        {0x03800000u, 4800000u},
+    },
+    .ptrCsdBase = CSD0,
+    .ptrCsdContext = &cy_csd_0_context,
+    .portCmod = Cmod_PORT,
+    .portCsh = NULL,
+    .portCintA = CintA_PORT,
+    .portCintB = CintB_PORT,
+    .pinCmod = Cmod_PIN,
+    .portCshNum = 0u,
+    .pinCsh = 0u,
+    .pinCintA = CintA_PIN,
+    .pinCintB = CintB_PIN,
+    .csdShieldEn = CY_CAPSENSE_DISABLE,
+    .csdInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        .csxInactiveSnsConnection = CY_CAPSENSE_SNS_CONNECTION_GROUND,
+    #endif
+    .csdShieldDelay = CY_CAPSENSE_SH_DELAY_0NS,
+    .csdVref = 0u,
+    .csdRConst = 1000u,
+    .csdCTankShieldEn = CY_CAPSENSE_DISABLE,
+    .csdShieldNumPin = 0u,
+    .csdShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
+    .csdInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
+    .csdChargeTransfer = CY_CAPSENSE_IDAC_SOURCING,
+    .csdRawTarget = 85u,
+    .csdAutotuneEn = CY_CAPSENSE_CSD_SS_HWTH_EN,
+    .csdIdacAutocalEn = CY_CAPSENSE_ENABLE,
+    .csdIdacAutoGainEn = CY_CAPSENSE_ENABLE,
+    .csdCalibrationError = 10u,
+    .csdIdacGainInitIndex = 4u,
+    .csdIdacMin = 20u,
+    .csdIdacCompEn = CY_CAPSENSE_ENABLE,
+    .csdFineInitTime = 10u,
+    .csdIdacRowColAlignEn = CY_CAPSENSE_ENABLE,
+    .csdMfsDividerOffsetF1 = 1u,
+    .csdMfsDividerOffsetF2 = 2u,
+    .csxRawTarget = 40u,
+    .csxIdacGainInitIndex = 2u,
+    .csxIdacAutocalEn = CY_CAPSENSE_ENABLE,
+    .csxCalibrationError = 20u,
+    .csxFineInitTime = 10u,
+    .csxInitSwRes = CY_CAPSENSE_INIT_SW_RES_MEDIUM,
+    .csxScanSwRes = CY_CAPSENSE_INIT_SW_RES_LOW,
+    .csxInitShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_MEDIUM,
+    .csxScanShieldSwRes = CY_CAPSENSE_SHIELD_SW_RES_LOW,
+    .csxMfsDividerOffsetF1 = 1u,
+    .csxMfsDividerOffsetF2 = 2u,
+};
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+    static const cy_stc_capsense_fptr_config_t cy_capsense_fptrConfig =
+    {
+    #if (CY_CAPSENSE_CSD_EN == 0)
+        .fptrCSDSetupWidget = NULL,
+        .fptrCSDScan = NULL,
+        .fptrDpProcessCsdWidgetRawCounts = NULL,
+        .fptrDpProcessCsdWidgetStatus = NULL,
+        .fptrCSDDisableMode = NULL,
+        .fptrCSDInitialize = NULL,
+        .fptrCSDScanISR = NULL,
+    #else
+        .fptrCSDSetupWidget = &Cy_CapSense_CSDSetupWidget,
+        .fptrCSDScan = &Cy_CapSense_CSDScan,
+        .fptrDpProcessCsdWidgetRawCounts = &Cy_CapSense_DpProcessCsdWidgetRawCounts,
+        .fptrDpProcessCsdWidgetStatus = &Cy_CapSense_DpProcessCsdWidgetStatus,
+        .fptrCSDDisableMode = &Cy_CapSense_CSDDisableMode,
+        .fptrCSDInitialize = &Cy_CapSense_CSDInitialize,
+        .fptrCSDScanISR = &Cy_CapSense_CSDScanISR,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_EN == 0)
+        .fptrCSXSetupWidget = NULL,
+        .fptrCSXScan = NULL,
+        .fptrDpProcessCsxWidgetRawCounts = NULL,
+        .fptrDpProcessCsxWidgetStatus = NULL,
+        .fptrCSXInitialize = NULL,
+        .fptrCSXDisableMode = NULL,
+        .fptrCSXScanISR = NULL,
+    #else
+        .fptrCSXSetupWidget = &Cy_CapSense_CSXSetupWidget,
+        .fptrCSXScan = &Cy_CapSense_CSXScan,
+        .fptrDpProcessCsxWidgetRawCounts = &Cy_CapSense_DpProcessCsxWidgetRawCounts,
+        .fptrDpProcessCsxWidgetStatus = &Cy_CapSense_DpProcessCsxWidgetStatus,
+        .fptrCSXInitialize = &Cy_CapSense_CSXInitialize,
+        .fptrCSXDisableMode = &Cy_CapSense_CSXDisableMode,
+        .fptrCSXScanISR = &Cy_CapSense_CSXScanISR,
+    #endif
+
+    #if (CY_CAPSENSE_ADAPTIVE_FILTER_EN == 0)
+        .fptrAdaptiveFilterInitializeLib = NULL,
+        .fptrAdaptiveFilterRunLib = NULL,
+    #else
+        .fptrAdaptiveFilterInitializeLib = &Cy_CapSense_AdaptiveFilterInitialize_Lib,
+        .fptrAdaptiveFilterRunLib = &Cy_CapSense_AdaptiveFilterRun_Lib,
+    #endif
+
+    #if (CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN == 0)
+        .fptrBallisticMultiplierLib = NULL,
+    #else
+        .fptrBallisticMultiplierLib = &Cy_CapSense_BallisticMultiplier_Lib,
+    #endif
+
+    #if (CY_CAPSENSE_RAWCOUNT_FILTER_EN == 0)
+        .fptrInitializeAllFilters = NULL,
+        .fptrFtRunEnabledFiltersInternal = NULL,
+    #else
+        .fptrInitializeAllFilters = &Cy_CapSense_InitializeAllFilters,
+        .fptrFtRunEnabledFiltersInternal = &Cy_CapSense_FtRunEnabledFiltersInternal,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0)
+        .fptrProcessPositionFilters = NULL,
+    #else
+        .fptrProcessPositionFilters = &Cy_CapSense_ProcessPositionFilters,
+    #endif
+
+    #if ((CY_CAPSENSE_CSX_POSITION_FILTER_EN == 0) && (CY_CAPSENSE_CSD_POSITION_FILTER_EN == 0))
+        .fptrRunPositionFilters = NULL,
+        .fptrInitPositionFilters = NULL,
+    #else
+        .fptrRunPositionFilters = &Cy_CapSense_RunPositionFilters,
+        .fptrInitPositionFilters = &Cy_CapSense_InitPositionFilters,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_BUTTON_EN == 0) && \
+         (CY_CAPSENSE_CSX_BUTTON_EN == 0) && (CY_CAPSENSE_CSX_MATRIX_EN == 0))
+        .fptrDpProcessButton = NULL,
+    #else
+        .fptrDpProcessButton = &Cy_CapSense_DpProcessButton,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_SLIDER_EN == 0) && \
+         (CY_CAPSENSE_CSX_SLIDER_EN == 0))
+        .fptrDpProcessSlider = NULL,
+    #else
+        .fptrDpProcessSlider = &Cy_CapSense_DpProcessSlider,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_MATRIX_EN == 0)
+        .fptrDpProcessCsdMatrix = NULL,
+    #else
+        .fptrDpProcessCsdMatrix = &Cy_CapSense_DpProcessCsdMatrix,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_TOUCHPAD_EN == 0)
+        .fptrDpProcessCsdTouchpad = NULL,
+    #else
+        .fptrDpProcessCsdTouchpad = &Cy_CapSense_DpProcessCsdTouchpad,
+    #endif
+
+    #if (CY_CAPSENSE_CSD_PROXIMITY_EN == 0)
+        .fptrDpProcessProximity = NULL,
+    #else
+        .fptrDpProcessProximity = &Cy_CapSense_DpProcessProximity,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_TOUCHPAD_EN == 0)
+        .fptrDpProcessCsxTouchpad = NULL,
+    #else
+        .fptrDpProcessCsxTouchpad = &Cy_CapSense_DpProcessCsxTouchpad,
+    #endif
+
+    #if (CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN == 0)
+        .fptrDpAdvancedCentroidTouchpad = NULL,
+    #else
+        .fptrDpAdvancedCentroidTouchpad = &Cy_CapSense_DpAdvancedCentroidTouchpad,
+    #endif
+
+    #if ((CY_CAPSENSE_CSD_CALIBRATION_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0))
+        .fptrCSDCalibrateWidget = NULL,
+        .fptrCalibrateAllCsdWidgets = NULL,
+    #else
+        .fptrCSDCalibrateWidget = &Cy_CapSense_CSDCalibrateWidget,
+        .fptrCalibrateAllCsdWidgets = &Cy_CapSense_CalibrateAllCsdWidgets,
+    #endif
+
+    #if (CY_CAPSENSE_CSX_CALIBRATION_EN == 0)
+        .fptrCalibrateAllCsxWidgets = NULL,
+    #else
+        .fptrCalibrateAllCsxWidgets = &Cy_CapSense_CalibrateAllCsxWidgets,
+    #endif
+
+    #if (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0)
+        .fptrRunNoiseEnvelopeLib = NULL,
+        .fptrDpUpdateThresholds = NULL,
+        .fptrInitializeNoiseEnvelopeLib = NULL,
+    #else
+        .fptrRunNoiseEnvelopeLib = &Cy_CapSense_RunNoiseEnvelope_Lib,
+        .fptrDpUpdateThresholds = &Cy_CapSense_DpUpdateThresholds,
+        .fptrInitializeNoiseEnvelopeLib = &Cy_CapSense_InitializeNoiseEnvelope_Lib,
+    #endif
+
+    #if ((CY_CAPSENSE_SMARTSENSE_HW_EN == 0) && (CY_CAPSENSE_SMARTSENSE_FULL_EN == 0))
+        .fptrSsAutoTune = NULL,
+    #else
+        .fptrSsAutoTune = &Cy_CapSense_SsAutoTune,
+    #endif
+
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+    #if (CY_CAPSENSE_BIST_EN == 0)
+        .fptrBistInitialize = NULL,
+        .fptrBistDisableMode = NULL,
+        .fptrBistDsInitialize = NULL,
+    #else
+        .fptrBistInitialize = &Cy_CapSense_BistInitialize,
+        .fptrBistDisableMode = &Cy_CapSense_BistDisableMode,
+        .fptrBistDsInitialize = &Cy_CapSense_BistDsInitialize,
+    #endif
+    #endif
+    };
+#endif
+
+static const cy_stc_capsense_pin_config_t cy_capsense_pinConfig[CY_CAPSENSE_PIN_COUNT] =
+{
+    { /* Button0_Rx0 */
+        Button0_Rx0_PORT,
+        Button0_Rx0_PIN,
+    },
+    { /* Button0_Tx */
+        Button0_Tx_PORT,
+        Button0_Tx_PIN,
+    },
+    { /* Button1_Rx0 */
+        Button1_Rx0_PORT,
+        Button1_Rx0_PIN,
+    },
+    { /* Button1_Tx */
+        Button1_Tx_PORT,
+        Button1_Tx_PIN,
+    },
+    { /* LinearSlider0_Sns0 */
+        LinearSlider0_Sns0_PORT,
+        LinearSlider0_Sns0_PIN,
+    },
+    { /* LinearSlider0_Sns1 */
+        LinearSlider0_Sns1_PORT,
+        LinearSlider0_Sns1_PIN,
+    },
+    { /* LinearSlider0_Sns2 */
+        LinearSlider0_Sns2_PORT,
+        LinearSlider0_Sns2_PIN,
+    },
+    { /* LinearSlider0_Sns3 */
+        LinearSlider0_Sns3_PORT,
+        LinearSlider0_Sns3_PIN,
+    },
+    { /* LinearSlider0_Sns4 */
+        LinearSlider0_Sns4_PORT,
+        LinearSlider0_Sns4_PIN,
+    },
+};
+
+#if (CY_CAPSENSE_SHIELD_PIN_COUNT > 0)
+    static const cy_stc_capsense_pin_config_t cy_capsense_shieldPinConfig[CY_CAPSENSE_SHIELD_PIN_COUNT] =
+    {
+    };
+#endif
+
+#if (CY_CAPSENSE_ELTD_COUNT > 0)
+    static const cy_stc_capsense_electrode_config_t cy_capsense_electrodeConfig[CY_CAPSENSE_ELTD_COUNT] =
+    {
+        { /* Button0_Rx0 */
+            .ptrPin = &cy_capsense_pinConfig[0u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
+            .numPins = 1u,
+        },
+        { /* Button0_Tx */
+            .ptrPin = &cy_capsense_pinConfig[1u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
+            .numPins = 1u,
+        },
+        { /* Button1_Rx0 */
+            .ptrPin = &cy_capsense_pinConfig[2u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_RX_E,
+            .numPins = 1u,
+        },
+        { /* Button1_Tx */
+            .ptrPin = &cy_capsense_pinConfig[3u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_MUT_TX_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns0 */
+            .ptrPin = &cy_capsense_pinConfig[4u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns1 */
+            .ptrPin = &cy_capsense_pinConfig[5u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns2 */
+            .ptrPin = &cy_capsense_pinConfig[6u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns3 */
+            .ptrPin = &cy_capsense_pinConfig[7u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+        { /* LinearSlider0_Sns4 */
+            .ptrPin = &cy_capsense_pinConfig[8u],
+            .type = (uint8_t)CY_CAPSENSE_ELTD_TYPE_SELF_E,
+            .numPins = 1u,
+        },
+    };
+#endif
+
+static const cy_stc_capsense_widget_config_t cy_capsense_widgetConfig[CY_CAPSENSE_WIDGET_COUNT] =
+{
+    { /* Button0 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[0u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[0u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = NULL,
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[0u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 0u,
+        .xResolution = 0u,
+        .yResolution = 0u,
+        .numSns = 1u,
+        .numCols = 1u,
+        .numRows = 1u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSX_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
+        #endif
+        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
+    },
+    { /* Button1 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[1u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[1u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[2u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = NULL,
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[1u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 0u,
+        .xResolution = 0u,
+        .yResolution = 0u,
+        .numSns = 1u,
+        .numCols = 1u,
+        .numRows = 1u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSX_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSX_E,
+        #endif
+        .wdType = (uint8_t)CY_CAPSENSE_WD_BUTTON_E,
+    },
+    { /* LinearSlider0 */
+        .ptrWdContext = &cy_capsense_tuner.widgetContext[2u],
+        .ptrSnsContext = &cy_capsense_tuner.sensorContext[2u],
+        .ptrEltdConfig = &cy_capsense_electrodeConfig[4u],
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrEltdCapacitance = NULL,
+        .ptrBslnInv = NULL,
+#endif
+        .ptrNoiseEnvelope = &cy_capsense_noiseEnvelope[0u],
+        .ptrRawFilterHistory = NULL,
+        .ptrRawFilterHistoryLow = NULL,
+        .iirCoeff = 128u,
+        .ptrDebounceArr = &cy_capsense_debounce[2u],
+        .ptrDiplexTable = NULL,
+        .centroidConfig = 1u,
+        .xResolution = 300u,
+        .yResolution = 0u,
+        .numSns = 5u,
+        .numCols = 5u,
+        .numRows = 0u,
+        .ptrPosFilterHistory = NULL,
+        .ptrCsxTouchHistory = NULL,
+        .ptrCsxTouchBuffer = NULL,
+        .ptrCsdTouchBuffer = NULL,
+        .ptrGestureConfig = NULL,
+        .ptrGestureContext = NULL,
+        .ballisticConfig = {
+            .accelCoeff = 9u,
+            .speedCoeff = 2u,
+            .divisorValue = 4u,
+            .speedThresholdX = 3u,
+            .speedThresholdY = 4u,
+        },
+        .ptrBallisticContext = NULL,
+        .aiirConfig = {
+            .maxK = 60u,
+            .minK = 1u,
+            .noMovTh = 3u,
+            .littleMovTh = 7u,
+            .largeMovTh = 12u,
+            .divVal = 64u,
+        },
+        .advConfig = {
+            .penultimateTh = 100u,
+            .virtualSnsTh = 100u,
+            .crossCouplingTh = 5u,
+        },
+        .posFilterConfig = 0u,
+        .rawFilterConfig = 0u,
+        #if (CY_CAPSENSE_MW_VERSION >= 300)
+            .senseMethod = CY_CAPSENSE_CSD_GROUP,
+        #else
+            .senseMethod = CY_CAPSENSE_SENSE_METHOD_CSD_E,
+        #endif
+        .wdType = (uint8_t)CY_CAPSENSE_WD_LINEAR_SLIDER_E,
+    },
+};
+
+cy_stc_capsense_tuner_t cy_capsense_tuner =
+{
+    .commonContext = {
+        #if (CY_CAPSENSE_MW_VERSION < 300)
+            .configId = 0x0990,
+        #else
+            .configId = 0x0991,
+        #endif
+
+        .tunerCmd = 0u,
+        .scanCounter = 0u,
+        .tunerSt = 0u,
+        .initDone = 0u,
+        #if (CY_CAPSENSE_MW_VERSION < 300)
+            .ptrSSCallback = NULL,
+            .ptrEOSCallback = NULL,
+            .ptrTunerSendCallback = NULL,
+            .ptrTunerReceiveCallback = NULL,
+        #endif
+        .status = 0u,
+        .timestampInterval = 1u,
+        .timestamp = 0u,
+        .modCsdClk = 2u,
+        .modCsxClk = 2u,
+        .tunerCnt = 0u,
+    },
+    .widgetContext = {
+        { /* Button0 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 100u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 32u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0,
+            .yDelta = 0,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 2u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = NULL,
+                .numPosition = 0,
+            },
+        },
+        { /* Button1 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 100u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 32u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0,
+            .yDelta = 0,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 2u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = NULL,
+                .numPosition = 0,
+            },
+        },
+        { /* LinearSlider0 */
+            .fingerCap = 160u,
+            .sigPFC = 0u,
+            .resolution = 12u,
+            .maxRawCount = 0u,
+            #if (CY_CAPSENSE_MW_VERSION >= 300)
+                .maxRawCountRow = 0u,
+            #endif
+            .fingerTh = 100u,
+            .proxTh = 200u,
+            .lowBslnRst = 30u,
+            .snsClk = 16u,
+            .rowSnsClk = 16u,
+            .gestureDetected = 0u,
+            .gestureDirection = 0u,
+            .xDelta = 0,
+            .yDelta = 0,
+            .noiseTh = 40u,
+            .nNoiseTh = 40u,
+            .hysteresis = 10u,
+            .onDebounce = 3u,
+            .snsClkSource = CY_CAPSENSE_CLK_SOURCE_AUTO_MASK,
+            .idacMod = { 32u, 32u, 32u, },
+            .idacGainIndex = 4u,
+            .rowIdacMod = { 32u, 32u, 32u, },
+            .bslnCoeff = 1u,
+            .status = 0u,
+            .wdTouch = {
+                .ptrPosition = &cy_capsense_tuner.position[0u],
+                .numPosition = 1,
+            },
+        },
+    },
+    .sensorContext = {
+        { /* Button0_Rx0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* Button1_Rx0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns0 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns1 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns2 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns3 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+        { /* LinearSlider0_Sns4 */
+            .raw = 0u,
+            .bsln = 0u,
+            .diff = 0u,
+            .status = 0u,
+            .negBslnRstCnt = 0u,
+            .idacComp = 32u,
+            .bslnExt = 0u,
+        },
+    },
+    .position = {
+        { /* LinearSlider0 */
+            .x = 0u,
+            .y = 0u,
+            .z = 0u,
+            .id = 0u,
+        },
+    },
+};
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+cy_stc_capsense_bist_context_t cy_capsense_bist_context =
+{
+};
+#endif
+#endif
+
+cy_stc_capsense_context_t cy_capsense_context =
+{
+    .ptrCommonConfig = &cy_capsense_commonConfig,
+    .ptrCommonContext = &cy_capsense_tuner.commonContext,
+    .ptrInternalContext = &cy_capsense_internalContext,
+    .ptrWdConfig = &cy_capsense_widgetConfig[0u],
+    .ptrWdContext = &cy_capsense_tuner.widgetContext[0u],
+    .ptrPinConfig = &cy_capsense_pinConfig[0u],
+    .ptrShieldPinConfig = NULL,
+    .ptrActiveScanSns = &cy_capsense_activeScanSns,
+    #if (CY_CAPSENSE_MW_VERSION < 300)
+        .ptrFptrConfig = (const void *) &cy_capsense_fptrConfig,
+    #endif
+    #if (CY_CAPSENSE_BIST_SUPPORTED)
+        .ptrBistContext = NULL,
+    #endif
+};
+
+#endif /* CY_CAPSENSE_CORE == __CORTEX_M */
+
+#endif /* !defined(CY_DISABLE_CAPSENSE) */
+
+/* [] END OF FILE */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h

@@ -0,0 +1,2330 @@
+/*******************************************************************************
+* File Name: cycfg_capsense.h
+*
+* Description:
+* CAPSENSE Middleware configuration
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.6195
+*
+********************************************************************************
+* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_H)
+#define CYCFG_CAPSENSE_H
+
+#include <stddef.h>
+#include "cy_device_headers.h"
+#include "cycfg_peripherals.h"
+#include "cycfg_capsense_defines.h"
+
+#define CY_CAPSENSE_CFG_TOOL_VERSION              (400)
+
+#if !defined(CY_DISABLE_CAPSENSE)
+
+#if (CY_CAPSENSE_CORE == __CORTEX_M)
+
+
+#if !defined(Cmod_PORT) || !defined(Cmod_PIN) || !defined(Cmod_PORT_NUM)
+#error Cmod Capacitor is not assigned: missing #define Cmod_PORT, #define Cmod_PIN, #define Cmod_PORT_NUM
+#endif
+
+#if !defined(CintA_PORT) || !defined(CintA_PIN) || !defined(CintA_PORT_NUM)
+#error CintA Capacitor is not assigned: missing #define CintA_PORT, #define CintA_PIN, #define CintA_PORT_NUM
+#endif
+
+#if !defined(CintB_PORT) || !defined(CintB_PIN) || !defined(CintB_PORT_NUM)
+#error CintB Capacitor is not assigned: missing #define CintB_PORT, #define CintB_PIN, #define CintB_PORT_NUM
+#endif
+
+#if !defined(Button0_Rx0_PORT) || !defined(Button0_Rx0_PIN)
+#error Button0_Rx0 Sensor is not assigned: missing #define Button0_Rx0_PORT, #define Button0_Rx0_PIN
+#endif
+
+#if !defined(Button0_Tx_PORT) || !defined(Button0_Tx_PIN)
+#error Button0_Tx Sensor is not assigned: missing #define Button0_Tx_PORT, #define Button0_Tx_PIN
+#endif
+
+#if !defined(Button1_Rx0_PORT) || !defined(Button1_Rx0_PIN)
+#error Button1_Rx0 Sensor is not assigned: missing #define Button1_Rx0_PORT, #define Button1_Rx0_PIN
+#endif
+
+#if !defined(Button1_Tx_PORT) || !defined(Button1_Tx_PIN)
+#error Button1_Tx Sensor is not assigned: missing #define Button1_Tx_PORT, #define Button1_Tx_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns0_PORT) || !defined(LinearSlider0_Sns0_PIN)
+#error LinearSlider0_Sns0 Sensor is not assigned: missing #define LinearSlider0_Sns0_PORT, #define LinearSlider0_Sns0_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns1_PORT) || !defined(LinearSlider0_Sns1_PIN)
+#error LinearSlider0_Sns1 Sensor is not assigned: missing #define LinearSlider0_Sns1_PORT, #define LinearSlider0_Sns1_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns2_PORT) || !defined(LinearSlider0_Sns2_PIN)
+#error LinearSlider0_Sns2 Sensor is not assigned: missing #define LinearSlider0_Sns2_PORT, #define LinearSlider0_Sns2_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns3_PORT) || !defined(LinearSlider0_Sns3_PIN)
+#error LinearSlider0_Sns3 Sensor is not assigned: missing #define LinearSlider0_Sns3_PORT, #define LinearSlider0_Sns3_PIN
+#endif
+
+#if !defined(LinearSlider0_Sns4_PORT) || !defined(LinearSlider0_Sns4_PIN)
+#error LinearSlider0_Sns4 Sensor is not assigned: missing #define LinearSlider0_Sns4_PORT, #define LinearSlider0_Sns4_PIN
+#endif
+
+#if !defined(CY_CAPSENSE_CPU_CLK)
+#error CPU clock frequency is not set: missing #define CY_CAPSENSE_CPU_CLK
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_CLK)
+#error Peripheral clock core is not set: missing #define CY_CAPSENSE_PERI_CLK
+#endif
+
+#if !defined(CY_CAPSENSE_VDDA_MV)
+#error VDDA voltage is not set: missing #define CY_CAPSENSE_VDDA_MV
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_DIV_TYPE)
+#error Peripheral clock divider type is not set: missing #define CY_CAPSENSE_PERI_DIV_TYPE
+#endif
+
+#if !defined(CY_CAPSENSE_PERI_DIV_INDEX)
+#error Peripheral clock divider index is not set: missing #define CY_CAPSENSE_PERI_DIV_INDEX
+#endif
+
+
+
+#include "cy_capsense.h"
+
+/* Supported CapSense Middleware version */
+#define CY_CAPSENSE_MW_VERSION_REQUIRED           (200)
+
+#if !defined (CY_CAPSENSE_MW_VERSION)
+    #if (CY_CAPSENSE_MW_VERSION_MAJOR == 2)
+        #define CY_CAPSENSE_MW_VERSION            (200)
+    #elif (CY_CAPSENSE_MW_VERSION_MAJOR == 1)
+        #define CY_CAPSENSE_MW_VERSION            (100)
+    #else
+        #define CY_CAPSENSE_MW_VERSION            (100)
+    #endif
+#endif
+
+/* Check the used Middleware version */
+#if (CY_CAPSENSE_MW_VERSION_REQUIRED > CY_CAPSENSE_MW_VERSION)
+    #error The CapSense Configurator requires a newer version of the CapSense Middleware. Update the CapSense Middleware in your project.
+#endif
+
+#define CY_CAPSENSE_BIST_SUPPORTED                (CY_CAPSENSE_MW_VERSION >= 210)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/* Widget names */
+#define CY_CAPSENSE_BUTTON0_WDGT_ID                                              (0u)
+#define CY_CAPSENSE_BUTTON1_WDGT_ID                                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_WDGT_ID                                        (2u)
+
+/* Button0 sensor names */
+#define CY_CAPSENSE_BUTTON0_SNS0_ID                                              (0u)
+
+/* Button0 node names */
+#define CY_CAPSENSE_BUTTON0_RX0_TX0_ID                                           (0u)
+
+/* Button0 sensor element IDs */
+#define CY_CAPSENSE_BUTTON0_RX0_ID                                               (0u)
+#define CY_CAPSENSE_BUTTON0_TX0_ID                                               (1u)
+
+/* Button1 sensor names */
+#define CY_CAPSENSE_BUTTON1_SNS0_ID                                              (0u)
+
+/* Button1 node names */
+#define CY_CAPSENSE_BUTTON1_RX0_TX0_ID                                           (0u)
+
+/* Button1 sensor element IDs */
+#define CY_CAPSENSE_BUTTON1_RX0_ID                                               (0u)
+#define CY_CAPSENSE_BUTTON1_TX0_ID                                               (1u)
+
+/* LinearSlider0 sensor names */
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ID                                        (0u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ID                                        (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ID                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ID                                        (3u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ID                                        (4u)
+
+
+typedef struct {
+    cy_stc_capsense_common_context_t commonContext;
+    cy_stc_capsense_widget_context_t widgetContext[3];
+    cy_stc_capsense_sensor_context_t sensorContext[7];
+    cy_stc_capsense_position_t position[1];
+} cy_stc_capsense_tuner_t;
+
+extern cy_stc_capsense_tuner_t cy_capsense_tuner;
+
+extern cy_stc_capsense_context_t cy_capsense_context;
+
+/* RAM Data structure register definitions */
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_CONFIG_ID_VALUE                                              (cy_capsense_tuner.commonContext.configId)
+#define CY_CAPSENSE_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_CONFIG_ID_SIZE                                               (2u)
+#define CY_CAPSENSE_CONFIG_ID_PARAM_ID                                           (0x02000000u)
+
+#define CY_CAPSENSE_TUNER_CMD_VALUE                                              (cy_capsense_tuner.commonContext.tunerCmd)
+#define CY_CAPSENSE_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_CMD_SIZE                                               (2u)
+#define CY_CAPSENSE_TUNER_CMD_PARAM_ID                                           (0x02000002u)
+
+#define CY_CAPSENSE_SCAN_COUNTER_VALUE                                           (cy_capsense_tuner.commonContext.scanCounter)
+#define CY_CAPSENSE_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_SCAN_COUNTER_SIZE                                            (2u)
+#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID                                        (0x02000004u)
+
+#define CY_CAPSENSE_TUNER_ST_VALUE                                               (cy_capsense_tuner.commonContext.tunerSt)
+#define CY_CAPSENSE_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_ST_SIZE                                                (1u)
+#define CY_CAPSENSE_TUNER_ST_PARAM_ID                                            (0x01000006u)
+
+#define CY_CAPSENSE_INITDONE_VALUE                                               (cy_capsense_tuner.commonContext.initDone)
+#define CY_CAPSENSE_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_INITDONE_SIZE                                                (1u)
+#define CY_CAPSENSE_INITDONE_PARAM_ID                                            (0x01000007u)
+
+#define CY_CAPSENSE_PTRSSCALLBACK_VALUE                                          (cy_capsense_tuner.commonContext.ptrSSCallback)
+#define CY_CAPSENSE_PTRSSCALLBACK_OFFSET                                         (8u)
+#define CY_CAPSENSE_PTRSSCALLBACK_SIZE                                           (4u)
+#define CY_CAPSENSE_PTRSSCALLBACK_PARAM_ID                                       (0x03000008u)
+
+#define CY_CAPSENSE_PTREOSCALLBACK_VALUE                                         (cy_capsense_tuner.commonContext.ptrEOSCallback)
+#define CY_CAPSENSE_PTREOSCALLBACK_OFFSET                                        (12u)
+#define CY_CAPSENSE_PTREOSCALLBACK_SIZE                                          (4u)
+#define CY_CAPSENSE_PTREOSCALLBACK_PARAM_ID                                      (0x0300000cu)
+
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_VALUE                                   (cy_capsense_tuner.commonContext.ptrTunerSendCallback)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_OFFSET                                  (16u)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_SIZE                                    (4u)
+#define CY_CAPSENSE_PTRTUNERSENDCALLBACK_PARAM_ID                                (0x03000010u)
+
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_VALUE                                (cy_capsense_tuner.commonContext.ptrTunerReceiveCallback)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_OFFSET                               (20u)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_SIZE                                 (4u)
+#define CY_CAPSENSE_PTRTUNERRECEIVECALLBACK_PARAM_ID                             (0x03000014u)
+
+#define CY_CAPSENSE_STATUS_VALUE                                                 (cy_capsense_tuner.commonContext.status)
+#define CY_CAPSENSE_STATUS_OFFSET                                                (24u)
+#define CY_CAPSENSE_STATUS_SIZE                                                  (4u)
+#define CY_CAPSENSE_STATUS_PARAM_ID                                              (0x03000018u)
+
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE                                      (cy_capsense_tuner.commonContext.timestampInterval)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET                                     (28u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE                                       (4u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID                                   (0x0300001cu)
+
+#define CY_CAPSENSE_TIMESTAMP_VALUE                                              (cy_capsense_tuner.commonContext.timestamp)
+#define CY_CAPSENSE_TIMESTAMP_OFFSET                                             (32u)
+#define CY_CAPSENSE_TIMESTAMP_SIZE                                               (4u)
+#define CY_CAPSENSE_TIMESTAMP_PARAM_ID                                           (0x03000020u)
+
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsdClk)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET                                   (36u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000024u)
+
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsxClk)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET                                   (37u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000025u)
+
+#define CY_CAPSENSE_TUNER_CNT_VALUE                                              (cy_capsense_tuner.commonContext.tunerCnt)
+#define CY_CAPSENSE_TUNER_CNT_OFFSET                                             (38u)
+#define CY_CAPSENSE_TUNER_CNT_SIZE                                               (1u)
+#define CY_CAPSENSE_TUNER_CNT_PARAM_ID                                           (0x01000026u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerCap)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET                                     (40u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID                                   (0x06000028u)
+
+#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[0].sigPFC)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET                                        (42u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID                                      (0x0600002au)
+
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_VALUE                                       (cy_capsense_tuner.widgetContext[0].resolution)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_OFFSET                                      (44u)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_PARAM_ID                                    (0x0600002cu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[0].maxRawCount)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET                                   (46u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID                                 (0x0200002eu)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerTh)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET                                     (48u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID                                   (0x06000030u)
+
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[0].proxTh)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (50u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID                               (0x06000032u)
+
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[0].lowBslnRst)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET                                  (52u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID                                (0x06000034u)
+
+#define CY_CAPSENSE_BUTTON0_TX_CLK_VALUE                                         (cy_capsense_tuner.widgetContext[0].snsClk)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_OFFSET                                        (54u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_PARAM_ID                                      (0x06000036u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[0].rowSnsClk)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET                                   (56u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID                                 (0x06000038u)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[0].gestureDetected)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET                              (58u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID                            (0x0200003au)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[0].gestureDirection)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET                             (60u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID                           (0x0200003cu)
+
+#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].xDelta)
+#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET                                        (62u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID                                      (0x0200003eu)
+
+#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].yDelta)
+#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET                                        (64u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID                                      (0x02000040u)
+
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[0].noiseTh)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET                                      (66u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE                                        (1u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID                                    (0x05000042u)
+
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].nNoiseTh)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET                                     (67u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID                                   (0x05000043u)
+
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[0].hysteresis)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET                                    (68u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID                                  (0x05000044u)
+
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[0].onDebounce)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET                                   (69u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID                                 (0x05000045u)
+
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_VALUE                                  (cy_capsense_tuner.widgetContext[0].snsClkSource)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_OFFSET                                 (70u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_PARAM_ID                               (0x05000046u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[0])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET                                     (71u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID                                   (0x05000047u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[1])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET                                     (72u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID                                   (0x05000048u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[2])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET                                     (73u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID                                   (0x05000049u)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[0].idacGainIndex)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (74u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID                             (0x0500004au)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (75u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID                               (0x0500004bu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (76u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID                               (0x0500004cu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (77u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID                               (0x0500004du)
+
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[0].bslnCoeff)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (78u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID                            (0x0100004eu)
+
+#define CY_CAPSENSE_BUTTON0_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[0].status)
+#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET                                        (79u)
+#define CY_CAPSENSE_BUTTON0_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID                                      (0x0100004fu)
+
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET                                   (80u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID                                 (0x03000050u)
+
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET                                 (84u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID                               (0x01000054u)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerCap)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET                                     (88u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID                                   (0x06010058u)
+
+#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[1].sigPFC)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET                                        (90u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID                                      (0x0601005au)
+
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_VALUE                                       (cy_capsense_tuner.widgetContext[1].resolution)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_OFFSET                                      (92u)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_PARAM_ID                                    (0x0601005cu)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[1].maxRawCount)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET                                   (94u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID                                 (0x0201005eu)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerTh)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET                                     (96u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID                                   (0x06010060u)
+
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[1].proxTh)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (98u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID                               (0x06010062u)
+
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[1].lowBslnRst)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET                                  (100u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID                                (0x06010064u)
+
+#define CY_CAPSENSE_BUTTON1_TX_CLK_VALUE                                         (cy_capsense_tuner.widgetContext[1].snsClk)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_OFFSET                                        (102u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_PARAM_ID                                      (0x06010066u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[1].rowSnsClk)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET                                   (104u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID                                 (0x06010068u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[1].gestureDetected)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET                              (106u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID                            (0x0201006au)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[1].gestureDirection)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET                             (108u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID                           (0x0201006cu)
+
+#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].xDelta)
+#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET                                        (110u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID                                      (0x0201006eu)
+
+#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].yDelta)
+#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET                                        (112u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID                                      (0x02010070u)
+
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[1].noiseTh)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET                                      (114u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE                                        (1u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID                                    (0x05010072u)
+
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].nNoiseTh)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET                                     (115u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID                                   (0x05010073u)
+
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[1].hysteresis)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET                                    (116u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE                                      (1u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID                                  (0x05010074u)
+
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[1].onDebounce)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET                                   (117u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID                                 (0x05010075u)
+
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_VALUE                                  (cy_capsense_tuner.widgetContext[1].snsClkSource)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_OFFSET                                 (118u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_PARAM_ID                               (0x05010076u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[0])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET                                     (119u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID                                   (0x05010077u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[1])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET                                     (120u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID                                   (0x05010078u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[2])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET                                     (121u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID                                   (0x05010079u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[1].idacGainIndex)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (122u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID                             (0x0501007au)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (123u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID                               (0x0501007bu)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (124u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID                               (0x0501007cu)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (125u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID                               (0x0501007du)
+
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[1].bslnCoeff)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (126u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID                            (0x0101007eu)
+
+#define CY_CAPSENSE_BUTTON1_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[1].status)
+#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET                                        (127u)
+#define CY_CAPSENSE_BUTTON1_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID                                      (0x0101007fu)
+
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID                                 (0x03010080u)
+
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID                               (0x01010084u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerCap)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID                             (0x06020088u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE                                   (cy_capsense_tuner.widgetContext[2].sigPFC)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID                                (0x0602008au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE                               (cy_capsense_tuner.widgetContext[2].resolution)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID                            (0x0602008cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE                              (cy_capsense_tuner.widgetContext[2].maxRawCount)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID                           (0x0202008eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerTh)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET                               (144u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID                             (0x02020090u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE                            (cy_capsense_tuner.widgetContext[2].proxTh)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (146u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID                         (0x02020092u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE                             (cy_capsense_tuner.widgetContext[2].lowBslnRst)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (148u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID                          (0x06020094u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE                                  (cy_capsense_tuner.widgetContext[2].snsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET                                 (150u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID                               (0x06020096u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE                              (cy_capsense_tuner.widgetContext[2].rowSnsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (152u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID                           (0x06020098u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE                         (cy_capsense_tuner.widgetContext[2].gestureDetected)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (154u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID                      (0x0202009au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE                        (cy_capsense_tuner.widgetContext[2].gestureDirection)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (156u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID                     (0x0202009cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].xDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET                                  (158u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID                                (0x0202009eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].yDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID                                (0x020200a0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE                                 (cy_capsense_tuner.widgetContext[2].noiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET                                (162u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE                                  (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID                              (0x010200a2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].nNoiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET                               (163u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID                             (0x010200a3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE                               (cy_capsense_tuner.widgetContext[2].hysteresis)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET                              (164u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID                            (0x010200a4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE                              (cy_capsense_tuner.widgetContext[2].onDebounce)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (165u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID                           (0x050200a5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE                           (cy_capsense_tuner.widgetContext[2].snsClkSource)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (166u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID                        (0x050200a6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (167u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID                             (0x050200a7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (168u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID                             (0x050200a8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (169u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID                             (0x050200a9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE                          (cy_capsense_tuner.widgetContext[2].idacGainIndex)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (170u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID                       (0x050200aau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (171u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID                         (0x050200abu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (172u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID                         (0x050200acu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (173u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID                         (0x050200adu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE                         (cy_capsense_tuner.widgetContext[2].bslnCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (174u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID                      (0x010200aeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE                                   (cy_capsense_tuner.widgetContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET                                  (175u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID                                (0x010200afu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE                              (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET                             (176u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID                           (0x030200b0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE                            (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (180u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID                         (0x010200b4u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_VALUE                                       (cy_capsense_tuner.sensorContext[0].raw)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_OFFSET                                      (184u)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_PARAM_ID                                    (0x020000b8u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_VALUE                                      (cy_capsense_tuner.sensorContext[0].bsln)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_OFFSET                                     (186u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_PARAM_ID                                   (0x020000bau)
+
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_VALUE                                      (cy_capsense_tuner.sensorContext[0].diff)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_OFFSET                                     (188u)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_PARAM_ID                                   (0x020000bcu)
+
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_VALUE                                    (cy_capsense_tuner.sensorContext[0].status)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_OFFSET                                   (190u)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_PARAM_ID                                 (0x010000beu)
+
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_VALUE                          (cy_capsense_tuner.sensorContext[0].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (191u)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_PARAM_ID                       (0x010000bfu)
+
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_VALUE                                      (cy_capsense_tuner.sensorContext[0].idacComp)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_OFFSET                                     (192u)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_PARAM_ID                                   (0x010000c0u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_VALUE                                  (cy_capsense_tuner.sensorContext[0].bslnExt)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_OFFSET                                 (193u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_PARAM_ID                               (0x010000c1u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_VALUE                                       (cy_capsense_tuner.sensorContext[1].raw)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_OFFSET                                      (194u)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_PARAM_ID                                    (0x020100c2u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_VALUE                                      (cy_capsense_tuner.sensorContext[1].bsln)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_OFFSET                                     (196u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_PARAM_ID                                   (0x020100c4u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_VALUE                                      (cy_capsense_tuner.sensorContext[1].diff)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_OFFSET                                     (198u)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_PARAM_ID                                   (0x020100c6u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_VALUE                                    (cy_capsense_tuner.sensorContext[1].status)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_OFFSET                                   (200u)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_PARAM_ID                                 (0x010100c8u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_VALUE                          (cy_capsense_tuner.sensorContext[1].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (201u)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_PARAM_ID                       (0x010100c9u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_VALUE                                      (cy_capsense_tuner.sensorContext[1].idacComp)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_OFFSET                                     (202u)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_PARAM_ID                                   (0x010100cau)
+
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_VALUE                                  (cy_capsense_tuner.sensorContext[1].bslnExt)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_OFFSET                                 (203u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_PARAM_ID                               (0x010100cbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[2].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (204u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID                             (0x020200ccu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[2].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (206u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID                            (0x020200ceu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[2].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (208u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID                            (0x020200d0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (210u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID                          (0x010200d2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[2].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (211u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200d3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[2].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (212u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID                            (0x010200d4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[2].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (213u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID                        (0x010200d5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[3].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (214u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID                             (0x020200d6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[3].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (216u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID                            (0x020200d8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[3].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (218u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID                            (0x020200dau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[3].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (220u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID                          (0x010200dcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[3].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (221u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200ddu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[3].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (222u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID                            (0x010200deu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[3].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (223u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID                        (0x010200dfu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[4].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (224u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID                             (0x020200e0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[4].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (226u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID                            (0x020200e2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[4].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (228u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID                            (0x020200e4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[4].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (230u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID                          (0x010200e6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[4].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (231u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200e7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[4].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (232u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID                            (0x010200e8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[4].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (233u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID                        (0x010200e9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[5].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (234u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID                             (0x020200eau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[5].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (236u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID                            (0x020200ecu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[5].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (238u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID                            (0x020200eeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[5].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (240u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID                          (0x010200f0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[5].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (241u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200f1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[5].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (242u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID                            (0x010200f2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[5].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (243u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID                        (0x010200f3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[6].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (244u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID                             (0x020200f4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[6].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (246u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID                            (0x020200f6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[6].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (248u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID                            (0x020200f8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[6].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (250u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID                          (0x010200fau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[6].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (251u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200fbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[6].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (252u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID                            (0x010200fcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[6].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (253u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID                        (0x010200fdu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE                                       (cy_capsense_tuner.position[0].x)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET                                      (254u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID                                    (0x020200feu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE                                       (cy_capsense_tuner.position[0].y)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET                                      (256u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID                                    (0x02020100u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE                                       (cy_capsense_tuner.position[0].z)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET                                      (258u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID                                    (0x02020102u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE                                      (cy_capsense_tuner.position[0].id)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET                                     (260u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE                                       (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID                                   (0x02020104u)
+
+#else /* CY_CAPSENSE_MW_VERSION >= 300 */
+#define CY_CAPSENSE_CONFIG_ID_VALUE                                              (cy_capsense_tuner.commonContext.configId)
+#define CY_CAPSENSE_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_CONFIG_ID_SIZE                                               (2u)
+#define CY_CAPSENSE_CONFIG_ID_PARAM_ID                                           (0x02000000u)
+
+#define CY_CAPSENSE_TUNER_CMD_VALUE                                              (cy_capsense_tuner.commonContext.tunerCmd)
+#define CY_CAPSENSE_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_CMD_SIZE                                               (2u)
+#define CY_CAPSENSE_TUNER_CMD_PARAM_ID                                           (0x02000002u)
+
+#define CY_CAPSENSE_SCAN_COUNTER_VALUE                                           (cy_capsense_tuner.commonContext.scanCounter)
+#define CY_CAPSENSE_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_SCAN_COUNTER_SIZE                                            (2u)
+#define CY_CAPSENSE_SCAN_COUNTER_PARAM_ID                                        (0x02000004u)
+
+#define CY_CAPSENSE_TUNER_ST_VALUE                                               (cy_capsense_tuner.commonContext.tunerSt)
+#define CY_CAPSENSE_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_ST_SIZE                                                (1u)
+#define CY_CAPSENSE_TUNER_ST_PARAM_ID                                            (0x01000006u)
+
+#define CY_CAPSENSE_INITDONE_VALUE                                               (cy_capsense_tuner.commonContext.initDone)
+#define CY_CAPSENSE_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_INITDONE_SIZE                                                (1u)
+#define CY_CAPSENSE_INITDONE_PARAM_ID                                            (0x01000007u)
+
+#define CY_CAPSENSE_STATUS_VALUE                                                 (cy_capsense_tuner.commonContext.status)
+#define CY_CAPSENSE_STATUS_OFFSET                                                (8u)
+#define CY_CAPSENSE_STATUS_SIZE                                                  (4u)
+#define CY_CAPSENSE_STATUS_PARAM_ID                                              (0x03000008u)
+
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_VALUE                                      (cy_capsense_tuner.commonContext.timestampInterval)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_OFFSET                                     (12u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_SIZE                                       (4u)
+#define CY_CAPSENSE_TIMESTAMPINTERVAL_PARAM_ID                                   (0x0300000cu)
+
+#define CY_CAPSENSE_TIMESTAMP_VALUE                                              (cy_capsense_tuner.commonContext.timestamp)
+#define CY_CAPSENSE_TIMESTAMP_OFFSET                                             (16u)
+#define CY_CAPSENSE_TIMESTAMP_SIZE                                               (4u)
+#define CY_CAPSENSE_TIMESTAMP_PARAM_ID                                           (0x03000010u)
+
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsdClk)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_OFFSET                                   (20u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSD_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000014u)
+
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_VALUE                                    (cy_capsense_tuner.commonContext.modCsxClk)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_OFFSET                                   (21u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+#define CY_CAPSENSE_CSX_MOD_CLK_DIVIDER_PARAM_ID                                 (0x01000015u)
+
+#define CY_CAPSENSE_TUNER_CNT_VALUE                                              (cy_capsense_tuner.commonContext.tunerCnt)
+#define CY_CAPSENSE_TUNER_CNT_OFFSET                                             (22u)
+#define CY_CAPSENSE_TUNER_CNT_SIZE                                               (1u)
+#define CY_CAPSENSE_TUNER_CNT_PARAM_ID                                           (0x01000016u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerCap)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_OFFSET                                     (24u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_CP_PARAM_ID                                   (0x06000018u)
+
+#define CY_CAPSENSE_BUTTON0_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[0].sigPFC)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_OFFSET                                        (26u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_SIGPFC_PARAM_ID                                      (0x0600001au)
+
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_VALUE                                       (cy_capsense_tuner.widgetContext[0].resolution)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_OFFSET                                      (28u)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_NUM_CONV_PARAM_ID                                    (0x0600001cu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[0].maxRawCount)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_OFFSET                                   (30u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNT_PARAM_ID                                 (0x0200001eu)
+
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_VALUE                                 (cy_capsense_tuner.widgetContext[0].maxRawCountRow)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_OFFSET                                (32u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_SIZE                                  (2u)
+#define CY_CAPSENSE_BUTTON0_MAXRAWCOUNTROW_PARAM_ID                              (0x02000020u)
+
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].fingerTh)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_OFFSET                                     (34u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_FINGER_TH_PARAM_ID                                   (0x06000022u)
+
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[0].proxTh)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (36u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON0_PROX_TOUCH_TH_PARAM_ID                               (0x06000024u)
+
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[0].lowBslnRst)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_OFFSET                                  (38u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON0_LOW_BSLN_RST_PARAM_ID                                (0x06000026u)
+
+#define CY_CAPSENSE_BUTTON0_TX_CLK_VALUE                                         (cy_capsense_tuner.widgetContext[0].snsClk)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_OFFSET                                        (40u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_PARAM_ID                                      (0x06000028u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[0].rowSnsClk)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_OFFSET                                   (42u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON0_ROW_SNS_CLK_PARAM_ID                                 (0x0600002au)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[0].gestureDetected)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_OFFSET                              (44u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DETECTED_PARAM_ID                            (0x0200002cu)
+
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[0].gestureDirection)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_OFFSET                             (46u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON0_GESTURE_DIRECTION_PARAM_ID                           (0x0200002eu)
+
+#define CY_CAPSENSE_BUTTON0_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].xDelta)
+#define CY_CAPSENSE_BUTTON0_XDELTA_OFFSET                                        (48u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_XDELTA_PARAM_ID                                      (0x02000030u)
+
+#define CY_CAPSENSE_BUTTON0_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[0].yDelta)
+#define CY_CAPSENSE_BUTTON0_YDELTA_OFFSET                                        (50u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON0_YDELTA_PARAM_ID                                      (0x02000032u)
+
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[0].noiseTh)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_OFFSET                                      (52u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_NOISE_TH_PARAM_ID                                    (0x06000034u)
+
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[0].nNoiseTh)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_OFFSET                                     (54u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_NNOISE_TH_PARAM_ID                                   (0x06000036u)
+
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[0].hysteresis)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_OFFSET                                    (56u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON0_HYSTERESIS_PARAM_ID                                  (0x06000038u)
+
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[0].onDebounce)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_OFFSET                                   (58u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_ON_DEBOUNCE_PARAM_ID                                 (0x0500003au)
+
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_VALUE                                  (cy_capsense_tuner.widgetContext[0].snsClkSource)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_OFFSET                                 (59u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_TX_CLK_SOURCE_PARAM_ID                               (0x0500003bu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[0])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_OFFSET                                     (60u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD0_PARAM_ID                                   (0x0500003cu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[1])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_OFFSET                                     (61u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD1_PARAM_ID                                   (0x0500003du)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[0].idacMod[2])
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_OFFSET                                     (62u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_MOD2_PARAM_ID                                   (0x0500003eu)
+
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[0].idacGainIndex)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (63u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON0_IDAC_GAIN_INDEX_PARAM_ID                             (0x0500003fu)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (64u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD0_PARAM_ID                               (0x05000040u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (65u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD1_PARAM_ID                               (0x05000041u)
+
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[0].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (66u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_ROW_IDAC_MOD2_PARAM_ID                               (0x05000042u)
+
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[0].bslnCoeff)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (67u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON0_REGULAR_IIR_BL_N_PARAM_ID                            (0x01000043u)
+
+#define CY_CAPSENSE_BUTTON0_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[0].status)
+#define CY_CAPSENSE_BUTTON0_STATUS_OFFSET                                        (68u)
+#define CY_CAPSENSE_BUTTON0_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON0_STATUS_PARAM_ID                                      (0x01000044u)
+
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[0].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_OFFSET                                   (72u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON0_PTRPOSITION_PARAM_ID                                 (0x03000048u)
+
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[0].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_OFFSET                                 (76u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_NUM_POSITIONS_PARAM_ID                               (0x0100004cu)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerCap)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_OFFSET                                     (80u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_CP_PARAM_ID                                   (0x06010050u)
+
+#define CY_CAPSENSE_BUTTON1_SIGPFC_VALUE                                         (cy_capsense_tuner.widgetContext[1].sigPFC)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_OFFSET                                        (82u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_SIGPFC_PARAM_ID                                      (0x06010052u)
+
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_VALUE                                       (cy_capsense_tuner.widgetContext[1].resolution)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_OFFSET                                      (84u)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_NUM_CONV_PARAM_ID                                    (0x06010054u)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_VALUE                                    (cy_capsense_tuner.widgetContext[1].maxRawCount)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_OFFSET                                   (86u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNT_PARAM_ID                                 (0x02010056u)
+
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_VALUE                                 (cy_capsense_tuner.widgetContext[1].maxRawCountRow)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_OFFSET                                (88u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_SIZE                                  (2u)
+#define CY_CAPSENSE_BUTTON1_MAXRAWCOUNTROW_PARAM_ID                              (0x02010058u)
+
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].fingerTh)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_OFFSET                                     (90u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_FINGER_TH_PARAM_ID                                   (0x0601005au)
+
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_VALUE                                  (cy_capsense_tuner.widgetContext[1].proxTh)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (92u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+#define CY_CAPSENSE_BUTTON1_PROX_TOUCH_TH_PARAM_ID                               (0x0601005cu)
+
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_VALUE                                   (cy_capsense_tuner.widgetContext[1].lowBslnRst)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_OFFSET                                  (94u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+#define CY_CAPSENSE_BUTTON1_LOW_BSLN_RST_PARAM_ID                                (0x0601005eu)
+
+#define CY_CAPSENSE_BUTTON1_TX_CLK_VALUE                                         (cy_capsense_tuner.widgetContext[1].snsClk)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_OFFSET                                        (96u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_PARAM_ID                                      (0x06010060u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_VALUE                                    (cy_capsense_tuner.widgetContext[1].rowSnsClk)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_OFFSET                                   (98u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+#define CY_CAPSENSE_BUTTON1_ROW_SNS_CLK_PARAM_ID                                 (0x06010062u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_VALUE                               (cy_capsense_tuner.widgetContext[1].gestureDetected)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_OFFSET                              (100u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DETECTED_PARAM_ID                            (0x02010064u)
+
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_VALUE                              (cy_capsense_tuner.widgetContext[1].gestureDirection)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_OFFSET                             (102u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+#define CY_CAPSENSE_BUTTON1_GESTURE_DIRECTION_PARAM_ID                           (0x02010066u)
+
+#define CY_CAPSENSE_BUTTON1_XDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].xDelta)
+#define CY_CAPSENSE_BUTTON1_XDELTA_OFFSET                                        (104u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_XDELTA_PARAM_ID                                      (0x02010068u)
+
+#define CY_CAPSENSE_BUTTON1_YDELTA_VALUE                                         (cy_capsense_tuner.widgetContext[1].yDelta)
+#define CY_CAPSENSE_BUTTON1_YDELTA_OFFSET                                        (106u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_SIZE                                          (2u)
+#define CY_CAPSENSE_BUTTON1_YDELTA_PARAM_ID                                      (0x0201006au)
+
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_VALUE                                       (cy_capsense_tuner.widgetContext[1].noiseTh)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_OFFSET                                      (108u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_NOISE_TH_PARAM_ID                                    (0x0601006cu)
+
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_VALUE                                      (cy_capsense_tuner.widgetContext[1].nNoiseTh)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_OFFSET                                     (110u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_NNOISE_TH_PARAM_ID                                   (0x0601006eu)
+
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_VALUE                                     (cy_capsense_tuner.widgetContext[1].hysteresis)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_OFFSET                                    (112u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_SIZE                                      (2u)
+#define CY_CAPSENSE_BUTTON1_HYSTERESIS_PARAM_ID                                  (0x06010070u)
+
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_VALUE                                    (cy_capsense_tuner.widgetContext[1].onDebounce)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_OFFSET                                   (114u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_ON_DEBOUNCE_PARAM_ID                                 (0x05010072u)
+
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_VALUE                                  (cy_capsense_tuner.widgetContext[1].snsClkSource)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_OFFSET                                 (115u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_TX_CLK_SOURCE_PARAM_ID                               (0x05010073u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[0])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_OFFSET                                     (116u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD0_PARAM_ID                                   (0x05010074u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[1])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_OFFSET                                     (117u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD1_PARAM_ID                                   (0x05010075u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_VALUE                                      (cy_capsense_tuner.widgetContext[1].idacMod[2])
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_OFFSET                                     (118u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_MOD2_PARAM_ID                                   (0x05010076u)
+
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_VALUE                                (cy_capsense_tuner.widgetContext[1].idacGainIndex)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (119u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+#define CY_CAPSENSE_BUTTON1_IDAC_GAIN_INDEX_PARAM_ID                             (0x05010077u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[0])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (120u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD0_PARAM_ID                               (0x05010078u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[1])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (121u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD1_PARAM_ID                               (0x05010079u)
+
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_VALUE                                  (cy_capsense_tuner.widgetContext[1].rowIdacMod[2])
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (122u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_ROW_IDAC_MOD2_PARAM_ID                               (0x0501007au)
+
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_VALUE                               (cy_capsense_tuner.widgetContext[1].bslnCoeff)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (123u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+#define CY_CAPSENSE_BUTTON1_REGULAR_IIR_BL_N_PARAM_ID                            (0x0101007bu)
+
+#define CY_CAPSENSE_BUTTON1_STATUS_VALUE                                         (cy_capsense_tuner.widgetContext[1].status)
+#define CY_CAPSENSE_BUTTON1_STATUS_OFFSET                                        (124u)
+#define CY_CAPSENSE_BUTTON1_STATUS_SIZE                                          (1u)
+#define CY_CAPSENSE_BUTTON1_STATUS_PARAM_ID                                      (0x0101007cu)
+
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_VALUE                                    (cy_capsense_tuner.widgetContext[1].wdTouch.ptrPosition)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+#define CY_CAPSENSE_BUTTON1_PTRPOSITION_PARAM_ID                                 (0x03010080u)
+
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_VALUE                                  (cy_capsense_tuner.widgetContext[1].wdTouch.numPosition)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_NUM_POSITIONS_PARAM_ID                               (0x01010084u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerCap)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_CP_PARAM_ID                             (0x06020088u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_VALUE                                   (cy_capsense_tuner.widgetContext[2].sigPFC)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SIGPFC_PARAM_ID                                (0x0602008au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_VALUE                               (cy_capsense_tuner.widgetContext[2].resolution)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_RESOLUTION_PARAM_ID                            (0x0602008cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_VALUE                              (cy_capsense_tuner.widgetContext[2].maxRawCount)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNT_PARAM_ID                           (0x0202008eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_VALUE                           (cy_capsense_tuner.widgetContext[2].maxRawCountRow)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET                          (144u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE                            (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_MAXRAWCOUNTROW_PARAM_ID                        (0x02020090u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].fingerTh)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_OFFSET                               (146u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_FINGER_TH_PARAM_ID                             (0x02020092u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_VALUE                            (cy_capsense_tuner.widgetContext[2].proxTh)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (148u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_PROX_TOUCH_TH_PARAM_ID                         (0x02020094u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_VALUE                             (cy_capsense_tuner.widgetContext[2].lowBslnRst)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (150u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_LOW_BSLN_RST_PARAM_ID                          (0x06020096u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_VALUE                                  (cy_capsense_tuner.widgetContext[2].snsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_OFFSET                                 (152u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_PARAM_ID                               (0x06020098u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_VALUE                              (cy_capsense_tuner.widgetContext[2].rowSnsClk)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (154u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_SNS_CLK_PARAM_ID                           (0x0602009au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_VALUE                         (cy_capsense_tuner.widgetContext[2].gestureDetected)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (156u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DETECTED_PARAM_ID                      (0x0202009cu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_VALUE                        (cy_capsense_tuner.widgetContext[2].gestureDirection)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (158u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_GESTURE_DIRECTION_PARAM_ID                     (0x0202009eu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].xDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_XDELTA_PARAM_ID                                (0x020200a0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_VALUE                                   (cy_capsense_tuner.widgetContext[2].yDelta)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_OFFSET                                  (162u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_YDELTA_PARAM_ID                                (0x020200a2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_VALUE                                 (cy_capsense_tuner.widgetContext[2].noiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_OFFSET                                (164u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_SIZE                                  (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_NOISE_TH_PARAM_ID                              (0x020200a4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_VALUE                                (cy_capsense_tuner.widgetContext[2].nNoiseTh)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_OFFSET                               (166u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_NNOISE_TH_PARAM_ID                             (0x020200a6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_VALUE                               (cy_capsense_tuner.widgetContext[2].hysteresis)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_OFFSET                              (168u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_HYSTERESIS_PARAM_ID                            (0x020200a8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_VALUE                              (cy_capsense_tuner.widgetContext[2].onDebounce)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (170u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ON_DEBOUNCE_PARAM_ID                           (0x050200aau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_VALUE                           (cy_capsense_tuner.widgetContext[2].snsClkSource)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (171u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS_CLK_SOURCE_PARAM_ID                        (0x050200abu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (172u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD0_PARAM_ID                             (0x050200acu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (173u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD1_PARAM_ID                             (0x050200adu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_VALUE                                (cy_capsense_tuner.widgetContext[2].idacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (174u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_MOD2_PARAM_ID                             (0x050200aeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_VALUE                          (cy_capsense_tuner.widgetContext[2].idacGainIndex)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (175u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_IDAC_GAIN_INDEX_PARAM_ID                       (0x050200afu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[0])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (176u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD0_PARAM_ID                         (0x050200b0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[1])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (177u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD1_PARAM_ID                         (0x050200b1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_VALUE                            (cy_capsense_tuner.widgetContext[2].rowIdacMod[2])
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (178u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_ROW_IDAC_MOD2_PARAM_ID                         (0x050200b2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_VALUE                         (cy_capsense_tuner.widgetContext[2].bslnCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (179u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_REGULAR_IIR_BL_N_PARAM_ID                      (0x010200b3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_VALUE                                   (cy_capsense_tuner.widgetContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_OFFSET                                  (180u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_STATUS_PARAM_ID                                (0x010200b4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_VALUE                              (cy_capsense_tuner.widgetContext[2].wdTouch.ptrPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_OFFSET                             (184u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+#define CY_CAPSENSE_LINEARSLIDER0_PTRPOSITION_PARAM_ID                           (0x030200b8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_VALUE                            (cy_capsense_tuner.widgetContext[2].wdTouch.numPosition)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (188u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_POSITIONS_PARAM_ID                         (0x010200bcu)
+
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_VALUE                                       (cy_capsense_tuner.sensorContext[0].raw)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_OFFSET                                      (192u)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_RAW0_PARAM_ID                                    (0x020000c0u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_VALUE                                      (cy_capsense_tuner.sensorContext[0].bsln)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_OFFSET                                     (194u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN0_PARAM_ID                                   (0x020000c2u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_VALUE                                      (cy_capsense_tuner.sensorContext[0].diff)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_OFFSET                                     (196u)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON0_RX0_DIFF0_PARAM_ID                                   (0x020000c4u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_VALUE                                    (cy_capsense_tuner.sensorContext[0].status)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_OFFSET                                   (198u)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_STATUS0_PARAM_ID                                 (0x010000c6u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_VALUE                          (cy_capsense_tuner.sensorContext[0].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (199u)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_NEG_BSLN_RST_CNT0_PARAM_ID                       (0x010000c7u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_VALUE                                      (cy_capsense_tuner.sensorContext[0].idacComp)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_OFFSET                                     (200u)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_IDAC0_PARAM_ID                                   (0x010000c8u)
+
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_VALUE                                  (cy_capsense_tuner.sensorContext[0].bslnExt)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_OFFSET                                 (201u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON0_RX0_BSLN_EXT0_PARAM_ID                               (0x010000c9u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_VALUE                                       (cy_capsense_tuner.sensorContext[1].raw)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_OFFSET                                      (202u)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_SIZE                                        (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_RAW0_PARAM_ID                                    (0x020100cau)
+
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_VALUE                                      (cy_capsense_tuner.sensorContext[1].bsln)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_OFFSET                                     (204u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN0_PARAM_ID                                   (0x020100ccu)
+
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_VALUE                                      (cy_capsense_tuner.sensorContext[1].diff)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_OFFSET                                     (206u)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_SIZE                                       (2u)
+#define CY_CAPSENSE_BUTTON1_RX0_DIFF0_PARAM_ID                                   (0x020100ceu)
+
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_VALUE                                    (cy_capsense_tuner.sensorContext[1].status)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_OFFSET                                   (208u)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_SIZE                                     (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_STATUS0_PARAM_ID                                 (0x010100d0u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_VALUE                          (cy_capsense_tuner.sensorContext[1].negBslnRstCnt)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (209u)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_NEG_BSLN_RST_CNT0_PARAM_ID                       (0x010100d1u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_VALUE                                      (cy_capsense_tuner.sensorContext[1].idacComp)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_OFFSET                                     (210u)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_SIZE                                       (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_IDAC0_PARAM_ID                                   (0x010100d2u)
+
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_VALUE                                  (cy_capsense_tuner.sensorContext[1].bslnExt)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_OFFSET                                 (211u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_SIZE                                   (1u)
+#define CY_CAPSENSE_BUTTON1_RX0_BSLN_EXT0_PARAM_ID                               (0x010100d3u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[2].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (212u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_RAW0_PARAM_ID                             (0x020200d4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[2].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (214u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN0_PARAM_ID                            (0x020200d6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[2].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (216u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_DIFF0_PARAM_ID                            (0x020200d8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[2].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (218u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_STATUS0_PARAM_ID                          (0x010200dau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[2].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (219u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200dbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[2].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (220u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_IDAC0_PARAM_ID                            (0x010200dcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[2].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (221u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_BSLN_EXT0_PARAM_ID                        (0x010200ddu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[3].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (222u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_RAW0_PARAM_ID                             (0x020200deu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[3].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (224u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN0_PARAM_ID                            (0x020200e0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[3].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (226u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_DIFF0_PARAM_ID                            (0x020200e2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[3].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (228u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_STATUS0_PARAM_ID                          (0x010200e4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[3].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (229u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200e5u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[3].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (230u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_IDAC0_PARAM_ID                            (0x010200e6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[3].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (231u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_BSLN_EXT0_PARAM_ID                        (0x010200e7u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[4].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (232u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_RAW0_PARAM_ID                             (0x020200e8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[4].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (234u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN0_PARAM_ID                            (0x020200eau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[4].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (236u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_DIFF0_PARAM_ID                            (0x020200ecu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[4].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (238u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_STATUS0_PARAM_ID                          (0x010200eeu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[4].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (239u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200efu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[4].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (240u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_IDAC0_PARAM_ID                            (0x010200f0u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[4].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (241u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_BSLN_EXT0_PARAM_ID                        (0x010200f1u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[5].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (242u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_RAW0_PARAM_ID                             (0x020200f2u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[5].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (244u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN0_PARAM_ID                            (0x020200f4u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[5].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (246u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_DIFF0_PARAM_ID                            (0x020200f6u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[5].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (248u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_STATUS0_PARAM_ID                          (0x010200f8u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[5].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (249u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_PARAM_ID                (0x010200f9u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[5].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (250u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_IDAC0_PARAM_ID                            (0x010200fau)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[5].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (251u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_BSLN_EXT0_PARAM_ID                        (0x010200fbu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_VALUE                                (cy_capsense_tuner.sensorContext[6].raw)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (252u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_RAW0_PARAM_ID                             (0x020200fcu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_VALUE                               (cy_capsense_tuner.sensorContext[6].bsln)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (254u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN0_PARAM_ID                            (0x020200feu)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_VALUE                               (cy_capsense_tuner.sensorContext[6].diff)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (256u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_DIFF0_PARAM_ID                            (0x02020100u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_VALUE                             (cy_capsense_tuner.sensorContext[6].status)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (258u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_STATUS0_PARAM_ID                          (0x01020102u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_VALUE                   (cy_capsense_tuner.sensorContext[6].negBslnRstCnt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (259u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_PARAM_ID                (0x01020103u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_VALUE                               (cy_capsense_tuner.sensorContext[6].idacComp)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (260u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_IDAC0_PARAM_ID                            (0x01020104u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_VALUE                           (cy_capsense_tuner.sensorContext[6].bslnExt)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (261u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_BSLN_EXT0_PARAM_ID                        (0x01020105u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_X0_VALUE                                       (cy_capsense_tuner.position[0].x)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_OFFSET                                      (262u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_X0_PARAM_ID                                    (0x02020106u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_VALUE                                       (cy_capsense_tuner.position[0].y)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_OFFSET                                      (264u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Y0_PARAM_ID                                    (0x02020108u)
+
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_VALUE                                       (cy_capsense_tuner.position[0].z)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_OFFSET                                      (266u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_SIZE                                        (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_Z0_PARAM_ID                                    (0x0202010au)
+
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_VALUE                                      (cy_capsense_tuner.position[0].id)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_OFFSET                                     (268u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_SIZE                                       (2u)
+#define CY_CAPSENSE_LINEARSLIDER0_ID0_PARAM_ID                                   (0x0202010cu)
+
+#endif
+/* cy_capsense_context */
+#define CY_CAPSENSE_COMMON_CONFIG_PTR_VALUE                                      (cy_capsense_context.ptrCommonConfig)
+#define CY_CAPSENSE_COMMON_CONFIG_PTR_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig))
+
+#define CY_CAPSENSE_COMMON_CONTEXT_PTR_VALUE                                     (cy_capsense_context.ptrCommonContext)
+#define CY_CAPSENSE_COMMON_CONTEXT_PTR_SIZE                                      (sizeof(cy_capsense_context.ptrCommonContext))
+
+#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_VALUE                                   (cy_capsense_context.ptrInternalContext)
+#define CY_CAPSENSE_INTERNAL_CONTEXT_PTR_SIZE                                    (sizeof(cy_capsense_context.ptrInternalContext))
+
+#define CY_CAPSENSE_WD_CONFIG_PTR_VALUE                                          (cy_capsense_context.ptrWdConfig)
+#define CY_CAPSENSE_WD_CONFIG_PTR_SIZE                                           (sizeof(cy_capsense_context.ptrWdConfig))
+
+#define CY_CAPSENSE_WD_CONTEXT_PTR_VALUE                                         (cy_capsense_context.ptrWdContext)
+#define CY_CAPSENSE_WD_CONTEXT_PTR_SIZE                                          (sizeof(cy_capsense_context.ptrWdContext))
+
+#define CY_CAPSENSE_PIN_CONFIG_PTR_VALUE                                         (cy_capsense_context.ptrPinConfig)
+#define CY_CAPSENSE_PIN_CONFIG_PTR_SIZE                                          (sizeof(cy_capsense_context.ptrPinConfig))
+
+#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_VALUE                                  (cy_capsense_context.ptrShieldPinConfig)
+#define CY_CAPSENSE_SHIELD_PIN_CONFIG_PTR_SIZE                                   (sizeof(cy_capsense_context.ptrShieldPinConfig))
+
+#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_VALUE                                    (cy_capsense_context.ptrActiveScanSns)
+#define CY_CAPSENSE_ACTIVE_SCAN_SNS_PTR_SIZE                                     (sizeof(cy_capsense_context.ptrActiveScanSns))
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_FPTR_CONFIG_PTR_VALUE                                        (cy_capsense_context.ptrFptrConfig)
+#define CY_CAPSENSE_FPTR_CONFIG_PTR_SIZE                                         (sizeof(cy_capsense_context.ptrFptrConfig))
+#endif
+
+#define CY_CAPSENSE_BIST_CONTEXT_PTR_VALUE                                       (cy_capsense_context.ptrBistContext)
+#define CY_CAPSENSE_BIST_CONTEXT_PTR_SIZE                                        (sizeof(cy_capsense_context.ptrBistContext))
+
+/* cy_capsense_commonConfig */
+#define CY_CAPSENSE_CPU_CLK_HZ_VALUE                                             (cy_capsense_context.ptrCommonConfig->cpuClkHz)
+#define CY_CAPSENSE_CPU_CLK_HZ_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->cpuClkHz))
+
+#define CY_CAPSENSE_PERI_CLK_HZ_VALUE                                            (cy_capsense_context.ptrCommonConfig->periClkHz)
+#define CY_CAPSENSE_PERI_CLK_HZ_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->periClkHz))
+
+#define CY_CAPSENSE_VDDA_VALUE                                                   (cy_capsense_context.ptrCommonConfig->vdda)
+#define CY_CAPSENSE_VDDA_SIZE                                                    (sizeof(cy_capsense_context.ptrCommonConfig->vdda))
+
+#define CY_CAPSENSE_NUM_PIN_VALUE                                                (cy_capsense_context.ptrCommonConfig->numPin)
+#define CY_CAPSENSE_NUM_PIN_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->numPin))
+
+#define CY_CAPSENSE_NUM_SNS_VALUE                                                (cy_capsense_context.ptrCommonConfig->numSns)
+#define CY_CAPSENSE_NUM_SNS_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->numSns))
+
+#define CY_CAPSENSE_NUM_WD_VALUE                                                 (cy_capsense_context.ptrCommonConfig->numWd)
+#define CY_CAPSENSE_NUM_WD_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->numWd))
+
+#define CY_CAPSENSE_CSD_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->csdEn)
+#define CY_CAPSENSE_CSD_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->csdEn))
+
+#define CY_CAPSENSE_CSX_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->csxEn)
+#define CY_CAPSENSE_CSX_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxEn))
+
+#if (CY_CAPSENSE_MW_VERSION < 300)
+#define CY_CAPSENSE_MFS_EN_VALUE                                                 (cy_capsense_context.ptrCommonConfig->mfsEn)
+#define CY_CAPSENSE_MFS_EN_SIZE                                                  (sizeof(cy_capsense_context.ptrCommonConfig->mfsEn))
+#endif
+
+#define CY_CAPSENSE_BIST_EN_VALUE                                                (cy_capsense_context.ptrCommonConfig->bistEn)
+#define CY_CAPSENSE_BIST_EN_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->bistEn))
+
+#define CY_CAPSENSE_POSITION_FILTER_EN_VALUE                                     (cy_capsense_context.ptrCommonConfig->positionFilterEn)
+#define CY_CAPSENSE_POSITION_FILTER_EN_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->positionFilterEn))
+
+#define CY_CAPSENSE_PERI_DIVIDER_TYPE_VALUE                                      (cy_capsense_context.ptrCommonConfig->periDividerType)
+#define CY_CAPSENSE_PERI_DIVIDER_TYPE_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->periDividerType))
+
+#define CY_CAPSENSE_PERI_DIVIDER_INDEX_VALUE                                     (cy_capsense_context.ptrCommonConfig->periDividerIndex)
+#define CY_CAPSENSE_PERI_DIVIDER_INDEX_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->periDividerIndex))
+
+#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_VALUE                                    (cy_capsense_context.ptrCommonConfig->analogWakeupDelay)
+#define CY_CAPSENSE_ANALOG_WAKEUP_DELAY_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->analogWakeupDelay))
+
+#define CY_CAPSENSE_SS_IREF_SOURCE_VALUE                                         (cy_capsense_context.ptrCommonConfig->ssIrefSource)
+#define CY_CAPSENSE_SS_IREF_SOURCE_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->ssIrefSource))
+
+#define CY_CAPSENSE_SS_VREF_SOURCE_VALUE                                         (cy_capsense_context.ptrCommonConfig->ssVrefSource)
+#define CY_CAPSENSE_SS_VREF_SOURCE_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->ssVrefSource))
+
+#define CY_CAPSENSE_PROX_TOUCH_COEFF_VALUE                                       (cy_capsense_context.ptrCommonConfig->proxTouchCoeff)
+#define CY_CAPSENSE_PROX_TOUCH_COEFF_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->proxTouchCoeff))
+
+#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_VALUE                                (cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn)
+#define CY_CAPSENSE_SW_SENSOR_AUTO_RESET_EN_SIZE                                 (sizeof(cy_capsense_context.ptrCommonConfig->swSensorAutoResetEn))
+
+#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_VALUE                                      (cy_capsense_context.ptrCommonConfig->portCmodPadNum)
+#define CY_CAPSENSE_PORT_CMOD_PAD_NUM_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->portCmodPadNum))
+
+#define CY_CAPSENSE_PIN_CMOD_PAD_VALUE                                           (cy_capsense_context.ptrCommonConfig->pinCmodPad)
+#define CY_CAPSENSE_PIN_CMOD_PAD_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->pinCmodPad))
+
+#define CY_CAPSENSE_PORT_CSH_PAD_NUM_VALUE                                       (cy_capsense_context.ptrCommonConfig->portCshPadNum)
+#define CY_CAPSENSE_PORT_CSH_PAD_NUM_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->portCshPadNum))
+
+#define CY_CAPSENSE_PIN_CSH_PAD_VALUE                                            (cy_capsense_context.ptrCommonConfig->pinCshPad)
+#define CY_CAPSENSE_PIN_CSH_PAD_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->pinCshPad))
+
+#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_VALUE                                    (cy_capsense_context.ptrCommonConfig->portShieldPadNum)
+#define CY_CAPSENSE_PORT_SHIELD_PAD_NUM_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->portShieldPadNum))
+
+#define CY_CAPSENSE_PIN_SHIELD_PAD_VALUE                                         (cy_capsense_context.ptrCommonConfig->pinShieldPad)
+#define CY_CAPSENSE_PIN_SHIELD_PAD_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->pinShieldPad))
+
+#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_VALUE                                  (cy_capsense_context.ptrCommonConfig->portVrefExtPadNum)
+#define CY_CAPSENSE_PORT_VREF_EXT_PAD_NUM_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->portVrefExtPadNum))
+
+#define CY_CAPSENSE_PIN_VREF_EXT_PAD_VALUE                                       (cy_capsense_context.ptrCommonConfig->pinVrefExtPad)
+#define CY_CAPSENSE_PIN_VREF_EXT_PAD_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->pinVrefExtPad))
+
+#define CY_CAPSENSE_PORT_CMOD_NUM_VALUE                                          (cy_capsense_context.ptrCommonConfig->portCmodNum)
+#define CY_CAPSENSE_PORT_CMOD_NUM_SIZE                                           (sizeof(cy_capsense_context.ptrCommonConfig->portCmodNum))
+
+#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_VALUE                                    (&cy_capsense_context.ptrCommonConfig->idacGainTable[0u])
+#define CY_CAPSENSE_IDAC_GAIN_TABLE_PTR_SIZE                                     (sizeof(&cy_capsense_context.ptrCommonConfig->idacGainTable[0u]))
+
+#define CY_CAPSENSE_PTR_CSD_BASE_VALUE                                           (cy_capsense_context.ptrCommonConfig->ptrCsdBase)
+#define CY_CAPSENSE_PTR_CSD_BASE_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdBase))
+
+#define CY_CAPSENSE_PTR_CSD_CONTEXT_VALUE                                        (cy_capsense_context.ptrCommonConfig->ptrCsdContext)
+#define CY_CAPSENSE_PTR_CSD_CONTEXT_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->ptrCsdContext))
+
+#define CY_CAPSENSE_PORT_CMOD_VALUE                                              (cy_capsense_context.ptrCommonConfig->portCmod)
+#define CY_CAPSENSE_PORT_CMOD_SIZE                                               (sizeof(cy_capsense_context.ptrCommonConfig->portCmod))
+
+#define CY_CAPSENSE_PORT_CSH_VALUE                                               (cy_capsense_context.ptrCommonConfig->portCsh)
+#define CY_CAPSENSE_PORT_CSH_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->portCsh))
+
+#define CY_CAPSENSE_PORT_CINT_A_VALUE                                            (cy_capsense_context.ptrCommonConfig->portCintA)
+#define CY_CAPSENSE_PORT_CINT_A_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->portCintA))
+
+#define CY_CAPSENSE_PORT_CINT_B_VALUE                                            (cy_capsense_context.ptrCommonConfig->portCintB)
+#define CY_CAPSENSE_PORT_CINT_B_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->portCintB))
+
+#define CY_CAPSENSE_PIN_CMOD_VALUE                                               (cy_capsense_context.ptrCommonConfig->pinCmod)
+#define CY_CAPSENSE_PIN_CMOD_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->pinCmod))
+
+#define CY_CAPSENSE_PORT_CSH_NUM_VALUE                                           (cy_capsense_context.ptrCommonConfig->portCshNum)
+#define CY_CAPSENSE_PORT_CSH_NUM_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->portCshNum))
+
+#define CY_CAPSENSE_PIN_CSH_VALUE                                                (cy_capsense_context.ptrCommonConfig->pinCsh)
+#define CY_CAPSENSE_PIN_CSH_SIZE                                                 (sizeof(cy_capsense_context.ptrCommonConfig->pinCsh))
+
+#define CY_CAPSENSE_PIN_CINT_A_VALUE                                             (cy_capsense_context.ptrCommonConfig->pinCintA)
+#define CY_CAPSENSE_PIN_CINT_A_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->pinCintA))
+
+#define CY_CAPSENSE_PIN_CINT_B_VALUE                                             (cy_capsense_context.ptrCommonConfig->pinCintB)
+#define CY_CAPSENSE_PIN_CINT_B_SIZE                                              (sizeof(cy_capsense_context.ptrCommonConfig->pinCintB))
+
+#define CY_CAPSENSE_CSD_SHIELD_EN_VALUE                                          (cy_capsense_context.ptrCommonConfig->csdShieldEn)
+#define CY_CAPSENSE_CSD_SHIELD_EN_SIZE                                           (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldEn))
+
+#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_VALUE                            (cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection)
+#define CY_CAPSENSE_CSD_INACTIVE_SNS_CONNECTION_SIZE                             (sizeof(cy_capsense_context.ptrCommonConfig->csdInactiveSnsConnection))
+
+#if (CY_CAPSENSE_MW_VERSION >= 300)
+#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_VALUE                            (cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection)
+#define CY_CAPSENSE_CSX_INACTIVE_SNS_CONNECTION_SIZE                             (sizeof(cy_capsense_context.ptrCommonConfig->csxInactiveSnsConnection))
+#endif
+
+#define CY_CAPSENSE_CSD_SHIELD_DELAY_VALUE                                       (cy_capsense_context.ptrCommonConfig->csdShieldDelay)
+#define CY_CAPSENSE_CSD_SHIELD_DELAY_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldDelay))
+
+#define CY_CAPSENSE_CSD_VREF_VALUE                                               (cy_capsense_context.ptrCommonConfig->csdVref)
+#define CY_CAPSENSE_CSD_VREF_SIZE                                                (sizeof(cy_capsense_context.ptrCommonConfig->csdVref))
+
+#define CY_CAPSENSE_CSD_R_CONST_VALUE                                            (cy_capsense_context.ptrCommonConfig->csdRConst)
+#define CY_CAPSENSE_CSD_R_CONST_SIZE                                             (sizeof(cy_capsense_context.ptrCommonConfig->csdRConst))
+
+#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_VALUE                                   (cy_capsense_context.ptrCommonConfig->csdCTankShieldEn)
+#define CY_CAPSENSE_CSD_C_TANK_SHIELD_EN_SIZE                                    (sizeof(cy_capsense_context.ptrCommonConfig->csdCTankShieldEn))
+
+#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_VALUE                                     (cy_capsense_context.ptrCommonConfig->csdShieldNumPin)
+#define CY_CAPSENSE_CSD_SHIELD_NUM_PIN_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldNumPin))
+
+#define CY_CAPSENSE_CSD_SHIELD_SW_RES_VALUE                                      (cy_capsense_context.ptrCommonConfig->csdShieldSwRes)
+#define CY_CAPSENSE_CSD_SHIELD_SW_RES_SIZE                                       (sizeof(cy_capsense_context.ptrCommonConfig->csdShieldSwRes))
+
+#define CY_CAPSENSE_CSD_INIT_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csdInitSwRes)
+#define CY_CAPSENSE_CSD_INIT_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csdInitSwRes))
+
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_VALUE                                    (cy_capsense_context.ptrCommonConfig->csdChargeTransfer)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csdChargeTransfer))
+
+#define CY_CAPSENSE_CSD_RAW_TARGET_VALUE                                         (cy_capsense_context.ptrCommonConfig->csdRawTarget)
+#define CY_CAPSENSE_CSD_RAW_TARGET_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->csdRawTarget))
+
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN_VALUE                                        (cy_capsense_context.ptrCommonConfig->csdAutotuneEn)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csdAutotuneEn))
+
+#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_VALUE                                    (cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn)
+#define CY_CAPSENSE_CSD_IDAC_AUTOCAL_EN_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutocalEn))
+
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_VALUE                                  (cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacAutoGainEn))
+
+#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_VALUE                                  (cy_capsense_context.ptrCommonConfig->csdCalibrationError)
+#define CY_CAPSENSE_CSD_CALIBRATION_ERROR_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csdCalibrationError))
+
+#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_VALUE                               (cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex)
+#define CY_CAPSENSE_CSD_IDAC_GAIN_INIT_INDEX_SIZE                                (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacGainInitIndex))
+
+#define CY_CAPSENSE_CSD_IDAC_MIN_VALUE                                           (cy_capsense_context.ptrCommonConfig->csdIdacMin)
+#define CY_CAPSENSE_CSD_IDAC_MIN_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacMin))
+
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN_VALUE                                       (cy_capsense_context.ptrCommonConfig->csdIdacCompEn)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN_SIZE                                        (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacCompEn))
+
+#define CY_CAPSENSE_CSD_FINE_INIT_TIME_VALUE                                     (cy_capsense_context.ptrCommonConfig->csdFineInitTime)
+#define CY_CAPSENSE_CSD_FINE_INIT_TIME_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csdFineInitTime))
+
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_VALUE                              (cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdIdacRowColAlignEn))
+
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_VALUE                              (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1)
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F1_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF1))
+
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_VALUE                              (cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2)
+#define CY_CAPSENSE_CSD_MFS_DIVIDER_OFFSET_F2_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csdMfsDividerOffsetF2))
+
+#define CY_CAPSENSE_CSX_RAW_TARGET_VALUE                                         (cy_capsense_context.ptrCommonConfig->csxRawTarget)
+#define CY_CAPSENSE_CSX_RAW_TARGET_SIZE                                          (sizeof(cy_capsense_context.ptrCommonConfig->csxRawTarget))
+
+#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_VALUE                               (cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex)
+#define CY_CAPSENSE_CSX_IDAC_GAIN_INIT_INDEX_SIZE                                (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacGainInitIndex))
+
+#define CY_CAPSENSE_CSX_REF_GAIN_VALUE                                           (cy_capsense_context.ptrCommonConfig->csxRefGain)
+#define CY_CAPSENSE_CSX_REF_GAIN_SIZE                                            (sizeof(cy_capsense_context.ptrCommonConfig->csxRefGain))
+
+#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_VALUE                                    (cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn)
+#define CY_CAPSENSE_CSX_IDAC_AUTOCAL_EN_SIZE                                     (sizeof(cy_capsense_context.ptrCommonConfig->csxIdacAutocalEn))
+
+#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_VALUE                                  (cy_capsense_context.ptrCommonConfig->csxCalibrationError)
+#define CY_CAPSENSE_CSX_CALIBRATION_ERROR_SIZE                                   (sizeof(cy_capsense_context.ptrCommonConfig->csxCalibrationError))
+
+#define CY_CAPSENSE_CSX_FINE_INIT_TIME_VALUE                                     (cy_capsense_context.ptrCommonConfig->csxFineInitTime)
+#define CY_CAPSENSE_CSX_FINE_INIT_TIME_SIZE                                      (sizeof(cy_capsense_context.ptrCommonConfig->csxFineInitTime))
+
+#define CY_CAPSENSE_CSX_INIT_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csxInitSwRes)
+#define CY_CAPSENSE_CSX_INIT_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csxInitSwRes))
+
+#define CY_CAPSENSE_CSX_SCAN_SW_RES_VALUE                                        (cy_capsense_context.ptrCommonConfig->csxScanSwRes)
+#define CY_CAPSENSE_CSX_SCAN_SW_RES_SIZE                                         (sizeof(cy_capsense_context.ptrCommonConfig->csxScanSwRes))
+
+#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_VALUE                                 (cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes)
+#define CY_CAPSENSE_CSX_INIT_SHIELD_SW_RES_SIZE                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxInitShieldSwRes))
+
+#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_VALUE                                 (cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes)
+#define CY_CAPSENSE_CSX_SCAN_SHIELD_SW_RES_SIZE                                  (sizeof(cy_capsense_context.ptrCommonConfig->csxScanShieldSwRes))
+
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_VALUE                              (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1)
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F1_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF1))
+
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_VALUE                              (cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2)
+#define CY_CAPSENSE_CSX_MFS_DIVIDER_OFFSET_F2_SIZE                               (sizeof(cy_capsense_context.ptrCommonConfig->csxMfsDividerOffsetF2))
+
+/* cy_capsense_widgetConfig */
+#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_VALUE                                 (cy_capsense_context.ptrWdConfig[0u].ptrWdContext)
+#define CY_CAPSENSE_BUTTON0_PTR_WD_CONTEXT_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrWdContext))
+#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_VALUE                                (cy_capsense_context.ptrWdConfig[0u].ptrSnsContext)
+#define CY_CAPSENSE_BUTTON0_PTR_SNS_CONTEXT_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrSnsContext))
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig)
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CONTEXT_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance)
+#define CY_CAPSENSE_BUTTON0_PTR_ELTD_CAPACITANCE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrEltdCapacitance))
+#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].ptrBslnInv)
+#define CY_CAPSENSE_BUTTON0_PTR_BSLN_INV_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBslnInv))
+#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_VALUE                             (cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_BUTTON0_PTR_NOISE_ENVELOPE_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_VALUE                     (cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_BUTTON0_PTR_RAW_FILTER_HISTORY_LOW_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_BUTTON0_IIR_COEFF_VALUE                                      (cy_capsense_context.ptrWdConfig[0u].iirCoeff)
+#define CY_CAPSENSE_BUTTON0_IIR_COEFF_SIZE                                       (sizeof(cy_capsense_context.ptrWdConfig[0u].iirCoeff))
+#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr)
+#define CY_CAPSENSE_BUTTON0_PTR_DEBOUNCE_ARR_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDebounceArr))
+#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable)
+#define CY_CAPSENSE_BUTTON0_PTR_DIPLEX_TABLE_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrDiplexTable))
+#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_VALUE                                (cy_capsense_context.ptrWdConfig[0u].centroidConfig)
+#define CY_CAPSENSE_BUTTON0_CENTROID_CONFIG_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[0u].centroidConfig))
+#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].xResolution)
+#define CY_CAPSENSE_BUTTON0_X_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].xResolution))
+#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].yResolution)
+#define CY_CAPSENSE_BUTTON0_Y_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].yResolution))
+#define CY_CAPSENSE_BUTTON0_NUM_SNS_VALUE                                        (cy_capsense_context.ptrWdConfig[0u].numSns)
+#define CY_CAPSENSE_BUTTON0_NUM_SNS_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[0u].numSns))
+#define CY_CAPSENSE_BUTTON0_NUM_COLS_VALUE                                       (cy_capsense_context.ptrWdConfig[0u].numCols)
+#define CY_CAPSENSE_BUTTON0_NUM_COLS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[0u].numCols))
+#define CY_CAPSENSE_BUTTON0_NUM_ROWS_VALUE                                       (cy_capsense_context.ptrWdConfig[0u].numRows)
+#define CY_CAPSENSE_BUTTON0_NUM_ROWS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[0u].numRows))
+#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_POS_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrPosFilterHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_VALUE                          (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_HISTORY_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_BUTTON0_PTR_CSX_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_BUTTON0_PTR_CSD_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_VALUE                             (cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig)
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONFIG_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_VALUE                            (cy_capsense_context.ptrWdConfig[0u].ptrGestureContext)
+#define CY_CAPSENSE_BUTTON0_PTR_GESTURE_CONTEXT_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrGestureContext))
+#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[0u].ballisticConfig)
+#define CY_CAPSENSE_BUTTON0_BALLISTIC_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[0u].ballisticConfig))
+#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext)
+#define CY_CAPSENSE_BUTTON0_PTR_BALLISTIC_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[0u].ptrBallisticContext))
+#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_VALUE                                    (cy_capsense_context.ptrWdConfig[0u].aiirConfig)
+#define CY_CAPSENSE_BUTTON0_AIIR_CONFIG_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[0u].aiirConfig))
+#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_VALUE                                     (cy_capsense_context.ptrWdConfig[0u].advConfig)
+#define CY_CAPSENSE_BUTTON0_ADV_CONFIG_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[0u].advConfig))
+#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[0u].posFilterConfig)
+#define CY_CAPSENSE_BUTTON0_POS_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[0u].posFilterConfig))
+#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[0u].rawFilterConfig)
+#define CY_CAPSENSE_BUTTON0_RAW_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[0u].rawFilterConfig))
+#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_VALUE                                   (cy_capsense_context.ptrWdConfig[0u].senseMethod)
+#define CY_CAPSENSE_BUTTON0_SENSE_METHOD_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0u].senseMethod))
+#define CY_CAPSENSE_BUTTON0_WD_TYPE_VALUE                                        (cy_capsense_context.ptrWdConfig[0u].wdType)
+#define CY_CAPSENSE_BUTTON0_WD_TYPE_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[0u].wdType))
+
+#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_VALUE                                 (cy_capsense_context.ptrWdConfig[1u].ptrWdContext)
+#define CY_CAPSENSE_BUTTON1_PTR_WD_CONTEXT_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrWdContext))
+#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_VALUE                                (cy_capsense_context.ptrWdConfig[1u].ptrSnsContext)
+#define CY_CAPSENSE_BUTTON1_PTR_SNS_CONTEXT_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrSnsContext))
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig)
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CONTEXT_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance)
+#define CY_CAPSENSE_BUTTON1_PTR_ELTD_CAPACITANCE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrEltdCapacitance))
+#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].ptrBslnInv)
+#define CY_CAPSENSE_BUTTON1_PTR_BSLN_INV_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBslnInv))
+#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_VALUE                             (cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_BUTTON1_PTR_NOISE_ENVELOPE_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_VALUE                     (cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_BUTTON1_PTR_RAW_FILTER_HISTORY_LOW_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_BUTTON1_IIR_COEFF_VALUE                                      (cy_capsense_context.ptrWdConfig[1u].iirCoeff)
+#define CY_CAPSENSE_BUTTON1_IIR_COEFF_SIZE                                       (sizeof(cy_capsense_context.ptrWdConfig[1u].iirCoeff))
+#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr)
+#define CY_CAPSENSE_BUTTON1_PTR_DEBOUNCE_ARR_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDebounceArr))
+#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable)
+#define CY_CAPSENSE_BUTTON1_PTR_DIPLEX_TABLE_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrDiplexTable))
+#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_VALUE                                (cy_capsense_context.ptrWdConfig[1u].centroidConfig)
+#define CY_CAPSENSE_BUTTON1_CENTROID_CONFIG_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[1u].centroidConfig))
+#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].xResolution)
+#define CY_CAPSENSE_BUTTON1_X_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].xResolution))
+#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].yResolution)
+#define CY_CAPSENSE_BUTTON1_Y_RESOLUTION_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].yResolution))
+#define CY_CAPSENSE_BUTTON1_NUM_SNS_VALUE                                        (cy_capsense_context.ptrWdConfig[1u].numSns)
+#define CY_CAPSENSE_BUTTON1_NUM_SNS_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[1u].numSns))
+#define CY_CAPSENSE_BUTTON1_NUM_COLS_VALUE                                       (cy_capsense_context.ptrWdConfig[1u].numCols)
+#define CY_CAPSENSE_BUTTON1_NUM_COLS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[1u].numCols))
+#define CY_CAPSENSE_BUTTON1_NUM_ROWS_VALUE                                       (cy_capsense_context.ptrWdConfig[1u].numRows)
+#define CY_CAPSENSE_BUTTON1_NUM_ROWS_SIZE                                        (sizeof(cy_capsense_context.ptrWdConfig[1u].numRows))
+#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_VALUE                         (cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_POS_FILTER_HISTORY_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrPosFilterHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_VALUE                          (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_HISTORY_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_BUTTON1_PTR_CSX_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_VALUE                           (cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_BUTTON1_PTR_CSD_TOUCH_BUFFER_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_VALUE                             (cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig)
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONFIG_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_VALUE                            (cy_capsense_context.ptrWdConfig[1u].ptrGestureContext)
+#define CY_CAPSENSE_BUTTON1_PTR_GESTURE_CONTEXT_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrGestureContext))
+#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[1u].ballisticConfig)
+#define CY_CAPSENSE_BUTTON1_BALLISTIC_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[1u].ballisticConfig))
+#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext)
+#define CY_CAPSENSE_BUTTON1_PTR_BALLISTIC_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[1u].ptrBallisticContext))
+#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_VALUE                                    (cy_capsense_context.ptrWdConfig[1u].aiirConfig)
+#define CY_CAPSENSE_BUTTON1_AIIR_CONFIG_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[1u].aiirConfig))
+#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_VALUE                                     (cy_capsense_context.ptrWdConfig[1u].advConfig)
+#define CY_CAPSENSE_BUTTON1_ADV_CONFIG_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[1u].advConfig))
+#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[1u].posFilterConfig)
+#define CY_CAPSENSE_BUTTON1_POS_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[1u].posFilterConfig))
+#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[1u].rawFilterConfig)
+#define CY_CAPSENSE_BUTTON1_RAW_FILTER_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[1u].rawFilterConfig))
+#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_VALUE                                   (cy_capsense_context.ptrWdConfig[1u].senseMethod)
+#define CY_CAPSENSE_BUTTON1_SENSE_METHOD_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1u].senseMethod))
+#define CY_CAPSENSE_BUTTON1_WD_TYPE_VALUE                                        (cy_capsense_context.ptrWdConfig[1u].wdType)
+#define CY_CAPSENSE_BUTTON1_WD_TYPE_SIZE                                         (sizeof(cy_capsense_context.ptrWdConfig[1u].wdType))
+
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_VALUE                           (cy_capsense_context.ptrWdConfig[2u].ptrWdContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_WD_CONTEXT_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrWdContext))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_VALUE                          (cy_capsense_context.ptrWdConfig[2u].ptrSnsContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_SNS_CONTEXT_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrSnsContext))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CONTEXT_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_ELTD_CAPACITANCE_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrEltdCapacitance))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_VALUE                             (cy_capsense_context.ptrWdConfig[2u].ptrBslnInv)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BSLN_INV_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBslnInv))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_VALUE                       (cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_NOISE_ENVELOPE_SIZE                        (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrNoiseEnvelope))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_VALUE                   (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_SIZE                    (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_VALUE               (cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_RAW_FILTER_HISTORY_LOW_SIZE                (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrRawFilterHistoryLow))
+#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_VALUE                                (cy_capsense_context.ptrWdConfig[2u].iirCoeff)
+#define CY_CAPSENSE_LINEARSLIDER0_IIR_COEFF_SIZE                                 (sizeof(cy_capsense_context.ptrWdConfig[2u].iirCoeff))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DEBOUNCE_ARR_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDebounceArr))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_DIPLEX_TABLE_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrDiplexTable))
+#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_VALUE                          (cy_capsense_context.ptrWdConfig[2u].centroidConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_CENTROID_CONFIG_SIZE                           (sizeof(cy_capsense_context.ptrWdConfig[2u].centroidConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_VALUE                             (cy_capsense_context.ptrWdConfig[2u].xResolution)
+#define CY_CAPSENSE_LINEARSLIDER0_X_RESOLUTION_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].xResolution))
+#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_VALUE                             (cy_capsense_context.ptrWdConfig[2u].yResolution)
+#define CY_CAPSENSE_LINEARSLIDER0_Y_RESOLUTION_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].yResolution))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_VALUE                                  (cy_capsense_context.ptrWdConfig[2u].numSns)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_SNS_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[2u].numSns))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_VALUE                                 (cy_capsense_context.ptrWdConfig[2u].numCols)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_COLS_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[2u].numCols))
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_VALUE                                 (cy_capsense_context.ptrWdConfig[2u].numRows)
+#define CY_CAPSENSE_LINEARSLIDER0_NUM_ROWS_SIZE                                  (sizeof(cy_capsense_context.ptrWdConfig[2u].numRows))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_VALUE                   (cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_POS_FILTER_HISTORY_SIZE                    (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrPosFilterHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_VALUE                    (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_HISTORY_SIZE                     (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchHistory))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSX_TOUCH_BUFFER_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsxTouchBuffer))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_VALUE                     (cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_CSD_TOUCH_BUFFER_SIZE                      (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrCsdTouchBuffer))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_VALUE                       (cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONFIG_SIZE                        (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_VALUE                      (cy_capsense_context.ptrWdConfig[2u].ptrGestureContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_GESTURE_CONTEXT_SIZE                       (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrGestureContext))
+#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_VALUE                         (cy_capsense_context.ptrWdConfig[2u].ballisticConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_BALLISTIC_CONFIG_SIZE                          (sizeof(cy_capsense_context.ptrWdConfig[2u].ballisticConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_VALUE                    (cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext)
+#define CY_CAPSENSE_LINEARSLIDER0_PTR_BALLISTIC_CONTEXT_SIZE                     (sizeof(cy_capsense_context.ptrWdConfig[2u].ptrBallisticContext))
+#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_VALUE                              (cy_capsense_context.ptrWdConfig[2u].aiirConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_AIIR_CONFIG_SIZE                               (sizeof(cy_capsense_context.ptrWdConfig[2u].aiirConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_VALUE                               (cy_capsense_context.ptrWdConfig[2u].advConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_ADV_CONFIG_SIZE                                (sizeof(cy_capsense_context.ptrWdConfig[2u].advConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_VALUE                        (cy_capsense_context.ptrWdConfig[2u].posFilterConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_POS_FILTER_CONFIG_SIZE                         (sizeof(cy_capsense_context.ptrWdConfig[2u].posFilterConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_VALUE                        (cy_capsense_context.ptrWdConfig[2u].rawFilterConfig)
+#define CY_CAPSENSE_LINEARSLIDER0_RAW_FILTER_CONFIG_SIZE                         (sizeof(cy_capsense_context.ptrWdConfig[2u].rawFilterConfig))
+#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_VALUE                             (cy_capsense_context.ptrWdConfig[2u].senseMethod)
+#define CY_CAPSENSE_LINEARSLIDER0_SENSE_METHOD_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2u].senseMethod))
+#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_VALUE                                  (cy_capsense_context.ptrWdConfig[2u].wdType)
+#define CY_CAPSENSE_LINEARSLIDER0_WD_TYPE_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[2u].wdType))
+
+/* cy_capsense_pinConfig */
+#define CY_CAPSENSE_BUTTON0_RX0_PIN0_PC_PTR_VALUE                                (cy_capsense_context.ptrPinConfig[0].pcPtr)
+#define CY_CAPSENSE_BUTTON0_RX0_PIN0_PC_PTR_SIZE                                 (sizeof(cy_capsense_context.ptrPinConfig[0].pcPtr))
+#define CY_CAPSENSE_BUTTON0_RX0_PIN0_NUMBER_VALUE                                (cy_capsense_context.ptrPinConfig[0].pinNumber)
+#define CY_CAPSENSE_BUTTON0_RX0_PIN0_NUMBER_SIZE                                 (sizeof(cy_capsense_context.ptrPinConfig[0].pinNumber))
+
+#define CY_CAPSENSE_BUTTON0_TX_PIN0_PC_PTR_VALUE                                 (cy_capsense_context.ptrPinConfig[1].pcPtr)
+#define CY_CAPSENSE_BUTTON0_TX_PIN0_PC_PTR_SIZE                                  (sizeof(cy_capsense_context.ptrPinConfig[1].pcPtr))
+#define CY_CAPSENSE_BUTTON0_TX_PIN0_NUMBER_VALUE                                 (cy_capsense_context.ptrPinConfig[1].pinNumber)
+#define CY_CAPSENSE_BUTTON0_TX_PIN0_NUMBER_SIZE                                  (sizeof(cy_capsense_context.ptrPinConfig[1].pinNumber))
+
+#define CY_CAPSENSE_BUTTON1_RX0_PIN0_PC_PTR_VALUE                                (cy_capsense_context.ptrPinConfig[2].pcPtr)
+#define CY_CAPSENSE_BUTTON1_RX0_PIN0_PC_PTR_SIZE                                 (sizeof(cy_capsense_context.ptrPinConfig[2].pcPtr))
+#define CY_CAPSENSE_BUTTON1_RX0_PIN0_NUMBER_VALUE                                (cy_capsense_context.ptrPinConfig[2].pinNumber)
+#define CY_CAPSENSE_BUTTON1_RX0_PIN0_NUMBER_SIZE                                 (sizeof(cy_capsense_context.ptrPinConfig[2].pinNumber))
+
+#define CY_CAPSENSE_BUTTON1_TX_PIN0_PC_PTR_VALUE                                 (cy_capsense_context.ptrPinConfig[3].pcPtr)
+#define CY_CAPSENSE_BUTTON1_TX_PIN0_PC_PTR_SIZE                                  (sizeof(cy_capsense_context.ptrPinConfig[3].pcPtr))
+#define CY_CAPSENSE_BUTTON1_TX_PIN0_NUMBER_VALUE                                 (cy_capsense_context.ptrPinConfig[3].pinNumber)
+#define CY_CAPSENSE_BUTTON1_TX_PIN0_NUMBER_SIZE                                  (sizeof(cy_capsense_context.ptrPinConfig[3].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[4].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[4].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[4].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[4].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[5].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[5].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[5].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[5].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[6].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[6].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[6].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[6].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[7].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[7].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[7].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[7].pinNumber))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_VALUE                         (cy_capsense_context.ptrPinConfig[8].pcPtr)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_PC_PTR_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[8].pcPtr))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_VALUE                         (cy_capsense_context.ptrPinConfig[8].pinNumber)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_PIN0_NUMBER_SIZE                          (sizeof(cy_capsense_context.ptrPinConfig[8].pinNumber))
+
+/* cy_capsense_electrodeConfig */
+#define CY_CAPSENSE_BUTTON0_RX0_CFG_PTR_VALUE                                    (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_BUTTON0_RX0_CFG_PTR_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_BUTTON0_RX0_ELTD_TYPE_VALUE                                  (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_BUTTON0_RX0_ELTD_TYPE_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_BUTTON0_RX0_NUM_PINS_VALUE                                   (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_BUTTON0_RX0_NUM_PINS_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_BUTTON0_TX_CFG_PTR_VALUE                                     (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].ptrPin)
+#define CY_CAPSENSE_BUTTON0_TX_CFG_PTR_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].ptrPin))
+#define CY_CAPSENSE_BUTTON0_TX_ELTD_TYPE_VALUE                                   (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].type)
+#define CY_CAPSENSE_BUTTON0_TX_ELTD_TYPE_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].type))
+#define CY_CAPSENSE_BUTTON0_TX_NUM_PINS_VALUE                                    (cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].numPins)
+#define CY_CAPSENSE_BUTTON0_TX_NUM_PINS_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[0].ptrEltdConfig[1].numPins))
+
+#define CY_CAPSENSE_BUTTON1_RX0_CFG_PTR_VALUE                                    (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_BUTTON1_RX0_CFG_PTR_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_BUTTON1_RX0_ELTD_TYPE_VALUE                                  (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_BUTTON1_RX0_ELTD_TYPE_SIZE                                   (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_BUTTON1_RX0_NUM_PINS_VALUE                                   (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_BUTTON1_RX0_NUM_PINS_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_BUTTON1_TX_CFG_PTR_VALUE                                     (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].ptrPin)
+#define CY_CAPSENSE_BUTTON1_TX_CFG_PTR_SIZE                                      (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].ptrPin))
+#define CY_CAPSENSE_BUTTON1_TX_ELTD_TYPE_VALUE                                   (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].type)
+#define CY_CAPSENSE_BUTTON1_TX_ELTD_TYPE_SIZE                                    (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].type))
+#define CY_CAPSENSE_BUTTON1_TX_NUM_PINS_VALUE                                    (cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].numPins)
+#define CY_CAPSENSE_BUTTON1_TX_NUM_PINS_SIZE                                     (sizeof(cy_capsense_context.ptrWdConfig[1].ptrEltdConfig[1].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS0_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[0].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS1_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[1].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS2_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[2].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS3_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[3].numPins))
+
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_VALUE                             (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_CFG_PTR_SIZE                              (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].ptrPin))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_VALUE                           (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_ELTD_TYPE_SIZE                            (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].type))
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_VALUE                            (cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins)
+#define CY_CAPSENSE_LINEARSLIDER0_SNS4_NUM_PINS_SIZE                             (sizeof(cy_capsense_context.ptrWdConfig[2].ptrEltdConfig[4].numPins))
+
+
+#if ((CY_CAPSENSE_PERI_CLK / 2) > 50000000)
+    #warning The maximum CSD modulator clock frequency is 50 MHz: increase CSD modulator clock divider to meet the valid operation conditions
+#endif
+
+#if ((CY_CAPSENSE_PERI_CLK / 2) > 50000000)
+    #warning The maximum CSX modulator clock frequency is 50 MHz: increase CSX modulator clock divider to meet the valid operation conditions
+#endif
+
+#if ((CY_CAPSENSE_PERI_CLK / 2 / 32) > 3000000)
+    #warning The maximum Tx clock frequency is 3 MHz: increase Tx clock divider for widget Button0 to meet the valid operation conditions
+#endif
+
+#if ((CY_CAPSENSE_PERI_CLK / 2 / 32) > 3000000)
+    #warning The maximum Tx clock frequency is 3 MHz: increase Tx clock divider for widget Button1 to meet the valid operation conditions
+#endif
+
+
+
+#if (CY_CAPSENSE_BIST_SUPPORTED)
+#if (CY_CAPSENSE_BIST_EN != 0)
+    extern uint32_t cy_capsense_eltdCap[];
+    #if (CY_CAPSENSE_MW_VERSION >= 300)
+        extern uint32_t cy_capsense_snsCap[];
+    #endif
+    extern uint16_t cy_capsense_bslnInv[];
+#endif
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* CY_CAPSENSE_CORE == __CORTEX_M */
+
+#endif /* !defined(CY_DISABLE_CAPSENSE) */
+
+#endif /* CYCFG_CAPSENSE_H */
+
+/* [] END OF FILE */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_defines.h

@@ -0,0 +1,140 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_defines.h
+*
+* Description:
+* CAPSENSE configuration defines.
+*
+* Note: This file is required for the CAPSENSE Middleware Library to build
+* successfully.
+*
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.6195
+*
+********************************************************************************
+* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_DEFINES_H)
+#define CYCFG_CAPSENSE_DEFINES_H
+
+#include <stddef.h>
+
+/* General */
+#define CY_CAPSENSE_WIDGET_COUNT                                                 (3u)
+#define CY_CAPSENSE_SENSOR_COUNT                                                 (7u)
+#define CY_CAPSENSE_ELTD_COUNT                                                   (9u)
+#define CY_CAPSENSE_PIN_COUNT                                                    (9u)
+#define CY_CAPSENSE_SHIELD_PIN_COUNT                                             (0u)
+#define CY_CAPSENSE_POSITION_SIZE                                                (1u)
+#define CY_CAPSENSE_DEBOUNCE_SIZE                                                (3u)
+#define CY_CAPSENSE_NOISE_ENVELOPE_SIZE                                          (5u)
+#define CY_CAPSENSE_MFS_CH_NUMBER                                                (1u)
+#define CY_CAPSENSE_RAW_HISTORY_SIZE                                             (0u)
+#define CY_CAPSENSE_IIR_HISTORY_LOW_SIZE                                         (0u)
+#define CY_CAPSENSE_POSITION_FILTER_HISTORY_SIZE                                 (0u)
+#define CY_CAPSENSE_TOUCH_FILTER_HISTORY_SIZE                                    (0u)
+#define CY_CAPSENSE_DIPLEX_SIZE                                                  (0u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_MAX_SENSORS_SIZE                                (0u)
+#define CY_CAPSENSE_CSX_TOUCH_BUFFER_ENABLE                                      (0u)
+#define CY_CAPSENSE_CSX_TOUCH_HISTORY_SIZE                                       (0u)
+#define CY_CAPSENSE_BALLISTIC_WIDGET_COUNT                                       (0u)
+#define CY_CAPSENSE_GESTURE_WIDGET_COUNT                                         (0u)
+
+/* Sensing Methods */
+#define CY_CAPSENSE_CSD_EN                                                       (1u)
+#define CY_CAPSENSE_CSX_EN                                                       (1u)
+#define CY_CAPSENSE_CSD_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_CSX_CALIBRATION_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_FULL_EN                                           (1u)
+#define CY_CAPSENSE_SMARTSENSE_HW_EN                                             (0u)
+#define CY_CAPSENSE_SMARTSENSE_DISABLED                                          (0u)
+#define CY_CAPSENSE_CSD_AUTOTUNE_EN                                              (CY_CAPSENSE_SMARTSENSE_FULL_EN || CY_CAPSENSE_SMARTSENSE_HW_EN)
+#define CY_CAPSENSE_CSD_SHIELD_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SHIELD_CAP_EN                                            (0u)
+#define CY_CAPSENSE_CSD_CHARGE_TRANSFER                                          (CY_CAPSENSE_IDAC_SOURCING)
+#define CY_CAPSENSE_CSD_IDAC_COMP_EN                                             (1u)
+#define CY_CAPSENSE_CSD_IDAC_AUTO_GAIN_EN                                        (1u)
+#define CY_CAPSENSE_CSD_IDAC_ROW_COL_ALIGN_EN                                    (1u)
+#define CY_CAPSENSE_LFSR_EN                                                      (1u)
+#define CY_CAPSENSE_LFSR_AUTO_EN                                                 (1u)
+#define CY_CAPSENSE_CLOCK_SOURCE_AUTO_EN                                         (1u)
+
+/* Filtering */
+#define CY_CAPSENSE_ADAPTIVE_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_BALLISTIC_MULTIPLIER_EN                                      (0u)
+#define CY_CAPSENSE_RAWCOUNT_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN                                  (0u)
+#define CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN                                 (0u)
+#define CY_CAPSENSE_REGULAR_RC_FILTER_EN                                         (CY_CAPSENSE_REGULAR_RC_IIR_FILTER_EN || CY_CAPSENSE_REGULAR_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_REGULAR_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_PROX_RC_IIR_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN                                     (0u)
+#define CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN                                    (0u)
+#define CY_CAPSENSE_PROX_RC_FILTER_EN                                            (CY_CAPSENSE_PROX_RC_IIR_FILTER_EN || CY_CAPSENSE_PROX_RC_MEDIAN_FILTER_EN || CY_CAPSENSE_PROX_RC_AVERAGE_FILTER_EN)
+#define CY_CAPSENSE_POSITION_FILTER_EN                                           (0u)
+#define CY_CAPSENSE_CSD_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_CSX_POSITION_FILTER_EN                                       (0u)
+#define CY_CAPSENSE_POS_IIR_FILTER_EN                                            (0u)
+#define CY_CAPSENSE_POS_MEDIAN_FILTER_EN                                         (0u)
+#define CY_CAPSENSE_POS_AVERAGE_FILTER_EN                                        (0u)
+#define CY_CAPSENSE_POS_JITTER_FILTER_EN                                         (0u)
+
+/* Widgets */
+#define CY_CAPSENSE_CSD_BUTTON_EN                                                (0u)
+#define CY_CAPSENSE_CSD_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSD_SLIDER_EN                                                (1u)
+#define CY_CAPSENSE_CSD_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_CSD_PROXIMITY_EN                                             (0u)
+#define CY_CAPSENSE_CSX_BUTTON_EN                                                (1u)
+#define CY_CAPSENSE_CSX_SLIDER_EN                                                (0u)
+#define CY_CAPSENSE_CSX_MATRIX_EN                                                (0u)
+#define CY_CAPSENSE_CSX_TOUCHPAD_EN                                              (0u)
+#define CY_CAPSENSE_ADVANCED_CENTROID_5X5_EN                                     (0u)
+#define CY_CAPSENSE_CSD_LINEAR_SLIDER_EN                                         (1u)
+#define CY_CAPSENSE_CSD_RADIAL_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSD_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_LINEAR_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_CSX_DIPLEX_SLIDER_EN                                         (0u)
+#define CY_CAPSENSE_GANGED_SNS_EN                                                (0u)
+#define CY_CAPSENSE_CSD_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_CSX_GANGED_SNS_EN                                            (0u)
+#define CY_CAPSENSE_BUTTON_EN                                                    (1u)
+#define CY_CAPSENSE_MATRIX_EN                                                    (0u)
+#define CY_CAPSENSE_SLIDER_EN                                                    (1u)
+#define CY_CAPSENSE_TOUCHPAD_EN                                                  (0u)
+
+/* Features */
+#define CY_CAPSENSE_GESTURE_EN                                                   (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_SCAN_EN                                      (0u)
+#define CY_CAPSENSE_MULTI_FREQUENCY_WIDGET_EN                                    (0u)
+#define CY_CAPSENSE_SNS_AUTO_RESET_EN                                            (0u)
+
+/* Self-test */
+#define CY_CAPSENSE_BIST_EN                                                      (0u)
+#define CY_CAPSENSE_TST_WDGT_CRC_EN                                              (0u)
+#define CY_CAPSENSE_TST_BSLN_INTEGRITY_EN                                        (0u)
+#define CY_CAPSENSE_TST_RAW_INTEGRITY_EN                                         (0u)
+#define CY_CAPSENSE_TST_SNS_SHORT_EN                                             (0u)
+#define CY_CAPSENSE_TST_SNS_CAP_EN                                               (0u)
+#define CY_CAPSENSE_TST_SH_CAP_EN                                                (0u)
+#define CY_CAPSENSE_TST_EXTERNAL_CAP_EN                                          (0u)
+#define CY_CAPSENSE_TST_VDDA_EN                                                  (0u)
+
+
+#endif /* CYCFG_CAPSENSE_DEFINES_H */
+
+/* [] END OF FILE */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense_tuner_regmap.h

@@ -0,0 +1,973 @@
+/*******************************************************************************
+* File Name: cycfg_capsense_tuner_regmap.h
+*
+* Description:
+* CAPSENSE Tuner register map configuration.
+* This file should not be modified. It was automatically generated by
+* CapSense Configurator 4.0.0.6195
+*
+********************************************************************************
+* Copyright 2022, Cypress Semiconductor Corporation (an Infineon company)
+* or an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*******************************************************************************/
+
+#if !defined(CYCFG_CAPSENSE_TUNER_REGMAP_H)
+#define CYCFG_CAPSENSE_TUNER_REGMAP_H
+
+#include "cy_capsense_common.h"
+
+#if !defined(CY_CAPSENSE_MW_VERSION)
+    #define CY_CAPSENSE_TUNER_MW_VERSION (200)
+#else
+    #define CY_CAPSENSE_TUNER_MW_VERSION (CY_CAPSENSE_MW_VERSION)
+#endif
+
+/* RAM Data structure register definitions */
+#if (CY_CAPSENSE_TUNER_MW_VERSION < 300)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE                                            (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_TUNER_INITDONE_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_OFFSET                                         (8u)
+#define CY_CAPSENSE_TUNER_PTRSSCALLBACK_SIZE                                           (4u)
+
+#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_OFFSET                                        (12u)
+#define CY_CAPSENSE_TUNER_PTREOSCALLBACK_SIZE                                          (4u)
+
+#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_OFFSET                                  (16u)
+#define CY_CAPSENSE_TUNER_PTRTUNERSENDCALLBACK_SIZE                                    (4u)
+
+#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_OFFSET                               (20u)
+#define CY_CAPSENSE_TUNER_PTRTUNERRECEIVECALLBACK_SIZE                                 (4u)
+
+#define CY_CAPSENSE_TUNER_STATUS_OFFSET                                                (24u)
+#define CY_CAPSENSE_TUNER_STATUS_SIZE                                                  (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET                                     (28u)
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE                                       (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET                                             (32u)
+#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE                                               (4u)
+
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET                                   (36u)
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET                                   (37u)
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (38u)
+#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (40u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (42u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_OFFSET                                      (44u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET                                   (46u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (48u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (50u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (52u)
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_OFFSET                                        (54u)
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (56u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (58u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (60u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (62u)
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (64u)
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (66u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (67u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (68u)
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (69u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_OFFSET                                 (70u)
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (71u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (72u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (73u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (74u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (75u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (76u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (77u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (78u)
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (79u)
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (80u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (84u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (88u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (90u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_OFFSET                                      (92u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET                                   (94u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (96u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (98u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (100u)
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_OFFSET                                        (102u)
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (104u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (106u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (108u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (110u)
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (112u)
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (114u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (115u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (116u)
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (117u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_OFFSET                                 (118u)
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (119u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (120u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (121u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (122u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (123u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (124u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (125u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (126u)
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (127u)
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (163u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (165u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (167u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (169u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_OFFSET                                      (184u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_OFFSET                                     (186u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_OFFSET                                     (188u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_OFFSET                                   (190u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (191u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_OFFSET                                     (192u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_OFFSET                                 (193u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_OFFSET                                      (194u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_OFFSET                                     (196u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_OFFSET                                     (198u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_OFFSET                                   (200u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (201u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_OFFSET                                     (202u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_OFFSET                                 (203u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (204u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (206u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (208u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (210u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (211u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (213u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (223u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (233u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (243u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (253u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
+
+#else /* CY_CAPSENSE_TUNER_MW_VERSION >= 300 */
+#define CY_CAPSENSE_TUNER_CONFIG_ID_OFFSET                                             (0u)
+#define CY_CAPSENSE_TUNER_CONFIG_ID_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CMD_OFFSET                                             (2u)
+#define CY_CAPSENSE_TUNER_TUNER_CMD_SIZE                                               (2u)
+
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_OFFSET                                          (4u)
+#define CY_CAPSENSE_TUNER_SCAN_COUNTER_SIZE                                            (2u)
+
+#define CY_CAPSENSE_TUNER_TUNER_ST_OFFSET                                              (6u)
+#define CY_CAPSENSE_TUNER_TUNER_ST_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_INITDONE_OFFSET                                              (7u)
+#define CY_CAPSENSE_TUNER_INITDONE_SIZE                                                (1u)
+
+#define CY_CAPSENSE_TUNER_STATUS_OFFSET                                                (8u)
+#define CY_CAPSENSE_TUNER_STATUS_SIZE                                                  (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_OFFSET                                     (12u)
+#define CY_CAPSENSE_TUNER_TIMESTAMPINTERVAL_SIZE                                       (4u)
+
+#define CY_CAPSENSE_TUNER_TIMESTAMP_OFFSET                                             (16u)
+#define CY_CAPSENSE_TUNER_TIMESTAMP_SIZE                                               (4u)
+
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_OFFSET                                   (20u)
+#define CY_CAPSENSE_TUNER_CSD_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_OFFSET                                   (21u)
+#define CY_CAPSENSE_TUNER_CSX_MOD_CLK_DIVIDER_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_TUNER_CNT_OFFSET                                             (22u)
+#define CY_CAPSENSE_TUNER_TUNER_CNT_SIZE                                               (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_OFFSET                                     (24u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_OFFSET                                        (26u)
+#define CY_CAPSENSE_TUNER_BUTTON0_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_OFFSET                                      (28u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_CONV_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_OFFSET                                   (30u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_OFFSET                                (32u)
+#define CY_CAPSENSE_TUNER_BUTTON0_MAXRAWCOUNTROW_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_OFFSET                                     (34u)
+#define CY_CAPSENSE_TUNER_BUTTON0_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_OFFSET                                 (36u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_OFFSET                                  (38u)
+#define CY_CAPSENSE_TUNER_BUTTON0_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_OFFSET                                        (40u)
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_OFFSET                                   (42u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_OFFSET                              (44u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_OFFSET                             (46u)
+#define CY_CAPSENSE_TUNER_BUTTON0_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_OFFSET                                        (48u)
+#define CY_CAPSENSE_TUNER_BUTTON0_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_OFFSET                                        (50u)
+#define CY_CAPSENSE_TUNER_BUTTON0_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_OFFSET                                      (52u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NOISE_TH_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_OFFSET                                     (54u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NNOISE_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_OFFSET                                    (56u)
+#define CY_CAPSENSE_TUNER_BUTTON0_HYSTERESIS_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_OFFSET                                   (58u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_OFFSET                                 (59u)
+#define CY_CAPSENSE_TUNER_BUTTON0_TX_CLK_SOURCE_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_OFFSET                                     (60u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_OFFSET                                     (61u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_OFFSET                                     (62u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_OFFSET                               (63u)
+#define CY_CAPSENSE_TUNER_BUTTON0_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_OFFSET                                 (64u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_OFFSET                                 (65u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_OFFSET                                 (66u)
+#define CY_CAPSENSE_TUNER_BUTTON0_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_OFFSET                              (67u)
+#define CY_CAPSENSE_TUNER_BUTTON0_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_OFFSET                                        (68u)
+#define CY_CAPSENSE_TUNER_BUTTON0_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_OFFSET                                   (72u)
+#define CY_CAPSENSE_TUNER_BUTTON0_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_OFFSET                                 (76u)
+#define CY_CAPSENSE_TUNER_BUTTON0_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_OFFSET                                     (80u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_CP_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_OFFSET                                        (82u)
+#define CY_CAPSENSE_TUNER_BUTTON1_SIGPFC_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_OFFSET                                      (84u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_CONV_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_OFFSET                                   (86u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNT_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_OFFSET                                (88u)
+#define CY_CAPSENSE_TUNER_BUTTON1_MAXRAWCOUNTROW_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_OFFSET                                     (90u)
+#define CY_CAPSENSE_TUNER_BUTTON1_FINGER_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_OFFSET                                 (92u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PROX_TOUCH_TH_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_OFFSET                                  (94u)
+#define CY_CAPSENSE_TUNER_BUTTON1_LOW_BSLN_RST_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_OFFSET                                        (96u)
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_OFFSET                                   (98u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_SNS_CLK_SIZE                                     (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_OFFSET                              (100u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DETECTED_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_OFFSET                             (102u)
+#define CY_CAPSENSE_TUNER_BUTTON1_GESTURE_DIRECTION_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_OFFSET                                        (104u)
+#define CY_CAPSENSE_TUNER_BUTTON1_XDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_OFFSET                                        (106u)
+#define CY_CAPSENSE_TUNER_BUTTON1_YDELTA_SIZE                                          (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_OFFSET                                      (108u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NOISE_TH_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_OFFSET                                     (110u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NNOISE_TH_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_OFFSET                                    (112u)
+#define CY_CAPSENSE_TUNER_BUTTON1_HYSTERESIS_SIZE                                      (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_OFFSET                                   (114u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ON_DEBOUNCE_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_OFFSET                                 (115u)
+#define CY_CAPSENSE_TUNER_BUTTON1_TX_CLK_SOURCE_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_OFFSET                                     (116u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_OFFSET                                     (117u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD1_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_OFFSET                                     (118u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_MOD2_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_OFFSET                               (119u)
+#define CY_CAPSENSE_TUNER_BUTTON1_IDAC_GAIN_INDEX_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_OFFSET                                 (120u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_OFFSET                                 (121u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD1_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_OFFSET                                 (122u)
+#define CY_CAPSENSE_TUNER_BUTTON1_ROW_IDAC_MOD2_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_OFFSET                              (123u)
+#define CY_CAPSENSE_TUNER_BUTTON1_REGULAR_IIR_BL_N_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_OFFSET                                        (124u)
+#define CY_CAPSENSE_TUNER_BUTTON1_STATUS_SIZE                                          (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_OFFSET                                   (128u)
+#define CY_CAPSENSE_TUNER_BUTTON1_PTRPOSITION_SIZE                                     (4u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_OFFSET                                 (132u)
+#define CY_CAPSENSE_TUNER_BUTTON1_NUM_POSITIONS_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_OFFSET                               (136u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_CP_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_OFFSET                                  (138u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SIGPFC_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_OFFSET                              (140u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_RESOLUTION_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_OFFSET                             (142u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNT_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_OFFSET                          (144u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_MAXRAWCOUNTROW_SIZE                            (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_OFFSET                               (146u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_FINGER_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_OFFSET                           (148u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PROX_TOUCH_TH_SIZE                             (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_OFFSET                            (150u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_LOW_BSLN_RST_SIZE                              (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_OFFSET                                 (152u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SIZE                                   (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_OFFSET                             (154u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_SNS_CLK_SIZE                               (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_OFFSET                        (156u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DETECTED_SIZE                          (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_OFFSET                       (158u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_GESTURE_DIRECTION_SIZE                         (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_OFFSET                                  (160u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_XDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_OFFSET                                  (162u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_YDELTA_SIZE                                    (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_OFFSET                                (164u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NOISE_TH_SIZE                                  (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_OFFSET                               (166u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NNOISE_TH_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_OFFSET                              (168u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_HYSTERESIS_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_OFFSET                             (170u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ON_DEBOUNCE_SIZE                               (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_OFFSET                          (171u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS_CLK_SOURCE_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_OFFSET                               (172u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD0_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_OFFSET                               (173u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD1_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_OFFSET                               (174u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_MOD2_SIZE                                 (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_OFFSET                         (175u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_IDAC_GAIN_INDEX_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_OFFSET                           (176u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD0_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_OFFSET                           (177u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD1_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_OFFSET                           (178u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ROW_IDAC_MOD2_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_OFFSET                        (179u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_REGULAR_IIR_BL_N_SIZE                          (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_OFFSET                                  (180u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_STATUS_SIZE                                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_OFFSET                             (184u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_PTRPOSITION_SIZE                               (4u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_OFFSET                           (188u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_NUM_POSITIONS_SIZE                             (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_OFFSET                                      (192u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_RAW0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_OFFSET                                     (194u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_OFFSET                                     (196u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_DIFF0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_OFFSET                                   (198u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_STATUS0_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (199u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_OFFSET                                     (200u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_IDAC0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_OFFSET                                 (201u)
+#define CY_CAPSENSE_TUNER_BUTTON0_RX0_BSLN_EXT0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_OFFSET                                      (202u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_RAW0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_OFFSET                                     (204u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_OFFSET                                     (206u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_DIFF0_SIZE                                       (2u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_OFFSET                                   (208u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_STATUS0_SIZE                                     (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_OFFSET                         (209u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_NEG_BSLN_RST_CNT0_SIZE                           (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_OFFSET                                     (210u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_IDAC0_SIZE                                       (1u)
+
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_OFFSET                                 (211u)
+#define CY_CAPSENSE_TUNER_BUTTON1_RX0_BSLN_EXT0_SIZE                                   (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_OFFSET                               (212u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_OFFSET                              (214u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_OFFSET                              (216u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_OFFSET                            (218u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_OFFSET                  (219u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_OFFSET                              (220u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_OFFSET                          (221u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS0_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_OFFSET                               (222u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_OFFSET                              (224u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_OFFSET                              (226u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_OFFSET                            (228u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_OFFSET                  (229u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_OFFSET                              (230u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_OFFSET                          (231u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS1_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_OFFSET                               (232u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_OFFSET                              (234u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_OFFSET                              (236u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_OFFSET                            (238u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_OFFSET                  (239u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_OFFSET                              (240u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_OFFSET                          (241u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS2_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_OFFSET                               (242u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_OFFSET                              (244u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_OFFSET                              (246u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_OFFSET                            (248u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_OFFSET                  (249u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_OFFSET                              (250u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_OFFSET                          (251u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS3_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_OFFSET                               (252u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_RAW0_SIZE                                 (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_OFFSET                              (254u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_OFFSET                              (256u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_DIFF0_SIZE                                (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_OFFSET                            (258u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_STATUS0_SIZE                              (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_OFFSET                  (259u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_NEG_BSLN_RST_CNT0_SIZE                    (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_OFFSET                              (260u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_IDAC0_SIZE                                (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_OFFSET                          (261u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_SNS4_BSLN_EXT0_SIZE                            (1u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_OFFSET                                      (262u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_X0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_OFFSET                                      (264u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Y0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_OFFSET                                      (266u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_Z0_SIZE                                        (2u)
+
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_OFFSET                                     (268u)
+#define CY_CAPSENSE_TUNER_LINEARSLIDER0_ID0_SIZE                                       (2u)
+
+#endif
+
+
+#endif /* CYCFG_CAPSENSE_TUNER_REGMAP_H */
+
+/* [] END OF FILE */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

@@ -0,0 +1,60 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.c
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+#include <rtthread.h>
+
+#include "cycfg_clocks.h"
+
+#if defined (CY_USING_HAL)
+const cyhal_resource_inst_t CLK_PWM_obj =
+{
+    .type = CYHAL_RSC_CLOCK,
+    .block_num = CLK_PWM_HW,
+    .channel_num = CLK_PWM_NUM,
+};
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
+{
+    .type = CYHAL_RSC_CLOCK,
+    .block_num = CYBSP_CSD_CLK_DIV_HW,
+    .channel_num = CYBSP_CSD_CLK_DIV_NUM,
+};
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_clocks(void)
+{
+    Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
+    Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
+#endif //defined (CY_USING_HAL)
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

@@ -0,0 +1,66 @@
+/*******************************************************************************
+* File Name: cycfg_clocks.h
+*
+* Description:
+* Clock configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CLOCKS_H)
+#define CYCFG_CLOCKS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CLK_PWM_ENABLED 1U
+#define CLK_PWM_HW CY_SYSCLK_DIV_16_BIT
+#define CLK_PWM_NUM 0U
+
+#define CYBSP_CSD_CLK_DIV_ENABLED 1U
+#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED
+#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW
+#define CYBSP_CSD_CLK_DIV_NUM 0U
+#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
+    #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_clocks(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CLOCKS_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c

@@ -0,0 +1,31 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.c
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_connectivity_bt.h"
+

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h

@@ -0,0 +1,55 @@
+/*******************************************************************************
+* File Name: cycfg_connectivity_bt.h
+*
+* Description:
+* Connectivity BT configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_CONNECTIVITY_BT_H)
+#define CYCFG_CONNECTIVITY_BT_H
+
+#include "cycfg_notices.h"
+#include "cycfg_pins.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define bt_0_power_0_ENABLED 1U
+#define CYCFG_BT_LP_ENABLED (1u)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0)
+#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1)
+#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE
+#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW
+#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE
+#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_CONNECTIVITY_BT_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.c

@@ -0,0 +1,181 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.c
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_dmas.h"
+
+const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config =
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_DESCR,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 1,
+    .dstXincrement = 0,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = NULL,
+};
+cy_stc_dma_descriptor_t TxDma_Descriptor_0 =
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t TxDma_channelConfig =
+{
+    .descriptor = &TxDma_Descriptor_0,
+    .preemptable = false,
+    .priority = 3,
+    .enable = false,
+    .bufferable = false,
+};
+const cy_stc_dma_crc_config_t TxDma_crcConfig =
+{
+    .dataReverse = false,
+    .dataXor = 0,
+    .reminderReverse = false,
+    .reminderXor = 0,
+    .polynomial = 79764919,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t TxDma_obj =
+    {
+        .type = CYHAL_RSC_DMA,
+        .block_num = 0U,
+        .channel_num = TxDma_CHANNEL,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config =
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_1ELEMENT,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 0,
+    .dstXincrement = 1,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = &RxDma_Descriptor_1,
+};
+const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config =
+{
+    .retrigger = CY_DMA_RETRIG_4CYC,
+    .interruptType = CY_DMA_DESCR,
+    .triggerOutType = CY_DMA_1ELEMENT,
+    .channelState = CY_DMA_CHANNEL_ENABLED,
+    .triggerInType = CY_DMA_1ELEMENT,
+    .dataSize = CY_DMA_BYTE,
+    .srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD,
+    .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA,
+    .descriptorType = CY_DMA_SINGLE_TRANSFER,
+    .srcAddress = NULL,
+    .dstAddress = NULL,
+    .srcXincrement = 0,
+    .dstXincrement = 1,
+    .xCount = 1,
+    .srcYincrement = 1,
+    .dstYincrement = 1,
+    .yCount = 1,
+    .nextDescriptor = &RxDma_Descriptor_0,
+};
+cy_stc_dma_descriptor_t RxDma_Descriptor_0 =
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+cy_stc_dma_descriptor_t RxDma_Descriptor_1 =
+{
+    .ctl = 0UL,
+    .src = 0UL,
+    .dst = 0UL,
+    .xCtl = 0UL,
+    .yCtl = 0UL,
+    .nextPtr = 0UL,
+};
+const cy_stc_dma_channel_config_t RxDma_channelConfig =
+{
+    .descriptor = &RxDma_Descriptor_0,
+    .preemptable = false,
+    .priority = 3,
+    .enable = false,
+    .bufferable = false,
+};
+const cy_stc_dma_crc_config_t RxDma_crcConfig =
+{
+    .dataReverse = false,
+    .dataXor = 0,
+    .reminderReverse = false,
+    .reminderXor = 0,
+    .polynomial = 79764919,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t RxDma_obj =
+    {
+        .type = CYHAL_RSC_DMA,
+        .block_num = 0U,
+        .channel_num = RxDma_CHANNEL,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_dmas(void)
+{
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&TxDma_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&RxDma_obj);
+#endif //defined (CY_USING_HAL)
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_dmas.h

@@ -0,0 +1,76 @@
+/*******************************************************************************
+* File Name: cycfg_dmas.h
+*
+* Description:
+* DMA configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_DMAS_H)
+#define CYCFG_DMAS_H
+
+#include "cycfg_notices.h"
+#include "cy_dma.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define TxDma_ENABLED 1U
+#define TxDma_HW DW0
+#define TxDma_CHANNEL 26U
+#define TxDma_IRQ cpuss_interrupts_dw0_26_IRQn
+#define RxDma_ENABLED 1U
+#define RxDma_HW DW0
+#define RxDma_CHANNEL 27U
+#define RxDma_IRQ cpuss_interrupts_dw0_27_IRQn
+
+extern const cy_stc_dma_descriptor_config_t TxDma_Descriptor_0_config;
+extern cy_stc_dma_descriptor_t TxDma_Descriptor_0;
+extern const cy_stc_dma_channel_config_t TxDma_channelConfig;
+extern const cy_stc_dma_crc_config_t TxDma_crcConfig;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t TxDma_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_0_config;
+extern const cy_stc_dma_descriptor_config_t RxDma_Descriptor_1_config;
+extern cy_stc_dma_descriptor_t RxDma_Descriptor_0;
+extern cy_stc_dma_descriptor_t RxDma_Descriptor_1;
+extern const cy_stc_dma_channel_config_t RxDma_channelConfig;
+extern const cy_stc_dma_crc_config_t RxDma_crcConfig;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t RxDma_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_dmas(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_DMAS_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

@@ -0,0 +1,41 @@
+/*******************************************************************************
+* File Name: cycfg_notices.h
+*
+* Description:
+* Contains warnings and errors that occurred while generating code for the
+* design.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_NOTICES_H)
+#define CYCFG_NOTICES_H
+
+#ifdef CY_SUPPORTS_DEVICE_VALIDATION
+#ifndef CY8C624ABZI_S2D44
+    #error "Unexpected target MCU; expected CY8C624ABZI-S2D44. There may be an inconsistency between the *.modus file and the makefile target configuration device sets."
+#endif
+#endif
+
+
+#endif /* CYCFG_NOTICES_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

@@ -0,0 +1,66 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.c
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+#include <rtthread.h>
+
+#include "cycfg_peripherals.h"
+
+cy_stc_csd_context_t cy_csd_0_context =
+{
+    .lockKey = CY_CSD_NONE_KEY,
+};
+
+void init_cycfg_peripherals(void)
+{
+    Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+
+#ifdef BSP_USING_UART0
+    /* UART0 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+#ifdef BSP_USING_UART1
+    /* UART1 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB1_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+#ifdef BSP_USING_UART2
+    /* UART2 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB2_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+#if defined(BSP_USING_UART3) || defined(BSP_USING_HW_I2C3)
+    /* UART3 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB3_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+#ifdef BSP_USING_UART4
+    /* UART4 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB4_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+#ifdef BSP_USING_UART5
+    /* UART5 Device Clock*/
+    Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
+#endif
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

@@ -0,0 +1,87 @@
+/*******************************************************************************
+* File Name: cycfg_peripherals.h
+*
+* Description:
+* Peripheral Hardware Block configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PERIPHERALS_H)
+#define CYCFG_PERIPHERALS_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_csd.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_CSD_ENABLED 1U
+#define CY_CAPSENSE_CORE 4u
+#define CY_CAPSENSE_CPU_CLK 100000000u
+#define CY_CAPSENSE_PERI_CLK 100000000u
+#define CY_CAPSENSE_VDDA_MV 3300u
+#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
+#define CY_CAPSENSE_PERI_DIV_INDEX 0u
+#define Cmod_PORT GPIO_PRT7
+#define CintA_PORT GPIO_PRT7
+#define CintB_PORT GPIO_PRT7
+#define Button0_Rx0_PORT GPIO_PRT1
+#define Button0_Tx_PORT GPIO_PRT8
+#define Button1_Rx0_PORT GPIO_PRT1
+#define Button1_Tx_PORT GPIO_PRT8
+#define LinearSlider0_Sns0_PORT GPIO_PRT8
+#define LinearSlider0_Sns1_PORT GPIO_PRT8
+#define LinearSlider0_Sns2_PORT GPIO_PRT8
+#define LinearSlider0_Sns3_PORT GPIO_PRT8
+#define LinearSlider0_Sns4_PORT GPIO_PRT8
+#define Cmod_PIN 7u
+#define CintA_PIN 1u
+#define CintB_PIN 2u
+#define Button0_Rx0_PIN 0u
+#define Button0_Tx_PIN 1u
+#define Button1_Rx0_PIN 0u
+#define Button1_Tx_PIN 2u
+#define LinearSlider0_Sns0_PIN 3u
+#define LinearSlider0_Sns1_PIN 4u
+#define LinearSlider0_Sns2_PIN 5u
+#define LinearSlider0_Sns3_PIN 6u
+#define LinearSlider0_Sns4_PIN 7u
+#define Cmod_PORT_NUM 7u
+#define CintA_PORT_NUM 7u
+#define CintB_PORT_NUM 7u
+#define CYBSP_CSD_HW CSD0
+#define CYBSP_CSD_IRQ csd_interrupt_IRQn
+
+extern cy_stc_csd_context_t cy_csd_0_context;
+
+void init_cycfg_peripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PERIPHERALS_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

@@ -0,0 +1,581 @@
+/*******************************************************************************
+* File Name: cycfg_pins.c
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_pins.h"
+
+#define CYBSP_SDHC_IO1_PORT GPIO_PRT13
+#define CYBSP_SDHC_IO1_PORT_NUM 13U
+#define CYBSP_SDHC_IO1_PIN 1U
+
+#ifndef ioss_0_port_13_pin_1_HSIOM
+    #define ioss_0_port_13_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SDHC_IO1_HSIOM ioss_0_port_13_pin_1_HSIOM
+
+#define CYBSP_SDHC_IO2_PORT GPIO_PRT13
+#define CYBSP_SDHC_IO2_PORT_NUM 13U
+#define CYBSP_SDHC_IO2_PIN 2U
+
+#ifndef ioss_0_port_13_pin_2_HSIOM
+    #define ioss_0_port_13_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SDHC_IO2_HSIOM ioss_0_port_13_pin_2_HSIOM
+
+const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .hsiom = CYBSP_SDHC_IO1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SDHC_IO1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SDHC_IO1_PORT_NUM,
+        .channel_num = CYBSP_SDHC_IO1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+const cy_stc_gpio_pin_config_t CYBSP_SDHC_IO2_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_OD_DRIVESLOW,
+    .hsiom = CYBSP_SDHC_IO2_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SDHC_IO2_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SDHC_IO2_PORT_NUM,
+        .channel_num = CYBSP_SDHC_IO2_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_IN_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_IN_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_IN_PORT_NUM,
+        .channel_num = CYBSP_WCO_IN_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_WCO_OUT_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_WCO_OUT_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_WCO_OUT_PORT_NUM,
+        .channel_num = CYBSP_WCO_OUT_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_RX_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_RX_PORT_NUM,
+        .channel_num = CYBSP_CSD_RX_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+    .hsiom = CYBSP_SWO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWO_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWO_PORT_NUM,
+        .channel_num = CYBSP_SWO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLUP,
+    .hsiom = CYBSP_SWDIO_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDIO_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDIO_PORT_NUM,
+        .channel_num = CYBSP_SWDIO_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_PULLDOWN,
+    .hsiom = CYBSP_SWDCK_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_SWDCK_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_SWDCK_PORT_NUM,
+        .channel_num = CYBSP_SWDCK_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CINA_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CINA_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CINA_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CINA_PORT_NUM,
+        .channel_num = CYBSP_CINA_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CINB_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CINB_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CINB_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CINB_PORT_NUM,
+        .channel_num = CYBSP_CINB_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CMOD_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CMOD_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CMOD_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CMOD_PORT_NUM,
+        .channel_num = CYBSP_CMOD_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN0_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_BTN1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_BTN1_PORT_NUM,
+        .channel_num = CYBSP_CSD_BTN1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD0_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD0_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD0_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD1_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD1_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD1_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD2_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD2_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD2_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD3_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD3_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD3_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_ANALOG,
+    .hsiom = CYBSP_CSD_SLD4_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = CYBSP_CSD_SLD4_PORT_NUM,
+        .channel_num = CYBSP_CSD_SLD4_PIN,
+    };
+#endif //defined (CY_USING_HAL)
+
+const cy_stc_gpio_pin_config_t SMART_IO_OUTPUT_PIN_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
+    .hsiom = P9_1_TCPWM1_LINE_COMPL20,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+};
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t SMART_IO_OUTPUT_PIN_obj =
+    {
+        .type = CYHAL_RSC_GPIO,
+        .block_num = 9U,
+        .channel_num = 1U,
+    };
+#endif //defined (CY_USING_HAL)
+
+
+void init_cycfg_pins(void)
+{
+    Cy_GPIO_Pin_Init(CYBSP_WCO_IN_PORT, CYBSP_WCO_IN_PIN, &CYBSP_WCO_IN_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_IN_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_WCO_OUT_PORT, CYBSP_WCO_OUT_PIN, &CYBSP_WCO_OUT_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_WCO_OUT_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWO_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj);
+#endif //defined (CY_USING_HAL)
+
+    Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config);
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CINA_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CINB_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CMOD_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_BTN1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&CYBSP_CSD_SLD4_obj);
+#endif //defined (CY_USING_HAL)
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

@@ -0,0 +1,936 @@
+/*******************************************************************************
+* File Name: cycfg_pins.h
+*
+* Description:
+* Pin configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_PINS_H)
+#define CYCFG_PINS_H
+
+#include "cycfg_notices.h"
+#include "cy_gpio.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cycfg_routing.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define CYBSP_WCO_IN_ENABLED 1U
+#define CYBSP_WCO_IN_PORT GPIO_PRT0
+#define CYBSP_WCO_IN_PORT_NUM 0U
+#define CYBSP_WCO_IN_PIN 0U
+#define CYBSP_WCO_IN_NUM 0U
+#define CYBSP_WCO_IN_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_IN_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_0_HSIOM
+    #define ioss_0_port_0_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_IN_HSIOM ioss_0_port_0_pin_0_HSIOM
+#define CYBSP_WCO_IN_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_PORT_PIN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN P0_0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_IN_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_WCO_OUT_ENABLED 1U
+#define CYBSP_WCO_OUT_PORT GPIO_PRT0
+#define CYBSP_WCO_OUT_PORT_NUM 0U
+#define CYBSP_WCO_OUT_PIN 1U
+#define CYBSP_WCO_OUT_NUM 1U
+#define CYBSP_WCO_OUT_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_WCO_OUT_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_0_pin_1_HSIOM
+    #define ioss_0_port_0_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_WCO_OUT_HSIOM ioss_0_port_0_pin_1_HSIOM
+#define CYBSP_WCO_OUT_IRQ ioss_interrupts_gpio_0_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_PORT_PIN P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT P0_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SW2 (P0_4)
+    #define CYBSP_USER_BTN1 CYBSP_SW2
+    #define CYBSP_USER_BTN CYBSP_SW2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED_RGB_GREEN (P0_5)
+    #define CYBSP_USER_LED4 CYBSP_LED_RGB_GREEN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A0 (P10_0)
+    #define CYBSP_J2_1 CYBSP_A0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A1 (P10_1)
+    #define CYBSP_J2_3 CYBSP_A1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A2 (P10_2)
+    #define CYBSP_J2_5 CYBSP_A2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A3 (P10_3)
+    #define CYBSP_J2_7 CYBSP_A3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A4 (P10_4)
+    #define CYBSP_J2_9 CYBSP_A4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A5 (P10_5)
+    #define CYBSP_J2_11 CYBSP_A5
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A6 (P10_6)
+    #define CYBSP_J2_13 CYBSP_A6
+    #define CYBSP_POT CYBSP_A6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A7 (P10_7)
+    #define CYBSP_J2_15 CYBSP_A7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_FRAM_SSEL (P11_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED9 (P11_1)
+    #define CYBSP_USER_LED2 CYBSP_LED9
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_SS (P11_2)
+    #define CYBSP_QSPI_FLASH_SSEL CYBSP_QSPI_SS
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D3 (P11_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D2 (P11_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D1 (P11_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_D0 (P11_6)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_QSPI_SCK (P11_7)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SPI_MOSI (P12_0)
+    #define CYBSP_D11 CYBSP_SPI_MOSI
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SPI_MISO (P12_1)
+    #define CYBSP_D12 CYBSP_SPI_MISO
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SPI_CLK (P12_2)
+    #define CYBSP_D13 CYBSP_SPI_CLK
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SPI_CS (P12_3)
+    #define CYBSP_D10 CYBSP_SPI_CS
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_CMD (P12_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_CLK (P12_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_IO0 (P13_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_IO1 (P13_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_IO2 (P13_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_IO3 (P13_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SDHC_DETECT (P13_5)
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_RX_ENABLED 1U
+#define CYBSP_CS_RX_ENABLED CYBSP_CSD_RX_ENABLED
+#define CYBSP_CS_TX_RX_ENABLED CYBSP_CSD_RX_ENABLED
+#define CYBSP_CSD_RX_PORT GPIO_PRT1
+#define CYBSP_CS_RX_PORT CYBSP_CSD_RX_PORT
+#define CYBSP_CS_TX_RX_PORT CYBSP_CSD_RX_PORT
+#define CYBSP_CSD_RX_PORT_NUM 1U
+#define CYBSP_CS_RX_PORT_NUM CYBSP_CSD_RX_PORT_NUM
+#define CYBSP_CS_TX_RX_PORT_NUM CYBSP_CSD_RX_PORT_NUM
+#define CYBSP_CSD_RX_PIN 0U
+#define CYBSP_CS_RX_PIN CYBSP_CSD_RX_PIN
+#define CYBSP_CS_TX_RX_PIN CYBSP_CSD_RX_PIN
+#define CYBSP_CSD_RX_NUM 0U
+#define CYBSP_CS_RX_NUM CYBSP_CSD_RX_NUM
+#define CYBSP_CS_TX_RX_NUM CYBSP_CSD_RX_NUM
+#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_RX_DRIVEMODE CYBSP_CSD_RX_DRIVEMODE
+#define CYBSP_CS_TX_RX_DRIVEMODE CYBSP_CSD_RX_DRIVEMODE
+#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
+#define CYBSP_CS_RX_INIT_DRIVESTATE CYBSP_CSD_RX_INIT_DRIVESTATE
+#define CYBSP_CS_TX_RX_INIT_DRIVESTATE CYBSP_CSD_RX_INIT_DRIVESTATE
+#ifndef ioss_0_port_1_pin_0_HSIOM
+    #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
+#define CYBSP_CS_RX_HSIOM CYBSP_CSD_RX_HSIOM
+#define CYBSP_CS_TX_RX_HSIOM CYBSP_CSD_RX_HSIOM
+#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
+#define CYBSP_CS_RX_IRQ CYBSP_CSD_RX_IRQ
+#define CYBSP_CS_TX_RX_IRQ CYBSP_CSD_RX_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
+    #define CYBSP_CS_RX_HAL_PORT_PIN CYBSP_CSD_RX_HAL_PORT_PIN
+    #define CYBSP_CS_TX_RX_HAL_PORT_PIN CYBSP_CSD_RX_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_RX P1_0
+    #define CYBSP_CS_RX CYBSP_CSD_RX
+    #define CYBSP_CS_TX_RX CYBSP_CSD_RX
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_RX_HAL_IRQ CYBSP_CSD_RX_HAL_IRQ
+    #define CYBSP_CS_TX_RX_HAL_IRQ CYBSP_CSD_RX_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_RX_HAL_DIR CYBSP_CSD_RX_HAL_DIR
+    #define CYBSP_CS_TX_RX_HAL_DIR CYBSP_CSD_RX_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE
+    #define CYBSP_CS_TX_RX_HAL_DRIVEMODE CYBSP_CSD_RX_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED_RGB_RED (P1_1)
+    #define CYBSP_USER_LED3 CYBSP_LED_RGB_RED
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SW4 (P1_4)
+    #define CYBSP_USER_BTN2 CYBSP_SW4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED4 (P13_7)
+    #define CYBSP_USER_LED1 CYBSP_LED4
+    #define CYBSP_USER_LED CYBSP_LED4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D0 (P2_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D1 (P2_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D2 (P2_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_D3 (P2_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_CMD (P2_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_SDIO_CLK (P2_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_WL_REG_ON (P2_6)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_RX (P3_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_TX (P3_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_RTS (P3_2)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_UART_CTS (P3_3)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_POWER (P3_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_DEVICE_WAKE (P3_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_BT_HOST_WAKE (P4_0)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_WIFI_HOST_WAKE (P4_1)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_RX (P5_0)
+    #define CYBSP_D0 CYBSP_DEBUG_UART_RX
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_TX (P5_1)
+    #define CYBSP_D1 CYBSP_DEBUG_UART_TX
+    #define CYBSP_DEBUG_UART_TX_PORT GPIO_PRT5
+    #define CYBSP_DEBUG_UART_TX_PIN 1U
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_RTS (P5_2)
+    #define CYBSP_D2 CYBSP_DEBUG_UART_RTS
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_DEBUG_UART_CTS (P5_3)
+    #define CYBSP_D3 CYBSP_DEBUG_UART_CTS
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D4 (P5_4)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D5 (P5_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D6 (P5_6)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D7 (P5_7)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_I2C_SCL (P6_0)
+    #define CYBSP_D15 CYBSP_I2C_SCL
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_I2C_SDA (P6_1)
+    #define CYBSP_D14 CYBSP_I2C_SDA
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWO_ENABLED 1U
+#define CYBSP_SWO_PORT GPIO_PRT6
+#define CYBSP_SWO_PORT_NUM 6U
+#define CYBSP_SWO_PIN 4U
+#define CYBSP_SWO_NUM 4U
+#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_SWO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_4_HSIOM
+    #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM
+#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO_HAL_PORT_PIN P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO P6_4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDIO_ENABLED 1U
+#define CYBSP_SWDIO_PORT GPIO_PRT6
+#define CYBSP_SWDIO_PORT_NUM 6U
+#define CYBSP_SWDIO_PIN 6U
+#define CYBSP_SWDIO_NUM 6U
+#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP
+#define CYBSP_SWDIO_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_6_HSIOM
+    #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM
+#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_PORT_PIN P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO P6_6
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP
+#endif //defined (CY_USING_HAL)
+#define CYBSP_SWDCK_ENABLED 1U
+#define CYBSP_SWDCK_PORT GPIO_PRT6
+#define CYBSP_SWDCK_PORT_NUM 6U
+#define CYBSP_SWDCK_PIN 7U
+#define CYBSP_SWDCK_NUM 7U
+#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN
+#define CYBSP_SWDCK_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_6_pin_7_HSIOM
+    #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM
+#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_PORT_PIN P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK P6_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINA_ENABLED 1U
+#define CYBSP_CINA_PORT GPIO_PRT7
+#define CYBSP_CINA_PORT_NUM 7U
+#define CYBSP_CINA_PIN 1U
+#define CYBSP_CINA_NUM 1U
+#define CYBSP_CINA_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINA_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_1_HSIOM
+    #define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINA_HSIOM ioss_0_port_7_pin_1_HSIOM
+#define CYBSP_CINA_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINA_HAL_PORT_PIN P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINA P7_1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINA_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINA_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINA_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CINB_ENABLED 1U
+#define CYBSP_CINB_PORT GPIO_PRT7
+#define CYBSP_CINB_PORT_NUM 7U
+#define CYBSP_CINB_PIN 2U
+#define CYBSP_CINB_NUM 2U
+#define CYBSP_CINB_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CINB_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_2_HSIOM
+    #define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CINB_HSIOM ioss_0_port_7_pin_2_HSIOM
+#define CYBSP_CINB_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINB_HAL_PORT_PIN P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINB P7_2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINB_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINB_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CINB_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_LED_RGB_BLUE (P7_3)
+    #define CYBSP_USER_LED5 CYBSP_LED_RGB_BLUE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D8 (P7_5)
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_D9 (P7_6)
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CMOD_ENABLED 1U
+#define CYBSP_CMOD_PORT GPIO_PRT7
+#define CYBSP_CMOD_PORT_NUM 7U
+#define CYBSP_CMOD_PIN 7U
+#define CYBSP_CMOD_NUM 7U
+#define CYBSP_CMOD_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CMOD_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_7_pin_7_HSIOM
+    #define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CMOD_HSIOM ioss_0_port_7_pin_7_HSIOM
+#define CYBSP_CMOD_IRQ ioss_interrupts_gpio_7_IRQn
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_PORT_PIN P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD P7_7
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_DIR CYHAL_GPIO_DIR_INPUT
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN0_ENABLED 1U
+#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED
+#define CYBSP_CSD_BTN0_PORT GPIO_PRT8
+#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT
+#define CYBSP_CSD_BTN0_PORT_NUM 8U
+#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM
+#define CYBSP_CSD_BTN0_PIN 1U
+#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN
+#define CYBSP_CSD_BTN0_NUM 1U
+#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM
+#define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE
+#define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1
+#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_1_HSIOM
+    #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM
+#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM
+#define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1
+    #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0 P8_1
+    #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_BTN1_ENABLED 1U
+#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED
+#define CYBSP_CSD_BTN1_PORT GPIO_PRT8
+#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT
+#define CYBSP_CSD_BTN1_PORT_NUM 8U
+#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM
+#define CYBSP_CSD_BTN1_PIN 2U
+#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN
+#define CYBSP_CSD_BTN1_NUM 2U
+#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM
+#define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE
+#define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1
+#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_2_HSIOM
+    #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM
+#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM
+#define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2
+    #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1 P8_2
+    #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD0_ENABLED 1U
+#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED
+#define CYBSP_CSD_SLD0_PORT GPIO_PRT8
+#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT
+#define CYBSP_CSD_SLD0_PORT_NUM 8U
+#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM
+#define CYBSP_CSD_SLD0_PIN 3U
+#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN
+#define CYBSP_CSD_SLD0_NUM 3U
+#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM
+#define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE
+#define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_3_HSIOM
+    #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM
+#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM
+#define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3
+    #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0 P8_3
+    #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD1_ENABLED 1U
+#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED
+#define CYBSP_CSD_SLD1_PORT GPIO_PRT8
+#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT
+#define CYBSP_CSD_SLD1_PORT_NUM 8U
+#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM
+#define CYBSP_CSD_SLD1_PIN 4U
+#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN
+#define CYBSP_CSD_SLD1_NUM 4U
+#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM
+#define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE
+#define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_4_HSIOM
+    #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM
+#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM
+#define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4
+    #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1 P8_4
+    #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD2_ENABLED 1U
+#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED
+#define CYBSP_CSD_SLD2_PORT GPIO_PRT8
+#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT
+#define CYBSP_CSD_SLD2_PORT_NUM 8U
+#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM
+#define CYBSP_CSD_SLD2_PIN 5U
+#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN
+#define CYBSP_CSD_SLD2_NUM 5U
+#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM
+#define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE
+#define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_5_HSIOM
+    #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM
+#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM
+#define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5
+    #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2 P8_5
+    #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD3_ENABLED 1U
+#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED
+#define CYBSP_CSD_SLD3_PORT GPIO_PRT8
+#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT
+#define CYBSP_CSD_SLD3_PORT_NUM 8U
+#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM
+#define CYBSP_CSD_SLD3_PIN 6U
+#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN
+#define CYBSP_CSD_SLD3_NUM 6U
+#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM
+#define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE
+#define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_6_HSIOM
+    #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM
+#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM
+#define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6
+    #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3 P8_6
+    #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#define CYBSP_CSD_SLD4_ENABLED 1U
+#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED
+#define CYBSP_CSD_SLD4_PORT GPIO_PRT8
+#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT
+#define CYBSP_CSD_SLD4_PORT_NUM 8U
+#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM
+#define CYBSP_CSD_SLD4_PIN 7U
+#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN
+#define CYBSP_CSD_SLD4_NUM 7U
+#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM
+#define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG
+#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE
+#define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1
+#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE
+#ifndef ioss_0_port_8_pin_7_HSIOM
+    #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM
+#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM
+#define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn
+#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7
+    #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4 P8_7
+    #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE
+    #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT
+    #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
+    #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A8 (P9_0)
+    #define CYBSP_J2_2 CYBSP_A8
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A9 (P9_1)
+    #define CYBSP_J2_4 CYBSP_A9
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A10 (P9_2)
+    #define CYBSP_J2_6 CYBSP_A10
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A11 (P9_3)
+    #define CYBSP_J2_8 CYBSP_A11
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A12 (P9_4)
+    #define CYBSP_J2_10 CYBSP_A12
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A13 (P9_5)
+    #define CYBSP_J2_12 CYBSP_A13
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A14 (P9_6)
+    #define CYBSP_J2_14 CYBSP_A14
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    #define CYBSP_A15 (P9_7)
+    #define CYBSP_J2_16 CYBSP_A15
+#endif //defined (CY_USING_HAL)
+
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_IN_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
+#define CYBSP_CS_RX_config CYBSP_CSD_RX_config
+#define CYBSP_CS_TX_RX_config CYBSP_CSD_RX_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
+    #define CYBSP_CS_RX_obj CYBSP_CSD_RX_obj
+    #define CYBSP_CS_TX_RX_obj CYBSP_CSD_RX_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDIO_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_SWDCK_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINA_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CINA_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CINB_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CINB_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config;
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CMOD_obj;
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config;
+#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj;
+    #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config;
+#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj;
+    #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config;
+#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj;
+    #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config;
+#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj;
+    #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config;
+#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj;
+    #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config;
+#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj;
+    #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj
+#endif //defined (CY_USING_HAL)
+extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config;
+#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj;
+    #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_pins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_PINS_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c

@@ -0,0 +1,271 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.c
+*
+* Description:
+* Provides definitions of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_qspi_memslot.h"
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xECU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_QUAD,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0x01U,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 4U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x06U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x04U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0xDCU,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x60U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x34U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_QUAD,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_QUAD
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x35U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x05U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd =
+{
+    /* The 8-bit command. 1 x I/O read command. */
+    .command = 0x01U,
+    /* The width of the command transfer. */
+    .cmdWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The width of the address transfer. */
+    .addrWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
+    .mode = 0xFFFFFFFFU,
+    /* The width of the mode command transfer. */
+    .modeWidth = CY_SMIF_WIDTH_SINGLE,
+    /* The number of dummy cycles. A zero value suggests no dummy cycles. */
+    .dummyCycles = 0U,
+    /* The width of the data transfer. */
+    .dataWidth = CY_SMIF_WIDTH_SINGLE
+};
+
+const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 =
+{
+    /* Specifies the number of address bytes used by the memory slave device. */
+    .numOfAddrBytes = 0x04U,
+    /* The size of the memory. */
+    .memSize = 0x04000000U,
+    /* Specifies the Read command. */
+    .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd,
+    /* Specifies the Write Enable command. */
+    .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd,
+    /* Specifies the Write Disable command. */
+    .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd,
+    /* Specifies the Erase command. */
+    .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd,
+    /* Specifies the sector size of each erase. */
+    .eraseSize = 0x00040000U,
+    /* Specifies the Chip Erase command. */
+    .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd,
+    /* Specifies the Program command. */
+    .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd,
+    /* Specifies the page size for programming. */
+    .programSize = 0x00000200U,
+    /* Specifies the command to read the QE-containing status register. */
+    .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd,
+    /* Specifies the command to read the WIP-containing status register. */
+    .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd,
+    /* Specifies the command to write into the QE-containing status register. */
+    .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd,
+    /* The mask for the status register. */
+    .stsRegBusyMask = 0x01U,
+    /* The mask for the status register. */
+    .stsRegQuadEnableMask = 0x02U,
+    /* The max time for the erase type-1 cycle-time in ms. */
+    .eraseTime = 2600U,
+    /* The max time for the chip-erase cycle-time in ms. */
+    .chipEraseTime = 460000U,
+    /* The max time for the page-program cycle-time in us. */
+    .programTime = 1300U,
+#if (CY_SMIF_DRV_VERSION_MAJOR > 1) || (CY_SMIF_DRV_VERSION_MINOR >= 50)
+    /* Points to NULL or to structure with info about sectors for hybrid memory. */
+    .hybridRegionCount = 0U,
+    .hybridRegionInfo = NULL
+#endif
+};
+
+const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 =
+{
+    /* Determines the slot number where the memory device is placed. */
+    .slaveSelect = CY_SMIF_SLAVE_SELECT_0,
+    /* Flags. */
+    .flags = CY_SMIF_FLAG_MEMORY_MAPPED | CY_SMIF_FLAG_WR_EN,
+    /* The data-line selection options for a slave device. */
+    .dataSelect = CY_SMIF_DATA_SEL0,
+    /* The base address the memory slave is mapped to in the PSoC memory map.
+    Valid when the memory-mapped mode is enabled. */
+    .baseAddress = 0x18000000U,
+    /* The size allocated in the PSoC memory map, for the memory slave device.
+    The size is allocated from the base address. Valid when the memory mapped mode is enabled. */
+    .memMappedSize = 0x4000000U,
+    /* If this memory device is one of the devices in the dual quad SPI configuration.
+    Valid when the memory mapped mode is enabled. */
+    .dualQuadSlots = 0,
+    /* The configuration of the device. */
+    .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_mem_config_t* const smifMemConfigs[] = {
+   &S25FL512S_SlaveSlot_0
+};
+
+const cy_stc_smif_block_config_t smifBlockConfig =
+{
+    /* The number of SMIF memories defined. */
+    .memCount = CY_SMIF_DEVICE_NUM,
+    /* The pointer to the array of memory config structures of size memCount. */
+    .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs,
+    /* The version of the SMIF driver. */
+    .majorVersion = CY_SMIF_DRV_VERSION_MAJOR,
+    /* The version of the SMIF driver. */
+    .minorVersion = CY_SMIF_DRV_VERSION_MINOR
+};
+

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

@@ -0,0 +1,65 @@
+/*******************************************************************************
+* File Name: cycfg_qspi_memslot.h
+*
+* Description:
+* Provides declarations of the SMIF-driver memory configuration.
+* This file was automatically generated and should not be modified.
+* QSPI Configurator 2.20.0.2857
+*
+********************************************************************************
+* Copyright 2020 Cypress Semiconductor Corporation
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#ifndef CYCFG_QSPI_MEMSLOT_H
+#define CYCFG_QSPI_MEMSLOT_H
+#include "cy_smif_memslot.h"
+
+#define CY_SMIF_CFG_TOOL_VERSION           (220)
+
+/* Supported QSPI Driver version */
+#define CY_SMIF_DRV_VERSION_REQUIRED       (100)
+
+#if !defined(CY_SMIF_DRV_VERSION)
+    #define CY_SMIF_DRV_VERSION            (100)
+#endif
+
+/* Check the used Driver version */
+#if (CY_SMIF_DRV_VERSION_REQUIRED > CY_SMIF_DRV_VERSION)
+   #error The QSPI Configurator requires a newer version of the PDL. Update the PDL in your project.
+#endif
+
+#define CY_SMIF_DEVICE_NUM 1
+
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd;
+extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd;
+
+extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0;
+
+extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0;
+extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
+
+extern const cy_stc_smif_block_config_t smifBlockConfig;
+
+
+#endif /*CYCFG_QSPI_MEMSLOT_H*/
+

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c

@@ -0,0 +1,44 @@
+/*******************************************************************************
+* File Name: cycfg_routing.c
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_routing.h"
+
+#include "cy_device_headers.h"
+
+void init_cycfg_routing(void)
+{
+    HSIOM->AMUX_SPLIT_CTL[2] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+    HSIOM->AMUX_SPLIT_CTL[4] = HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk |
+        HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk;
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h

@@ -0,0 +1,62 @@
+/*******************************************************************************
+* File Name: cycfg_routing.h
+*
+* Description:
+* Establishes all necessary connections between hardware elements.
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_ROUTING_H)
+#define CYCFG_ROUTING_H
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#include "cycfg_notices.h"
+void init_cycfg_routing(void);
+#define init_cycfg_connectivity() init_cycfg_routing()
+#define ioss_0_port_0_pin_0_ANALOG P0_0_SRSS_WCO_IN
+#define ioss_0_port_0_pin_1_ANALOG P0_1_SRSS_WCO_OUT
+#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO
+#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS
+#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK
+#define ioss_0_port_7_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_7_pin_7_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_AMUXA
+#define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_AMUXA
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_ROUTING_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c

@@ -0,0 +1,1212 @@
+/*******************************************************************************
+* File Name: cycfg_system.c
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.14850
+* personalities 6.0.0.0
+* udd 3.0.0.2024
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#include "cycfg_system.h"
+
+#define CY_CFG_SYSCLK_ECO_ERROR 1
+#define CY_CFG_SYSCLK_ALTHF_ERROR 2
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+#define CY_CFG_SYSCLK_FLL_ERROR 4
+#define CY_CFG_SYSCLK_WCO_ERROR 5
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE CY_SYSTICK_CLOCK_SOURCE_CLK_LF
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_INTERVAL 0
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_FREQUENCY 32768
+#define CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS ((0)/1000000.0)*32768
+#define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
+#define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
+#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
+#define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
+#define CY_CFG_SYSCLK_FLL_ENABLED 1
+#define CY_CFG_SYSCLK_FLL_MULT 500U
+#define CY_CFG_SYSCLK_FLL_REFDIV 20U
+#define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
+#define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
+#define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
+#define CY_CFG_SYSCLK_FLL_IGAIN 9U
+#define CY_CFG_SYSCLK_FLL_PGAIN 5U
+#define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
+#define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
+#define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
+#define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
+#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
+#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
+#define CY_CFG_SYSCLK_ILO_ENABLED 1
+#define CY_CFG_SYSCLK_ILO_HIBERNATE true
+#define CY_CFG_SYSCLK_IMO_ENABLED 1
+#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
+#define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL
+#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
+#define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
+#define CY_CFG_SYSCLK_PLL0_ENABLED 1
+#define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30
+#define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5
+#define CY_CFG_SYSCLK_PLL0_LF_MODE false
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
+#define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
+#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
+#define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
+#define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
+#define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
+#define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
+#define CY_CFG_SYSCLK_WCO_ENABLED 1
+#define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_IN_PIN 0U
+#define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
+#define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
+#define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
+#define CY_CFG_PWR_ENABLED 1
+#define CY_CFG_PWR_INIT 1
+#define CY_CFG_PWR_USING_PMIC 0
+#define CY_CFG_PWR_VBACKUP_USING_VDDD 1
+#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
+#define CY_CFG_PWR_USING_ULP 0
+#define CY_CFG_PWR_REGULATOR_MODE_MIN false
+#define CY_CFG_PWR_BKP_ERROR 6
+
+#if defined (CY_DEVICE_SECURE)
+    static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig;
+#endif //defined (CY_DEVICE_SECURE)
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
+    {
+        .fllMult = 500U,
+        .refDiv = 20U,
+        .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
+        .enableOutputDiv = true,
+        .lockTolerance = 10U,
+        .igain = 9U,
+        .pgain = 5U,
+        .settlingCount = 8U,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
+        .cco_Freq = 355U,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 0U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 1U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 2U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 3U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 4U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
+    {
+        .type = CYHAL_RSC_CLKPATH,
+        .block_num = 5U,
+        .channel_num = 0U,
+    };
+#endif //defined (CY_USING_HAL)
+#if (!defined(CY_DEVICE_SECURE))
+    static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
+    {
+        .feedbackDiv = 30,
+        .referenceDiv = 1,
+        .outputDiv = 5,
+        .lfMode = false,
+        .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+    };
+#endif //(!defined(CY_DEVICE_SECURE))
+
+__WEAK void __NO_RETURN cycfg_ClockStartupError(uint32_t error)
+{
+    (void)error; /* Suppress the compiler warning */
+    while(1);
+}
+#if defined (CY_DEVICE_SECURE)
+    void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config)
+    {
+        #ifdef CY_CFG_PWR_ENABLED
+            secure_config->powerEnable = CY_CFG_PWR_ENABLED;
+        #endif /* CY_CFG_PWR_ENABLED */
+
+        #ifdef CY_CFG_PWR_USING_LDO
+            secure_config->ldoEnable = CY_CFG_PWR_USING_LDO;
+        #endif /* CY_CFG_PWR_USING_LDO */
+
+        #ifdef CY_CFG_PWR_USING_PMIC
+            secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC;
+        #endif /* CY_CFG_PWR_USING_PMIC */
+
+        #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD
+            secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD;
+        #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+
+        #ifdef CY_CFG_PWR_USING_ULP
+            secure_config->ulpEnable = CY_CFG_PWR_USING_ULP;
+        #endif /* CY_CFG_PWR_USING_ULP */
+
+        #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+            secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ECO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+            secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+            secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+            secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+            secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED;
+        #endif /* CY_CFG_SYSCLK_FLL_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+            secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+            secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+            secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+            secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+            secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+            secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+            secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+            secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+            secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+            secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+            secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
+            secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+            secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+            secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+            secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+            secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+            secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+            secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+            secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+            secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+            #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
+        #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+            secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED;
+        #endif /* CY_CFG_SYSCLK_PILO_ENABLED */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
+            secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED;
+        #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */
+
+        #ifdef CY_CFG_PWR_LDO_VOLTAGE
+            secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE;
+        #endif /* CY_CFG_PWR_LDO_VOLTAGE */
+
+        #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN
+            secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN;
+        #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+
+        #ifdef CY_CFG_PWR_BUCK_VOLTAGE
+            secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE;
+        #endif /* CY_CFG_PWR_BUCK_VOLTAGE */
+
+        #ifdef CY_CFG_SYSCLK_ECO_FREQ
+            secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ;
+        #endif /* CY_CFG_SYSCLK_ECO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_ECO_CLOAD
+            secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD;
+        #endif /* CY_CFG_SYSCLK_ECO_CLOAD */
+
+        #ifdef CY_CFG_SYSCLK_ECO_ESR
+            secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR;
+        #endif /* CY_CFG_SYSCLK_ECO_ESR */
+
+        #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL
+            secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL;
+        #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT
+            secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT
+            secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN
+            secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */
+
+        #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN
+            secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN;
+        #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+            secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT
+            secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN
+            secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM
+            secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM;
+        #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */
+
+        #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE
+            secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE;
+        #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */
+
+        #ifdef CY_CFG_SYSCLK_WCO_BYPASS
+            secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS;
+        #endif /* CY_CFG_SYSCLK_WCO_BYPASS */
+
+        #ifdef CY_CFG_SYSCLK_WCO_IN_PRT
+            secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT;
+        #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */
+
+        #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT
+            secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT;
+        #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */
+
+        #ifdef CY_CFG_SYSCLK_WCO_IN_PIN
+            secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN;
+        #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */
+
+        #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN
+            secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN;
+        #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ
+            secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_FLL_MULT
+            secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT;
+        #endif /* CY_CFG_SYSCLK_FLL_MULT */
+
+        #ifdef CY_CFG_SYSCLK_FLL_REFDIV
+            secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV;
+        #endif /* CY_CFG_SYSCLK_FLL_REFDIV */
+
+        #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE
+            secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE;
+        #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV
+            secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV;
+        #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */
+
+        #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE
+            secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE;
+        #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_IGAIN
+            secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN;
+        #endif /* CY_CFG_SYSCLK_FLL_IGAIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_PGAIN
+            secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN;
+        #endif /* CY_CFG_SYSCLK_FLL_PGAIN */
+
+        #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT
+            secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT;
+        #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */
+
+        #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE
+            secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ
+            secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ;
+        #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV
+            secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV
+            secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV
+            secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE
+            secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE
+            secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ
+            secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV
+            secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV
+            secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV
+            secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE
+            secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE
+            secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */
+
+        #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ
+            secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ;
+        #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE
+            secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE
+            secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE
+            secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE
+            secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE
+            secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE
+            secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER
+            secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER
+            secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER
+            secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH
+            secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER
+            secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ
+            secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH
+            secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER
+            secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ
+            secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH
+            secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER
+            secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ
+            secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH
+            secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER
+            secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ
+            secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH
+            secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER
+            secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ
+            secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH
+            secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER
+            secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ
+            secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ;
+        #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE
+            secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER
+            secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE
+            secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE
+            secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE
+            secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER
+            secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER;
+        #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE
+            secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE;
+        #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD
+            secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME
+            secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ
+            secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV
+            secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */
+
+        #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR
+            secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR;
+        #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
+    }
+#endif //defined (CY_DEVICE_SECURE)
+__STATIC_INLINE void Cy_SysClk_ClkAltSysTickInit()
+{
+ Cy_SysTick_Init(CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE, CY_CFG_SYSCLK_CLKALTSYSTICK_TICKS);
+}
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkBakInit()
+    {
+        Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkFastInit()
+    {
+        Cy_SysClk_ClkFastSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_FllInit()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
+    {
+        Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
+        Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_IloInit()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_IloEnable();
+        Cy_SysClk_IloHibernateOn(true);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkLfInit()
+    {
+        /* The WDT is unlocked in the default startup code */
+        Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
+    {
+        Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
+    {
+        Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
+    {
+        Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
+    {
+        Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
+    {
+        Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPath5Init()
+    {
+        Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
+    {
+        Cy_SysClk_ClkPeriSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_Pll0Init()
+    {
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkSlowInit()
+    {
+        Cy_SysClk_ClkSlowSetDivider(0U);
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_ClkTimerInit()
+    {
+        Cy_SysClk_ClkTimerDisable();
+        Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
+        Cy_SysClk_ClkTimerSetDivider(0U);
+        Cy_SysClk_ClkTimerEnable();
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void Cy_SysClk_WcoInit()
+    {
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
+        if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
+        {
+            cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
+        }
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+#if (!defined(CY_DEVICE_SECURE))
+    __STATIC_INLINE void init_cycfg_power(void)
+    {
+        /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
+         #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
+             #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+                 if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
+                 {
+                 #if CY_CFG_SYSCLK_WCO_ENABLED
+                     uint32_t wcoTrim = Cy_SysLib_GetWcoTrim();
+                     if (CY_SYSLIB_SUCCESS != Cy_SysLib_ResetBackupDomain())
+                     {
+                         Cy_SysLib_DelayUs(1U);
+                         if (CY_SYSLIB_SUCCESS != Cy_SysLib_GetResetStatus())
+                         {
+                             cycfg_ClockStartupError(CY_CFG_PWR_BKP_ERROR);
+                         }
+                     }
+                     Cy_SysLib_SetWcoTrim(wcoTrim);
+                 #else /* CY_CFG_SYSCLK_WCO_ENABLED */
+                     (void) Cy_SysLib_ResetBackupDomain();
+                 #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
+                    Cy_SysClk_IloDisable();
+                    Cy_SysClk_IloInit();
+                }
+            #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
+        #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
+        /* Configure core regulator */
+        #if !(defined(CY_DEVICE_SECURE))
+            #if defined (CY_IP_M4CPUSS)
+                #if CY_CFG_PWR_USING_LDO
+                    Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
+                #else
+                    Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
+                #endif /* CY_CFG_PWR_USING_LDO */
+            #endif /* defined (CY_IP_M4CPUSS) */
+            #if CY_CFG_PWR_REGULATOR_MODE_MIN
+                Cy_SysPm_SystemSetMinRegulatorCurrent();
+            #else
+                Cy_SysPm_SystemSetNormalRegulatorCurrent();
+            #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
+        #endif /* !(defined(CY_DEVICE_SECURE)) */
+        /* Configure PMIC */
+        Cy_SysPm_UnlockPmic();
+        #if CY_CFG_PWR_USING_PMIC
+            Cy_SysPm_PmicEnableOutput();
+        #else
+            Cy_SysPm_PmicDisableOutput();
+        #endif /* CY_CFG_PWR_USING_PMIC */
+    }
+#endif //(!defined(CY_DEVICE_SECURE))
+
+
+void init_cycfg_system(void)
+{
+    #if defined(CY_DEVICE_SECURE)
+        cy_en_pra_status_t configStatus;
+        init_cycfg_secure_struct(&srss_0_clock_0_secureConfig);
+        #if (((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM <= 5UL))  && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+        #if (((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM >= 3UL) && (CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM <= 5UL)) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL))
+            #error Configuration Error : ALTHF, ILO, PILO cannot drive HF0.
+        #endif
+
+        configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
+                                    CY_PRA_FUNC_INIT_CYCFG_DEVICE,
+                                    &srss_0_clock_0_secureConfig);
+        if ( configStatus != CY_PRA_STATUS_SUCCESS )
+        {
+            cycfg_ClockStartupError(configStatus);
+        }
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
+            Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);
+        #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
+    #else /* defined(CY_DEVICE_SECURE) */
+
+        /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
+        Cy_SysLib_SetWaitStates(false, 150UL);
+        #ifdef CY_CFG_PWR_ENABLED
+            #ifdef CY_CFG_PWR_INIT
+                init_cycfg_power();
+            #else
+                #warning Power system will not be configured. Update power personality to v1.20 or later.
+            #endif /* CY_CFG_PWR_INIT */
+        #endif /* CY_CFG_PWR_ENABLED */
+
+        /* Reset the core clock path to default and disable all the FLLs/PLLs */
+        Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
+        Cy_SysClk_ClkFastSetDivider(0U);
+        Cy_SysClk_ClkPeriSetDivider(1U);
+        Cy_SysClk_ClkSlowSetDivider(0U);
+        for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
+        {
+            (void)Cy_SysClk_PllDisable(pll);
+        }
+        Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
+
+        if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
+            (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
+        {
+            Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+        }
+
+        Cy_SysClk_FllDisable();
+        Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
+        Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
+        #ifdef CY_IP_MXBLESS
+            (void)Cy_BLE_EcoReset();
+        #endif
+
+
+        /* Enable all source clocks */
+        #ifdef CY_CFG_SYSCLK_PILO_ENABLED
+            Cy_SysClk_PiloInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_WCO_ENABLED
+            Cy_SysClk_WcoInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            Cy_SysClk_ClkLfInit();
+        #endif
+
+        #if (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED)
+
+            Cy_SysClk_AltHfInit();
+        #endif /* (defined(CY_IP_M4CPUSS) && CY_CFG_SYSCLK_ALTHF_ENABLED */
+
+
+        #ifdef CY_CFG_SYSCLK_ECO_ENABLED
+            Cy_SysClk_EcoInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
+            Cy_SysClk_ExtClkInit();
+        #endif
+
+        /* Configure CPU clock dividers */
+        #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
+            Cy_SysClk_ClkFastInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
+            Cy_SysClk_ClkPeriInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
+            Cy_SysClk_ClkSlowInit();
+        #endif
+
+        #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+            /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
+            Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
+            Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+        #else
+            #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+                Cy_SysClk_ClkPath1Init();
+            #endif
+        #endif
+
+        /* Configure Path Clocks */
+        #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
+            Cy_SysClk_ClkPath0Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
+            Cy_SysClk_ClkPath2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
+            Cy_SysClk_ClkPath3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
+            Cy_SysClk_ClkPath4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
+            Cy_SysClk_ClkPath5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
+            Cy_SysClk_ClkPath6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
+            Cy_SysClk_ClkPath7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
+            Cy_SysClk_ClkPath8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
+            Cy_SysClk_ClkPath9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
+            Cy_SysClk_ClkPath10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
+            Cy_SysClk_ClkPath11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
+            Cy_SysClk_ClkPath12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
+            Cy_SysClk_ClkPath13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
+            Cy_SysClk_ClkPath14Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
+            Cy_SysClk_ClkPath15Init();
+        #endif
+
+        /* Configure and enable FLL */
+        #ifdef CY_CFG_SYSCLK_FLL_ENABLED
+            Cy_SysClk_FllInit();
+        #endif
+
+        Cy_SysClk_ClkHf0Init();
+
+        #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
+            #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
+                /* Apply the ClkPath1 user setting */
+                Cy_SysClk_ClkPath1Init();
+            #endif
+        #endif
+
+        /* Configure and enable PLLs */
+        #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
+            Cy_SysClk_Pll0Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
+            Cy_SysClk_Pll1Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
+            Cy_SysClk_Pll2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
+            Cy_SysClk_Pll3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
+            Cy_SysClk_Pll4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
+            Cy_SysClk_Pll5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
+            Cy_SysClk_Pll6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
+            Cy_SysClk_Pll7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
+            Cy_SysClk_Pll8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
+            Cy_SysClk_Pll9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
+            Cy_SysClk_Pll10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
+            Cy_SysClk_Pll11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
+            Cy_SysClk_Pll12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
+            Cy_SysClk_Pll13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
+            Cy_SysClk_Pll14Init();
+        #endif
+
+        /* Configure HF clocks */
+        #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
+            Cy_SysClk_ClkHf1Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
+            Cy_SysClk_ClkHf2Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
+            Cy_SysClk_ClkHf3Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
+            Cy_SysClk_ClkHf4Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
+            Cy_SysClk_ClkHf5Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
+            Cy_SysClk_ClkHf6Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
+            Cy_SysClk_ClkHf7Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
+            Cy_SysClk_ClkHf8Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
+            Cy_SysClk_ClkHf9Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
+            Cy_SysClk_ClkHf10Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
+            Cy_SysClk_ClkHf11Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
+            Cy_SysClk_ClkHf12Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
+            Cy_SysClk_ClkHf13Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
+            Cy_SysClk_ClkHf14Init();
+        #endif
+        #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
+            Cy_SysClk_ClkHf15Init();
+        #endif
+
+        /* Configure miscellaneous clocks */
+        #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
+            Cy_SysClk_ClkTimerInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
+            Cy_SysClk_ClkAltSysTickInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
+            Cy_SysClk_ClkPumpInit();
+        #endif
+
+        #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
+            Cy_SysClk_ClkBakInit();
+        #endif
+
+        /* Configure default enabled clocks */
+        #ifdef CY_CFG_SYSCLK_ILO_ENABLED
+            Cy_SysClk_IloInit();
+        #endif
+
+        #ifndef CY_CFG_SYSCLK_IMO_ENABLED
+            #error the IMO must be enabled for proper chip operation
+        #endif
+
+        #ifndef CY_CFG_SYSCLK_CLKHF0_ENABLED
+            #error the CLKHF0 must be enabled for proper chip operation
+        #endif
+
+    #endif /* defined(CY_DEVICE_SECURE) */
+
+    #ifdef CY_CFG_SYSCLK_MFO_ENABLED
+        Cy_SysClk_MfoInit();
+    #endif
+
+    #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
+        Cy_SysClk_ClkMfInit();
+    #endif
+
+    #if (!defined(CY_DEVICE_SECURE))
+        /* Set accurate flash wait states */
+        #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
+            Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
+        #endif
+
+        /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
+        SystemCoreClockUpdate();
+        #ifndef CY_CFG_SYSCLK_ILO_ENABLED
+            #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
+            /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */
+            Cy_SysLib_DelayUs(200U);
+            #endif
+        Cy_SysClk_IloDisable();
+        Cy_SysClk_IloHibernateOn(false);
+        #endif
+
+    #endif /* (!defined(CY_DEVICE_SECURE)) */
+
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
+#endif //defined (CY_USING_HAL)
+
+#if defined (CY_USING_HAL)
+    cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
+#endif //defined (CY_USING_HAL)
+}

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h

@@ -0,0 +1,116 @@
+/*******************************************************************************
+* File Name: cycfg_system.h
+*
+* Description:
+* System configuration
+* This file was automatically generated and should not be modified.
+* Tools Package 2.4.0.5972
+* mtb-pdl-cat1 2.4.0.13881
+* personalities 6.0.0.0
+* udd 3.0.0.1974
+*
+********************************************************************************
+* Copyright 2022 Cypress Semiconductor Corporation (an Infineon company) or
+* an affiliate of Cypress Semiconductor Corporation.
+* SPDX-License-Identifier: Apache-2.0
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+********************************************************************************/
+
+#if !defined(CYCFG_SYSTEM_H)
+#define CYCFG_SYSTEM_H
+
+#include "cycfg_notices.h"
+#include "cy_sysclk.h"
+#include "cy_pra.h"
+#include "cy_pra_cfg.h"
+#include "cy_systick.h"
+#if defined (CY_USING_HAL)
+    #include "cyhal_hwmgr.h"
+#endif //defined (CY_USING_HAL)
+#include "cy_gpio.h"
+#include "cy_syspm.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#define cpuss_0_dap_0_ENABLED 1U
+#define srss_0_clock_0_ENABLED 1U
+#define srss_0_clock_0_altsystickclk_0_ENABLED 1U
+#define srss_0_clock_0_bakclk_0_ENABLED 1U
+#define srss_0_clock_0_fastclk_0_ENABLED 1U
+#define srss_0_clock_0_fll_0_ENABLED 1U
+#define srss_0_clock_0_hfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKHF0 0UL
+#define CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM 0UL
+#define srss_0_clock_0_ilo_0_ENABLED 1U
+#define srss_0_clock_0_imo_0_ENABLED 1U
+#define srss_0_clock_0_lfclk_0_ENABLED 1U
+#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768
+#define CY_CFG_SYSCLK_CLKLF_SOURCE CY_SYSCLK_CLKLF_IN_WCO
+#define srss_0_clock_0_pathmux_0_ENABLED 1U
+#define srss_0_clock_0_pathmux_1_ENABLED 1U
+#define srss_0_clock_0_pathmux_2_ENABLED 1U
+#define srss_0_clock_0_pathmux_3_ENABLED 1U
+#define srss_0_clock_0_pathmux_4_ENABLED 1U
+#define srss_0_clock_0_pathmux_5_ENABLED 1U
+#define srss_0_clock_0_periclk_0_ENABLED 1U
+#define srss_0_clock_0_pll_0_ENABLED 1U
+#define srss_0_clock_0_slowclk_0_ENABLED 1U
+#define srss_0_clock_0_timerclk_0_ENABLED 1U
+#define srss_0_clock_0_wco_0_ENABLED 1U
+#define srss_0_power_0_ENABLED 1U
+#define CY_CFG_PWR_MODE_LP 0x01UL
+#define CY_CFG_PWR_MODE_ULP 0x02UL
+#define CY_CFG_PWR_MODE_ACTIVE 0x04UL
+#define CY_CFG_PWR_MODE_SLEEP 0x08UL
+#define CY_CFG_PWR_MODE_DEEPSLEEP 0x10UL
+#define CY_CFG_PWR_SYS_IDLE_MODE CY_CFG_PWR_MODE_DEEPSLEEP
+#define CY_CFG_PWR_SYS_ACTIVE_MODE CY_CFG_PWR_MODE_LP
+#define CY_CFG_PWR_DEEPSLEEP_LATENCY 0UL
+#define CY_CFG_PWR_USING_LDO 1
+#define CY_CFG_PWR_VDDA_MV 3300
+#define CY_CFG_PWR_VDDD_MV 3300
+#define CY_CFG_PWR_VBACKUP_MV 3300
+#define CY_CFG_PWR_VDD_NS_MV 3300
+#define CY_CFG_PWR_VDDIO0_MV 3300
+#define CY_CFG_PWR_VDDIO1_MV 3300
+
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj;
+#endif //defined (CY_USING_HAL)
+#if defined (CY_USING_HAL)
+    extern const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj;
+#endif //defined (CY_USING_HAL)
+
+void init_cycfg_system(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+
+#endif /* CYCFG_SYSTEM_H */

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg

@@ -0,0 +1,29 @@
+################################################################################
+# File Name: qspi_config.cfg
+#
+# Description:
+# This file contains a SMIF Bank layout for use with OpenOCD.
+# This file was automatically generated and should not be modified.
+# QSPI Configurator: 2.20.0.2857
+#
+################################################################################
+# Copyright 2020 Cypress Semiconductor Corporation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+################################################################################
+
+set SMIF_BANKS {
+  0 {addr 0x18000000 size 0x4000000 psize 0x00000200 esize 0x00040000}
+}
+

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list

@@ -0,0 +1,20 @@
+[Device=CY8C624ABZI-S2D44]
+
+[Blocks]
+# WIFI
+# CYBSP_WIFI_SDIO
+sdhc[0]
+# CYBSP_WIFI_SDIO_D0
+ioss[0].port[2].pin[0]
+# CYBSP_WIFI_SDIO_D1
+ioss[0].port[2].pin[1]
+# CYBSP_WIFI_SDIO_D2
+ioss[0].port[2].pin[2]
+# CYBSP_WIFI_SDIO_D3
+ioss[0].port[2].pin[3]
+# CYBSP_WIFI_SDIO_CMD
+ioss[0].port[2].pin[4]
+# CYBSP_WIFI_SDIO_CLK
+ioss[0].port[2].pin[5]
+# CYBSP_WIFI_WL_REG_ON
+ioss[0].port[2].pin[6]

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense

@@ -0,0 +1,415 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by CapSense Configurator 4.0.0.5470-->
+<Configuration app="Capsense" major="4" minor="0" lastSavedWithToolName="CapSense Configurator" formatVersion="1">
+    <DesignProperties>
+        <Property id="DEVICE_TYPE" value="P6_CSDV2"/>
+    </DesignProperties>
+    <GeneralProperties>
+        <Property id="REGULAR_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="REGULAR_IIR_RC_N" value="128"/>
+        <Property id="REGULAR_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="REGULAR_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="PROX_RC_IIR_FILTER_EN" value="false"/>
+        <Property id="PROX_IIR_RC_N" value="128"/>
+        <Property id="PROX_RC_MEDIAN_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_FILTER_EN" value="false"/>
+        <Property id="PROX_RC_AVERAGE_SAMPLE_SIZE" value="SAMPLE_4"/>
+        <Property id="REGULAR_IIR_BL_N" value="1"/>
+        <Property id="REGULAR_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="PROX_IIR_BL_N" value="1"/>
+        <Property id="PROX_IIR_BL_TYPE" value="PERFORMANCE"/>
+        <Property id="MULTI_FREQ_SCAN_EN" value="false"/>
+        <Property id="SENSOR_AUTO_RESET_EN" value="false"/>
+        <Property id="SLIDER_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="TOUCHPAD_MULTIPLIER" value="SNS_NUM_MINUS_1"/>
+        <Property id="BLOCK_ANALOG_WAKEUP_DELAY_US" value="25"/>
+        <Property id="VREF_SOURCE" value="SRSS"/>
+        <Property id="IREF_SOURCE" value="SRSS"/>
+        <Property id="PROX_TOUCH_COEFF" value="300"/>
+        <Property id="BIST_EN" value="false"/>
+        <Property id="BIST_SHIELD_CAP_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSD_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_SNS_CAP_CSX_ISC" value="BIST_IO_STRONG"/>
+        <Property id="BIST_FINE_INIT_TIME" value="10"/>
+        <Property id="BIST_ELTD_CAP_MOD_CLC_DIVIDER" value="2"/>
+        <Property id="BIST_ELTD_CAP_SNS_CLC_DIVIDER" value="0"/>
+        <Property id="BIST_ELTD_CAP_RESOLUTION" value="12"/>
+        <Property id="BIST_ELTD_CAP_VREF_MV" value="1200"/>
+        <Property id="BIST_SHORT_SETTLING_TIME" value="2"/>
+        <Property id="VDDA_MOD_CLK" value="2"/>
+        <Property id="VDDA_VREF_MV" value="1200"/>
+        <Property id="EXT_CAP_MOD_CLK" value="2"/>
+        <Property id="EXT_CAP_SNS_CLK" value="1024"/>
+        <Property id="EXT_CAP_VREF_MV" value="1200"/>
+        <Property id="NUM_CENTROIDS" value="1"/>
+    </GeneralProperties>
+    <CsdProperties>
+        <Property id="CSD_AUTOTUNE" value="HWTH"/>
+        <Property id="CSD_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSD_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSD_CHARGE_TRANSFER" value="SOURCING"/>
+        <Property id="CSD_IDAC_ROW_COL_ALIGN_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSD_IDAC_AUTOGAIN_EN" value="true"/>
+        <Property id="CSD_IDAC_GAIN_INIT_INDEX" value="GAIN_2400"/>
+        <Property id="CSD_IDAC_MIN" value="20"/>
+        <Property id="CSD_IDAC_COMP_EN" value="true"/>
+        <Property id="CSD_RAWCOUNT_CAL_LEVEL" value="85"/>
+        <Property id="CSD_VREF_CUSTOM" value="false"/>
+        <Property id="CSD_VREF" value="1219"/>
+        <Property id="CSD_SHIELD_EN" value="false"/>
+        <Property id="CSD_SHIELD_TANK_EN" value="false"/>
+        <Property id="CSD_SHIELD_DELAY" value="DELAY_0NS"/>
+        <Property id="CSD_TOTAL_SHIELD_COUNT" value="1"/>
+        <Property id="CSD_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSD_FINE_INIT_TIME" value="10"/>
+        <Property id="CSD_CALIBRATION_ERROR" value="10"/>
+        <Property id="CSD_R_CONST" value="1000"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSD_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsdProperties>
+    <CsxProperties>
+        <Property id="CSX_MOD_CLK_DIVIDER" value="2"/>
+        <Property id="CSX_INACTIVE_SNS_CONNECTION" value="GROUND"/>
+        <Property id="CSX_MAX_FINGERS" value="3"/>
+        <Property id="CSX_IDAC_GAIN_INIT_INDEX" value="GAIN_300"/>
+        <Property id="CSX_IDAC_AUTOCAL_EN" value="true"/>
+        <Property id="CSX_RAWCOUNT_CAL_LEVEL" value="40"/>
+        <Property id="CSX_INIT_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_INIT_SHIELD_SWITCH_RES" value="MEDIUM"/>
+        <Property id="CSX_SCAN_SHIELD_SWITCH_RES" value="LOW"/>
+        <Property id="CSX_FINE_INIT_TIME" value="10"/>
+        <Property id="CSX_CALIBRATION_ERROR" value="20"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F1" value="1"/>
+        <Property id="CSX_MFS_DIVIDER_OFFSET_F2" value="2"/>
+    </CsxProperties>
+    <Widgets>
+        <Widget id="Button0" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="Button1" type="CSX_BUTTON">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_300"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Rx0" kind="Column">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Tx" kind="Row">
+                    <ElectrodeProperties>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+        <Widget id="LinearSlider0" type="LINEAR_SLIDER">
+            <WidgetProperties>
+                <Property id="DIPLEXING" value="false"/>
+                <Property id="MAX_POS_X" value="300"/>
+                <Property id="MAX_POS_Y" value="300"/>
+                <Property id="FINGER_CP" value="0.16"/>
+                <Property id="SNS_CLK" value="16"/>
+                <Property id="ROW_SNS_CLK" value="16"/>
+                <Property id="SNS_CLK_SOURCE" value="AUTO"/>
+                <Property id="TX_CLK" value="32"/>
+                <Property id="TX_CLK_SOURCE" value="AUTO"/>
+                <Property id="RESOLUTION" value="RES12BIT"/>
+                <Property id="NUM_CONV" value="100"/>
+                <Property id="IDAC_MOD0" value="32"/>
+                <Property id="IDAC_MOD1" value="32"/>
+                <Property id="IDAC_MOD2" value="32"/>
+                <Property id="ROW_IDAC_MOD0" value="32"/>
+                <Property id="ROW_IDAC_MOD1" value="32"/>
+                <Property id="ROW_IDAC_MOD2" value="32"/>
+                <Property id="IDAC_GAIN_INDEX" value="GAIN_2400"/>
+                <Property id="FINGER_TH" value="100"/>
+                <Property id="PROX_TOUCH_TH" value="200"/>
+                <Property id="NOISE_TH" value="40"/>
+                <Property id="NNOISE_TH" value="40"/>
+                <Property id="LOW_BSLN_RST" value="30"/>
+                <Property id="HYSTERESIS" value="10"/>
+                <Property id="ON_DEBOUNCE" value="3"/>
+                <Property id="VELOCITY" value="45000"/>
+                <Property id="IIR_FILTER" value="false"/>
+                <Property id="IIR_FILTER_COEFF" value="128"/>
+                <Property id="MEDIAN_FILTER" value="false"/>
+                <Property id="AVG_FILTER" value="false"/>
+                <Property id="JITTER_FILTER" value="false"/>
+                <Property id="AIIR_FILTER" value="false"/>
+                <Property id="AIIR_NO_MOV_TH" value="3"/>
+                <Property id="AIIR_LITTLE_MOV_TH" value="7"/>
+                <Property id="AIIR_LARGE_MOV_TH" value="12"/>
+                <Property id="AIIR_MAXK" value="60"/>
+                <Property id="AIIR_MINK" value="1"/>
+                <Property id="AIIR_DIV_VAL" value="64"/>
+                <Property id="CENTROID_TYPE" value="CSD3X3"/>
+                <Property id="CROSS_COUPLING_POS_TH" value="5"/>
+                <Property id="EDGE_CORRECTION" value="true"/>
+                <Property id="EDGE_VIRTUAL_SENSOR_TH" value="100"/>
+                <Property id="EDGE_PENULTIMATE_TH" value="100"/>
+                <Property id="TWO_FINGER_DETECTION" value="false"/>
+                <Property id="BALLISTIC_MULT" value="false"/>
+                <Property id="ACCEL_COEFF" value="9"/>
+                <Property id="SPEED_COEFF" value="2"/>
+                <Property id="DIVISOR" value="4"/>
+                <Property id="SPEED_TH_X" value="3"/>
+                <Property id="SPEED_TH_Y" value="4"/>
+                <Property id="GESTURE_ENABLE" value="false"/>
+                <Property id="GESTURE_1F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_DOUBLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_CLICK_DRAG_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SINGLE_CLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_SCROLL_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_EDGE_SWIPE_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_FLICK_ENABLE" value="true"/>
+                <Property id="GESTURE_1F_ROTATE_ENABLE" value="true"/>
+                <Property id="GESTURE_2F_ZOOM_ENABLE" value="true"/>
+                <Property id="GESTURE_FILTERING_ENABLE" value="false"/>
+                <Property id="CLICK_TIMEOUT_MAX" value="1000"/>
+                <Property id="CLICK_TIMEOUT_MIN" value="0"/>
+                <Property id="CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SECOND_CLICK_INTERVAL_MAX" value="1000"/>
+                <Property id="SECOND_CLICK_INTERVAL_MIN" value="0"/>
+                <Property id="SECOND_CLICK_DISTANCE_MAX" value="100"/>
+                <Property id="SCROLL_DEBOUNCE" value="3"/>
+                <Property id="SCROLL_DISTANCE_MIN" value="20"/>
+                <Property id="ROTATE_DEBOUNCE" value="10"/>
+                <Property id="ROTATE_DISTANCE_MIN" value="50"/>
+                <Property id="ZOOM_DEBOUNCE" value="3"/>
+                <Property id="ZOOM_DISTANCE_MIN" value="50"/>
+                <Property id="FLICK_TIMEOUT_MAX" value="300"/>
+                <Property id="FLICK_DISTANCE_MIN" value="100"/>
+                <Property id="EDGE_EDGE_SIZE" value="200"/>
+                <Property id="EDGE_DISTANCE_MIN" value="200"/>
+                <Property id="EDGE_TIMEOUT_MAX" value="2000"/>
+                <Property id="EDGE_ANGLE_MAX" value="45"/>
+            </WidgetProperties>
+            <Electrodes>
+                <Electrode id="Sns0" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns1" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns2" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns3" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+                <Electrode id="Sns4" kind="Sensor">
+                    <ElectrodeProperties>
+                        <Property id="IDAC0" value="32"/>
+                        <Property id="IDAC1" value="32"/>
+                        <Property id="IDAC2" value="32"/>
+                        <Property id="PINS" value="Dedicated pin"/>
+                    </ElectrodeProperties>
+                </Electrode>
+            </Electrodes>
+        </Widget>
+    </Widgets>
+</Configuration>

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi

@@ -0,0 +1,63 @@
+<?xml version="1.0"?>
+<!--This file should not be modified. It was automatically generated by QSPI Configurator 2.20.0.2857-->
+<Configuration app="QSPI" major="2" minor="20">
+    <DevicePath>PSoC 6.xml</DevicePath>
+    <SlotConfigs>
+        <SlotConfig>
+            <SlaveSlot>0</SlaveSlot>
+            <MemoryId>S25FL512S-4byteaddr</MemoryId>
+            <MemoryMapped>true</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18000000</StartAddress>
+            <Size>0x4000000</Size>
+            <EndAddress>0x1BFFFFFF</EndAddress>
+            <WriteEnable>true</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
+            <MemoryConfigsPath>S25FL512S-4byteaddr</MemoryConfigsPath>
+            <ConfigDataInFlash>true</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>1</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18010000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1801FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>2</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18020000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1802FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+        <SlotConfig>
+            <SlaveSlot>3</SlaveSlot>
+            <MemoryId>Not used</MemoryId>
+            <MemoryMapped>false</MemoryMapped>
+            <DualQuad>None</DualQuad>
+            <StartAddress>0x18030000</StartAddress>
+            <Size>0x10000</Size>
+            <EndAddress>0x1803FFFF</EndAddress>
+            <WriteEnable>false</WriteEnable>
+            <Encrypt>false</Encrypt>
+            <DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
+            <MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
+            <ConfigDataInFlash>false</ConfigDataInFlash>
+        </SlotConfig>
+    </SlotConfigs>
+</Configuration>

project_0/libraries/IFX_PSOC6_HAL/TARGET_CY8CKIT-062S2-43012/COMPONENT_BSP_DESIGN_MODUS/design.modus

@@ -0,0 +1,727 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<Design version="12" xmlns="http://cypress.com/xsd/cydesignfile_v3">
+    <ToolInfo version="2.4.0.5972"/>
+    <Devices>
+        <Device mpn="CY8C624ABZI-S2D44">
+            <BlockConfig>
+                <Block location="cpuss[0].dap[0]">
+                    <Personality template="mxs40dap" version="1.0">
+                        <Param id="dbgMode" value="SWD"/>
+                        <Param id="traceEnable" value="false"/>
+                    </Personality>
+                </Block>
+                <Block location="csd[0].csd[0]">
+                    <Alias value="CYBSP_CSD"/>
+                    <Personality template="mxs40csd" version="2.0">
+                        <Param id="CapSenseEnable" value="true"/>
+                        <Param id="CapSenseCore" value="4"/>
+                        <Param id="SensorCount" value="12"/>
+                        <Param id="CapacitorCount" value="3"/>
+                        <Param id="SensorName0" value="Cmod"/>
+                        <Param id="SensorName1" value="CintA"/>
+                        <Param id="SensorName2" value="CintB"/>
+                        <Param id="SensorName3" value="Button0_Rx0"/>
+                        <Param id="SensorName4" value="Button0_Tx"/>
+                        <Param id="SensorName5" value="Button1_Rx0"/>
+                        <Param id="SensorName6" value="Button1_Tx"/>
+                        <Param id="SensorName7" value="LinearSlider0_Sns0"/>
+                        <Param id="SensorName8" value="LinearSlider0_Sns1"/>
+                        <Param id="SensorName9" value="LinearSlider0_Sns2"/>
+                        <Param id="SensorName10" value="LinearSlider0_Sns3"/>
+                        <Param id="SensorName11" value="LinearSlider0_Sns4"/>
+                        <Param id="CapSenseConfigurator" value="0"/>
+                        <Param id="CapSenseTuner" value="0"/>
+                        <Param id="CsdAdcEnable" value="false"/>
+                        <Param id="numChannels" value="1"/>
+                        <Param id="resolution" value="CY_CSDADC_RESOLUTION_10BIT"/>
+                        <Param id="range" value="CY_CSDADC_RANGE_VDDA"/>
+                        <Param id="acqTime" value="10"/>
+                        <Param id="autoCalibrInterval" value="30"/>
+                        <Param id="vref" value="-1"/>
+                        <Param id="operClkDivider" value="1"/>
+                        <Param id="azTime" value="5"/>
+                        <Param id="csdInitTime" value="25"/>
+                        <Param id="inFlash" value="true"/>
+                        <Param id="CsdIdacEnable" value="false"/>
+                        <Param id="CsdIdacAselect" value="CY_CSDIDAC_GPIO"/>
+                        <Param id="CsdIdacBselect" value="CY_CSDIDAC_DISABLED"/>
+                        <Param id="csdIdacInitTime" value="25"/>
+                        <Param id="idacInFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[0]">
+                    <Alias value="CYBSP_WCO_IN"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[1]">
+                    <Alias value="CYBSP_WCO_OUT"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[0].pin[4]">
+                    <Alias value="CYBSP_SW2"/>
+                    <Alias value="CYBSP_USER_BTN1"/>
+                    <Alias value="CYBSP_USER_BTN"/>
+                </Block>
+                <Block location="ioss[0].port[0].pin[5]">
+                    <Alias value="CYBSP_LED_RGB_GREEN"/>
+                    <Alias value="CYBSP_USER_LED4"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[0]">
+                    <Alias value="CYBSP_A0"/>
+                    <Alias value="CYBSP_J2_1"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[1]">
+                    <Alias value="CYBSP_A1"/>
+                    <Alias value="CYBSP_J2_3"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[2]">
+                    <Alias value="CYBSP_A2"/>
+                    <Alias value="CYBSP_J2_5"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[3]">
+                    <Alias value="CYBSP_A3"/>
+                    <Alias value="CYBSP_J2_7"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[4]">
+                    <Alias value="CYBSP_A4"/>
+                    <Alias value="CYBSP_J2_9"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[5]">
+                    <Alias value="CYBSP_A5"/>
+                    <Alias value="CYBSP_J2_11"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[6]">
+                    <Alias value="CYBSP_A6"/>
+                    <Alias value="CYBSP_J2_13"/>
+                    <Alias value="CYBSP_POT"/>
+                </Block>
+                <Block location="ioss[0].port[10].pin[7]">
+                    <Alias value="CYBSP_A7"/>
+                    <Alias value="CYBSP_J2_15"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[0]">
+                    <Alias value="CYBSP_QSPI_FRAM_SSEL"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[1]">
+                    <Alias value="CYBSP_LED9"/>
+                    <Alias value="CYBSP_USER_LED2"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[2]">
+                    <Alias value="CYBSP_QSPI_SS"/>
+                    <Alias value="CYBSP_QSPI_FLASH_SSEL"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[3]">
+                    <Alias value="CYBSP_QSPI_D3"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[4]">
+                    <Alias value="CYBSP_QSPI_D2"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[5]">
+                    <Alias value="CYBSP_QSPI_D1"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[6]">
+                    <Alias value="CYBSP_QSPI_D0"/>
+                </Block>
+                <Block location="ioss[0].port[11].pin[7]">
+                    <Alias value="CYBSP_QSPI_SCK"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[0]">
+                    <Alias value="CYBSP_SPI_MOSI"/>
+                    <Alias value="CYBSP_D11"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[1]">
+                    <Alias value="CYBSP_SPI_MISO"/>
+                    <Alias value="CYBSP_D12"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[2]">
+                    <Alias value="CYBSP_SPI_CLK"/>
+                    <Alias value="CYBSP_D13"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[3]">
+                    <Alias value="CYBSP_SPI_CS"/>
+                    <Alias value="CYBSP_D10"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[4]">
+                    <Alias value="CYBSP_SDHC_CMD"/>
+                </Block>
+                <Block location="ioss[0].port[12].pin[5]">
+                    <Alias value="CYBSP_SDHC_CLK"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[0]">
+                    <Alias value="CYBSP_SDHC_IO0"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[1]">
+                    <Alias value="CYBSP_SDHC_IO1"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[2]">
+                    <Alias value="CYBSP_SDHC_IO2"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[3]">
+                    <Alias value="CYBSP_SDHC_IO3"/>
+                </Block>
+                <Block location="ioss[0].port[13].pin[7]">
+                    <Alias value="CYBSP_SDHC_DETECT"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[0]">
+                    <Alias value="CYBSP_CSD_RX"/>
+                    <Alias value="CYBSP_CS_RX"/>
+                    <Alias value="CYBSP_CS_TX_RX"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[1].pin[1]">
+                    <Alias value="CYBSP_LED_RGB_RED"/>
+                    <Alias value="CYBSP_USER_LED3"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[4]">
+                    <Alias value="CYBSP_SW4"/>
+                    <Alias value="CYBSP_USER_BTN2"/>
+                </Block>
+                <Block location="ioss[0].port[1].pin[5]">
+                    <Alias value="CYBSP_LED8"/>
+                    <Alias value="CYBSP_USER_LED1"/>
+                    <Alias value="CYBSP_USER_LED"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[0]">
+                    <Alias value="CYBSP_WIFI_SDIO_D0"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[1]">
+                    <Alias value="CYBSP_WIFI_SDIO_D1"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[2]">
+                    <Alias value="CYBSP_WIFI_SDIO_D2"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[3]">
+                    <Alias value="CYBSP_WIFI_SDIO_D3"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[4]">
+                    <Alias value="CYBSP_WIFI_SDIO_CMD"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[5]">
+                    <Alias value="CYBSP_WIFI_SDIO_CLK"/>
+                </Block>
+                <Block location="ioss[0].port[2].pin[6]">
+                    <Alias value="CYBSP_WIFI_WL_REG_ON"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[0]">
+                    <Alias value="CYBSP_BT_UART_RX"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[1]">
+                    <Alias value="CYBSP_BT_UART_TX"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[2]">
+                    <Alias value="CYBSP_BT_UART_RTS"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[3]">
+                    <Alias value="CYBSP_BT_UART_CTS"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[4]">
+                    <Alias value="CYBSP_BT_POWER"/>
+                </Block>
+                <Block location="ioss[0].port[3].pin[5]">
+                    <Alias value="CYBSP_BT_DEVICE_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[4].pin[0]">
+                    <Alias value="CYBSP_BT_HOST_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[4].pin[1]">
+                    <Alias value="CYBSP_WIFI_HOST_WAKE"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[0]">
+                    <Alias value="CYBSP_DEBUG_UART_RX"/>
+                    <Alias value="CYBSP_D0"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[1]">
+                    <Alias value="CYBSP_DEBUG_UART_TX"/>
+                    <Alias value="CYBSP_D1"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[2]">
+                    <Alias value="CYBSP_DEBUG_UART_RTS"/>
+                    <Alias value="CYBSP_D2"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[3]">
+                    <Alias value="CYBSP_DEBUG_UART_CTS"/>
+                    <Alias value="CYBSP_D3"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[4]">
+                    <Alias value="CYBSP_D4"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[5]">
+                    <Alias value="CYBSP_D5"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[6]">
+                    <Alias value="CYBSP_D6"/>
+                </Block>
+                <Block location="ioss[0].port[5].pin[7]">
+                    <Alias value="CYBSP_D7"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[0]">
+                    <Alias value="CYBSP_I2C_SCL"/>
+                    <Alias value="CYBSP_D15"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[1]">
+                    <Alias value="CYBSP_I2C_SDA"/>
+                    <Alias value="CYBSP_D14"/>
+                </Block>
+                <Block location="ioss[0].port[6].pin[4]">
+                    <Alias value="CYBSP_SWO"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_STRONG_IN_OFF"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[6].pin[6]">
+                    <Alias value="CYBSP_SWDIO"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_PULLUP"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[6].pin[7]">
+                    <Alias value="CYBSP_SWDCK"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_PULLDOWN"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[1]">
+                    <Alias value="CYBSP_CINA"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[2]">
+                    <Alias value="CYBSP_CINB"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[7].pin[3]">
+                    <Alias value="CYBSP_LED_RGB_BLUE"/>
+                    <Alias value="CYBSP_USER_LED5"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[5]">
+                    <Alias value="CYBSP_D8"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[6]">
+                    <Alias value="CYBSP_D9"/>
+                </Block>
+                <Block location="ioss[0].port[7].pin[7]">
+                    <Alias value="CYBSP_CMOD"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[1]">
+                    <Alias value="CYBSP_CSD_BTN0"/>
+                    <Alias value="CYBSP_CS_BTN0"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[2]">
+                    <Alias value="CYBSP_CSD_BTN1"/>
+                    <Alias value="CYBSP_CS_BTN1"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[3]">
+                    <Alias value="CYBSP_CSD_SLD0"/>
+                    <Alias value="CYBSP_CS_SLD0"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[4]">
+                    <Alias value="CYBSP_CSD_SLD1"/>
+                    <Alias value="CYBSP_CS_SLD1"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[5]">
+                    <Alias value="CYBSP_CSD_SLD2"/>
+                    <Alias value="CYBSP_CS_SLD2"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[6]">
+                    <Alias value="CYBSP_CSD_SLD3"/>
+                    <Alias value="CYBSP_CS_SLD3"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[8].pin[7]">
+                    <Alias value="CYBSP_CSD_SLD4"/>
+                    <Alias value="CYBSP_CS_SLD4"/>
+                    <Personality template="mxs40pin" version="1.1">
+                        <Param id="DriveModes" value="CY_GPIO_DM_ANALOG"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="inFlash" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="ioss[0].port[9].pin[0]">
+                    <Alias value="CYBSP_A8"/>
+                    <Alias value="CYBSP_J2_2"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[1]">
+                    <Alias value="CYBSP_A9"/>
+                    <Alias value="CYBSP_J2_4"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[2]">
+                    <Alias value="CYBSP_A10"/>
+                    <Alias value="CYBSP_J2_6"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[3]">
+                    <Alias value="CYBSP_A11"/>
+                    <Alias value="CYBSP_J2_8"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[4]">
+                    <Alias value="CYBSP_A12"/>
+                    <Alias value="CYBSP_J2_10"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[5]">
+                    <Alias value="CYBSP_A13"/>
+                    <Alias value="CYBSP_J2_12"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[6]">
+                    <Alias value="CYBSP_A14"/>
+                    <Alias value="CYBSP_J2_14"/>
+                </Block>
+                <Block location="ioss[0].port[9].pin[7]">
+                    <Alias value="CYBSP_A15"/>
+                    <Alias value="CYBSP_J2_16"/>
+                </Block>
+                <Block location="peri[0].div_8[0]">
+                    <Alias value="CYBSP_CSD_CLK_DIV"/>
+                    <Alias value="CYBSP_CS_CLK_DIV"/>
+                    <Personality template="mxs40peripheralclock" version="1.0">
+                        <Param id="intDivider" value="1"/>
+                        <Param id="fracDivider" value="0"/>
+                        <Param id="startOnReset" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0]">
+                    <Personality template="mxs40sysclocks" version="1.2"/>
+                </Block>
+                <Block location="srss[0].clock[0].altsystickclk[0]">
+                    <Personality template="mxs40altsystick" version="1.0">
+                        <Param id="sourceClock" value="lfclk"/>
+                        <Param id="interval" value="0"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].bakclk[0]">
+                    <Personality template="mxs40bakclk" version="1.0">
+                        <Param id="sourceClock" value="lfclk"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].fastclk[0]">
+                    <Personality template="mxs40fastclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].fll[0]">
+                    <Personality template="mxs40fll" version="2.0">
+                        <Param id="configuration" value="auto"/>
+                        <Param id="desiredFrequency" value="100.000"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].hfclk[0]">
+                    <Personality template="mxs40hfclk" version="1.1">
+                        <Param id="sourceClockNumber" value="0"/>
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].ilo[0]">
+                    <Personality template="mxs40ilo" version="1.0">
+                        <Param id="hibernate" value="true"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].imo[0]">
+                    <Personality template="mxs40imo" version="1.0">
+                        <Param id="trim" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].lfclk[0]">
+                    <Personality template="mxs40lfclk" version="1.1">
+                        <Param id="sourceClock" value="wco"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[0]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[1]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[2]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[3]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[4]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pathmux[5]">
+                    <Personality template="mxs40pathmux" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].periclk[0]">
+                    <Personality template="mxs40periclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].pll[0]">
+                    <Personality template="mxs40pll" version="2.0">
+                        <Param id="lowFrequencyMode" value="false"/>
+                        <Param id="configuration" value="auto"/>
+                        <Param id="desiredFrequency" value="48.000"/>
+                        <Param id="optimization" value="MinPower"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].slowclk[0]">
+                    <Personality template="mxs40slowclk" version="1.0">
+                        <Param id="divider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].timerclk[0]">
+                    <Personality template="mxs40timerclk" version="1.0">
+                        <Param id="sourceClock" value="imo"/>
+                        <Param id="timerDivider" value="1"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].clock[0].wco[0]">
+                    <Personality template="mxs40wco" version="1.0">
+                        <Param id="clockPort" value="CY_SYSCLK_WCO_NOT_BYPASSED"/>
+                        <Param id="clockLostDetection" value="false"/>
+                        <Param id="clockSupervisor" value="CY_SYSCLK_WCO_CSV_SUPERVISOR_ILO"/>
+                        <Param id="lossWindow" value="CY_SYSCLK_CSV_LOSS_4_CYCLES"/>
+                        <Param id="lossAction" value="CY_SYSCLK_CSV_ERROR_FAULT"/>
+                        <Param id="accuracyPpm" value="150"/>
+                    </Personality>
+                </Block>
+                <Block location="srss[0].power[0]">
+                    <Personality template="mxs40power" version="1.3">
+                        <Param id="pwrMode" value="LDO_1_1"/>
+                        <Param id="actPwrMode" value="LP"/>
+                        <Param id="coreRegulator" value="CY_SYSPM_LDO_MODE_NORMAL"/>
+                        <Param id="pmicEnable" value="false"/>
+                        <Param id="backupSrc" value="VDDD"/>
+                        <Param id="idlePwrMode" value="CY_CFG_PWR_MODE_DEEPSLEEP"/>
+                        <Param id="deepsleepLatency" value="0"/>
+                        <Param id="vddaMv" value="3300"/>
+                        <Param id="vdddMv" value="3300"/>
+                        <Param id="vBackupMv" value="3300"/>
+                        <Param id="vddNsMv" value="3300"/>
+                        <Param id="vddio0Mv" value="3300"/>
+                        <Param id="vddio1Mv" value="3300"/>
+                    </Personality>
+                </Block>
+            </BlockConfig>
+            <Netlist>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swclk_tclk[0]"/>
+                    <Port name="ioss[0].port[6].pin[7].digital_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swdio_tms[0]"/>
+                    <Port name="ioss[0].port[6].pin[6].digital_inout[0]"/>
+                </Net>
+                <Net>
+                    <Port name="cpuss[0].dap[0].swj_swo_tdo[0]"/>
+                    <Port name="ioss[0].port[6].pin[4].digital_out[0]"/>
+                </Net>
+                <Net>
+                    <Port name="csd[0].csd[0].clock[0]"/>
+                    <Port name="peri[0].div_8[0].clk[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[0].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_in[0]"/>
+                </Net>
+                <Net>
+                    <Port name="ioss[0].port[0].pin[1].analog[0]"/>
+                    <Port name="srss[0].clock[0].wco[0].wco_out[0]"/>
+                </Net>
+                <Mux name="sense" location="csd[0].csd[0]">
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[7].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[7].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[1].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[1].pin[0].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[2].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[3].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[4].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[5].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[6].analog[0]"/>
+                    </Arm>
+                    <Arm>
+                        <Port name="ioss[0].port[8].pin[7].analog[0]"/>
+                    </Arm>
+                </Mux>
+            </Netlist>
+        </Device>
+        <Device mpn="CYW43012C0WKWBG">
+            <BlockConfig>
+                <Block location="bt[0].power[0]">
+                    <Personality template="connectivity_bt" version="1.0">
+                        <Param id="hostWakePin" value=""/>
+                        <Param id="hostWakeIrqEvent" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
+                        <Param id="devWakePin" value=""/>
+                        <Param id="devWakePolarity" value="CYCFG_BT_WAKE_EVENT_ACTIVE_LOW"/>
+                    </Personality>
+                </Block>
+            </BlockConfig>
+            <Netlist/>
+        </Device>
+    </Devices>
+    <ConfiguratorData/>
+</Design>