rc-pi-3562-v1_0-mipi-800x1280.dtsi 7.1 KB

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  1. // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2. /*
  3. * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
  4. *
  5. */
  6. / {
  7. backlight: backlight {
  8. compatible = "pwm-backlight";
  9. pwms = <&pwm4 0 25000 0>;
  10. brightness-levels = <
  11. 0 20 20 21 21 22 22 23
  12. 23 24 24 25 25 26 26 27
  13. 27 28 28 29 29 30 30 31
  14. 31 32 32 33 33 34 34 35
  15. 35 36 36 37 37 38 38 39
  16. 40 41 42 43 44 45 46 47
  17. 48 49 50 51 52 53 54 55
  18. 56 57 58 59 60 61 62 63
  19. 64 65 66 67 68 69 70 71
  20. 72 73 74 75 76 77 78 79
  21. 80 81 82 83 84 85 86 87
  22. 88 89 90 91 92 93 94 95
  23. 96 97 98 99 100 101 102 103
  24. 104 105 106 107 108 109 110 111
  25. 112 113 114 115 116 117 118 119
  26. 120 121 122 123 124 125 126 127
  27. 128 129 130 131 132 133 134 135
  28. 136 137 138 139 140 141 142 143
  29. 144 145 146 147 148 149 150 151
  30. 152 153 154 155 156 157 158 159
  31. 160 161 162 163 164 165 166 167
  32. 168 169 170 171 172 173 174 175
  33. 176 177 178 179 180 181 182 183
  34. 184 185 186 187 188 189 190 191
  35. 192 193 194 195 196 197 198 199
  36. 200 201 202 203 204 205 206 207
  37. 208 209 210 211 212 213 214 215
  38. 216 217 218 219 220 221 222 223
  39. 224 225 226 227 228 229 230 231
  40. 232 233 234 235 236 237 238 239
  41. 240 241 242 243 244 245 246 247
  42. 248 249 250 251 252 253 254 255
  43. >;
  44. default-brightness-level = <200>;
  45. };
  46. vcc3v3_lcd_n: vcc3v3-lcd0-n {
  47. compatible = "regulator-fixed";
  48. regulator-name = "vcc3v3_lcd_n";
  49. regulator-boot-on;
  50. regulator-state-mem {
  51. regulator-off-in-suspend;
  52. };
  53. };
  54. };
  55. &display_subsystem {
  56. status = "okay";
  57. };
  58. &dsi {
  59. status = "okay";
  60. //rockchip,lane-rate = <1000>;
  61. dsi_panel: panel@0 {
  62. status = "okay";
  63. compatible = "simple-panel-dsi";
  64. reg = <0>;
  65. power-supply = <&vcc3v3_lcd_n>;
  66. pinctrl-names = "default";
  67. pinctrl-0 = <&lcd_rst_gpio>;
  68. reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
  69. backlight = <&backlight>;
  70. reset-delay-ms = <60>;
  71. enable-delay-ms = <60>;
  72. prepare-delay-ms = <60>;
  73. unprepare-delay-ms = <60>;
  74. disable-delay-ms = <60>;
  75. init-delay-ms = <60>;
  76. dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
  77. MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>;
  78. dsi,format = <MIPI_DSI_FMT_RGB888>;
  79. dsi,lanes = <4>;
  80. panel-init-sequence = [
  81. 29 00 04 FF 98 81 03
  82. 29 00 02 01 00
  83. 29 00 02 02 00
  84. 29 00 02 03 73
  85. 29 00 02 04 13
  86. 29 00 02 05 00
  87. 29 00 02 06 0A
  88. 29 00 02 07 05
  89. 29 00 02 08 00
  90. 29 00 02 09 28
  91. 29 00 02 0a 00
  92. 29 00 02 0b 00
  93. 29 00 02 0c 00
  94. 29 00 02 0d 28
  95. 29 00 02 0e 00
  96. 29 00 02 0f 28
  97. 29 00 02 10 28
  98. 29 00 02 11 00
  99. 29 00 02 12 00
  100. 29 00 02 13 00
  101. 29 00 02 14 00
  102. 29 00 02 15 00
  103. 29 00 02 16 00
  104. 29 00 02 17 00
  105. 29 00 02 18 00
  106. 29 00 02 19 00
  107. 29 00 02 1a 00
  108. 29 00 02 1b 00
  109. 29 00 02 1c 00
  110. 29 00 02 1d 00
  111. 29 00 02 1e 40
  112. 29 00 02 1f 80
  113. 29 00 02 20 06
  114. 29 00 02 21 01
  115. 29 00 02 22 00
  116. 29 00 02 23 00
  117. 29 00 02 24 00
  118. 29 00 02 25 00
  119. 29 00 02 26 00
  120. 29 00 02 27 00
  121. 29 00 02 28 33
  122. 29 00 02 29 33
  123. 29 00 02 2a 00
  124. 29 00 02 2b 00
  125. 29 00 02 2c 04
  126. 29 00 02 2d 04
  127. 29 00 02 2e 05
  128. 29 00 02 2f 05
  129. 29 00 02 30 00
  130. 29 00 02 31 00
  131. 29 00 02 32 31
  132. 29 00 02 33 00
  133. 29 00 02 34 00
  134. 29 00 02 35 0A
  135. 29 00 02 36 00
  136. 29 00 02 37 08
  137. 29 00 02 38 00
  138. 29 00 02 39 00
  139. 29 00 02 3a 00
  140. 29 00 02 3b 00
  141. 29 00 02 3c 00
  142. 29 00 02 3d 00
  143. 29 00 02 3e 00
  144. 29 00 02 3f 00
  145. 29 00 02 40 00
  146. 29 00 02 41 00
  147. 29 00 02 42 00
  148. 29 00 02 43 08
  149. 29 00 02 44 00
  150. 29 00 02 50 01
  151. 29 00 02 51 23
  152. 29 00 02 52 44
  153. 29 00 02 53 67
  154. 29 00 02 54 89
  155. 29 00 02 55 ab
  156. 29 00 02 56 01
  157. 29 00 02 57 23
  158. 29 00 02 58 45
  159. 29 00 02 59 67
  160. 29 00 02 5a 89
  161. 29 00 02 5b ab
  162. 29 00 02 5c cd
  163. 29 00 02 5d ef
  164. 29 00 02 5e 11
  165. 29 00 02 5f 02
  166. 29 00 02 60 08
  167. 29 00 02 61 0E
  168. 29 00 02 62 0F
  169. 29 00 02 63 0C
  170. 29 00 02 64 0D
  171. 29 00 02 65 17
  172. 29 00 02 66 01
  173. 29 00 02 67 01
  174. 29 00 02 68 02
  175. 29 00 02 69 02
  176. 29 00 02 6a 00
  177. 29 00 02 6b 00
  178. 29 00 02 6c 02
  179. 29 00 02 6d 02
  180. 29 00 02 6e 16
  181. 29 00 02 6f 16
  182. 29 00 02 70 06
  183. 29 00 02 71 06
  184. 29 00 02 72 07
  185. 29 00 02 73 07
  186. 29 00 02 74 02
  187. 29 00 02 75 02
  188. 29 00 02 76 08
  189. 29 00 02 77 0E
  190. 29 00 02 78 0F
  191. 29 00 02 79 0C
  192. 29 00 02 7a 0D
  193. 29 00 02 7b 17
  194. 29 00 02 7c 01
  195. 29 00 02 7d 01
  196. 29 00 02 7e 02
  197. 29 00 02 7f 02
  198. 29 00 02 80 00
  199. 29 00 02 81 00
  200. 29 00 02 82 02
  201. 29 00 02 83 02
  202. 29 00 02 84 16
  203. 29 00 02 85 16
  204. 29 00 02 86 06
  205. 29 00 02 87 06
  206. 29 00 02 88 07
  207. 29 00 02 89 07
  208. 29 00 02 8A 02
  209. 29 00 04 FF 98 81 04
  210. 29 00 02 6E 1A
  211. 29 00 02 6F 37
  212. 29 00 02 3A A4
  213. 29 00 02 8D 1F
  214. 29 00 02 87 BA
  215. 29 00 02 B2 D1
  216. 29 00 02 88 0B
  217. 29 00 02 38 01
  218. 29 00 02 39 00
  219. 29 00 02 B5 02
  220. 29 00 02 31 25
  221. 29 00 02 3B 98
  222. 29 00 04 FF 98 81 01
  223. 29 00 02 22 0A
  224. 29 00 02 31 00
  225. 29 00 02 53 5A
  226. 29 00 02 55 3D
  227. 29 00 02 50 9E
  228. 29 00 02 51 99
  229. 29 00 02 60 06
  230. 29 00 02 62 20
  231. 29 00 02 A0 00
  232. 29 00 02 A1 17
  233. 29 00 02 A2 26
  234. 29 00 02 A3 13
  235. 29 00 02 A4 16
  236. 29 00 02 A5 29
  237. 29 00 02 A6 1E
  238. 29 00 02 A7 1F
  239. 29 00 02 A8 8B
  240. 29 00 02 A9 1D
  241. 29 00 02 AA 2A
  242. 29 00 02 AB 7B
  243. 29 00 02 AC 1A
  244. 29 00 02 AD 19
  245. 29 00 02 AE 4E
  246. 29 00 02 AF 24
  247. 29 00 02 B0 29
  248. 29 00 02 B1 4F
  249. 29 00 02 B2 5C
  250. 29 00 02 B3 23
  251. 29 00 02 C0 00
  252. 29 00 02 C1 17
  253. 29 00 02 C2 26
  254. 29 00 02 C3 13
  255. 29 00 02 C4 16
  256. 29 00 02 C5 29
  257. 29 00 02 C6 1E
  258. 29 00 02 C7 1F
  259. 29 00 02 C8 8B
  260. 29 00 02 C9 1D
  261. 29 00 02 CA 2A
  262. 29 00 02 CB 7B
  263. 29 00 02 CC 1A
  264. 29 00 02 CD 19
  265. 29 00 02 CE 4E
  266. 29 00 02 CF 24
  267. 29 00 02 D0 29
  268. 29 00 02 D1 4F
  269. 29 00 02 D2 5C
  270. 29 00 02 D3 23
  271. 29 00 04 FF 98 81 00
  272. 29 00 02 35 00
  273. 05 78 01 11
  274. 05 1E 01 29
  275. ];
  276. panel-exit-sequence = [
  277. 05 00 01 28
  278. 05 00 01 10
  279. ];
  280. disp_timings0: display-timings {
  281. native-mode = <&dsi_timing0>;
  282. dsi_timing0: timing0 {
  283. clock-frequency = <73400000>;
  284. hactive = <800>;
  285. vactive = <1280>;
  286. hfront-porch = <52>;
  287. hsync-len = <4>;
  288. hback-porch = <12>;
  289. vfront-porch = <60>;
  290. vsync-len = <18>;
  291. vback-porch = <50>;
  292. hsync-active = <0>;
  293. vsync-active = <0>;
  294. de-active = <0>;
  295. pixelclk-active = <1>;
  296. };
  297. };
  298. ports {
  299. #address-cells = <1>;
  300. #size-cells = <0>;
  301. port@0 {
  302. reg = <0>;
  303. panel_in_dsi: endpoint {
  304. remote-endpoint = <&dsi_out_panel>;
  305. };
  306. };
  307. };
  308. };
  309. ports {
  310. #address-cells = <1>;
  311. #size-cells = <0>;
  312. port@1 {
  313. reg = <1>;
  314. dsi_out_panel: endpoint {
  315. remote-endpoint = <&panel_in_dsi>;
  316. };
  317. };
  318. };
  319. };
  320. &route_dsi {
  321. status = "okay";
  322. };
  323. &dsi_in_vp0 {
  324. status = "okay";
  325. };
  326. &video_phy {
  327. status = "okay";
  328. };
  329. &pwm4 {
  330. pinctrl-0 = <&pwm4m0_pins>;
  331. status = "okay";
  332. };
  333. &wdt {
  334. status = "okay";
  335. };
  336. &pinctrl {
  337. touch {
  338. touch_gpio: touch-gpio {
  339. rockchip,pins =
  340. <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
  341. <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
  342. };
  343. };
  344. lcd {
  345. lcd_rst_gpio: lcd-rst-gpio {
  346. rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
  347. };
  348. };
  349. };