/* generated HAL source file - do not edit */ #include "hal_data.h" gpt_instance_ctrl_t g_timer1_ctrl; #if 0 const gpt_extended_pwm_cfg_t g_timer1_pwm_extend = { #if defined(VECTOR_NUMBER_GPT8_UDF) .trough_ipl = (BSP_IRQ_DISABLED), .trough_irq = VECTOR_NUMBER_GPT8_UDF, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .trough_ipl = FSP_NOT_DEFINED, .trough_irq = VECTOR_NUMBER_GPT01_1_INT, #else .trough_ipl = (BSP_IRQ_DISABLED), .trough_irq = FSP_INVALID_VECTOR, #endif .poeg_link = GPT_POEG_LINK_POEG0, .output_disable = GPT_OUTPUT_DISABLE_NONE, .adc_trigger = GPT_ADC_TRIGGER_NONE, .dead_time_count_up = 0, .dead_time_count_down = 0, .adc_a_compare_match = 0, .adc_b_compare_match = 0, .interrupt_skip_source = GPT_INTERRUPT_SKIP_SOURCE_NONE, .interrupt_skip_count = GPT_INTERRUPT_SKIP_COUNT_0, .interrupt_skip_adc = GPT_INTERRUPT_SKIP_ADC_NONE, .gtioca_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, .gtiocb_disable_setting = GPT_GTIOC_DISABLE_PROHIBITED, .interrupt_skip_source_ext1 = GPT_INTERRUPT_SKIP_SOURCE_NONE, .interrupt_skip_count_ext1 = GPT_INTERRUPT_SKIP_COUNT_0, .interrupt_skip_source_ext2 = GPT_INTERRUPT_SKIP_SOURCE_NONE, .interrupt_skip_count_ext2 = GPT_INTERRUPT_SKIP_COUNT_0, .interrupt_skip_func_ovf = GPT_INTERRUPT_SKIP_SELECT_NONE, .interrupt_skip_func_unf = GPT_INTERRUPT_SKIP_SELECT_NONE, .interrupt_skip_func_adc_a = GPT_INTERRUPT_SKIP_SELECT_NONE, .interrupt_skip_func_adc_b = GPT_INTERRUPT_SKIP_SELECT_NONE, }; #endif const gpt_extended_cfg_t g_timer1_extend = { .gtioca = { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, .gtiocb = { .output_enabled = false, .stop_level = GPT_PIN_LEVEL_LOW }, .start_source = (gpt_source_t) ( GPT_SOURCE_NONE), .stop_source = (gpt_source_t) ( GPT_SOURCE_NONE), .clear_source = (gpt_source_t) ( GPT_SOURCE_NONE), #if (0 == (0)) .count_up_source = (gpt_source_t) ( GPT_SOURCE_NONE), .count_down_source = (gpt_source_t) ( GPT_SOURCE_NONE), #else .count_up_source = (gpt_source_t) ((GPT_PHASE_COUNTING_MODE_1_UP | (GPT_PHASE_COUNTING_MODE_1_DN << 16)) & 0x000FFFFU), .count_down_source = (gpt_source_t) (((GPT_PHASE_COUNTING_MODE_1_UP | (GPT_PHASE_COUNTING_MODE_1_DN << 16)) & 0xFFFF0000U) >> 16), #endif .capture_a_source = (gpt_source_t) ( GPT_SOURCE_NONE), .capture_b_source = (gpt_source_t) ( GPT_SOURCE_NONE), #if defined(VECTOR_NUMBER_GPT8_CCMPA) .capture_a_ipl = (BSP_IRQ_DISABLED), .capture_a_irq = VECTOR_NUMBER_GPT8_CCMPA, .capture_a_source_select = BSP_IRQ_DISABLED, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .capture_a_ipl = FSP_NOT_DEFINED, .capture_a_irq = VECTOR_NUMBER_GPT01_1_INT, .capture_a_source_select = , #else .capture_a_ipl = (BSP_IRQ_DISABLED), .capture_a_irq = FSP_INVALID_VECTOR, .capture_a_source_select = BSP_IRQ_DISABLED, #endif #if defined(VECTOR_NUMBER_GPT8_CCMPB) .capture_b_irq = VECTOR_NUMBER_GPT8_CCMPB, .capture_b_ipl = (BSP_IRQ_DISABLED), .capture_b_source_select = BSP_IRQ_DISABLED, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .capture_b_irq = VECTOR_NUMBER_GPT01_1_INT, .capture_b_ipl = FSP_NOT_DEFINED, .capture_b_source_select = , #else .capture_b_ipl = (BSP_IRQ_DISABLED), .capture_b_irq = FSP_INVALID_VECTOR, .capture_b_source_select = BSP_IRQ_DISABLED, #endif .capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE, .capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE, #if 0 .p_pwm_cfg = &g_timer1_pwm_extend, #else .p_pwm_cfg = NULL, #endif #if defined(VECTOR_NUMBER_GPT8_DTE) .dead_time_ipl = (BSP_IRQ_DISABLED), .dead_time_irq = VECTOR_NUMBER_GPT8_DTE, .dead_time_error_source_select = BSP_IRQ_DISABLED, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .dead_time_ipl = FSP_NOT_DEFINED, .dead_time_irq = VECTOR_NUMBER_GPT01_1_INT, .dead_time_error_source_select = , #else .dead_time_ipl = (BSP_IRQ_DISABLED), .dead_time_irq = FSP_INVALID_VECTOR, .dead_time_error_source_select = BSP_IRQ_DISABLED, #endif .icds = 0, #if (2U == BSP_FEATURE_GPT_REGISTER_MASK_TYPE) #if (1U == BSP_FEATURE_GPT_INPUT_CAPTURE_SIGNAL_SELECTABLE) .gtioc_isel = 0, #endif #endif #if defined(VECTOR_NUMBER_GPT8_OVF) .cycle_end_source_select = BSP_IRQ_DISABLED, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .cycle_end_source_select = , #else .cycle_end_source_select = BSP_IRQ_DISABLED, #endif #if defined(VECTOR_NUMBER_GPT8_UDF) .trough_source_select = BSP_IRQ_DISABLED, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .trough_source_select = , #else .trough_source_select = BSP_IRQ_DISABLED, #endif }; const timer_cfg_t g_timer1_cfg = { .mode = TIMER_MODE_PERIODIC, /* Actual period: 42.94967296 seconds. Actual duty: 50%. */ .period_counts = (uint32_t) 0x100000000, .duty_cycle_counts = 0x80000000, .source_div = (timer_source_div_t)0, .channel = GPT_CHANNEL_UNIT1_1, #if (1 == BSP_FEATURE_BSP_IRQ_GPT_SEL_SUPPORTED) .p_callback = NULL, #else .p_callback = timer1_callback, #endif .p_context = NULL, .p_extend = &g_timer1_extend, #if defined(VECTOR_NUMBER_GPT8_OVF) .cycle_end_ipl = (12), .cycle_end_irq = VECTOR_NUMBER_GPT8_OVF, #elif defined(VECTOR_NUMBER_GPT01_1_INT) .cycle_end_ipl = FSP_NOT_DEFINED, .cycle_end_irq = VECTOR_NUMBER_GPT01_1_INT, #else .cycle_end_ipl = (12), .cycle_end_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const timer_instance_t g_timer1 = { .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_gpt }; /* Nominal and Data bit timing configuration */ can_bit_timing_cfg_t g_canfd1_bit_timing_cfg = { /* Actual bitrate: 1000000 Hz. Actual sample point: 75 %. */ .baud_rate_prescaler = 1, .time_segment_1 = 29, .time_segment_2 = 10, .synchronization_jump_width = 4 }; can_bit_timing_cfg_t g_canfd1_data_timing_cfg = { /* Actual bitrate: 1000000 Hz. Actual sample point: 75 %. */ .baud_rate_prescaler = 1, .time_segment_1 = 29, .time_segment_2 = 10, .synchronization_jump_width = 4 }; extern const canfd_afl_entry_t p_canfd1_afl[CANFD_CFG_AFL_CH1_RULE_NUM]; #ifndef CANFD_PRV_GLOBAL_CFG #define CANFD_PRV_GLOBAL_CFG canfd_global_cfg_t g_canfd_global_cfg = { .global_interrupts = CANFD_CFG_GLOBAL_ERR_SOURCES, .global_config = (CANFD_CFG_TX_PRIORITY | CANFD_CFG_DLC_CHECK | CANFD_CFD_CLOCK_SOURCE | CANFD_CFG_FD_OVERFLOW | (uint32_t) (CANFD_CFG_TIMER_PRESCALER << R_CANFD_CFDGCFG_ITRCP_Pos)), .rx_mb_config = (CANFD_CFG_RXMB_NUMBER | (CANFD_CFG_RXMB_SIZE << R_CANFD_CFDRMNB_RMPLS_Pos)), .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, .rx_fifo_config = { ((CANFD_CFG_RXFIFO0_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO0_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO0_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO0_INT_MODE) | (CANFD_CFG_RXFIFO0_ENABLE)), ((CANFD_CFG_RXFIFO1_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO1_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO1_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO1_INT_MODE) | (CANFD_CFG_RXFIFO1_ENABLE)), ((CANFD_CFG_RXFIFO2_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO2_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO2_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO2_INT_MODE) | (CANFD_CFG_RXFIFO2_ENABLE)), ((CANFD_CFG_RXFIFO3_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO3_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO3_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO3_INT_MODE) | (CANFD_CFG_RXFIFO3_ENABLE)), ((CANFD_CFG_RXFIFO4_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO4_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO4_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO4_INT_MODE) | (CANFD_CFG_RXFIFO4_ENABLE)), ((CANFD_CFG_RXFIFO5_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO5_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO5_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO5_INT_MODE) | (CANFD_CFG_RXFIFO5_ENABLE)), ((CANFD_CFG_RXFIFO6_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO6_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO6_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO6_INT_MODE) | (CANFD_CFG_RXFIFO6_ENABLE)), ((CANFD_CFG_RXFIFO7_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO7_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO7_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO7_INT_MODE) | (CANFD_CFG_RXFIFO7_ENABLE)), }, .common_fifo_config = { CANFD_CFG_COMMONFIFO0, CANFD_CFG_COMMONFIFO1, CANFD_CFG_COMMONFIFO2, CANFD_CFG_COMMONFIFO3, CANFD_CFG_COMMONFIFO4, CANFD_CFG_COMMONFIFO5, } }; #endif canfd_extended_cfg_t g_canfd1_extended_cfg = { .p_afl = p_canfd1_afl, .txmb_txi_enable = ((1ULL << 0) | (1ULL << 1) | 0ULL), .error_interrupts = ( 0U), .p_data_timing = &g_canfd1_data_timing_cfg, .delay_compensation = (1), .p_global_cfg = &g_canfd_global_cfg, }; canfd_instance_ctrl_t g_canfd1_ctrl; const can_cfg_t g_canfd1_cfg = { .channel = 1, .p_bit_timing = &g_canfd1_bit_timing_cfg, .p_callback = canfd1_callback, .p_extend = &g_canfd1_extended_cfg, .p_context = NULL, .ipl = (12), #if defined(VECTOR_NUMBER_CAN1_COMFRX) .rx_irq = VECTOR_NUMBER_CAN1_COMFRX, #else .rx_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_CAN1_TX) .tx_irq = VECTOR_NUMBER_CAN1_TX, #else .tx_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_CAN1_CHERR) .error_irq = VECTOR_NUMBER_CAN1_CHERR, #else .error_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const can_instance_t g_canfd1 = { .p_ctrl = &g_canfd1_ctrl, .p_cfg = &g_canfd1_cfg, .p_api = &g_canfd_on_canfd }; /* Nominal and Data bit timing configuration */ can_bit_timing_cfg_t g_canfd0_bit_timing_cfg = { /* Actual bitrate: 1000000 Hz. Actual sample point: 75 %. */ .baud_rate_prescaler = 1, .time_segment_1 = 29, .time_segment_2 = 10, .synchronization_jump_width = 4 }; can_bit_timing_cfg_t g_canfd0_data_timing_cfg = { /* Actual bitrate: 1000000 Hz. Actual sample point: 75 %. */ .baud_rate_prescaler = 1, .time_segment_1 = 29, .time_segment_2 = 10, .synchronization_jump_width = 4 }; extern const canfd_afl_entry_t p_canfd0_afl[CANFD_CFG_AFL_CH0_RULE_NUM]; #ifndef CANFD_PRV_GLOBAL_CFG #define CANFD_PRV_GLOBAL_CFG canfd_global_cfg_t g_canfd_global_cfg = { .global_interrupts = CANFD_CFG_GLOBAL_ERR_SOURCES, .global_config = (CANFD_CFG_TX_PRIORITY | CANFD_CFG_DLC_CHECK | CANFD_CFD_CLOCK_SOURCE | CANFD_CFG_FD_OVERFLOW | (uint32_t) (CANFD_CFG_TIMER_PRESCALER << R_CANFD_CFDGCFG_ITRCP_Pos)), .rx_mb_config = (CANFD_CFG_RXMB_NUMBER | (CANFD_CFG_RXMB_SIZE << R_CANFD_CFDRMNB_RMPLS_Pos)), .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, .rx_fifo_config = { ((CANFD_CFG_RXFIFO0_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO0_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO0_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO0_INT_MODE) | (CANFD_CFG_RXFIFO0_ENABLE)), ((CANFD_CFG_RXFIFO1_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO1_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO1_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO1_INT_MODE) | (CANFD_CFG_RXFIFO1_ENABLE)), ((CANFD_CFG_RXFIFO2_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO2_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO2_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO2_INT_MODE) | (CANFD_CFG_RXFIFO2_ENABLE)), ((CANFD_CFG_RXFIFO3_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO3_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO3_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO3_INT_MODE) | (CANFD_CFG_RXFIFO3_ENABLE)), ((CANFD_CFG_RXFIFO4_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO4_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO4_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO4_INT_MODE) | (CANFD_CFG_RXFIFO4_ENABLE)), ((CANFD_CFG_RXFIFO5_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO5_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO5_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO5_INT_MODE) | (CANFD_CFG_RXFIFO5_ENABLE)), ((CANFD_CFG_RXFIFO6_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO6_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO6_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO6_INT_MODE) | (CANFD_CFG_RXFIFO6_ENABLE)), ((CANFD_CFG_RXFIFO7_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO7_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO7_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO7_INT_MODE) | (CANFD_CFG_RXFIFO7_ENABLE)), }, .common_fifo_config = { CANFD_CFG_COMMONFIFO0, CANFD_CFG_COMMONFIFO1, CANFD_CFG_COMMONFIFO2, CANFD_CFG_COMMONFIFO3, CANFD_CFG_COMMONFIFO4, CANFD_CFG_COMMONFIFO5, } }; #endif canfd_extended_cfg_t g_canfd0_extended_cfg = { .p_afl = p_canfd0_afl, .txmb_txi_enable = ((1ULL << 0) | (1ULL << 1) | 0ULL), .error_interrupts = ( 0U), .p_data_timing = &g_canfd0_data_timing_cfg, .delay_compensation = (1), .p_global_cfg = &g_canfd_global_cfg, }; canfd_instance_ctrl_t g_canfd0_ctrl; const can_cfg_t g_canfd0_cfg = { .channel = 0, .p_bit_timing = &g_canfd0_bit_timing_cfg, .p_callback = canfd0_callback, .p_extend = &g_canfd0_extended_cfg, .p_context = NULL, .ipl = (12), #if defined(VECTOR_NUMBER_CAN0_COMFRX) .rx_irq = VECTOR_NUMBER_CAN0_COMFRX, #else .rx_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_CAN0_TX) .tx_irq = VECTOR_NUMBER_CAN0_TX, #else .tx_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_CAN0_CHERR) .error_irq = VECTOR_NUMBER_CAN0_CHERR, #else .error_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const can_instance_t g_canfd0 = { .p_ctrl = &g_canfd0_ctrl, .p_cfg = &g_canfd0_cfg, .p_api = &g_canfd_on_canfd }; sci_uart_instance_ctrl_t g_uart0_ctrl; #define FSP_NOT_DEFINED (1) #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) /* If the transfer module is DMAC, define a DMAC transfer callback. */ extern void sci_uart_tx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); void g_uart0_tx_transfer_callback (transfer_callback_args_t * p_args) { FSP_PARAMETER_NOT_USED(p_args); sci_uart_tx_dmac_callback(&g_uart0_ctrl); } #endif #if (FSP_NOT_DEFINED) != (FSP_NOT_DEFINED) /* If the transfer module is DMAC, define a DMAC transfer callback. */ extern void sci_uart_rx_dmac_callback(sci_uart_instance_ctrl_t * p_instance_ctrl); void g_uart0_rx_transfer_callback (transfer_callback_args_t * p_args) { FSP_PARAMETER_NOT_USED(p_args); sci_uart_rx_dmac_callback(&g_uart0_ctrl); } #endif #undef FSP_NOT_DEFINED sci_baud_setting_t g_uart0_baud_setting = { /* Baud rate calculated with 0.160% error. */ .baudrate_bits_b.abcse = 0, .baudrate_bits_b.abcs = 0, .baudrate_bits_b.bgdm = 1, .baudrate_bits_b.cks = 0, .baudrate_bits_b.brr = 51, .baudrate_bits_b.mddr = (uint8_t) 256, .baudrate_bits_b.brme = false }; /** UART extended configuration for UARTonSCI HAL driver */ const sci_uart_extended_cfg_t g_uart0_cfg_extend = { .clock = SCI_UART_CLOCK_INT, .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart0_baud_setting, #if 1 .clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK, #else .clock_source = SCI_UART_CLOCK_SOURCE_PCLKM, #endif .flow_control = SCI_UART_FLOW_CONTROL_RTS, #if 0xFF != 0xFF .flow_control_pin = BSP_IO_PORT_FF_PIN_0xFF, #else .flow_control_pin = (bsp_io_port_pin_t) UINT16_MAX, #endif .rs485_setting = { .enable = SCI_UART_RS485_DISABLE, .polarity = SCI_UART_RS485_DE_POLARITY_HIGH, .assertion_time = 1, .negation_time = 1, }, }; /** UART interface configuration */ const uart_cfg_t g_uart0_cfg = { .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = user_uart0_callback, .p_context = NULL, .p_extend = &g_uart0_cfg_extend, .p_transfer_tx = g_uart0_P_TRANSFER_TX, .p_transfer_rx = g_uart0_P_TRANSFER_RX, .rxi_ipl = (12), .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), #if defined(VECTOR_NUMBER_SCI0_RXI) .rxi_irq = VECTOR_NUMBER_SCI0_RXI, #else .rxi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_TXI) .txi_irq = VECTOR_NUMBER_SCI0_TXI, #else .txi_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_TEI) .tei_irq = VECTOR_NUMBER_SCI0_TEI, #else .tei_irq = FSP_INVALID_VECTOR, #endif #if defined(VECTOR_NUMBER_SCI0_ERI) .eri_irq = VECTOR_NUMBER_SCI0_ERI, #else .eri_irq = FSP_INVALID_VECTOR, #endif }; /* Instance structure to use this module. */ const uart_instance_t g_uart0 = { .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; void g_hal_init(void) { g_common_init(); }