first

project_0/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>stm32f767</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

project_0/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

project_0/.settings/projcfg.ini

@@ -0,0 +1,22 @@
+#RT-Thread Studio Project Configuration
+#Sat Jan 16 15:18:32 CST 2021
+project_type=rtt
+chip_name=STM32F767ZITx
+cpu_name=None
+target_freq=
+clock_source=
+dvendor_name=
+rx_pin_name=
+rtt_path=
+source_freq=
+csp_path=
+sub_series_name=
+selected_rtt_version=latest
+cfg_version=v3.0
+tool_chain=gcc
+uart_name=
+tx_pin_name=
+rtt_nano_path=
+output_project_path=
+hardware_adapter=ST-Link
+project_name=stm32f767

project_0/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "libraries/Kconfig"
+source "board/Kconfig"

project_0/README.md

@@ -0,0 +1,95 @@
+# STM32F767-Nucleo BSP Introduction
+
+[中文](README_zh.md) 
+
+## MCU: STM32F767ZI @216MHz, 2MB FLASH,  512KB RAM
+
+The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency. The Cortex®-M7 core features a floating point unit (FPU) which supports Arm® double-precision and single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances the application security.
+
+The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate high-speed embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including 128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM (for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power modes, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memories access.
+All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers, a true random number generator (RNG). They also feature standard and advanced communication interfaces.
+Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC) interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors.
+The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices operate in the –40 to +105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available on all the packages except LQFP100 for a greater power supply choice.
+The supply voltage can drop to 1.7 V with the use of an external power supply supervisor. A comprehensive set of power-saving mode allows the design of low-power applications.
+The STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx devices offer devices in 11 packages ranging from 100 pins to 216 pins. The set of included peripherals changes with the device chosen.
+These features make the STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx microcontrollers suitable for a wide range of applications.
+
+#### KEY FEATURES
+
+- Core: Arm® 32-bit Cortex®-M7 CPU with DPFPU, ART Accelerator™ and L1-cache: 16 Kbytes I/D cache, allowing 0-wait state execution from embedded Flash and external memories, up to 216 MHz, MPU, 462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions.
+- Memories
+  - Up to 2 Mbytes of Flash memory organized into two banks allowing read-while-write
+  - SRAM: 512 Kbytes (including 128 Kbytes of data TCM RAM for critical real-time data) + 16 Kbytes of instruction TCM RAM (for critical real-time routines) + 4 Kbytes of backup SRAM
+  - Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
+- Dual mode Quad-SPI
+- Graphics
+  - Chrom-ART Accelerator™ (DMA2D), graphical hardware accelerator enabling enhanced graphical user interface
+  - Hardware JPEG codec
+  - LCD-TFT controller supporting up to XGA resolution
+  - MIPI® DSI host controller supporting up to 720p 30 Hz resolution
+- Clock, reset and supply management
+  - 1.7 V to 3.6 V application supply and I/Os
+  - POR, PDR, PVD and BOR
+  - Dedicated USB power
+  - 4-to-26 MHz crystal oscillator
+  - Internal 16 MHz factory-trimmed RC (1% accuracy)
+  - 32 kHz oscillator for RTC with calibration
+  - Internal 32 kHz RC with calibration
+- Low-power
+  - Sleep, Stop and Standby modes
+  - VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM
+- 3×12-bit, 2.4 MSPS ADC: up to 24 channels
+- Digital filters for sigma delta modulator (DFSDM), 8 channels / 4 filters
+- 2×12-bit D/A converters
+- General-purpose DMA: 16-stream DMA controller with FIFOs and burst support
+
+- Up to 18 timers: up to thirteen 16-bit (1x low- power 16-bit timer available in Stop mode) and two 32-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input. All 15 timers running up to 216 MHz. 2x watchdogs, SysTick timer
+- Debug mode
+  - SWD & JTAG interfaces
+  - Cortex®-M7 Trace Macrocell™
+- Up to 168 I/O ports with interrupt capability
+  - Up to 164 fast I/Os up to 108 MHz
+  - Up to 166 5 V-tolerant I/Os
+- Up to 28 communication interfaces
+  - Up to 4 I2C interfaces (SMBus/PMBus)
+  - Up to 4 USARTs/4 UARTs (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, modem control)
+  - Up to 6 SPIs (up to 54 Mbit/s), 3 with muxed simplex I2S for audio
+  - 2 x SAIs (serial audio interface)
+  - 3 x CANs (2.0B Active) and 2 x SDMMCs
+  - SPDIFRX interface
+  - HDMI-CEC
+  - MDIO slave interface
+- Advanced connectivity
+  - USB 2.0 full-speed device/host/OTG controller with on-chip PHY
+  - USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
+  - 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII
+- 8- to 14-bit camera interface up to 54 Mbyte/s
+- True random number generator
+- CRC calculation unit
+- RTC: subsecond accuracy, hardware calendar
+- 96-bit unique ID
+
+
+
+## Read more
+
+|                          Documents                           |                         Description                          |
+| :----------------------------------------------------------: | :----------------------------------------------------------: |
+| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) |
+| [STM32F767ZI ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32f767zi.html#documentation) |          STM32F767ZI datasheet and other resources           |
+
+
+
+## Maintained By
+
+[e31207077](https://github.com/e31207077)  <e31207077@yahoo.com.tw>
+
+
+
+## Translated By
+
+Meco Man @ RT-Thread Community
+
+> jiantingman@foxmail.com 
+>
+> https://github.com/mysterywolf

project_0/README_zh.md

@@ -0,0 +1,110 @@
+# STM32F767 NUCLEO-F767ZI开发板 BSP 说明
+## 简介
+
+本文档为 NUCLEO-F767ZI 开发板的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+NUCLEO-F767ZI 是st推出的一款基于 ARM Cortex-M7 内核的开发板，最高主频为 216Mhz，该开发板具有丰富的板载资源，可以充分发挥 STM32F767 的芯片性能。
+
+开发板外观如下图所示：
+
+![board](figures/en.high-perf_nucleo-144_mbed.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：STM32f767，主频 216MHz，2MB FLASH ，512KB RAM ，16K CACHE
+
+- 常用外设
+  - LED ：3个，LED1 (绿色，PB0),LED2（蓝色，PB7），LED3（红色，PB14）
+  - 按键：2个，B1（用户按键，PC13），B2（复位引脚）
+- 常用接口：USB 转串口3、以太网接口
+- 调试接口：ST-LINK
+
+开发板更多详细信息请参考ST [NUCLEO-F767ZI开发板介绍](https://www.st.com/en/evaluation-tools/nucleo-f767zi.html)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**      | **支持情况** | **备注**                              |
+| :-----------------| :----------: | :-------------------------------------|
+| USB 转串口3        |     支持     |                                       |
+| 以太网            |   支持   | PHY 选项 LAN8720A（兼容 LAN8742A） |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     | PA0, PA1... PK15 ---> PIN: 0, 1...144 |
+| UART              |     支持     | UART3                                 |
+| **扩展模块**      | **支持情况** | **备注**                              |
+| 暂无              |   暂不支持   | 暂不支持                              |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用数据线连接开发板到 PC，打开电源开关。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用 ST-LINK 仿真器下载程序，在通过 ST-LINK 连接开发板的基础上，点击下载按钮即可下载程序到开发板
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，LED 闪烁。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.0 build Jan  9 2019
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口3 的功能，如果需使用 Ethernet 等更多高级功能，需要利用 ENV 工具对BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。
+
+本章节更多详细的介绍请参考 [STM32 系列 BSP 外设驱动使用教程](../docs/STM32系列BSP外设驱动使用教程.md)。
+
+## 注意事项
+
+暂无
+
+## 联系人信息
+
+维护人:
+
+-  [e31207077](https://github.com/e31207077), 邮箱：<e31207077@yahoo.com.tw>

project_0/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

project_0/SConstruct

@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+# set RTT_ROOT
+if not os.getenv("RTT_ROOT"): 
+    RTT_ROOT="rt-thread"
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32F7xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

project_0/applications/SConscript

@@ -0,0 +1,12 @@
+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd, str(Dir('#'))]
+src     = Split("""
+main.c
+""")
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

project_0/applications/main.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-1-10      e31207077    add stm32f767-st-nucleo bsp
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED1 pin: PB0 */
+#define LED1_PIN    GET_PIN(B, 0)
+
+int main(void)
+{
+    int count = 1;
+    /* set LED1 pin mode to output */
+    rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED1_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED1_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;		
+}

project_0/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,324 @@
+#MicroXplorer Configuration settings - do not modify
+ETH.IPParameters=MediaInterface,PHY_Name,PHY_Value,PhyAddress
+ETH.MediaInterface=ETH_MEDIA_INTERFACE_RMII
+ETH.PHY_Name=LAN8742A_PHY_ADDRESS
+ETH.PHY_Value=0
+ETH.PhyAddress=0
+File.Version=6
+KeepUserPlacement=true
+Mcu.Family=STM32F7
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=ETH
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IP5=USART3
+Mcu.IP6=USB_OTG_FS
+Mcu.IPNb=7
+Mcu.Name=STM32F767ZITx
+Mcu.Package=LQFP144
+Mcu.Pin0=PC13
+Mcu.Pin1=PC14/OSC32_IN
+Mcu.Pin10=PC5
+Mcu.Pin11=PB13
+Mcu.Pin12=PB14
+Mcu.Pin13=PD8
+Mcu.Pin14=PD9
+Mcu.Pin15=PG6
+Mcu.Pin16=PG7
+Mcu.Pin17=PA8
+Mcu.Pin18=PA9
+Mcu.Pin19=PA10
+Mcu.Pin2=PC15/OSC32_OUT
+Mcu.Pin20=PA11
+Mcu.Pin21=PA12
+Mcu.Pin22=PA13
+Mcu.Pin23=PA14
+Mcu.Pin24=PG11
+Mcu.Pin25=PG13
+Mcu.Pin26=PB3
+Mcu.Pin27=PB7
+Mcu.Pin28=VP_SYS_VS_Systick
+Mcu.Pin3=PH0/OSC_IN
+Mcu.Pin4=PH1/OSC_OUT
+Mcu.Pin5=PC1
+Mcu.Pin6=PA1
+Mcu.Pin7=PA2
+Mcu.Pin8=PA7
+Mcu.Pin9=PC4
+Mcu.PinsNb=29
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32F767ZITx
+MxCube.Version=5.0.1
+MxDb.Version=DB.5.0.1
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=RMII_REF_CLK [LAN8742A-CZ-TR_REFCLK0]
+PA1.Locked=true
+PA1.Mode=RMII
+PA1.Signal=ETH_REF_CLK
+PA10.GPIOParameters=GPIO_Label
+PA10.GPIO_Label=USB_ID
+PA10.Locked=true
+PA10.Signal=USB_OTG_FS_ID
+PA11.GPIOParameters=GPIO_Label
+PA11.GPIO_Label=USB_DM
+PA11.Locked=true
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Label
+PA12.GPIO_Label=USB_DP
+PA12.Locked=true
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA13.GPIOParameters=GPIO_Label
+PA13.GPIO_Label=TMS
+PA13.Locked=true
+PA13.Mode=Serial_Wire
+PA13.Signal=SYS_JTMS-SWDIO
+PA14.GPIOParameters=GPIO_Label
+PA14.GPIO_Label=TCK
+PA14.Locked=true
+PA14.Mode=Serial_Wire
+PA14.Signal=SYS_JTCK-SWCLK
+PA2.GPIOParameters=GPIO_Label
+PA2.GPIO_Label=RMII_MDIO [LAN8742A-CZ-TR_MDIO]
+PA2.Locked=true
+PA2.Mode=RMII
+PA2.Signal=ETH_MDIO
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=RMII_CRS_DV [LAN8742A-CZ-TR_CRS_DV]
+PA7.Locked=true
+PA7.Mode=RMII
+PA7.Signal=ETH_CRS_DV
+PA8.GPIOParameters=GPIO_Label
+PA8.GPIO_Label=USB_SOF [TP1]
+PA8.Locked=true
+PA8.Mode=Activate_SOF_FS
+PA8.Signal=USB_OTG_FS_SOF
+PA9.GPIOParameters=GPIO_Label
+PA9.GPIO_Label=USB_VBUS
+PA9.Locked=true
+PA9.Mode=Activate_VBUS
+PA9.Signal=USB_OTG_FS_VBUS
+PB13.GPIOParameters=GPIO_Label
+PB13.GPIO_Label=RMII_TXD1 [LAN8742A-CZ-TR_TXD1]
+PB13.Locked=true
+PB13.Mode=RMII
+PB13.Signal=ETH_TXD1
+PB14.GPIOParameters=GPIO_Label
+PB14.GPIO_Label=LD3 [Red]
+PB14.Locked=true
+PB14.Signal=GPIO_Output
+PB3.GPIOParameters=GPIO_Label
+PB3.GPIO_Label=SWO
+PB3.Locked=true
+PB3.Signal=SYS_JTDO-SWO
+PB7.GPIOParameters=GPIO_Label
+PB7.GPIO_Label=LD2 [Blue]
+PB7.Locked=true
+PB7.Signal=GPIO_Output
+PC1.GPIOParameters=GPIO_Label
+PC1.GPIO_Label=RMII_MDC [LAN8742A-CZ-TR_MDC]
+PC1.Locked=true
+PC1.Mode=RMII
+PC1.Signal=ETH_MDC
+PC13.GPIOParameters=GPIO_Label
+PC13.GPIO_Label=USER_Btn [B1]
+PC13.Locked=true
+PC13.Signal=GPXTI13
+PC14/OSC32_IN.Locked=true
+PC14/OSC32_IN.Mode=LSE-External-Oscillator
+PC14/OSC32_IN.Signal=RCC_OSC32_IN
+PC15/OSC32_OUT.Locked=true
+PC15/OSC32_OUT.Mode=LSE-External-Oscillator
+PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
+PC4.GPIOParameters=GPIO_Label
+PC4.GPIO_Label=RMII_RXD0 [LAN8742A-CZ-TR_RXD0]
+PC4.Locked=true
+PC4.Mode=RMII
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Label
+PC5.GPIO_Label=RMII_RXD1 [LAN8742A-CZ-TR_RXD1]
+PC5.Locked=true
+PC5.Mode=RMII
+PC5.Signal=ETH_RXD1
+PCC.Checker=false
+PCC.Line=STM32F7x7
+PCC.MCU=STM32F767ZITx
+PCC.PartNumber=STM32F767ZITx
+PCC.Seq0=0
+PCC.Series=STM32F7
+PCC.Temperature=25
+PCC.Vdd=3.6
+PD8.GPIOParameters=GPIO_Label
+PD8.GPIO_Label=STLK_RX [STM32F103CBT6_PA3]
+PD8.Locked=true
+PD8.Mode=Asynchronous
+PD8.Signal=USART3_TX
+PD9.GPIOParameters=GPIO_Label
+PD9.GPIO_Label=STLK_TX [STM32F103CBT6_PA2]
+PD9.Locked=true
+PD9.Mode=Asynchronous
+PD9.Signal=USART3_RX
+PG11.GPIOParameters=GPIO_Label
+PG11.GPIO_Label=RMII_TX_EN [LAN8742A-CZ-TR_TXEN]
+PG11.Locked=true
+PG11.Mode=RMII
+PG11.Signal=ETH_TX_EN
+PG13.GPIOParameters=GPIO_Label
+PG13.GPIO_Label=RMII_TXD0 [LAN8742A-CZ-TR_TXD0]
+PG13.Locked=true
+PG13.Mode=RMII
+PG13.Signal=ETH_TXD0
+PG6.GPIOParameters=GPIO_Label
+PG6.GPIO_Label=USB_PowerSwitchOn [STMPS2151STR_EN]
+PG6.Locked=true
+PG6.Signal=GPIO_Output
+PG7.GPIOParameters=GPIO_Label
+PG7.GPIO_Label=USB_OverCurrent [STMPS2151STR_FAULT]
+PG7.Locked=true
+PG7.Signal=GPIO_Input
+PH0/OSC_IN.GPIOParameters=GPIO_Label
+PH0/OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8]
+PH0/OSC_IN.Locked=true
+PH0/OSC_IN.Mode=HSE-External-Clock-Source
+PH0/OSC_IN.Signal=RCC_OSC_IN
+PH1/OSC_OUT.Locked=true
+PH1/OSC_OUT.Mode=HSE-External-Clock-Source
+PH1/OSC_OUT.Signal=RCC_OSC_OUT
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32F767ZITx
+ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.14.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=0
+ProjectManager.MainLocation=Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=EWARM V8
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,4-MX_ETH_Init-ETH-false-HAL-true,5-MX_USART3_UART_Init-USART3-false-HAL-true,6-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true
+RCC.48MHZClocksFreq_Value=24000000
+RCC.ADC12outputFreq_Value=72000000
+RCC.ADC34outputFreq_Value=72000000
+RCC.AHBFreq_Value=216000000
+RCC.APB1CLKDivider=RCC_HCLK_DIV4
+RCC.APB1Freq_Value=54000000
+RCC.APB1TimFreq_Value=108000000
+RCC.APB2CLKDivider=RCC_HCLK_DIV2
+RCC.APB2Freq_Value=108000000
+RCC.APB2TimFreq_Value=216000000
+RCC.CECFreq_Value=32786.88524590164
+RCC.CortexFreq_Value=216000000
+RCC.DFSDMAudioFreq_Value=96000000
+RCC.DFSDMFreq_Value=108000000
+RCC.EthernetFreq_Value=216000000
+RCC.FCLKCortexFreq_Value=216000000
+RCC.FamilyName=M
+RCC.HCLKFreq_Value=216000000
+RCC.HSE_VALUE=8000000
+RCC.HSI_VALUE=16000000
+RCC.I2C1Freq_Value=54000000
+RCC.I2C2Freq_Value=54000000
+RCC.I2C3Freq_Value=54000000
+RCC.I2C4Freq_Value=54000000
+RCC.I2SClocksFreq_Value=48000000
+RCC.I2SFreq_Value=96000000
+RCC.IPParameters=48MHZClocksFreq_Value,ADC12outputFreq_Value,ADC34outputFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SClocksFreq_Value,I2SFreq_Value,LCDTFTFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSI_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,MCOFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLMCOFreq_Value,PLLMUL,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PRESCALERUSB,RNGFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,SYSCLKSourceVirtual,TIM15Freq_Value,TIM16Freq_Value,TIM17Freq_Value,TIM1Freq_Value,TIM20Freq_Value,TIM2Freq_Value,TIM3Freq_Value,TIM8Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutput2Freq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VcooutputI2S,WatchDogFreq_Value
+RCC.LCDTFTFreq_Value=48000000
+RCC.LCDTFToutputFreq_Value=96000000
+RCC.LPTIM1Freq_Value=54000000
+RCC.LSI_VALUE=32000
+RCC.MCO1PinFreq_Value=16000000
+RCC.MCO2PinFreq_Value=216000000
+RCC.MCOFreq_Value=72000000
+RCC.PLLCLKFreq_Value=216000000
+RCC.PLLI2SPCLKFreq_Value=96000000
+RCC.PLLI2SQCLKFreq_Value=96000000
+RCC.PLLI2SRCLKFreq_Value=96000000
+RCC.PLLI2SRoutputFreq_Value=96000000
+RCC.PLLM=8
+RCC.PLLMCOFreq_Value=72000000
+RCC.PLLMUL=RCC_PLL_MUL9
+RCC.PLLN=432
+RCC.PLLQ=9
+RCC.PLLQCLKFreq_Value=48000000
+RCC.PLLQoutputFreq_Value=48000000
+RCC.PLLRFreq_Value=216000000
+RCC.PLLSAIPCLKFreq_Value=96000000
+RCC.PLLSAIQCLKFreq_Value=96000000
+RCC.PLLSAIRCLKFreq_Value=96000000
+RCC.PLLSAIoutputFreq_Value=96000000
+RCC.PRESCALERUSB=RCC_USBCLKSOURCE_PLL_DIV1_5
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.RTCHSEDivFreq_Value=4000000
+RCC.SAI1Freq_Value=96000000
+RCC.SAI2Freq_Value=96000000
+RCC.SDMMC2Freq_Value=216000000
+RCC.SDMMCFreq_Value=216000000
+RCC.SPDIFRXFreq_Value=96000000
+RCC.SYSCLKFreq_VALUE=216000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.SYSCLKSourceVirtual=RCC_SYSCLKSOURCE_PLLCLK
+RCC.TIM15Freq_Value=72000000
+RCC.TIM16Freq_Value=72000000
+RCC.TIM17Freq_Value=72000000
+RCC.TIM1Freq_Value=72000000
+RCC.TIM20Freq_Value=72000000
+RCC.TIM2Freq_Value=72000000
+RCC.TIM3Freq_Value=72000000
+RCC.TIM8Freq_Value=72000000
+RCC.UART4Freq_Value=54000000
+RCC.UART5Freq_Value=54000000
+RCC.UART7Freq_Value=54000000
+RCC.UART8Freq_Value=54000000
+RCC.USART1Freq_Value=108000000
+RCC.USART2Freq_Value=54000000
+RCC.USART3Freq_Value=54000000
+RCC.USART6Freq_Value=108000000
+RCC.USBFreq_Value=48000000
+RCC.VCOI2SOutputFreq_Value=192000000
+RCC.VCOInputFreq_Value=1000000
+RCC.VCOOutput2Freq_Value=8000000
+RCC.VCOOutputFreq_Value=432000000
+RCC.VCOSAIOutputFreq_Value=192000000
+RCC.VcooutputI2S=48000000
+RCC.WatchDogFreq_Value=32000
+SH.GPXTI13.0=GPIO_EXTI13
+SH.GPXTI13.ConfNb=1
+USART3.IPParameters=VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=NUCLEO-F767ZI
+boardIOC=true

project_0/board/CubeMX_Config/Inc/main.h

@@ -0,0 +1,141 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  ** This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+#define USER_Btn_Pin GPIO_PIN_13
+#define USER_Btn_GPIO_Port GPIOC
+#define MCO_Pin GPIO_PIN_0
+#define MCO_GPIO_Port GPIOH
+#define RMII_MDC_Pin GPIO_PIN_1
+#define RMII_MDC_GPIO_Port GPIOC
+#define RMII_REF_CLK_Pin GPIO_PIN_1
+#define RMII_REF_CLK_GPIO_Port GPIOA
+#define RMII_MDIO_Pin GPIO_PIN_2
+#define RMII_MDIO_GPIO_Port GPIOA
+#define RMII_CRS_DV_Pin GPIO_PIN_7
+#define RMII_CRS_DV_GPIO_Port GPIOA
+#define RMII_RXD0_Pin GPIO_PIN_4
+#define RMII_RXD0_GPIO_Port GPIOC
+#define RMII_RXD1_Pin GPIO_PIN_5
+#define RMII_RXD1_GPIO_Port GPIOC
+#define RMII_TXD1_Pin GPIO_PIN_13
+#define RMII_TXD1_GPIO_Port GPIOB
+#define LD3_Pin GPIO_PIN_14
+#define LD3_GPIO_Port GPIOB
+#define STLK_RX_Pin GPIO_PIN_8
+#define STLK_RX_GPIO_Port GPIOD
+#define STLK_TX_Pin GPIO_PIN_9
+#define STLK_TX_GPIO_Port GPIOD
+#define USB_PowerSwitchOn_Pin GPIO_PIN_6
+#define USB_PowerSwitchOn_GPIO_Port GPIOG
+#define USB_OverCurrent_Pin GPIO_PIN_7
+#define USB_OverCurrent_GPIO_Port GPIOG
+#define USB_SOF_Pin GPIO_PIN_8
+#define USB_SOF_GPIO_Port GPIOA
+#define USB_VBUS_Pin GPIO_PIN_9
+#define USB_VBUS_GPIO_Port GPIOA
+#define USB_ID_Pin GPIO_PIN_10
+#define USB_ID_GPIO_Port GPIOA
+#define USB_DM_Pin GPIO_PIN_11
+#define USB_DM_GPIO_Port GPIOA
+#define USB_DP_Pin GPIO_PIN_12
+#define USB_DP_GPIO_Port GPIOA
+#define TMS_Pin GPIO_PIN_13
+#define TMS_GPIO_Port GPIOA
+#define TCK_Pin GPIO_PIN_14
+#define TCK_GPIO_Port GPIOA
+#define RMII_TX_EN_Pin GPIO_PIN_11
+#define RMII_TX_EN_GPIO_Port GPIOG
+#define RMII_TXD0_Pin GPIO_PIN_13
+#define RMII_TXD0_GPIO_Port GPIOG
+#define SWO_Pin GPIO_PIN_3
+#define SWO_GPIO_Port GPIOB
+#define LD2_Pin GPIO_PIN_7
+#define LD2_GPIO_Port GPIOB
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Inc/stm32f7xx_hal_conf.h

@@ -0,0 +1,458 @@
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_hal_conf.h
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CONF_H
+#define __STM32F7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver 
+  */
+#define HAL_MODULE_ENABLED  
+
+/* #define HAL_ADC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_CAN_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+#define HAL_ETH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+/* #define HAL_SDRAM_MODULE_ENABLED   */
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+/* #define HAL_LTDC_MODULE_ENABLED   */
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+/* #define HAL_SD_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+/* #define HAL_SPI_MODULE_ENABLED   */
+/* #define HAL_TIM_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_EXTI_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).  
+  */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL). 
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE) 
+ #define LSI_VALUE  ((uint32_t)32000U)       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.  */
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  ((uint32_t)32768U)    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source 
+  *        frequency, this source is inserted directly through I2S_CKIN pad. 
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    ((uint32_t)12288000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */     
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              0U
+#define  ART_ACCLERATOR_ENABLE        0U /* To enable instruction cache and prefetch */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */   
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* LAN8742A_PHY_ADDRESS Address*/ 
+#define LAN8742A_PHY_ADDRESS           0
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 
+#define PHY_RESET_DELAY                 ((uint32_t)0x000000FFU)
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                ((uint32_t)0x00000FFFU)
+
+#define PHY_READ_TO                     ((uint32_t)0x0000FFFFU)
+#define PHY_WRITE_TO                    ((uint32_t)0x0000FFFFU)
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x00U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x01U)    /*!< Transceiver Basic Status Register    */
+ 
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+  
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
+
+#define PHY_ISFR                        ((uint16_t)0x000BU)    /*!< PHY Interrupt Source Flag register Offset   */
+#define PHY_ISFR_INT4                   ((uint16_t)0x000BU)  /*!< PHY Link down inturrupt       */  
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file 
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+   
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f7xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32f7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f7xx_hal_cryp.h" 
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+ 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */      
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32f7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32f7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */   
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CONF_H */
+ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Inc/stm32f7xx_it.h

@@ -0,0 +1,84 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_IT_H
+#define __STM32F7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Src/main.c

@@ -0,0 +1,396 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  ** This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+
+ETH_HandleTypeDef heth;
+
+UART_HandleTypeDef huart3;
+
+PCD_HandleTypeDef hpcd_USB_OTG_FS;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ETH_Init(void);
+static void MX_USART3_UART_Init(void);
+static void MX_USB_OTG_FS_PCD_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ETH_Init();
+  MX_USART3_UART_Init();
+  MX_USB_OTG_FS_PCD_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /**Configure LSE Drive Capability 
+  */
+  HAL_PWR_EnableBkUpAccess();
+  /**Configure the main internal regulator output voltage 
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /**Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 432;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Activate the Over-Drive mode 
+  */
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48;
+  PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief ETH Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ETH_Init(void)
+{
+
+  /* USER CODE BEGIN ETH_Init 0 */
+
+  /* USER CODE END ETH_Init 0 */
+
+   uint8_t MACAddr[6] ;
+
+  /* USER CODE BEGIN ETH_Init 1 */
+
+  /* USER CODE END ETH_Init 1 */
+  heth.Instance = ETH;
+  heth.Init.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE;
+  heth.Init.PhyAddress = LAN8742A_PHY_ADDRESS;
+  MACAddr[0] = 0x00;
+  MACAddr[1] = 0x80;
+  MACAddr[2] = 0xE1;
+  MACAddr[3] = 0x00;
+  MACAddr[4] = 0x00;
+  MACAddr[5] = 0x00;
+  heth.Init.MACAddr = &MACAddr[0];
+  heth.Init.RxMode = ETH_RXPOLLING_MODE;
+  heth.Init.ChecksumMode = ETH_CHECKSUM_BY_HARDWARE;
+  heth.Init.MediaInterface = ETH_MEDIA_INTERFACE_RMII;
+
+  /* USER CODE BEGIN MACADDRESS */
+    
+  /* USER CODE END MACADDRESS */
+
+  if (HAL_ETH_Init(&heth) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ETH_Init 2 */
+
+  /* USER CODE END ETH_Init 2 */
+
+}
+
+/**
+  * @brief USART3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART3_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART3_Init 0 */
+
+  /* USER CODE END USART3_Init 0 */
+
+  /* USER CODE BEGIN USART3_Init 1 */
+
+  /* USER CODE END USART3_Init 1 */
+  huart3.Instance = USART3;
+  huart3.Init.BaudRate = 115200;
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;
+  huart3.Init.StopBits = UART_STOPBITS_1;
+  huart3.Init.Parity = UART_PARITY_NONE;
+  huart3.Init.Mode = UART_MODE_TX_RX;
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART3_Init 2 */
+
+  /* USER CODE END USART3_Init 2 */
+
+}
+
+/**
+  * @brief USB_OTG_FS Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USB_OTG_FS_PCD_Init(void)
+{
+
+  /* USER CODE BEGIN USB_OTG_FS_Init 0 */
+
+  /* USER CODE END USB_OTG_FS_Init 0 */
+
+  /* USER CODE BEGIN USB_OTG_FS_Init 1 */
+
+  /* USER CODE END USB_OTG_FS_Init 1 */
+  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
+  hpcd_USB_OTG_FS.Init.dev_endpoints = 6;
+  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.ep0_mps = DEP0CTL_MPS_64;
+  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_OTG_FS.Init.Sof_enable = ENABLE;
+  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = ENABLE;
+  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
+  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_OTG_FS_Init 2 */
+
+  /* USER CODE END USB_OTG_FS_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, LD3_Pin|LD2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(USB_PowerSwitchOn_GPIO_Port, USB_PowerSwitchOn_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : USER_Btn_Pin */
+  GPIO_InitStruct.Pin = USER_Btn_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(USER_Btn_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : LD3_Pin LD2_Pin */
+  GPIO_InitStruct.Pin = LD3_Pin|LD2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : USB_PowerSwitchOn_Pin */
+  GPIO_InitStruct.Pin = USB_PowerSwitchOn_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(USB_PowerSwitchOn_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : USB_OverCurrent_Pin */
+  GPIO_InitStruct.Pin = USB_OverCurrent_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(USB_OverCurrent_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{ 
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Src/stm32f7xx_hal_msp.c

@@ -0,0 +1,364 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32f7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization 
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  ** This notice applies to any and all portions of this file
+  * that are not between comment pairs USER CODE BEGIN and
+  * USER CODE END. Other portions of this file, whether 
+  * inserted by the user or by software development tools
+  * are owned by their respective copyright owners.
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+ 
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ETH MSP Initialization
+* This function configures the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspInit 0 */
+
+  /* USER CODE END ETH_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ETH_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    /**ETH GPIO Configuration    
+    PC1     ------> ETH_MDC
+    PA1     ------> ETH_REF_CLK
+    PA2     ------> ETH_MDIO
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    PB13     ------> ETH_TXD1
+    PG11     ------> ETH_TX_EN
+    PG13     ------> ETH_TXD0 
+    */
+    GPIO_InitStruct.Pin = RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = RMII_TXD1_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(RMII_TXD1_GPIO_Port, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = RMII_TX_EN_Pin|RMII_TXD0_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ETH_MspInit 1 */
+
+  /* USER CODE END ETH_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ETH MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
+{
+
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspDeInit 0 */
+
+  /* USER CODE END ETH_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ETH_CLK_DISABLE();
+  
+    /**ETH GPIO Configuration    
+    PC1     ------> ETH_MDC
+    PA1     ------> ETH_REF_CLK
+    PA2     ------> ETH_MDIO
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    PB13     ------> ETH_TXD1
+    PG11     ------> ETH_TX_EN
+    PG13     ------> ETH_TXD0 
+    */
+    HAL_GPIO_DeInit(GPIOC, RMII_MDC_Pin|RMII_RXD0_Pin|RMII_RXD1_Pin);
+
+    HAL_GPIO_DeInit(GPIOA, RMII_REF_CLK_Pin|RMII_MDIO_Pin|RMII_CRS_DV_Pin);
+
+    HAL_GPIO_DeInit(RMII_TXD1_GPIO_Port, RMII_TXD1_Pin);
+
+    HAL_GPIO_DeInit(GPIOG, RMII_TX_EN_Pin|RMII_TXD0_Pin);
+
+  /* USER CODE BEGIN ETH_MspDeInit 1 */
+
+  /* USER CODE END ETH_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspInit 0 */
+
+  /* USER CODE END USART3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART3_CLK_ENABLE();
+  
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**USART3 GPIO Configuration    
+    PD8     ------> USART3_TX
+    PD9     ------> USART3_RX 
+    */
+    GPIO_InitStruct.Pin = STLK_RX_Pin|STLK_TX_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART3_MspInit 1 */
+
+  /* USER CODE END USART3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+
+  if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+  /* USER CODE END USART3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART3_CLK_DISABLE();
+  
+    /**USART3 GPIO Configuration    
+    PD8     ------> USART3_TX
+    PD9     ------> USART3_RX 
+    */
+    HAL_GPIO_DeInit(GPIOD, STLK_RX_Pin|STLK_TX_Pin);
+
+  /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+  /* USER CODE END USART3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief PCD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB_OTG_FS GPIO Configuration    
+    PA8     ------> USB_OTG_FS_SOF
+    PA9     ------> USB_OTG_FS_VBUS
+    PA10     ------> USB_OTG_FS_ID
+    PA11     ------> USB_OTG_FS_DM
+    PA12     ------> USB_OTG_FS_DP 
+    */
+    GPIO_InitStruct.Pin = USB_SOF_Pin|USB_ID_Pin|USB_DM_Pin|USB_DP_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = USB_VBUS_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(USB_VBUS_GPIO_Port, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief PCD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
+{
+
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
+  
+    /**USB_OTG_FS GPIO Configuration    
+    PA8     ------> USB_OTG_FS_SOF
+    PA9     ------> USB_OTG_FS_VBUS
+    PA10     ------> USB_OTG_FS_ID
+    PA11     ------> USB_OTG_FS_DM
+    PA12     ------> USB_OTG_FS_DP 
+    */
+    HAL_GPIO_DeInit(GPIOA, USB_SOF_Pin|USB_VBUS_Pin|USB_ID_Pin|USB_DM_Pin 
+                          |USB_DP_Pin);
+
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Src/stm32f7xx_it.c

@@ -0,0 +1,217 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  *
+  * COPYRIGHT(c) 2018 STMicroelectronics
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+ 
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M7 Processor Interruption and Exception Handlers          */ 
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f7xx.s).                    */
+/******************************************************************************/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/CubeMX_Config/Src/system_stm32f7xx.c

@@ -0,0 +1,278 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from 
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f7xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f7xx.h"
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Variables
+  * @{
+  */
+
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

project_0/board/Kconfig

@@ -0,0 +1,67 @@
+menu "Hardware Drivers Config"
+
+config SOC_STM32F767ZI 
+    bool
+    select SOC_SERIES_STM32F7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_USB_TO_USART 
+        bool "Enable USB TO USART (uart3)"
+        select BSP_USING_UART3
+        default y
+        
+    config BSP_USING_ETH
+        bool "Enable Ethernet"
+        select RT_USING_LWIP
+        default n
+
+        if BSP_USING_ETH
+            choice
+                prompt "On-board PHY chip"
+                default PHY_USING_LAN8720A
+
+                config PHY_USING_LAN8720A
+                    bool "LAN8720A"
+
+                config PHY_USING_DM9161CEP
+                    bool "DM9161CEP"
+
+            endchoice
+        endif
+ 
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART3"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default y
+
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA
+                default n
+        endif
+    source "libraries/HAL_Drivers/Kconfig"
+    
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+ 
+endmenu

project_0/board/SConscript

@@ -0,0 +1,35 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Glob('board.c')
+src += Glob('CubeMX_Config/Src/stm32f7xx_hal_msp.c')
+
+if GetDepend(['BSP_USING_ETH']):
+    src += Glob('ports/phy_reset.c')
+
+path = [cwd]
+path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/gcc/startup_stm32f767xx.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/arm/startup_stm32f767xx.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [startup_path_prefix + '/STM32F7xx_HAL/CMSIS/Device/ST/STM32F7xx/Source/Templates/iar/startup_stm32f767xx.s']
+
+# STM32F756xx || STM32F746xx || STM32F745xx || STM32F767xx  || 
+# STM32F769xx || STM32F777xx || STM32F779xx || STM32F722xx  || 
+# STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx  || STM32F750xx
+# You can select chips from the list above
+CPPDEFINES = ['STM32F767xx']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+Return('group')

project_0/board/board.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-1-10      e31207077    add stm32f767-st-nucleo bsp
+ */
+
+#include "board.h"
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /**Configure LSE Drive Capability 
+  */
+  HAL_PWR_EnableBkUpAccess();
+  /**Configure the main internal regulator output voltage 
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+  /**Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 8;
+  RCC_OscInitStruct.PLL.PLLN = 432;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 9;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Activate the Over-Drive mode 
+  */
+  if (HAL_PWREx_EnableOverDrive() != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /**Initializes the CPU, AHB and APB busses clocks 
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART3|RCC_PERIPHCLK_CLK48;
+  PeriphClkInitStruct.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
+  PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+

project_0/board/board.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-5      SummerGift   first version
+ * 2019-1-10      e31207077    add stm32f767-st-nucleo bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32f7xx.h>
+#include "drv_common.h"
+#include "drv_gpio.h"
+
+#define STM32_FLASH_START_ADRESS     ((uint32_t)0x08000000)
+#define STM32_FLASH_SIZE             (2048 * 1024)
+#define STM32_FLASH_END_ADDRESS      ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
+
+#define STM32_SRAM_SIZE           (512)
+#define STM32_SRAM_END            (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      (&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN      (&__bss_end)
+#endif
+
+#define HEAP_END        STM32_SRAM_END
+
+void SystemClock_Config(void);
+
+#endif

project_0/board/linker_scripts/link.icf

@@ -0,0 +1,28 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x081FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2007FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0400;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, last block CSTACK};

project_0/board/linker_scripts/link.lds

@@ -0,0 +1,157 @@
+/*
+ * linker script for STM32F4xx with GNU ld
+ * bernard.xiong 2009-10-14
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH =  512k /* 512K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

project_0/board/linker_scripts/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00200000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00200000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20020000 0x00080000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

project_0/board/ports/phy_reset.c

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-27     luhuadong    first version
+ */
+
+#include <board.h>
+
+void phy_reset(void)
+{
+    /*
+     * The PHY reset pin of NUCLEO-F767ZI is connected to the MCU reset pin,
+     * so no additional reset is required.
+     */
+    
+    return ;
+}

project_0/cconfig.h

@@ -0,0 +1,9 @@
+#ifndef CCONFIG_H__
+#define CCONFIG_H__
+/* Automatically generated file; DO NOT EDIT. */
+/* compiler configure file for RT-Thread in GCC*/
+
+
+#define STDC "1989"
+
+#endif

project_0/libraries/HAL_Drivers/Kconfig

@@ -0,0 +1,62 @@
+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif
+
+config BSP_USING_CRC
+    bool "Enable CRC (CRC-32 0x04C11DB7 Polynomial)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRC
+    # "Crypto device frame dose not support above 8-bits granularity"
+    # "Reserve progress, running well, about 32-bits granularity, such as stm32f1, stm32f4"
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F0 || SOC_SERIES_STM32F7 || SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
+    default n 
+
+config BSP_USING_RNG
+    bool "Enable RNG (Random Number Generator)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_RNG
+    depends on (SOC_SERIES_STM32L4 || SOC_SERIES_STM32F4 || SOC_SERIES_STM32F7 || \
+                SOC_SERIES_STM32H7 || SOC_SERIES_STM32MP1)
+    default n
+
+config BSP_USING_HASH
+    bool "Enable HASH (Hash House Harriers)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_HASH
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
+config BSP_USING_CRYP
+    bool "Enable CRYP (Encrypt And Decrypt Data)"
+    select RT_USING_HWCRYPTO
+    select RT_HWCRYPTO_USING_CRYP
+    depends on (SOC_SERIES_STM32MP1)
+    default n
+
+config BSP_USING_UDID
+    bool "Enable UDID (Unique Device Identifier)"
+    select RT_USING_HWCRYPTO
+    default n
+

project_0/libraries/HAL_Drivers/SConscript

@@ -0,0 +1,116 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+if GetDepend(['RT_USING_HWTIMER']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['RT_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['RT_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['RT_USING_QSPI']):
+    src += ['drv_qspi.c']
+
+if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_ETH', 'RT_USING_LWIP']):
+    src += ['drv_eth.c']
+
+if GetDepend(['RT_USING_ADC']):
+    src += Glob('drv_adc.c')
+
+if GetDepend(['RT_USING_DAC']):
+    src += Glob('drv_dac.c')
+
+if GetDepend(['RT_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['RT_USING_PM', 'SOC_SERIES_STM32L4']):
+    src += ['drv_pm.c']
+    src += ['drv_lptim.c']
+
+if GetDepend('BSP_USING_SDRAM'):
+    src += ['drv_sdram.c']
+
+if GetDepend('BSP_USING_LCD'):
+    src += ['drv_lcd.c']
+
+if GetDepend('BSP_USING_LCD_MIPI'):
+    src += ['drv_lcd_mipi.c']
+
+if GetDepend('BSP_USING_ONCHIP_RTC'):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32G0']):
+    src += ['drv_flash/drv_flash_g0.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F0']):
+    src += ['drv_flash/drv_flash_f0.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
+    src += ['drv_flash/drv_flash_f1.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F2']):
+    src += ['drv_flash/drv_flash_f2.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
+    src += ['drv_flash/drv_flash_f4.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
+    src += ['drv_flash/drv_flash_f7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
+    src += ['drv_flash/drv_flash_l4.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
+    src += ['drv_flash/drv_flash_h7.c']
+
+if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32WB']):
+    src += ['drv_flash/drv_flash_wb.c']
+
+if GetDepend('RT_USING_HWCRYPTO'):
+    src += ['drv_crypto.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_SDIO']):
+    src += ['drv_sdio.c']
+
+if GetDepend(['BSP_USING_USBD']):
+    src += ['drv_usbd.c']
+
+if GetDepend(['BSP_USING_PULSE_ENCODER']):
+    src += ['drv_pulse_encoder.c']
+
+if GetDepend(['BSP_USING_USBH']):
+    src += ['drv_usbh.c']
+
+src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+if GetDepend('BSP_USING_ON_CHIP_FLASH'):
+    path += [cwd + '/drv_flash']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

project_0/libraries/HAL_Drivers/config/f0/adc_config.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f0/dma_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+
+/* DMA1 channel2-3 DMA2 channel1-2 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler          DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define UART1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE            DMA1_Channel3
+#define UART1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler 
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+
+#if  defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_RX_TX_IRQHandler       DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Ch2_3_DMA2_Ch1_2_IRQn
+#endif
+/* DMA1 channel2-3 DMA2 channel1-2 */
+
+/* DMA1 channel4-7 DMA2 channel3-5 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Channel5
+#define UART2_RX_DMA_IRQ                 DMA1_Ch4_7_DMA2_Ch3_5_IRQn
+#endif
+/* DMA1 channel4-7 DMA2 channel3-5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f0/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f0/spi_config.h

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f0/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-24     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM14,         \
+       .tim_irqn                = TIM14_IRQn,    \
+       .name                    = "timer14",     \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef BSP_USING_TIM16
+#ifndef TIM16_CONFIG
+#define TIM16_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM16,         \
+       .tim_irqn                = TIM16_IRQn,    \
+       .name                    = "timer16",     \
+    }
+#endif /* TIM16_CONFIG */
+#endif /* BSP_USING_TIM16 */
+
+#ifdef BSP_USING_TIM17
+#ifndef TIM17_CONFIG
+#define TIM17_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM17,         \
+       .tim_irqn                = TIM17_IRQn,    \
+       .name                    = "timer17",     \
+    }
+#endif /* TIM17_CONFIG */
+#endif /* BSP_USING_TIM17 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f0/uart_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+    
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/adc_config.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-07     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC1,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC2,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                \
+    {                                                              \
+       .Instance                   = ADC3,                         \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,          \
+       .Init.ScanConvMode          = ADC_SCAN_DISABLE,             \
+       .Init.ContinuousConvMode    = DISABLE,                      \
+       .Init.NbrOfConversion       = 1,                            \
+       .Init.DiscontinuousConvMode = DISABLE,                      \
+       .Init.NbrOfDiscConversion   = 1,                            \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,           \
+    }  
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/dma_config.h

@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-02     SummerGift   first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1 */
+/* DMA1 channel2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler          DMA1_Channel2_IRQHandler
+#define SPI1_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_RX_DMA_IRQ                 DMA1_Channel2_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler         DMA1_Channel2_IRQHandler
+#define UART3_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE           DMA1_Channel2
+#define UART3_TX_DMA_IRQ                DMA1_Channel2_IRQn
+#endif
+
+/* DMA1 channel3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel3
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel3_IRQn
+#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler         DMA1_Channel3_IRQHandler
+#define UART3_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE           DMA1_Channel3
+#define UART3_RX_DMA_IRQ                DMA1_Channel3_IRQn
+#endif
+
+/* DMA1 channel4 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel4_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel4
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel4_IRQn
+#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA1_Channel4_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_TX_DMA_INSTANCE           DMA1_Channel4
+#define UART1_TX_DMA_IRQ                DMA1_Channel4_IRQn
+#endif
+
+/* DMA1 channel5 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel5_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel5
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel5_IRQn
+
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel5
+#define UART1_RX_DMA_IRQ                DMA1_Channel5_IRQn
+#endif
+
+/* DMA1 channel6 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel6_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel6
+#define UART2_RX_DMA_IRQ                DMA1_Channel6_IRQn
+#endif
+
+/* DMA1 channel7 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler         DMA1_Channel7_IRQHandler
+#define UART2_TX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE           DMA1_Channel7
+#define UART2_TX_DMA_IRQ                DMA1_Channel7_IRQn
+#endif
+
+/* DMA2 channel1 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler          DMA2_Channel1_IRQHandler
+#define SPI3_RX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_RX_DMA_INSTANCE            DMA2_Channel1
+#define SPI3_RX_DMA_IRQ                 DMA2_Channel1_IRQn
+#endif
+
+/* DMA2 channel2 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler          DMA2_Channel2_IRQHandler
+#define SPI3_TX_DMA_RCC                 RCC_AHBENR_DMA2EN
+#define SPI3_TX_DMA_INSTANCE            DMA2_Channel2
+#define SPI3_TX_DMA_IRQ                 DMA2_Channel2_IRQn
+#endif
+
+/* DMA2 channel3 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler         DMA2_Channel3_IRQHandler
+#define UART4_RX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_RX_DMA_INSTANCE           DMA2_Channel3
+#define UART4_RX_DMA_IRQ                DMA2_Channel3_IRQn
+#endif
+/* DMA2 channel4 */
+/* DMA2 channel5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler         DMA2_Channel4_5_IRQHandler
+#define UART4_TX_DMA_RCC                RCC_AHBENR_DMA2EN
+#define UART4_TX_DMA_INSTANCE           DMA2_Channel5
+#define UART4_TX_DMA_IRQ                DMA2_Channel4_5_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                     \
+    {                                             \
+       .tim_handler.Instance     = TIM1,          \
+       .encoder_irqn             = TIM1_UP_IRQn,  \
+       .name                     = "pulse1"       \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM2,       \
+       .encoder_irqn             = TIM2_IRQn,  \
+       .name                     = "pulse2"    \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM3,       \
+       .encoder_irqn             = TIM3_IRQn,  \
+       .name                     = "pulse3"    \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                  \
+    {                                          \
+       .tim_handler.Instance     = TIM4,       \
+       .encoder_irqn             = TIM4_IRQn,  \
+       .name                     = "pulse4"    \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM1
+#ifndef PWM1_CONFIG
+#define PWM1_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM1,         \
+       .name                    = "pwm1",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM1_CONFIG */
+#endif /* BSP_USING_PWM1 */
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/sdio_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f1xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_tx.dma_rcc = RCC_AHBENR_DMA2EN,             \
+        .dma_rx.Instance = DMA2_Channel4,                \
+        .dma_rx.dma_irq = DMA2_Channel4_IRQn,            \
+        .dma_tx.Instance = DMA2_Channel4,                \
+        .dma_tx.dma_irq = DMA2_Channel4_IRQn,            \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f1/spi_config.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f1/tim_config.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f1/uart_config.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     BalanceTWK   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "dma_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/f1/usbd_config.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-07-29     Chinese66    change from f4 to f1
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#define USBD_IRQ_TYPE        USB_LP_CAN1_RX0_IRQn
+#define USBD_IRQ_HANDLER     USB_LP_CAN1_RX0_IRQHandler
+#define USBD_INSTANCE        USB
+#define USBD_PCD_SPEED       PCD_SPEED_FULL
+#define USBD_PCD_PHY_MODULE  PCD_PHY_EMBEDDED
+
+#ifndef BSP_USB_CONNECT_PIN
+#define BSP_USB_CONNECT_PIN  -1
+#endif
+
+#ifndef BSP_USB_PULL_UP_STATUS
+#define BSP_USB_PULL_UP_STATUS  1
+#endif
+#endif

project_0/libraries/HAL_Drivers/config/f2/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f2/dma_config.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART6_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART6_RX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+/* DMA2 stream3 */
+
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)	
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+
+/* DMA2 stream7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f2/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f2/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f2xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f2/spi_config.h

@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-05     SummerGift   modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f2/tim_config.h

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM4
+#ifndef TIM4_CONFIG
+#define TIM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .tim_irqn                = TIM4_IRQn,    \
+       .name                    = "timer4",     \
+    }
+#endif /* TIM4_CONFIG */
+#endif /* BSP_USING_TIM4 */
+
+#ifdef BSP_USING_TIM5
+#ifndef TIM5_CONFIG
+#define TIM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .tim_irqn                = TIM5_IRQn,    \
+       .name                    = "timer5",     \
+    }
+#endif /* TIM5_CONFIG */
+#endif /* BSP_USING_TIM5 */
+
+#ifdef BSP_USING_TIM7
+#ifndef TIM7_CONFIG
+#define TIM7_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM7,         \
+       .tim_irqn                = TIM7_IRQn,    \
+       .name                    = "timer7",     \
+    }
+#endif /* TIM7_CONFIG */
+#endif /* BSP_USING_TIM7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f2/uart_config.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/f4/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/dac_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/dma_config.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
+#define UART8_DMA_TX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART8_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_TX_DMA_INSTANCE            DMA1_Stream0
+#define UART8_TX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_TX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE            DMA1_Stream3
+#define UART3_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_TX_DMA_IRQ                 DMA1_Stream3_IRQn
+#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream3
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_TX_DMA_INSTANCE            DMA1_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_TX_DMA_IRQ                 DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream6
+#define UART2_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_TX_DMA_IRQ                 DMA1_Stream6_IRQn
+#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
+#define UART8_DMA_RX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART8_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_RX_DMA_INSTANCE            DMA1_Stream6
+#define UART8_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_RX_DMA_IRQ                 DMA1_Stream6_IRQn
+#endif
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_TX_DMA_INSTANCE            DMA1_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler          DMA2_Stream1_IRQHandler
+#define UART6_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE            DMA2_Stream1
+#define UART6_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                 DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_DMA_TX_IRQHandler         DMA2_Stream6_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_TX_DMA_INSTANCE           DMA2_Stream6
+#define UART6_TX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_TX_DMA_IRQ                DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Stream7_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Stream7
+#define UART1_TX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_TX_DMA_IRQ                DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM1,                \
+       .encoder_irqn            = TIM1_UP_TIM10_IRQn,  \
+       .name                    = "pulse1"             \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM2,                \
+       .encoder_irqn            = TIM2_IRQn,           \
+       .name                    = "pulse2"             \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM3,                \
+       .encoder_irqn            = TIM3_IRQn,           \
+       .name                    = "pulse3"             \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM4,                \
+       .encoder_irqn            = TIM4_IRQn,           \
+       .name                    = "pulse4"             \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/pwm_config.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef BSP_USING_PWM9
+#ifndef PWM9_CONFIG
+#define PWM9_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM9,         \
+       .name                    = "pwm9",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM9_CONFIG */
+#endif /* BSP_USING_PWM9 */
+
+#ifdef BSP_USING_PWM12
+#ifndef PWM12_CONFIG
+#define PWM12_CONFIG                            \
+    {                                           \
+       .tim_handle.Instance     = TIM12,        \
+       .name                    = "pwm12",      \
+       .channel                 = 0             \
+    }
+#endif /* PWM12_CONFIG */
+#endif /* BSP_USING_PWM12 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f4/spi_config.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-03     zylx         modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/tim_config.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                                         \
+    {                                                       \
+       .tim_handle.Instance     = TIM3,                     \
+       .tim_irqn                = TIM3_IRQn,                \
+       .name                    = "timer3",                 \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f4/uart_config.h

@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                         \
+        .irq_type = USART6_IRQn,                                    \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+		
+#if defined(BSP_UART6_TX_USING_DMA)
+#ifndef UART6_DMA_TX_CONFIG
+#define UART6_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART6_TX_DMA_INSTANCE,                         \
+        .channel = UART6_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_TX_DMA_RCC,                               \
+        .dma_irq = UART6_TX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_TX_CONFIG */
+#endif /* BSP_UART6_TX_USING_DMA */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .Instance = UART7,                                         \
+        .irq_type = UART7_IRQn,                                    \
+    }
+#endif /* UART7_CONFIG */
+
+#if defined(BSP_UART7_RX_USING_DMA)
+#ifndef UART7_DMA_RX_CONFIG
+#define UART7_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART7_RX_DMA_INSTANCE,                         \
+        .channel = UART7_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART7_RX_DMA_RCC,                               \
+        .dma_irq = UART7_RX_DMA_IRQ,                               \
+    }
+#endif /* UART7_DMA_RX_CONFIG */
+#endif /* BSP_UART7_RX_USING_DMA */
+		
+#if defined(BSP_UART7_TX_USING_DMA)
+#ifndef UART7_DMA_TX_CONFIG
+#define UART7_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART7_TX_DMA_INSTANCE,                         \
+        .channel = UART7_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART7_TX_DMA_RCC,                               \
+        .dma_irq = UART7_TX_DMA_IRQ,                               \
+    }
+#endif /* UART7_DMA_TX_CONFIG */
+#endif /* BSP_UART7_TX_USING_DMA */
+#endif /* BSP_USING_UART7 */
+
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .Instance = UART8,                                         \
+        .irq_type = UART8_IRQn,                                    \
+    }
+#endif /* UART8_CONFIG */
+
+#if defined(BSP_UART8_RX_USING_DMA)
+#ifndef UART8_DMA_RX_CONFIG
+#define UART8_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART8_RX_DMA_INSTANCE,                         \
+        .channel = UART8_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART8_RX_DMA_RCC,                               \
+        .dma_irq = UART8_RX_DMA_IRQ,                               \
+    }
+#endif /* UART8_DMA_RX_CONFIG */
+#endif /* BSP_UART8_RX_USING_DMA */
+		
+#if defined(BSP_UART8_TX_USING_DMA)
+#ifndef UART8_DMA_TX_CONFIG
+#define UART8_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART8_TX_DMA_INSTANCE,                         \
+        .channel = UART8_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART8_TX_DMA_RCC,                               \
+        .dma_irq = UART8_TX_DMA_IRQ,                               \
+    }
+#endif /* UART8_DMA_TX_CONFIG */
+#endif /* BSP_UART8_TX_USING_DMA */
+#endif /* BSP_USING_UART8 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/f4/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/f7/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/dma_config.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream2_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream2
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_11
+#define QSPI_DMA_IRQ                     DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE)
+#define SPI4_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_RX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32f7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/f7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/f7/uart_config.h

@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = USART6,                                          \
+        .irq_type = USART6_IRQn,                                     \
+    }
+#endif /* UART6_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_UART6_RX_USING_DMA)
+#ifndef UART6_DMA_RX_CONFIG
+#define UART6_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART6_RX_DMA_INSTANCE,                         \
+        .channel = UART6_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART6_RX_DMA_RCC,                               \
+        .dma_irq = UART6_RX_DMA_IRQ,                               \
+    }
+#endif /* UART6_DMA_RX_CONFIG */
+#endif /* BSP_UART6_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/g0/adc_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV1,          \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD,    \
+       .Init.EOCSelection          = ADC_EOC_SINGLE_CONV,           \
+       .Init.LowPowerAutoWait      = DISABLE,                       \
+       .Init.LowPowerAutoPowerOff  = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.DiscontinuousConvMode = ENABLE,                        \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = ENABLE,                        \
+       .Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN,      \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g0/dma_config.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 channel1  */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA1_Channel1_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHBENR_DMA1EN
+#define SPI1_RX_DMA_INSTANCE             DMA1_Channel1
+#define SPI1_RX_DMA_REQUEST              DMA_REQUEST_SPI1_RX
+#define SPI1_RX_DMA_IRQ                  DMA1_Channel1_IRQn
+#ifdef BSP_UART1_RX_USING_DMA
+#undef BSP_UART1_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA1_Channel1_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART1_RX_DMA_INSTANCE           DMA1_Channel1
+#define UART1_RX_DMA_REQUEST            DMA_REQUEST_USART1_RX
+#define UART1_RX_DMA_IRQ                DMA1_Channel1_IRQn
+#ifdef BSP_SPI2_RX_USING_DMA
+#undef BSP_SPI2_RX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler          DMA1_Channel1_IRQHandler
+#define SPI2_RX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE            DMA1_Channel1
+#define SPI2_RX_DMA_REQUEST             DMA_REQUEST_SPI2_RX
+#define SPI2_RX_DMA_IRQ                 DMA1_Channel1_IRQn
+#endif
+
+/* DMA1 channle2-3 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI1_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI1_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI1_TX_DMA_REQUEST             DMA_REQUEST_SPI1_TX
+#define SPI1_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#ifdef BSP_UART2_RX_USING_DMA
+#undef BSP_UART2_RX_USING_DMA
+#endif
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler         DMA1_Channel2_3_IRQHandler
+#define UART2_RX_DMA_RCC                RCC_AHBENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE           DMA1_Channel2
+#define UART2_RX_DMA_REQUEST            DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                DMA1_Channel2_3_IRQn
+#ifdef BSP_SPI2_TX_USING_DMA
+#undef BSP_SPI2_TX_USING_DMA
+#endif
+#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler          DMA1_Channel2_3_IRQHandler
+#define SPI2_TX_DMA_RCC                 RCC_AHBENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE            DMA1_Channel2
+#define SPI2_TX_DMA_REQUEST             DMA_REQUEST_SPI2_TX
+#define SPI2_TX_DMA_IRQ                 DMA1_Channel2_3_IRQn
+#endif
+
+#if defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
+#define LPUART1_DMA_RX_IRQHandler       DMA1_Ch4_7_DMAMUX1_OVR_IRQHandler
+#define LPUART1_RX_DMA_RCC              RCC_AHBENR_DMA1EN
+#define LPUART1_RX_DMA_INSTANCE         DMA1_Channel5
+#define LPUART1_RX_DMA_REQUEST          DMA_REQUEST_LPUART1_RX
+#define LPUART1_RX_DMA_IRQ              DMA1_Ch4_7_DMAMUX1_OVR_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g0/pwm_config.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g0/spi_config.h

@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .request = SPI1_TX_DMA_REQUEST,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .request = SPI1_RX_DMA_REQUEST,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .request = SPI2_TX_DMA_REQUEST,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .request = SPI2_RX_DMA_REQUEST,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/g0/tim_config.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-01-05     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 2000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM2
+#ifndef TIM2_CONFIG
+#define TIM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .tim_irqn                = TIM2_IRQn,    \
+       .name                    = "timer2",     \
+    }
+#endif /* TIM2_CONFIG */
+#endif /* BSP_USING_TIM2 */
+
+#ifdef BSP_USING_TIM3
+#ifndef TIM3_CONFIG
+#define TIM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .tim_irqn                = TIM3_IRQn,    \
+       .name                    = "timer3",     \
+    }
+#endif /* TIM3_CONFIG */
+#endif /* BSP_USING_TIM3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g0/uart_config.h

@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     zylx         first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#define LPUART1_IRQHandler      USART3_4_LPUART1_IRQHandler
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request =  LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request =  UART1_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request =  UART2_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#else
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request =  UART3_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#ifndef SOC_SERIES_STM32G0
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#else
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = USART4,                                         \
+        .irq_type = USART3_4_LPUART1_IRQn,                          \
+    }
+#endif /* UART4_CONFIG */
+#endif /* SOC_SERIES_STM32G0 */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request =  UART4_RX_DMA_REQUEST,                           \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                            \
+    {                                                               \
+        .Instance = DMA_NOT_AVAILABLE,                              \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UART_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/adc_config.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC1,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC2,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                 \
+    {                                                               \
+       .Instance                   = ADC3,                          \
+       .Init.ClockPrescaler        = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+       .Init.Resolution            = ADC_RESOLUTION_12B,            \
+       .Init.DataAlign             = ADC_DATAALIGN_RIGHT,           \
+       .Init.ScanConvMode          = DISABLE,                       \
+       .Init.EOCSelection          = DISABLE,                       \
+       .Init.ContinuousConvMode    = DISABLE,                       \
+       .Init.NbrOfConversion       = 1,                             \
+       .Init.DiscontinuousConvMode = DISABLE,                       \
+       .Init.NbrOfDiscConversion   = 0,                             \
+       .Init.ExternalTrigConv      = ADC_SOFTWARE_START,            \
+       .Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+       .Init.DMAContinuousRequests = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/dma_config.h

@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream0_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream0
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream0_IRQn
+#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART5_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART5_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
+#define UART8_DMA_TX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART8_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_TX_DMA_INSTANCE            DMA1_Stream0
+#define UART8_TX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_TX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
+#define UART3_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART3_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART3_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream1
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_DMA_RX_IRQHandler          DMA1_Stream2_IRQHandler
+#define UART4_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_RX_DMA_INSTANCE            DMA1_Stream2
+#define UART4_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_RX_DMA_IRQ                 DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
+#define UART3_DMA_TX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART3_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART3_TX_DMA_INSTANCE            DMA1_Stream3
+#define UART3_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART3_TX_DMA_IRQ                 DMA1_Stream3_IRQn
+#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
+#define UART7_DMA_RX_IRQHandler          DMA1_Stream3_IRQHandler
+#define UART7_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART7_RX_DMA_INSTANCE            DMA1_Stream3
+#define UART7_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART7_RX_DMA_IRQ                 DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_DMA_TX_IRQHandler          DMA1_Stream4_IRQHandler
+#define UART4_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART4_TX_DMA_INSTANCE            DMA1_Stream4
+#define UART4_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART4_TX_DMA_IRQ                 DMA1_Stream4_IRQn
+#endif
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream5_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream5
+#define UART2_RX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_RX_DMA_IRQ                 DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream6
+#define UART2_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART2_TX_DMA_IRQ                 DMA1_Stream6_IRQn
+#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
+#define UART8_DMA_RX_IRQHandler          DMA1_Stream6_IRQHandler
+#define UART8_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART8_RX_DMA_INSTANCE            DMA1_Stream6
+#define UART8_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART8_RX_DMA_IRQ                 DMA1_Stream6_IRQn
+#endif
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_DMA_TX_IRQHandler          DMA1_Stream7_IRQHandler
+#define UART5_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART5_TX_DMA_INSTANCE            DMA1_Stream7
+#define UART5_TX_DMA_CHANNEL             DMA_CHANNEL_4
+#define UART5_TX_DMA_IRQ                 DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream0
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
+#define UART6_DMA_RX_IRQHandler          DMA2_Stream1_IRQHandler
+#define UART6_RX_DMA_RCC                 RCC_AHB1ENR_DMA2EN
+#define UART6_RX_DMA_INSTANCE            DMA2_Stream1
+#define UART6_RX_DMA_CHANNEL             DMA_CHANNEL_5
+#define UART6_RX_DMA_IRQ                 DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream2_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream2
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream3
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#elif defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_5
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_DMA_RX_IRQHandler         DMA2_Stream5_IRQHandler
+#define UART1_RX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_RX_DMA_INSTANCE           DMA2_Stream5
+#define UART1_RX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_RX_DMA_IRQ                DMA2_Stream5_IRQn
+#elif defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream5
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
+#define UART6_DMA_TX_IRQHandler         DMA2_Stream6_IRQHandler
+#define UART6_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART6_TX_DMA_INSTANCE           DMA2_Stream6
+#define UART6_TX_DMA_CHANNEL            DMA_CHANNEL_5
+#define UART6_TX_DMA_IRQ                DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_DMA_TX_IRQHandler         DMA2_Stream7_IRQHandler
+#define UART1_TX_DMA_RCC                RCC_AHB1ENR_DMA2EN
+#define UART1_TX_DMA_INSTANCE           DMA2_Stream7
+#define UART1_TX_DMA_CHANNEL            DMA_CHANNEL_4
+#define UART1_TX_DMA_IRQ                DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/pulse_encoder_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-08-23     balanceTWK   first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PULSE_ENCODER1
+#ifndef PULSE_ENCODER1_CONFIG
+#define PULSE_ENCODER1_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM1,                \
+       .encoder_irqn            = TIM1_UP_TIM10_IRQn,  \
+       .name                    = "pulse1"             \
+    }
+#endif /* PULSE_ENCODER1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER1 */
+
+#ifdef BSP_USING_PULSE_ENCODER2
+#ifndef PULSE_ENCODER2_CONFIG
+#define PULSE_ENCODER2_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM2,                \
+       .encoder_irqn            = TIM2_IRQn,           \
+       .name                    = "pulse2"             \
+    }
+#endif /* PULSE_ENCODER2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER2 */
+
+#ifdef BSP_USING_PULSE_ENCODER3
+#ifndef PULSE_ENCODER3_CONFIG
+#define PULSE_ENCODER3_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM3,                \
+       .encoder_irqn            = TIM3_IRQn,           \
+       .name                    = "pulse3"             \
+    }
+#endif /* PULSE_ENCODER3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER3 */
+
+#ifdef BSP_USING_PULSE_ENCODER4
+#ifndef PULSE_ENCODER4_CONFIG
+#define PULSE_ENCODER4_CONFIG                          \
+    {                                                  \
+       .tim_handler.Instance    = TIM4,                \
+       .encoder_irqn            = TIM4_IRQn,           \
+       .name                    = "pulse4"             \
+    }
+#endif /* PULSE_ENCODER4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/pwm_config.h

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef BSP_USING_PWM12
+#ifndef PWM12_CONFIG
+#define PWM12_CONFIG                            \
+    {                                           \
+       .tim_handle.Instance     = TIM12,        \
+       .name                    = "pwm12",      \
+       .channel                 = 0             \
+    }
+#endif /* PWM12_CONFIG */
+#endif /* BSP_USING_PWM12 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32g4xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDIO,                                \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/g4/spi_config.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ * 2019-01-03     zylx         modify DMA support
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/g4/uart_config.h

@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-03     zylx         modify dma support
+ * 2019-10-03     xuzhuoyi     modify for STM32G4
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_LPUART1)
+#ifndef LPUART1_CONFIG
+#define LPUART1_CONFIG                                              \
+    {                                                               \
+        .name = "lpuart1",                                          \
+        .Instance = LPUART1,                                        \
+        .irq_type = LPUART1_IRQn,                                   \
+    }
+#endif /* LPUART1_CONFIG */
+#if defined(BSP_LPUART1_RX_USING_DMA)
+#ifndef LPUART1_DMA_CONFIG
+#define LPUART1_DMA_CONFIG                                          \
+    {                                                               \
+        .Instance = LPUART1_RX_DMA_INSTANCE,                        \
+        .request  = LPUART1_RX_DMA_REQUEST,                         \
+        .dma_rcc  = LPUART1_RX_DMA_RCC,                             \
+        .dma_irq  = LPUART1_RX_DMA_IRQ,                             \
+    }
+#endif /* LPUART1_DMA_CONFIG */
+#endif /* BSP_LPUART1_RX_USING_DMA */
+#endif /* BSP_USING_LPUART1 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+		
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_RX_DMA_INSTANCE,                         \
+        .channel = UART1_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_RX_DMA_RCC,                               \
+        .dma_irq = UART1_RX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART1_TX_DMA_INSTANCE,                         \
+        .channel = UART1_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART1_TX_DMA_RCC,                               \
+        .dma_irq = UART1_TX_DMA_IRQ,                               \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_RX_DMA_INSTANCE,                         \
+        .channel = UART2_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_RX_DMA_RCC,                               \
+        .dma_irq = UART2_RX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+		
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART2_TX_DMA_INSTANCE,                         \
+        .channel = UART2_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART2_TX_DMA_RCC,                               \
+        .dma_irq = UART2_TX_DMA_IRQ,                               \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_RX_DMA_INSTANCE,                         \
+        .channel = UART3_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_RX_DMA_RCC,                               \
+        .dma_irq = UART3_RX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+		
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART3_TX_DMA_INSTANCE,                         \
+        .channel = UART3_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART3_TX_DMA_RCC,                               \
+        .dma_irq = UART3_TX_DMA_IRQ,                               \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_RX_DMA_INSTANCE,                         \
+        .channel = UART4_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_RX_DMA_RCC,                               \
+        .dma_irq = UART4_RX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART4_TX_DMA_INSTANCE,                         \
+        .channel = UART4_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART4_TX_DMA_RCC,                               \
+        .dma_irq = UART4_TX_DMA_IRQ,                               \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_RX_DMA_INSTANCE,                         \
+        .channel = UART5_RX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_RX_DMA_RCC,                               \
+        .dma_irq = UART5_RX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+		
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                        \
+    {                                                              \
+        .Instance = UART5_TX_DMA_INSTANCE,                         \
+        .channel = UART5_TX_DMA_CHANNEL,                           \
+        .dma_rcc = UART5_TX_DMA_RCC,                               \
+        .dma_irq = UART5_TX_DMA_IRQ,                               \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/g4/usbd_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-10     ZYH          first version
+ * 2019-10-27     flybreak     Compatible with the HS
+ */
+#ifndef __USBD_CONFIG_H__
+#define __USBD_CONFIG_H__
+
+#include <rtconfig.h>
+
+#ifdef BSP_USBD_TYPE_HS
+#define USBD_IRQ_TYPE     OTG_HS_IRQn
+#define USBD_IRQ_HANDLER  OTG_HS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_HS
+#else
+#define USBD_IRQ_TYPE     OTG_FS_IRQn
+#define USBD_IRQ_HANDLER  OTG_FS_IRQHandler
+#define USBD_INSTANCE     USB_OTG_FS
+#endif
+
+#ifdef BSP_USBD_SPEED_HS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH
+#elif  BSP_USBD_SPEED_HSINFS
+#define USBD_PCD_SPEED    PCD_SPEED_HIGH_IN_FULL
+#else
+#define USBD_PCD_SPEED    PCD_SPEED_FULL
+#endif
+
+#ifdef BSP_USBD_PHY_ULPI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_ULPI
+#elif  BSP_USBD_PHY_UTMI
+#define USBD_PCD_PHY_MODULE    PCD_PHY_UTMI
+#else
+#define USBD_PCD_PHY_MODULE    PCD_PHY_EMBEDDED
+#endif
+
+#endif

project_0/libraries/HAL_Drivers/config/h7/adc_config.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-06     zylx         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_CONFIG
+#define ADC1_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC1,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC1_CONFIG */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_CONFIG
+#define ADC2_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC2,                          \
+        .Init.ClockPrescaler           = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC2_CONFIG */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_CONFIG
+#define ADC3_CONFIG                                                     \
+    {                                                                   \
+        .Instance                      = ADC3,                          \
+       .Init.ClockPrescaler            = ADC_CLOCK_SYNC_PCLK_DIV4,      \
+        .Init.Resolution               = ADC_RESOLUTION_16B,            \
+        .Init.ScanConvMode             = ADC_SCAN_DISABLE,              \
+        .Init.EOCSelection             = ADC_EOC_SINGLE_CONV,           \
+        .Init.LowPowerAutoWait         = DISABLE,                       \
+        .Init.ContinuousConvMode       = DISABLE,                       \
+        .Init.NbrOfConversion          = 1,                             \
+        .Init.DiscontinuousConvMode    = DISABLE,                       \
+        .Init.NbrOfDiscConversion      = 1,                             \
+        .Init.ExternalTrigConv         = ADC_SOFTWARE_START,            \
+        .Init.ExternalTrigConvEdge     = ADC_EXTERNALTRIGCONVEDGE_NONE, \
+        .Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR,         \
+        .Init.Overrun                  = ADC_OVR_DATA_OVERWRITTEN,      \
+        .Init.OversamplingMode         = DISABLE,                       \
+    }
+#endif /* ADC3_CONFIG */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/dac_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-06-16     thread-liu   first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_CONFIG
+#define DAC1_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC1,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_CONFIG
+#define DAC2_CONFIG                                                    \
+    {                                                                  \
+       .Instance                      = DAC2,                          \
+    }
+#endif /* DAC2_CONFIG */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/dma_config.h

@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-01-02     zylx         first version
+ * 2019-01-08     SummerGift   clean up the code
+ * 2020-05-02     whj4674672   support stm32h7 dma1 and dma2
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 stream0 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_DMA_RX_IRQHandler          DMA1_Stream0_IRQHandler
+#define UART2_RX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_RX_DMA_INSTANCE            DMA1_Stream0
+#define UART2_RX_DMA_REQUEST             DMA_REQUEST_USART2_RX
+#define UART2_RX_DMA_IRQ                 DMA1_Stream0_IRQn
+#endif
+
+/* DMA1 stream1 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_DMA_TX_IRQHandler          DMA1_Stream1_IRQHandler
+#define UART2_TX_DMA_RCC                 RCC_AHB1ENR_DMA1EN
+#define UART2_TX_DMA_INSTANCE            DMA1_Stream1
+#define UART2_TX_DMA_REQUEST             DMA_REQUEST_USART2_TX
+#define UART2_TX_DMA_IRQ                 DMA1_Stream1_IRQn
+#endif
+
+/* DMA1 stream2 */
+#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_DMA_RX_IRQHandler           DMA1_Stream2_IRQHandler
+#define SPI3_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_RX_DMA_INSTANCE             DMA1_Stream2
+#define SPI3_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_RX_DMA_IRQ                  DMA1_Stream2_IRQn
+#endif
+
+/* DMA1 stream3 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_DMA_RX_IRQHandler           DMA1_Stream3_IRQHandler
+#define SPI2_RX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_RX_DMA_INSTANCE             DMA1_Stream3
+#define SPI2_RX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_RX_DMA_IRQ                  DMA1_Stream3_IRQn
+#endif
+
+/* DMA1 stream4 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_DMA_TX_IRQHandler           DMA1_Stream4_IRQHandler
+#define SPI2_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI2_TX_DMA_INSTANCE             DMA1_Stream4
+#define SPI2_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI2_TX_DMA_IRQ                  DMA1_Stream4_IRQn
+#endif
+
+
+/* DMA1 stream5 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream5_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream5
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream5_IRQn
+#endif
+
+/* DMA1 stream6 */
+
+/* DMA1 stream7 */
+#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_DMA_TX_IRQHandler           DMA1_Stream7_IRQHandler
+#define SPI3_TX_DMA_RCC                  RCC_AHB1ENR_DMA1EN
+#define SPI3_TX_DMA_INSTANCE             DMA1_Stream7
+#define SPI3_TX_DMA_CHANNEL              DMA_CHANNEL_0
+#define SPI3_TX_DMA_IRQ                  DMA1_Stream7_IRQn
+#endif
+
+/* DMA2 stream0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream0_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream0
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream0_IRQn
+#endif
+
+/* DMA2 stream1 */
+#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
+#define SPI4_DMA_TX_IRQHandler           DMA2_Stream1_IRQHandler
+#define SPI4_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI4_TX_DMA_INSTANCE             DMA2_Stream1
+#define SPI4_TX_DMA_CHANNEL              DMA_CHANNEL_4
+#define SPI4_TX_DMA_IRQ                  DMA2_Stream1_IRQn
+#endif
+
+/* DMA2 stream2 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_DMA_RX_IRQHandler           DMA2_Stream2_IRQHandler
+#define SPI1_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_RX_DMA_INSTANCE             DMA2_Stream2
+#define SPI1_RX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_RX_DMA_IRQ                  DMA2_Stream2_IRQn
+#endif
+
+/* DMA2 stream3 */
+#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
+#define SPI5_DMA_RX_IRQHandler           DMA2_Stream3_IRQHandler
+#define SPI5_RX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_RX_DMA_INSTANCE             DMA2_Stream3
+#define SPI5_RX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_RX_DMA_IRQ                  DMA2_Stream3_IRQn
+#endif
+
+/* DMA2 stream4 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream4_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream4
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_2
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream4_IRQn
+#endif
+
+/* DMA2 stream5 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_DMA_TX_IRQHandler           DMA2_Stream5_IRQHandler
+#define SPI1_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI1_TX_DMA_INSTANCE             DMA2_Stream5
+#define SPI1_TX_DMA_CHANNEL              DMA_CHANNEL_3
+#define SPI1_TX_DMA_IRQ                  DMA2_Stream5_IRQn
+#endif
+
+/* DMA2 stream6 */
+#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
+#define SPI5_DMA_TX_IRQHandler           DMA2_Stream6_IRQHandler
+#define SPI5_TX_DMA_RCC                  RCC_AHB1ENR_DMA2EN
+#define SPI5_TX_DMA_INSTANCE             DMA2_Stream6
+#define SPI5_TX_DMA_CHANNEL              DMA_CHANNEL_7
+#define SPI5_TX_DMA_IRQ                  DMA2_Stream6_IRQn
+#endif
+
+/* DMA2 stream7 */
+#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_IRQHandler              DMA2_Stream7_IRQHandler
+#define QSPI_DMA_RCC                     RCC_AHB1ENR_DMA2EN
+#define QSPI_DMA_INSTANCE                DMA2_Stream7
+#define QSPI_DMA_CHANNEL                 DMA_CHANNEL_3
+#define QSPI_DMA_IRQ                     DMA2_Stream7_IRQn
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     zylx         first version
+ */
+
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM2
+#ifndef PWM2_CONFIG
+#define PWM2_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM2,         \
+       .name                    = "pwm2",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM2_CONFIG */
+#endif /* BSP_USING_PWM2 */
+
+#ifdef BSP_USING_PWM3
+#ifndef PWM3_CONFIG
+#define PWM3_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM3,         \
+       .name                    = "pwm3",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM3_CONFIG */
+#endif /* BSP_USING_PWM3 */
+
+#ifdef BSP_USING_PWM4
+#ifndef PWM4_CONFIG
+#define PWM4_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM4,         \
+       .name                    = "pwm4",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM4_CONFIG */
+#endif /* BSP_USING_PWM4 */
+
+#ifdef BSP_USING_PWM5
+#ifndef PWM5_CONFIG
+#define PWM5_CONFIG                             \
+    {                                           \
+       .tim_handle.Instance     = TIM5,         \
+       .name                    = "pwm5",       \
+       .channel                 = 0             \
+    }
+#endif /* PWM5_CONFIG */
+#endif /* BSP_USING_PWM5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/qspi_config.h

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-22     zylx         first version 
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                        \
+    {                                                          \
+        .Instance = QUADSPI,                                   \
+        .Init.FifoThreshold = 4,                               \
+        .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
+        .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE,  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+#endif /* BSP_USING_QSPI */
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                        \
+    {                                                          \
+        .Instance = QSPI_DMA_INSTANCE,                         \
+        .Init.Channel  = QSPI_DMA_CHANNEL,                     \
+        .Init.Direction = DMA_PERIPH_TO_MEMORY,                \
+        .Init.PeriphInc = DMA_PINC_DISABLE,                    \
+        .Init.MemInc = DMA_MINC_ENABLE,                        \
+        .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE,       \
+        .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE,          \
+        .Init.Mode = DMA_NORMAL,                               \
+        .Init.Priority = DMA_PRIORITY_LOW                      \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+
+#define QSPI_IRQn                   QUADSPI_IRQn
+#define QSPI_IRQHandler             QUADSPI_IRQHandler
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __QSPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/sdio_config.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-13     BalanceTWK   first version
+ */
+
+#ifndef __SDIO_CONFIG_H__
+#define __SDIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "stm32h7xx_hal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SDIO
+#define SDIO_BUS_CONFIG                                  \
+    {                                                    \
+        .Instance = SDMMC1,                              \
+        .dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN,            \
+        .dma_rx.Instance = DMA2_Stream3,                 \
+        .dma_rx.channel = DMA_CHANNEL_4,                 \
+        .dma_rx.dma_irq = DMA2_Stream3_IRQn,             \
+        .dma_tx.Instance = DMA2_Stream6,                 \
+        .dma_tx.channel = DMA_CHANNEL_4,                 \
+        .dma_tx.dma_irq = DMA2_Stream6_IRQn,             \
+    }
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SDIO_CONFIG_H__ */
+
+
+

project_0/libraries/HAL_Drivers/config/h7/spi_config.h

@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-06     SummerGift   first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .channel = SPI1_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .channel = SPI1_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_TX_DMA_RCC,                 \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .channel = SPI2_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI2_RX_DMA_RCC,                 \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .channel = SPI2_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI2_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_TX_DMA_RCC,                 \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .channel = SPI3_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI3_RX_DMA_RCC,                 \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .channel = SPI3_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI3_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI4,                           \
+        .bus_name = "spi4",                         \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+    
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_TX_DMA_RCC,                 \
+        .Instance = SPI4_TX_DMA_INSTANCE,           \
+        .channel = SPI4_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI4_RX_DMA_RCC,                 \
+        .Instance = SPI4_RX_DMA_INSTANCE,           \
+        .channel = SPI4_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI4_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI5,                           \
+        .bus_name = "spi5",                         \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+    
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_TX_DMA_RCC,                 \
+        .Instance = SPI5_TX_DMA_INSTANCE,           \
+        .channel = SPI5_TX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI5_RX_DMA_RCC,                 \
+        .Instance = SPI5_RX_DMA_INSTANCE,           \
+        .channel = SPI5_RX_DMA_CHANNEL,             \
+        .dma_irq = SPI5_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/tim_config.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-12-11     zylx         first version
+ */
+
+#ifndef __TIM_CONFIG_H__
+#define __TIM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef TIM_DEV_INFO_CONFIG
+#define TIM_DEV_INFO_CONFIG                     \
+    {                                           \
+        .maxfreq = 1000000,                     \
+        .minfreq = 3000,                        \
+        .maxcnt  = 0xFFFF,                      \
+        .cntmode = HWTIMER_CNTMODE_UP,          \
+    }
+#endif /* TIM_DEV_INFO_CONFIG */
+
+#ifdef BSP_USING_TIM11
+#ifndef TIM11_CONFIG
+#define TIM11_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM11,                    \
+       .tim_irqn                = TIM1_TRG_COM_TIM11_IRQn,  \
+       .name                    = "timer11",                \
+    }
+#endif /* TIM11_CONFIG */
+#endif /* BSP_USING_TIM11 */
+
+#ifdef BSP_USING_TIM13
+#ifndef TIM13_CONFIG
+#define TIM13_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM13,                    \
+       .tim_irqn                = TIM8_UP_TIM13_IRQn,       \
+       .name                    = "timer13",                \
+    }
+#endif /* TIM13_CONFIG */
+#endif /* BSP_USING_TIM13 */
+
+#ifdef BSP_USING_TIM14
+#ifndef TIM14_CONFIG
+#define TIM14_CONFIG                                        \
+    {                                                       \
+       .tim_handle.Instance     = TIM14,                    \
+       .tim_irqn                = TIM8_TRG_COM_TIM14_IRQn,  \
+       .name                    = "timer14",                \
+    }
+#endif /* TIM14_CONFIG */
+#endif /* BSP_USING_TIM14 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_CONFIG_H__ */

project_0/libraries/HAL_Drivers/config/h7/uart_config.h

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2019-01-05     zylx         modify dma support
+ * 2020-05-02     whj4674672   support stm32h7 uart dma
+ */
+ 
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG    
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = USART1,                                         \
+        .irq_type = USART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .request = UART1_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART1_RX_DMA_RCC,                                \
+        .dma_irq = UART1_RX_DMA_IRQ,                                \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = USART2,                                         \
+        .irq_type = USART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .request = UART2_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_RX_DMA_RCC,                                \
+        .dma_irq = UART2_RX_DMA_IRQ,                                \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .request = UART2_TX_DMA_REQUEST,                            \
+        .dma_rcc = UART2_TX_DMA_RCC,                                \
+        .dma_irq = UART2_TX_DMA_IRQ,                                \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+    
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = USART3,                                         \
+        .irq_type = USART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .request = UART3_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART3_RX_DMA_RCC,                                \
+        .dma_irq = UART3_RX_DMA_IRQ,                                \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .request = UART4_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART4_RX_DMA_RCC,                                \
+        .dma_irq = UART4_RX_DMA_IRQ,                                \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART5_RX_DMA_INSTANCE,                          \
+        .request = UART5_RX_DMA_REQUEST,                            \
+        .dma_rcc = UART5_RX_DMA_RCC,                                \
+        .dma_irq = UART5_RX_DMA_IRQ,                                \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif