add lrs007_lora_radio example

add lrs007_lorawan_end_device example

RealThread_STMH750-ART-Pi.yaml

@@ -232,6 +232,48 @@ example_projects:
     - libraries
     - rt-thread
   external_files:
+  - package_type: Chip_Support_Packages
+    package_vendor: RealThread
+    package_name: STM32H7
+    package_version: 0.1.9
+    source_path_offset: ''
+    target_path_offset: ''
+    files_and_folders: []
+- project_name: lrs007_lora_radio
+  project_description: creat this peoject if user choose rt-thread project
+  project_type: rt-thread|@full|@4.0.3
+  builtin_files:
+  - source_path_offset: projects/lrs007_lora_radio
+    target_path_offset: ''
+    files_and_folders:
+    - "*"
+  - source_path_offset: ''
+    target_path_offset: ''
+    files_and_folders:
+    - libraries
+    - rt-thread
+  external_files:
+  - package_type: Chip_Support_Packages
+    package_vendor: RealThread
+    package_name: STM32H7
+    package_version: 0.1.9
+    source_path_offset: ''
+    target_path_offset: ''
+    files_and_folders: []
+- project_name: lrs007_lorawan_end_device
+  project_description: creat this peoject if user choose rt-thread project
+  project_type: rt-thread|@full|@4.0.3
+  builtin_files:
+  - source_path_offset: projects/lrs007_lorawan_end_device
+    target_path_offset: ''
+    files_and_folders:
+    - "*"
+  - source_path_offset: ''
+    target_path_offset: ''
+    files_and_folders:
+    - libraries
+    - rt-thread
+  external_files:
   - package_type: Chip_Support_Packages
     package_vendor: RealThread
     package_name: STM32H7

projects/.gitignore

@@ -0,0 +1 @@
+/.metadata/

projects/README.md

@@ -9,4 +9,6 @@ ART-Pi 开源项目如下表所示：
 | [art_pi_factory](./art_pi_factory) | 实现 webnet. ART-Pi 的出厂DEMO |
 | [art_pi_wifi](./art_pi_wifi) | 实现 wifi 联网 |
 | [industry_io_gateway](./industry_io_gateway) | 实现 modbustcp2rtu 及 ftp |
-| [art_pi_net_player](./art_pi_net_player) | 实现 MP3 音乐播放，支持本地音乐和网易云音乐 |
+| [art_pi_net_player](./art_pi_net_player) | 实现 MP3 音乐播放，支持本地音乐和网易云音乐 |
+| [lrs007_lora_radio](./lrs007_lora_radio) | 实现 LoRa Radio (SX126x\SX127x...) 单向/双向通信、抓包及shell示例 |
+| [lrs007_lorawan_end_device](./lrs007_lorawan_end_device) | 实现 LoRaWAN End Device 协议栈Class A\C通信及shell示例 |

projects/lrs007_lora_radio/.config

@@ -0,0 +1,663 @@
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_SMALL_MEM is not set
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
+# end of Kernel Device Object
+
+CONFIG_RT_VER_NUM=0x40003
+# end of RT-Thread Kernel
+
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C++ features
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+# end of Command shell
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=6
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=6
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# end of Device virtual file system
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+# end of POSIX layer and C standard library
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+# end of Socket abstraction layer
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+# end of Network interface device
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+# end of light weight TCP/IP stack
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# end of AT commands
+# end of Network
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+# end of VBUS(Virtual Software BUS)
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_ULOG=y
+# CONFIG_ULOG_OUTPUT_LVL_A is not set
+# CONFIG_ULOG_OUTPUT_LVL_E is not set
+# CONFIG_ULOG_OUTPUT_LVL_W is not set
+# CONFIG_ULOG_OUTPUT_LVL_I is not set
+CONFIG_ULOG_OUTPUT_LVL_D=y
+CONFIG_ULOG_OUTPUT_LVL=7
+# CONFIG_ULOG_USING_ISR_LOG is not set
+CONFIG_ULOG_ASSERT_ENABLE=y
+CONFIG_ULOG_LINE_BUF_SIZE=384
+# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set
+
+#
+# log format
+#
+# CONFIG_ULOG_OUTPUT_FLOAT is not set
+CONFIG_ULOG_USING_COLOR=y
+CONFIG_ULOG_OUTPUT_TIME=y
+# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set
+CONFIG_ULOG_OUTPUT_LEVEL=y
+CONFIG_ULOG_OUTPUT_TAG=y
+# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set
+# end of log format
+
+CONFIG_ULOG_BACKEND_USING_CONSOLE=y
+# CONFIG_ULOG_USING_FILTER is not set
+# CONFIG_ULOG_USING_SYSLOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# end of Utilities
+
+# CONFIG_RT_USING_LWP is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_LORAGW_PKT_FWD is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# end of tools packages
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+CONFIG_PKG_USING_LORA_RADIO_DRIVER=y
+CONFIG_PKG_LORA_RADIO_DRIVER_PATH="/packages/peripherals/lora_radio_driver"
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP=y
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_SINGLE_INSTANCE=y
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_MULTI_INSTANCE is not set
+CONFIG_LORA_RADIO0_DEVICE_NAME="lora-radio0"
+CONFIG_LORA_RADIO0_SPI_BUS_NAME="spi4"
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X=y
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP_SX127X is not set
+
+#
+# Select Supported LoRa Module [SX126X]
+#
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R717N40=y
+
+#
+# LoRa Chip SX1268 (SPI module)
+#
+CONFIG_LORA_RADIO_USE_TCXO=y
+CONFIG_LORA_RADIO_GPIO_SETUP=y
+
+#
+# Select Supported Target Borad
+#
+# CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_LSD4RF_TEST2002 is not set
+CONFIG_LORA_RADIO_SPI_SETUP=y
+# CONFIG_LORA_RADIO_GPIO_SETUP_BY_PIN_NAME is not set
+CONFIG_LORA_RADIO_GPIO_SETUP_BY_PIN_NUMBER=y
+CONFIG_LORA_RADIO_NSS_PIN=68
+CONFIG_LORA_RADIO_RESET_PIN=114
+CONFIG_LORA_RADIO_DIO1_PIN=16
+CONFIG_LORA_RADIO_DIO2_PIN=115
+CONFIG_LORA_RADIO_RFSW1_PIN=17
+CONFIG_LORA_RADIO_RFSW2_PIN=18
+CONFIG_LORA_RADIO_BUSY_PIN=6
+# CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_ART_PI_AND_LRS007_RF_A is not set
+CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_ART_PI_AND_LRS007_RF_B=y
+# end of Select Supported Target Borad
+
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R822N30 is not set
+# end of Select Supported LoRa Module [SX126X]
+
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_DEBUG=y
+CONFIG_LR_DBG_APP_CONFIG=y
+CONFIG_LR_DBG_APP=1
+CONFIG_LR_DBG_INTERFACE_CONFIG=y
+CONFIG_LR_DBG_INTERFACE=1
+CONFIG_LR_DBG_CHIP_CONFIG=y
+CONFIG_LR_DBG_CHIP=1
+CONFIG_LR_DBG_SPI_CONFIG=y
+CONFIG_LR_DBG_SPI=1
+
+#
+# Select LoRa Radio Driver Example
+#
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_TEST_SHELL=y
+CONFIG_PHY_REGION_CN470=y
+# CONFIG_PHY_REGION_EU868 is not set
+# CONFIG_PHY_REGION_KR920 is not set
+CONFIG_USE_MODEM_LORA=y
+# CONFIG_USE_MODEM_FSK is not set
+# end of Select LoRa Radio Driver Example
+
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER_V100 is not set
+CONFIG_PKG_USING_LORA_RADIO_DRIVER_V130=y
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER_LATEST_VERSION is not set
+CONFIG_PKG_LORA_RADIO_DRIVER_VER="v1.3.0"
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_LORAGW_LIB_SX1302 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# end of peripheral libraries and drivers
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# end of miscellaneous packages
+# end of RT-Thread online packages
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32H750XB=y
+CONFIG_SOC_SERIES_STM32H7=y
+
+#
+# Board extended module
+#
+# CONFIG_ART_PI_USING_MEDIA_IO is not set
+# CONFIG_ART_PI_USING_INDUSTRY_IO is not set
+# CONFIG_ART_PI_USING_LORA_SHIELD_LRS007 is not set
+# end of Board extended module
+
+#
+# Onboard Peripheral
+#
+CONFIG_BSP_USING_USB_TO_USART=y
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_WIFI is not set
+# CONFIG_BSP_USING_OV2640 is not set
+# CONFIG_BSP_USING_FS is not set
+# end of Onboard Peripheral
+
+#
+# On-chip Peripheral
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+# CONFIG_BSP_USING_UART6 is not set
+CONFIG_BSP_USING_SPI=y
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_SPI2 is not set
+CONFIG_BSP_USING_SPI4=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_SDRAM is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_DCMI is not set
+# CONFIG_BSP_USING_FDCAN is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_USBH is not set
+# CONFIG_BSP_USING_TIM is not set
+# CONFIG_BSP_USING_ONCHIP_RTC is not set
+# end of On-chip Peripheral
+# end of Hardware Drivers Config
+
+#
+# External Libraries
+#
+# CONFIG_ART_PI_USING_WIFI_6212_LIB is not set
+# CONFIG_ART_PI_USING_OTA_LIB is not set
+# CONFIG_ART_PI_TouchGFX_LIB is not set
+# CONFIG_ART_PI_USING_FTP_LIB is not set
+# end of External Libraries
+
+CONFIG_RT_STUDIO_BUILT_IN=y

projects/lrs007_lora_radio/.gitattributes

@@ -0,0 +1,36 @@
+# Sources
+*.c     text diff=c
+*.cc    text diff=cpp
+*.cxx   text diff=cpp
+*.cpp   text diff=cpp
+*.c++   text diff=cpp
+*.hpp   text diff=cpp
+*.h     text diff=c
+*.h++   text diff=cpp
+*.hh    text diff=cpp
+
+# Compiled Object files
+*.slo   binary
+*.lo    binary
+*.o     binary
+*.obj   binary
+
+# Precompiled Headers
+*.gch   binary
+*.pch   binary
+
+# Compiled Dynamic libraries
+*.so    binary
+*.dylib binary
+*.dll   binary
+
+# Compiled Static libraries
+*.lai   binary
+*.la    binary
+*.a     binary
+*.lib   binary
+
+# Executables
+*.exe   binary
+*.out   binary
+*.app   binary

projects/lrs007_lora_radio/.gitignore

@@ -0,0 +1,37 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.pdb
+*.idb
+*.ilk
+!*.old
+build
+Debug
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*

projects/lrs007_lora_radio/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>lrs007_lora_radio</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

projects/lrs007_lora_radio/.settings/lrs007_lora_radio.STLink.Debug.rttlaunch

@@ -0,0 +1,60 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.rtthread.studio.debug.gdbjtag.stlink.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${rtt_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32H7\0.1.9\debug\svd\STM32H750x.svd"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.connectMode" value="NORMAL"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.debugInterface" value="SWD"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.erase" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.externalLoader" value="${workspace_loc:/${ProjName}/board/stldr/ART-Pi_W25Q64.stldr}"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.externalLoaderButton" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.flashVerify" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.isUseInternal" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherDownloadOption" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherGdbserverOption" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61235"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetMode" value=" -hardRst"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetRun" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${external_gdb_tool}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="lrs007_lora_radio"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/lrs007_lora_radio"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.adapterName" value="ST-LINK"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerDeviceName" value="STM32H750XB"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerExecutable" value="${rtt_install_path}/repo/Extract/Debugger_Support_Packages/STMicroelectronics/ST-LINK_Debugger/1.2.0/ST-LINK_gdbserver.exe"/>
+<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.useRemoteTarget" value="true"/>
+<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.doContinue" value="true"/>
+</launchConfiguration>

projects/lrs007_lora_radio/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

projects/lrs007_lora_radio/.settings/projcfg.ini

@@ -0,0 +1,19 @@
+#RT-Thread Studio Project Configuration
+#Sat Dec 12 11:41:28 CST 2020
+cfg_version=v3.0
+board_name=STM32H750-RT-ART-Pi
+example_name=art_pi_blink_led
+hardware_adapter=ST-LINK
+project_type=rt-thread
+board_base_nano_proj=False
+chip_name=STM32H750XBHx
+selected_rtt_version=4.0.3
+bsp_version=1.1.0
+os_branch=full
+output_project_path=F\:/K-Forest/RTOS/RT-Thread/artpi-master/sdk-artpi-pr/sdk-bsp-stm32h750-realthread-artpi/projects
+is_base_example_project=True
+is_use_scons_build=True
+project_base_bsp=true
+project_name=lrs007_lora_radio
+os_version=4.0.3
+bsp_path=repo/Extract/Board_Support_Packages/RealThread/STM32H750-RT-ART-Pi/1.1.0

projects/lrs007_lora_radio/Kconfig

@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$RTT_DIR/../libraries/Kconfig"
+
+config RT_STUDIO_BUILT_IN
+    bool
+    select ARCH_ARM_CORTEX_M7
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y

projects/lrs007_lora_radio/README.md

@@ -0,0 +1,45 @@
+# LoRa-Radio Shell例程
+
+## 简介
+
+LoRa-Radio Shell示例程序主要功能是通过串口shell命令来控制LoRa Radio实现点对点单\双通信、空口抓包等功能。
+
+该例程基于ART-Pi与LoRa多功能扩展板(LRS007)实现，使用了470M LoRa模块(LSD4RF-2R717N40[SX1268])。
+
+[LSD4RF-2R717N40[SX1268]](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)主要技术参数：
+
+- LoRa芯片：SX1268
+- 频段范围：470~510M
+- 发射性能：~105mA@ 22dBm(max)
+- 接收性能:  ~6mA, -124dBm@SF7&BW125
+- 晶振类型：TXCO
+- 通信接口：SPI
+
+## 硬件说明
+<img src="./figures/LoRa-Shield_LRS007_RF_A_SCH_SX126x.png" alt="LED 连接单片机引脚" style="zoom: 50%;" />
+如上图所示，LRS007扩展板的M6位号当前默认贴装470M LoRa模块(LSD4RF-2R717N40[SX1268])，其采用硬件SPI接口(SPI4)与ART-Pi主板连接。
+
+## 软件说明
+
+基于ART-Pi的lora-radio-driver软件包使用参考如下
+
+![lora-radio-driver软件包使用说明](./figures/lora-radio-driver-manual-for-art-pi.gif)
+
+lora-radio的测试代码采用的是 `/lrs007_lora_radio/art_pi_blink_led/packages/lora_radio_driver-v1.3.0/samples/lora-radio-test-shell ` 。
+具体使用方式可参考[《lora-radio-driver软件包使用说明》](https://github.com/Forest-Rain/lora-radio-driver/tree/master/doc)
+
+
+## 运行
+### 编译&下载
+
+编译完成后，将开发板的 ST-Link USB 口与 PC 机连接，然后将固件下载至开发板。
+
+### 运行效果
+
+![lora-radio双向通信测试](./figures/lora-radio-test-llcc68-sx1268.gif)。
+
+## 注意事项
+
+1. 该示例默认使用了内核的rt_timer来提供定时服务，可根据实际需要，使能multi-rtimer软件包来提供定时\超时服务（STM32平台）。
+2. 如果使能ulog进行日志输出，需要开启“Enable ISR log”，为了保证日志输出完整，日志最大长度建议设置≥384
+

projects/lrs007_lora_radio/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

projects/lrs007_lora_radio/SConstruct

@@ -0,0 +1,58 @@
+import os
+import sys
+import rtconfig
+
+if os.path.exists('rt-thread'):
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/rt-thread')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '../../../rt-thread')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except Exception as e:
+    print("Error message:", e.message)
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    sys.exit(-1)
+
+TARGET = 'rt-thread.elf'
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+env.AppendUnique(CPPDEFINES = [])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+if os.path.exists('libraries'):
+    libraries_path_prefix = 'libraries'
+else:
+    libraries_path_prefix = '../../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+stm32_library = 'STM32H7xx_HAL'
+rtconfig.BSP_LIBRARY_TYPE = stm32_library
+
+if not os.path.exists('libraries'):
+    # include libraries
+    objs.extend(SConscript(os.path.join(libraries_path_prefix, 'SConscript')))
+
+    # include applications
+    #objs.extend(SConscript(os.path.join(APP_ROOT, 'applications', 'SConscript')))
+
+#objs += PrepareBuilding(env, LIB_ROOT, has_libcpu=False)
+# make a building
+DoBuilding(TARGET, objs)

projects/lrs007_lora_radio/applications/SConscript

@@ -0,0 +1,10 @@
+import rtconfig
+from building import *
+
+cwd  = GetCurrentDir()
+path = [cwd]
+src  = Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = path)
+
+Return('group')

projects/lrs007_lora_radio/applications/main.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-09-02     RT-Thread    first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_common.h"
+
+#define LED_PIN GET_PIN(I, 8)
+
+int main(void)
+{
+    rt_uint32_t count = 1;
+
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while(count++)
+    {
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+    }
+    return RT_EOK;
+}
+
+#include "stm32h7xx.h"
+static int vtor_config(void)
+{
+    /* Vector Table Relocation in Internal QSPI_FLASH */
+    SCB->VTOR = QSPI_BASE;
+    return 0;
+}
+INIT_BOARD_EXPORT(vtor_config);
+
+

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Inc/main.h

@@ -0,0 +1,71 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Inc/stm32h7xx_hal_conf.h

@@ -0,0 +1,511 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_conf.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_CONF_H
+#define STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  #define HAL_ADC_MODULE_ENABLED
+/* #define HAL_FDCAN_MODULE_ENABLED   */
+/* #define HAL_FMAC_MODULE_ENABLED   */
+/* #define HAL_CEC_MODULE_ENABLED   */
+/* #define HAL_COMP_MODULE_ENABLED   */
+/* #define HAL_CORDIC_MODULE_ENABLED   */
+/* #define HAL_CRC_MODULE_ENABLED   */
+/* #define HAL_CRYP_MODULE_ENABLED   */
+/* #define HAL_DAC_MODULE_ENABLED   */
+/* #define HAL_DCMI_MODULE_ENABLED   */
+/* #define HAL_DMA2D_MODULE_ENABLED   */
+#define HAL_ETH_MODULE_ENABLED
+/* #define HAL_NAND_MODULE_ENABLED   */
+/* #define HAL_NOR_MODULE_ENABLED   */
+/* #define HAL_OTFDEC_MODULE_ENABLED   */
+/* #define HAL_SRAM_MODULE_ENABLED   */
+#define HAL_SDRAM_MODULE_ENABLED
+/* #define HAL_HASH_MODULE_ENABLED   */
+/* #define HAL_HRTIM_MODULE_ENABLED   */
+/* #define HAL_HSEM_MODULE_ENABLED   */
+/* #define HAL_GFXMMU_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_OPAMP_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_OSPI_MODULE_ENABLED   */
+/* #define HAL_I2S_MODULE_ENABLED   */
+/* #define HAL_SMBUS_MODULE_ENABLED   */
+/* #define HAL_IWDG_MODULE_ENABLED   */
+/* #define HAL_LPTIM_MODULE_ENABLED   */
+#define HAL_LTDC_MODULE_ENABLED
+/* #define HAL_QSPI_MODULE_ENABLED   */
+/* #define HAL_RNG_MODULE_ENABLED   */
+/* #define HAL_RTC_MODULE_ENABLED   */
+/* #define HAL_SAI_MODULE_ENABLED   */
+#define HAL_SD_MODULE_ENABLED
+/* #define HAL_MMC_MODULE_ENABLED   */
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
+#define HAL_SPI_MODULE_ENABLED
+/* #define HAL_SWPMI_MODULE_ENABLED   */
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED   */
+/* #define HAL_IRDA_MODULE_ENABLED   */
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
+/* #define HAL_WWDG_MODULE_ENABLED   */
+#define HAL_PCD_MODULE_ENABLED
+/* #define HAL_HCD_MODULE_ENABLED   */
+/* #define HAL_DFSDM_MODULE_ENABLED   */
+/* #define HAL_DSI_MODULE_ENABLED   */
+/* #define HAL_JPEG_MODULE_ENABLED   */
+/* #define HAL_MDIOS_MODULE_ENABLED   */
+/* #define HAL_PSSI_MODULE_ENABLED   */
+/* #define HAL_DTS_MODULE_ENABLED   */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)100U)   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal  oscillator (CSI) default value.
+  *        This value is the default CSI value after Reset.
+  */
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  *        This value is used by the UART, RTC HAL module to compute the system frequency
+  */
+#if !defined  (LSE_VALUE)
+  #define LSE_VALUE    ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+#if !defined  (LSI_VALUE)
+  #define LSI_VALUE  (32000UL)              /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                              The real value may vary depending on the variations
+                                              in voltage and temperature.*/
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE                    ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            ((uint32_t)0U) /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  USE_SD_TRANSCEIVER           0U               /*!< use uSD Transceiver */
+#define  USE_SPI_CRC	              0U               /*!< use CRC in SPI */
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */
+#define  USE_HAL_CORDIC_REGISTER_CALLBACKS  0U /* CORDIC register callback disabled  */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
+#define  USE_HAL_FMAC_REGISTER_CALLBACKS    0U /* FMAC register callback disabled  */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0    ((uint8_t)0x02)
+#define ETH_MAC_ADDR1    ((uint8_t)0x00)
+#define ETH_MAC_ADDR2    ((uint8_t)0x00)
+#define ETH_MAC_ADDR3    ((uint8_t)0x00)
+#define ETH_MAC_ADDR4    ((uint8_t)0x00)
+#define ETH_MAC_ADDR5    ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+  #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+  #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+  #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+  #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CORDIC_MODULE_ENABLED
+   #include "stm32h7xx_hal_cordic.h"
+#endif /* HAL_CORDIC_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_FMAC_MODULE_ENABLED
+  #include "stm32h7xx_hal_fmac.h"
+#endif /* HAL_FMAC_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+  #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+  #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+  #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+  #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Inc/stm32h7xx_it.h

@@ -0,0 +1,73 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_IT_H
+#define __STM32H7xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void SDMMC1_IRQHandler(void);
+void ETH_IRQHandler(void);
+void OTG_FS_IRQHandler(void);
+void SDMMC2_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_IT_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Src/main.c

@@ -0,0 +1,781 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "string.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+#if defined ( __ICCARM__ ) /*!< IAR Compiler */
+
+#pragma location=0x30040000
+ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+#pragma location=0x30040060
+ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+#pragma location=0x30040200
+uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffers */
+
+#elif defined ( __CC_ARM )  /* MDK ARM Compiler */
+
+__attribute__((at(0x30040000))) ETH_DMADescTypeDef  DMARxDscrTab[ETH_RX_DESC_CNT]; /* Ethernet Rx DMA Descriptors */
+__attribute__((at(0x30040060))) ETH_DMADescTypeDef  DMATxDscrTab[ETH_TX_DESC_CNT]; /* Ethernet Tx DMA Descriptors */
+__attribute__((at(0x30040200))) uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE]; /* Ethernet Receive Buffer */
+
+#elif defined ( __GNUC__ ) /* GNU Compiler */
+
+ETH_DMADescTypeDef DMARxDscrTab[ETH_RX_DESC_CNT] __attribute__((section(".RxDecripSection"))); /* Ethernet Rx DMA Descriptors */
+ETH_DMADescTypeDef DMATxDscrTab[ETH_TX_DESC_CNT] __attribute__((section(".TxDecripSection")));   /* Ethernet Tx DMA Descriptors */
+uint8_t Rx_Buff[ETH_RX_DESC_CNT][ETH_MAX_PACKET_SIZE] __attribute__((section(".RxArraySection"))); /* Ethernet Receive Buffers */
+
+#endif
+
+ETH_TxPacketConfig TxConfig;
+
+ETH_HandleTypeDef heth;
+
+LTDC_HandleTypeDef hltdc;
+
+SD_HandleTypeDef hsd1;
+SD_HandleTypeDef hsd2;
+
+SPI_HandleTypeDef hspi1;
+SPI_HandleTypeDef hspi4;
+
+UART_HandleTypeDef huart4;
+UART_HandleTypeDef huart3;
+
+PCD_HandleTypeDef hpcd_USB_OTG_FS;
+
+SDRAM_HandleTypeDef hsdram1;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_ETH_Init(void);
+static void MX_FMC_Init(void);
+static void MX_LTDC_Init(void);
+static void MX_SDMMC1_SD_Init(void);
+static void MX_SDMMC2_SD_Init(void);
+static void MX_SPI4_Init(void);
+static void MX_UART4_Init(void);
+static void MX_SPI1_Init(void);
+static void MX_USART3_UART_Init(void);
+static void MX_USB_OTG_FS_PCD_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_ETH_Init();
+  MX_FMC_Init();
+  MX_LTDC_Init();
+  MX_SDMMC1_SD_Init();
+  MX_SDMMC2_SD_Init();
+  MX_SPI4_Init();
+  MX_UART4_Init();
+  MX_SPI1_Init();
+  MX_USART3_UART_Init();
+  MX_USB_OTG_FS_PCD_Init();
+  /* USER CODE BEGIN 2 */
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+  /** Macro to configure the PLL clock source
+  */
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 192;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART3
+                              |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_SPI4
+                              |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_SDMMC
+                              |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_FMC;
+  PeriphClkInitStruct.PLL2.PLL2M = 2;
+  PeriphClkInitStruct.PLL2.PLL2N = 64;
+  PeriphClkInitStruct.PLL2.PLL2P = 4;
+  PeriphClkInitStruct.PLL2.PLL2Q = 2;
+  PeriphClkInitStruct.PLL2.PLL2R = 4;
+  PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+  PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
+  PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3M = 5;
+  PeriphClkInitStruct.PLL3.PLL3N = 160;
+  PeriphClkInitStruct.PLL3.PLL3P = 8;
+  PeriphClkInitStruct.PLL3.PLL3Q = 8;
+  PeriphClkInitStruct.PLL3.PLL3R = 24;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
+  PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
+  PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2;
+  PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL3;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Enable USB Voltage detector
+  */
+  HAL_PWREx_EnableUSBVoltageDetector();
+}
+
+/**
+  * @brief ETH Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ETH_Init(void)
+{
+
+  /* USER CODE BEGIN ETH_Init 0 */
+
+  /* USER CODE END ETH_Init 0 */
+
+  /* USER CODE BEGIN ETH_Init 1 */
+
+  /* USER CODE END ETH_Init 1 */
+  heth.Instance = ETH;
+  heth.Init.MACAddr[0] =   0x00;
+  heth.Init.MACAddr[1] =   0x80;
+  heth.Init.MACAddr[2] =   0xE1;
+  heth.Init.MACAddr[3] =   0x00;
+  heth.Init.MACAddr[4] =   0x00;
+  heth.Init.MACAddr[5] =   0x00;
+  heth.Init.MediaInterface = HAL_ETH_RMII_MODE;
+  heth.Init.TxDesc = DMATxDscrTab;
+  heth.Init.RxDesc = DMARxDscrTab;
+  heth.Init.RxBuffLen = 1524;
+
+  /* USER CODE BEGIN MACADDRESS */
+
+  /* USER CODE END MACADDRESS */
+
+  if (HAL_ETH_Init(&heth) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  memset(&TxConfig, 0 , sizeof(ETH_TxPacketConfig));
+  TxConfig.Attributes = ETH_TX_PACKETS_FEATURES_CSUM | ETH_TX_PACKETS_FEATURES_CRCPAD;
+  TxConfig.ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC;
+  TxConfig.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+  /* USER CODE BEGIN ETH_Init 2 */
+
+  /* USER CODE END ETH_Init 2 */
+
+}
+
+/**
+  * @brief LTDC Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_LTDC_Init(void)
+{
+
+  /* USER CODE BEGIN LTDC_Init 0 */
+
+  /* USER CODE END LTDC_Init 0 */
+
+  LTDC_LayerCfgTypeDef pLayerCfg = {0};
+  LTDC_LayerCfgTypeDef pLayerCfg1 = {0};
+
+  /* USER CODE BEGIN LTDC_Init 1 */
+
+  /* USER CODE END LTDC_Init 1 */
+  hltdc.Instance = LTDC;
+  hltdc.Init.HSPolarity = LTDC_HSPOLARITY_AL;
+  hltdc.Init.VSPolarity = LTDC_VSPOLARITY_AL;
+  hltdc.Init.DEPolarity = LTDC_DEPOLARITY_AL;
+  hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC;
+  hltdc.Init.HorizontalSync = 7;
+  hltdc.Init.VerticalSync = 3;
+  hltdc.Init.AccumulatedHBP = 14;
+  hltdc.Init.AccumulatedVBP = 5;
+  hltdc.Init.AccumulatedActiveW = 654;
+  hltdc.Init.AccumulatedActiveH = 485;
+  hltdc.Init.TotalWidth = 660;
+  hltdc.Init.TotalHeigh = 487;
+  hltdc.Init.Backcolor.Blue = 0;
+  hltdc.Init.Backcolor.Green = 0;
+  hltdc.Init.Backcolor.Red = 0;
+  if (HAL_LTDC_Init(&hltdc) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pLayerCfg.WindowX0 = 0;
+  pLayerCfg.WindowX1 = 0;
+  pLayerCfg.WindowY0 = 0;
+  pLayerCfg.WindowY1 = 0;
+  pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
+  pLayerCfg.Alpha = 0;
+  pLayerCfg.Alpha0 = 0;
+  pLayerCfg.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
+  pLayerCfg.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
+  pLayerCfg.FBStartAdress = 0;
+  pLayerCfg.ImageWidth = 0;
+  pLayerCfg.ImageHeight = 0;
+  pLayerCfg.Backcolor.Blue = 0;
+  pLayerCfg.Backcolor.Green = 0;
+  pLayerCfg.Backcolor.Red = 0;
+  if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg, 0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pLayerCfg1.WindowX0 = 0;
+  pLayerCfg1.WindowX1 = 0;
+  pLayerCfg1.WindowY0 = 0;
+  pLayerCfg1.WindowY1 = 0;
+  pLayerCfg1.PixelFormat = LTDC_PIXEL_FORMAT_ARGB8888;
+  pLayerCfg1.Alpha = 0;
+  pLayerCfg1.Alpha0 = 0;
+  pLayerCfg1.BlendingFactor1 = LTDC_BLENDING_FACTOR1_CA;
+  pLayerCfg1.BlendingFactor2 = LTDC_BLENDING_FACTOR2_CA;
+  pLayerCfg1.FBStartAdress = 0;
+  pLayerCfg1.ImageWidth = 0;
+  pLayerCfg1.ImageHeight = 0;
+  pLayerCfg1.Backcolor.Blue = 0;
+  pLayerCfg1.Backcolor.Green = 0;
+  pLayerCfg1.Backcolor.Red = 0;
+  if (HAL_LTDC_ConfigLayer(&hltdc, &pLayerCfg1, 1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN LTDC_Init 2 */
+
+  /* USER CODE END LTDC_Init 2 */
+
+}
+
+/**
+  * @brief SDMMC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC1_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDMMC1_Init 0 */
+
+  /* USER CODE END SDMMC1_Init 0 */
+
+  /* USER CODE BEGIN SDMMC1_Init 1 */
+
+  /* USER CODE END SDMMC1_Init 1 */
+  hsd1.Instance = SDMMC1;
+  hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd1.Init.BusWide = SDMMC_BUS_WIDE_4B;
+  hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd1.Init.ClockDiv = 0;
+  hsd1.Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+  if (HAL_SD_Init(&hsd1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SDMMC1_Init 2 */
+
+  /* USER CODE END SDMMC1_Init 2 */
+
+}
+
+/**
+  * @brief SDMMC2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SDMMC2_SD_Init(void)
+{
+
+  /* USER CODE BEGIN SDMMC2_Init 0 */
+
+  /* USER CODE END SDMMC2_Init 0 */
+
+  /* USER CODE BEGIN SDMMC2_Init 1 */
+
+  /* USER CODE END SDMMC2_Init 1 */
+  hsd2.Instance = SDMMC2;
+  hsd2.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
+  hsd2.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
+  hsd2.Init.BusWide = SDMMC_BUS_WIDE_4B;
+  hsd2.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
+  hsd2.Init.ClockDiv = 0;
+  hsd2.Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT;
+  if (HAL_SD_Init(&hsd2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SDMMC2_Init 2 */
+
+  /* USER CODE END SDMMC2_Init 2 */
+
+}
+
+/**
+  * @brief SPI1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI1_Init(void)
+{
+
+  /* USER CODE BEGIN SPI1_Init 0 */
+
+  /* USER CODE END SPI1_Init 0 */
+
+  /* USER CODE BEGIN SPI1_Init 1 */
+
+  /* USER CODE END SPI1_Init 1 */
+  /* SPI1 parameter configuration*/
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 0x0;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+  hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
+  hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+  hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
+  hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
+  hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
+  hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI1_Init 2 */
+
+  /* USER CODE END SPI1_Init 2 */
+
+}
+
+/**
+  * @brief SPI4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_SPI4_Init(void)
+{
+
+  /* USER CODE BEGIN SPI4_Init 0 */
+
+  /* USER CODE END SPI4_Init 0 */
+
+  /* USER CODE BEGIN SPI4_Init 1 */
+
+  /* USER CODE END SPI4_Init 1 */
+  /* SPI4 parameter configuration*/
+  hspi4.Instance = SPI4;
+  hspi4.Init.Mode = SPI_MODE_MASTER;
+  hspi4.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi4.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi4.Init.CLKPolarity = SPI_POLARITY_LOW;
+  hspi4.Init.CLKPhase = SPI_PHASE_1EDGE;
+  hspi4.Init.NSS = SPI_NSS_SOFT;
+  hspi4.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+  hspi4.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi4.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi4.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi4.Init.CRCPolynomial = 0x0;
+  hspi4.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  hspi4.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+  hspi4.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
+  hspi4.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi4.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi4.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+  hspi4.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
+  hspi4.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
+  hspi4.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
+  hspi4.Init.IOSwap = SPI_IO_SWAP_DISABLE;
+  if (HAL_SPI_Init(&hspi4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN SPI4_Init 2 */
+
+  /* USER CODE END SPI4_Init 2 */
+
+}
+
+/**
+  * @brief UART4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART4_Init(void)
+{
+
+  /* USER CODE BEGIN UART4_Init 0 */
+
+  /* USER CODE END UART4_Init 0 */
+
+  /* USER CODE BEGIN UART4_Init 1 */
+
+  /* USER CODE END UART4_Init 1 */
+  huart4.Instance = UART4;
+  huart4.Init.BaudRate = 115200;
+  huart4.Init.WordLength = UART_WORDLENGTH_8B;
+  huart4.Init.StopBits = UART_STOPBITS_1;
+  huart4.Init.Parity = UART_PARITY_NONE;
+  huart4.Init.Mode = UART_MODE_TX_RX;
+  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART4_Init 2 */
+
+  /* USER CODE END UART4_Init 2 */
+
+}
+
+/**
+  * @brief USART3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART3_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART3_Init 0 */
+
+  /* USER CODE END USART3_Init 0 */
+
+  /* USER CODE BEGIN USART3_Init 1 */
+
+  /* USER CODE END USART3_Init 1 */
+  huart3.Instance = USART3;
+  huart3.Init.BaudRate = 115200;
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;
+  huart3.Init.StopBits = UART_STOPBITS_1;
+  huart3.Init.Parity = UART_PARITY_NONE;
+  huart3.Init.Mode = UART_MODE_TX_RX;
+  huart3.Init.HwFlowCtl = UART_HWCONTROL_RTS_CTS;
+  huart3.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart3, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart3, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART3_Init 2 */
+
+  /* USER CODE END USART3_Init 2 */
+
+}
+
+/**
+  * @brief USB_OTG_FS Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USB_OTG_FS_PCD_Init(void)
+{
+
+  /* USER CODE BEGIN USB_OTG_FS_Init 0 */
+
+  /* USER CODE END USB_OTG_FS_Init 0 */
+
+  /* USER CODE BEGIN USB_OTG_FS_Init 1 */
+
+  /* USER CODE END USB_OTG_FS_Init 1 */
+  hpcd_USB_OTG_FS.Instance = USB_OTG_FS;
+  hpcd_USB_OTG_FS.Init.dev_endpoints = 9;
+  hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;
+  hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;
+  hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;
+  hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;
+  if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USB_OTG_FS_Init 2 */
+
+  /* USER CODE END USB_OTG_FS_Init 2 */
+
+}
+
+/* FMC initialization function */
+static void MX_FMC_Init(void)
+{
+
+  /* USER CODE BEGIN FMC_Init 0 */
+
+  /* USER CODE END FMC_Init 0 */
+
+  FMC_SDRAM_TimingTypeDef SdramTiming = {0};
+
+  /* USER CODE BEGIN FMC_Init 1 */
+
+  /* USER CODE END FMC_Init 1 */
+
+  /** Perform the SDRAM1 memory initialization sequence
+  */
+  hsdram1.Instance = FMC_SDRAM_DEVICE;
+  /* hsdram1.Init */
+  hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
+  hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
+  hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
+  hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_16;
+  hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
+  hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_1;
+  hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
+  hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE;
+  hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
+  hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
+  /* SdramTiming */
+  SdramTiming.LoadToActiveDelay = 16;
+  SdramTiming.ExitSelfRefreshDelay = 16;
+  SdramTiming.SelfRefreshTime = 16;
+  SdramTiming.RowCycleDelay = 16;
+  SdramTiming.WriteRecoveryTime = 16;
+  SdramTiming.RPDelay = 16;
+  SdramTiming.RCDDelay = 16;
+
+  if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  /* USER CODE BEGIN FMC_Init 2 */
+
+  /* USER CODE END FMC_Init 2 */
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOK_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOJ_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOI_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+
+}
+
+/* USER CODE BEGIN 4 */
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c

@@ -0,0 +1,1162 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * File Name          : stm32h7xx_hal_msp.c
+  * Description        : This file provides code for the MSP Initialization
+  *                      and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief ADC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspInit 0 */
+
+  /* USER CODE END ADC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC12_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PB1     ------> ADC1_INP5
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN ADC1_MspInit 1 */
+
+  /* USER CODE END ADC1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ADC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hadc: ADC handle pointer
+* @retval None
+*/
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+  /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+  /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC12_CLK_DISABLE();
+
+    /**ADC1 GPIO Configuration
+    PB1     ------> ADC1_INP5
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1);
+
+  /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+  /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief ETH MSP Initialization
+* This function configures the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspInit(ETH_HandleTypeDef* heth)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspInit 0 */
+
+  /* USER CODE END ETH_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_ETH1MAC_CLK_ENABLE();
+    __HAL_RCC_ETH1TX_CLK_ENABLE();
+    __HAL_RCC_ETH1RX_CLK_ENABLE();
+
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**ETH GPIO Configuration
+    PG11     ------> ETH_TX_EN
+    PG14     ------> ETH_TXD1
+    PG13     ------> ETH_TXD0
+    PC1     ------> ETH_MDC
+    PA2     ------> ETH_MDIO
+    PA1     ------> ETH_REF_CLK
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* ETH interrupt Init */
+    HAL_NVIC_SetPriority(ETH_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(ETH_IRQn);
+  /* USER CODE BEGIN ETH_MspInit 1 */
+
+  /* USER CODE END ETH_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief ETH MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param heth: ETH handle pointer
+* @retval None
+*/
+void HAL_ETH_MspDeInit(ETH_HandleTypeDef* heth)
+{
+  if(heth->Instance==ETH)
+  {
+  /* USER CODE BEGIN ETH_MspDeInit 0 */
+
+  /* USER CODE END ETH_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ETH1MAC_CLK_DISABLE();
+    __HAL_RCC_ETH1TX_CLK_DISABLE();
+    __HAL_RCC_ETH1RX_CLK_DISABLE();
+
+    /**ETH GPIO Configuration
+    PG11     ------> ETH_TX_EN
+    PG14     ------> ETH_TXD1
+    PG13     ------> ETH_TXD0
+    PC1     ------> ETH_MDC
+    PA2     ------> ETH_MDIO
+    PA1     ------> ETH_REF_CLK
+    PA7     ------> ETH_CRS_DV
+    PC4     ------> ETH_RXD0
+    PC5     ------> ETH_RXD1
+    */
+    HAL_GPIO_DeInit(GPIOG, GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_13);
+
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_7);
+
+    /* ETH interrupt DeInit */
+    HAL_NVIC_DisableIRQ(ETH_IRQn);
+  /* USER CODE BEGIN ETH_MspDeInit 1 */
+
+  /* USER CODE END ETH_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief LTDC MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hltdc: LTDC handle pointer
+* @retval None
+*/
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hltdc->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspInit 0 */
+
+  /* USER CODE END LTDC_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_LTDC_CLK_ENABLE();
+
+    __HAL_RCC_GPIOK_CLK_ENABLE();
+    __HAL_RCC_GPIOJ_CLK_ENABLE();
+    __HAL_RCC_GPIOI_CLK_ENABLE();
+    /**LTDC GPIO Configuration
+    PK5     ------> LTDC_B6
+    PK4     ------> LTDC_B5
+    PJ15     ------> LTDC_B3
+    PK6     ------> LTDC_B7
+    PK3     ------> LTDC_B4
+    PK7     ------> LTDC_DE
+    PJ14     ------> LTDC_B2
+    PJ12     ------> LTDC_B0
+    PJ13     ------> LTDC_B1
+    PI12     ------> LTDC_HSYNC
+    PI13     ------> LTDC_VSYNC
+    PI14     ------> LTDC_CLK
+    PK2     ------> LTDC_G7
+    PK0     ------> LTDC_G5
+    PK1     ------> LTDC_G6
+    PJ11     ------> LTDC_G4
+    PJ10     ------> LTDC_G3
+    PJ9     ------> LTDC_G2
+    PJ0     ------> LTDC_R1
+    PJ8     ------> LTDC_G1
+    PJ7     ------> LTDC_G0
+    PJ6     ------> LTDC_R7
+    PI15     ------> LTDC_R0
+    PJ1     ------> LTDC_R2
+    PJ5     ------> LTDC_R6
+    PJ2     ------> LTDC_R3
+    PJ3     ------> LTDC_R4
+    PJ4     ------> LTDC_R5
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_3
+                          |GPIO_PIN_7|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOK, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_0
+                          |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_1
+                          |GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOJ, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN LTDC_MspInit 1 */
+
+  /* USER CODE END LTDC_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief LTDC MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hltdc: LTDC handle pointer
+* @retval None
+*/
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+{
+  if(hltdc->Instance==LTDC)
+  {
+  /* USER CODE BEGIN LTDC_MspDeInit 0 */
+
+  /* USER CODE END LTDC_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_LTDC_CLK_DISABLE();
+
+    /**LTDC GPIO Configuration
+    PK5     ------> LTDC_B6
+    PK4     ------> LTDC_B5
+    PJ15     ------> LTDC_B3
+    PK6     ------> LTDC_B7
+    PK3     ------> LTDC_B4
+    PK7     ------> LTDC_DE
+    PJ14     ------> LTDC_B2
+    PJ12     ------> LTDC_B0
+    PJ13     ------> LTDC_B1
+    PI12     ------> LTDC_HSYNC
+    PI13     ------> LTDC_VSYNC
+    PI14     ------> LTDC_CLK
+    PK2     ------> LTDC_G7
+    PK0     ------> LTDC_G5
+    PK1     ------> LTDC_G6
+    PJ11     ------> LTDC_G4
+    PJ10     ------> LTDC_G3
+    PJ9     ------> LTDC_G2
+    PJ0     ------> LTDC_R1
+    PJ8     ------> LTDC_G1
+    PJ7     ------> LTDC_G0
+    PJ6     ------> LTDC_R7
+    PI15     ------> LTDC_R0
+    PJ1     ------> LTDC_R2
+    PJ5     ------> LTDC_R6
+    PJ2     ------> LTDC_R3
+    PJ3     ------> LTDC_R4
+    PJ4     ------> LTDC_R5
+    */
+    HAL_GPIO_DeInit(GPIOK, GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_6|GPIO_PIN_3
+                          |GPIO_PIN_7|GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1);
+
+    HAL_GPIO_DeInit(GPIOJ, GPIO_PIN_15|GPIO_PIN_14|GPIO_PIN_12|GPIO_PIN_13
+                          |GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_0
+                          |GPIO_PIN_8|GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_1
+                          |GPIO_PIN_5|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4);
+
+    HAL_GPIO_DeInit(GPIOI, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+  /* USER CODE BEGIN LTDC_MspDeInit 1 */
+
+  /* USER CODE END LTDC_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspInit(SD_HandleTypeDef* hsd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspInit 0 */
+
+  /* USER CODE END SDMMC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC1 GPIO Configuration
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8
+                          |GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF12_SDIO1;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC1 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspInit 1 */
+
+  /* USER CODE END SDMMC1_MspInit 1 */
+  }
+  else if(hsd->Instance==SDMMC2)
+  {
+  /* USER CODE BEGIN SDMMC2_MspInit 0 */
+
+  /* USER CODE END SDMMC2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SDMMC2_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**SDMMC2 GPIO Configuration
+    PB4 (NJTRST)     ------> SDMMC2_D3
+    PD6     ------> SDMMC2_CK
+    PB3 (JTDO/TRACESWO)     ------> SDMMC2_D2
+    PD7     ------> SDMMC2_CMD
+    PB15     ------> SDMMC2_D1
+    PB14     ------> SDMMC2_D0
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_SDIO2;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_SDIO2;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+    /* SDMMC2 interrupt Init */
+    HAL_NVIC_SetPriority(SDMMC2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SDMMC2_IRQn);
+  /* USER CODE BEGIN SDMMC2_MspInit 1 */
+
+  /* USER CODE END SDMMC2_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hsd: SD handle pointer
+* @retval None
+*/
+void HAL_SD_MspDeInit(SD_HandleTypeDef* hsd)
+{
+  if(hsd->Instance==SDMMC1)
+  {
+  /* USER CODE BEGIN SDMMC1_MspDeInit 0 */
+
+  /* USER CODE END SDMMC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC1_CLK_DISABLE();
+
+    /**SDMMC1 GPIO Configuration
+    PC10     ------> SDMMC1_D2
+    PC11     ------> SDMMC1_D3
+    PC12     ------> SDMMC1_CK
+    PD2     ------> SDMMC1_CMD
+    PC8     ------> SDMMC1_D0
+    PC9     ------> SDMMC1_D1
+    */
+    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_8
+                          |GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);
+
+    /* SDMMC1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC1_IRQn);
+  /* USER CODE BEGIN SDMMC1_MspDeInit 1 */
+
+  /* USER CODE END SDMMC1_MspDeInit 1 */
+  }
+  else if(hsd->Instance==SDMMC2)
+  {
+  /* USER CODE BEGIN SDMMC2_MspDeInit 0 */
+
+  /* USER CODE END SDMMC2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SDMMC2_CLK_DISABLE();
+
+    /**SDMMC2 GPIO Configuration
+    PB4 (NJTRST)     ------> SDMMC2_D3
+    PD6     ------> SDMMC2_CK
+    PB3 (JTDO/TRACESWO)     ------> SDMMC2_D2
+    PD7     ------> SDMMC2_CMD
+    PB15     ------> SDMMC2_D1
+    PB14     ------> SDMMC2_D0
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4|GPIO_PIN_3|GPIO_PIN_15|GPIO_PIN_14);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* SDMMC2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(SDMMC2_IRQn);
+  /* USER CODE BEGIN SDMMC2_MspDeInit 1 */
+
+  /* USER CODE END SDMMC2_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**SPI1 GPIO Configuration
+    PB5     ------> SPI1_MOSI
+    PG9     ------> SPI1_MISO
+    PA5     ------> SPI1_SCK
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+  else if(hspi->Instance==SPI4)
+  {
+  /* USER CODE BEGIN SPI4_MspInit 0 */
+
+  /* USER CODE END SPI4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_SPI4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    /**SPI4 GPIO Configuration
+    PE2     ------> SPI4_SCK
+    PE5     ------> SPI4_MISO
+    PE6     ------> SPI4_MOSI
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_5|GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI4;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN SPI4_MspInit 1 */
+
+  /* USER CODE END SPI4_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief SPI MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hspi: SPI handle pointer
+* @retval None
+*/
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+  if(hspi->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+
+    /**SPI1 GPIO Configuration
+    PB5     ------> SPI1_MOSI
+    PG9     ------> SPI1_MISO
+    PA5     ------> SPI1_SCK
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+
+    HAL_GPIO_DeInit(GPIOG, GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5);
+
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+  else if(hspi->Instance==SPI4)
+  {
+  /* USER CODE BEGIN SPI4_MspDeInit 0 */
+
+  /* USER CODE END SPI4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI4_CLK_DISABLE();
+
+    /**SPI4 GPIO Configuration
+    PE2     ------> SPI4_SCK
+    PE5     ------> SPI4_MISO
+    PE6     ------> SPI4_MOSI
+    */
+    HAL_GPIO_DeInit(GPIOE, GPIO_PIN_2|GPIO_PIN_5|GPIO_PIN_6);
+
+  /* USER CODE BEGIN SPI4_MspDeInit 1 */
+
+  /* USER CODE END SPI4_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief TIM_PWM MSP Initialization
+* This function configures the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspInit 0 */
+
+  /* USER CODE END TIM5_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM5_CLK_ENABLE();
+  /* USER CODE BEGIN TIM5_MspInit 1 */
+
+  /* USER CODE END TIM5_MspInit 1 */
+  }
+
+}
+
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspPostInit 0 */
+
+  /* USER CODE END TIM5_MspPostInit 0 */
+
+    __HAL_RCC_GPIOH_CLK_ENABLE();
+    /**TIM5 GPIO Configuration
+    PH10     ------> TIM5_CH1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM5;
+    HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM5_MspPostInit 1 */
+
+  /* USER CODE END TIM5_MspPostInit 1 */
+  }
+
+}
+/**
+* @brief TIM_PWM MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param htim_pwm: TIM_PWM handle pointer
+* @retval None
+*/
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+  if(htim_pwm->Instance==TIM5)
+  {
+  /* USER CODE BEGIN TIM5_MspDeInit 0 */
+
+  /* USER CODE END TIM5_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM5_CLK_DISABLE();
+  /* USER CODE BEGIN TIM5_MspDeInit 1 */
+
+  /* USER CODE END TIM5_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspInit 0 */
+
+  /* USER CODE END UART4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_UART4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOI_CLK_ENABLE();
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**UART4 GPIO Configuration
+    PI9     ------> UART4_RX
+    PA0     ------> UART4_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_9;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_0;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN UART4_MspInit 1 */
+
+  /* USER CODE END UART4_MspInit 1 */
+  }
+  else if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspInit 0 */
+
+  /* USER CODE END USART3_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_USART3_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOD_CLK_ENABLE();
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    PD11     ------> USART3_CTS
+    PD12     ------> USART3_RTS
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN USART3_MspInit 1 */
+
+  /* USER CODE END USART3_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspDeInit 0 */
+
+  /* USER CODE END UART4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART4_CLK_DISABLE();
+
+    /**UART4 GPIO Configuration
+    PI9     ------> UART4_RX
+    PA0     ------> UART4_TX
+    */
+    HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9);
+
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0);
+
+  /* USER CODE BEGIN UART4_MspDeInit 1 */
+
+  /* USER CODE END UART4_MspDeInit 1 */
+  }
+  else if(huart->Instance==USART3)
+  {
+  /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+  /* USER CODE END USART3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART3_CLK_DISABLE();
+
+    /**USART3 GPIO Configuration
+    PB10     ------> USART3_TX
+    PB11     ------> USART3_RX
+    PD11     ------> USART3_CTS
+    PD12     ------> USART3_RTS
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_10|GPIO_PIN_11);
+
+    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_11|GPIO_PIN_12);
+
+  /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+  /* USER CODE END USART3_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief PCD MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF10_OTG1_FS;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
+    /* USB_OTG_FS interrupt Init */
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
+  /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief PCD MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hpcd: PCD handle pointer
+* @retval None
+*/
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd)
+{
+  if(hpcd->Instance==USB_OTG_FS)
+  {
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USB_OTG_FS_CLK_DISABLE();
+
+    /**USB_OTG_FS GPIO Configuration
+    PA12     ------> USB_OTG_FS_DP
+    PA11     ------> USB_OTG_FS_DM
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12|GPIO_PIN_11);
+
+    /* USB_OTG_FS interrupt DeInit */
+    HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
+  /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */
+
+  /* USER CODE END USB_OTG_FS_MspDeInit 1 */
+  }
+
+}
+
+static uint32_t FMC_Initialized = 0;
+
+static void HAL_FMC_MspInit(void){
+  /* USER CODE BEGIN FMC_MspInit 0 */
+
+  /* USER CODE END FMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct ={0};
+  if (FMC_Initialized) {
+    return;
+  }
+  FMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_ENABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PD1   ------> FMC_D3
+  PG8   ------> FMC_SDCLK
+  PF2   ------> FMC_A2
+  PF1   ------> FMC_A1
+  PF0   ------> FMC_A0
+  PG5   ------> FMC_BA1
+  PF3   ------> FMC_A3
+  PG4   ------> FMC_BA0
+  PG2   ------> FMC_A12
+  PF5   ------> FMC_A5
+  PF4   ------> FMC_A4
+  PC2   ------> FMC_SDNE0
+  PC3   ------> FMC_SDCKE0
+  PE10   ------> FMC_D7
+  PH5   ------> FMC_SDNWE
+  PF13   ------> FMC_A7
+  PF14   ------> FMC_A8
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PD15   ------> FMC_D1
+  PD14   ------> FMC_D0
+  PF12   ------> FMC_A6
+  PF15   ------> FMC_A9
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PF11   ------> FMC_SDNRAS
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PE13   ------> FMC_D10
+  PD10   ------> FMC_D15
+  PD9   ------> FMC_D14
+  PG1   ------> FMC_A11
+  PE7   ------> FMC_D4
+  PE14   ------> FMC_D11
+  PD8   ------> FMC_D13
+  */
+  GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_8
+                          |GPIO_PIN_13|GPIO_PIN_7|GPIO_PIN_14;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
+                          |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
+                          |GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3
+                          |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_11;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+  HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FMC_MspInit 1 */
+
+  /* USER CODE END FMC_MspInit 1 */
+}
+
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
+  /* USER CODE BEGIN SDRAM_MspInit 0 */
+
+  /* USER CODE END SDRAM_MspInit 0 */
+  HAL_FMC_MspInit();
+  /* USER CODE BEGIN SDRAM_MspInit 1 */
+
+  /* USER CODE END SDRAM_MspInit 1 */
+}
+
+static uint32_t FMC_DeInitialized = 0;
+
+static void HAL_FMC_MspDeInit(void){
+  /* USER CODE BEGIN FMC_MspDeInit 0 */
+
+  /* USER CODE END FMC_MspDeInit 0 */
+  if (FMC_DeInitialized) {
+    return;
+  }
+  FMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FMC_CLK_DISABLE();
+
+  /** FMC GPIO Configuration
+  PE1   ------> FMC_NBL1
+  PE0   ------> FMC_NBL0
+  PG15   ------> FMC_SDNCAS
+  PD0   ------> FMC_D2
+  PD1   ------> FMC_D3
+  PG8   ------> FMC_SDCLK
+  PF2   ------> FMC_A2
+  PF1   ------> FMC_A1
+  PF0   ------> FMC_A0
+  PG5   ------> FMC_BA1
+  PF3   ------> FMC_A3
+  PG4   ------> FMC_BA0
+  PG2   ------> FMC_A12
+  PF5   ------> FMC_A5
+  PF4   ------> FMC_A4
+  PC2   ------> FMC_SDNE0
+  PC3   ------> FMC_SDCKE0
+  PE10   ------> FMC_D7
+  PH5   ------> FMC_SDNWE
+  PF13   ------> FMC_A7
+  PF14   ------> FMC_A8
+  PE9   ------> FMC_D6
+  PE11   ------> FMC_D8
+  PD15   ------> FMC_D1
+  PD14   ------> FMC_D0
+  PF12   ------> FMC_A6
+  PF15   ------> FMC_A9
+  PE12   ------> FMC_D9
+  PE15   ------> FMC_D12
+  PF11   ------> FMC_SDNRAS
+  PG0   ------> FMC_A10
+  PE8   ------> FMC_D5
+  PE13   ------> FMC_D10
+  PD10   ------> FMC_D15
+  PD9   ------> FMC_D14
+  PG1   ------> FMC_A11
+  PE7   ------> FMC_D4
+  PE14   ------> FMC_D11
+  PD8   ------> FMC_D13
+  */
+  HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_10|GPIO_PIN_9
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_8
+                          |GPIO_PIN_13|GPIO_PIN_7|GPIO_PIN_14);
+
+  HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
+                          |GPIO_PIN_2|GPIO_PIN_0|GPIO_PIN_1);
+
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
+                          |GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8);
+
+  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_3
+                          |GPIO_PIN_5|GPIO_PIN_4|GPIO_PIN_13|GPIO_PIN_14
+                          |GPIO_PIN_12|GPIO_PIN_15|GPIO_PIN_11);
+
+  HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3);
+
+  HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5);
+
+  /* USER CODE BEGIN FMC_MspDeInit 1 */
+
+  /* USER CODE END FMC_MspDeInit 1 */
+}
+
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
+  /* USER CODE BEGIN SDRAM_MspDeInit 0 */
+
+  /* USER CODE END SDRAM_MspDeInit 0 */
+  HAL_FMC_MspDeInit();
+  /* USER CODE BEGIN SDRAM_MspDeInit 1 */
+
+  /* USER CODE END SDRAM_MspDeInit 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Src/stm32h7xx_it.c

@@ -0,0 +1,262 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32h7xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern ETH_HandleTypeDef heth;
+extern SD_HandleTypeDef hsd1;
+extern SD_HandleTypeDef hsd2;
+extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32H7xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32h7xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles SDMMC1 global interrupt.
+  */
+void SDMMC1_IRQHandler(void)
+{
+  /* USER CODE BEGIN SDMMC1_IRQn 0 */
+
+  /* USER CODE END SDMMC1_IRQn 0 */
+  HAL_SD_IRQHandler(&hsd1);
+  /* USER CODE BEGIN SDMMC1_IRQn 1 */
+
+  /* USER CODE END SDMMC1_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Ethernet global interrupt.
+  */
+void ETH_IRQHandler(void)
+{
+  /* USER CODE BEGIN ETH_IRQn 0 */
+
+  /* USER CODE END ETH_IRQn 0 */
+  HAL_ETH_IRQHandler(&heth);
+  /* USER CODE BEGIN ETH_IRQn 1 */
+
+  /* USER CODE END ETH_IRQn 1 */
+}
+
+/**
+  * @brief This function handles USB On The Go FS global interrupt.
+  */
+void OTG_FS_IRQHandler(void)
+{
+  /* USER CODE BEGIN OTG_FS_IRQn 0 */
+
+  /* USER CODE END OTG_FS_IRQn 0 */
+  HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);
+  /* USER CODE BEGIN OTG_FS_IRQn 1 */
+
+  /* USER CODE END OTG_FS_IRQn 1 */
+}
+
+/**
+  * @brief This function handles SDMMC2 global interrupt.
+  */
+void SDMMC2_IRQHandler(void)
+{
+  /* USER CODE BEGIN SDMMC2_IRQn 0 */
+
+  /* USER CODE END SDMMC2_IRQn 0 */
+  HAL_SD_IRQHandler(&hsd2);
+  /* USER CODE BEGIN SDMMC2_IRQn 1 */
+
+  /* USER CODE END SDMMC2_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/Core/Src/system_stm32h7xx.c

@@ -0,0 +1,421 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32h7xx.c
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
+  *
+  *   This file provides two functions and one global variable to be called from
+  *   user application:
+  *      - SystemInit(): This function is called at startup just after reset and
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32h7xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock, it can be used
+  *                                  by the user application to setup the SysTick
+  *                                  timer or configure other parameters.
+  *
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32h7xx_system
+  * @{
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32h7xx.h"
+#include <math.h>
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (CSI_VALUE)
+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Defines
+  * @{
+  */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
+/* #define DATA_IN_D2_SRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00000000UL /*!< Vector Table base offset field.
+                                      This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Variables
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 64000000;
+  uint32_t SystemD2Clock = 64000000;
+  const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32H7xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the FPU setting and  vector table location
+  *         configuration.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+#if defined (DATA_IN_D2_SRAM)
+ __IO uint32_t tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+  /* FPU settings ------------------------------------------------------------*/
+  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
+  #endif
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+
+   /* Increasing the CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+  }
+
+  /* Set HSION bit */
+  RCC->CR |= RCC_CR_HSION;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
+  RCC->CR &= 0xEAF6ED7FU;
+  
+   /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
+  }
+
+#if defined(D3_SRAM_BASE)
+  /* Reset D1CFGR register */
+  RCC->D1CFGR = 0x00000000;
+
+  /* Reset D2CFGR register */
+  RCC->D2CFGR = 0x00000000;
+
+  /* Reset D3CFGR register */
+  RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
+
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
+  /* Reset PLLCKSELR register */
+  RCC->PLLCKSELR = 0x02020200;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x01FF0000;
+  /* Reset PLL1DIVR register */
+  RCC->PLL1DIVR = 0x01010280;
+  /* Reset PLL1FRACR register */
+  RCC->PLL1FRACR = 0x00000000;
+
+  /* Reset PLL2DIVR register */
+  RCC->PLL2DIVR = 0x01010280;
+
+  /* Reset PLL2FRACR register */
+
+  RCC->PLL2FRACR = 0x00000000;
+  /* Reset PLL3DIVR register */
+  RCC->PLL3DIVR = 0x01010280;
+
+  /* Reset PLL3FRACR register */
+  RCC->PLL3FRACR = 0x00000000;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= 0xFFFBFFFFU;
+
+  /* Disable all interrupts */
+  RCC->CIER = 0x00000000;
+
+#if (STM32H7_DEV_ID == 0x450UL)
+  /* dual core CM7 or single core line */
+  if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
+  {
+    /* if stm32h7 revY*/
+    /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
+    *((__IO uint32_t*)0x51008108) = 0x000000001U;
+  }
+#endif
+
+#if defined (DATA_IN_D2_SRAM)
+  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
+#if defined(RCC_AHB2ENR_D2SRAM3EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
+#elif defined(RCC_AHB2ENR_D2SRAM2EN)
+  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
+#else
+  RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
+#endif /* RCC_AHB2ENR_D2SRAM3EN */
+
+  tmpreg = RCC->AHB2ENR;
+  (void) tmpreg;
+#endif /* DATA_IN_D2_SRAM */
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D2_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif /* VECT_TAB_SRAM */
+
+#else
+
+  /*
+   * Disable the FMC bank1 (enabled after reset).
+   * This, prevents CPU speculation access on this bank which blocks the use of FMC during
+   * 24us. During this time the others FMC master (such as LTDC) cannot use it!
+   */
+  FMC_Bank1_R->BTCR[0] = 0x000030D2;
+
+  /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = D1_AXISRAM_BASE  | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
+#else
+  SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+#endif /*DUAL_CORE && CORE_CM4*/
+
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock , it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *
+  * @note   Each time the core clock changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.
+  *
+  * @note   - The system frequency computed by this function is not the real
+  *           frequency in the chip. It is calculated based on the predefined
+  *           constant and the selected clock source:
+  *
+  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
+  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
+  *
+  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             4 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *             64 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.
+  *
+  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
+  uint32_t common_system_clock;
+  float_t fracn1, pllvco;
+
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
+    break;
+
+  case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
+    common_system_clock = CSI_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    common_system_clock = HSE_VALUE;
+    break;
+
+  case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
+
+    /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
+    SYSCLK = PLL_VCO / PLLR
+    */
+    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
+    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
+    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
+    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
+
+    if (pllm != 0U)
+    {
+      switch (pllsource)
+      {
+        case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
+
+        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
+        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+        case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
+          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+
+      default:
+          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
+        break;
+      }
+      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
+      common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
+    }
+    else
+    {
+      common_system_clock = 0U;
+    }
+    break;
+
+  default:
+    common_system_clock = CSI_VALUE;
+    break;
+  }
+
+  /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
+  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
+
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* common_system_clock frequency : CM7 CPU frequency  */
+  common_system_clock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
+
+#if defined(DUAL_CORE) && defined(CORE_CM4)
+  SystemCoreClock = SystemD2Clock;
+#else
+  SystemCoreClock = common_system_clock;
+#endif /* DUAL_CORE && CORE_CM4 */
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

projects/lrs007_lora_radio/board/CubeMX_Config/CubeMX_Config.ioc

@@ -0,0 +1,748 @@
+#MicroXplorer Configuration settings - do not modify
+ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_5
+ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag
+ADC1.NbrOfConversionFlag=1
+ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
+ADC1.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
+ADC1.Rank-0\#ChannelRegularConversion=1
+ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
+ADC1.master=1
+ETH.IPParameters=MediaInterface
+ETH.MediaInterface=HAL_ETH_RMII_MODE
+File.Version=6
+GPIO.groupedBy=
+KeepUserPlacement=false
+Mcu.Family=STM32H7
+Mcu.IP0=ADC1
+Mcu.IP1=CORTEX_M7
+Mcu.IP10=SPI4
+Mcu.IP11=SYS
+Mcu.IP12=TIM5
+Mcu.IP13=UART4
+Mcu.IP14=USART3
+Mcu.IP15=USB_OTG_FS
+Mcu.IP2=ETH
+Mcu.IP3=FMC
+Mcu.IP4=LTDC
+Mcu.IP5=NVIC
+Mcu.IP6=RCC
+Mcu.IP7=SDMMC1
+Mcu.IP8=SDMMC2
+Mcu.IP9=SPI1
+Mcu.IPNb=16
+Mcu.Name=STM32H750XBHx
+Mcu.Package=TFBGA240
+Mcu.Pin0=PB5
+Mcu.Pin1=PK5
+Mcu.Pin10=PC11
+Mcu.Pin100=PJ4
+Mcu.Pin101=PG1
+Mcu.Pin102=PE7
+Mcu.Pin103=PE14
+Mcu.Pin104=PB14
+Mcu.Pin105=PD8
+Mcu.Pin106=VP_SYS_VS_Systick
+Mcu.Pin11=PE2
+Mcu.Pin12=PE0
+Mcu.Pin13=PB3 (JTDO/TRACESWO)
+Mcu.Pin14=PK6
+Mcu.Pin15=PK3
+Mcu.Pin16=PD7
+Mcu.Pin17=PC12
+Mcu.Pin18=PE5
+Mcu.Pin19=PG15
+Mcu.Pin2=PG9
+Mcu.Pin20=PK7
+Mcu.Pin21=PG14
+Mcu.Pin22=PG13
+Mcu.Pin23=PJ14
+Mcu.Pin24=PJ12
+Mcu.Pin25=PD2
+Mcu.Pin26=PD0
+Mcu.Pin27=PI9
+Mcu.Pin28=PE6
+Mcu.Pin29=PJ13
+Mcu.Pin3=PC10
+Mcu.Pin30=PD1
+Mcu.Pin31=PC8
+Mcu.Pin32=PC9
+Mcu.Pin33=PA12
+Mcu.Pin34=PA11
+Mcu.Pin35=PG8
+Mcu.Pin36=PF2
+Mcu.Pin37=PF1
+Mcu.Pin38=PF0
+Mcu.Pin39=PG5
+Mcu.Pin4=PE1
+Mcu.Pin40=PI12
+Mcu.Pin41=PI13
+Mcu.Pin42=PI14
+Mcu.Pin43=PF3
+Mcu.Pin44=PG4
+Mcu.Pin45=PG2
+Mcu.Pin46=PK2
+Mcu.Pin47=PH1-OSC_OUT (PH1)
+Mcu.Pin48=PH0-OSC_IN (PH0)
+Mcu.Pin49=PF5
+Mcu.Pin5=PB4 (NJTRST)
+Mcu.Pin50=PF4
+Mcu.Pin51=PK0
+Mcu.Pin52=PK1
+Mcu.Pin53=PJ11
+Mcu.Pin54=PJ10
+Mcu.Pin55=PC1
+Mcu.Pin56=PC2
+Mcu.Pin57=PC3
+Mcu.Pin58=PJ9
+Mcu.Pin59=PA2
+Mcu.Pin6=PK4
+Mcu.Pin60=PA1
+Mcu.Pin61=PA0
+Mcu.Pin62=PJ0
+Mcu.Pin63=PE10
+Mcu.Pin64=PJ8
+Mcu.Pin65=PJ7
+Mcu.Pin66=PJ6
+Mcu.Pin67=PH5
+Mcu.Pin68=PI15
+Mcu.Pin69=PJ1
+Mcu.Pin7=PG11
+Mcu.Pin70=PF13
+Mcu.Pin71=PF14
+Mcu.Pin72=PE9
+Mcu.Pin73=PE11
+Mcu.Pin74=PB10
+Mcu.Pin75=PB11
+Mcu.Pin76=PH10
+Mcu.Pin77=PD15
+Mcu.Pin78=PD14
+Mcu.Pin79=PA7
+Mcu.Pin8=PJ15
+Mcu.Pin80=PF12
+Mcu.Pin81=PF15
+Mcu.Pin82=PE12
+Mcu.Pin83=PE15
+Mcu.Pin84=PJ5
+Mcu.Pin85=PD11
+Mcu.Pin86=PD12
+Mcu.Pin87=PA5
+Mcu.Pin88=PC4
+Mcu.Pin89=PB1
+Mcu.Pin9=PD6
+Mcu.Pin90=PJ2
+Mcu.Pin91=PF11
+Mcu.Pin92=PG0
+Mcu.Pin93=PE8
+Mcu.Pin94=PE13
+Mcu.Pin95=PB15
+Mcu.Pin96=PD10
+Mcu.Pin97=PD9
+Mcu.Pin98=PC5
+Mcu.Pin99=PJ3
+Mcu.PinsNb=107
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
+Mcu.UserName=STM32H750XBHx
+MxCube.Version=6.0.1
+MxDb.Version=DB.6.0.0
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.ForceEnableDMAVector=true
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
+NVIC.SDMMC1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SDMMC2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
+PA0.Locked=true
+PA0.Mode=Asynchronous
+PA0.Signal=UART4_TX
+PA1.GPIOParameters=GPIO_Speed
+PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA1.Mode=RMII
+PA1.Signal=ETH_REF_CLK
+PA11.GPIOParameters=GPIO_Speed
+PA11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA11.Mode=Device_Only
+PA11.Signal=USB_OTG_FS_DM
+PA12.GPIOParameters=GPIO_Speed
+PA12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA12.Mode=Device_Only
+PA12.Signal=USB_OTG_FS_DP
+PA2.GPIOParameters=GPIO_Speed
+PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA2.Mode=RMII
+PA2.Signal=ETH_MDIO
+PA5.GPIOParameters=GPIO_Speed
+PA5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PA5.Mode=Full_Duplex_Master
+PA5.Signal=SPI1_SCK
+PA7.GPIOParameters=GPIO_Speed
+PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PA7.Mode=RMII
+PA7.Signal=ETH_CRS_DV
+PB1.Signal=ADCx_INP5
+PB10.Mode=Asynchronous
+PB10.Signal=USART3_TX
+PB11.Mode=Asynchronous
+PB11.Signal=USART3_RX
+PB14.Mode=SD_4_bits_Wide_bus
+PB14.Signal=SDMMC2_D0
+PB15.Mode=SD_4_bits_Wide_bus
+PB15.Signal=SDMMC2_D1
+PB3\ (JTDO/TRACESWO).Mode=SD_4_bits_Wide_bus
+PB3\ (JTDO/TRACESWO).Signal=SDMMC2_D2
+PB4\ (NJTRST).Mode=SD_4_bits_Wide_bus
+PB4\ (NJTRST).Signal=SDMMC2_D3
+PB5.GPIOParameters=GPIO_Speed
+PB5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PB5.Mode=Full_Duplex_Master
+PB5.Signal=SPI1_MOSI
+PC1.GPIOParameters=GPIO_Speed
+PC1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC1.Mode=RMII
+PC1.Signal=ETH_MDC
+PC10.Mode=SD_4_bits_Wide_bus
+PC10.Signal=SDMMC1_D2
+PC11.Mode=SD_4_bits_Wide_bus
+PC11.Signal=SDMMC1_D3
+PC12.Mode=SD_4_bits_Wide_bus
+PC12.Signal=SDMMC1_CK
+PC2.GPIOParameters=GPIO_Speed_High_Default
+PC2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC2.Mode=SdramChipSelect1_1
+PC2.Signal=FMC_SDNE0
+PC3.GPIOParameters=GPIO_Speed_High_Default
+PC3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PC3.Mode=SdramChipSelect1_1
+PC3.Signal=FMC_SDCKE0
+PC4.GPIOParameters=GPIO_Speed
+PC4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC4.Mode=RMII
+PC4.Signal=ETH_RXD0
+PC5.GPIOParameters=GPIO_Speed
+PC5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PC5.Mode=RMII
+PC5.Signal=ETH_RXD1
+PC8.Mode=SD_4_bits_Wide_bus
+PC8.Signal=SDMMC1_D0
+PC9.Mode=SD_4_bits_Wide_bus
+PC9.Signal=SDMMC1_D1
+PD0.GPIOParameters=GPIO_Speed_High_Default
+PD0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD0.Signal=FMC_D2_DA2
+PD1.GPIOParameters=GPIO_Speed_High_Default
+PD1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD1.Signal=FMC_D3_DA3
+PD10.GPIOParameters=GPIO_Speed_High_Default
+PD10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD10.Signal=FMC_D15_DA15
+PD11.Mode=CTS_RTS
+PD11.Signal=USART3_CTS
+PD12.Mode=CTS_RTS
+PD12.Signal=USART3_RTS
+PD14.GPIOParameters=GPIO_Speed_High_Default
+PD14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD14.Signal=FMC_D0_DA0
+PD15.GPIOParameters=GPIO_Speed_High_Default
+PD15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD15.Signal=FMC_D1_DA1
+PD2.Mode=SD_4_bits_Wide_bus
+PD2.Signal=SDMMC1_CMD
+PD6.Mode=SD_4_bits_Wide_bus
+PD6.Signal=SDMMC2_CK
+PD7.Mode=SD_4_bits_Wide_bus
+PD7.Signal=SDMMC2_CMD
+PD8.GPIOParameters=GPIO_Speed_High_Default
+PD8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD8.Signal=FMC_D13_DA13
+PD9.GPIOParameters=GPIO_Speed_High_Default
+PD9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PD9.Signal=FMC_D14_DA14
+PE0.GPIOParameters=GPIO_Speed_High_Default
+PE0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE0.Signal=FMC_NBL0
+PE1.GPIOParameters=GPIO_Speed_High_Default
+PE1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE1.Signal=FMC_NBL1
+PE10.GPIOParameters=GPIO_Speed_High_Default
+PE10.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE10.Signal=FMC_D7_DA7
+PE11.GPIOParameters=GPIO_Speed_High_Default
+PE11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE11.Signal=FMC_D8_DA8
+PE12.GPIOParameters=GPIO_Speed_High_Default
+PE12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE12.Signal=FMC_D9_DA9
+PE13.GPIOParameters=GPIO_Speed_High_Default
+PE13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE13.Signal=FMC_D10_DA10
+PE14.GPIOParameters=GPIO_Speed_High_Default
+PE14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE14.Signal=FMC_D11_DA11
+PE15.GPIOParameters=GPIO_Speed_High_Default
+PE15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE15.Signal=FMC_D12_DA12
+PE2.GPIOParameters=GPIO_Speed
+PE2.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE2.Mode=Full_Duplex_Master
+PE2.Signal=SPI4_SCK
+PE5.GPIOParameters=GPIO_Speed
+PE5.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE5.Mode=Full_Duplex_Master
+PE5.Signal=SPI4_MISO
+PE6.GPIOParameters=GPIO_Speed
+PE6.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PE6.Mode=Full_Duplex_Master
+PE6.Signal=SPI4_MOSI
+PE7.GPIOParameters=GPIO_Speed_High_Default
+PE7.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE7.Signal=FMC_D4_DA4
+PE8.GPIOParameters=GPIO_Speed_High_Default
+PE8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE8.Signal=FMC_D5_DA5
+PE9.GPIOParameters=GPIO_Speed_High_Default
+PE9.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PE9.Signal=FMC_D6_DA6
+PF0.GPIOParameters=GPIO_Speed_High_Default
+PF0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF0.Signal=FMC_A0
+PF1.GPIOParameters=GPIO_Speed_High_Default
+PF1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF1.Signal=FMC_A1
+PF11.GPIOParameters=GPIO_Speed_High_Default
+PF11.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF11.Signal=FMC_SDNRAS
+PF12.GPIOParameters=GPIO_Speed_High_Default
+PF12.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF12.Signal=FMC_A6
+PF13.GPIOParameters=GPIO_Speed_High_Default
+PF13.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF13.Signal=FMC_A7
+PF14.GPIOParameters=GPIO_Speed_High_Default
+PF14.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF14.Signal=FMC_A8
+PF15.GPIOParameters=GPIO_Speed_High_Default
+PF15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF15.Signal=FMC_A9
+PF2.GPIOParameters=GPIO_Speed_High_Default
+PF2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF2.Signal=FMC_A2
+PF3.GPIOParameters=GPIO_Speed_High_Default
+PF3.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF3.Signal=FMC_A3
+PF4.GPIOParameters=GPIO_Speed_High_Default
+PF4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF4.Signal=FMC_A4
+PF5.GPIOParameters=GPIO_Speed_High_Default
+PF5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PF5.Signal=FMC_A5
+PG0.GPIOParameters=GPIO_Speed_High_Default
+PG0.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG0.Signal=FMC_A10
+PG1.GPIOParameters=GPIO_Speed_High_Default
+PG1.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG1.Signal=FMC_A11
+PG11.GPIOParameters=GPIO_Speed
+PG11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG11.Locked=true
+PG11.Mode=RMII
+PG11.Signal=ETH_TX_EN
+PG13.GPIOParameters=GPIO_Speed
+PG13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG13.Mode=RMII
+PG13.Signal=ETH_TXD0
+PG14.GPIOParameters=GPIO_Speed
+PG14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PG14.Locked=true
+PG14.Mode=RMII
+PG14.Signal=ETH_TXD1
+PG15.GPIOParameters=GPIO_Speed_High_Default
+PG15.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG15.Signal=FMC_SDNCAS
+PG2.GPIOParameters=GPIO_Speed_High_Default
+PG2.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG2.Signal=FMC_A12
+PG4.GPIOParameters=GPIO_Speed_High_Default
+PG4.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG4.Signal=FMC_A14_BA0
+PG5.GPIOParameters=GPIO_Speed_High_Default
+PG5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG5.Signal=FMC_A15_BA1
+PG8.GPIOParameters=GPIO_Speed_High_Default
+PG8.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PG8.Signal=FMC_SDCLK
+PG9.GPIOParameters=GPIO_Speed
+PG9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
+PG9.Mode=Full_Duplex_Master
+PG9.Signal=SPI1_MISO
+PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
+PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
+PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
+PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
+PH10.Signal=S_TIM5_CH1
+PH5.GPIOParameters=GPIO_Speed_High_Default
+PH5.GPIO_Speed_High_Default=GPIO_SPEED_FREQ_VERY_HIGH
+PH5.Locked=true
+PH5.Signal=FMC_SDNWE
+PI12.GPIOParameters=GPIO_Speed
+PI12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI12.Locked=true
+PI12.Mode=RGB888
+PI12.Signal=LTDC_HSYNC
+PI13.GPIOParameters=GPIO_Speed
+PI13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI13.Locked=true
+PI13.Mode=RGB888
+PI13.Signal=LTDC_VSYNC
+PI14.GPIOParameters=GPIO_Speed
+PI14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI14.Locked=true
+PI14.Mode=RGB888
+PI14.Signal=LTDC_CLK
+PI15.GPIOParameters=GPIO_Speed
+PI15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PI15.Locked=true
+PI15.Mode=RGB888
+PI15.Signal=LTDC_R0
+PI9.Locked=true
+PI9.Mode=Asynchronous
+PI9.Signal=UART4_RX
+PJ0.GPIOParameters=GPIO_Speed
+PJ0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ0.Mode=RGB888
+PJ0.Signal=LTDC_R1
+PJ1.GPIOParameters=GPIO_Speed
+PJ1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ1.Mode=RGB888
+PJ1.Signal=LTDC_R2
+PJ10.GPIOParameters=GPIO_Speed
+PJ10.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ10.Locked=true
+PJ10.Mode=RGB888
+PJ10.Signal=LTDC_G3
+PJ11.GPIOParameters=GPIO_Speed
+PJ11.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ11.Locked=true
+PJ11.Mode=RGB888
+PJ11.Signal=LTDC_G4
+PJ12.GPIOParameters=GPIO_Speed
+PJ12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ12.Locked=true
+PJ12.Mode=RGB888
+PJ12.Signal=LTDC_B0
+PJ13.GPIOParameters=GPIO_Speed
+PJ13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ13.Locked=true
+PJ13.Mode=RGB888
+PJ13.Signal=LTDC_B1
+PJ14.GPIOParameters=GPIO_Speed
+PJ14.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ14.Mode=RGB888
+PJ14.Signal=LTDC_B2
+PJ15.GPIOParameters=GPIO_Speed
+PJ15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ15.Mode=RGB888
+PJ15.Signal=LTDC_B3
+PJ2.GPIOParameters=GPIO_Speed
+PJ2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ2.Locked=true
+PJ2.Mode=RGB888
+PJ2.Signal=LTDC_R3
+PJ3.GPIOParameters=GPIO_Speed
+PJ3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ3.Locked=true
+PJ3.Mode=RGB888
+PJ3.Signal=LTDC_R4
+PJ4.GPIOParameters=GPIO_Speed
+PJ4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ4.Locked=true
+PJ4.Mode=RGB888
+PJ4.Signal=LTDC_R5
+PJ5.GPIOParameters=GPIO_Speed
+PJ5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ5.Locked=true
+PJ5.Mode=RGB888
+PJ5.Signal=LTDC_R6
+PJ6.GPIOParameters=GPIO_Speed
+PJ6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ6.Locked=true
+PJ6.Mode=RGB888
+PJ6.Signal=LTDC_R7
+PJ7.GPIOParameters=GPIO_Speed
+PJ7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ7.Mode=RGB888
+PJ7.Signal=LTDC_G0
+PJ8.GPIOParameters=GPIO_Speed
+PJ8.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ8.Mode=RGB888
+PJ8.Signal=LTDC_G1
+PJ9.GPIOParameters=GPIO_Speed
+PJ9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PJ9.Locked=true
+PJ9.Mode=RGB888
+PJ9.Signal=LTDC_G2
+PK0.GPIOParameters=GPIO_Speed
+PK0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK0.Locked=true
+PK0.Mode=RGB888
+PK0.Signal=LTDC_G5
+PK1.GPIOParameters=GPIO_Speed
+PK1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK1.Locked=true
+PK1.Mode=RGB888
+PK1.Signal=LTDC_G6
+PK2.GPIOParameters=GPIO_Speed
+PK2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK2.Locked=true
+PK2.Mode=RGB888
+PK2.Signal=LTDC_G7
+PK3.GPIOParameters=GPIO_Speed
+PK3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK3.Locked=true
+PK3.Mode=RGB888
+PK3.Signal=LTDC_B4
+PK4.GPIOParameters=GPIO_Speed
+PK4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK4.Locked=true
+PK4.Mode=RGB888
+PK4.Signal=LTDC_B5
+PK5.GPIOParameters=GPIO_Speed
+PK5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK5.Locked=true
+PK5.Mode=RGB888
+PK5.Signal=LTDC_B6
+PK6.GPIOParameters=GPIO_Speed
+PK6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK6.Locked=true
+PK6.Mode=RGB888
+PK6.Signal=LTDC_B7
+PK7.GPIOParameters=GPIO_Speed
+PK7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PK7.Mode=RGB888
+PK7.Signal=LTDC_DE
+PinOutPanel.CurrentBGAView=Top
+PinOutPanel.RotationAngle=0
+ProjectManager.AskForMigrate=true
+ProjectManager.BackupPrevious=false
+ProjectManager.CompilerOptimize=6
+ProjectManager.ComputerToolchain=false
+ProjectManager.CoupleFile=false
+ProjectManager.CustomerFirmwarePackage=
+ProjectManager.DefaultFWLocation=true
+ProjectManager.DeletePrevious=true
+ProjectManager.DeviceId=STM32H750XBHx
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.8.0
+ProjectManager.FreePins=false
+ProjectManager.HalAssertFull=false
+ProjectManager.HeapSize=0x200
+ProjectManager.KeepUserCode=true
+ProjectManager.LastFirmware=true
+ProjectManager.LibraryCopy=1
+ProjectManager.MainLocation=Core/Src
+ProjectManager.NoMain=false
+ProjectManager.PreviousToolchain=
+ProjectManager.ProjectBuild=false
+ProjectManager.ProjectFileName=CubeMX_Config.ioc
+ProjectManager.ProjectName=CubeMX_Config
+ProjectManager.RegisterCallBack=
+ProjectManager.StackSize=0x400
+ProjectManager.TargetToolchain=MDK-ARM V5.27
+ProjectManager.ToolChainLocation=
+ProjectManager.UnderRoot=false
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_LTDC_Init-LTDC-false-HAL-true,6-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,7-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,8-MX_SPI4_Init-SPI4-false-HAL-true,9-MX_UART4_Init-UART4-false-HAL-true,10-MX_SPI1_Init-SPI1-false-HAL-true,11-MX_USART3_UART_Init-USART3-false-HAL-true,12-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,13-MX_ADC1_Init-ADC1-false-HAL-true,14-MX_TIM5_Init-TIM5-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=400000000
+RCC.AHB12Freq_Value=240000000
+RCC.AHB4Freq_Value=240000000
+RCC.APB1Freq_Value=120000000
+RCC.APB2Freq_Value=120000000
+RCC.APB3Freq_Value=120000000
+RCC.APB4Freq_Value=120000000
+RCC.AXIClockFreq_Value=240000000
+RCC.CECFreq_Value=32000
+RCC.CKPERFreq_Value=64000000
+RCC.CortexFreq_Value=480000000
+RCC.CpuClockFreq_Value=480000000
+RCC.D1CPREFreq_Value=480000000
+RCC.D1PPRE=RCC_APB3_DIV2
+RCC.D2PPRE1=RCC_APB1_DIV2
+RCC.D2PPRE2=RCC_APB2_DIV2
+RCC.D3PPRE=RCC_APB4_DIV2
+RCC.DFSDMACLkFreq_Value=480000000
+RCC.DFSDMFreq_Value=120000000
+RCC.DIVM1=5
+RCC.DIVM2=2
+RCC.DIVM3=5
+RCC.DIVN1=192
+RCC.DIVN2=64
+RCC.DIVN3=160
+RCC.DIVP1Freq_Value=480000000
+RCC.DIVP2Freq_Value=400000000
+RCC.DIVP3=8
+RCC.DIVP3Freq_Value=100000000
+RCC.DIVQ1Freq_Value=480000000
+RCC.DIVQ2Freq_Value=400000000
+RCC.DIVQ3=8
+RCC.DIVQ3Freq_Value=100000000
+RCC.DIVR1Freq_Value=480000000
+RCC.DIVR2=4
+RCC.DIVR2Freq_Value=200000000
+RCC.DIVR3=24
+RCC.DIVR3Freq_Value=33333333.333333332
+RCC.FDCANFreq_Value=480000000
+RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL2
+RCC.FMCFreq_Value=200000000
+RCC.FamilyName=M
+RCC.HCLK3ClockFreq_Value=240000000
+RCC.HCLKFreq_Value=240000000
+RCC.HPRE=RCC_HCLK_DIV2
+RCC.HRTIMFreq_Value=240000000
+RCC.I2C123Freq_Value=120000000
+RCC.I2C4Freq_Value=120000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=120000000
+RCC.LPTIM2Freq_Value=120000000
+RCC.LPTIM345Freq_Value=120000000
+RCC.LPUART1Freq_Value=120000000
+RCC.LTDCFreq_Value=33333333.333333332
+RCC.MCO1PinFreq_Value=64000000
+RCC.MCO2PinFreq_Value=480000000
+RCC.PLL2FRACN=0
+RCC.PLLFRACN=0
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
+RCC.QSPIFreq_Value=240000000
+RCC.RNGFreq_Value=48000000
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=480000000
+RCC.SAI23Freq_Value=480000000
+RCC.SAI4AFreq_Value=480000000
+RCC.SAI4BFreq_Value=480000000
+RCC.SDMMC1CLockSelection=RCC_SDMMCCLKSOURCE_PLL2
+RCC.SDMMCFreq_Value=200000000
+RCC.SPDIFRXFreq_Value=480000000
+RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL2
+RCC.SPI123Freq_Value=400000000
+RCC.SPI45Freq_Value=100000000
+RCC.SPI6Freq_Value=120000000
+RCC.SWPMI1Freq_Value=120000000
+RCC.SYSCLKFreq_VALUE=480000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_PLL3
+RCC.Tim1OutputFreq_Value=240000000
+RCC.Tim2OutputFreq_Value=240000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=120000000
+RCC.USART234578Freq_Value=120000000
+RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48
+RCC.USBFreq_Value=48000000
+RCC.VCO1OutputFreq_Value=960000000
+RCC.VCO2OutputFreq_Value=800000000
+RCC.VCO3OutputFreq_Value=800000000
+RCC.VCOInput1Freq_Value=5000000
+RCC.VCOInput2Freq_Value=12500000
+RCC.VCOInput3Freq_Value=5000000
+SH.ADCx_INP5.0=ADC1_INP5,IN5-Single-Ended
+SH.ADCx_INP5.ConfNb=1
+SH.FMC_A0.0=FMC_A0,13b-sda1
+SH.FMC_A0.ConfNb=1
+SH.FMC_A1.0=FMC_A1,13b-sda1
+SH.FMC_A1.ConfNb=1
+SH.FMC_A10.0=FMC_A10,13b-sda1
+SH.FMC_A10.ConfNb=1
+SH.FMC_A11.0=FMC_A11,13b-sda1
+SH.FMC_A11.ConfNb=1
+SH.FMC_A12.0=FMC_A12,13b-sda1
+SH.FMC_A12.ConfNb=1
+SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
+SH.FMC_A14_BA0.ConfNb=1
+SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
+SH.FMC_A15_BA1.ConfNb=1
+SH.FMC_A2.0=FMC_A2,13b-sda1
+SH.FMC_A2.ConfNb=1
+SH.FMC_A3.0=FMC_A3,13b-sda1
+SH.FMC_A3.ConfNb=1
+SH.FMC_A4.0=FMC_A4,13b-sda1
+SH.FMC_A4.ConfNb=1
+SH.FMC_A5.0=FMC_A5,13b-sda1
+SH.FMC_A5.ConfNb=1
+SH.FMC_A6.0=FMC_A6,13b-sda1
+SH.FMC_A6.ConfNb=1
+SH.FMC_A7.0=FMC_A7,13b-sda1
+SH.FMC_A7.ConfNb=1
+SH.FMC_A8.0=FMC_A8,13b-sda1
+SH.FMC_A8.ConfNb=1
+SH.FMC_A9.0=FMC_A9,13b-sda1
+SH.FMC_A9.ConfNb=1
+SH.FMC_D0_DA0.0=FMC_D0,sd-16b-d1
+SH.FMC_D0_DA0.ConfNb=1
+SH.FMC_D10_DA10.0=FMC_D10,sd-16b-d1
+SH.FMC_D10_DA10.ConfNb=1
+SH.FMC_D11_DA11.0=FMC_D11,sd-16b-d1
+SH.FMC_D11_DA11.ConfNb=1
+SH.FMC_D12_DA12.0=FMC_D12,sd-16b-d1
+SH.FMC_D12_DA12.ConfNb=1
+SH.FMC_D13_DA13.0=FMC_D13,sd-16b-d1
+SH.FMC_D13_DA13.ConfNb=1
+SH.FMC_D14_DA14.0=FMC_D14,sd-16b-d1
+SH.FMC_D14_DA14.ConfNb=1
+SH.FMC_D15_DA15.0=FMC_D15,sd-16b-d1
+SH.FMC_D15_DA15.ConfNb=1
+SH.FMC_D1_DA1.0=FMC_D1,sd-16b-d1
+SH.FMC_D1_DA1.ConfNb=1
+SH.FMC_D2_DA2.0=FMC_D2,sd-16b-d1
+SH.FMC_D2_DA2.ConfNb=1
+SH.FMC_D3_DA3.0=FMC_D3,sd-16b-d1
+SH.FMC_D3_DA3.ConfNb=1
+SH.FMC_D4_DA4.0=FMC_D4,sd-16b-d1
+SH.FMC_D4_DA4.ConfNb=1
+SH.FMC_D5_DA5.0=FMC_D5,sd-16b-d1
+SH.FMC_D5_DA5.ConfNb=1
+SH.FMC_D6_DA6.0=FMC_D6,sd-16b-d1
+SH.FMC_D6_DA6.ConfNb=1
+SH.FMC_D7_DA7.0=FMC_D7,sd-16b-d1
+SH.FMC_D7_DA7.ConfNb=1
+SH.FMC_D8_DA8.0=FMC_D8,sd-16b-d1
+SH.FMC_D8_DA8.ConfNb=1
+SH.FMC_D9_DA9.0=FMC_D9,sd-16b-d1
+SH.FMC_D9_DA9.ConfNb=1
+SH.FMC_NBL0.0=FMC_NBL0,Sd2ByteEnable1
+SH.FMC_NBL0.ConfNb=1
+SH.FMC_NBL1.0=FMC_NBL1,Sd2ByteEnable1
+SH.FMC_NBL1.ConfNb=1
+SH.FMC_SDCLK.0=FMC_SDCLK,13b-sda1
+SH.FMC_SDCLK.ConfNb=1
+SH.FMC_SDNCAS.0=FMC_SDNCAS,13b-sda1
+SH.FMC_SDNCAS.ConfNb=1
+SH.FMC_SDNRAS.0=FMC_SDNRAS,13b-sda1
+SH.FMC_SDNRAS.ConfNb=1
+SH.FMC_SDNWE.0=FMC_SDNWE,13b-sda1
+SH.FMC_SDNWE.ConfNb=1
+SH.S_TIM5_CH1.0=TIM5_CH1,PWM Generation1 CH1
+SH.S_TIM5_CH1.ConfNb=1
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI1.CalculateBaudRate=200.0 MBits/s
+SPI1.Direction=SPI_DIRECTION_2LINES
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI1.Mode=SPI_MODE_MASTER
+SPI1.VirtualType=VM_MASTER
+SPI4.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2
+SPI4.CalculateBaudRate=50.0 MBits/s
+SPI4.Direction=SPI_DIRECTION_2LINES
+SPI4.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI4.Mode=SPI_MODE_MASTER
+SPI4.VirtualType=VM_MASTER
+TIM5.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM5.IPParameters=Channel-PWM Generation1 CH1
+USART3.IPParameters=VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USB_OTG_FS.IPParameters=VirtualMode
+USB_OTG_FS.VirtualMode=Device_Only
+VP_SYS_VS_Systick.Mode=SysTick
+VP_SYS_VS_Systick.Signal=SYS_VS_Systick
+board=custom

projects/lrs007_lora_radio/board/SConscript

@@ -0,0 +1,21 @@
+import os
+from building import *
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Glob('*.c')
+src += Glob('port/*.c')
+
+# add cubemx drivers
+src += Split('''
+CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
+''')
+
+path = [cwd]
+path += [cwd + '/port']
+path += [cwd + '/CubeMX_Config/Core/Inc']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

projects/lrs007_lora_radio/board/board.c

@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-29     RealThread   first version
+ */
+
+#include <rtthread.h>
+#include <board.h>
+#include <drv_common.h>
+
+#define DBG_TAG "board"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+void system_clock_config(int target_freq_mhz)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+  /** Supply configuration update enable
+  */
+  HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+  /** Macro to configure the PLL clock source
+  */
+  __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE);
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 5;
+  RCC_OscInitStruct.PLL.PLLN = 192;
+  RCC_OscInitStruct.PLL.PLLP = 2;
+  RCC_OscInitStruct.PLL.PLLQ = 2;
+  RCC_OscInitStruct.PLL.PLLR = 2;
+  RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+  RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+  RCC_OscInitStruct.PLL.PLLFRACN = 0;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
+                              |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+  RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+  RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC|RCC_PERIPHCLK_USART3
+                              |RCC_PERIPHCLK_UART4|RCC_PERIPHCLK_SPI4
+                              |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_SDMMC
+                              |RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB
+                              |RCC_PERIPHCLK_FMC;
+  PeriphClkInitStruct.PLL2.PLL2M = 2;
+  PeriphClkInitStruct.PLL2.PLL2N = 64;
+  PeriphClkInitStruct.PLL2.PLL2P = 2;
+  PeriphClkInitStruct.PLL2.PLL2Q = 2;
+  PeriphClkInitStruct.PLL2.PLL2R = 4;
+  PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
+  PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
+  PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
+  PeriphClkInitStruct.PLL3.PLL3M = 5;
+  PeriphClkInitStruct.PLL3.PLL3N = 160;
+  PeriphClkInitStruct.PLL3.PLL3P = 8;
+  PeriphClkInitStruct.PLL3.PLL3Q = 8;
+  PeriphClkInitStruct.PLL3.PLL3R = 24;
+  PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_2;
+  PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
+  PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
+  PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
+  PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL2;
+  PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL2;
+  PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL3;
+  PeriphClkInitStruct.Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1;
+  PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+  PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
+  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /** Enable USB Voltage detector
+  */
+  HAL_PWREx_EnableUSBVoltageDetector();
+}
+int clock_information(void)
+{
+    LOG_D("System Clock information");
+    LOG_D("SYSCLK_Frequency = %d", HAL_RCC_GetSysClockFreq());
+    LOG_D("HCLK_Frequency   = %d", HAL_RCC_GetHCLKFreq());
+    LOG_D("PCLK1_Frequency  = %d", HAL_RCC_GetPCLK1Freq());
+    LOG_D("PCLK2_Frequency  = %d", HAL_RCC_GetPCLK2Freq());
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(clock_information);
+
+void clk_init(char *clk_source, int source_freq, int target_freq)
+{
+    system_clock_config(target_freq);
+}
+
+
+RT_WEAK void rt_hw_board_init()
+{
+    extern void hw_board_init(char *clock_src, int32_t clock_src_freq, int32_t clock_target_freq);
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    hw_board_init(BSP_CLOCK_SOURCE, BSP_CLOCK_SOURCE_FREQ_MHZ, BSP_CLOCK_SYSTEM_FREQ_MHZ);
+
+    /* Set the shell console output device */
+#if defined(RT_USING_DEVICE) && defined(RT_USING_CONSOLE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}

projects/lrs007_lora_radio/board/board.h

@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-07-29     RealThread   first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include <stm32h7xx.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*-------------------------- CHIP CONFIG BEGIN --------------------------*/
+
+#define CHIP_FAMILY_STM32
+#define CHIP_SERIES_STM32H7
+#define CHIP_NAME_STM32H750XBHX
+
+/*-------------------------- CHIP CONFIG END --------------------------*/
+
+/*-------------------------- ROM/RAM CONFIG BEGIN --------------------------*/
+ #define ROM_START              ((uint32_t)0x90000000)
+ #define ROM_SIZE               (16384)
+ #define ROM_END                ((uint32_t)(ROM_START + ROM_SIZE * 1024))
+
+#define RAM_START              (0x24000000)
+#define RAM_SIZE               (512)
+#define RAM_END                (RAM_START + RAM_SIZE * 1024)
+
+/*-------------------------- ROM/RAM CONFIG END --------------------------*/
+
+/*-------------------------- CLOCK CONFIG BEGIN --------------------------*/
+
+#define BSP_CLOCK_SOURCE                  ("HSE")
+#define BSP_CLOCK_SOURCE_FREQ_MHZ         ((int32_t)0)
+#define BSP_CLOCK_SYSTEM_FREQ_MHZ         ((int32_t)480)
+
+/*-------------------------- CLOCK CONFIG END --------------------------*/
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+ *
+ * STEP 1, define macro define related to the serial port opening based on the serial port number
+ *                 such as     #define BSP_USING_UATR1
+ *
+ * STEP 2, according to the corresponding pin of serial port, define the related serial port information macro
+ *                 such as     #define BSP_UART1_TX_PIN       "PA9"
+ *                             #define BSP_UART1_RX_PIN       "PA10"
+ *
+ * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+ *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+ *
+ * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+ *                 such as     #define BSP_UART1_RX_USING_DMA
+ *
+ */
+
+#ifdef BSP_USING_UART1
+#define BSP_UART1_TX_PIN       "PA9"
+#define BSP_UART1_RX_PIN       "PA10"
+#endif
+
+#ifdef BSP_USING_UART4
+#define BSP_UART4_TX_PIN       "PA0"
+#define BSP_UART4_RX_PIN       "PI9"
+#endif
+
+#ifdef BSP_USING_UART6
+#define BSP_UART6_TX_PIN       "PC6"
+#define BSP_UART6_RX_PIN       "PC7"
+#endif
+
+
+/*-------------------------- UART CONFIG END --------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H__ */

projects/lrs007_lora_radio/board/drv_mpu.c

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-14     whj4674672   first version
+ */
+#include <rtthread.h>
+#include "stm32h7xx.h"
+#include "board.h"
+
+int mpu_init(void)
+{
+    MPU_Region_InitTypeDef MPU_InitStruct;
+
+    /* Disable the MPU */
+    HAL_MPU_Disable();
+
+    /* Configure the MPU attributes as WT for AXI SRAM */
+    MPU_InitStruct.Enable            = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress       = 0x24000000;
+    MPU_InitStruct.Size              = MPU_REGION_SIZE_512KB;
+    MPU_InitStruct.AccessPermission  = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable      = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable       = MPU_ACCESS_CACHEABLE;
+    MPU_InitStruct.IsShareable       = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number            = MPU_REGION_NUMBER0;
+    MPU_InitStruct.TypeExtField      = MPU_TEX_LEVEL0;
+    MPU_InitStruct.SubRegionDisable  = 0X00;
+    MPU_InitStruct.DisableExec       = MPU_INSTRUCTION_ACCESS_ENABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+
+#ifdef BSP_USING_SDRAM
+    /* Configure the MPU attributes as WT for SDRAM */
+    MPU_InitStruct.Enable            = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress       = 0xC0000000;
+    MPU_InitStruct.Size              = MPU_REGION_SIZE_32MB;
+    MPU_InitStruct.AccessPermission  = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable      = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable       = MPU_ACCESS_CACHEABLE;
+    MPU_InitStruct.IsShareable       = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number            = MPU_REGION_NUMBER1;
+    MPU_InitStruct.TypeExtField      = MPU_TEX_LEVEL0;
+    MPU_InitStruct.SubRegionDisable  = 0x00;
+    MPU_InitStruct.DisableExec       = MPU_INSTRUCTION_ACCESS_ENABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+#endif
+
+#ifdef BSP_USING_ETH
+    /* Configure the MPU attributes as Device not cacheable 
+       for ETH DMA descriptors */
+    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress = 0x30040000;
+    MPU_InitStruct.Size = MPU_REGION_SIZE_256B;
+    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
+    MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
+    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number = MPU_REGION_NUMBER2;
+    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+    MPU_InitStruct.SubRegionDisable = 0x00;
+    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+  
+    /* Configure the MPU attributes as Cacheable write through 
+       for LwIP RAM heap which contains the Tx buffers */
+    MPU_InitStruct.Enable = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress = 0x30044000;
+    MPU_InitStruct.Size = MPU_REGION_SIZE_16KB;
+    MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
+    MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number = MPU_REGION_NUMBER3;
+    MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
+    MPU_InitStruct.SubRegionDisable = 0x00;
+    MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+#endif
+
+    /* Configure the MPU attributes as WT for QSPI */
+    MPU_InitStruct.Enable            = MPU_REGION_ENABLE;
+    MPU_InitStruct.BaseAddress       = 0x90000000;
+    MPU_InitStruct.Size              = MPU_REGION_SIZE_8MB;
+    MPU_InitStruct.AccessPermission  = MPU_REGION_FULL_ACCESS;
+    MPU_InitStruct.IsBufferable      = MPU_ACCESS_NOT_BUFFERABLE;
+    MPU_InitStruct.IsCacheable       = MPU_ACCESS_CACHEABLE;
+    MPU_InitStruct.IsShareable       = MPU_ACCESS_NOT_SHAREABLE;
+    MPU_InitStruct.Number            = MPU_REGION_NUMBER4;
+    MPU_InitStruct.TypeExtField      = MPU_TEX_LEVEL0;
+    MPU_InitStruct.SubRegionDisable  = 0X00;
+    MPU_InitStruct.DisableExec       = MPU_INSTRUCTION_ACCESS_ENABLE;
+
+    HAL_MPU_ConfigRegion(&MPU_InitStruct);
+
+    /* Enable the MPU */
+    HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
+
+    /* Enable CACHE */
+    SCB_EnableICache();
+    SCB_EnableDCache();
+    
+    return RT_EOK;
+
+}
+INIT_BOARD_EXPORT(mpu_init);

projects/lrs007_lora_radio/board/linker_scripts/STM32H750XBHx/link.lds

@@ -0,0 +1,206 @@
+/*
+ * linker script for STM32H750XBHx with GNU ld
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+ROM (rx) : ORIGIN =0x90000000,LENGTH =8192k
+RAM (rw) : ORIGIN =0x24000000,LENGTH =512k
+RxDecripSection (rw) : ORIGIN =0x30040000,LENGTH =32k
+TxDecripSection (rw) : ORIGIN =0x30040060,LENGTH =32k
+RxArraySection (rw) : ORIGIN =0x30040200,LENGTH =32k
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x200;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for at server */
+        . = ALIGN(4);
+        __rtatcmdtab_start = .;
+        KEEP(*(RtAtCmdTab))
+        __rtatcmdtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+
+        _etext = .;
+    } > ROM = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > ROM
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >RAM
+
+    .stack : 
+    {
+        . = ALIGN(4);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >RAM
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > RAM
+    __bss_end = .;
+
+    .RxDecripSection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.RxDecripSection)
+    *(.RxDecripSection.*)
+    . = ALIGN(4);
+    __RxDecripSection_free__ = .;
+    } > RxDecripSection
+    
+    .TxDecripSection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.TxDecripSection)
+    *(.TxDecripSection.*)
+    . = ALIGN(4);
+    __TxDecripSection_free__ = .;
+    } > TxDecripSection
+    
+    .RxArraySection (NOLOAD) : ALIGN(4)
+    {
+    . = ALIGN(4);
+    *(.RxArraySection)
+    *(.RxArraySection.*)
+    . = ALIGN(4);
+    __RxArraySection_free__ = .;
+    } > RxArraySection
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

projects/lrs007_lora_radio/board/linker_scripts/STM32H750XBHx/link.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x90000000 0x00800000  {    ; load region size_region
+  ER_IROM1 0x90000000 0x00800000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x24000000 0x00080000  {  ; AXI SRAM 512K
+   .ANY (+RW +ZI)
+  }
+}

projects/lrs007_lora_radio/board/port/fal_cfg.h

@@ -0,0 +1,53 @@
+/*
+ * File      : fal_cfg.h
+ * This file is part of FAL (Flash Abstraction Layer) package
+ * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-17     armink       the first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtconfig.h>
+#include <board.h>
+
+#define NOR_FLASH_DEV_NAME             "norflash0"
+
+/* ===================== Flash device Configuration ========================= */
+extern struct fal_flash_dev nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &nor_flash0,                                                     \
+}
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+#define FAL_PART_TABLE                                                                     \
+{                                                                                          \
+    {FAL_PART_MAGIC_WORD, "wifi_image", NOR_FLASH_DEV_NAME,           0,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "bt_image",   NOR_FLASH_DEV_NAME,    512*1024,     512*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "download",   NOR_FLASH_DEV_NAME,   1024*1024,  2*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "easyflash",  NOR_FLASH_DEV_NAME, 3*1024*1024,  1*1024*1024, 0}, \
+    {FAL_PART_MAGIC_WORD, "filesystem", NOR_FLASH_DEV_NAME, 4*1024*1024, 12*1024*1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */

projects/lrs007_lora_radio/board/port/filesystem.c

@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2018-12-13     balanceTWK    add sdcard port file
+ * 2019-06-11     WillianChan   Add SD card hot plug detection
+ */
+
+#include <rtthread.h>
+
+#ifdef BSP_USING_FS
+#if DFS_FILESYSTEMS_MAX < 4
+#error "Please define DFS_FILESYSTEMS_MAX more than 4"
+#endif
+#if DFS_FILESYSTEM_TYPES_MAX < 4
+#error "Please define DFS_FILESYSTEM_TYPES_MAX more than 4"
+#endif
+
+#ifdef BSP_USING_SPI_FLASH_FS
+#include "fal.h"
+#endif
+
+#include <dfs_fs.h>
+#include "dfs_romfs.h"
+#include "drv_sdio.h"
+
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+
+static const struct romfs_dirent _romfs_root[] = {
+    {ROMFS_DIRENT_DIR, "flash", RT_NULL, 0},
+    {ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0}};
+
+const struct romfs_dirent romfs_root = {
+    ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root) / sizeof(_romfs_root[0])};
+
+#ifdef BSP_USING_SDCARD_FS
+
+/* SD Card hot plug detection pin */
+#define SD_CHECK_PIN GET_PIN(D, 5)
+
+static void _sdcard_mount(void)
+{
+    rt_device_t device;
+
+    device = rt_device_find("sd0");
+    if (device == NULL)
+    {
+        mmcsd_wait_cd_changed(0);
+        sdcard_change();
+        mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+        device = rt_device_find("sd0");
+    }
+    if (device != RT_NULL)
+    {
+        if (dfs_mount("sd0", "/sdcard", "elm", 0, 0) == RT_EOK)
+        {
+            LOG_I("sd card mount to '/sdcard'");
+        }
+        else
+        {
+            LOG_W("sd card mount to '/sdcard' failed!");
+        }
+    }
+}
+
+static void _sdcard_unmount(void)
+{
+    rt_thread_mdelay(200);
+    dfs_unmount("/sdcard");
+    LOG_I("Unmount \"/sdcard\"");
+
+    mmcsd_wait_cd_changed(0);
+    sdcard_change();
+    mmcsd_wait_cd_changed(RT_WAITING_FOREVER);
+}
+
+static void sd_mount(void *parameter)
+{
+    rt_uint8_t re_sd_check_pin = 1;
+    rt_thread_mdelay(200);
+    if (rt_pin_read(SD_CHECK_PIN))
+    {
+        _sdcard_mount();
+    }
+    while (1)
+    {
+        rt_thread_mdelay(200);
+        if (!re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) != 0)
+        {
+            _sdcard_mount();
+        }
+
+        if (re_sd_check_pin && (re_sd_check_pin = rt_pin_read(SD_CHECK_PIN)) == 0)
+        {
+            _sdcard_unmount();
+        }
+    }
+}
+
+#endif /* BSP_USING_SDCARD_FS */
+
+int mount_init(void)
+{
+    if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) != 0)
+    {
+        LOG_E("rom mount to '/' failed!");
+    }
+#ifdef BSP_USING_SPI_FLASH_FS
+    struct rt_device *flash_dev = RT_NULL;
+
+#ifndef RT_USING_WIFI
+    fal_init();
+#endif
+
+    flash_dev = fal_mtd_nor_device_create("filesystem");
+
+    if (flash_dev)
+    {
+        //mount filesystem
+        if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) != 0)
+        {
+            LOG_W("mount to '/flash' failed! try to mkfs %s", flash_dev->parent.name);
+            dfs_mkfs("lfs", flash_dev->parent.name);
+            if (dfs_mount(flash_dev->parent.name, "/flash", "lfs", 0, 0) == 0)
+            {
+                LOG_I("mount to '/flash' success!");
+            }
+        }
+        else
+        {
+            LOG_I("mount to '/flash' success!");
+        }
+    }
+    else
+    {
+        LOG_E("Can't create  block device  filesystem or bt_image partition.");
+    }
+
+#endif
+
+#ifdef BSP_USING_SDCARD_FS
+    rt_thread_t tid;
+
+    rt_pin_mode(SD_CHECK_PIN, PIN_MODE_INPUT_PULLUP);
+
+    tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX - 2, 20);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        LOG_E("create sd_mount thread err!");
+    }
+#endif
+    return RT_EOK;
+}
+INIT_APP_EXPORT(mount_init);
+
+#endif /* BSP_USING_FS */

projects/lrs007_lora_radio/cconfig.h

@@ -0,0 +1,18 @@
+#ifndef CCONFIG_H__
+#define CCONFIG_H__
+/* Automatically generated file; DO NOT EDIT. */
+/* compiler configure file for RT-Thread in GCC*/
+
+#define HAVE_NEWLIB_H 1
+#define LIBC_VERSION "newlib 2.4.0"
+
+#define HAVE_SYS_SIGNAL_H 1
+#define HAVE_SYS_SELECT_H 1
+#define HAVE_PTHREAD_H 1
+
+#define HAVE_FDSET 1
+#define HAVE_SIGACTION 1
+#define GCC_VERSION_STR "5.4.1 20160919 (release) [ARM/embedded-5-branch revision 240496]"
+#define STDC "2011"
+
+#endif

projects/lrs007_lora_radio/makefile.targets

@@ -0,0 +1,7 @@
+clean2:
+	-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
+	-$(RM) $(OBJS) *.elf
+	-@echo ' '
+
+
+*.elf: $(wildcard F:/K-Forest/RTOS/RT-Thread/artpi-master/sdk-artpi-pr/sdk-bsp-stm32h750-realthread-artpi/projects/lrs007_lora_radio/board/linker_scripts/STM32H750XBHx/link.lds)

projects/lrs007_lora_radio/mklinks.bat

@@ -0,0 +1,6 @@
+@echo off
+%1 mshta vbscript:CreateObject("Shell.Application").ShellExecute("cmd.exe","/c %~s0 ::","","runas",1)(window.close)&&exit
+cd /d "%~dp0"
+
+mklink /D rt-thread ..\..\rt-thread
+mklink /D libraries ..\..\libraries

projects/lrs007_lora_radio/packages/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/README.md

@@ -0,0 +1,4 @@
+# LoRa-Radio-Driver软件包 简介
+  LoRa-Radio-Driver软件包是基于RTOS( RT-Thread ) 实现的LoRa Tranceiver芯片的驱动文件包，可用于快速搭建基于LoRa等通信的应用产品。
+
+更多详细信息请查看[LoRa-Radio-Driver/doc](https://github.com/Forest-Rain/lora-radio-driver/tree/master/doc)

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/SConscript

@@ -0,0 +1,12 @@
+import os
+from building import *
+
+objs = []
+cwd  = GetCurrentDir()
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/doc/README.md

@@ -0,0 +1,377 @@
+# LoRa-Radio-Driver软件包使用说明
+
+# 1 简介
+LoRa-Radio-Driver软件包是基于RTOS( RT-Thread ) 实现的LoRa Tranceiver芯片的驱动文件，可用于快速搭建基于LoRa等通信的应用产品。
+LoRa-Radio-Driver软件包在LoRaWAN开源协议栈[LoRaMAC-Node中的radio](https://github.com/Forest-Rain/lora-radio-driver/blob/master/doc)基础上，进一步封装实现。
+> LoRaMac\Radio
+> [https://github.com/Lora-net/LoRaMac-node/tree/master/src/radio](https://github.com/Lora-net/LoRaMac-node/tree/master/src/radio)
+
+
+- 主要特点:
+   - 当前支持LoRa Transceiver（sx126x\sx127x ）
+      - 支持调制方式
+         - [x] LoRa
+         - [ ] FSK
+   - 可通过EVN工具menuconfig直接定义LoRa模块的对外接口，降低入门门槛
+     - 支持使用引脚号来定义GPIO
+     - 支持使用引脚名来定义GPIO
+   - 提供常用实例代码，可用于射频性能测试、空口数据包监听、双向通信测试等
+   - 可作为phy层对接到LoRaWAN End-Device协议栈
+   - 当前测试的LoRa 模块\芯片
+      - LoRa Transceiver (SPI)
+         - SX126X (SX1262\ASR6500S\LLCC68\SX1268..)
+            - SX1268
+               - [x] [LSD4RF-2R717N40 (CN470频段)](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)
+            - SX1262
+               - [x] ASR6500S
+               - [x] [LSD4RF-2R822N30 (868/915MHz频段)](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)
+            - LLCC68
+            - LR1110
+         - SX127X (SX1272\SX1276\SX1278..)
+            - SX1278
+               - [x] [LSD4RF-2F717N30(CN470频段)](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)
+               - [x] [Ra-01](http://wiki.ai-thinker.com/lora/man)
+         - [ ] SX1276
+      - LoRa SIP\SoC
+   - 当前测试的MCU平台
+      - LoRa Radio Driver当前功能主要在STM32L平台测试通过，未来计划将适配更多的MCU平台（华大MCU、nRF、BK）
+         - [x] STM32L0系列
+         - [x] STM32L4系列
+         - [x] STM32H7系列
+   - 当前支持的RTOS
+      - [x] RT-Thread
+      - [ ] RT-Thread Nano
+   - 当前测试的IDE
+      - [x] MDK5.29
+      - [x] RT-Thread Studio 1.1.3
+# 2 LoRa Radio Driver 软件包组织结构
+![image.png](https://github.com/Forest-Rain/lora-radio-driver/raw/master/doc/pics/01_lora-radio-driver_pkgs_struction.png)
+
+- lora-radio
+   - sx126x
+      - lora-radio-sx126x.c
+         - 对外提供了上层访问接口实现
+      - lora-spi-sx126x.c 
+         - sx126x芯片的spi读写接口实现，独立于MCU平台
+            - [x] rt_device
+            - [ ] SPI裸机方式
+      - sx126x.c
+         - lora芯片sx126x底层驱动
+   - sx127x
+      - lora-radio-sx127x.c 
+         - 对外提供了上层访问接口
+      - lora-spi-sx127x.c
+         - sx127x芯片的spi读写接口实现，独立于MCU平台
+            - [x] rt_device
+            - [ ] SPI裸机方式
+      - sx127x.c
+         - lora芯片sx127x底层驱动
+   - common
+      - lora-radio-timer.c
+         - 提供了lora-radio所需的定时服务接口，用于发送与接收超时等，基于RT-Thread内核rt_timer实现
+            - 注意这种方式提供的定时最小颗粒度取决于系统tick RT_TICK_PER_SECOND
+            - 注:如果使能了Multi-Rtimer软件包，则优先使用Multi-Rtimer提供定时\超时服务
+   - include
+      - lora-radio.h
+         - 上层服务接口
+      - lora-radio-debug.h
+         - 根据需要使能输出lora-radio不同层级的调试信息
+      - lora-radio-rtos-config.h
+         - rtos适配层，选择，当前默认为RT-Thread
+         - 未来支持RT-Thread-Nano、以及其他RTOS....
+- samples
+   - lora radio driver示例文件
+      - lora-radio-test-shell
+         - shell示例，主要实现了射频性能测试、空口数据包监听、双向通信测试等shell命令，便于日常测试
+- port
+   - 主要包含当前在不同MCU平台下支持的lora模块，lora-module文件夹中的xxxx-borad.c包含了与LoRa模块直接相关的主要硬件接口配置：
+      - lora-module
+         - stm32_adapter 
+            - lora-board-spi.c
+               - STM32平台的SPI外设初始化等通用接口
+            - LSD4RF-2F717N30 （SX1278 LoRa模块）
+            - LSD4RF-2R717N40 （SX1268 LoRa模块）
+            - LSD4RF-2R822N30 （SX1262 LoRa模块）
+            - Ra-01 （SX1278 LoRa模块）
+               - xxxx-borad.c
+                  - LoRa模块功率输出方式（PA\RFO...）
+                  - LoRa模块的RF高频开关控制方式（TXE、RXE、无..）
+                  - LoRa模块的DIO口（DIO0、DIO1、DIO2....）
+                  - LoRa模块的工作频率限制等
+         - xxx_adapter
+            - 其他mcu平台下的硬件接口实现
+# 3 LoRa Radio Driver软件包使用说明
+## 3.1 依赖
+
+- SPI外设——用户需根据实际MCU平台，自定义LoRa模块实际所需要使用的SPI外设
+   - 选择SPI外设 
+```
+  Hardware Drivers Config --->
+     On-chip Peripheral Drivers --->
+         [*] Enable SPI  --->
+                 --- Enable SPI
+                 [ ]   Enable SPI1
+                 [ ]   Enable SPI2
+                 [ ]   Enable SPI3
+                 [ ]   Enable SPI4
+                 [ ]   Enable SPI5
+```
+   - 在bsp\目标板XX\board\Kconfig增加如下定义
+```c
+  menuconfig BSP_USING_SPI
+       bool "Enable SPI"
+       select RT_USING_SPI
+
+       if BSP_USING_SPI
+         config BSP_USING_SPI1
+            bool "Enable SPI1"
+            default n
+            if BSP_USING_SPI1
+              config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+              config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+            endif
+            
+            # 根据实际需要，增加其他BSP_USING_SPI2、BSP_USING_SPI3...
+        endif
+```
+
+- 定时服务——用于提供射频通信所需的定时\超时服务，目前支持以下两种方式，二选一
+   - 内核 SOFT_TIMER
+      - 若未选用Multi-Rtimer软件包，则默认采用内核的rt_timer来提供定时服务(lora-radio-timer.c)
+      - 注意检测是否**开启RT-Thread内核的SOFT_TIMER**
+   - M[ulti-Rtimer](https://github.com/Forest-Rain/multi-rtimer)软件包
+      - 若使能multi-rtimer，lora-radio-driver优先使用multi-rtimer提供定时\超时服务。 
+> 注：如果应用在工业温度范围、时间精度要求高(us\ms级别)的场景，建议使用multi-rtimer，并设置RTC时钟源为外部32768晶振，否则可能会出现下行丢包的情况。
+
+```
+RT-Thread online packages --->
+    peripheral libraries and drivers --->
+        [*] multi_rtimer: a real-time and low power software timer module. --->
+                Version (latest)  --->
+                multi_rtimer options --->
+                    [] multi_rtimer demo example
+```
+
+- 可选内核组件
+   - ulog组件——用于打印日志信息
+      - 使能ulog
+         - ulog缓存大小设置≥ 128 Byte
+         - lora-raido-driver内部可看到更多LoRa底层的调试信息
+         - lora-radio-test-shell.c使用ulog接口，用于打印调试信息、原始16进制数据等
+      - 如果没有使用ulog，默认使用rt_kprintf来实现信息输出功能
+```
+RT-Thread Components --->
+   Utiliess --->
+       [*] Enable ulog
+           [*] Enable ISR log.
+```
+
+## 3.2 获取软件包
+使用 lora-radio-driver 软件包，需要在 RT-Thread 的包管理中选中它，具体路径如下：
+```c
+RT-Thread online packages --->
+    peripheral libraries and drivers --->
+        [*] lora_radio_driver: lora chipset(sx126x\sx127x.)driver. --->
+            Select LoRa Radio Object Type (LoRa Radio Single-Instance)
+                (lora-radio0)Setup LoRa Radio Device Name       
+                (spi3)  Setup LoRa Radio Spi Name (Define BSP_USING_SPIx in [Target Platform]\Board\Kconfig)
+                        Select LoRa Chip Type (LoRa Transceiver [SX126X])  --->
+                        Select Supported LoRa Module [SX126X]  --->
+                [ ]     Enable LoRa Radio Debug
+                        Select LoRa Radio Driver Sample --->  
+                    Version (latest)  --->
+```
+
+1. Select LoRa Chip \ LoRa Module
+   1. "Setup LoRa Radio Device Name"
+      1. 设置LoRa Radio设备名称，缺省为"lora-radio0"
+   2. "Setup LoRa Radio Spi Name"
+      1. 设置LoRa Radio Spi名称
+      1. 若在 [Target Platform]\Board\Kconfig提前设定好所使用的BSP_USING_SPIx，则会自动配置
+   3. "Select LoRa Radio Single-Instance"
+      1. 选择为单实例对象，当前只支持单个lora设备
+   4. "Select LoRa Chip Type"
+      1. 选择实际使用的LoRa芯片类型
+         - 当前支持 SX126X、SX127x Transceiver
+   5. "Select Supported LoRa Module"
+      1. 选择lora模块，根据实际使用的MCU硬件平台与lora模块，配置关联的GPIO引脚等功能选项
+         1. 设定LoRa模块的GPIO口（比如 RESET、NSS、BUSY、DIO1、TXE、RXE...）
+            - " Select LoRa Chip GPIO by Pin Number  "
+               - 支持使用引脚号来定义GPIO，比如 输入 10 代表 A10 
+            - "Select LoRa Chip GPIO by Pin Name"
+               - 支持使用引脚名来定义GPIO，比如 输入 A10 代表引脚GPIOA的PIN10脚 (STM32)
+2. Select LoRa Radio Driver Sample
+   1. 根据实际情况，可选择测试示例
+## 3.3 新增LoRa模块
+在 lora-radio-driver\ports\lora-module文件下，参考已有模板，根据实际需要增加新的mcu平台适配文件、新的lora模块驱动文件xxxx-board.c
+
+
+# 4 使用示例
+
+## 4.1 硬件测试平台
+当前所使用的硬件测试平台如下所示
+| 序号 | 硬件平台 | MCU | LoRa模块 | 主要用户接口 |
+| --- | --- | --- | --- | --- |
+| 1 | LSD4RF-TEST2002  | STM32L476VG | [LSD4RF-2R717N40](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)<br />[ ( SX1268 )](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87) | <br />- 用户接口定义<br />   - VCC  - 3.3V<br />   - GND<br />   - SCK    - PC10 (SPI3)<br />   - MISO  - PC11 (SPI3)<br />   - MOSI  - PC12 (SPI3)<br />   - NSS    - PA15<br />   - RESET - PA7<br />   - DIO0  - PB1<br />   - BUSY - PB2<br />   - RFSW1 - PB0<br />   - RFSW2 - PC5<br />- 射频开关TX trace<br />   - TX: RFSW1 = 1 , RFSW2 = 0<br />   - TX: RFSW1 = 0 , RFSW2 = 1<br /> |
+| 2 | LSD4RF-TEST2002  | STM32L476VG | [LSD4RF-2F717N30](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)<br />[ ( SX1278 )](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87) | <br />- 用户接口定义<br />   - VCC   - 3.3V<br />   - GND<br />   - SCK    - PC10 (SPI3)<br />   - MISO  - PC11 (SPI3)<br />   - MOSI  - PC12 (SPI3)<br />   - NSS    - PB6<br />   - RESET - PA7<br />   - DIO0  - PB1<br />   - DIO1  - PC4<br />   - DIO2  - PB2<br />   - DIO3  - NC<br />   - DIO4  - NC<br />   - RFSW1 - PB0<br />   - RFSW2 - PC5<br />- 射频开关TX trace<br />   - TX: RFSW1 = 1 , RFSW2 = 0<br />   - TX: RFSW1 = 0 , RFSW2 = 1<br /> |
+| 3 | Nucleo-L476RG | STM32L476RG | [Ra-01](http://wiki.ai-thinker.com/lora/man)<br />(RT-thread LoRa Adruino扩展板V1) | <br />- 用户接口定义<br />   - VCC    - 3.3V<br />   - GND<br />   - SCK    - PA5(SPI1)<br />   - MISO  - PA6(SPI1)<br />   - MOSI  - PA7(SPI1)<br />   - NSS    - PB6<br />   - RESET - PC7<br />   - DIO0  - PA9<br />   - DIO1  - PA8<br /> |
+| 4 | ART-Pi  | STM32H750XB | [LSD4RF-2R717N40](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)<br />[ ( SX1268 )](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87) | <br />- 用户接口定义<br />   - VCC  - 3.3V<br />   - GND<br />   - SCK    - PI1 (SPI2)<br />   - MISO  - PI2 (SPI2)<br />   - MOSI  - PI3 (SPI2)<br />   - NSS    - PI0<br />   - RESET - PA15<br />   - DIO1  - PG7<br />   - BUSY - PH15<br />   - RFSW1 - PH14<br />   - RFSW2 - PH13<br />- 射频开关TX trace<br />   - TX: RFSW1 = 1 , RFSW2 = 0<br />   - TX: RFSW1 = 0 , RFSW2 = 1<br /> |
+| 5 | ART-Pi  | STM32H750XB | [LSD4RF-2R822N30](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87)<br />[ ( SX1262 )](http://bbs.lierda.com/forum.php?mod=viewthread&tid=87) | |
+## 4.2 Shell测试命令
+若使能 [* ] LoRa Radio Test Shell，则可以通过shell（finish）命令直接进行LoRa相关测试
+```c
+[*] Enable LoRa Radio Test Shell                                                                                              │ │
+     Select the RF frequency (Region CN470)  --->                                                                            │ │
+     Select RF Modem (Modem LoRa)  --->
+```
+![image.png](https://github.com/Forest-Rain/lora-radio-driver/raw/master/doc/pics/02_lora-radio-test-shell-cmdlist.png)
+
+| 序号 | finish命令 | 说明 |
+| --- | --- | --- |
+| 1 | lora probe | 测试lora设备(SPI)访问是否正常 |
+| 2 | lora cw <para1> <para2> | \<para1\>:频点，单位Hz<br>\<para2\>:功率，单位dBm|
+| 3 | lora ping <para1> <para2> | \<para1\> : 主机\从机<br>-m 主机<br>-s 从机<br> \<para2\>: 发送数据包个数 |
+| 4 | lora rx  | 接收数据包，同时以16进制格式与ASCII码显示数据内容 |
+
+![image.png](https://github.com/Forest-Rain/lora-radio-driver/raw/master/doc/pics/03_lora-ping_SX1278-SX1268-TRX-test.png)
+lora ping 双向通信测试示例(SX1278 <-> SX1268)
+![image.png](https://github.com/Forest-Rain/lora-radio-driver/raw/master/doc/pics/04_lora-rx_sniffer-test.png)
+lora rx 单向接收(监听)lora数据包测试示例 (SX1278 <- 或-> SX1268)
+
+## 4.3 应用层调用说明
+用户层调用可以参考如下步骤
+
+1. 定义射频DIO中断服务回调函数
+```c
+
+/*!
+ * \brief Function to be executed on Radio Tx Done event
+ */
+void OnTxDone( void );
+
+/*!
+ * \brief Function to be executed on Radio Rx Done event
+ */
+void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
+
+/*!
+ * \brief Function executed on Radio Tx Timeout event
+ */
+void OnTxTimeout( void );
+
+/*!
+ * \brief Function executed on Radio Rx Timeout event
+ */
+void OnRxTimeout( void );
+
+/*!
+ * \brief Function executed on Radio Rx Error event
+ */
+void OnRxError( void );
+
+```
+2. 调用lora-radio初始化
+```c
+void main(void)
+{
+    // Radio initialization
+    RadioEvents.TxDone = OnTxDone;
+    RadioEvents.RxDone = OnRxDone;
+    RadioEvents.TxTimeout = OnTxTimeout;
+    RadioEvents.RxTimeout = OnRxTimeout;
+    RadioEvents.RxError = OnRxError;
+
+    if(Radio.Init(&RadioEvents))
+    {
+        Radio.SetPublicNetwork( false );
+        lora_chip_initialized = true;
+    }
+    //.....
+}
+```
+
+3. 配置射频通信参数
+```c
+{
+    Radio.SetChannel( lora_radio_test_paras.frequency );
+
+    if( lora_radio_test_paras.modem == MODEM_LORA )
+    {
+        Radio.SetTxConfig( MODEM_LORA, lora_radio_test_paras.txpower, 0, lora_radio_test_paras.bw,
+                          lora_radio_test_paras.sf, lora_radio_test_paras.cr,
+                          LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE,
+                          true, 0, 0, LORA_IQ_INVERSION_ON_DISABLE, 3000 );
+
+        Radio.SetRxConfig( MODEM_LORA, lora_radio_test_paras.bw, lora_radio_test_paras.sf,
+                          lora_radio_test_paras.cr, 0, LORA_PREAMBLE_LENGTH,
+                          LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE,
+                          0, true, 0, 0, LORA_IQ_INVERSION_ON_DISABLE, true );
+    }
+}
+```
+
+4. 数据发送
+```c
+Radio.Send( Buffer, len );
+```
+5. 数据接收
+```c
+void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr )
+{
+    Radio.Sleep( );
+    BufferSize = size;
+    rt_memcpy( Buffer, payload, BufferSize );
+    rssi_value = rssi;
+    snr_value = snr;
+    // .....
+}
+```
+# 5 版本更新历史
+
+- V1.0.0 版本 2020-06-20
+   - 基于lorawan4.4.2 release版本的radio
+   - 主体功能实现基于STM32平台
+      - 支持SX126x、SX127x系列芯片
+         - 测试LoRa芯片支持LSD4RF-2R717N40(SX1268)、SX1278、ASR6500S @ [**zyk6271**](https://github.com/zyk6271)
+   - 支持基于RT-Thread内核rt_timer的lora-radio-timer接口@ [**AnswerInTheWind** ](https://github.com/AnswerInTheWind)
+   - 优化日志换行功能、sx126x.c的multi-rtimer.h包含问题@[**zyk6271**](https://github.com/zyk6271)
+- V1.1.0 版本 2020-08-30
+   - 完善用户使用指南
+   - .lora-radio-driver软件包
+      - 新增日志输出选择 lora-radio-debug.h，可以按需开启调试日志，也可以用于适配不同日志输出方式
+      - 新增rtos适配选择 lora-radio-rtos-config.h，便于未来适配RT-Thread-Nano、不同的RTOS平台
+      - lora-radio(sx126x\sx127x)
+         - 同步更新到lorawan4.4.4 release版本的radio
+            - sx126x更新 SX126xSetLoRaSymbNumTimeout（同步到loramac-node-master）
+            - sx126x更新 RadioRandom 与 SX126xGetRandom
+            - 更新 RadioIrqProcess
+            - 更新RadioTimeOnAir
+         - RadioIrqProcess 增加 临界区保护，优先完成RF中断回调服务函数，防止出现硬件异常
+      - 调整lora-radio-driver软件包架构，便于未来适配不同的MCU平台
+         - port目录下新增mcu平台适配层，如stm32_adapter
+   - lora-radio-test-shell
+      - 修复 PHY CRC Error后，没有重新进入接收问题
+      - lora ping命令
+         - 新增发送空口数据包的TOA时间显示
+         - 新增主机侧接收到数据包后，seqno显示
+   - [Kconfig](https://github.com/Forest-Rain/packages/blob/master/peripherals/lora_radio_driver)
+      - 更新[lora-radio-driver\Kconfig](https://github.com/Forest-Rain/packages) 软件包配置文件
+         - 区分单实例(单lora模块)与多实例（多lora模块）情况，目前支持单实例
+         - 移除了Kconfig中对BSP_USING_SPIx的直接定义，BSP_USING_SPIx定义调整到[Target Platform]\Board\Kconfig)
+         - 重命名宏定义REGION_X为PHY_REGION_X(如REGION_CN470 -> PHY_REGION_CN470)，以便与LoRaWAN协议栈中缺省REGION_X共存
+- V1.1.2 版本 2020-10-12
+   - 修复Ra-01未同步与v1.1.1更新导致的问题
+   - 优化 drv_gpio.h使用，兼容RT-Thread Studio
+   - 优化 lora-radio-test-shell.c 功能
+     - 新增接收超时时间设置
+ - V1.2 版本 2020-10-14
+   - 新增硬件测试平台
+      - ART-Pi+LSD4RF-2F717N30(SX1268)模块平台 (470~510MHz频段)
+      - ART-Pi+LSD4RF-2R717N40(SX1268)模块平台 (470~510MHz频段)
+      - ART-Pi+LSD4RF-2R822N30(SX1262)模块平台 (868/915MHz频段)
+# 6 问题和建议
+如果有什么问题或者建议欢迎提交 [Issue](https://github.com/Forest-Rain/lora-radio-driver/issues) 进行讨论。

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/SConscript

@@ -0,0 +1,27 @@
+from building import *
+
+src   = []
+cwd   = GetCurrentDir()
+include_path = [cwd]
+include_path += [cwd+'/include']
+
+# add lora radio driver.
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X'):
+    src = Split('''
+    sx126x/lora-radio-sx126x.c
+    sx126x/lora-spi-sx126x.c
+    sx126x/sx126x.c
+    ''')
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_CHIP_SX127X'):
+    src = Split('''
+    sx127x/lora-radio-sx127x.c
+    sx127x/lora-spi-sx127x.c
+    sx127x/sx127x.c
+    ''')
+
+src += ['common/lora-radio-timer.c']
+include_path += [cwd+'/common']
+
+group = DefineGroup('lora-radio-driver', src, depend = ['PKG_USING_LORA_RADIO_DRIVER'], CPPPATH = include_path)
+
+Return('group')

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/common/lora-radio-timer.c

@@ -0,0 +1,64 @@
+/*!
+ * \file      lora-radio-timer.c
+ *
+ * \brief     lora-radio timer 
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    DerekChen
+ */
+
+#include "lora-radio-rtos-config.h"
+#include <stdint.h>
+#include "lora-radio-timer.h"
+
+#if defined ( LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD ) || defined ( LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO )
+#ifndef PKG_USING_MULTI_RTIMER
+
+void rtick_timer_init( rtick_timer_event_t *obj, void ( *callback )( void ) )
+{
+    int count = 0;
+    
+    char name[RT_NAME_MAX];
+    rt_snprintf(name,8,"rtk_%d",count++);
+
+    rt_timer_init(&(obj->timer),name,(void (*)(void*))callback,RT_NULL,1000,RT_TIMER_FLAG_ONE_SHOT|RT_TIMER_FLAG_SOFT_TIMER);
+}
+
+void rtick_timer_start( rtick_timer_event_t *obj )
+{
+    rt_timer_start(&(obj->timer));
+}
+
+void rtick_timer_stop( rtick_timer_event_t *obj )
+{
+    rt_timer_stop(&(obj->timer));
+}
+
+void rtick_timer_reset( rtick_timer_event_t *obj )
+{
+    rtick_timer_stop(obj);
+    rtick_timer_start(obj);
+}
+
+void rtick_timer_set_value( rtick_timer_event_t *obj, uint32_t value )
+{
+    uint32_t tick = rt_tick_from_millisecond(value);
+    rt_timer_control(&(obj->timer),RT_TIMER_CTRL_SET_TIME,&tick);
+}
+
+TimerTime_t rtick_timer_get_current_time( void )
+{
+    uint32_t now = rt_tick_get();
+    return  now;
+}
+
+TimerTime_t rtick_timer_get_elapsed_time( TimerTime_t past )
+{
+    return rt_tick_get() - past;
+}
+
+#endif
+
+#endif // End Of  ( LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD ) || defined ( LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO )
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/common/lora-radio-timer.h

@@ -0,0 +1,57 @@
+#ifndef __LORA_RADIO_TIMER_H__
+#define __LORA_RADIO_TIMER_H__
+
+#include <rtconfig.h>
+#include <rtthread.h>
+#include <stdint.h>
+
+#ifdef PKG_USING_MULTI_RTIMER
+
+#include "multi_rtimer.h"
+#include "hw_rtc_stm32.h"
+
+#else
+
+#define TimerInit            rtick_timer_init
+#define TimerStart           rtick_timer_start
+#define TimerStop            rtick_timer_stop   
+#define TimerReset           rtick_timer_reset
+#define TimerSetValue        rtick_timer_set_value
+#define TimerGetCurrentTime  rtick_timer_get_current_time
+#define TimerGetElapsedTime  rtick_timer_get_elapsed_time
+#define TimerEvent_t         rtick_timer_event_t
+
+/*!
+ * \brief Timer object description
+ */
+typedef struct TimerEvent_s
+{
+    struct rt_timer timer; 
+}rtick_timer_event_t;
+
+/*!
+ * \brief Timer time variable definition
+ */
+#ifndef TimerTime_t
+typedef uint32_t TimerTime_t;
+#define TIMERTIME_T_MAX                             ( ( uint32_t )~0 )
+
+void rtick_timer_init( rtick_timer_event_t *obj, void ( *callback )( void ) );
+
+void rtick_timer_start( rtick_timer_event_t *obj );
+
+void rtick_timer_stop( rtick_timer_event_t *obj );
+
+void rtick_timer_reset( rtick_timer_event_t *obj );
+
+void rtick_timer_set_value( rtick_timer_event_t *obj, uint32_t value );
+
+TimerTime_t rtick_timer_get_current_time( void );
+
+TimerTime_t rtick_timer_get_elapsed_time( TimerTime_t past );
+
+#endif
+
+#endif
+
+#endif

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/include/lora-radio-debug.h

@@ -0,0 +1,87 @@
+/*!
+ * \file      lora-radio-debug.h
+ *
+ * \brief     control all LoRa Radio Driver debug features.
+ *
+ * \copyright SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+ 
+#ifndef __LORA_RADIO_DEBUG_H__
+#define __LORA_RADIO_DEBUG_H__
+
+#if ( defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD ) || ( defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO )
+#ifdef RT_USING_ULOG
+#include <rtdbg.h>
+#include <ulog.h> 
+#else
+
+#endif
+
+#endif
+
+
+/* Using this macro to control all LoRa Radio Driver debug features. */
+#ifdef LORA_RADIO_DRIVER_USING_LORA_RADIO_DEBUG
+
+/* Turn on some of these (set to non-zero) to debug LoRa Radio */
+
+/* application */
+#ifndef LR_DBG_APP
+#define LR_DBG_APP                          0
+#endif
+
+/* API interface */
+#ifndef LR_DBG_INTERFACE
+#define LR_DBG_INTERFACE                    0
+#endif
+
+/*lora chip driver, eg: sx126x.c\sx27x.c*/
+#ifndef LR_DBG_CHIP
+#define LR_DBG_CHIP                         0
+#endif
+
+/* spi driver ,eg: lora-spi.c*/
+#ifndef LR_DBG_SPI
+#define LR_DBG_SPI                          0
+#endif
+
+#if ( defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD ) || ( defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO )
+
+#if defined RT_USING_ULOG
+#define LORA_RADIO_DEBUG_LOG(type, level, ...)                                \
+do                                                                            \
+{                                                                             \
+    if (type)                                                                 \
+    {                                                                         \
+        ulog_output(level, LOG_TAG, RT_TRUE, __VA_ARGS__);                    \
+    }                                                                         \
+}                                                                             \
+while (0)
+
+#else
+
+#define LORA_RADIO_DEBUG_LOG(type, level, ...)                                \
+do                                                                            \
+{                                                                             \
+    if (type)                                                                 \
+    {                                                                         \
+        rt_kprintf(__VA_ARGS__);                                              \
+        rt_kprintf("\r\n");                                                   \
+    }                                                                         \
+}                                                                             \
+while (0)
+#endif
+
+#endif
+
+
+
+#else /* LORA_RADIO_DEBUG */
+
+#define LORA_RADIO_DEBUG_LOG(type, level, ...)
+
+#endif /* LORA_RADIO_DEBUG */
+
+#endif /* __LORA_RADIO_DEBUG_H__ */

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/include/lora-radio-rtos-config.h

@@ -0,0 +1,41 @@
+/*!
+ * \file      lora-radio-rtos-config.h
+ *
+ * \brief     adapter to different RTOS implementation
+ *
+ * \copyright SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+ 
+#ifndef __LORA_RADIO_RTOS_CONFIG_H_
+#define __LORA_RADIO_RTOS_CONFIG_H_
+
+#define LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+//#define LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+#elif defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO
+#else
+    #error "Please Choose your RTOS setup!"
+#endif
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "drv_spi.h"
+
+#define LOG_LVL_ASSERT                 0
+#define LOG_LVL_ERROR                  3
+#define LOG_LVL_WARNING                4
+#define LOG_LVL_INFO                   6
+#define LOG_LVL_DBG                    7
+
+#elif defined LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD_NANO
+#include <rtthread.h>
+
+#endif
+
+
+
+#endif // end of __LORA_RADIO_RTOS_CONFIG_H_

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/include/lora-radio.h

@@ -0,0 +1,428 @@
+/*!
+ * \file      lora-radio.h
+ *
+ * \brief     LoRa Radio driver API definition
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+  *
+ * \author    forest-rain
+ */
+#ifndef __LORA_RADIO_H__
+#define __LORA_RADIO_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/*!
+ * Begins critical section
+ */
+#define LORA_RADIO_CRITICAL_SECTION_BEGIN( )  register rt_base_t level; level = rt_hw_interrupt_disable()
+
+/*!
+ * Ends critical section
+ */
+#define LORA_RADIO_CRITICAL_SECTION_END( ) rt_hw_interrupt_enable(level)
+
+/*!
+ * Radio driver supported modems
+ */
+typedef enum
+{
+    MODEM_FSK = 0,
+    MODEM_LORA,
+}RadioModems_t;
+
+/*!
+ * Radio driver internal state machine states definition
+ */
+typedef enum
+{
+    RF_IDLE = 0,   //!< The radio is idle
+    RF_RX_RUNNING, //!< The radio is in reception state
+    RF_TX_RUNNING, //!< The radio is in transmission state
+    RF_CAD,        //!< The radio is doing channel activity detection
+}RadioState_t;
+
+/*!
+ * Radio Dio Irq event definition
+ */
+typedef enum
+{
+    EV_LORA_RADIO_IRQ0_FIRED    =   0x0001,
+    EV_LORA_RADIO_IRQ1_FIRED    =   0x0002,
+    EV_LORA_RADIO_IRQ2_FIRED    =   0x0004,
+    EV_LORA_RADIO_IRQ3_FIRED    =   0x0008,
+    EV_LORA_RADIO_IRQ4_FIRED    =   0x0010,
+    EV_LORA_RADIO_IRQ5_FIRED    =   0x0020,
+}RadioDioIrqEvent_t;
+
+/*!
+ * \brief Radio driver callback functions
+ */
+typedef struct
+{
+    /*!
+     * \brief  Tx Done callback prototype.
+     */
+    void    ( *TxDone )( void );
+    /*!
+     * \brief  Tx Timeout callback prototype.
+     */
+    void    ( *TxTimeout )( void );
+    /*!
+     * \brief Rx Done callback prototype.
+     *
+     * \param [IN] payload Received buffer pointer
+     * \param [IN] size    Received buffer size
+     * \param [IN] rssi    RSSI value computed while receiving the frame [dBm]
+     * \param [IN] snr     SNR value computed while receiving the frame [dB]
+     *                     FSK : N/A ( set to 0 )
+     *                     LoRa: SNR value in dB
+     */
+    void    ( *RxDone )( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
+    /*!
+     * \brief  Rx Timeout callback prototype.
+     */
+    void    ( *RxTimeout )( void );
+    /*!
+     * \brief Rx Error callback prototype.
+     */
+    void    ( *RxError )( void );
+    /*!
+     * \brief  FHSS Change Channel callback prototype.
+     *
+     * \param [IN] currentChannel   Index number of the current channel
+     */
+    void ( *FhssChangeChannel )( uint8_t currentChannel );
+
+    /*!
+     * \brief CAD Done callback prototype.
+     *
+     * \param [IN] channelDetected    Channel Activity detected during the CAD
+     */
+    void ( *CadDone ) ( bool channelActivityDetected );
+}RadioEvents_t;
+
+/*!
+ * \brief Radio driver definition
+ */
+struct Radio_s
+{
+    /*!
+     * \brief Initializes the radio
+     *
+     * \param [IN] events Structure containing the driver callback functions
+     */
+    bool    ( *Init )( RadioEvents_t *events );
+    /*!
+     * Return current radio status
+     *
+     * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+     */
+    RadioState_t ( *GetStatus )( void );
+    /*!
+     * \brief Configures the radio with the given modem
+     *
+     * \param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+     */
+    void    ( *SetModem )( RadioModems_t modem );
+    /*!
+     * \brief Sets the channel frequency
+     *
+     * \param [IN] freq         Channel RF frequency
+     */
+    void    ( *SetChannel )( uint32_t freq );
+    /*!
+     * \brief Checks if the channel is free for the given time
+     *
+     * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+     * \param [IN] freq       Channel RF frequency
+     * \param [IN] rssiThresh RSSI threshold
+     * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured
+     *
+     * \retval isFree         [true: Channel is free, false: Channel is not free]
+     */
+    bool    ( *IsChannelFree )( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime );
+    /*!
+     * \brief Generates a 32 bits random value based on the RSSI readings
+     *
+     * \remark This function sets the radio in LoRa modem mode and disables
+     *         all interrupts.
+     *         After calling this function either Radio.SetRxConfig or
+     *         Radio.SetTxConfig functions must be called.
+     *
+     * \retval randomValue    32 bits random value
+     */
+    uint32_t ( *Random )( void );
+    /*!
+     * \brief Sets the reception parameters
+     *
+     * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+     * \param [IN] bandwidth    Sets the bandwidth
+     *                          FSK : >= 2600 and <= 250000 Hz
+     *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+     *                                 2: 500 kHz, 3: Reserved]
+     * \param [IN] datarate     Sets the Datarate
+     *                          FSK : 600..300000 bits/s
+     *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+     *                                10: 1024, 11: 2048, 12: 4096  chips]
+     * \param [IN] coderate     Sets the coding rate (LoRa only)
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+     * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only)
+     *                          FSK : >= 2600 and <= 250000 Hz
+     *                          LoRa: N/A ( set to 0 )
+     * \param [IN] preambleLen  Sets the Preamble length
+     *                          FSK : Number of bytes
+     *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+     * \param [IN] symbTimeout  Sets the RxSingle timeout value
+     *                          FSK : timeout in number of bytes
+     *                          LoRa: timeout in symbols
+     * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+     * \param [IN] payloadLen   Sets payload length when fixed length is used
+     * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+     * \param [IN] freqHopOn    Enables disables the intra-packet frequency hopping
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [0: OFF, 1: ON]
+     * \param [IN] hopPeriod    Number of symbols between each hop
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: Number of symbols
+     * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [0: not inverted, 1: inverted]
+     * \param [IN] rxContinuous Sets the reception in continuous mode
+     *                          [false: single mode, true: continuous mode]
+     */
+    void    ( *SetRxConfig )( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint32_t bandwidthAfc, uint16_t preambleLen,
+                              uint16_t symbTimeout, bool fixLen,
+                              uint8_t payloadLen,
+                              bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+                              bool iqInverted, bool rxContinuous );
+    /*!
+     * \brief Sets the transmission parameters
+     *
+     * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+     * \param [IN] power        Sets the output power [dBm]
+     * \param [IN] fdev         Sets the frequency deviation (FSK only)
+     *                          FSK : [Hz]
+     *                          LoRa: 0
+     * \param [IN] bandwidth    Sets the bandwidth (LoRa only)
+     *                          FSK : 0
+     *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+     *                                 2: 500 kHz, 3: Reserved]
+     * \param [IN] datarate     Sets the Datarate
+     *                          FSK : 600..300000 bits/s
+     *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+     *                                10: 1024, 11: 2048, 12: 4096  chips]
+     * \param [IN] coderate     Sets the coding rate (LoRa only)
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+     * \param [IN] preambleLen  Sets the preamble length
+     *                          FSK : Number of bytes
+     *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+     * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+     * \param [IN] crcOn        Enables disables the CRC [0: OFF, 1: ON]
+     * \param [IN] freqHopOn    Enables disables the intra-packet frequency hopping
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [0: OFF, 1: ON]
+     * \param [IN] hopPeriod    Number of symbols between each hop
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: Number of symbols
+     * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [0: not inverted, 1: inverted]
+     * \param [IN] timeout      Transmission timeout [ms]
+     */
+    void    ( *SetTxConfig )( RadioModems_t modem, int8_t power, uint32_t fdev,
+                              uint32_t bandwidth, uint32_t datarate,
+                              uint8_t coderate, uint16_t preambleLen,
+                              bool fixLen, bool crcOn, bool freqHopOn,
+                              uint8_t hopPeriod, bool iqInverted, uint32_t timeout );
+    /*!
+     * \brief Checks if the given RF frequency is supported by the hardware
+     *
+     * \param [IN] frequency RF frequency to be checked
+     * \retval isSupported [true: supported, false: unsupported]
+     */
+    bool    ( *CheckRfFrequency )( uint32_t frequency );
+    /*!
+     * \brief Computes the packet time on air in ms for the given payload
+     *
+     * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
+     *
+     * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+     * \param [IN] bandwidth    Sets the bandwidth
+     *                          FSK : >= 2600 and <= 250000 Hz
+     *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+     *                                 2: 500 kHz, 3: Reserved]
+     * \param [IN] datarate     Sets the Datarate
+     *                          FSK : 600..300000 bits/s
+     *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+     *                                10: 1024, 11: 2048, 12: 4096  chips]
+     * \param [IN] coderate     Sets the coding rate (LoRa only)
+     *                          FSK : N/A ( set to 0 )
+     *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+     * \param [IN] preambleLen  Sets the Preamble length
+     *                          FSK : Number of bytes
+     *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+     * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+     * \param [IN] payloadLen   Sets payload length when fixed length is used
+     * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+     *
+     * \retval airTime        Computed airTime (ms) for the given packet payload length
+     */
+    uint32_t  ( *TimeOnAir )( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn );
+
+    /*!
+     * \brief Sends the buffer of size. Prepares the packet to be sent and sets
+     *        the radio in transmission
+     *
+     * \param [IN]: buffer     Buffer pointer
+     * \param [IN]: size       Buffer size
+     */
+    void    ( *Send )( uint8_t *buffer, uint8_t size );
+    /*!
+     * \brief Sets the radio in sleep mode
+     */
+    void    ( *Sleep )( void );
+    /*!
+     * \brief Sets the radio in standby mode
+     */
+    void    ( *Standby )( void );
+    /*!
+     * \brief Sets the radio in reception mode for the given time
+     * \param [IN] timeout Reception timeout [ms]
+     *                     [0: continuous, others timeout]
+     */
+    void    ( *Rx )( uint32_t timeout );
+    /*!
+     * \brief Start a Channel Activity Detection
+     */
+    void    ( *StartCad )( void );
+    /*!
+     * \brief Sets the radio in continuous wave transmission mode
+     *
+     * \param [IN]: freq       Channel RF frequency
+     * \param [IN]: power      Sets the output power [dBm]
+     * \param [IN]: time       Transmission mode timeout [s]
+     */
+    void    ( *SetTxContinuousWave )( uint32_t freq, int8_t power, uint16_t time );
+    /*!
+     * \brief Reads the current RSSI value
+     *
+     * \retval rssiValue Current RSSI value in [dBm]
+     */
+    int16_t ( *Rssi )( RadioModems_t modem );
+    /*!
+     * \brief Writes the radio register at the specified address
+     *
+     * \param [IN]: addr Register address
+     * \param [IN]: data New register value
+     */
+    void    ( *Write )( uint16_t addr, uint8_t data );
+    /*!
+     * \brief Reads the radio register at the specified address
+     *
+     * \param [IN]: addr Register address
+     * \retval data Register value
+     */
+    uint8_t ( *Read )( uint16_t addr );
+    /*!
+     * \brief Writes multiple radio registers starting at address
+     *
+     * \param [IN] addr   First Radio register address
+     * \param [IN] buffer Buffer containing the new register's values
+     * \param [IN] size   Number of registers to be written
+     */
+    //void    ( *WriteBuffer )( uint16_t addr, uint8_t *buffer, uint8_t size );
+    /*!
+     * \brief Reads multiple radio registers starting at address
+     *
+     * \param [IN] addr First Radio register address
+     * \param [OUT] buffer Buffer where to copy the registers data
+     * \param [IN] size Number of registers to be read
+     */
+    //void    ( *ReadBuffer )( uint16_t addr, uint8_t *buffer, uint8_t size );
+    /*!
+     * \brief Sets the maximum payload length.
+     *
+     * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+     * \param [IN] max        Maximum payload length in bytes
+     */
+    void    ( *SetMaxPayloadLength )( RadioModems_t modem, uint8_t max );
+    /*!
+     * \brief Sets the network to public or private. Updates the sync byte.
+     *
+     * \remark Applies to LoRa modem only
+     *
+     * \param [IN] enable if true, it enables a public network
+     */
+    void    ( *SetPublicNetwork )( bool enable );
+    /*!
+     * \brief Gets the time required for the board plus radio to get out of sleep.[ms]
+     *
+     * \retval time Radio plus board wakeup time in ms.
+     */
+    uint32_t  ( *GetWakeupTime )( void );
+    /*!
+     * \brief Process radio irq
+     */
+    void ( *IrqProcess )( void );
+    /*!
+     * \brief radio spi check
+     */
+    uint8_t ( *Check )( void );
+    /*
+     * The next functions are available only on SX126x radios.
+     */
+    /*!
+     * \brief Sets the radio in reception mode with Max LNA gain for the given time
+     *
+     * \remark Available on SX126x radios only.
+     *
+     * \param [IN] timeout Reception timeout [ms]
+     *                     [0: continuous, others timeout]
+     */
+    void    ( *RxBoosted )( uint32_t timeout );
+    /*!
+     * \brief Sets the Rx duty cycle management parameters
+     *
+     * \remark Available on SX126x radios only.
+     *
+     * \param [in]  rxTime        Structure describing reception timeout value
+     * \param [in]  sleepTime     Structure describing sleep timeout value
+     */
+    void ( *SetRxDutyCycle ) ( uint32_t rxTime, uint32_t sleepTime );
+};
+
+/*!
+ * \brief Radio driver
+ *
+ * \remark This variable is defined and initialized in the specific radio
+ *         board implementation
+ */
+extern const struct Radio_s Radio;
+
+
+
+#endif // __RADIO_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx126x/lora-radio-sx126x.c

@@ -0,0 +1,1469 @@
+/*!
+ * \file      lora-radio-sx126x.c
+ *
+ * \brief     lora radio driver for sx126x API definition
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include <string.h>
+#include "lora-radio-timer.h"
+#include "lora-radio.h"
+#include "lora-spi-sx126x.h"
+#include "sx126x-board.h"
+
+#define LOG_TAG "PHY.LoRa.SX126X"
+#define LOG_LEVEL  LOG_LVL_DBG
+#include "lora-radio-debug.h"
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+
+#define EV_LORA_RADIO_DIO_IRQ_FIRED       0x0001
+
+static struct rt_event lora_radio_event;
+static struct rt_thread lora_radio_thread;
+static rt_uint8_t rt_lora_radio_thread_stack[4096];
+#endif
+
+/*!
+ * \brief Initializes the radio
+ *
+ * \param [IN] events Structure containing the driver callback functions
+ */
+bool RadioInit( RadioEvents_t *events );
+
+/*!
+ * Return current radio status
+ *
+ * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+ */
+RadioState_t RadioGetStatus( void );
+
+/*!
+ * \brief Configures the radio with the given modem
+ *
+ * \param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+ */
+void RadioSetModem( RadioModems_t modem );
+
+/*!
+ * \brief Sets the channel frequency
+ *
+ * \param [IN] freq         Channel RF frequency
+ */
+void RadioSetChannel( uint32_t freq );
+
+/*!
+ * \brief Checks if the channel is free for the given time
+ *
+ * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] freq       Channel RF frequency
+ * \param [IN] rssiThresh RSSI threshold
+ * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured
+ *
+ * \retval isFree         [true: Channel is free, false: Channel is not free]
+ */
+bool RadioIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime );
+
+/*!
+ * \brief Generates a 32 bits random value based on the RSSI readings
+ *
+ * \remark This function sets the radio in LoRa modem mode and disables
+ *         all interrupts.
+ *         After calling this function either Radio.SetRxConfig or
+ *         Radio.SetTxConfig functions must be called.
+ *
+ * \retval randomValue    32 bits random value
+ */
+uint32_t RadioRandom( void );
+
+/*!
+ * \brief Sets the reception parameters
+ *
+ * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] bandwidth    Sets the bandwidth
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only)
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: N/A ( set to 0 )
+ * \param [IN] preambleLen  Sets the Preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] symbTimeout  Sets the RxSingle timeout value
+ *                          FSK : timeout in number of bytes
+ *                          LoRa: timeout in symbols
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] payloadLen   Sets payload length when fixed length is used
+ * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+ * \param [IN] FreqHopOn    Enables disables the intra-packet frequency hopping
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: OFF, 1: ON]
+ * \param [IN] HopPeriod    Number of symbols between each hop
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: Number of symbols
+ * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: not inverted, 1: inverted]
+ * \param [IN] rxContinuous Sets the reception in continuous mode
+ *                          [false: single mode, true: continuous mode]
+ */
+void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth,
+                          uint32_t datarate, uint8_t coderate,
+                          uint32_t bandwidthAfc, uint16_t preambleLen,
+                          uint16_t symbTimeout, bool fixLen,
+                          uint8_t payloadLen,
+                          bool crcOn, bool FreqHopOn, uint8_t HopPeriod,
+                          bool iqInverted, bool rxContinuous );
+
+/*!
+ * \brief Sets the transmission parameters
+ *
+ * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] power        Sets the output power [dBm]
+ * \param [IN] fdev         Sets the frequency deviation (FSK only)
+ *                          FSK : [Hz]
+ *                          LoRa: 0
+ * \param [IN] bandwidth    Sets the bandwidth (LoRa only)
+ *                          FSK : 0
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] preambleLen  Sets the preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] crcOn        Enables disables the CRC [0: OFF, 1: ON]
+ * \param [IN] FreqHopOn    Enables disables the intra-packet frequency hopping
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: OFF, 1: ON]
+ * \param [IN] HopPeriod    Number of symbols between each hop
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: Number of symbols
+ * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: not inverted, 1: inverted]
+ * \param [IN] timeout      Transmission timeout [ms]
+ */
+void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+                          uint32_t bandwidth, uint32_t datarate,
+                          uint8_t coderate, uint16_t preambleLen,
+                          bool fixLen, bool crcOn, bool FreqHopOn,
+                          uint8_t HopPeriod, bool iqInverted, uint32_t timeout );
+
+/*!
+ * \brief Checks if the given RF frequency is supported by the hardware
+ *
+ * \param [IN] frequency RF frequency to be checked
+ * \retval isSupported [true: supported, false: unsupported]
+ */
+bool RadioCheckRfFrequency( uint32_t frequency );
+
+/*!
+ * \brief Computes the packet time on air in ms for the given payload
+ *
+ * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] bandwidth    Sets the bandwidth
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] preambleLen  Sets the Preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] payloadLen   Sets payload length when fixed length is used
+ * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+ *
+ * \retval airTime        Computed airTime (ms) for the given packet payload length
+ */
+uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn );
+
+
+/*!
+ * \brief Sends the buffer of size. Prepares the packet to be sent and sets
+ *        the radio in transmission
+ *
+ * \param [IN]: buffer     Buffer pointer
+ * \param [IN]: size       Buffer size
+ */
+void RadioSend( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Sets the radio in sleep mode
+ */
+void RadioSleep( void );
+
+/*!
+ * \brief Sets the radio in standby mode
+ */
+void RadioStandby( void );
+
+/*!
+ * \brief Sets the radio in reception mode for the given time
+ * \param [IN] timeout Reception timeout [ms]
+ *                     [0: continuous, others timeout]
+ */
+void RadioRx( uint32_t timeout );
+
+/*!
+ * \brief Start a Channel Activity Detection
+ */
+void RadioStartCad( void );
+
+/*!
+ * \brief Sets the radio in continuous wave transmission mode
+ *
+ * \param [IN]: freq       Channel RF frequency
+ * \param [IN]: power      Sets the output power [dBm]
+ * \param [IN]: time       Transmission mode timeout [s]
+ */
+void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time );
+
+/*!
+ * \brief Reads the current RSSI value
+ *
+ * \retval rssiValue Current RSSI value in [dBm]
+ */
+int16_t RadioRssi( RadioModems_t modem );
+
+/*!
+ * \brief Writes the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [IN]: data New register value
+ */
+void RadioWrite( uint16_t addr, uint8_t data );
+
+/*!
+ * \brief Reads the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \retval data Register value
+ */
+uint8_t RadioRead( uint16_t addr );
+
+/*!
+ * \brief Writes multiple radio registers starting at address
+ *
+ * \param [IN] addr   First Radio register address
+ * \param [IN] buffer Buffer containing the new register's values
+ * \param [IN] size   Number of registers to be written
+ */
+void RadioWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads multiple radio registers starting at address
+ *
+ * \param [IN] addr First Radio register address
+ * \param [OUT] buffer Buffer where to copy the registers data
+ * \param [IN] size Number of registers to be read
+ */
+void RadioReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Sets the maximum payload length.
+ *
+ * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] max        Maximum payload length in bytes
+ */
+void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max );
+
+/*!
+ * \brief Sets the network to public or private. Updates the sync byte.
+ *
+ * \remark Applies to LoRa modem only
+ *
+ * \param [IN] enable if true, it enables a public network
+ */
+void RadioSetPublicNetwork( bool enable );
+
+/*!
+ * \brief Gets the time required for the board plus radio to get out of sleep.[ms]
+ *
+ * \retval time Radio plus board wakeup time in ms.
+ */
+uint32_t RadioGetWakeupTime( void );
+
+/*!
+ * \brief Process radio irq
+ */
+void RadioIrqProcess( void );
+
+/*!
+ * \brief Radio spi check
+ * \retval radio spi access result  [0: Fail, 1: OK]
+ */
+uint8_t RadioCheck( void );
+
+/*!
+ * \brief Sets the radio in reception mode with Max LNA gain for the given time
+ * \param [IN] timeout Reception timeout [ms]
+ *                     [0: continuous, others timeout]
+ */
+void RadioRxBoosted( uint32_t timeout );
+
+/*!
+ * \brief Sets the Rx duty cycle management parameters
+ *
+ * \param [in]  rxTime        Structure describing reception timeout value
+ * \param [in]  sleepTime     Structure describing sleep timeout value
+ */
+void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime );
+
+/*!
+ * Radio driver structure initialization
+ */
+const struct Radio_s Radio =
+{
+    RadioInit,
+    RadioGetStatus,
+    RadioSetModem,
+    RadioSetChannel,
+    RadioIsChannelFree,
+    RadioRandom,
+    RadioSetRxConfig,
+    RadioSetTxConfig,
+    RadioCheckRfFrequency,
+    RadioTimeOnAir,
+    RadioSend,
+    RadioSleep,
+    RadioStandby,
+    RadioRx,
+    RadioStartCad,
+    RadioSetTxContinuousWave,
+    RadioRssi,
+    RadioWrite,
+    RadioRead,
+    //RadioWriteBuffer,
+    //RadioReadBuffer,
+    RadioSetMaxPayloadLength,
+    RadioSetPublicNetwork,
+    RadioGetWakeupTime,
+    RadioIrqProcess,
+    RadioCheck,
+    // Available on SX126x only
+    RadioRxBoosted,
+    RadioSetRxDutyCycle
+};
+
+/*
+ * Local types definition
+ */
+
+
+ /*!
+ * FSK bandwidth definition
+ */
+typedef struct
+{
+    uint32_t bandwidth;
+    uint8_t  RegValue;
+}FskBandwidth_t;
+
+/*!
+ * Precomputed FSK bandwidth registers values
+ */
+const FskBandwidth_t FskBandwidths[] =
+{
+    { 4800  , 0x1F },
+    { 5800  , 0x17 },
+    { 7300  , 0x0F },
+    { 9700  , 0x1E },
+    { 11700 , 0x16 },
+    { 14600 , 0x0E },
+    { 19500 , 0x1D },
+    { 23400 , 0x15 },
+    { 29300 , 0x0D },
+    { 39000 , 0x1C },
+    { 46900 , 0x14 },
+    { 58600 , 0x0C },
+    { 78200 , 0x1B },
+    { 93800 , 0x13 },
+    { 117300, 0x0B },
+    { 156200, 0x1A },
+    { 187200, 0x12 },
+    { 234300, 0x0A },
+    { 312000, 0x19 },
+    { 373600, 0x11 },
+    { 467000, 0x09 },
+    { 500000, 0x00 }, // Invalid Bandwidth
+};
+
+const RadioLoRaBandwidths_t Bandwidths[] = { LORA_BW_125, LORA_BW_250, LORA_BW_500 };
+
+uint8_t MaxPayloadLength = 0xFF;
+
+uint32_t TxTimeout = 0;
+uint32_t RxTimeout = 0;
+
+bool RxContinuous = false;
+
+PacketStatus_t RadioPktStatus;
+uint8_t RadioRxPayload[255];
+
+bool IrqFired = false;
+static bool lora_radio_init = false;
+/*
+ * SX126x DIO IRQ callback functions prototype
+ */
+
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void RadioOnDioIrq( void* context );
+
+/*!
+ * \brief Tx timeout timer callback
+ */
+void RadioOnTxTimeoutIrq( void/** context*/ );
+
+/*!
+ * \brief Rx timeout timer callback
+ */
+void RadioOnRxTimeoutIrq( void/** context*/);
+
+/*
+ * \brief spi initilize
+ */
+extern struct rt_spi_device *lora_radio_spi_init(const char *bus_name,const char *lora_device_name, rt_uint8_t param);
+
+/*
+ * Private global variables
+ */
+
+/*!
+ * Holds the current network type for the radio
+ */
+typedef struct
+{
+    bool Previous;
+    bool Current;
+}RadioPublicNetwork_t;
+
+static RadioPublicNetwork_t RadioPublicNetwork = { false };
+
+/*!
+ * Radio callbacks variable
+ */
+static RadioEvents_t* RadioEvents;
+
+/*
+ * Public global variables
+ */
+
+/*!
+ * Radio hardware and global parameters
+ */
+SX126x_t SX126x;
+
+/*!
+ * Tx and Rx timers
+ */
+static TimerEvent_t TxTimeoutTimer;
+static TimerEvent_t RxTimeoutTimer;
+
+/*
+ * Radio spi check
+ * 0     - spi access fail  
+ * non 0 - spi access success 
+ */
+uint8_t RadioCheck(void)
+{
+    uint8_t test = 0;
+
+    LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "Packet Type is %s\n",( SX126x.PacketParams.PacketType == PACKET_TYPE_LORA )? "LoRa":"FSK");
+    
+    /* SPI Access Check */
+    SX126xWriteRegister(REG_LR_PAYLOADLENGTH, 0x55); 
+    test = SX126xReadRegister(REG_LR_PAYLOADLENGTH);
+    LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"SPI Access Check %s, LoRa PAYLOAD LENGTH Reg(0x22) Current Value: 0x%02X, Expected Value: 0x55", ((test == 0x55)? "Success":"Fail"),test);
+    if (test != 0x55)
+    {
+        return 0;
+    }		
+    
+    return test;
+}
+
+
+/*!
+ * Returns the known FSK bandwidth registers value
+ *
+ * \param [IN] bandwidth Bandwidth value in Hz
+ * \retval regValue Bandwidth register value.
+ */
+static uint8_t RadioGetFskBandwidthRegValue( uint32_t bandwidth )
+{
+    uint8_t i;
+
+    if( bandwidth == 0 )
+    {
+        return( 0x1F );
+    }
+
+    for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
+    {
+        if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
+        {
+            return FskBandwidths[i+1].RegValue;
+        }
+    }
+    // ERROR: Value not found
+    while( 1 );
+}
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+/**
+  * @brief  lora_radio_thread_entry
+  * @param  None
+  * @retval None
+  */
+static void lora_radio_thread_entry(void* parameter)
+{
+    rt_uint32_t ev;
+    
+    while(1)
+    {
+        if (rt_event_recv(&lora_radio_event, EV_LORA_RADIO_DIO_IRQ_FIRED,
+                                RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                                RT_WAITING_FOREVER, &ev) == RT_EOK)
+        {
+            RadioIrqProcess();
+        }
+    }
+}
+
+#endif
+
+bool RadioInit( RadioEvents_t *events )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    if( lora_radio_init == false )
+    {
+        SX126x.spi = lora_radio_spi_init(LORA_RADIO0_SPI_BUS_NAME, LORA_RADIO0_DEVICE_NAME, RT_NULL);
+        if (SX126x.spi == RT_NULL)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "SX126x SPI Init Failed\n");
+            return false;
+        }
+        
+        LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "SX126x SPI Init Succeed\n");
+        
+        rt_event_init(&lora_radio_event, "ev_phy", RT_IPC_FLAG_PRIO);//RT_IPC_FLAG_FIFO);
+
+        rt_thread_init(&lora_radio_thread,
+                       "lora-phy",
+                       lora_radio_thread_entry,
+                       RT_NULL,
+                       &rt_lora_radio_thread_stack[0],
+                       sizeof(rt_lora_radio_thread_stack),
+                       1, // highest priority 
+                       20);
+                                   
+        rt_thread_startup(&lora_radio_thread);                         
+
+        lora_radio_init = true;
+    } 
+#else
+        IrqFired = false;
+#endif
+    
+    RadioEvents = events;
+
+#ifdef PKG_USING_MULTI_RTIMER
+    hw_rtc_init();
+#endif
+    // Initialize driver timeout timers
+    TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq );
+    TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq );
+    
+    SX126xIoInit();
+
+    SX126xInit( RadioOnDioIrq );
+    SX126xSetStandby( STDBY_RC );
+    SX126xSetRegulatorMode( USE_DCDC );
+
+    SX126xSetBufferBaseAddress( 0x00, 0x00 );
+    SX126xSetTxParams( 0, RADIO_RAMP_200_US );
+    SX126xSetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE );    
+    
+    return true;
+}
+
+RadioState_t RadioGetStatus( void )
+{
+    switch( SX126xGetOperatingMode( ) )
+    {
+        case MODE_TX:
+            return RF_TX_RUNNING;
+        case MODE_RX:
+            return RF_RX_RUNNING;
+        case MODE_CAD:
+            return RF_CAD;
+        default:
+            return RF_IDLE;
+    }
+}
+
+void RadioSetModem( RadioModems_t modem )
+{
+    switch( modem )
+    {
+        default:
+        case MODEM_FSK:
+            SX126xSetPacketType( PACKET_TYPE_GFSK );
+            // When switching to GFSK mode the LoRa SyncWord register value is reset
+            // Thus, we also reset the RadioPublicNetwork variable
+            RadioPublicNetwork.Current = false;
+            break;
+        case MODEM_LORA:
+            SX126xSetPacketType( PACKET_TYPE_LORA );
+            // Public/Private network register is reset when switching modems
+            if( RadioPublicNetwork.Current != RadioPublicNetwork.Previous )
+            {
+                RadioPublicNetwork.Current = RadioPublicNetwork.Previous;
+                RadioSetPublicNetwork( RadioPublicNetwork.Current );
+            }
+            break;
+    }
+}
+
+void RadioSetChannel( uint32_t freq )
+{
+    SX126xSetRfFrequency( freq );
+}
+
+bool RadioIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime )
+{
+    bool status = true;
+    int16_t rssi = 0;
+    uint32_t carrierSenseTime = 0;
+
+    RadioSleep( );
+
+    RadioSetModem( modem );
+
+    RadioSetChannel( freq );
+
+    RadioRx( 0 );
+
+    SX126X_DELAY_MS( 1 );
+
+    carrierSenseTime = TimerGetCurrentTime( );
+
+    // Perform carrier sense for maxCarrierSenseTime
+    while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime )
+    {
+        rssi = RadioRssi( modem );
+
+        if( rssi > rssiThresh )
+        {
+            status = false;
+            break;
+        }
+    }
+    RadioSleep( );
+    return status;
+}
+
+
+uint32_t RadioRandom( void )
+{
+    uint32_t rnd = 0;
+
+    /*
+     * Radio setup for random number generation
+     */
+    // Set LoRa modem ON
+    RadioSetModem( MODEM_LORA );
+
+    // Disable LoRa modem interrupts ( RxDone RXTimeout )
+    SX126xSetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE );
+
+    rnd = SX126xGetRandom( );
+
+    return rnd;
+}
+
+void RadioSetRxConfig( RadioModems_t modem, uint32_t bandwidth,
+                         uint32_t datarate, uint8_t coderate,
+                         uint32_t bandwidthAfc, uint16_t preambleLen,
+                         uint16_t symbTimeout, bool fixLen,
+                         uint8_t payloadLen,
+                         bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+                         bool iqInverted, bool rxContinuous )
+{
+
+    RxContinuous = rxContinuous;
+    if( rxContinuous == true )
+    {
+        symbTimeout = 0;
+    }
+    if( fixLen == true )
+    {
+        MaxPayloadLength = payloadLen;
+    }
+    else
+    {
+        MaxPayloadLength = 0xFF;
+    }
+
+    switch( modem )
+    {
+        case MODEM_FSK:
+            SX126xSetStopRxTimerOnPreambleDetect( false );
+            SX126x.ModulationParams.PacketType = PACKET_TYPE_GFSK;
+
+            SX126x.ModulationParams.Params.Gfsk.BitRate = datarate;
+            SX126x.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1;
+            SX126x.ModulationParams.Params.Gfsk.Bandwidth = RadioGetFskBandwidthRegValue( bandwidth );
+
+            SX126x.PacketParams.PacketType = PACKET_TYPE_GFSK;
+            SX126x.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit
+            SX126x.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS;
+            SX126x.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit
+            SX126x.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF;
+            SX126x.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH;
+            SX126x.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength;
+            if( crcOn == true )
+            {
+                SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT;
+            }
+            else
+            {
+                SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF;
+            }
+            SX126x.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING;
+
+            RadioStandby( );
+            RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA );
+            SX126xSetModulationParams( &SX126x.ModulationParams );
+            SX126xSetPacketParams( &SX126x.PacketParams );
+            SX126xSetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } );
+            SX126xSetWhiteningSeed( 0x01FF );
+
+            RxTimeout = ( uint32_t )( symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1000 );
+            break;
+
+        case MODEM_LORA:
+            SX126xSetStopRxTimerOnPreambleDetect( false );
+            SX126x.ModulationParams.PacketType = PACKET_TYPE_LORA;
+            SX126x.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate;
+            SX126x.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth];
+            SX126x.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate;
+
+            if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+            ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+            {
+                SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            SX126x.PacketParams.PacketType = PACKET_TYPE_LORA;
+
+            if( ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
+                ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) )
+            {
+                if( preambleLen < 12 )
+                {
+                    SX126x.PacketParams.Params.LoRa.PreambleLength = 12;
+                }
+                else
+                {
+                    SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen;
+                }
+            }
+            else
+            {
+                SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen;
+            }
+
+            SX126x.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen;
+
+            SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength;
+            SX126x.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn;
+            SX126x.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted;
+            
+            RadioStandby( );
+            RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA );
+            SX126xSetModulationParams( &SX126x.ModulationParams );
+            SX126xSetPacketParams( &SX126x.PacketParams );
+            SX126xSetLoRaSymbNumTimeout( symbTimeout );
+            
+            // WORKAROUND - Optimizing the Inverted IQ Operation, see DS_SX1261-2_V1.2 datasheet chapter 15.4
+            if( SX126x.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED )
+            {
+                // RegIqPolaritySetup = @address 0x0736
+                SX126xWriteRegister( 0x0736, SX126xReadRegister( 0x0736 ) & ~( 1 << 2 ) );
+            }
+            else
+            {
+                // RegIqPolaritySetup @address 0x0736
+                SX126xWriteRegister( 0x0736, SX126xReadRegister( 0x0736 ) | ( 1 << 2 ) );
+            }
+            // WORKAROUND END
+
+            // Timeout Max, Timeout handled directly in SetRx function
+            RxTimeout = 0xFFFF;
+
+            break;
+    }
+}
+
+void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+                        uint32_t bandwidth, uint32_t datarate,
+                        uint8_t coderate, uint16_t preambleLen,
+                        bool fixLen, bool crcOn, bool freqHopOn,
+                        uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
+{
+
+    switch( modem )
+    {
+        case MODEM_FSK:
+            SX126x.ModulationParams.PacketType = PACKET_TYPE_GFSK;
+            SX126x.ModulationParams.Params.Gfsk.BitRate = datarate;
+
+            SX126x.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1;
+            SX126x.ModulationParams.Params.Gfsk.Bandwidth = RadioGetFskBandwidthRegValue( bandwidth );
+            SX126x.ModulationParams.Params.Gfsk.Fdev = fdev;
+
+            SX126x.PacketParams.PacketType = PACKET_TYPE_GFSK;
+            SX126x.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit
+            SX126x.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS;
+            SX126x.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit
+            SX126x.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF;
+            SX126x.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH;
+
+            if( crcOn == true )
+            {
+                SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT;
+            }
+            else
+            {
+                SX126x.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF;
+            }
+            SX126x.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING;
+
+            RadioStandby( );
+            RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA );
+            SX126xSetModulationParams( &SX126x.ModulationParams );
+            SX126xSetPacketParams( &SX126x.PacketParams );
+            SX126xSetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } );
+            SX126xSetWhiteningSeed( 0x01FF );
+            break;
+
+        case MODEM_LORA:
+            SX126x.ModulationParams.PacketType = PACKET_TYPE_LORA;
+            SX126x.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate;
+            SX126x.ModulationParams.Params.LoRa.Bandwidth =  Bandwidths[bandwidth];
+            SX126x.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate;
+
+            if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+            ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+            {
+                SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX126x.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            SX126x.PacketParams.PacketType = PACKET_TYPE_LORA;
+
+            if( ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) ||
+                ( SX126x.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) )
+            {
+                if( preambleLen < 12 )
+                {
+                    SX126x.PacketParams.Params.LoRa.PreambleLength = 12;
+                }
+                else
+                {
+                    SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen;
+                }
+            }
+            else
+            {
+                SX126x.PacketParams.Params.LoRa.PreambleLength = preambleLen;
+            }
+
+            SX126x.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen;
+            SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength;
+            SX126x.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn;
+            SX126x.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted;
+
+            RadioStandby( );
+            RadioSetModem( ( SX126x.ModulationParams.PacketType == PACKET_TYPE_GFSK ) ? MODEM_FSK : MODEM_LORA );
+            SX126xSetModulationParams( &SX126x.ModulationParams );
+            SX126xSetPacketParams( &SX126x.PacketParams );
+            break;
+    }
+
+    // WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see DS_SX1261-2_V1.2 datasheet chapter 15.1
+    if( ( modem == MODEM_LORA ) && ( SX126x.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) )
+    {
+        // RegTxModulation = @address 0x0889
+        SX126xWriteRegister( 0x0889, SX126xReadRegister( 0x0889 ) & ~( 1 << 2 ) );
+    }
+    else
+    {
+        // RegTxModulation = @address 0x0889
+        SX126xWriteRegister( 0x0889, SX126xReadRegister( 0x0889 ) | ( 1 << 2 ) );
+    }
+    // WORKAROUND END
+
+    SX126xSetRfTxPower( power );
+    TxTimeout = timeout;
+}
+
+bool RadioCheckRfFrequency( uint32_t frequency )
+{
+    return true;
+}
+
+static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw )
+{
+    uint32_t bandwidthInHz = 0;
+
+    switch( bw )
+    {
+    case LORA_BW_007:
+        bandwidthInHz = 7812UL;
+        break;
+    case LORA_BW_010:
+        bandwidthInHz = 10417UL;
+        break;
+    case LORA_BW_015:
+        bandwidthInHz = 15625UL;
+        break;
+    case LORA_BW_020:
+        bandwidthInHz = 20833UL;
+        break;
+    case LORA_BW_031:
+        bandwidthInHz = 31250UL;
+        break;
+    case LORA_BW_041:
+        bandwidthInHz = 41667UL;
+        break;
+    case LORA_BW_062:
+        bandwidthInHz = 62500UL;
+        break;
+    case LORA_BW_125:
+        bandwidthInHz = 125000UL;
+        break;
+    case LORA_BW_250:
+        bandwidthInHz = 250000UL;
+        break;
+    case LORA_BW_500:
+        bandwidthInHz = 500000UL;
+        break;
+    }
+
+    return bandwidthInHz;
+}
+
+static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+    const RadioAddressComp_t addrComp = RADIO_ADDRESSCOMP_FILT_OFF;
+    const uint8_t syncWordLength = 3;
+
+    return ( preambleLen << 3 ) +
+           ( ( fixLen == false ) ? 8 : 0 ) +
+             ( syncWordLength << 3 ) +
+             ( ( payloadLen +
+               ( addrComp == RADIO_ADDRESSCOMP_FILT_OFF ? 0 : 1 ) +
+               ( ( crcOn == true ) ? 2 : 0 ) 
+               ) << 3 
+             );
+}
+
+static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+    int32_t crDenom           = coderate + 4;
+    bool    lowDatareOptimize = false;
+
+    // Ensure that the preamble length is at least 12 symbols when using SF5 or
+    // SF6
+    if( ( datarate == 5 ) || ( datarate == 6 ) )
+    {
+        if( preambleLen < 12 )
+        {
+            preambleLen = 12;
+        }
+    }
+
+    if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+        ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+    {
+        lowDatareOptimize = true;
+    }
+
+    int32_t ceilDenominator;
+    int32_t ceilNumerator = ( payloadLen << 3 ) +
+                            ( crcOn ? 16 : 0 ) -
+                            ( 4 * datarate ) +
+                            ( fixLen ? 0 : 20 );
+
+    if( datarate <= 6 )
+    {
+        ceilDenominator = 4 * datarate;
+    }
+    else
+    {
+        ceilNumerator += 8;
+
+        if( lowDatareOptimize == true )
+        {
+            ceilDenominator = 4 * ( datarate - 2 );
+        }
+        else
+        {
+            ceilDenominator = 4 * datarate;
+        }
+    }
+
+    if( ceilNumerator < 0 )
+    {
+        ceilNumerator = 0;
+    }
+
+    // Perform integral ceil()
+    int32_t intermediate =
+        ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12;
+
+    if( datarate <= 6 )
+    {
+        intermediate += 2;
+    }
+
+    return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) );
+}
+
+uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+    uint32_t numerator = 0;
+    uint32_t denominator = 1;
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        {
+            numerator   = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate,
+                                                                  preambleLen, fixLen,
+                                                                  payloadLen, crcOn );
+            denominator = datarate;
+        }
+        break;
+    case MODEM_LORA:
+        {
+            numerator   = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate,
+                                                                  coderate, preambleLen,
+                                                                  fixLen, payloadLen, crcOn );
+            denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] );
+        }
+        break;
+    }
+    // Perform integral ceil()
+    return ( numerator + denominator - 1 ) / denominator;
+}
+
+
+void RadioSend( uint8_t *buffer, uint8_t size )
+{
+    SX126xSetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_RADIO_NONE,
+                           IRQ_RADIO_NONE );
+
+    if( SX126xGetPacketType( ) == PACKET_TYPE_LORA )
+    {
+        SX126x.PacketParams.Params.LoRa.PayloadLength = size;
+    }
+    else
+    {
+        SX126x.PacketParams.Params.Gfsk.PayloadLength = size;
+    }
+    SX126xSetPacketParams( &SX126x.PacketParams );
+
+    SX126xSendPayload( buffer, size, 0 );
+    
+    TimerSetValue( &TxTimeoutTimer, TxTimeout );
+    TimerStart( &TxTimeoutTimer );
+}
+
+void RadioSleep( void )
+{
+    SleepParams_t params = { 0 };
+
+    params.Fields.WarmStart = 1;
+    SX126xSetSleep( params );
+
+    SX126X_BLOCK_DELAY_1MS();
+}
+
+void RadioStandby( void )
+{
+    SX126xSetStandby( STDBY_RC );
+}
+
+void RadioRx( uint32_t timeout )
+{
+    SX126xSetDioIrqParams( IRQ_RADIO_ALL, //IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_RADIO_ALL, //IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_RADIO_NONE,
+                           IRQ_RADIO_NONE );
+
+    if( timeout != 0 )
+    {
+        TimerSetValue( &RxTimeoutTimer, timeout );
+        TimerStart( &RxTimeoutTimer );
+    }
+
+    if( RxContinuous == true )
+    {
+        SX126xSetRx( 0xFFFFFF ); // Rx Continuous
+    }
+    else
+    {
+        SX126xSetRx( RxTimeout << 6 );
+    }
+}
+
+void RadioRxBoosted( uint32_t timeout )
+{
+    SX126xSetDioIrqParams( IRQ_RADIO_ALL, //IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_RADIO_ALL, //IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT,
+                           IRQ_RADIO_NONE,
+                           IRQ_RADIO_NONE );
+
+    if( timeout != 0 )
+    {
+        TimerSetValue( &RxTimeoutTimer, timeout );
+        TimerStart( &RxTimeoutTimer );
+    }
+
+    if( RxContinuous == true )
+    {
+        SX126xSetRxBoosted( 0xFFFFFF ); // Rx Continuous
+    }
+    else
+    {
+        SX126xSetRxBoosted( RxTimeout << 6 );
+    }
+}
+
+void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime )
+{
+    SX126xSetRxDutyCycle( rxTime, sleepTime );
+}
+
+void RadioStartCad( void )
+{
+    SX126xSetDioIrqParams( IRQ_CAD_DONE | IRQ_CAD_ACTIVITY_DETECTED, IRQ_CAD_DONE | IRQ_CAD_ACTIVITY_DETECTED, IRQ_RADIO_NONE, IRQ_RADIO_NONE );
+    SX126xSetCad( );
+}
+
+void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
+{
+    uint32_t timeout = ( uint32_t )time * 1000;
+    SX126xSetRfFrequency( freq );
+    SX126xSetRfTxPower( power );
+    SX126xSetTxContinuousWave( );
+
+    TimerSetValue( &TxTimeoutTimer, timeout );
+    TimerStart( &TxTimeoutTimer );
+}
+
+int16_t RadioRssi( RadioModems_t modem )
+{
+    return SX126xGetRssiInst( );
+}
+
+void RadioWrite( uint16_t addr, uint8_t data )
+{
+    SX126xWriteRegister( addr, data );
+}
+
+uint8_t RadioRead( uint16_t addr )
+{
+    return SX126xReadRegister( addr );
+}
+
+void RadioWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size )
+{
+    SX126xWriteRegisters( addr, buffer, size );
+}
+
+void RadioReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size )
+{
+    SX126xReadRegisters( addr, buffer, size );
+}
+void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max )
+{
+    if( modem == MODEM_LORA )
+    {
+        SX126x.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max;
+        SX126xSetPacketParams( &SX126x.PacketParams );
+    }
+    else
+    {
+        if( SX126x.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH )
+        {
+            SX126x.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max;
+            SX126xSetPacketParams( &SX126x.PacketParams );
+        }
+    }
+}
+
+void RadioSetPublicNetwork( bool enable )
+{
+    RadioPublicNetwork.Current = RadioPublicNetwork.Previous = enable;
+
+    RadioSetModem( MODEM_LORA );
+    if( enable == true )
+    {
+        // Change LoRa modem SyncWord
+        SX126xWriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF );
+        SX126xWriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF );
+    }
+    else
+    {
+        // Change LoRa modem SyncWord
+        SX126xWriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF );
+        SX126xWriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF );
+    }
+}
+
+uint32_t RadioGetWakeupTime( void )
+{
+    return SX126xGetBoardTcxoWakeupTime( ) + RADIO_WAKEUP_TIME;
+}
+
+void RadioOnTxTimeoutIrq( void /** context*/ )
+{
+    if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) )
+    {
+        RadioEvents->TxTimeout( );
+    }
+    LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY TX Timeout\r");
+}
+
+void RadioOnRxTimeoutIrq( void /** context*/ )
+{
+    if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
+    {
+        RadioEvents->RxTimeout( );
+    }
+    LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY RX Timeout\r");
+}
+
+void RadioOnDioIrq( void* context )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_DIO_IRQ_FIRED);      
+#else
+    IrqFired = true;
+#endif
+}
+
+void RadioIrqProcess( void )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    LORA_RADIO_CRITICAL_SECTION_BEGIN( );
+#else
+    if( IrqFired == true )
+#endif    
+    {
+#ifndef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+        LORA_RADIO_CRITICAL_SECTION_BEGIN( );
+        // Clear IRQ flag
+        IrqFired = false;
+        LORA_RADIO_CRITICAL_SECTION_END( );
+#endif
+
+        uint16_t irqRegs = SX126xGetIrqStatus( );
+        SX126xClearIrqStatus( IRQ_RADIO_ALL );
+
+        if( ( irqRegs & IRQ_TX_DONE ) == IRQ_TX_DONE )
+        {
+            TimerStop( &TxTimeoutTimer );
+            //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+            SX126xSetOperatingMode( MODE_STDBY_RC );
+            if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) )
+            {
+                RadioEvents->TxDone( );
+            }
+            LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY TX Done\r");
+        }
+
+        if( ( irqRegs & IRQ_RX_DONE ) == IRQ_RX_DONE )
+        {
+            if( ( irqRegs & IRQ_CRC_ERROR ) == IRQ_CRC_ERROR )
+            {    
+                if( RxContinuous == false )
+                {
+                    //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+                    SX126xSetOperatingMode( MODE_STDBY_RC );
+                }
+                
+                if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) )
+                {
+                        RadioEvents->RxError( );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY CRC Error\r");
+            }
+            else
+            {
+                uint8_t size;
+
+                TimerStop( &RxTimeoutTimer );
+                    
+                if( RxContinuous == false )
+                {
+                     //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+                     SX126xSetOperatingMode( MODE_STDBY_RC );
+
+                     // WORKAROUND - Implicit Header Mode Timeout Behavior, see DS_SX1261-2_V1.2 datasheet chapter 15.3
+                     // RegRtcControl = @address 0x0902
+                     SX126xWriteRegister( 0x0902, 0x00 );
+                     // RegEventMask = @address 0x0944
+                     SX126xWriteRegister( 0x0944, SX126xReadRegister( 0x0944 ) | ( 1 << 1 ) );
+                     // WORKAROUND END
+                 } 
+                SX126xGetPayload( RadioRxPayload, &size , 255 );
+                SX126xGetPacketStatus( &RadioPktStatus );
+                if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) )
+                {
+                    RadioEvents->RxDone( RadioRxPayload, size, RadioPktStatus.Params.LoRa.RssiPkt, RadioPktStatus.Params.LoRa.SnrPkt );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY RX Done\r");
+            }
+        }
+
+        if( ( irqRegs & IRQ_CAD_DONE ) == IRQ_CAD_DONE )
+        {
+            //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+            SX126xSetOperatingMode( MODE_STDBY_RC );
+            if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) )
+            {
+                RadioEvents->CadDone( ( ( irqRegs & IRQ_CAD_ACTIVITY_DETECTED ) == IRQ_CAD_ACTIVITY_DETECTED ) );
+            }
+            LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY CAD Done\r");
+        }
+
+        if( ( irqRegs & IRQ_RX_TX_TIMEOUT ) == IRQ_RX_TX_TIMEOUT )
+        {
+            if( SX126xGetOperatingMode( ) == MODE_TX )
+            {
+                TimerStop( &TxTimeoutTimer );
+                //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+                SX126xSetOperatingMode( MODE_STDBY_RC );
+                if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) )
+                {
+                    RadioEvents->TxTimeout( );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY TX Timeout\r");
+            }
+            else if( SX126xGetOperatingMode( ) == MODE_RX )
+            {
+                TimerStop( &RxTimeoutTimer );
+                //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+                SX126xSetOperatingMode( MODE_STDBY_RC );
+                if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
+                {
+                    RadioEvents->RxTimeout( );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY RX Timeout\r");
+            }
+        }
+
+        if( ( irqRegs & IRQ_PREAMBLE_DETECTED ) == IRQ_PREAMBLE_DETECTED )
+        {
+            //__NOP( );
+        }
+
+        if( ( irqRegs & IRQ_SYNCWORD_VALID ) == IRQ_SYNCWORD_VALID )
+        {
+            //__NOP( );
+        }
+
+        if( ( irqRegs & IRQ_HEADER_VALID ) == IRQ_HEADER_VALID )
+        {
+            //__NOP( );
+        }
+
+        if( ( irqRegs & IRQ_HEADER_ERROR ) == IRQ_HEADER_ERROR )
+        {
+            TimerStop( &RxTimeoutTimer );
+            if( RxContinuous == false )
+            {
+                //!< Update operating mode state to a value lower than \ref MODE_STDBY_XOSC
+                SX126xSetOperatingMode( MODE_STDBY_RC );
+            }
+            if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
+            {
+                RadioEvents->RxTimeout( );
+            }
+            LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "PHY HEADER Error\r");
+        }
+    }
+    
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    LORA_RADIO_CRITICAL_SECTION_END( );
+#endif
+}
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx126x/lora-spi-sx126x.c

@@ -0,0 +1,157 @@
+/*!
+ * \file      lora-spi-SX126x.c
+ *
+ * \brief     spi driver implementation for SX126X
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+ 
+#include "sx126x-board.h"
+
+#define LOG_TAG "LoRa.SX126X.SPI"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+void SX126xWakeup( void )
+{
+#ifdef RT_USING_SPI
+    uint8_t msg[2] = { RADIO_GET_STATUS, 0x00 };
+    
+    rt_spi_transfer(SX126x.spi,msg,RT_NULL,2);
+    
+    // Wait for chip to be ready.
+    SX126xWaitOnBusy( );
+    
+    // Update operating mode context variable
+    SX126xSetOperatingMode( MODE_STDBY_RC );
+#else
+#endif
+    
+}
+
+void SX126xWriteCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
+{    
+#ifdef RT_USING_SPI
+    SX126xCheckDeviceReady( );
+
+    rt_spi_send_then_send(SX126x.spi,&command,1,buffer,size);
+    
+    if( command != RADIO_SET_SLEEP )
+    {
+        SX126xWaitOnBusy( );
+    }
+#else
+#endif    
+}
+
+uint8_t SX126xReadCommand( RadioCommands_t command, uint8_t *buffer, uint16_t size )
+{
+#ifdef RT_USING_SPI
+    uint8_t status = 0;
+    uint8_t buffer_temp[16] = {0}; // command size is 2 size
+    
+    SX126xCheckDeviceReady( );
+    
+    rt_spi_send_then_recv(SX126x.spi,&command,1,buffer_temp,size + 1);
+    
+    status = buffer_temp[0];
+    
+    rt_memcpy(buffer,buffer_temp+1,size);
+    
+    SX126xWaitOnBusy( );
+    
+    return status;
+#else
+#endif    
+}
+
+void SX126xWriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size )
+{
+#ifdef RT_USING_SPI
+    uint8_t msg[3] = {0};
+    
+    msg[0] = RADIO_WRITE_REGISTER;
+    msg[1] = ( address & 0xFF00 ) >> 8;
+    msg[2] = address & 0x00FF;
+    
+    SX126xCheckDeviceReady( );
+    
+    rt_spi_send_then_send(SX126x.spi,msg,3,buffer,size);
+
+    SX126xWaitOnBusy( );
+#else
+#endif    
+}
+
+void SX126xWriteRegister( uint16_t address, uint8_t value )
+{
+    SX126xWriteRegisters( address, &value, 1 );
+}
+
+void SX126xReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size )
+{ 
+#ifdef RT_USING_SPI
+    uint8_t msg[4] = {0};
+    
+    msg[0] = RADIO_READ_REGISTER;
+    msg[1] = ( address & 0xFF00 ) >> 8;
+    msg[2] = address & 0x00FF;
+    msg[3] = 0;
+    
+    SX126xCheckDeviceReady( );
+
+    rt_spi_send_then_recv(SX126x.spi,msg,4,buffer,size);
+
+    SX126xWaitOnBusy( );
+#else
+#endif
+}
+
+uint8_t SX126xReadRegister( uint16_t address )
+{
+    uint8_t data;
+    SX126xReadRegisters( address, &data, 1 );
+    return data;
+}
+
+void SX126xWriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
+{
+#ifdef RT_USING_SPI
+
+    uint8_t msg[2] = {0};
+    
+    msg[0] = RADIO_WRITE_BUFFER;
+    msg[1] = offset;
+    
+    SX126xCheckDeviceReady( );
+    
+    rt_spi_send_then_send(SX126x.spi,msg,2,buffer,size);
+    
+    SX126xWaitOnBusy( );  
+
+#else    
+
+#endif
+}
+
+void SX126xReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size )
+{
+#ifdef RT_USING_SPI
+    uint8_t msg[3] = {0};
+    
+    msg[0] = RADIO_READ_BUFFER;
+    msg[1] = offset;
+    msg[2] = 0;
+    
+    SX126xCheckDeviceReady( );
+
+    rt_spi_send_then_recv(SX126x.spi,msg,3,buffer,size);
+
+    SX126xWaitOnBusy( );
+#else    
+
+#endif
+    
+}

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx126x/lora-spi-sx126x.h

@@ -0,0 +1,95 @@
+/*!
+ * \file      lora-spi-sx126x.h
+ *
+ * \brief     SX126x spi interface
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * \author    Forest-Rain
+ */
+#ifndef __LORA_SPI_SX126X_H__
+#define __LORA_SPI_SX126X_H__
+
+#include "sx126x/sx126x.h"
+
+/*!
+ * \brief Wakes up the radio
+ */
+void SX126xWakeup( void );
+
+/*!
+ * \brief Send a command that write data to the radio
+ *
+ * \param [in]  opcode        Opcode of the command
+ * \param [in]  buffer        Buffer to be send to the radio
+ * \param [in]  size          Size of the buffer to send
+ */
+void SX126xWriteCommand( RadioCommands_t opcode, uint8_t *buffer, uint16_t size );
+
+/*!
+ * \brief Send a command that read data from the radio
+ *
+ * \param [in]  opcode        Opcode of the command
+ * \param [out] buffer        Buffer holding data from the radio
+ * \param [in]  size          Size of the buffer
+ *
+ * \retval status Return command radio status
+ */
+uint8_t SX126xReadCommand( RadioCommands_t opcode, uint8_t *buffer, uint16_t size );
+
+/*!
+ * \brief Write a single byte of data to the radio memory
+ *
+ * \param [in]  address       The address of the first byte to write in the radio
+ * \param [in]  value         The data to be written in radio's memory
+ */
+void SX126xWriteRegister( uint16_t address, uint8_t value );
+
+/*!
+ * \brief Read a single byte of data from the radio memory
+ *
+ * \param [in]  address       The address of the first byte to write in the radio
+ *
+ * \retval      value         The value of the byte at the given address in radio's memory
+ */
+uint8_t SX126xReadRegister( uint16_t address );
+
+/*!
+ * \brief Write data to the radio memory
+ *
+ * \param [in]  address       The address of the first byte to write in the radio
+ * \param [in]  buffer        The data to be written in radio's memory
+ * \param [in]  size          The number of bytes to write in radio's memory
+ */
+void SX126xWriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size );
+
+/*!
+ * \brief Read data from the radio memory
+ *
+ * \param [in]  address       The address of the first byte to read from the radio
+ * \param [out] buffer        The buffer that holds data read from radio
+ * \param [in]  size          The number of bytes to read from radio's memory
+ */
+void SX126xReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size );
+
+/*!
+ * \brief Write data to the buffer holding the payload in the radio
+ *
+ * \param [in]  offset        The offset to start writing the payload
+ * \param [in]  buffer        The data to be written (the payload)
+ * \param [in]  size          The number of byte to be written
+ */
+void SX126xWriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Read data from the buffer holding the payload in the radio
+ *
+ * \param [in]  offset        The offset to start reading the payload
+ * \param [out] buffer        A pointer to a buffer holding the data from the radio
+ * \param [in]  size          The number of byte to be read
+ */
+void SX126xReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size );
+
+#endif /* __LORA_SPI_SX126X_H__ */
+
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx126x/sx126x.c

@@ -0,0 +1,808 @@
+/*!
+ * \file      sx126x.c
+ *
+ * \brief     SX126x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ */
+ 
+#include "lora-radio-rtos-config.h"
+#include <board.h>
+#include "lora-radio-timer.h"
+#include "lora-radio.h"
+#include "lora-spi-sx126x.h"
+#include "sx126x-board.h"
+
+/*!
+ * \brief Radio registers definition
+ */
+typedef struct
+{
+    uint16_t      Addr;                             //!< The address of the register
+    uint8_t       Value;                            //!< The value of the register
+}RadioRegisters_t;
+
+/*!
+ * \brief Holds the internal operating mode of the radio
+ */
+static RadioOperatingModes_t OperatingMode;
+
+/*!
+ * \brief Stores the current packet type set in the radio
+ */
+static RadioPacketTypes_t PacketType;
+
+/*!
+ * \brief Stores the current packet header type set in the radio
+ */
+static volatile RadioLoRaPacketLengthsMode_t LoRaHeaderType;
+
+/*!
+ * \brief Stores the last frequency error measured on LoRa received packet
+ */
+volatile uint32_t FrequencyError = 0;
+
+/*!
+ * \brief Hold the status of the Image calibration
+ */
+static bool ImageCalibrated = false;
+
+/*
+ * SX126x DIO IRQ callback functions prototype
+ */
+
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX126xOnDioIrq( void );
+
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX126xSetPollingMode( void );
+
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX126xSetInterruptMode( void );
+
+/*
+ * \brief Process the IRQ if handled by the driver
+ */
+void SX126xProcessIrqs( void );
+
+void SX126xInit( DioIrqHandler dioIrq )
+{   
+    SX126xReset( );
+
+    SX126xIoIrqInit( dioIrq );
+
+    SX126xWakeup( );
+    SX126xSetStandby( STDBY_RC );
+    
+#ifdef LORA_RADIO_USE_TCXO
+    // Initialize TCXO control
+    SX126xIoTcxoInit( );
+#endif
+    
+#ifdef LORA_RADIO_USE_DIO2_AS_RF_SWITCH_CTRL
+    SX126xSetDio2AsRfSwitchCtrl( true );
+#endif
+    
+    SX126xSetOperatingMode( MODE_STDBY_RC );
+}
+
+RadioOperatingModes_t SX126xGetOperatingMode( void )
+{
+    return OperatingMode;
+}
+
+void SX126xSetOperatingMode( RadioOperatingModes_t mode )
+{
+    OperatingMode = mode;
+
+#if defined( LORA_RADIO_RFSW2_PIN ) && defined( LORA_RADIO_RFSW1_PIN )      
+    SX126xSetAntSw( mode );
+#endif
+    
+#if defined( USE_RADIO_DEBUG )
+    switch( mode )
+    {
+        case MODE_TX:
+            SX126xDbgPinTxWrite( 1 );
+            SX126xDbgPinRxWrite( 0 );
+            break;
+        case MODE_RX:
+        case MODE_RX_DC:
+            SX126xDbgPinTxWrite( 0 );
+            SX126xDbgPinRxWrite( 1 );
+            break;
+        default:
+            SX126xDbgPinTxWrite( 0 );
+            SX126xDbgPinRxWrite( 0 );
+            break;
+    }
+#endif
+}
+
+void SX126xCheckDeviceReady( void )
+{
+    if( ( SX126xGetOperatingMode( ) == MODE_SLEEP ) || ( SX126xGetOperatingMode( ) == MODE_RX_DC ) )
+    {
+        SX126xWakeup( );
+        // Switch is turned off when device is in sleep mode and turned on is all other modes
+        SX126xAntSwOn( );
+    }
+    SX126xWaitOnBusy( );
+}
+
+void SX126xSetPayload( uint8_t *payload, uint8_t size )
+{
+    SX126xWriteBuffer( 0x00, payload, size );
+}
+
+uint8_t SX126xGetPayload( uint8_t *buffer, uint8_t *size,  uint8_t maxSize )
+{
+    uint8_t offset = 0;
+
+    SX126xGetRxBufferStatus( size, &offset );
+    if( *size > maxSize )
+    {
+        return 1;
+    }
+    SX126xReadBuffer( offset, buffer, *size );
+    return 0;
+}
+
+void SX126xSendPayload( uint8_t *payload, uint8_t size, uint32_t timeout )
+{
+    SX126xSetPayload( payload, size );
+    SX126xSetTx( timeout );
+}
+
+uint8_t SX126xSetSyncWord( uint8_t *syncWord )
+{
+    SX126xWriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 );
+    return 0;
+}
+
+void SX126xSetCrcSeed( uint16_t seed )
+{
+    uint8_t buf[2];
+
+    buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF );
+    buf[1] = ( uint8_t )( seed & 0xFF );
+
+    switch( SX126xGetPacketType( ) )
+    {
+        case PACKET_TYPE_GFSK:
+            SX126xWriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 );
+            break;
+
+        default:
+            break;
+    }
+}
+
+void SX126xSetCrcPolynomial( uint16_t polynomial )
+{
+    uint8_t buf[2];
+
+    buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF );
+    buf[1] = ( uint8_t )( polynomial & 0xFF );
+
+    switch( SX126xGetPacketType( ) )
+    {
+        case PACKET_TYPE_GFSK:
+            SX126xWriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 );
+            break;
+
+        default:
+            break;
+    }
+}
+
+void SX126xSetWhiteningSeed( uint16_t seed )
+{
+    uint8_t regValue = 0;
+    
+    switch( SX126xGetPacketType( ) )
+    {
+        case PACKET_TYPE_GFSK:
+            regValue = SX126xReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE;
+            regValue = ( ( seed >> 8 ) & 0x01 ) | regValue;
+            SX126xWriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit.
+            SX126xWriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, ( uint8_t )seed );
+            break;
+
+        default:
+            break;
+    }
+}
+
+uint32_t SX126xGetRandom( void )
+{
+    uint32_t number = 0;
+    uint8_t regAnaLna = 0;
+    uint8_t regAnaMixer = 0;
+
+    regAnaLna = SX126xReadRegister( REG_ANA_LNA );
+    SX126xWriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) );
+
+    regAnaMixer = SX126xReadRegister( REG_ANA_MIXER );
+    SX126xWriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) );
+
+    // Set radio in continuous reception
+    SX126xSetRx( 0xFFFFFF ); // Rx Continuous
+
+    SX126xReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 );
+
+    SX126xSetStandby( STDBY_RC );
+
+    SX126xWriteRegister( REG_ANA_LNA, regAnaLna );
+    SX126xWriteRegister( REG_ANA_MIXER, regAnaMixer );
+
+    return number;
+}
+
+void SX126xSetSleep( SleepParams_t sleepConfig )
+{
+    SX126xAntSwOff( );
+    uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) |
+                      ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) |
+                      ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) );
+    SX126xWriteCommand( RADIO_SET_SLEEP, &value, 1 ); 
+    SX126xSetOperatingMode( MODE_SLEEP );
+}
+
+void SX126xSetStandby( RadioStandbyModes_t standbyConfig )
+{
+    SX126xWriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 );
+    if( standbyConfig == STDBY_RC )
+    {
+        SX126xSetOperatingMode( MODE_STDBY_RC );
+    }
+    else
+    {
+        SX126xSetOperatingMode( MODE_STDBY_XOSC );
+    }
+}
+
+void SX126xSetFs( void )
+{
+    SX126xWriteCommand( RADIO_SET_FS, 0, 0 );
+    SX126xSetOperatingMode( MODE_FS );
+}
+
+void SX126xSetTx( uint32_t timeout )
+{
+    uint8_t buf[3];
+
+    SX126xSetOperatingMode( MODE_TX );
+
+    buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
+    buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
+    buf[2] = ( uint8_t )( timeout & 0xFF );
+    SX126xWriteCommand( RADIO_SET_TX, buf, 3 );
+}
+
+void SX126xSetRx( uint32_t timeout )
+{
+    uint8_t buf[3];
+
+    SX126xSetOperatingMode( MODE_RX );
+
+    buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
+    buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
+    buf[2] = ( uint8_t )( timeout & 0xFF );
+    SX126xWriteCommand( RADIO_SET_RX, buf, 3 );
+}
+
+void SX126xSetRxBoosted( uint32_t timeout )
+{
+    uint8_t buf[3];
+
+    SX126xSetOperatingMode( MODE_RX );
+
+    SX126xWriteRegister( REG_RX_GAIN, 0x96 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensivity
+
+    buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
+    buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
+    buf[2] = ( uint8_t )( timeout & 0xFF );
+    SX126xWriteCommand( RADIO_SET_RX, buf, 3 );
+}
+
+void SX126xSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime )
+{
+    uint8_t buf[6];
+
+    buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF );
+    buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF );
+    buf[2] = ( uint8_t )( rxTime & 0xFF );
+    buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF );
+    buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF );
+    buf[5] = ( uint8_t )( sleepTime & 0xFF );
+    SX126xWriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 );
+    SX126xSetOperatingMode( MODE_RX_DC );
+}
+
+void SX126xSetCad( void )
+{
+    SX126xWriteCommand( RADIO_SET_CAD, 0, 0 );
+    SX126xSetOperatingMode( MODE_CAD );
+}
+
+void SX126xSetTxContinuousWave( void )
+{
+    SX126xSetAntSw(MODE_TX);
+    SX126xWriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 );
+}
+
+void SX126xSetTxInfinitePreamble( void )
+{
+    SX126xWriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 );
+}
+
+void SX126xSetStopRxTimerOnPreambleDetect( bool enable )
+{
+    SX126xWriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 );
+}
+
+void SX126xSetLoRaSymbNumTimeout( uint8_t symbNum )
+{
+    SX126xWriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 );
+    
+    if( symbNum >= 64 )
+    {
+        uint8_t mant = symbNum >> 1;
+        uint8_t exp  = 0;
+        uint8_t reg  = 0;
+
+        while( mant > 31 )
+        {
+            mant >>= 2;
+            exp++;
+        }
+
+        reg = exp + ( mant << 3 );
+        SX126xWriteRegister( REG_LR_SYNCH_TIMEOUT, reg );
+    }
+}
+
+void SX126xSetRegulatorMode( RadioRegulatorMode_t mode )
+{
+    SX126xWriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 );
+}
+
+void SX126xCalibrate( CalibrationParams_t calibParam )
+{
+    uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) |
+                      ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) |
+                      ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) |
+                      ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) |
+                      ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) |
+                      ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) |
+                      ( ( uint8_t )calibParam.Fields.RC64KEnable ) );
+
+    SX126xWriteCommand( RADIO_CALIBRATE, &value, 1 );  
+}
+
+void SX126xCalibrateImage( uint32_t freq )
+{
+    uint8_t calFreq[2];
+
+    if( freq > 900000000 )
+    {
+        calFreq[0] = 0xE1;
+        calFreq[1] = 0xE9;
+    }
+    else if( freq > 850000000 )
+    {
+        calFreq[0] = 0xD7;
+        calFreq[1] = 0xDB;
+    }
+    else if( freq > 770000000 )
+    {
+        calFreq[0] = 0xC1;
+        calFreq[1] = 0xC5;
+    }
+    else if( freq > 460000000 )
+    {
+        calFreq[0] = 0x75;
+        calFreq[1] = 0x81;
+    }
+    else if( freq > 425000000 )
+    {
+        calFreq[0] = 0x6B;
+        calFreq[1] = 0x6F;
+    }
+    SX126xWriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 );
+}
+
+void SX126xSetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut )
+{
+    uint8_t buf[4];
+
+    buf[0] = paDutyCycle;
+    buf[1] = hpMax;
+    buf[2] = deviceSel;
+    buf[3] = paLut;
+    SX126xWriteCommand( RADIO_SET_PACONFIG, buf, 4 );
+}
+
+void SX126xSetRxTxFallbackMode( uint8_t fallbackMode )
+{
+    SX126xWriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 );
+}
+
+void SX126xSetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask )
+{
+    uint8_t buf[8];
+
+    buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF );
+    buf[1] = ( uint8_t )( irqMask & 0x00FF );
+    buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF );
+    buf[3] = ( uint8_t )( dio1Mask & 0x00FF );
+    buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF );
+    buf[5] = ( uint8_t )( dio2Mask & 0x00FF );
+    buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF );
+    buf[7] = ( uint8_t )( dio3Mask & 0x00FF );
+    SX126xWriteCommand( RADIO_CFG_DIOIRQ, buf, 8 );
+}
+
+uint16_t SX126xGetIrqStatus( void )
+{
+    uint8_t irqStatus[2];
+
+    SX126xReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 );
+    return ( irqStatus[0] << 8 ) | irqStatus[1];
+}
+
+void SX126xSetDio2AsRfSwitchCtrl( uint8_t enable )
+{
+    SX126xWriteCommand( RADIO_SET_RFSWITCHMODE, &enable, 1 );
+}
+
+void SX126xSetDio3AsTcxoCtrl( RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout )
+{
+    uint8_t buf[4];
+
+    buf[0] = tcxoVoltage & 0x07;
+    buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF );
+    buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF );
+    buf[3] = ( uint8_t )( timeout & 0xFF );
+
+    SX126xWriteCommand( RADIO_SET_TCXOMODE, buf, 4 );
+}
+
+void SX126xSetRfFrequency( uint32_t frequency )
+{
+    uint8_t buf[4];
+    uint32_t freq = 0;
+
+    if( ImageCalibrated == false )
+    {
+        SX126xCalibrateImage( frequency );
+        ImageCalibrated = true;
+    }
+
+    freq = ( uint32_t )( ( double )frequency / ( double )FREQ_STEP );
+    buf[0] = ( uint8_t )( ( freq >> 24 ) & 0xFF );
+    buf[1] = ( uint8_t )( ( freq >> 16 ) & 0xFF );
+    buf[2] = ( uint8_t )( ( freq >> 8 ) & 0xFF );
+    buf[3] = ( uint8_t )( freq & 0xFF );
+    SX126xWriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 );
+}
+
+void SX126xSetPacketType( RadioPacketTypes_t packetType )
+{
+    // Save packet type internally to avoid questioning the radio
+    PacketType = packetType;
+    SX126xWriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 );
+}
+
+RadioPacketTypes_t SX126xGetPacketType( void )
+{
+    return PacketType;
+}
+
+void SX126xSetTxParams( int8_t power, RadioRampTimes_t rampTime )
+{
+    uint8_t buf[2];
+
+////    if( SX126xGetDeviceId( ) == SX1261 )
+////    {
+////        if( power == 15 )
+////        {
+////            SX126xSetPaConfig( 0x06, 0x00, 0x01, 0x01 );
+////        }
+////        else
+////        {
+////            SX126xSetPaConfig( 0x04, 0x00, 0x01, 0x01 );
+////        }
+////        if( power >= 14 )
+////        {
+////            power = 14;
+////        }
+////        else if( power < -17 )
+////        {
+////            power = -17;
+////        }
+////        SX126xWriteRegister( REG_OCP, 0x18 ); // current max is 80 mA for the whole device
+////    }
+////    else // sx1262
+    {
+        // WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
+        // RegTxClampConfig = @address 0x08D8
+        SX126xWriteRegister( 0x08D8, SX126xReadRegister( 0x08D8 ) | ( 0x0F << 1 ) );
+        // WORKAROUND END
+
+        SX126xSetPaConfig( 0x04, 0x07, 0x00, 0x01 );
+        if( power > 22 )
+        {
+            power = 22;
+        }
+        else if( power < -9 ) 
+        {
+            power = -9;
+        }
+        SX126xWriteRegister( REG_OCP, 0x38 ); // current max 160mA for the whole device
+    }
+    buf[0] = power;
+    buf[1] = ( uint8_t )rampTime;
+    SX126xWriteCommand( RADIO_SET_TXPARAMS, buf, 2 );
+}
+
+void SX126xSetRfTxPower( int8_t power )
+{
+    SX126xSetTxParams( power, RADIO_RAMP_40_US );
+}
+
+void SX126xSetModulationParams( ModulationParams_t *modulationParams )
+{
+    uint8_t n;
+    uint32_t tempVal = 0;
+    uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+    // Check if required configuration corresponds to the stored packet type
+    // If not, silently update radio packet type
+    if( PacketType != modulationParams->PacketType )
+    {
+        SX126xSetPacketType( modulationParams->PacketType );
+    }
+
+    switch( modulationParams->PacketType )
+    {
+    case PACKET_TYPE_GFSK:
+        n = 8;
+        tempVal = ( uint32_t )( 32 * ( ( double )XTAL_FREQ / ( double )modulationParams->Params.Gfsk.BitRate ) );
+        buf[0] = ( tempVal >> 16 ) & 0xFF;
+        buf[1] = ( tempVal >> 8 ) & 0xFF;
+        buf[2] = tempVal & 0xFF;
+        buf[3] = modulationParams->Params.Gfsk.ModulationShaping;
+        buf[4] = modulationParams->Params.Gfsk.Bandwidth;
+        tempVal = ( uint32_t )( ( double )modulationParams->Params.Gfsk.Fdev / ( double )FREQ_STEP );
+        buf[5] = ( tempVal >> 16 ) & 0xFF;
+        buf[6] = ( tempVal >> 8 ) & 0xFF;
+        buf[7] = ( tempVal& 0xFF );
+        SX126xWriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
+        break;
+    case PACKET_TYPE_LORA:
+        n = 4;
+        buf[0] = modulationParams->Params.LoRa.SpreadingFactor;
+        buf[1] = modulationParams->Params.LoRa.Bandwidth;
+        buf[2] = modulationParams->Params.LoRa.CodingRate;
+        buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize;
+
+        SX126xWriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n );
+
+        break;
+    default:
+    case PACKET_TYPE_NONE:
+        return;
+    }
+}
+
+void SX126xSetPacketParams( PacketParams_t *packetParams )
+{
+    uint8_t n;
+    uint8_t crcVal = 0;
+    uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+    // Check if required configuration corresponds to the stored packet type
+    // If not, silently update radio packet type
+    if( PacketType != packetParams->PacketType )
+    {
+        SX126xSetPacketType( packetParams->PacketType );
+    }
+
+    switch( packetParams->PacketType )
+    {
+    case PACKET_TYPE_GFSK:
+        if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM )
+        {
+            SX126xSetCrcSeed( CRC_IBM_SEED );
+            SX126xSetCrcPolynomial( CRC_POLYNOMIAL_IBM );
+            crcVal = RADIO_CRC_2_BYTES;
+        }
+        else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT )
+        {
+            SX126xSetCrcSeed( CRC_CCITT_SEED );
+            SX126xSetCrcPolynomial( CRC_POLYNOMIAL_CCITT );
+            crcVal = RADIO_CRC_2_BYTES_INV;
+        }
+        else
+        {
+            crcVal = packetParams->Params.Gfsk.CrcLength;
+        }
+        n = 9;
+        buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF;
+        buf[1] = packetParams->Params.Gfsk.PreambleLength;
+        buf[2] = packetParams->Params.Gfsk.PreambleMinDetect;
+        buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit
+        buf[4] = packetParams->Params.Gfsk.AddrComp;
+        buf[5] = packetParams->Params.Gfsk.HeaderType;
+        buf[6] = packetParams->Params.Gfsk.PayloadLength;
+        buf[7] = crcVal;
+        buf[8] = packetParams->Params.Gfsk.DcFree;
+        break;
+    case PACKET_TYPE_LORA:
+        n = 6;
+        buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF;
+        buf[1] = packetParams->Params.LoRa.PreambleLength;
+        buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType;
+        buf[3] = packetParams->Params.LoRa.PayloadLength;
+        buf[4] = packetParams->Params.LoRa.CrcMode;
+        buf[5] = packetParams->Params.LoRa.InvertIQ;
+        break;
+    default:
+    case PACKET_TYPE_NONE:
+        return;
+    }
+    SX126xWriteCommand( RADIO_SET_PACKETPARAMS, buf, n );
+}
+
+void SX126xSetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout )
+{
+    uint8_t buf[7];
+
+    buf[0] = ( uint8_t )cadSymbolNum;
+    buf[1] = cadDetPeak;
+    buf[2] = cadDetMin;
+    buf[3] = ( uint8_t )cadExitMode;
+    buf[4] = ( uint8_t )( ( cadTimeout >> 16 ) & 0xFF );
+    buf[5] = ( uint8_t )( ( cadTimeout >> 8 ) & 0xFF );
+    buf[6] = ( uint8_t )( cadTimeout & 0xFF );
+    SX126xWriteCommand( RADIO_SET_CADPARAMS, buf, 7 );
+    SX126xSetOperatingMode( MODE_CAD );
+}
+
+void SX126xSetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress )
+{
+    uint8_t buf[2];
+
+    buf[0] = txBaseAddress;
+    buf[1] = rxBaseAddress;
+    SX126xWriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 );
+}
+
+RadioStatus_t SX126xGetStatus( void )
+{
+    uint8_t stat = 0;
+    RadioStatus_t status = { .Value = 0 };
+
+    stat = SX126xReadCommand( RADIO_GET_STATUS, NULL, 0 );
+    status.Fields.CmdStatus = ( stat & ( 0x07 << 1 ) ) >> 1;
+    status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4;
+    return status;
+}
+
+int8_t SX126xGetRssiInst( void )
+{
+    uint8_t buf[1];
+    int8_t rssi = 0;
+
+    SX126xReadCommand( RADIO_GET_RSSIINST, buf, 1 );
+    rssi = -buf[0] >> 1;
+    return rssi;
+}
+
+void SX126xGetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer )
+{
+    uint8_t status[2];
+
+    SX126xReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 );
+
+    // In case of LORA fixed header, the payloadLength is obtained by reading
+    // the register REG_LR_PAYLOADLENGTH
+    if( ( SX126xGetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) )
+    {
+        *payloadLength = SX126xReadRegister( REG_LR_PAYLOADLENGTH );
+    }
+    else
+    {
+        *payloadLength = status[0];
+    }
+    *rxStartBufferPointer = status[1];
+}
+
+void SX126xGetPacketStatus( PacketStatus_t *pktStatus )
+{
+    uint8_t status[3];
+
+    SX126xReadCommand( RADIO_GET_PACKETSTATUS, status, 3 );
+
+    pktStatus->packetType = SX126xGetPacketType( );
+    switch( pktStatus->packetType )
+    {
+        case PACKET_TYPE_GFSK:
+            pktStatus->Params.Gfsk.RxStatus = status[0];
+            pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1;
+            pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1;
+            pktStatus->Params.Gfsk.FreqError = 0;
+            break;
+
+        case PACKET_TYPE_LORA:
+            pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1;
+            // Returns SNR value [dB] rounded to the nearest integer value
+            pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2;
+            pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1;
+            pktStatus->Params.LoRa.FreqError = FrequencyError;
+            break;
+
+        default:
+        case PACKET_TYPE_NONE:
+            // In that specific case, we set everything in the pktStatus to zeros
+            // and reset the packet type accordingly
+            rt_memset( pktStatus, 0, sizeof( PacketStatus_t ) );
+            pktStatus->packetType = PACKET_TYPE_NONE;
+            break;
+    }
+}
+
+RadioError_t SX126xGetDeviceErrors( void )
+{
+    uint8_t err[] = { 0, 0 };
+    RadioError_t error = { .Value = 0 };
+
+    SX126xReadCommand( RADIO_GET_ERROR, ( uint8_t* )err, 2 );
+    error.Fields.PaRamp     = ( err[0] & ( 1 << 0 ) ) >> 0;
+    error.Fields.PllLock    = ( err[1] & ( 1 << 6 ) ) >> 6;
+    error.Fields.XoscStart  = ( err[1] & ( 1 << 5 ) ) >> 5;
+    error.Fields.ImgCalib   = ( err[1] & ( 1 << 4 ) ) >> 4;
+    error.Fields.AdcCalib   = ( err[1] & ( 1 << 3 ) ) >> 3;
+    error.Fields.PllCalib   = ( err[1] & ( 1 << 2 ) ) >> 2;
+    error.Fields.Rc13mCalib = ( err[1] & ( 1 << 1 ) ) >> 1;
+    error.Fields.Rc64kCalib = ( err[1] & ( 1 << 0 ) ) >> 0;
+    return error;
+}
+
+void SX126xClearDeviceErrors( void )
+{
+    uint8_t buf[2] = { 0x00, 0x00 };
+    SX126xWriteCommand( RADIO_CLR_ERROR, buf, 2 );
+}
+
+void SX126xClearIrqStatus( uint16_t irq )
+{
+    uint8_t buf[2];
+
+    buf[0] = ( uint8_t )( ( ( uint16_t )irq >> 8 ) & 0x00FF );
+    buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF );
+    SX126xWriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 );
+}

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx126x/sx126x.h

@@ -0,0 +1,1112 @@
+/*!
+ * \file      sx126x.h
+ *
+ * \brief     SX126x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ */
+#ifndef __SX126x_H__
+#define __SX126x_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <math.h>
+//#include "gpio.h"
+//#include "spi.h"
+#include "lora-radio.h"
+
+#define SX1261                                      1
+#define SX1262                                      2
+
+/*!
+ * Radio complete Wake-up Time with margin for temperature compensation
+ */
+#define RADIO_WAKEUP_TIME                           3 // [ms]
+
+/*!
+ * \brief Compensation delay for SetAutoTx/Rx functions in 15.625 microseconds
+ */
+#define AUTO_RX_TX_OFFSET                           2
+
+/*!
+ * \brief LFSR initial value to compute IBM type CRC
+ */
+#define CRC_IBM_SEED                                0xFFFF
+
+/*!
+ * \brief LFSR initial value to compute CCIT type CRC
+ */
+#define CRC_CCITT_SEED                              0x1D0F
+
+/*!
+ * \brief Polynomial used to compute IBM CRC
+ */
+#define CRC_POLYNOMIAL_IBM                          0x8005
+
+/*!
+ * \brief Polynomial used to compute CCIT CRC
+ */
+#define CRC_POLYNOMIAL_CCITT                        0x1021
+
+/*!
+ * \brief The address of the register holding the first byte defining the CRC seed
+ *
+ */
+#define REG_LR_CRCSEEDBASEADDR                      0x06BC
+
+/*!
+ * \brief The address of the register holding the first byte defining the CRC polynomial
+ */
+#define REG_LR_CRCPOLYBASEADDR                      0x06BE
+
+/*!
+ * \brief The address of the register holding the first byte defining the whitening seed
+ */
+#define REG_LR_WHITSEEDBASEADDR_MSB                 0x06B8
+#define REG_LR_WHITSEEDBASEADDR_LSB                 0x06B9
+
+/*!
+ * \brief The address of the register holding the packet configuration
+ */
+#define REG_LR_PACKETPARAMS                         0x0704
+
+/*!
+ * \brief The address of the register holding the payload size
+ */
+ 
+#define REG_LR_PAYLOADLENGTH                        0x0702
+/*!
+ * \brief The address of the register holding the re-calculated number of symbols
+ */
+#define REG_LR_SYNCH_TIMEOUT                        0x0706
+/*!
+ * \brief The addresses of the registers holding SyncWords values
+ */
+#define REG_LR_SYNCWORDBASEADDRESS                  0x06C0
+
+/*!
+ * \brief The addresses of the register holding LoRa Modem SyncWord value
+ */
+#define REG_LR_SYNCWORD                             0x0740
+
+/*!
+ * Syncword for Private LoRa networks
+ */
+#define LORA_MAC_PRIVATE_SYNCWORD                   0x1424
+
+/*!
+ * Syncword for Public LoRa networks
+ */
+#define LORA_MAC_PUBLIC_SYNCWORD                    0x3444
+
+/*!
+ * The address of the register giving a 4 bytes random number
+ */
+#define RANDOM_NUMBER_GENERATORBASEADDR             0x0819
+
+/*!
+ * The address of the register used to disable the LNA
+ */
+#define REG_ANA_LNA                                 0x08E2
+
+/*!
+ * The address of the register used to disable the mixer
+ */
+#define REG_ANA_MIXER                               0x08E5
+
+/*!
+ * The address of the register holding RX Gain value (0x94: power saving, 0x96: rx boosted)
+ */
+#define REG_RX_GAIN                                 0x08AC
+
+/*!
+ * Change the value on the device internal trimming capacitor
+ */
+#define REG_XTA_TRIM                                0x0911
+
+/*!
+ * Set the current max value in the over current protection
+ */
+#define REG_OCP                                     0x08E7
+
+/*!
+ * \brief Structure describing the radio status
+ */
+typedef union RadioStatus_u
+{
+    uint8_t Value;
+    struct
+    {   //bit order is lsb -> msb
+        uint8_t           : 1;  //!< Reserved
+        uint8_t CmdStatus : 3;  //!< Command status
+        uint8_t ChipMode  : 3;  //!< Chip mode
+        uint8_t           : 1;  //!< Reserved
+    }Fields;
+}RadioStatus_t;
+
+/*!
+ * \brief Structure describing the error codes for callback functions
+ */
+typedef enum
+{
+    IRQ_HEADER_ERROR_CODE                   = 0x01,
+    IRQ_SYNCWORD_ERROR_CODE                 = 0x02,
+    IRQ_CRC_ERROR_CODE                      = 0x04,
+}IrqErrorCode_t;
+
+enum IrqPblSyncHeaderCode_t
+{
+    IRQ_PBL_DETECT_CODE                     = 0x01,
+    IRQ_SYNCWORD_VALID_CODE                 = 0x02,
+    IRQ_HEADER_VALID_CODE                   = 0x04,
+};
+
+/*!
+ * \brief Represents the operating mode the radio is actually running
+ */
+typedef enum
+{
+    MODE_SLEEP                              = 0x00,         //! The radio is in sleep mode
+    MODE_STDBY_RC,                                          //! The radio is in standby mode with RC oscillator
+    MODE_STDBY_XOSC,                                        //! The radio is in standby mode with XOSC oscillator
+    MODE_FS,                                                //! The radio is in frequency synthesis mode
+    MODE_TX,                                                //! The radio is in transmit mode
+    MODE_RX,                                                //! The radio is in receive mode
+    MODE_RX_DC,                                             //! The radio is in receive duty cycle mode
+    MODE_CAD                                                //! The radio is in channel activity detection mode
+}RadioOperatingModes_t;
+
+/*!
+ * \brief Declares the oscillator in use while in standby mode
+ *
+ * Using the STDBY_RC standby mode allow to reduce the energy consumption
+ * STDBY_XOSC should be used for time critical applications
+ */
+typedef enum
+{
+    STDBY_RC                                = 0x00,
+    STDBY_XOSC                              = 0x01,
+}RadioStandbyModes_t;
+
+/*!
+ * \brief Declares the power regulation used to power the device
+ *
+ * This command allows the user to specify if DC-DC or LDO is used for power regulation.
+ * Using only LDO implies that the Rx or Tx current is doubled
+ */
+typedef enum
+{
+    USE_LDO                                 = 0x00, // default
+    USE_DCDC                                = 0x01,
+}RadioRegulatorMode_t;
+
+/*!
+ * \brief Represents the possible packet type (i.e. modem) used
+ */
+typedef enum
+{
+    PACKET_TYPE_GFSK                        = 0x00,
+    PACKET_TYPE_LORA                        = 0x01,
+    PACKET_TYPE_NONE                        = 0x0F,
+}RadioPacketTypes_t;
+
+/*!
+ * \brief Represents the ramping time for power amplifier
+ */
+typedef enum
+{
+    RADIO_RAMP_10_US                        = 0x00,
+    RADIO_RAMP_20_US                        = 0x01,
+    RADIO_RAMP_40_US                        = 0x02,
+    RADIO_RAMP_80_US                        = 0x03,
+    RADIO_RAMP_200_US                       = 0x04,
+    RADIO_RAMP_800_US                       = 0x05,
+    RADIO_RAMP_1700_US                      = 0x06,
+    RADIO_RAMP_3400_US                      = 0x07,
+}RadioRampTimes_t;
+
+/*!
+ * \brief Represents the number of symbols to be used for channel activity detection operation
+ */
+typedef enum
+{
+    LORA_CAD_01_SYMBOL                      = 0x00,
+    LORA_CAD_02_SYMBOL                      = 0x01,
+    LORA_CAD_04_SYMBOL                      = 0x02,
+    LORA_CAD_08_SYMBOL                      = 0x03,
+    LORA_CAD_16_SYMBOL                      = 0x04,
+}RadioLoRaCadSymbols_t;
+
+/*!
+ * \brief Represents the Channel Activity Detection actions after the CAD operation is finished
+ */
+typedef enum
+{
+    LORA_CAD_ONLY                           = 0x00,
+    LORA_CAD_RX                             = 0x01,
+    LORA_CAD_LBT                            = 0x10,
+}RadioCadExitModes_t;
+
+/*!
+ * \brief Represents the modulation shaping parameter
+ */
+typedef enum
+{
+    MOD_SHAPING_OFF                         = 0x00,
+    MOD_SHAPING_G_BT_03                     = 0x08,
+    MOD_SHAPING_G_BT_05                     = 0x09,
+    MOD_SHAPING_G_BT_07                     = 0x0A,
+    MOD_SHAPING_G_BT_1                      = 0x0B,
+}RadioModShapings_t;
+
+/*!
+ * \brief Represents the modulation shaping parameter
+ */
+typedef enum
+{
+    RX_BW_4800                              = 0x1F,
+    RX_BW_5800                              = 0x17,
+    RX_BW_7300                              = 0x0F,
+    RX_BW_9700                              = 0x1E,
+    RX_BW_11700                             = 0x16,
+    RX_BW_14600                             = 0x0E,
+    RX_BW_19500                             = 0x1D,
+    RX_BW_23400                             = 0x15,
+    RX_BW_29300                             = 0x0D,
+    RX_BW_39000                             = 0x1C,
+    RX_BW_46900                             = 0x14,
+    RX_BW_58600                             = 0x0C,
+    RX_BW_78200                             = 0x1B,
+    RX_BW_93800                             = 0x13,
+    RX_BW_117300                            = 0x0B,
+    RX_BW_156200                            = 0x1A,
+    RX_BW_187200                            = 0x12,
+    RX_BW_234300                            = 0x0A,
+    RX_BW_312000                            = 0x19,
+    RX_BW_373600                            = 0x11,
+    RX_BW_467000                            = 0x09,
+}RadioRxBandwidth_t;
+
+/*!
+ * \brief Represents the possible spreading factor values in LoRa packet types
+ */
+typedef enum
+{
+    LORA_SF5                                = 0x05,
+    LORA_SF6                                = 0x06,
+    LORA_SF7                                = 0x07,
+    LORA_SF8                                = 0x08,
+    LORA_SF9                                = 0x09,
+    LORA_SF10                               = 0x0A,
+    LORA_SF11                               = 0x0B,
+    LORA_SF12                               = 0x0C,
+}RadioLoRaSpreadingFactors_t;
+
+/*!
+ * \brief Represents the bandwidth values for LoRa packet type
+ */
+typedef enum
+{
+    LORA_BW_500                             = 6,
+    LORA_BW_250                             = 5,
+    LORA_BW_125                             = 4,
+    LORA_BW_062                             = 3,
+    LORA_BW_041                             = 10,
+    LORA_BW_031                             = 2,
+    LORA_BW_020                             = 9,
+    LORA_BW_015                             = 1,
+    LORA_BW_010                             = 8,
+    LORA_BW_007                             = 0,
+}RadioLoRaBandwidths_t;
+
+/*!
+ * \brief Represents the coding rate values for LoRa packet type
+ */
+typedef enum
+{
+    LORA_CR_4_5                             = 0x01,
+    LORA_CR_4_6                             = 0x02,
+    LORA_CR_4_7                             = 0x03,
+    LORA_CR_4_8                             = 0x04,
+}RadioLoRaCodingRates_t;
+
+/*!
+ * \brief Represents the preamble length used to detect the packet on Rx side
+ */
+typedef enum
+{
+    RADIO_PREAMBLE_DETECTOR_OFF             = 0x00,         //!< Preamble detection length off
+    RADIO_PREAMBLE_DETECTOR_08_BITS         = 0x04,         //!< Preamble detection length 8 bits
+    RADIO_PREAMBLE_DETECTOR_16_BITS         = 0x05,         //!< Preamble detection length 16 bits
+    RADIO_PREAMBLE_DETECTOR_24_BITS         = 0x06,         //!< Preamble detection length 24 bits
+    RADIO_PREAMBLE_DETECTOR_32_BITS         = 0x07,         //!< Preamble detection length 32 bit
+}RadioPreambleDetection_t;
+
+/*!
+ * \brief Represents the possible combinations of SyncWord correlators activated
+ */
+typedef enum
+{
+    RADIO_ADDRESSCOMP_FILT_OFF              = 0x00,         //!< No correlator turned on, i.e. do not search for SyncWord
+    RADIO_ADDRESSCOMP_FILT_NODE             = 0x01,
+    RADIO_ADDRESSCOMP_FILT_NODE_BROAD       = 0x02,
+}RadioAddressComp_t;
+
+/*!
+ *  \brief Radio GFSK packet length mode
+ */
+typedef enum
+{
+    RADIO_PACKET_FIXED_LENGTH               = 0x00,         //!< The packet is known on both sides, no header included in the packet
+    RADIO_PACKET_VARIABLE_LENGTH            = 0x01,         //!< The packet is on variable size, header included
+}RadioPacketLengthModes_t;
+
+/*!
+ * \brief Represents the CRC length
+ */
+typedef enum
+{
+    RADIO_CRC_OFF                           = 0x01,         //!< No CRC in use
+    RADIO_CRC_1_BYTES                       = 0x00,
+    RADIO_CRC_2_BYTES                       = 0x02,
+    RADIO_CRC_1_BYTES_INV                   = 0x04,
+    RADIO_CRC_2_BYTES_INV                   = 0x06,
+    RADIO_CRC_2_BYTES_IBM                   = 0xF1,
+    RADIO_CRC_2_BYTES_CCIT                  = 0xF2,
+}RadioCrcTypes_t;
+
+/*!
+ * \brief Radio whitening mode activated or deactivated
+ */
+typedef enum
+{
+    RADIO_DC_FREE_OFF                       = 0x00,
+    RADIO_DC_FREEWHITENING                  = 0x01,
+}RadioDcFree_t;
+
+/*!
+ * \brief Holds the Radio lengths mode for the LoRa packet type
+ */
+typedef enum
+{
+    LORA_PACKET_VARIABLE_LENGTH             = 0x00,         //!< The packet is on variable size, header included
+    LORA_PACKET_FIXED_LENGTH                = 0x01,         //!< The packet is known on both sides, no header included in the packet
+    LORA_PACKET_EXPLICIT                    = LORA_PACKET_VARIABLE_LENGTH,
+    LORA_PACKET_IMPLICIT                    = LORA_PACKET_FIXED_LENGTH,
+}RadioLoRaPacketLengthsMode_t;
+
+/*!
+ * \brief Represents the CRC mode for LoRa packet type
+ */
+typedef enum
+{
+    LORA_CRC_ON                             = 0x01,         //!< CRC activated
+    LORA_CRC_OFF                            = 0x00,         //!< CRC not used
+}RadioLoRaCrcModes_t;
+
+/*!
+ * \brief Represents the IQ mode for LoRa packet type
+ */
+typedef enum
+{
+    LORA_IQ_NORMAL                          = 0x00,
+    LORA_IQ_INVERTED                        = 0x01,
+}RadioLoRaIQModes_t;
+
+/*!
+ * \brief Represents the voltage used to control the TCXO on/off from DIO3
+ */
+typedef enum
+{
+    TCXO_CTRL_1_6V                          = 0x00,
+    TCXO_CTRL_1_7V                          = 0x01,
+    TCXO_CTRL_1_8V                          = 0x02,
+    TCXO_CTRL_2_2V                          = 0x03,
+    TCXO_CTRL_2_4V                          = 0x04,
+    TCXO_CTRL_2_7V                          = 0x05,
+    TCXO_CTRL_3_0V                          = 0x06,
+    TCXO_CTRL_3_3V                          = 0x07,
+}RadioTcxoCtrlVoltage_t;
+
+/*!
+ * \brief Represents the interruption masks available for the radio
+ *
+ * \remark Note that not all these interruptions are available for all packet types
+ */
+typedef enum
+{
+    IRQ_RADIO_NONE                          = 0x0000,
+    IRQ_TX_DONE                             = 0x0001,
+    IRQ_RX_DONE                             = 0x0002,
+    IRQ_PREAMBLE_DETECTED                   = 0x0004,
+    IRQ_SYNCWORD_VALID                      = 0x0008,
+    IRQ_HEADER_VALID                        = 0x0010,
+    IRQ_HEADER_ERROR                        = 0x0020,
+    IRQ_CRC_ERROR                           = 0x0040,
+    IRQ_CAD_DONE                            = 0x0080,
+    IRQ_CAD_ACTIVITY_DETECTED               = 0x0100,
+    IRQ_RX_TX_TIMEOUT                       = 0x0200,
+    IRQ_RADIO_ALL                           = 0xFFFF,
+}RadioIrqMasks_t;
+
+/*!
+ * \brief Represents all possible opcode understood by the radio
+ */
+typedef enum RadioCommands_e
+{
+    RADIO_GET_STATUS                        = 0xC0,
+    RADIO_WRITE_REGISTER                    = 0x0D,
+    RADIO_READ_REGISTER                     = 0x1D,
+    RADIO_WRITE_BUFFER                      = 0x0E,
+    RADIO_READ_BUFFER                       = 0x1E,
+    RADIO_SET_SLEEP                         = 0x84,
+    RADIO_SET_STANDBY                       = 0x80,
+    RADIO_SET_FS                            = 0xC1,
+    RADIO_SET_TX                            = 0x83,
+    RADIO_SET_RX                            = 0x82,
+    RADIO_SET_RXDUTYCYCLE                   = 0x94,
+    RADIO_SET_CAD                           = 0xC5,
+    RADIO_SET_TXCONTINUOUSWAVE              = 0xD1,
+    RADIO_SET_TXCONTINUOUSPREAMBLE          = 0xD2,
+    RADIO_SET_PACKETTYPE                    = 0x8A,
+    RADIO_GET_PACKETTYPE                    = 0x11,
+    RADIO_SET_RFFREQUENCY                   = 0x86,
+    RADIO_SET_TXPARAMS                      = 0x8E,
+    RADIO_SET_PACONFIG                      = 0x95,
+    RADIO_SET_CADPARAMS                     = 0x88,
+    RADIO_SET_BUFFERBASEADDRESS             = 0x8F,
+    RADIO_SET_MODULATIONPARAMS              = 0x8B,
+    RADIO_SET_PACKETPARAMS                  = 0x8C,
+    RADIO_GET_RXBUFFERSTATUS                = 0x13,
+    RADIO_GET_PACKETSTATUS                  = 0x14,
+    RADIO_GET_RSSIINST                      = 0x15,
+    RADIO_GET_STATS                         = 0x10,
+    RADIO_RESET_STATS                       = 0x00,
+    RADIO_CFG_DIOIRQ                        = 0x08,
+    RADIO_GET_IRQSTATUS                     = 0x12,
+    RADIO_CLR_IRQSTATUS                     = 0x02,
+    RADIO_CALIBRATE                         = 0x89,
+    RADIO_CALIBRATEIMAGE                    = 0x98,
+    RADIO_SET_REGULATORMODE                 = 0x96,
+    RADIO_GET_ERROR                         = 0x17,
+    RADIO_CLR_ERROR                         = 0x07,
+    RADIO_SET_TCXOMODE                      = 0x97,
+    RADIO_SET_TXFALLBACKMODE                = 0x93,
+    RADIO_SET_RFSWITCHMODE                  = 0x9D,
+    RADIO_SET_STOPRXTIMERONPREAMBLE         = 0x9F,
+    RADIO_SET_LORASYMBTIMEOUT               = 0xA0,
+}RadioCommands_t;
+
+/*!
+ * \brief The type describing the modulation parameters for every packet types
+ */
+typedef struct
+{
+    RadioPacketTypes_t                   PacketType;        //!< Packet to which the modulation parameters are referring to.
+    struct
+    {
+        struct
+        {
+            uint32_t                     BitRate;
+            uint32_t                     Fdev;
+            RadioModShapings_t           ModulationShaping;
+            uint8_t                      Bandwidth;
+        }Gfsk;
+        struct
+        {
+            RadioLoRaSpreadingFactors_t  SpreadingFactor;   //!< Spreading Factor for the LoRa modulation
+            RadioLoRaBandwidths_t        Bandwidth;         //!< Bandwidth for the LoRa modulation
+            RadioLoRaCodingRates_t       CodingRate;        //!< Coding rate for the LoRa modulation
+            uint8_t                      LowDatarateOptimize; //!< Indicates if the modem uses the low datarate optimization
+        }LoRa;
+    }Params;                                                //!< Holds the modulation parameters structure
+}ModulationParams_t;
+
+/*!
+ * \brief The type describing the packet parameters for every packet types
+ */
+typedef struct
+{
+    RadioPacketTypes_t                    PacketType;        //!< Packet to which the packet parameters are referring to.
+    struct
+    {
+        /*!
+         * \brief Holds the GFSK packet parameters
+         */
+        struct
+        {
+            uint16_t                     PreambleLength;    //!< The preamble Tx length for GFSK packet type in bit
+            RadioPreambleDetection_t     PreambleMinDetect; //!< The preamble Rx length minimal for GFSK packet type
+            uint8_t                      SyncWordLength;    //!< The synchronization word length for GFSK packet type
+            RadioAddressComp_t           AddrComp;          //!< Activated SyncWord correlators
+            RadioPacketLengthModes_t     HeaderType;        //!< If the header is explicit, it will be transmitted in the GFSK packet. If the header is implicit, it will not be transmitted
+            uint8_t                      PayloadLength;     //!< Size of the payload in the GFSK packet
+            RadioCrcTypes_t              CrcLength;         //!< Size of the CRC block in the GFSK packet
+            RadioDcFree_t                DcFree;
+        }Gfsk;
+        /*!
+         * \brief Holds the LoRa packet parameters
+         */
+        struct
+        {
+            uint16_t                     PreambleLength;    //!< The preamble length is the number of LoRa symbols in the preamble
+            RadioLoRaPacketLengthsMode_t HeaderType;        //!< If the header is explicit, it will be transmitted in the LoRa packet. If the header is implicit, it will not be transmitted
+            uint8_t                      PayloadLength;     //!< Size of the payload in the LoRa packet
+            RadioLoRaCrcModes_t          CrcMode;           //!< Size of CRC block in LoRa packet
+            RadioLoRaIQModes_t           InvertIQ;          //!< Allows to swap IQ for LoRa packet
+        }LoRa;
+    }Params;                                                //!< Holds the packet parameters structure
+}PacketParams_t;
+
+/*!
+ * \brief Represents the packet status for every packet type
+ */
+typedef struct
+{
+    RadioPacketTypes_t                    packetType;      //!< Packet to which the packet status are referring to.
+    struct
+    {
+        struct
+        {
+            uint8_t RxStatus;
+            int8_t RssiAvg;                                //!< The averaged RSSI
+            int8_t RssiSync;                               //!< The RSSI measured on last packet
+            uint32_t FreqError;
+        }Gfsk;
+        struct
+        {
+            int8_t RssiPkt;                                //!< The RSSI of the last packet
+            int8_t SnrPkt;                                 //!< The SNR of the last packet
+            int8_t SignalRssiPkt;
+            uint32_t FreqError;
+        }LoRa;
+    }Params;
+}PacketStatus_t;
+
+/*!
+ * \brief Represents the Rx internal counters values when GFSK or LoRa packet type is used
+ */
+typedef struct
+{
+    RadioPacketTypes_t                    packetType;       //!< Packet to which the packet status are referring to.
+    uint16_t PacketReceived;
+    uint16_t CrcOk;
+    uint16_t LengthError;
+}RxCounter_t;
+
+/*!
+ * \brief Represents a calibration configuration
+ */
+typedef union
+{
+    struct
+    {
+        uint8_t RC64KEnable    : 1;                             //!< Calibrate RC64K clock
+        uint8_t RC13MEnable    : 1;                             //!< Calibrate RC13M clock
+        uint8_t PLLEnable      : 1;                             //!< Calibrate PLL
+        uint8_t ADCPulseEnable : 1;                             //!< Calibrate ADC Pulse
+        uint8_t ADCBulkNEnable : 1;                             //!< Calibrate ADC bulkN
+        uint8_t ADCBulkPEnable : 1;                             //!< Calibrate ADC bulkP
+        uint8_t ImgEnable      : 1;
+        uint8_t                : 1;
+    }Fields;
+    uint8_t Value;
+}CalibrationParams_t;
+
+/*!
+ * \brief Represents a sleep mode configuration
+ */
+typedef union
+{
+    struct
+    {
+        uint8_t WakeUpRTC               : 1;                    //!< Get out of sleep mode if wakeup signal received from RTC
+        uint8_t Reset                   : 1;
+        uint8_t WarmStart               : 1;
+        uint8_t Reserved                : 5;
+    }Fields;
+    uint8_t Value;
+}SleepParams_t;
+
+/*!
+ * \brief Represents the possible radio system error states
+ */
+typedef union
+{
+    struct
+    {
+        uint8_t Rc64kCalib              : 1;                    //!< RC 64kHz oscillator calibration failed
+        uint8_t Rc13mCalib              : 1;                    //!< RC 13MHz oscillator calibration failed
+        uint8_t PllCalib                : 1;                    //!< PLL calibration failed
+        uint8_t AdcCalib                : 1;                    //!< ADC calibration failed
+        uint8_t ImgCalib                : 1;                    //!< Image calibration failed
+        uint8_t XoscStart               : 1;                    //!< XOSC oscillator failed to start
+        uint8_t PllLock                 : 1;                    //!< PLL lock failed
+        uint8_t                         : 1;                    //!< Buck converter failed to start
+        uint8_t PaRamp                  : 1;                    //!< PA ramp failed
+        uint8_t                         : 7;                    //!< Reserved
+    }Fields;
+    uint16_t Value;
+}RadioError_t;
+
+/*!
+ * Radio hardware and global parameters
+ */
+typedef struct SX126x_s
+{
+    struct rt_spi_device *spi;
+
+    PacketParams_t PacketParams;
+    PacketStatus_t PacketStatus;
+    ModulationParams_t ModulationParams;
+}SX126x_t;
+
+/*!
+ * Hardware IO IRQ callback function definition
+ */
+typedef void ( DioIrqHandler )( void* context );
+
+/*!
+ * SX126x definitions
+ */
+
+/*!
+ * \brief Provides the frequency of the chip running on the radio and the frequency step
+ *
+ * \remark These defines are used for computing the frequency divider to set the RF frequency
+ */
+#define XTAL_FREQ                                   ( double )32000000
+#define FREQ_DIV                                    ( double )pow( 2.0, 25.0 )
+#define FREQ_STEP                                   ( double )( XTAL_FREQ / FREQ_DIV )
+
+#define RX_BUFFER_SIZE                              256
+
+/*!
+ * \brief The radio callbacks structure
+ * Holds function pointers to be called on radio interrupts
+ */
+typedef struct
+{
+    void ( *txDone )( void );                       //!< Pointer to a function run on successful transmission
+    void ( *rxDone )( void );                       //!< Pointer to a function run on successful reception
+    void ( *rxPreambleDetect )( void );             //!< Pointer to a function run on successful Preamble detection
+    void ( *rxSyncWordDone )( void );               //!< Pointer to a function run on successful SyncWord reception
+    void ( *rxHeaderDone )( bool isOk );            //!< Pointer to a function run on successful Header reception
+    void ( *txTimeout )( void );                    //!< Pointer to a function run on transmission timeout
+    void ( *rxTimeout )( void );                    //!< Pointer to a function run on reception timeout
+    void ( *rxError )( IrqErrorCode_t errCode );    //!< Pointer to a function run on reception error
+    void ( *cadDone )( bool cadFlag );              //!< Pointer to a function run on channel activity detected
+}SX126xCallbacks_t;
+
+/*!
+ * ============================================================================
+ * Public functions prototypes
+ * ============================================================================
+ */
+ 
+/*!
+ * \brief Initializes the radio driver
+ */
+void SX126xInit( DioIrqHandler dioIrq );
+
+/*!
+ * \brief Gets the current Radio OperationMode variable
+ *
+ * \retval      RadioOperatingModes_t last operating mode
+ */
+RadioOperatingModes_t SX126xGetOperatingMode( void );
+
+/*!
+ * \brief Sets/Updates the current Radio OperationMode variable.
+ *
+ * \remark WARNING: This function is only required to reflect the current radio
+ *                  operating mode when processing interrupts.
+ *
+ * \param [in] mode           New operating mode
+ */
+void SX126xSetOperatingMode( RadioOperatingModes_t mode );
+
+/*!
+ * \brief Wakeup the radio if it is in Sleep mode and check that Busy is low
+ */
+void SX126xCheckDeviceReady( void );
+
+/*!
+ * \brief Saves the payload to be send in the radio buffer
+ *
+ * \param [in]  payload       A pointer to the payload
+ * \param [in]  size          The size of the payload
+ */
+void SX126xSetPayload( uint8_t *payload, uint8_t size );
+
+/*!
+ * \brief Reads the payload received. If the received payload is longer
+ * than maxSize, then the method returns 1 and do not set size and payload.
+ *
+ * \param [out] payload       A pointer to a buffer into which the payload will be copied
+ * \param [out] size          A pointer to the size of the payload received
+ * \param [in]  maxSize       The maximal size allowed to copy into the buffer
+ */
+uint8_t SX126xGetPayload( uint8_t *payload, uint8_t *size, uint8_t maxSize );
+
+/*!
+ * \brief Sends a payload
+ *
+ * \param [in]  payload       A pointer to the payload to send
+ * \param [in]  size          The size of the payload to send
+ * \param [in]  timeout       The timeout for Tx operation
+ */
+void SX126xSendPayload( uint8_t *payload, uint8_t size, uint32_t timeout );
+
+/*!
+ * \brief Sets the Sync Word given by index used in GFSK
+ *
+ * \param [in]  syncWord      SyncWord bytes ( 8 bytes )
+ *
+ * \retval      status        [0: OK, 1: NOK]
+ */
+uint8_t SX126xSetSyncWord( uint8_t *syncWord );
+
+/*!
+ * \brief Sets the Initial value for the LFSR used for the CRC calculation
+ *
+ * \param [in]  seed          Initial LFSR value ( 2 bytes )
+ *
+ */
+void SX126xSetCrcSeed( uint16_t seed );
+
+/*!
+ * \brief Sets the seed used for the CRC calculation
+ *
+ * \param [in]  seed          The seed value
+ *
+ */
+void SX126xSetCrcPolynomial( uint16_t polynomial );
+
+/*!
+ * \brief Sets the Initial value of the LFSR used for the whitening in GFSK protocols
+ *
+ * \param [in]  seed          Initial LFSR value
+ */
+void SX126xSetWhiteningSeed( uint16_t seed );
+
+/*!
+ * \brief Gets a 32-bit random value generated by the radio
+ *
+ * \remark A valid packet type must have been configured with \ref SX126xSetPacketType
+ *         before using this command.
+ *
+ * \remark The radio must be in reception mode before executing this function
+ *         This code can potentially result in interrupt generation. It is the responsibility of
+ *         the calling code to disable radio interrupts before calling this function,
+ *         and re-enable them afterwards if necessary, or be certain that any interrupts
+ *         generated during this process will not cause undesired side-effects in the software.
+ *
+ *         Please note that the random numbers produced by the generator do not have a uniform or Gaussian distribution. If
+ *         uniformity is needed, perform appropriate software post-processing.
+ *
+ * \retval randomValue    32 bits random value
+ */
+uint32_t SX126xGetRandom( void );
+
+/*!
+ * \brief Sets the radio in sleep mode
+ *
+ * \param [in]  sleepConfig   The sleep configuration describing data
+ *                            retention and RTC wake-up
+ */
+void SX126xSetSleep( SleepParams_t sleepConfig );
+
+/*!
+ * \brief Sets the radio in configuration mode
+ *
+ * \param [in]  mode          The standby mode to put the radio into
+ */
+void SX126xSetStandby( RadioStandbyModes_t mode );
+
+/*!
+ * \brief Sets the radio in FS mode
+ */
+void SX126xSetFs( void );
+
+/*!
+ * \brief Sets the radio in transmission mode
+ *
+ * \param [in]  timeout       Structure describing the transmission timeout value
+ */
+void SX126xSetTx( uint32_t timeout );
+
+/*!
+ * \brief Sets the radio in reception mode
+ *
+ * \param [in]  timeout       Structure describing the reception timeout value
+ */
+void SX126xSetRx( uint32_t timeout );
+
+/*!
+ * \brief Sets the radio in reception mode with Boosted LNA gain
+ *
+ * \param [in]  timeout       Structure describing the reception timeout value
+ */
+void SX126xSetRxBoosted( uint32_t timeout );
+
+/*!
+ * \brief Sets the Rx duty cycle management parameters
+ *
+ * \param [in]  rxTime        Structure describing reception timeout value
+ * \param [in]  sleepTime     Structure describing sleep timeout value
+ */
+void SX126xSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime );
+
+/*!
+ * \brief Sets the radio in CAD mode
+ */
+void SX126xSetCad( void );
+
+/*!
+ * \brief Sets the radio output power.
+ *
+ * \param [IN] power Sets the RF output power
+ */
+void SX126xSetRfTxPower( int8_t power );
+
+/*!
+ * \brief Sets the radio in continuous wave transmission mode
+ */
+void SX126xSetTxContinuousWave( void );
+
+/*!
+ * \brief Sets the radio in continuous preamble transmission mode
+ */
+void SX126xSetTxInfinitePreamble( void );
+
+/*!
+ * \brief Decide which interrupt will stop the internal radio rx timer.
+ *
+ * \param [in]  enable          [0: Timer stop after header/syncword detection
+ *                               1: Timer stop after preamble detection]
+ */
+void SX126xSetStopRxTimerOnPreambleDetect( bool enable );
+
+/*!
+ * \brief Set the number of symbol the radio will wait to validate a reception
+ *
+ * \param [in]  SymbNum          number of LoRa symbols
+ */
+void SX126xSetLoRaSymbNumTimeout( uint8_t SymbNum );
+
+/*!
+ * \brief Sets the power regulators operating mode
+ *
+ * \param [in]  mode          [0: LDO, 1:DC_DC]
+ */
+void SX126xSetRegulatorMode( RadioRegulatorMode_t mode );
+
+/*!
+ * \brief Calibrates the given radio block
+ *
+ * \param [in]  calibParam    The description of blocks to be calibrated
+ */
+void SX126xCalibrate( CalibrationParams_t calibParam );
+
+/*!
+ * \brief Calibrates the Image rejection depending of the frequency
+ *
+ * \param [in]  freq    The operating frequency
+ */
+void SX126xCalibrateImage( uint32_t freq );
+
+/*!
+ * \brief Activate the extention of the timeout when long preamble is used
+ *
+ * \param [in]  enable      The radio will extend the timeout to cope with long preamble
+ */
+void SX126xSetLongPreamble( uint8_t enable );
+
+/*!
+ * \brief Sets the transmission parameters
+ *
+ * \param [in]  paDutyCycle     Duty Cycle for the PA
+ * \param [in]  hpMax          0 for sx1261, 7 for sx1262
+ * \param [in]  deviceSel       1 for sx1261, 0 for sx1262
+ * \param [in]  paLut           0 for 14dBm LUT, 1 for 22dBm LUT
+ */
+void SX126xSetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut );
+
+/*!
+ * \brief Defines into which mode the chip goes after a TX / RX done
+ *
+ * \param [in]  fallbackMode    The mode in which the radio goes
+ */
+void SX126xSetRxTxFallbackMode( uint8_t fallbackMode );
+
+/*!
+ * \brief   Sets the IRQ mask and DIO masks
+ *
+ * \param [in]  irqMask       General IRQ mask
+ * \param [in]  dio1Mask      DIO1 mask
+ * \param [in]  dio2Mask      DIO2 mask
+ * \param [in]  dio3Mask      DIO3 mask
+ */
+void SX126xSetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask );
+
+/*!
+ * \brief Returns the current IRQ status
+ *
+ * \retval      irqStatus     IRQ status
+ */
+uint16_t SX126xGetIrqStatus( void );
+
+/*!
+ * \brief Indicates if DIO2 is used to control an RF Switch
+ *
+ * \param [in] enable     true of false
+ */
+void SX126xSetDio2AsRfSwitchCtrl( uint8_t enable );
+
+/*!
+ * \brief Indicates if the Radio main clock is supplied from a tcxo
+ *
+ * \param [in] tcxoVoltage     voltage used to control the TCXO
+ * \param [in] timeout         time given to the TCXO to go to 32MHz
+ */
+void SX126xSetDio3AsTcxoCtrl( RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout );
+
+/*!
+ * \brief Sets the RF frequency
+ *
+ * \param [in]  frequency     RF frequency [Hz]
+ */
+void SX126xSetRfFrequency( uint32_t frequency );
+
+/*!
+ * \brief Sets the radio for the given protocol
+ *
+ * \param [in]  packetType    [PACKET_TYPE_GFSK, PACKET_TYPE_LORA]
+ *
+ * \remark This method has to be called before SetRfFrequency,
+ *         SetModulationParams and SetPacketParams
+ */
+void SX126xSetPacketType( RadioPacketTypes_t packetType );
+
+/*!
+ * \brief Gets the current radio protocol
+ *
+ * \retval      packetType    [PACKET_TYPE_GFSK, PACKET_TYPE_LORA]
+ */
+RadioPacketTypes_t SX126xGetPacketType( void );
+
+/*!
+ * \brief Sets the transmission parameters
+ *
+ * \param [in]  power         RF output power [-18..13] dBm
+ * \param [in]  rampTime      Transmission ramp up time
+ */
+void SX126xSetTxParams( int8_t power, RadioRampTimes_t rampTime );
+
+/*!
+ * \brief Set the modulation parameters
+ *
+ * \param [in]  modParams     A structure describing the modulation parameters
+ */
+void SX126xSetModulationParams( ModulationParams_t *modParams );
+
+/*!
+ * \brief Sets the packet parameters
+ *
+ * \param [in]  packetParams  A structure describing the packet parameters
+ */
+void SX126xSetPacketParams( PacketParams_t *packetParams );
+
+/*!
+ * \brief Sets the Channel Activity Detection (CAD) parameters
+ *
+ * \param [in]  cadSymbolNum   The number of symbol to use for CAD operations
+ *                             [LORA_CAD_01_SYMBOL, LORA_CAD_02_SYMBOL,
+ *                              LORA_CAD_04_SYMBOL, LORA_CAD_08_SYMBOL,
+ *                              LORA_CAD_16_SYMBOL]
+ * \param [in]  cadDetPeak     Limit for detection of SNR peak used in the CAD
+ * \param [in]  cadDetMin      Set the minimum symbol recognition for CAD
+ * \param [in]  cadExitMode    Operation to be done at the end of CAD action
+ *                             [LORA_CAD_ONLY, LORA_CAD_RX, LORA_CAD_LBT]
+ * \param [in]  cadTimeout     Defines the timeout value to abort the CAD activity
+ */
+void SX126xSetCadParams( RadioLoRaCadSymbols_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, RadioCadExitModes_t cadExitMode, uint32_t cadTimeout );
+
+/*!
+ * \brief Sets the data buffer base address for transmission and reception
+ *
+ * \param [in]  txBaseAddress Transmission base address
+ * \param [in]  rxBaseAddress Reception base address
+ */
+void SX126xSetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress );
+
+/*!
+ * \brief Gets the current radio status
+ *
+ * \retval      status        Radio status
+ */
+RadioStatus_t SX126xGetStatus( void );
+
+/*!
+ * \brief Returns the instantaneous RSSI value for the last packet received
+ *
+ * \retval      rssiInst      Instantaneous RSSI
+ */
+int8_t SX126xGetRssiInst( void );
+
+/*!
+ * \brief Gets the last received packet buffer status
+ *
+ * \param [out] payloadLength Last received packet payload length
+ * \param [out] rxStartBuffer Last received packet buffer address pointer
+ */
+void SX126xGetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBuffer );
+
+/*!
+ * \brief Gets the last received packet payload length
+ *
+ * \param [out] pktStatus     A structure of packet status
+ */
+void SX126xGetPacketStatus( PacketStatus_t *pktStatus );
+
+/*!
+ * \brief Returns the possible system errors
+ *
+ * \retval sysErrors Value representing the possible sys failures
+ */
+RadioError_t SX126xGetDeviceErrors( void );
+
+/*!
+ * \brief Clear all the errors in the device
+ */
+void SX126xClearDeviceErrors( void );
+
+/*!
+ * \brief Clears the IRQs
+ *
+ * \param [in]  irq           IRQ(s) to be cleared
+ */
+void SX126xClearIrqStatus( uint16_t irq );
+
+/*!
+ * Radio hardware and global parameters
+ */
+extern SX126x_t SX126x;
+
+#endif // __SX126x_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/lora-radio-sx127x.c

@@ -0,0 +1,209 @@
+/*!
+ * \file      lora-radio.c for sx127x
+ *
+ * \brief     LoRa Radio interface
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+
+#include <stdlib.h>
+#include "lora-radio.h"
+#include "sx127x\sx127x.h"
+#include "sx127x-board.h"
+
+#define LOG_TAG "PHY.LoRa.SX127X"
+#define LOG_LEVEL  LOG_LVL_DBG
+#include "lora-radio-debug.h"
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+
+#define EV_LORA_RADIO_IRQ_MASK         0x0007 // DIO0 | DIO1 | DIO2 depend on board
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+static struct rt_event lora_radio_event;
+static struct rt_thread lora_radio_thread;
+static rt_uint8_t rt_lora_radio_thread_stack[4096];
+                            
+extern struct rt_spi_device *lora_radio_spi_init(const char *bus_name, const char *lora_device_name, rt_uint8_t param);
+
+#endif
+
+#endif // end of LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+
+static bool SX127xRadioInit( RadioEvents_t *events );
+
+/*!
+ * Radio driver structure initialization
+ */
+const struct Radio_s Radio =
+{
+    SX127xRadioInit,
+    SX127xGetStatus,
+    SX127xSetModem,
+    SX127xSetChannel,
+    SX127xIsChannelFree,
+    SX127xRandom,
+    SX127xSetRxConfig,
+    SX127xSetTxConfig,
+    SX127xCheckRfFrequency,
+    SX127xGetTimeOnAir,
+    SX127xSend,
+    SX127xSetSleep,
+    SX127xSetStby,
+    SX127xSetRx,
+    SX127xStartCad,
+    SX127xSetTxContinuousWave,
+    SX127xReadRssi,
+    SX127xWrite,
+    SX127xRead,
+    //SX127xWriteBuffer,
+    //SX127xReadBuffer,
+    SX127xSetMaxPayloadLength,
+    SX127xSetPublicNetwork,
+    SX127xGetWakeupTime,
+    NULL, // void ( *IrqProcess )( void )
+    SX127xCheck,
+    //SX126x Only
+    NULL, // void ( *RxBoosted )( uint32_t timeout ) 
+    NULL, // void ( *SetRxDutyCycle )( uint32_t rxTime, uint32_t sleepTime ) 
+};
+
+static bool lora_radio_init = false;
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+
+static uint8_t get_irq_index(uint32_t ev)
+{
+    uint32_t i = 0;
+    for(i = 0; i < 32; i++)
+    {
+        if(ev & 0x01)
+        {
+            break;
+        }
+        ev >>= 1;
+    }
+    return i;
+}
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+/**
+  * @brief  lora_radio_thread_entry
+  * @param  None
+  * @retval None
+  */
+void lora_radio_thread_entry(void* parameter)
+{
+    rt_uint32_t ev;
+    
+    while(1)
+    {
+        if (rt_event_recv(&lora_radio_event, EV_LORA_RADIO_IRQ_MASK,
+                                (RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR),
+                                RT_WAITING_FOREVER, &ev) == RT_EOK)
+        {
+            RadioIrqProcess(get_irq_index(ev));
+        }
+    }
+}
+#endif
+
+bool SX127xRadioInit( RadioEvents_t *events )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    if( lora_radio_init == false )
+    {
+        // Initialize spi bus
+        SX127x.spi = lora_radio_spi_init(LORA_RADIO0_SPI_BUS_NAME, LORA_RADIO0_DEVICE_NAME, RT_NULL);
+        if (SX127x.spi == RT_NULL)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "SX127x SPI Init Failed\n");
+            return false;
+        }
+
+        LORA_RADIO_DEBUG_LOG(LR_DBG_INTERFACE, LOG_LEVEL, "SX127x SPI Init Succeed\n");
+
+        rt_event_init(&lora_radio_event, "ev_lora_phy", RT_IPC_FLAG_PRIO);//RT_IPC_FLAG_FIFO);
+
+        rt_thread_init(&lora_radio_thread,               	  
+                       "lora-phy",                     	  
+                       lora_radio_thread_entry,          	  
+                       RT_NULL,                    	  
+                       &rt_lora_radio_thread_stack[0],       
+                       sizeof(rt_lora_radio_thread_stack),  
+                       1,   // highest priority                       	  
+                       20);                           
+                                   
+        rt_thread_startup(&lora_radio_thread);   
+                       
+       lora_radio_init = true;
+   }
+#endif /* LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD */ 
+   
+   SX127xIoInit();   
+   SX127xInit(events);
+   
+   return true;
+}
+
+void SX127xOnDio0IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ0_FIRED);
+#endif
+    }
+void SX127xOnDio1IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ1_FIRED);
+#endif    
+}
+void SX127xOnDio2IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ2_FIRED);
+#endif  
+}
+void SX127xOnDio3IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ3_FIRED);
+#endif    
+}
+void SX127xOnDio4IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ4_FIRED);
+#endif
+}
+void SX127xOnDio5IrqEvent( void *args )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_event_send(&lora_radio_event, EV_LORA_RADIO_IRQ5_FIRED);
+#endif
+}
+
+#else
+void RadioInit( RadioEvents_t *events )
+{
+    SX127xInit(events);
+}
+#endif

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/lora-spi-sx127x.c

@@ -0,0 +1,62 @@
+/*!
+ * \file      lora-radio-spi-sx127x.c
+ *
+ * \brief     sx127x spi driver implementation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+#include "sx127x\sx127x.h"
+#include "sx127x-board.h"
+
+void SX127xWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size )
+{   
+#ifdef RT_USING_SPI
+    uint8_t msg[1] = {0};
+    
+    msg[0] = (addr | 0x80);
+
+    rt_spi_send_then_send(SX127x.spi,msg,1,buffer,size);
+#else
+//    uint8_t i;
+
+//    //NSS = 0;
+//    GpioWrite( &SX127x.Spi.Nss, 0 );
+
+//    SpiInOut( &SX127x.Spi, addr | 0x80 );
+//    for( i = 0; i < size; i++ )
+//    {
+//        SpiInOut( &SX127x.Spi, buffer[i] );
+//    }
+
+//    //NSS = 1;
+//    GpioWrite( &SX127x.Spi.Nss, 1 );
+#endif
+}
+
+void SX127xReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size )
+{
+#ifdef RT_USING_SPI
+    uint8_t msg[1] = {0};
+    
+    msg[0] = (addr & 0x7F);
+
+    rt_spi_send_then_recv(SX127x.spi,msg,1,buffer,size);
+#else
+//    uint8_t i;
+
+//    //NSS = 0;
+//    GpioWrite( &SX127x.Spi.Nss, 0 );
+
+//    SpiInOut( &SX127x.Spi, addr & 0x7F );
+
+//    for( i = 0; i < size; i++ )
+//    {
+//        buffer[i] = SpiInOut( &SX127x.Spi, 0 );
+//    }
+
+//    //NSS = 1;
+//    GpioWrite( &SX127x.Spi.Nss, 1 );
+#endif
+}

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/lora-spi-sx127x.h

@@ -0,0 +1,49 @@
+/*!
+ * \file      lora-spi-sx127x.h
+ *
+ * \brief     SX127x spi interface
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+#ifndef __LORA_SPI_SX127x_H__
+#define __LORA_SPI_SX127x_H__
+
+/*!
+ * \brief Writes the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [IN]: data New register value
+ */
+void SX127xWrite( uint16_t addr, uint8_t data );
+
+/*!
+ * \brief Reads the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \retval data Register value
+ */
+uint8_t SX127xRead( uint16_t addr );
+
+/*!
+ * \brief Writes multiple radio registers starting at address
+ *
+ * \param [IN] addr   First Radio register address
+ * \param [IN] buffer Buffer containing the new register's values
+ * \param [IN] size   Number of registers to be written
+ */
+void SX127xWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads multiple radio registers starting at address
+ *
+ * \param [IN] addr First Radio register address
+ * \param [OUT] buffer Buffer where to copy the registers data
+ * \param [IN] size Number of registers to be read
+ */
+void SX127xReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+
+
+#endif // __LORA_SPI_SX127x_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/sx127x.c

@@ -0,0 +1,2085 @@
+/*!
+ * \file      sx127x.c
+ *
+ * \brief     SX127x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Wael Guibene ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include <math.h>
+#include <string.h>
+#include "board.h"
+#include "lora-radio-timer.h"
+#include "lora-radio.h"
+#include "lora-spi-sx127x.h"
+#include "sx127x\sx127x.h"
+#include "sx127x-board.h"
+
+#ifndef LORA_RADIO0_DEVICE_NAME
+#define LORA_RADIO0_DEVICE_NAME  "lora-radio0"
+#endif
+
+#define LOG_TAG "PHY.LoRa.SX127X"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+/*
+ * Local types definition
+ */
+
+/*!
+ * Radio registers definition
+ */
+typedef struct
+{
+    RadioModems_t Modem;
+    uint8_t       Addr;
+    uint8_t       Value;
+}RadioRegisters_t;
+
+/*!
+ * FSK bandwidth definition
+ */
+typedef struct
+{
+    uint32_t bandwidth;
+    uint8_t  RegValue;
+}FskBandwidth_t;
+
+/*
+ * Private functions prototypes
+ */
+
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) 
+/*!
+ * Performs the Rx chain calibration for LF and HF bands
+ * \remark Must be called just after the reset so all registers are at their
+ *         default values
+ */
+static void RxChainCalibration( void );
+#endif
+
+/*!
+ * \brief Sets the SX127x in transmission mode for the given time
+ * \param [IN] timeout Transmission timeout [ms] [0: continuous, others timeout]
+ */
+void SX127xSetTx( uint32_t timeout );
+
+/*!
+ * \brief Writes the buffer contents to the SX127x FIFO
+ *
+ * \param [IN] buffer Buffer containing data to be put on the FIFO.
+ * \param [IN] size Number of bytes to be written to the FIFO
+ */
+void SX127xWriteFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads the contents of the SX127x FIFO
+ *
+ * \param [OUT] buffer Buffer where to copy the FIFO read data.
+ * \param [IN] size Number of bytes to be read from the FIFO
+ */
+void SX127xReadFifo( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Sets the SX127x operating mode
+ *
+ * \param [IN] opMode New operating mode
+ */
+void SX127xSetOpMode( uint8_t opMode );
+
+/*
+ * SX127x DIO IRQ callback functions prototype
+ */
+
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX127xOnDio0Irq( void  );
+
+/*!
+ * \brief DIO 1 IRQ callback
+ */
+void SX127xOnDio1Irq( void  );
+
+/*!
+ * \brief DIO 2 IRQ callback
+ */
+void SX127xOnDio2Irq( void  );
+
+/*!
+ * \brief DIO 3 IRQ callback
+ */
+void SX127xOnDio3Irq( void  );
+
+/*!
+ * \brief DIO 4 IRQ callback
+ */
+void SX127xOnDio4Irq( void  );
+
+/*!
+ * \brief DIO 5 IRQ callback
+ */
+void SX127xOnDio5Irq( void  );
+
+/*!
+ * \brief Tx & Rx timeout timer callback
+ */
+void SX127xOnTimeoutIrq( void );
+
+/*
+ * Private global constants
+ */
+
+/*!
+ * Radio hardware registers initialization
+ *
+ * \remark RADIO_INIT_REGISTERS_VALUE is defined in sx1276-board.h file
+ */
+const RadioRegisters_t RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
+
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+/*!
+ * Constant values need to compute the RSSI value
+ */
+#define RSSI_OFFSET_LF                              -164
+#define RSSI_OFFSET_HF                              -157
+
+#elif defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1272 )
+
+#define RSSI_OFFSET_HF                              -139
+
+#else 
+#error "LoRa Chip Undefined!"
+#endif
+/*!
+ * Precomputed FSK bandwidth registers values
+ */
+const FskBandwidth_t FskBandwidths[] =
+{
+    { 2600  , 0x17 },
+    { 3100  , 0x0F },
+    { 3900  , 0x07 },
+    { 5200  , 0x16 },
+    { 6300  , 0x0E },
+    { 7800  , 0x06 },
+    { 10400 , 0x15 },
+    { 12500 , 0x0D },
+    { 15600 , 0x05 },
+    { 20800 , 0x14 },
+    { 25000 , 0x0C },
+    { 31300 , 0x04 },
+    { 41700 , 0x13 },
+    { 50000 , 0x0B },
+    { 62500 , 0x03 },
+    { 83333 , 0x12 },
+    { 100000, 0x0A },
+    { 125000, 0x02 },
+    { 166700, 0x11 },
+    { 200000, 0x09 },
+    { 250000, 0x01 },
+    { 300000, 0x00 }, // Invalid Bandwidth
+};
+
+/*
+ * Private global variables
+ */
+
+/*!
+ * Radio callbacks variable
+ */
+static RadioEvents_t *RadioEvents;
+
+/*!
+ * Reception buffer
+ */
+static uint8_t RxTxBuffer[RX_BUFFER_SIZE];
+
+/*!
+ * Hardware DIO IRQ callback initialization
+ */
+static DioIrqHandler *SX127xDioIrq[] = { SX127xOnDio0Irq, SX127xOnDio1Irq,
+                                          SX127xOnDio2Irq, SX127xOnDio3Irq,
+                                          SX127xOnDio4Irq, NULL };
+/*!
+ * Tx and Rx timers
+ */
+static TimerEvent_t TxTimeoutTimer;
+static TimerEvent_t RxTimeoutTimer;
+static TimerEvent_t RxTimeoutSyncWord;
+
+/*
+ * Public global variables
+ */
+
+/*!
+ * Radio hardware and global parameters
+ */
+SX127x_t SX127x;
+                                          
+/*
+ * Radio spi check
+ * 0     - spi access fail 
+ * non 0 - spi access success 
+ */
+uint8_t SX127xCheck(void)
+{
+    uint8_t test = 0;
+
+    LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL, "LoRa Chip is SX127X, Packet Type is %s",( SX127x.Settings.Modem == MODEM_LORA )? "LoRa":"FSK");
+
+    /* SPI Access Check */
+    SX127xWrite(REG_LR_PAYLOADLENGTH, 0x55); 
+    test = SX127xRead(REG_LR_PAYLOADLENGTH);
+    LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"SPI Access Check %s, LoRa PAYLOAD LENGTH Reg(0x22) Current Value: 0x%02X, Expected Value: 0x55", ((test == 0x55)? "Success":"Fail"),test);
+    if (test != 0x55)
+    {
+        return 0;
+    }
+   
+    return test;
+}
+
+/*
+ * Radio driver functions implementation
+ */
+
+void SX127xInit( RadioEvents_t *events )
+{
+    uint8_t i; 
+    
+    RadioEvents = events;
+
+#ifdef PKG_USING_MULTI_RTIMER
+    hw_rtc_init();
+#endif
+    
+    // Initialize driver timeout timers
+    TimerInit( &TxTimeoutTimer, SX127xOnTimeoutIrq );
+    TimerInit( &RxTimeoutTimer, SX127xOnTimeoutIrq );
+    TimerInit( &RxTimeoutSyncWord, SX127xOnTimeoutIrq );
+
+    SX127xReset( );
+    
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) 
+    RxChainCalibration( );
+#endif    
+
+    SX127xSetOpMode( RF_OPMODE_SLEEP );
+
+    SX127xIoIrqInit( SX127xDioIrq );
+
+    for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
+    {
+        SX127xSetModem( RadioRegsInit[i].Modem );
+        SX127xWrite( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
+    }
+
+    SX127xSetModem( MODEM_FSK );
+
+    SX127x.Settings.State = RF_IDLE;
+}
+
+RadioState_t SX127xGetStatus( void )
+{
+    return SX127x.Settings.State;
+}
+
+void SX127xSetChannel( uint32_t freq )
+{
+    SX127x.Settings.Channel = freq;
+    freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
+    SX127xWrite( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
+    SX127xWrite( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
+    SX127xWrite( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
+    
+    LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"Set Freq:%d",SX127x.Settings.Channel);
+}
+
+bool SX127xIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime )
+{
+    bool status = true;
+    int16_t rssi = 0;
+    uint32_t carrierSenseTime = 0;
+
+    SX127xSetSleep( );
+
+    SX127xSetModem( modem );
+
+    SX127xSetChannel( freq );
+
+    SX127xSetOpMode( RF_OPMODE_RECEIVER );
+
+    SX127X_DELAY_MS( 1 );
+
+    carrierSenseTime = TimerGetCurrentTime( );
+
+    // Perform carrier sense for maxCarrierSenseTime
+    while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime )
+    {
+        rssi = SX127xReadRssi( modem );
+
+        if( rssi > rssiThresh )
+        {
+            status = false;
+            break;
+        }
+    }
+    SX127xSetSleep( );
+    return status;
+}
+
+uint32_t SX127xRandom( void )
+{
+    uint8_t i;
+    uint32_t rnd = 0;
+
+    /*
+     * Radio setup for random number generation
+     */
+    // Set LoRa modem ON
+    SX127xSetModem( MODEM_LORA );
+
+    // Disable LoRa modem interrupts
+    SX127xWrite( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+                  RFLR_IRQFLAGS_RXDONE |
+                  RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                  RFLR_IRQFLAGS_VALIDHEADER |
+                  RFLR_IRQFLAGS_TXDONE |
+                  RFLR_IRQFLAGS_CADDONE |
+                  RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+                  RFLR_IRQFLAGS_CADDETECTED );
+
+    // Set radio in continuous reception
+    SX127xSetOpMode( RF_OPMODE_RECEIVER );
+
+    for( i = 0; i < 32; i++ )
+    {
+        SX127X_DELAY_MS( 1 );
+        // Unfiltered RSSI value reading. Only takes the LSB value
+        rnd |= ( ( uint32_t )SX127xRead( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
+    }
+
+    SX127xSetSleep( );
+
+    return rnd;
+}
+
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 )
+/*!
+ * Performs the Rx chain calibration for LF and HF bands
+ * \remark Must be called just after the reset so all registers are at their
+ *         default values
+ */
+static void RxChainCalibration( void )
+{
+    uint8_t regPaConfigInitVal;
+    uint32_t initialFreq;
+
+    // Save context
+    regPaConfigInitVal = SX127xRead( REG_PACONFIG );
+    initialFreq = ( double )( ( ( uint32_t )SX127xRead( REG_FRFMSB ) << 16 ) |
+                              ( ( uint32_t )SX127xRead( REG_FRFMID ) << 8 ) |
+                              ( ( uint32_t )SX127xRead( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
+
+    // Cut the PA just in case, RFO output, power = -1 dBm
+    SX127xWrite( REG_PACONFIG, 0x00 );
+
+    // Launch Rx chain calibration for LF band
+    SX127xWrite( REG_IMAGECAL, ( SX127xRead( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
+    while( ( SX127xRead( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
+    {
+    }
+
+    // Sets a Frequency in HF band
+    SX127xSetChannel( 868000000 );
+
+    // Launch Rx chain calibration for HF band
+    SX127xWrite( REG_IMAGECAL, ( SX127xRead( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
+    while( ( SX127xRead( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
+    {
+    }
+
+    // Restore context
+    SX127xWrite( REG_PACONFIG, regPaConfigInitVal );
+    SX127xSetChannel( initialFreq );
+}
+#endif
+
+/*!
+ * Returns the known FSK bandwidth registers value
+ *
+ * \param [IN] bandwidth Bandwidth value in Hz
+ * \retval regValue Bandwidth register value.
+ */
+static uint8_t GetFskBandwidthRegValue( uint32_t bandwidth )
+{
+    uint8_t i;
+
+    for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
+    {
+        if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
+        {
+            return FskBandwidths[i].RegValue;
+        }
+    }
+    // ERROR: Value not found
+    while( 1 );
+}
+
+void SX127xSetRxConfig( RadioModems_t modem, uint32_t bandwidth,
+                         uint32_t datarate, uint8_t coderate,
+                         uint32_t bandwidthAfc, uint16_t preambleLen,
+                         uint16_t symbTimeout, bool fixLen,
+                         uint8_t payloadLen,
+                         bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+                         bool iqInverted, bool rxContinuous )
+{
+    SX127xSetModem( modem );
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        {
+            SX127x.Settings.Fsk.Bandwidth = bandwidth;
+            SX127x.Settings.Fsk.Datarate = datarate;
+            SX127x.Settings.Fsk.BandwidthAfc = bandwidthAfc;
+            SX127x.Settings.Fsk.FixLen = fixLen;
+            SX127x.Settings.Fsk.PayloadLen = payloadLen;
+            SX127x.Settings.Fsk.CrcOn = crcOn;
+            SX127x.Settings.Fsk.IqInverted = iqInverted;
+            SX127x.Settings.Fsk.RxContinuous = rxContinuous;
+            SX127x.Settings.Fsk.PreambleLen = preambleLen;
+            SX127x.Settings.Fsk.RxSingleTimeout = ( uint32_t )( symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1000 );
+
+            datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
+            SX127xWrite( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
+            SX127xWrite( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
+
+            SX127xWrite( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
+            SX127xWrite( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
+
+            SX127xWrite( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
+            SX127xWrite( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
+
+            if( fixLen == 1 )
+            {
+                SX127xWrite( REG_PAYLOADLENGTH, payloadLen );
+            }
+            else
+            {
+                SX127xWrite( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
+            }
+
+            SX127xWrite( REG_PACKETCONFIG1,
+                         ( SX127xRead( REG_PACKETCONFIG1 ) &
+                           RF_PACKETCONFIG1_CRC_MASK &
+                           RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
+                           ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
+                           ( crcOn << 4 ) );
+            SX127xWrite( REG_PACKETCONFIG2, ( SX127xRead( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
+        }
+        break;
+    case MODEM_LORA:
+        {
+
+            if( bandwidth > 2 )
+            {
+                // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+                while( 1 );
+            }
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 			
+            bandwidth += 7;
+#endif
+            SX127x.Settings.LoRa.Bandwidth = bandwidth;
+            SX127x.Settings.LoRa.Datarate = datarate;
+            SX127x.Settings.LoRa.Coderate = coderate;
+            SX127x.Settings.LoRa.PreambleLen = preambleLen;
+            SX127x.Settings.LoRa.FixLen = fixLen;
+            SX127x.Settings.LoRa.PayloadLen = payloadLen;
+            SX127x.Settings.LoRa.CrcOn = crcOn;
+            SX127x.Settings.LoRa.FreqHopOn = freqHopOn;
+            SX127x.Settings.LoRa.HopPeriod = hopPeriod;
+            SX127x.Settings.LoRa.IqInverted = iqInverted;
+            SX127x.Settings.LoRa.RxContinuous = rxContinuous;
+
+            if( datarate > 12 )
+            {
+                datarate = 12;
+            }
+            else if( datarate < 6 )
+            {
+                datarate = 6;
+            }
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+            if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+                ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
+            {
+                SX127x.Settings.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX127x.Settings.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            SX127xWrite( REG_LR_MODEMCONFIG1,
+                         ( SX127xRead( REG_LR_MODEMCONFIG1 ) &
+                           RFLR_MODEMCONFIG1_BW_MASK &
+                           RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+                           RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
+                           ( bandwidth << 4 ) | ( coderate << 1 ) |
+                           fixLen );
+
+            SX127xWrite( REG_LR_MODEMCONFIG2,
+                         ( SX127xRead( REG_LR_MODEMCONFIG2 ) &
+                           RFLR_MODEMCONFIG2_SF_MASK &
+                           RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
+                           RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
+                           ( datarate << 4 ) | ( crcOn << 2 ) |
+                           ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
+
+            SX127xWrite( REG_LR_MODEMCONFIG3,
+                         ( SX127xRead( REG_LR_MODEMCONFIG3 ) &
+                           RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
+                           ( SX127x.Settings.LoRa.LowDatarateOptimize << 3 ) );
+
+#elif defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1272 )
+      		if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+                ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+            {
+                SX1272.Settings.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX1272.Settings.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            SX1272Write( REG_LR_MODEMCONFIG1,
+                         ( SX1272Read( REG_LR_MODEMCONFIG1 ) &
+                           RFLR_MODEMCONFIG1_BW_MASK &
+                           RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+                           RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
+                           RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
+                           RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
+                           ( bandwidth << 6 ) | ( coderate << 3 ) |
+                           ( fixLen << 2 ) | ( crcOn << 1 ) |
+                           SX1272.Settings.LoRa.LowDatarateOptimize );
+
+            SX1272Write( REG_LR_MODEMCONFIG2,
+                         ( SX1272Read( REG_LR_MODEMCONFIG2 ) &
+                           RFLR_MODEMCONFIG2_SF_MASK &
+                           RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
+                           ( datarate << 4 ) |
+                           ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
+
+#endif
+
+            SX127xWrite( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
+
+            SX127xWrite( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
+            SX127xWrite( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
+
+            if( fixLen == 1 )
+            {
+                SX127xWrite( REG_LR_PAYLOADLENGTH, payloadLen );
+            }
+
+            if( SX127x.Settings.LoRa.FreqHopOn == true )
+            {
+                SX127xWrite( REG_LR_PLLHOP, ( SX127xRead( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
+                SX127xWrite( REG_LR_HOPPERIOD, SX127x.Settings.LoRa.HopPeriod );
+            }
+			
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+            if( ( bandwidth == 9 ) && ( SX127x.Settings.Channel > RF_MID_BAND_THRESH ) )
+            {
+                // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+                SX127xWrite( REG_LR_HIGHBWOPTIMIZE1, 0x02 );
+                SX127xWrite( REG_LR_HIGHBWOPTIMIZE2, 0x64 );
+            }
+            else if( bandwidth == 9 )
+            {
+                // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+                SX127xWrite( REG_LR_HIGHBWOPTIMIZE1, 0x02 );
+                SX127xWrite( REG_LR_HIGHBWOPTIMIZE2, 0x7F );
+            }
+            else
+            {
+                // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
+                SX127xWrite( REG_LR_HIGHBWOPTIMIZE1, 0x03 );
+            }
+#endif 
+
+            if( datarate == 6 )
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE,
+                             ( SX127xRead( REG_LR_DETECTOPTIMIZE ) &
+                               RFLR_DETECTIONOPTIMIZE_MASK ) |
+                               RFLR_DETECTIONOPTIMIZE_SF6 );
+                SX127xWrite( REG_LR_DETECTIONTHRESHOLD,
+                             RFLR_DETECTIONTHRESH_SF6 );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE,
+                             ( SX127xRead( REG_LR_DETECTOPTIMIZE ) &
+                             RFLR_DETECTIONOPTIMIZE_MASK ) |
+                             RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
+                SX127xWrite( REG_LR_DETECTIONTHRESHOLD,
+                             RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
+            }
+        }
+        break;
+        default:
+            break;
+    }
+}
+
+
+void SX127xSetRfTxPower( int8_t power )
+{
+    uint8_t paConfig = 0;
+    uint8_t paDac = 0;
+
+    paConfig = SX127xRead( REG_PACONFIG );
+    paDac = SX127xRead( REG_PADAC );
+
+    paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | SX127xGetPaSelect( power );
+
+    if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+    {
+        if( power > 17 )
+        {
+            paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
+        }
+        else
+        {
+            paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
+        }
+        if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
+        {
+            if( power < 5 )
+            {
+                power = 5;
+            }
+            if( power > 20 )
+            {
+                power = 20;
+            }
+            paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
+        }
+        else
+        {
+            if( power < 2 )
+            {
+                power = 2;
+            }
+            if( power > 17 )
+            {
+                power = 17;
+            }
+            paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
+        }
+    }
+    else
+    {
+        if( power > 0 )
+        {
+            if( power > 15 )
+            {
+                power = 15;
+            }
+            paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( 7 << 4 ) | ( power );
+        }
+        else
+        {
+            if( power < -4 )
+            {
+                power = -4;
+            }
+            paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( 0 << 4 ) | ( power + 4 );
+        }
+    }
+    SX127xWrite( REG_PACONFIG, paConfig );
+    SX127xWrite( REG_PADAC, paDac );
+}
+
+void SX127xSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+                        uint32_t bandwidth, uint32_t datarate,
+                        uint8_t coderate, uint16_t preambleLen,
+                        bool fixLen, bool crcOn, bool freqHopOn,
+                        uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
+{
+    SX127xSetModem( modem );
+
+    SX127xSetRfTxPower( power );
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        {
+            SX127x.Settings.Fsk.Power = power;
+            SX127x.Settings.Fsk.Fdev = fdev;
+            SX127x.Settings.Fsk.Bandwidth = bandwidth;
+            SX127x.Settings.Fsk.Datarate = datarate;
+            SX127x.Settings.Fsk.PreambleLen = preambleLen;
+            SX127x.Settings.Fsk.FixLen = fixLen;
+            SX127x.Settings.Fsk.CrcOn = crcOn;
+            SX127x.Settings.Fsk.IqInverted = iqInverted;
+            SX127x.Settings.Fsk.TxTimeout = timeout;
+
+            fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
+            SX127xWrite( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
+            SX127xWrite( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
+
+            datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
+            SX127xWrite( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
+            SX127xWrite( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
+
+            SX127xWrite( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
+            SX127xWrite( REG_PREAMBLELSB, preambleLen & 0xFF );
+
+            SX127xWrite( REG_PACKETCONFIG1,
+                         ( SX127xRead( REG_PACKETCONFIG1 ) &
+                           RF_PACKETCONFIG1_CRC_MASK &
+                           RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
+                           ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
+                           ( crcOn << 4 ) );
+            SX127xWrite( REG_PACKETCONFIG2, ( SX127xRead( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
+        }
+        break;
+    case MODEM_LORA:
+        {
+            SX127x.Settings.LoRa.Power = power;
+            if( bandwidth > 2 )
+            {
+                // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+                while( 1 );
+            }
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+            bandwidth += 7;
+#endif
+            SX127x.Settings.LoRa.Bandwidth = bandwidth;
+            SX127x.Settings.LoRa.Datarate = datarate;
+            SX127x.Settings.LoRa.Coderate = coderate;
+            SX127x.Settings.LoRa.PreambleLen = preambleLen;
+            SX127x.Settings.LoRa.FixLen = fixLen;
+            SX127x.Settings.LoRa.FreqHopOn = freqHopOn;
+            SX127x.Settings.LoRa.HopPeriod = hopPeriod;
+            SX127x.Settings.LoRa.CrcOn = crcOn;
+            SX127x.Settings.LoRa.IqInverted = iqInverted;
+            SX127x.Settings.LoRa.TxTimeout = timeout;
+
+            if( datarate > 12 )
+            {
+                datarate = 12;
+            }
+            else if( datarate < 6 )
+            {
+                datarate = 6;
+            }
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+            if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+                ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
+            {
+                SX127x.Settings.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX127x.Settings.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            if( SX127x.Settings.LoRa.FreqHopOn == true )
+            {
+                SX127xWrite( REG_LR_PLLHOP, ( SX127xRead( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
+                SX127xWrite( REG_LR_HOPPERIOD, SX127x.Settings.LoRa.HopPeriod );
+            }
+
+            SX127xWrite( REG_LR_MODEMCONFIG1,
+                         ( SX127xRead( REG_LR_MODEMCONFIG1 ) &
+                           RFLR_MODEMCONFIG1_BW_MASK &
+                           RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+                           RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
+                           ( bandwidth << 4 ) | ( coderate << 1 ) |
+                           fixLen );
+
+            SX127xWrite( REG_LR_MODEMCONFIG2,
+                         ( SX127xRead( REG_LR_MODEMCONFIG2 ) &
+                           RFLR_MODEMCONFIG2_SF_MASK &
+                           RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
+                           ( datarate << 4 ) | ( crcOn << 2 ) );
+
+            SX127xWrite( REG_LR_MODEMCONFIG3,
+                         ( SX127xRead( REG_LR_MODEMCONFIG3 ) &
+                           RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
+                           ( SX127x.Settings.LoRa.LowDatarateOptimize << 3 ) );
+#elif defined ( LORA_CHIP_SX1272 )
+            if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+                ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+            {
+                SX1272.Settings.LoRa.LowDatarateOptimize = 0x01;
+            }
+            else
+            {
+                SX1272.Settings.LoRa.LowDatarateOptimize = 0x00;
+            }
+
+            if( SX1272.Settings.LoRa.FreqHopOn == true )
+            {
+                SX1272Write( REG_LR_PLLHOP, ( SX1272Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
+                SX1272Write( REG_LR_HOPPERIOD, SX1272.Settings.LoRa.HopPeriod );
+            }
+
+            SX1272Write( REG_LR_MODEMCONFIG1,
+                         ( SX1272Read( REG_LR_MODEMCONFIG1 ) &
+                           RFLR_MODEMCONFIG1_BW_MASK &
+                           RFLR_MODEMCONFIG1_CODINGRATE_MASK &
+                           RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
+                           RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
+                           RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
+                           ( bandwidth << 6 ) | ( coderate << 3 ) |
+                           ( fixLen << 2 ) | ( crcOn << 1 ) |
+                           SX1272.Settings.LoRa.LowDatarateOptimize );
+
+            SX1272Write( REG_LR_MODEMCONFIG2,
+                        ( SX1272Read( REG_LR_MODEMCONFIG2 ) &
+                          RFLR_MODEMCONFIG2_SF_MASK ) |
+                          ( datarate << 4 ) );
+#endif
+            SX127xWrite( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
+            SX127xWrite( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
+
+            if( datarate == 6 )
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE,
+                             ( SX127xRead( REG_LR_DETECTOPTIMIZE ) &
+                               RFLR_DETECTIONOPTIMIZE_MASK ) |
+                               RFLR_DETECTIONOPTIMIZE_SF6 );
+                SX127xWrite( REG_LR_DETECTIONTHRESHOLD,
+                             RFLR_DETECTIONTHRESH_SF6 );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE,
+                             ( SX127xRead( REG_LR_DETECTOPTIMIZE ) &
+                             RFLR_DETECTIONOPTIMIZE_MASK ) |
+                             RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
+                SX127xWrite( REG_LR_DETECTIONTHRESHOLD,
+                             RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
+            }
+        }
+        break;
+    }
+}
+
+
+static uint32_t SX127xGetLoRaBandwidthInHz( uint32_t bw )
+{
+    uint32_t bandwidthInHz = 0;
+
+    switch( bw )
+    {
+    case 0: // 125 kHz
+        bandwidthInHz = 125000UL;
+        break;
+    case 1: // 250 kHz
+        bandwidthInHz = 250000UL;
+        break;
+    case 2: // 500 kHz
+        bandwidthInHz = 500000UL;
+        break;
+    }
+
+    return bandwidthInHz;
+}
+
+static uint32_t SX127xGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+    const uint8_t syncWordLength = 3;
+
+    return ( preambleLen << 3 ) +
+           ( ( fixLen == false ) ? 8 : 0 ) +
+             ( syncWordLength << 3 ) +
+             ( ( payloadLen +
+               ( 0 ) + // Address filter size
+               ( ( crcOn == true ) ? 2 : 0 ) 
+               ) << 3 
+             );
+}
+
+static uint32_t SX127xGetLoRaTimeOnAirNumerator( uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+    int32_t crDenom           = coderate + 4;
+    bool    lowDatareOptimize = false;
+
+    // Ensure that the preamble length is at least 12 symbols when using SF5 or
+    // SF6
+    if( ( datarate == 5 ) || ( datarate == 6 ) )
+    {
+        if( preambleLen < 12 )
+        {
+            preambleLen = 12;
+        }
+    }
+
+    if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
+        ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
+    {
+        lowDatareOptimize = true;
+    }
+
+    int32_t ceilDenominator;
+    int32_t ceilNumerator = ( payloadLen << 3 ) +
+                            ( crcOn ? 16 : 0 ) -
+                            ( 4 * datarate ) +
+                            ( fixLen ? 0 : 20 );
+
+    if( datarate <= 6 )
+    {
+        ceilDenominator = 4 * datarate;
+    }
+    else
+    {
+        ceilNumerator += 8;
+
+        if( lowDatareOptimize == true )
+        {
+            ceilDenominator = 4 * ( datarate - 2 );
+        }
+        else
+        {
+            ceilDenominator = 4 * datarate;
+        }
+    }
+
+    if( ceilNumerator < 0 )
+    {
+        ceilNumerator = 0;
+    }
+
+    // Perform integral ceil()
+    int32_t intermediate =
+        ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12;
+
+    if( datarate <= 6 )
+    {
+        intermediate += 2;
+    }
+
+    return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) );
+}
+uint32_t SX127xGetTimeOnAir( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn )
+{
+  uint32_t numerator = 0;
+    uint32_t denominator = 1;
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        {
+            numerator   = 1000U * SX127xGetGfskTimeOnAirNumerator( datarate, coderate,
+                                                                  preambleLen, fixLen,
+                                                                  payloadLen, crcOn );
+            denominator = datarate;
+        }
+        break;
+    case MODEM_LORA:
+        {
+            numerator   = 1000U * SX127xGetLoRaTimeOnAirNumerator( bandwidth, datarate,
+                                                                  coderate, preambleLen,
+                                                                  fixLen, payloadLen, crcOn );
+            denominator = SX127xGetLoRaBandwidthInHz( bandwidth );
+        }
+        break;
+    }
+   // Perform integral ceil()
+    return ( numerator + denominator - 1 ) / denominator;
+}
+
+void SX127xSend( uint8_t *buffer, uint8_t size )
+{
+    uint32_t txTimeout = 0;
+
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        {
+            SX127x.Settings.FskPacketHandler.NbBytes = 0;
+            SX127x.Settings.FskPacketHandler.Size = size;
+
+            if( SX127x.Settings.Fsk.FixLen == false )
+            {
+                SX127xWriteFifo( ( uint8_t* )&size, 1 );
+            }
+            else
+            {
+                SX127xWrite( REG_PAYLOADLENGTH, size );
+            }
+
+            if( ( size > 0 ) && ( size <= 64 ) )
+            {
+                SX127x.Settings.FskPacketHandler.ChunkSize = size;
+            }
+            else
+            {
+                memcpy( RxTxBuffer, buffer, size );
+                //rt_memcpy( RxTxBuffer, buffer, size );
+                SX127x.Settings.FskPacketHandler.ChunkSize = 32;
+            }
+
+            // Write payload buffer
+            SX127xWriteFifo( buffer, SX127x.Settings.FskPacketHandler.ChunkSize );
+            SX127x.Settings.FskPacketHandler.NbBytes += SX127x.Settings.FskPacketHandler.ChunkSize;
+            txTimeout = SX127x.Settings.Fsk.TxTimeout;
+        }
+        break;
+    case MODEM_LORA:
+        {
+            if( SX127x.Settings.LoRa.IqInverted == true )
+            {
+                SX127xWrite( REG_LR_INVERTIQ, ( ( SX127xRead( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
+                SX127xWrite( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_INVERTIQ, ( ( SX127xRead( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
+                SX127xWrite( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
+            }
+
+            SX127x.Settings.LoRaPacketHandler.Size = size;
+
+            // Initializes the payload size
+            SX127xWrite( REG_LR_PAYLOADLENGTH, size );
+
+            // Full buffer used for Tx
+            SX127xWrite( REG_LR_FIFOTXBASEADDR, 0 );
+            SX127xWrite( REG_LR_FIFOADDRPTR, 0 );
+
+            // FIFO operations can not take place in Sleep mode
+            if( ( SX127xRead( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
+            {
+                SX127xSetStby( );
+                SX127X_DELAY_MS( 1 );
+            }
+            // Write payload buffer
+            SX127xWriteFifo( buffer, size );
+            txTimeout = SX127x.Settings.LoRa.TxTimeout;
+        }
+        break;
+        default:
+        break;
+    }
+
+    SX127xSetTx( txTimeout );
+}
+
+void SX127xSetSleep( void )
+{
+    TimerStop( &RxTimeoutTimer );
+    TimerStop( &TxTimeoutTimer );
+    TimerStop( &RxTimeoutSyncWord );
+
+    SX127xSetOpMode( RF_OPMODE_SLEEP );
+
+#ifdef USE_LORA_RADIO_TCXO
+    // Disable TCXO radio is in SLEEP mode
+    SX127xSetBoardTcxo( false );
+#endif
+
+    SX127x.Settings.State = RF_IDLE;
+}
+
+void SX127xSetStby( void )
+{
+    TimerStop( &RxTimeoutTimer );
+    TimerStop( &TxTimeoutTimer );
+    TimerStop( &RxTimeoutSyncWord );
+
+    SX127xSetOpMode( RF_OPMODE_STANDBY );
+    SX127x.Settings.State = RF_IDLE;
+}
+
+void SX127xSetRx( uint32_t timeout )
+{
+    bool rxContinuous = false;
+    TimerStop( &TxTimeoutTimer );
+
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        {
+            rxContinuous = SX127x.Settings.Fsk.RxContinuous;
+
+            // DIO0=PayloadReady
+            // DIO1=FifoLevel
+            // DIO2=SyncAddr
+            // DIO3=FifoEmpty
+            // DIO4=Preamble
+            // DIO5=ModeReady
+            SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
+                                                                            RF_DIOMAPPING1_DIO1_MASK &
+                                                                            RF_DIOMAPPING1_DIO2_MASK ) |
+                                                                            RF_DIOMAPPING1_DIO0_00 |
+                                                                            RF_DIOMAPPING1_DIO1_00 |
+                                                                            RF_DIOMAPPING1_DIO2_11 );
+
+            SX127xWrite( REG_DIOMAPPING2, ( SX127xRead( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
+                                                                            RF_DIOMAPPING2_MAP_MASK ) |
+                                                                            RF_DIOMAPPING2_DIO4_11 |
+                                                                            RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
+
+            SX127x.Settings.FskPacketHandler.FifoThresh = SX127xRead( REG_FIFOTHRESH ) & 0x3F;
+
+            SX127xWrite( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
+
+            SX127x.Settings.FskPacketHandler.PreambleDetected = false;
+            SX127x.Settings.FskPacketHandler.SyncWordDetected = false;
+            SX127x.Settings.FskPacketHandler.NbBytes = 0;
+            SX127x.Settings.FskPacketHandler.Size = 0;
+        }
+        break;
+    case MODEM_LORA:
+        {
+            if( SX127x.Settings.LoRa.IqInverted == true )
+            {
+                SX127xWrite( REG_LR_INVERTIQ, ( ( SX127xRead( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
+                SX127xWrite( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_INVERTIQ, ( ( SX127xRead( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
+                SX127xWrite( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
+            }
+			
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+            // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
+            if( SX127x.Settings.LoRa.Bandwidth < 9 )
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE, SX127xRead( REG_LR_DETECTOPTIMIZE ) & 0x7F );
+                SX127xWrite( REG_LR_IFFREQ2, 0x00 );
+                switch( SX127x.Settings.LoRa.Bandwidth )
+                {
+                case 0: // 7.8 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x48 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 7810 );
+                    break;
+                case 1: // 10.4 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x44 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 10420 );
+                    break;
+                case 2: // 15.6 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x44 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 15620 );
+                    break;
+                case 3: // 20.8 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x44 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 20830 );
+                    break;
+                case 4: // 31.2 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x44 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 31250 );
+                    break;
+                case 5: // 41.4 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x44 );
+                    SX127xSetChannel(SX127x.Settings.Channel + 41670 );
+                    break;
+                case 6: // 62.5 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x40 );
+                    break;
+                case 7: // 125 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x40 );
+                    break;
+                case 8: // 250 kHz
+                    SX127xWrite( REG_LR_IFFREQ1, 0x40 );
+                    break;
+                }
+            }
+            else
+            {
+                SX127xWrite( REG_LR_DETECTOPTIMIZE, SX127xRead( REG_LR_DETECTOPTIMIZE ) | 0x80 );
+            }
+#endif
+
+            rxContinuous = SX127x.Settings.LoRa.RxContinuous;
+
+            if( SX127x.Settings.LoRa.FreqHopOn == true )
+            {
+                SX127xWrite( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
+                                                  //RFLR_IRQFLAGS_RXDONE |
+                                                  //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                                                  RFLR_IRQFLAGS_VALIDHEADER |
+                                                  RFLR_IRQFLAGS_TXDONE |
+                                                  RFLR_IRQFLAGS_CADDONE |
+                                                  //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+                                                  RFLR_IRQFLAGS_CADDETECTED );
+
+                // DIO0=RxDone, DIO2=FhssChangeChannel
+                SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK  ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
+                                                  //RFLR_IRQFLAGS_RXDONE |
+                                                  //RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                                                  RFLR_IRQFLAGS_VALIDHEADER |
+                                                  RFLR_IRQFLAGS_TXDONE |
+                                                  RFLR_IRQFLAGS_CADDONE |
+                                                  RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+                                                  RFLR_IRQFLAGS_CADDETECTED );
+
+                // DIO0=RxDone
+                SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
+            }
+            SX127xWrite( REG_LR_FIFORXBASEADDR, 0 );
+            SX127xWrite( REG_LR_FIFOADDRPTR, 0 );
+        }
+        break;
+    }
+
+    memset( RxTxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
+
+    SX127x.Settings.State = RF_RX_RUNNING;
+    if( timeout != 0 )
+    {
+        TimerSetValue( &RxTimeoutTimer, timeout );
+        TimerStart( &RxTimeoutTimer );
+    }
+
+    if( SX127x.Settings.Modem == MODEM_FSK )
+    {
+        SX127xSetOpMode( RF_OPMODE_RECEIVER );
+
+        TimerSetValue( &RxTimeoutSyncWord, SX127x.Settings.Fsk.RxSingleTimeout );
+        TimerStart( &RxTimeoutSyncWord );
+    }
+    else
+    {
+        if( rxContinuous == true )
+        {
+            SX127xSetOpMode( RFLR_OPMODE_RECEIVER );
+        }
+        else
+        {
+            SX127xSetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
+        }
+    }
+}
+
+void SX127xSetTx( uint32_t timeout )
+{
+    TimerStop( &RxTimeoutTimer );
+
+    TimerSetValue( &TxTimeoutTimer, timeout );
+
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        {
+            // DIO0=PacketSent
+            // DIO1=FifoEmpty
+            // DIO2=FifoFull
+            // DIO3=FifoEmpty
+            // DIO4=LowBat
+            // DIO5=ModeReady
+            SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
+                                                                            RF_DIOMAPPING1_DIO1_MASK &
+                                                                            RF_DIOMAPPING1_DIO2_MASK ) |
+                                                                            RF_DIOMAPPING1_DIO1_01 );
+
+            SX127xWrite( REG_DIOMAPPING2, ( SX127xRead( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
+                                                                            RF_DIOMAPPING2_MAP_MASK ) );
+            SX127x.Settings.FskPacketHandler.FifoThresh = SX127xRead( REG_FIFOTHRESH ) & 0x3F;
+        }
+        break;
+    case MODEM_LORA:
+        {
+            if( SX127x.Settings.LoRa.FreqHopOn == true )
+            {
+                SX127xWrite( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+                                                  RFLR_IRQFLAGS_RXDONE |
+                                                  RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                                                  RFLR_IRQFLAGS_VALIDHEADER |
+                                                  //RFLR_IRQFLAGS_TXDONE |
+                                                  RFLR_IRQFLAGS_CADDONE |
+                                                  //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+                                                  RFLR_IRQFLAGS_CADDETECTED );
+
+                // DIO0=TxDone, DIO2=FhssChangeChannel
+                SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
+            }
+            else
+            {
+                SX127xWrite( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+                                                  RFLR_IRQFLAGS_RXDONE |
+                                                  RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                                                  RFLR_IRQFLAGS_VALIDHEADER |
+                                                  //RFLR_IRQFLAGS_TXDONE |
+                                                  RFLR_IRQFLAGS_CADDONE |
+                                                  RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
+                                                  RFLR_IRQFLAGS_CADDETECTED );
+
+                // DIO0=TxDone
+                SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
+            }
+        }
+        break;
+        default:
+            break;
+    }
+
+    SX127x.Settings.State = RF_TX_RUNNING;
+    TimerStart( &TxTimeoutTimer );
+    SX127xSetOpMode( RF_OPMODE_TRANSMITTER );
+}
+
+void SX127xStartCad( void )
+{
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        {
+
+        }
+        break;
+    case MODEM_LORA:
+        {
+            SX127xWrite( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
+                                        RFLR_IRQFLAGS_RXDONE |
+                                        RFLR_IRQFLAGS_PAYLOADCRCERROR |
+                                        RFLR_IRQFLAGS_VALIDHEADER |
+                                        RFLR_IRQFLAGS_TXDONE |
+                                        //RFLR_IRQFLAGS_CADDONE |
+                                        RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
+                                        //RFLR_IRQFLAGS_CADDETECTED
+                                        );
+
+            // DIO3=CADDone
+            SX127xWrite( REG_DIOMAPPING1, ( SX127xRead( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
+
+            SX127x.Settings.State = RF_CAD;
+            SX127xSetOpMode( RFLR_OPMODE_CAD );
+        }
+        break;
+    default:
+        break;
+    }
+}
+
+void SX127xSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
+{
+    uint32_t timeout = ( uint32_t )( time * 1000 );
+
+    SX127xSetChannel( freq );
+
+    SX127xSetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
+
+    SX127xWrite( REG_PACKETCONFIG2, ( SX127xRead( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
+    // Disable radio interrupts
+    SX127xWrite( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
+    SX127xWrite( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
+    
+    SX127x.Settings.State = RF_TX_RUNNING;
+    SX127xSetOpMode( RF_OPMODE_TRANSMITTER );
+    
+    if(timeout)
+    {
+        TimerSetValue( &TxTimeoutTimer, timeout );
+        TimerStart( &TxTimeoutTimer );
+    }
+}
+
+int16_t SX127xReadRssi( RadioModems_t modem )
+{
+    int16_t rssi = 0;
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        rssi = -( SX127xRead( REG_RSSIVALUE ) >> 1 );
+        break;
+    case MODEM_LORA:
+         	LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+        if( SX127x.Settings.Channel > RF_MID_BAND_THRESH )
+        {
+            rssi = RSSI_OFFSET_HF + SX127xRead( REG_LR_RSSIVALUE );
+        }
+        else
+        {
+            rssi = RSSI_OFFSET_LF + SX127xRead( REG_LR_RSSIVALUE );
+        }
+#elif defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1272 )  
+            rssi = RSSI_OFFSET_HF + SX127xRead( REG_LR_RSSIVALUE );
+#endif
+        break;
+    default:
+        rssi = -1;
+        break;
+    }
+    return rssi;
+}
+
+void SX127xSetOpMode( uint8_t opMode )
+{
+#if defined( USE_RADIO_DEBUG )
+    switch( opMode )
+    {
+        case RF_OPMODE_TRANSMITTER:
+            SX127xDbgPinTxWrite( 1 );
+            SX127xDbgPinRxWrite( 0 );
+            break;
+        case RF_OPMODE_RECEIVER:
+        case RFLR_OPMODE_RECEIVER_SINGLE:
+            SX127xDbgPinTxWrite( 0 );
+            SX127xDbgPinRxWrite( 1 );
+            break;
+        default:
+            SX127xDbgPinTxWrite( 0 );
+            SX127xDbgPinRxWrite( 0 );
+            break;
+    }
+#endif
+    if( opMode == RF_OPMODE_SLEEP )
+    {
+        SX127xSetAntSwLowPower( true );
+    }
+    else
+    {
+        // Enable TCXO if operating mode different from SLEEP.
+#ifdef USE_LORA_RADIO_TCXO		
+        SX127xSetBoardTcxo( true );
+#endif		
+        SX127xSetAntSwLowPower( false );
+        SX127xSetAntSw( opMode );
+    }
+    SX127xWrite( REG_OPMODE, ( SX127xRead( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
+}
+
+void SX127xSetModem( RadioModems_t modem )
+{
+    if( ( SX127xRead( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
+    {
+        SX127x.Settings.Modem = MODEM_LORA;
+    }
+    else
+    {
+        SX127x.Settings.Modem = MODEM_FSK;
+    }
+
+    if( SX127x.Settings.Modem == modem )
+    {
+        return;
+    }
+
+    SX127x.Settings.Modem = modem;
+    switch( SX127x.Settings.Modem )
+    {
+    default:
+    case MODEM_FSK:
+        SX127xSetOpMode( RF_OPMODE_SLEEP );
+        SX127xWrite( REG_OPMODE, ( SX127xRead( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
+
+        SX127xWrite( REG_DIOMAPPING1, 0x00 );
+        SX127xWrite( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
+        break;
+    case MODEM_LORA:
+        SX127xSetOpMode( RF_OPMODE_SLEEP );
+        SX127xWrite( REG_OPMODE, ( SX127xRead( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
+
+        SX127xWrite( REG_DIOMAPPING1, 0x00 );
+        SX127xWrite( REG_DIOMAPPING2, 0x00 );
+        break;
+    }
+}
+
+void SX127xWrite( uint16_t addr, uint8_t data )
+{
+    SX127xWriteBuffer( addr, &data, 1 );
+}
+
+uint8_t SX127xRead( uint16_t addr )
+{
+    uint8_t data;
+    SX127xReadBuffer( addr, &data, 1 );
+    return data;
+}
+
+void SX127xWriteFifo( uint8_t *buffer, uint8_t size )
+{
+    SX127xWriteBuffer( 0, buffer, size );
+}
+
+void SX127xReadFifo( uint8_t *buffer, uint8_t size )
+{
+    SX127xReadBuffer( 0, buffer, size );
+}
+
+void SX127xSetMaxPayloadLength( RadioModems_t modem, uint8_t max )
+{
+    SX127xSetModem( modem );
+
+    switch( modem )
+    {
+    case MODEM_FSK:
+        if( SX127x.Settings.Fsk.FixLen == false )
+        {
+            SX127xWrite( REG_PAYLOADLENGTH, max );
+        }
+        break;
+    case MODEM_LORA:
+        SX127xWrite( REG_LR_PAYLOADMAXLENGTH, max );
+        break;
+    }
+}
+
+void SX127xSetPublicNetwork( bool enable )
+{
+    SX127xSetModem( MODEM_LORA );
+    SX127x.Settings.LoRa.PublicNetwork = enable;
+    if( enable == true )
+    {
+        // Change LoRa modem SyncWord
+        SX127xWrite( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
+    }
+    else
+    {
+        // Change LoRa modem SyncWord
+        SX127xWrite( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
+    }
+}
+
+uint32_t SX127xGetWakeupTime( void )
+{
+    return /* SX127xGetBoardTcxoWakeupTime( ) + */ RADIO_WAKEUP_TIME;
+}
+
+void SX127xOnTimeoutIrq( void )
+{
+    switch( SX127x.Settings.State )
+    {
+    case RF_RX_RUNNING:
+        if( SX127x.Settings.Modem == MODEM_FSK )
+        {
+            SX127x.Settings.FskPacketHandler.PreambleDetected = false;
+            SX127x.Settings.FskPacketHandler.SyncWordDetected = false;
+            SX127x.Settings.FskPacketHandler.NbBytes = 0;
+            SX127x.Settings.FskPacketHandler.Size = 0;
+
+            // Clear Irqs
+            SX127xWrite( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+                                        RF_IRQFLAGS1_PREAMBLEDETECT |
+                                        RF_IRQFLAGS1_SYNCADDRESSMATCH );
+            SX127xWrite( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
+
+            if( SX127x.Settings.Fsk.RxContinuous == true )
+            {
+                // Continuous mode restart Rx chain
+                SX127xWrite( REG_RXCONFIG, SX127xRead( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+                TimerStart( &RxTimeoutSyncWord );
+            }
+            else
+            {
+                SX127x.Settings.State = RF_IDLE;
+                TimerStop( &RxTimeoutSyncWord );
+            }
+        }
+        if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
+        {
+            RadioEvents->RxTimeout( );
+        }
+        LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY RxTimeout\r");
+        break;
+    case RF_TX_RUNNING:
+        // Tx timeout shouldn't happen.
+		// Reported issue of SPI data corruption resulting in TX TIMEOUT 
+        // is NOT related to a bug in radio transceiver.
+        // It is mainly caused by improper PCB routing of SPI lines and/or
+        // violation of SPI specifications.
+        // To mitigate redesign, Semtech offers a workaround which resets
+        // the radio transceiver and putting it into a known state.
+        // The workaround is to put the radio in a known state. Thus, we re-initialize it.
+
+        // BEGIN WORKAROUND
+
+        // Reset the radio
+        SX127xReset( );
+    
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) 
+        // Calibrate Rx chain
+        RxChainCalibration( );
+#endif
+    
+        // Initialize radio default values
+        SX127xSetOpMode( RF_OPMODE_SLEEP );
+
+        for( uint8_t i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
+        {
+            SX127xSetModem( RadioRegsInit[i].Modem );
+            SX127xWrite( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
+        }
+        SX127xSetModem( MODEM_FSK );
+
+        // Restore previous network type setting.
+        SX127xSetPublicNetwork( SX127x.Settings.LoRa.PublicNetwork );
+        // END WORKAROUND
+
+        SX127x.Settings.State = RF_IDLE;
+        if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) )
+        {
+            RadioEvents->TxTimeout( );
+        }
+        LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY TxTimeout\r");
+        break;
+    default:
+        break;
+    }
+}
+
+void SX127xOnDio0Irq( void )
+{
+    volatile uint8_t irqFlags = 0;
+
+    switch( SX127x.Settings.State )
+    {
+        case RF_RX_RUNNING:
+            //TimerStop( &RxTimeoutTimer );
+            // RxDone interrupt
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_FSK:
+                if( SX127x.Settings.Fsk.CrcOn == true )
+                {
+                    irqFlags = SX127xRead( REG_IRQFLAGS2 );
+                    if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
+                    {
+                        // Clear Irqs
+                        SX127xWrite( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
+                                                    RF_IRQFLAGS1_PREAMBLEDETECT |
+                                                    RF_IRQFLAGS1_SYNCADDRESSMATCH );
+                        SX127xWrite( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
+
+                        TimerStop( &RxTimeoutTimer );
+
+                        if( SX127x.Settings.Fsk.RxContinuous == false )
+                        {
+                            TimerStop( &RxTimeoutSyncWord );
+                            SX127x.Settings.State = RF_IDLE;
+                        }
+                        else
+                        {
+                            // Continuous mode restart Rx chain
+                            SX127xWrite( REG_RXCONFIG, SX127xRead( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+                            TimerStart( &RxTimeoutSyncWord );
+                        }
+
+                        if( ( RadioEvents != NULL ) && ( RadioEvents->RxError != NULL ) )
+                        {
+                            RadioEvents->RxError( );
+                        }
+                        LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY RX Error\r");
+                        
+                        SX127x.Settings.FskPacketHandler.PreambleDetected = false;
+                        SX127x.Settings.FskPacketHandler.SyncWordDetected = false;
+                        SX127x.Settings.FskPacketHandler.NbBytes = 0;
+                        SX127x.Settings.FskPacketHandler.Size = 0;
+                        break;
+                    }
+                }
+
+                // Read received packet size
+                if( ( SX127x.Settings.FskPacketHandler.Size == 0 ) && ( SX127x.Settings.FskPacketHandler.NbBytes == 0 ) )
+                {
+                    if( SX127x.Settings.Fsk.FixLen == false )
+                    {
+                        SX127xReadFifo( ( uint8_t* )&SX127x.Settings.FskPacketHandler.Size, 1 );
+                    }
+                    else
+                    {
+                        SX127x.Settings.FskPacketHandler.Size = SX127xRead( REG_PAYLOADLENGTH );
+                    }
+                    SX127xReadFifo( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes, SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                    SX127x.Settings.FskPacketHandler.NbBytes += ( SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                }
+                else
+                {
+                    SX127xReadFifo( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes, SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                    SX127x.Settings.FskPacketHandler.NbBytes += ( SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                }
+
+                TimerStop( &RxTimeoutTimer );
+
+                if( SX127x.Settings.Fsk.RxContinuous == false )
+                {
+                    SX127x.Settings.State = RF_IDLE;
+                    TimerStop( &RxTimeoutSyncWord );
+                }
+                else
+                {
+                    // Continuous mode restart Rx chain
+                    SX127xWrite( REG_RXCONFIG, SX127xRead( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
+                    TimerStart( &RxTimeoutSyncWord );
+                }
+
+                if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) )
+                {
+                    RadioEvents->RxDone( RxTxBuffer, SX127x.Settings.FskPacketHandler.Size, SX127x.Settings.FskPacketHandler.RssiValue, 0 );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY RX Done\r");
+                SX127x.Settings.FskPacketHandler.PreambleDetected = false;
+                SX127x.Settings.FskPacketHandler.SyncWordDetected = false;
+                SX127x.Settings.FskPacketHandler.NbBytes = 0;
+                SX127x.Settings.FskPacketHandler.Size = 0;
+                break;
+            case MODEM_LORA:
+                {
+                    // Clear Irq
+                    SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
+
+                    irqFlags = SX127xRead( REG_LR_IRQFLAGS );
+                    if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
+                    {
+                        // Clear Irq
+                        SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
+
+                        if( SX127x.Settings.LoRa.RxContinuous == false )
+                        {
+                            SX127x.Settings.State = RF_IDLE;
+                        }
+                        TimerStop( &RxTimeoutTimer );
+
+                        if( ( RadioEvents != NULL ) && ( RadioEvents->RxError != NULL ) )
+                        {
+                            RadioEvents->RxError( );
+                        }
+                        LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY RX Error\r");
+                        break;
+                    }
+
+                    // Returns SNR value [dB] rounded to the nearest integer value
+                    SX127x.Settings.LoRaPacketHandler.SnrValue = ( ( ( int8_t )SX127xRead( REG_LR_PKTSNRVALUE ) ) + 2 ) >> 2;
+
+                    int16_t rssi = SX127xRead( REG_LR_PKTRSSIVALUE );
+					
+					int16_t rssi_offset = RSSI_OFFSET_HF;
+					
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1276 ) || defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX1278 ) 
+					if( SX127x.Settings.Channel <= RF_MID_BAND_THRESH )
+					{
+						rssi_offset = RSSI_OFFSET_LF;
+					}
+#endif					
+                    if( SX127x.Settings.LoRaPacketHandler.SnrValue < 0 )
+                    {
+                        SX127x.Settings.LoRaPacketHandler.RssiValue = rssi_offset + rssi + ( rssi >> 4 ) +
+                                                                      SX127x.Settings.LoRaPacketHandler.SnrValue;
+                    }
+                    else
+                    {
+                        SX127x.Settings.LoRaPacketHandler.RssiValue = rssi_offset + rssi + ( rssi >> 4 );
+                    }
+
+                    SX127x.Settings.LoRaPacketHandler.Size = SX127xRead( REG_LR_RXNBBYTES );
+                    SX127xWrite( REG_LR_FIFOADDRPTR, SX127xRead( REG_LR_FIFORXCURRENTADDR ) );
+                    SX127xReadFifo( RxTxBuffer, SX127x.Settings.LoRaPacketHandler.Size );
+
+                    if( SX127x.Settings.LoRa.RxContinuous == false )
+                    {
+                        SX127x.Settings.State = RF_IDLE;
+                    }
+                    TimerStop( &RxTimeoutTimer );
+
+                    if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) )
+                    {
+                        RadioEvents->RxDone( RxTxBuffer, SX127x.Settings.LoRaPacketHandler.Size, SX127x.Settings.LoRaPacketHandler.RssiValue, SX127x.Settings.LoRaPacketHandler.SnrValue );
+                    }
+                    LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY RX Done\r");
+                }
+                break;
+            default:
+                break;
+            }
+            break;
+        case RF_TX_RUNNING:
+            TimerStop( &TxTimeoutTimer );
+            // TxDone interrupt
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_LORA:
+                // Clear Irq
+                SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
+                // Intentional fall through
+            case MODEM_FSK:
+            default:
+                SX127x.Settings.State = RF_IDLE;
+                if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) )
+                {
+                    RadioEvents->TxDone( );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY TX Done\r");
+                break;
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+void SX127xOnDio1Irq( void )
+{
+    switch( SX127x.Settings.State )
+    {
+        case RF_RX_RUNNING:
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_FSK:
+                // Stop timer
+                TimerStop( &RxTimeoutSyncWord );
+
+                // FifoLevel interrupt
+                // Read received packet size
+                if( ( SX127x.Settings.FskPacketHandler.Size == 0 ) && ( SX127x.Settings.FskPacketHandler.NbBytes == 0 ) )
+                {
+                    if( SX127x.Settings.Fsk.FixLen == false )
+                    {
+                        SX127xReadFifo( ( uint8_t* )&SX127x.Settings.FskPacketHandler.Size, 1 );
+                    }
+                    else
+                    {
+                        SX127x.Settings.FskPacketHandler.Size = SX127xRead( REG_PAYLOADLENGTH );
+                    }
+                }
+
+                // ERRATA 3.1 - PayloadReady Set for 31.25ns if FIFO is Empty
+                //
+                //              When FifoLevel interrupt is used to offload the
+                //              FIFO, the microcontroller should  monitor  both
+                //              PayloadReady  and FifoLevel interrupts, and
+                //              read only (FifoThreshold-1) bytes off the FIFO
+                //              when FifoLevel fires
+                if( ( SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes ) >= SX127x.Settings.FskPacketHandler.FifoThresh )
+                {
+                    SX127xReadFifo( ( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes ), SX127x.Settings.FskPacketHandler.FifoThresh - 1 );
+                    SX127x.Settings.FskPacketHandler.NbBytes += SX127x.Settings.FskPacketHandler.FifoThresh - 1;
+                }
+                else
+                {
+                    SX127xReadFifo( ( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes ), SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                    SX127x.Settings.FskPacketHandler.NbBytes += ( SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                }
+                break;
+            case MODEM_LORA:
+                // Sync time out
+                TimerStop( &RxTimeoutTimer );
+                // Clear Irq
+                SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
+
+                SX127x.Settings.State = RF_IDLE;
+                if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) )
+                {
+                    RadioEvents->RxTimeout( );
+                }
+                LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY Single Rxtimeout\r");
+                break;
+            default:
+                break;
+            }
+            break;
+        case RF_TX_RUNNING:
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_FSK:
+                // FifoEmpty interrupt
+                if( ( SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes ) > SX127x.Settings.FskPacketHandler.ChunkSize )
+                {
+                    SX127xWriteFifo( ( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes ), SX127x.Settings.FskPacketHandler.ChunkSize );
+                    SX127x.Settings.FskPacketHandler.NbBytes += SX127x.Settings.FskPacketHandler.ChunkSize;
+                }
+                else
+                {
+                    // Write the last chunk of data
+                    SX127xWriteFifo( RxTxBuffer + SX127x.Settings.FskPacketHandler.NbBytes, SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes );
+                    SX127x.Settings.FskPacketHandler.NbBytes += SX127x.Settings.FskPacketHandler.Size - SX127x.Settings.FskPacketHandler.NbBytes;
+                }
+                break;
+            case MODEM_LORA:
+                break;
+            default:
+                break;
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+void SX127xOnDio2Irq( void )
+{
+    switch( SX127x.Settings.State )
+    {
+        case RF_RX_RUNNING:
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_FSK:
+                // Checks if DIO4 is connected. If it is not PreambleDetected is set to true.
+                ////if( SX127x.DIO4.port == NULL )
+                {
+                    SX127x.Settings.FskPacketHandler.PreambleDetected = true;
+                }
+
+                if( ( SX127x.Settings.FskPacketHandler.PreambleDetected == true ) && ( SX127x.Settings.FskPacketHandler.SyncWordDetected == false ) )
+                {
+                    TimerStop( &RxTimeoutSyncWord );
+
+                    SX127x.Settings.FskPacketHandler.SyncWordDetected = true;
+
+                    SX127x.Settings.FskPacketHandler.RssiValue = -( SX127xRead( REG_RSSIVALUE ) >> 1 );
+
+                    SX127x.Settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )SX127xRead( REG_AFCMSB ) << 8 ) |
+                                                                           ( uint16_t )SX127xRead( REG_AFCLSB ) ) *
+                                                                           ( double )FREQ_STEP;
+                    SX127x.Settings.FskPacketHandler.RxGain = ( SX127xRead( REG_LNA ) >> 5 ) & 0x07;
+                }
+                break;
+            case MODEM_LORA:
+                if( SX127x.Settings.LoRa.FreqHopOn == true )
+                {
+                    // Clear Irq
+                    SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+                    if( ( RadioEvents != NULL ) && ( RadioEvents->FhssChangeChannel != NULL ) )
+                    {
+                        RadioEvents->FhssChangeChannel( ( SX127xRead( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
+                    }
+                }
+                break;
+            default:
+                break;
+            }
+            break;
+        case RF_TX_RUNNING:
+            switch( SX127x.Settings.Modem )
+            {
+            case MODEM_FSK:
+                break;
+            case MODEM_LORA:
+                if( SX127x.Settings.LoRa.FreqHopOn == true )
+                {
+                    // Clear Irq
+                    SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
+
+                    if( ( RadioEvents != NULL ) && ( RadioEvents->FhssChangeChannel != NULL ) )
+                    {
+                        RadioEvents->FhssChangeChannel( ( SX127xRead( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
+                    }
+                }
+                break;
+            default:
+                break;
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+void SX127xOnDio3Irq( void  )
+{
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        break;
+    case MODEM_LORA:
+        if( ( SX127xRead( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
+        {
+            // Clear Irq
+            SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
+            if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) )
+            {
+                RadioEvents->CadDone( true );
+            }
+            LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY CAD Done,Detected\r");
+        }
+        else
+        {
+            // Clear Irq
+            SX127xWrite( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
+            if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) )
+            {
+                RadioEvents->CadDone( false );
+            }
+            LORA_RADIO_DEBUG_LOG(LR_DBG_CHIP, LOG_LEVEL,"PHY CAD Done,Not Detected\r");
+        }
+        
+        break;
+    default:
+        break;
+    }
+}
+
+void SX127xOnDio4Irq( void  )
+{
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        {
+            if( SX127x.Settings.FskPacketHandler.PreambleDetected == false )
+            {
+                SX127x.Settings.FskPacketHandler.PreambleDetected = true;
+            }
+        }
+        break;
+    case MODEM_LORA:
+        break;
+    default:
+        break;
+    }
+}
+
+void SX127xOnDio5Irq( void )
+{
+    switch( SX127x.Settings.Modem )
+    {
+    case MODEM_FSK:
+        break;
+    case MODEM_LORA:
+        break;
+    default:
+        break;
+    }
+}
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+void RadioIrqProcess( uint8_t irq_index )
+{
+    LORA_RADIO_CRITICAL_SECTION_BEGIN( );
+    SX127xDioIrq[irq_index]();
+    LORA_RADIO_CRITICAL_SECTION_END( );
+}
+#endif

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/sx127x.h

@@ -0,0 +1,509 @@
+/*!
+ * \file      SX127x.h
+ *
+ * \brief     SX127x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#ifndef __SX127x_H__
+#define __SX127x_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "lora-radio.h"
+#include "sx127xRegs-Fsk.h"
+#include "sx127xRegs-LoRa.h"
+
+/*!
+ * Radio wake-up time from sleep
+ */
+#define RADIO_WAKEUP_TIME                           1 // [ms]
+
+/*!
+ * Sync word for Private LoRa networks
+ */
+#define LORA_MAC_PRIVATE_SYNCWORD                   0x12
+
+/*!
+ * Sync word for Public LoRa networks
+ */
+#define LORA_MAC_PUBLIC_SYNCWORD                    0x34
+
+/*!
+ * Radio FSK modem parameters
+ */
+typedef struct
+{
+    int8_t   Power;
+    uint32_t Fdev;
+    uint32_t Bandwidth;
+    uint32_t BandwidthAfc;
+    uint32_t Datarate;
+    uint16_t PreambleLen;
+    bool     FixLen;
+    uint8_t  PayloadLen;
+    bool     CrcOn;
+    bool     IqInverted;
+    bool     RxContinuous;
+    uint32_t TxTimeout;
+    uint32_t RxSingleTimeout;
+}RadioFskSettings_t;
+
+/*!
+ * Radio FSK packet handler state
+ */
+typedef struct
+{
+    uint8_t  PreambleDetected;
+    uint8_t  SyncWordDetected;
+    int8_t   RssiValue;
+    int32_t  AfcValue;
+    uint8_t  RxGain;
+    uint16_t Size;
+    uint16_t NbBytes;
+    uint8_t  FifoThresh;
+    uint8_t  ChunkSize;
+}RadioFskPacketHandler_t;
+
+/*!
+ * Radio LoRa modem parameters
+ */
+typedef struct
+{
+    int8_t   Power;
+    uint32_t Bandwidth;
+    uint32_t Datarate;
+    bool     LowDatarateOptimize;
+    uint8_t  Coderate;
+    uint16_t PreambleLen;
+    bool     FixLen;
+    uint8_t  PayloadLen;
+    bool     CrcOn;
+    bool     FreqHopOn;
+    uint8_t  HopPeriod;
+    bool     IqInverted;
+    bool     RxContinuous;
+    uint32_t TxTimeout;
+    bool     PublicNetwork;
+}RadioLoRaSettings_t;
+
+/*!
+ * Radio LoRa packet handler state
+ */
+typedef struct
+{
+    int8_t SnrValue;
+    int16_t RssiValue;
+    uint8_t Size;
+}RadioLoRaPacketHandler_t;
+
+/*!
+ * Radio Settings
+ */
+typedef struct
+{
+    RadioState_t             State;
+    RadioModems_t            Modem;
+    uint32_t                 Channel;
+    RadioFskSettings_t       Fsk;
+    RadioFskPacketHandler_t  FskPacketHandler;
+    RadioLoRaSettings_t      LoRa;
+    RadioLoRaPacketHandler_t LoRaPacketHandler;
+}RadioSettings_t;
+
+/*!
+ * Radio hardware and global parameters
+ */
+typedef struct SX127x_s
+{
+//    Gpio_t        Reset;
+//    Gpio_t        DIO0;
+//    Gpio_t        DIO1;
+//    Gpio_t        DIO2;
+//    Gpio_t        DIO3;
+//    Gpio_t        DIO4;
+//    Gpio_t        DIO5;
+//    Spi_t         Spi;
+    
+/*!
+ * Radio Spi bus
+ */
+    struct rt_spi_device *spi;
+    
+    RadioSettings_t Settings;
+}SX127x_t;
+
+/*!
+ * Hardware IO IRQ callback function definition
+ */
+typedef void ( DioIrqHandler )( void );
+
+/*!
+ * SX127x definitions
+ */
+#define XTAL_FREQ                                   32000000
+#define FREQ_STEP                                   61.03515625
+
+#define RX_BUFFER_SIZE                              256
+
+/*!
+ * \brief Radio hardware registers initialization definition
+ *
+ * \remark Can be automatically generated by the SX127x GUI (not yet implemented)
+ */
+#define RADIO_INIT_REGISTERS_VALUE                \
+{                                                 \
+    { MODEM_FSK , REG_LNA                , 0x23 },\
+    { MODEM_FSK , REG_RXCONFIG           , 0x1E },\
+    { MODEM_FSK , REG_RSSICONFIG         , 0xD2 },\
+    { MODEM_FSK , REG_AFCFEI             , 0x01 },\
+    { MODEM_FSK , REG_PREAMBLEDETECT     , 0xAA },\
+    { MODEM_FSK , REG_OSC                , 0x07 },\
+    { MODEM_FSK , REG_SYNCCONFIG         , 0x12 },\
+    { MODEM_FSK , REG_SYNCVALUE1         , 0xC1 },\
+    { MODEM_FSK , REG_SYNCVALUE2         , 0x94 },\
+    { MODEM_FSK , REG_SYNCVALUE3         , 0xC1 },\
+    { MODEM_FSK , REG_PACKETCONFIG1      , 0xD8 },\
+    { MODEM_FSK , REG_FIFOTHRESH         , 0x8F },\
+    { MODEM_FSK , REG_IMAGECAL           , 0x02 },\
+    { MODEM_FSK , REG_DIOMAPPING1        , 0x00 },\
+    { MODEM_FSK , REG_DIOMAPPING2        , 0x30 },\
+    { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },\
+}                                                 \
+
+#define RF_MID_BAND_THRESH                          525000000
+
+/*!
+ * ============================================================================
+ * Public functions prototypes
+ * ============================================================================
+ */
+
+/*!
+ * \brief Initializes the radio
+ *
+ * \param [IN] events Structure containing the driver callback functions
+ */
+void SX127xInit( RadioEvents_t *events );
+
+/*!
+ * Return current radio status
+ *
+ * \param status Radio status.[RF_IDLE, RF_RX_RUNNING, RF_TX_RUNNING]
+ */
+RadioState_t SX127xGetStatus( void );
+
+/*!
+ * \brief Configures the radio with the given modem
+ *
+ * \param [IN] modem Modem to be used [0: FSK, 1: LoRa]
+ */
+void SX127xSetModem( RadioModems_t modem );
+
+/*!
+ * \brief Sets the channel configuration
+ *
+ * \param [IN] freq         Channel RF frequency
+ */
+void SX127xSetChannel( uint32_t freq );
+
+/*!
+ * \brief Sets the radio output power.
+ *
+ * \param [IN] power Sets the RF output power
+ */
+void SX127xSetRfTxPower( int8_t power );
+
+/*!
+ * \brief Checks if the channel is free for the given time
+ *
+ * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] freq       Channel RF frequency
+ * \param [IN] rssiThresh RSSI threshold
+ * \param [IN] maxCarrierSenseTime Max time while the RSSI is measured
+ *
+ * \retval isFree         [true: Channel is free, false: Channel is not free]
+ */
+bool SX127xIsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh, uint32_t maxCarrierSenseTime );
+
+/*!
+ * \brief Generates a 32 bits random value based on the RSSI readings
+ *
+ * \remark This function sets the radio in LoRa modem mode and disables
+ *         all interrupts.
+ *         After calling this function either SX127xSetRxConfig or
+ *         SX127xSetTxConfig functions must be called.
+ *
+ * \retval randomValue    32 bits random value
+ */
+uint32_t SX127xRandom( void );
+
+/*!
+ * \brief Sets the reception parameters
+ *
+ * \remark When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ *
+ * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] bandwidth    Sets the bandwidth
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] bandwidthAfc Sets the AFC Bandwidth (FSK only)
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: N/A ( set to 0 )
+ * \param [IN] preambleLen  Sets the Preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] symbTimeout  Sets the RxSingle timeout value
+ *                          FSK : timeout number of bytes
+ *                          LoRa: timeout in symbols
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] payloadLen   Sets payload length when fixed length is used
+ * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+ * \param [IN] freqHopOn    Enables disables the intra-packet frequency hopping
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: OFF, 1: ON]
+ * \param [IN] hopPeriod    Number of symbols between each hop
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: Number of symbols
+ * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: not inverted, 1: inverted]
+ * \param [IN] rxContinuous Sets the reception in continuous mode
+ *                          [false: single mode, true: continuous mode]
+ */
+void SX127xSetRxConfig( RadioModems_t modem, uint32_t bandwidth,
+                         uint32_t datarate, uint8_t coderate,
+                         uint32_t bandwidthAfc, uint16_t preambleLen,
+                         uint16_t symbTimeout, bool fixLen,
+                         uint8_t payloadLen,
+                         bool crcOn, bool freqHopOn, uint8_t hopPeriod,
+                         bool iqInverted, bool rxContinuous );
+
+/*!
+ * \brief Sets the transmission parameters
+ *
+ * \remark When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
+ *
+ * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] power        Sets the output power [dBm]
+ * \param [IN] fdev         Sets the frequency deviation (FSK only)
+ *                          FSK : [Hz]
+ *                          LoRa: 0
+ * \param [IN] bandwidth    Sets the bandwidth (LoRa only)
+ *                          FSK : 0
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] preambleLen  Sets the preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] crcOn        Enables disables the CRC [0: OFF, 1: ON]
+ * \param [IN] freqHopOn    Enables disables the intra-packet frequency hopping
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: OFF, 1: ON]
+ * \param [IN] hopPeriod    Number of symbols between each hop
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: Number of symbols
+ * \param [IN] iqInverted   Inverts IQ signals (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [0: not inverted, 1: inverted]
+ * \param [IN] timeout      Transmission timeout [ms]
+ */
+void SX127xSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
+                        uint32_t bandwidth, uint32_t datarate,
+                        uint8_t coderate, uint16_t preambleLen,
+                        bool fixLen, bool crcOn, bool freqHopOn,
+                        uint8_t hopPeriod, bool iqInverted, uint32_t timeout );
+
+/*!
+ * \brief Computes the packet time on air in ms for the given payload
+ *
+ * \Remark Can only be called once SetRxConfig or SetTxConfig have been called
+ *
+ * \param [IN] modem        Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] bandwidth    Sets the bandwidth
+ *                          FSK : >= 2600 and <= 250000 Hz
+ *                          LoRa: [0: 125 kHz, 1: 250 kHz,
+ *                                 2: 500 kHz, 3: Reserved]
+ * \param [IN] datarate     Sets the Datarate
+ *                          FSK : 600..300000 bits/s
+ *                          LoRa: [6: 64, 7: 128, 8: 256, 9: 512,
+ *                                10: 1024, 11: 2048, 12: 4096  chips]
+ * \param [IN] coderate     Sets the coding rate (LoRa only)
+ *                          FSK : N/A ( set to 0 )
+ *                          LoRa: [1: 4/5, 2: 4/6, 3: 4/7, 4: 4/8]
+ * \param [IN] preambleLen  Sets the Preamble length
+ *                          FSK : Number of bytes
+ *                          LoRa: Length in symbols (the hardware adds 4 more symbols)
+ * \param [IN] fixLen       Fixed length packets [0: variable, 1: fixed]
+ * \param [IN] payloadLen   Sets payload length when fixed length is used
+ * \param [IN] crcOn        Enables/Disables the CRC [0: OFF, 1: ON]
+ *
+ * \retval airTime        Computed airTime (ms) for the given packet payload length
+ */
+uint32_t SX127xGetTimeOnAir( RadioModems_t modem, uint32_t bandwidth,
+                              uint32_t datarate, uint8_t coderate,
+                              uint16_t preambleLen, bool fixLen, uint8_t payloadLen,
+                              bool crcOn );
+
+/*!
+ * \brief Sends the buffer of size. Prepares the packet to be sent and sets
+ *        the radio in transmission
+ *
+ * \param [IN]: buffer     Buffer pointer
+ * \param [IN]: size       Buffer size
+ */
+void SX127xSend( uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Sets the radio in sleep mode
+ */
+void SX127xSetSleep( void );
+
+/*!
+ * \brief Sets the radio in standby mode
+ */
+void SX127xSetStby( void );
+
+/*!
+ * \brief Sets the radio in reception mode for the given time
+ * \param [IN] timeout Reception timeout [ms] [0: continuous, others timeout]
+ */
+void SX127xSetRx( uint32_t timeout );
+
+/*!
+ * \brief Start a Channel Activity Detection
+ */
+void SX127xStartCad( void );
+
+/*!
+ * \brief Sets the radio in continuous wave transmission mode
+ *
+ * \param [IN]: freq       Channel RF frequency
+ * \param [IN]: power      Sets the output power [dBm]
+ * \param [IN]: time       Transmission mode timeout [s]
+ */
+void SX127xSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time );
+
+/*!
+ * \brief Reads the current RSSI value
+ *
+ * \retval rssiValue Current RSSI value in [dBm]
+ */
+int16_t SX127xReadRssi( RadioModems_t modem );
+
+/*!
+ * \brief Writes the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \param [IN]: data New register value
+ */
+void SX127xWrite( uint16_t addr, uint8_t data );
+
+/*!
+ * \brief Reads the radio register at the specified address
+ *
+ * \param [IN]: addr Register address
+ * \retval data Register value
+ */
+uint8_t SX127xRead( uint16_t addr );
+
+/*!
+ * \brief Writes multiple radio registers starting at address
+ *
+ * \param [IN] addr   First Radio register address
+ * \param [IN] buffer Buffer containing the new register's values
+ * \param [IN] size   Number of registers to be written
+ */
+void SX127xWriteBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Reads multiple radio registers starting at address
+ *
+ * \param [IN] addr First Radio register address
+ * \param [OUT] buffer Buffer where to copy the registers data
+ * \param [IN] size Number of registers to be read
+ */
+void SX127xReadBuffer( uint16_t addr, uint8_t *buffer, uint8_t size );
+
+/*!
+ * \brief Sets the maximum payload length.
+ *
+ * \param [IN] modem      Radio modem to be used [0: FSK, 1: LoRa]
+ * \param [IN] max        Maximum payload length in bytes
+ */
+void SX127xSetMaxPayloadLength( RadioModems_t modem, uint8_t max );
+
+/*!
+ * \brief Sets the network to public or private. Updates the sync byte.
+ *
+ * \remark Applies to LoRa modem only
+ *
+ * \param [IN] enable if true, it enables a public network
+ */
+void SX127xSetPublicNetwork( bool enable );
+
+/*!
+ * \brief Gets the time required for the board plus radio to get out of sleep.[ms]
+ *
+ * \retval time Radio plus board wakeup time in ms.
+ */
+uint32_t SX127xGetWakeupTime( void );
+
+/*!
+ * \brief Check spi access
+ *
+ * \retval the .
+ */
+uint8_t SX127xCheck( void );
+
+/*!
+ * \brief Initializes DIO IRQ handlers
+ *
+ * \param [IN] irqHandlers Array containing the IRQ callback functions
+ */
+void SX127xIoIrqInit( DioIrqHandler **irqHandlers );
+
+/*!
+ * \brief Process radio irq
+ */
+void RadioIrqProcess( uint8_t irq_index );
+
+/*!
+ * Radio hardware and global parameters
+ */
+extern SX127x_t SX127x;
+
+#endif // __SX127x_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/sx127xRegs-Fsk.h

@@ -0,0 +1,1142 @@
+/*!
+ * \file      sx1276Regs-Fsk.h
+ *
+ * \brief     SX1276 FSK modem registers and bits definitions
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ */
+#ifndef __SX1276_REGS_FSK_H__
+#define __SX1276_REGS_FSK_H__
+
+/*!
+ * ============================================================================
+ * SX1276 Internal registers Address
+ * ============================================================================
+ */
+#define REG_FIFO                                    0x00
+// Common settings
+#define REG_OPMODE                                  0x01
+#define REG_BITRATEMSB                              0x02
+#define REG_BITRATELSB                              0x03
+#define REG_FDEVMSB                                 0x04
+#define REG_FDEVLSB                                 0x05
+#define REG_FRFMSB                                  0x06
+#define REG_FRFMID                                  0x07
+#define REG_FRFLSB                                  0x08
+// Tx settings
+#define REG_PACONFIG                                0x09
+#define REG_PARAMP                                  0x0A
+#define REG_OCP                                     0x0B
+// Rx settings
+#define REG_LNA                                     0x0C
+#define REG_RXCONFIG                                0x0D
+#define REG_RSSICONFIG                              0x0E
+#define REG_RSSICOLLISION                           0x0F
+#define REG_RSSITHRESH                              0x10
+#define REG_RSSIVALUE                               0x11
+#define REG_RXBW                                    0x12
+#define REG_AFCBW                                   0x13
+#define REG_OOKPEAK                                 0x14
+#define REG_OOKFIX                                  0x15
+#define REG_OOKAVG                                  0x16
+#define REG_RES17                                   0x17
+#define REG_RES18                                   0x18
+#define REG_RES19                                   0x19
+#define REG_AFCFEI                                  0x1A
+#define REG_AFCMSB                                  0x1B
+#define REG_AFCLSB                                  0x1C
+#define REG_FEIMSB                                  0x1D
+#define REG_FEILSB                                  0x1E
+#define REG_PREAMBLEDETECT                          0x1F
+#define REG_RXTIMEOUT1                              0x20
+#define REG_RXTIMEOUT2                              0x21
+#define REG_RXTIMEOUT3                              0x22
+#define REG_RXDELAY                                 0x23
+// Oscillator settings
+#define REG_OSC                                     0x24
+// Packet handler settings
+#define REG_PREAMBLEMSB                             0x25
+#define REG_PREAMBLELSB                             0x26
+#define REG_SYNCCONFIG                              0x27
+#define REG_SYNCVALUE1                              0x28
+#define REG_SYNCVALUE2                              0x29
+#define REG_SYNCVALUE3                              0x2A
+#define REG_SYNCVALUE4                              0x2B
+#define REG_SYNCVALUE5                              0x2C
+#define REG_SYNCVALUE6                              0x2D
+#define REG_SYNCVALUE7                              0x2E
+#define REG_SYNCVALUE8                              0x2F
+#define REG_PACKETCONFIG1                           0x30
+#define REG_PACKETCONFIG2                           0x31
+#define REG_PAYLOADLENGTH                           0x32
+#define REG_NODEADRS                                0x33
+#define REG_BROADCASTADRS                           0x34
+#define REG_FIFOTHRESH                              0x35
+// SM settings
+#define REG_SEQCONFIG1                              0x36
+#define REG_SEQCONFIG2                              0x37
+#define REG_TIMERRESOL                              0x38
+#define REG_TIMER1COEF                              0x39
+#define REG_TIMER2COEF                              0x3A
+// Service settings
+#define REG_IMAGECAL                                0x3B
+#define REG_TEMP                                    0x3C
+#define REG_LOWBAT                                  0x3D
+// Status
+#define REG_IRQFLAGS1                               0x3E
+#define REG_IRQFLAGS2                               0x3F
+// I/O settings
+#define REG_DIOMAPPING1                             0x40
+#define REG_DIOMAPPING2                             0x41
+// Version
+#define REG_VERSION                                 0x42
+// Additional settings
+#define REG_PLLHOP                                  0x44
+#define REG_TCXO                                    0x4B
+#define REG_PADAC                                   0x4D
+#define REG_FORMERTEMP                              0x5B
+#define REG_BITRATEFRAC                             0x5D
+#define REG_AGCREF                                  0x61
+#define REG_AGCTHRESH1                              0x62
+#define REG_AGCTHRESH2                              0x63
+#define REG_AGCTHRESH3                              0x64
+#define REG_PLL                                     0x70
+
+/*!
+ * ============================================================================
+ * SX1276 FSK bits control definition
+ * ============================================================================
+ */
+
+/*!
+ * RegFifo
+ */
+
+/*!
+ * RegOpMode
+ */
+#define RF_OPMODE_LONGRANGEMODE_MASK                0x7F
+#define RF_OPMODE_LONGRANGEMODE_OFF                 0x00
+#define RF_OPMODE_LONGRANGEMODE_ON                  0x80
+
+#define RF_OPMODE_MODULATIONTYPE_MASK               0x9F
+#define RF_OPMODE_MODULATIONTYPE_FSK                0x00  // Default
+#define RF_OPMODE_MODULATIONTYPE_OOK                0x20
+
+#define RF_OPMODE_MODULATIONSHAPING_MASK            0xE7
+#define RF_OPMODE_MODULATIONSHAPING_00              0x00  // Default
+#define RF_OPMODE_MODULATIONSHAPING_01              0x08
+#define RF_OPMODE_MODULATIONSHAPING_10              0x10
+#define RF_OPMODE_MODULATIONSHAPING_11              0x18
+
+#define RF_OPMODE_MASK                              0xF8
+#define RF_OPMODE_SLEEP                             0x00
+#define RF_OPMODE_STANDBY                           0x01  // Default
+#define RF_OPMODE_SYNTHESIZER_TX                    0x02
+#define RF_OPMODE_TRANSMITTER                       0x03
+#define RF_OPMODE_SYNTHESIZER_RX                    0x04
+#define RF_OPMODE_RECEIVER                          0x05
+
+/*!
+ * RegBitRate (bits/sec)
+ */
+#define RF_BITRATEMSB_1200_BPS                      0x68
+#define RF_BITRATELSB_1200_BPS                      0x2B
+#define RF_BITRATEMSB_2400_BPS                      0x34
+#define RF_BITRATELSB_2400_BPS                      0x15
+#define RF_BITRATEMSB_4800_BPS                      0x1A  // Default
+#define RF_BITRATELSB_4800_BPS                      0x0B  // Default
+#define RF_BITRATEMSB_9600_BPS                      0x0D
+#define RF_BITRATELSB_9600_BPS                      0x05
+#define RF_BITRATEMSB_15000_BPS                     0x08
+#define RF_BITRATELSB_15000_BPS                     0x55
+#define RF_BITRATEMSB_19200_BPS                     0x06
+#define RF_BITRATELSB_19200_BPS                     0x83
+#define RF_BITRATEMSB_38400_BPS                     0x03
+#define RF_BITRATELSB_38400_BPS                     0x41
+#define RF_BITRATEMSB_76800_BPS                     0x01
+#define RF_BITRATELSB_76800_BPS                     0xA1
+#define RF_BITRATEMSB_153600_BPS                    0x00
+#define RF_BITRATELSB_153600_BPS                    0xD0
+#define RF_BITRATEMSB_57600_BPS                     0x02
+#define RF_BITRATELSB_57600_BPS                     0x2C
+#define RF_BITRATEMSB_115200_BPS                    0x01
+#define RF_BITRATELSB_115200_BPS                    0x16
+#define RF_BITRATEMSB_12500_BPS                     0x0A
+#define RF_BITRATELSB_12500_BPS                     0x00
+#define RF_BITRATEMSB_25000_BPS                     0x05
+#define RF_BITRATELSB_25000_BPS                     0x00
+#define RF_BITRATEMSB_50000_BPS                     0x02
+#define RF_BITRATELSB_50000_BPS                     0x80
+#define RF_BITRATEMSB_100000_BPS                    0x01
+#define RF_BITRATELSB_100000_BPS                    0x40
+#define RF_BITRATEMSB_150000_BPS                    0x00
+#define RF_BITRATELSB_150000_BPS                    0xD5
+#define RF_BITRATEMSB_200000_BPS                    0x00
+#define RF_BITRATELSB_200000_BPS                    0xA0
+#define RF_BITRATEMSB_250000_BPS                    0x00
+#define RF_BITRATELSB_250000_BPS                    0x80
+#define RF_BITRATEMSB_32768_BPS                     0x03
+#define RF_BITRATELSB_32768_BPS                     0xD1
+
+/*!
+ * RegFdev (Hz)
+ */
+#define RF_FDEVMSB_2000_HZ                          0x00
+#define RF_FDEVLSB_2000_HZ                          0x21
+#define RF_FDEVMSB_5000_HZ                          0x00  // Default
+#define RF_FDEVLSB_5000_HZ                          0x52  // Default
+#define RF_FDEVMSB_10000_HZ                         0x00
+#define RF_FDEVLSB_10000_HZ                         0xA4
+#define RF_FDEVMSB_15000_HZ                         0x00
+#define RF_FDEVLSB_15000_HZ                         0xF6
+#define RF_FDEVMSB_20000_HZ                         0x01
+#define RF_FDEVLSB_20000_HZ                         0x48
+#define RF_FDEVMSB_25000_HZ                         0x01
+#define RF_FDEVLSB_25000_HZ                         0x9A
+#define RF_FDEVMSB_30000_HZ                         0x01
+#define RF_FDEVLSB_30000_HZ                         0xEC
+#define RF_FDEVMSB_35000_HZ                         0x02
+#define RF_FDEVLSB_35000_HZ                         0x3D
+#define RF_FDEVMSB_40000_HZ                         0x02
+#define RF_FDEVLSB_40000_HZ                         0x8F
+#define RF_FDEVMSB_45000_HZ                         0x02
+#define RF_FDEVLSB_45000_HZ                         0xE1
+#define RF_FDEVMSB_50000_HZ                         0x03
+#define RF_FDEVLSB_50000_HZ                         0x33
+#define RF_FDEVMSB_55000_HZ                         0x03
+#define RF_FDEVLSB_55000_HZ                         0x85
+#define RF_FDEVMSB_60000_HZ                         0x03
+#define RF_FDEVLSB_60000_HZ                         0xD7
+#define RF_FDEVMSB_65000_HZ                         0x04
+#define RF_FDEVLSB_65000_HZ                         0x29
+#define RF_FDEVMSB_70000_HZ                         0x04
+#define RF_FDEVLSB_70000_HZ                         0x7B
+#define RF_FDEVMSB_75000_HZ                         0x04
+#define RF_FDEVLSB_75000_HZ                         0xCD
+#define RF_FDEVMSB_80000_HZ                         0x05
+#define RF_FDEVLSB_80000_HZ                         0x1F
+#define RF_FDEVMSB_85000_HZ                         0x05
+#define RF_FDEVLSB_85000_HZ                         0x71
+#define RF_FDEVMSB_90000_HZ                         0x05
+#define RF_FDEVLSB_90000_HZ                         0xC3
+#define RF_FDEVMSB_95000_HZ                         0x06
+#define RF_FDEVLSB_95000_HZ                         0x14
+#define RF_FDEVMSB_100000_HZ                        0x06
+#define RF_FDEVLSB_100000_HZ                        0x66
+#define RF_FDEVMSB_110000_HZ                        0x07
+#define RF_FDEVLSB_110000_HZ                        0x0A
+#define RF_FDEVMSB_120000_HZ                        0x07
+#define RF_FDEVLSB_120000_HZ                        0xAE
+#define RF_FDEVMSB_130000_HZ                        0x08
+#define RF_FDEVLSB_130000_HZ                        0x52
+#define RF_FDEVMSB_140000_HZ                        0x08
+#define RF_FDEVLSB_140000_HZ                        0xF6
+#define RF_FDEVMSB_150000_HZ                        0x09
+#define RF_FDEVLSB_150000_HZ                        0x9A
+#define RF_FDEVMSB_160000_HZ                        0x0A
+#define RF_FDEVLSB_160000_HZ                        0x3D
+#define RF_FDEVMSB_170000_HZ                        0x0A
+#define RF_FDEVLSB_170000_HZ                        0xE1
+#define RF_FDEVMSB_180000_HZ                        0x0B
+#define RF_FDEVLSB_180000_HZ                        0x85
+#define RF_FDEVMSB_190000_HZ                        0x0C
+#define RF_FDEVLSB_190000_HZ                        0x29
+#define RF_FDEVMSB_200000_HZ                        0x0C
+#define RF_FDEVLSB_200000_HZ                        0xCD
+
+/*!
+ * RegFrf (MHz)
+ */
+#define RF_FRFMSB_863_MHZ                           0xD7
+#define RF_FRFMID_863_MHZ                           0xC0
+#define RF_FRFLSB_863_MHZ                           0x00
+#define RF_FRFMSB_864_MHZ                           0xD8
+#define RF_FRFMID_864_MHZ                           0x00
+#define RF_FRFLSB_864_MHZ                           0x00
+#define RF_FRFMSB_865_MHZ                           0xD8
+#define RF_FRFMID_865_MHZ                           0x40
+#define RF_FRFLSB_865_MHZ                           0x00
+#define RF_FRFMSB_866_MHZ                           0xD8
+#define RF_FRFMID_866_MHZ                           0x80
+#define RF_FRFLSB_866_MHZ                           0x00
+#define RF_FRFMSB_867_MHZ                           0xD8
+#define RF_FRFMID_867_MHZ                           0xC0
+#define RF_FRFLSB_867_MHZ                           0x00
+#define RF_FRFMSB_868_MHZ                           0xD9
+#define RF_FRFMID_868_MHZ                           0x00
+#define RF_FRFLSB_868_MHZ                           0x00
+#define RF_FRFMSB_869_MHZ                           0xD9
+#define RF_FRFMID_869_MHZ                           0x40
+#define RF_FRFLSB_869_MHZ                           0x00
+#define RF_FRFMSB_870_MHZ                           0xD9
+#define RF_FRFMID_870_MHZ                           0x80
+#define RF_FRFLSB_870_MHZ                           0x00
+
+#define RF_FRFMSB_902_MHZ                           0xE1
+#define RF_FRFMID_902_MHZ                           0x80
+#define RF_FRFLSB_902_MHZ                           0x00
+#define RF_FRFMSB_903_MHZ                           0xE1
+#define RF_FRFMID_903_MHZ                           0xC0
+#define RF_FRFLSB_903_MHZ                           0x00
+#define RF_FRFMSB_904_MHZ                           0xE2
+#define RF_FRFMID_904_MHZ                           0x00
+#define RF_FRFLSB_904_MHZ                           0x00
+#define RF_FRFMSB_905_MHZ                           0xE2
+#define RF_FRFMID_905_MHZ                           0x40
+#define RF_FRFLSB_905_MHZ                           0x00
+#define RF_FRFMSB_906_MHZ                           0xE2
+#define RF_FRFMID_906_MHZ                           0x80
+#define RF_FRFLSB_906_MHZ                           0x00
+#define RF_FRFMSB_907_MHZ                           0xE2
+#define RF_FRFMID_907_MHZ                           0xC0
+#define RF_FRFLSB_907_MHZ                           0x00
+#define RF_FRFMSB_908_MHZ                           0xE3
+#define RF_FRFMID_908_MHZ                           0x00
+#define RF_FRFLSB_908_MHZ                           0x00
+#define RF_FRFMSB_909_MHZ                           0xE3
+#define RF_FRFMID_909_MHZ                           0x40
+#define RF_FRFLSB_909_MHZ                           0x00
+#define RF_FRFMSB_910_MHZ                           0xE3
+#define RF_FRFMID_910_MHZ                           0x80
+#define RF_FRFLSB_910_MHZ                           0x00
+#define RF_FRFMSB_911_MHZ                           0xE3
+#define RF_FRFMID_911_MHZ                           0xC0
+#define RF_FRFLSB_911_MHZ                           0x00
+#define RF_FRFMSB_912_MHZ                           0xE4
+#define RF_FRFMID_912_MHZ                           0x00
+#define RF_FRFLSB_912_MHZ                           0x00
+#define RF_FRFMSB_913_MHZ                           0xE4
+#define RF_FRFMID_913_MHZ                           0x40
+#define RF_FRFLSB_913_MHZ                           0x00
+#define RF_FRFMSB_914_MHZ                           0xE4
+#define RF_FRFMID_914_MHZ                           0x80
+#define RF_FRFLSB_914_MHZ                           0x00
+#define RF_FRFMSB_915_MHZ                           0xE4  // Default
+#define RF_FRFMID_915_MHZ                           0xC0  // Default
+#define RF_FRFLSB_915_MHZ                           0x00  // Default
+#define RF_FRFMSB_916_MHZ                           0xE5
+#define RF_FRFMID_916_MHZ                           0x00
+#define RF_FRFLSB_916_MHZ                           0x00
+#define RF_FRFMSB_917_MHZ                           0xE5
+#define RF_FRFMID_917_MHZ                           0x40
+#define RF_FRFLSB_917_MHZ                           0x00
+#define RF_FRFMSB_918_MHZ                           0xE5
+#define RF_FRFMID_918_MHZ                           0x80
+#define RF_FRFLSB_918_MHZ                           0x00
+#define RF_FRFMSB_919_MHZ                           0xE5
+#define RF_FRFMID_919_MHZ                           0xC0
+#define RF_FRFLSB_919_MHZ                           0x00
+#define RF_FRFMSB_920_MHZ                           0xE6
+#define RF_FRFMID_920_MHZ                           0x00
+#define RF_FRFLSB_920_MHZ                           0x00
+#define RF_FRFMSB_921_MHZ                           0xE6
+#define RF_FRFMID_921_MHZ                           0x40
+#define RF_FRFLSB_921_MHZ                           0x00
+#define RF_FRFMSB_922_MHZ                           0xE6
+#define RF_FRFMID_922_MHZ                           0x80
+#define RF_FRFLSB_922_MHZ                           0x00
+#define RF_FRFMSB_923_MHZ                           0xE6
+#define RF_FRFMID_923_MHZ                           0xC0
+#define RF_FRFLSB_923_MHZ                           0x00
+#define RF_FRFMSB_924_MHZ                           0xE7
+#define RF_FRFMID_924_MHZ                           0x00
+#define RF_FRFLSB_924_MHZ                           0x00
+#define RF_FRFMSB_925_MHZ                           0xE7
+#define RF_FRFMID_925_MHZ                           0x40
+#define RF_FRFLSB_925_MHZ                           0x00
+#define RF_FRFMSB_926_MHZ                           0xE7
+#define RF_FRFMID_926_MHZ                           0x80
+#define RF_FRFLSB_926_MHZ                           0x00
+#define RF_FRFMSB_927_MHZ                           0xE7
+#define RF_FRFMID_927_MHZ                           0xC0
+#define RF_FRFLSB_927_MHZ                           0x00
+#define RF_FRFMSB_928_MHZ                           0xE8
+#define RF_FRFMID_928_MHZ                           0x00
+#define RF_FRFLSB_928_MHZ                           0x00
+
+/*!
+ * RegPaConfig
+ */
+#define RF_PACONFIG_PASELECT_MASK                   0x7F
+#define RF_PACONFIG_PASELECT_PABOOST                0x80
+#define RF_PACONFIG_PASELECT_RFO                    0x00 // Default
+
+#define RF_PACONFIG_MAX_POWER_MASK                  0x8F
+
+#define RF_PACONFIG_OUTPUTPOWER_MASK                0xF0
+
+/*!
+ * RegPaRamp
+ */
+#define RF_PARAMP_MODULATIONSHAPING_MASK            0x9F
+#define RF_PARAMP_MODULATIONSHAPING_00              0x00  // Default
+#define RF_PARAMP_MODULATIONSHAPING_01              0x20
+#define RF_PARAMP_MODULATIONSHAPING_10              0x40
+#define RF_PARAMP_MODULATIONSHAPING_11              0x60
+
+#define RF_PARAMP_LOWPNTXPLL_MASK                   0xEF
+#define RF_PARAMP_LOWPNTXPLL_OFF                    0x10
+#define RF_PARAMP_LOWPNTXPLL_ON                     0x00  // Default
+
+#define RF_PARAMP_MASK                              0xF0
+#define RF_PARAMP_3400_US                           0x00
+#define RF_PARAMP_2000_US                           0x01
+#define RF_PARAMP_1000_US                           0x02
+#define RF_PARAMP_0500_US                           0x03
+#define RF_PARAMP_0250_US                           0x04
+#define RF_PARAMP_0125_US                           0x05
+#define RF_PARAMP_0100_US                           0x06
+#define RF_PARAMP_0062_US                           0x07
+#define RF_PARAMP_0050_US                           0x08
+#define RF_PARAMP_0040_US                           0x09  // Default
+#define RF_PARAMP_0031_US                           0x0A
+#define RF_PARAMP_0025_US                           0x0B
+#define RF_PARAMP_0020_US                           0x0C
+#define RF_PARAMP_0015_US                           0x0D
+#define RF_PARAMP_0012_US                           0x0E
+#define RF_PARAMP_0010_US                           0x0F
+
+/*!
+ * RegOcp
+ */
+#define RF_OCP_MASK                                 0xDF
+#define RF_OCP_ON                                   0x20  // Default
+#define RF_OCP_OFF                                  0x00
+
+#define RF_OCP_TRIM_MASK                            0xE0
+#define RF_OCP_TRIM_045_MA                          0x00
+#define RF_OCP_TRIM_050_MA                          0x01
+#define RF_OCP_TRIM_055_MA                          0x02
+#define RF_OCP_TRIM_060_MA                          0x03
+#define RF_OCP_TRIM_065_MA                          0x04
+#define RF_OCP_TRIM_070_MA                          0x05
+#define RF_OCP_TRIM_075_MA                          0x06
+#define RF_OCP_TRIM_080_MA                          0x07
+#define RF_OCP_TRIM_085_MA                          0x08
+#define RF_OCP_TRIM_090_MA                          0x09
+#define RF_OCP_TRIM_095_MA                          0x0A
+#define RF_OCP_TRIM_100_MA                          0x0B  // Default
+#define RF_OCP_TRIM_105_MA                          0x0C
+#define RF_OCP_TRIM_110_MA                          0x0D
+#define RF_OCP_TRIM_115_MA                          0x0E
+#define RF_OCP_TRIM_120_MA                          0x0F
+#define RF_OCP_TRIM_130_MA                          0x10
+#define RF_OCP_TRIM_140_MA                          0x11
+#define RF_OCP_TRIM_150_MA                          0x12
+#define RF_OCP_TRIM_160_MA                          0x13
+#define RF_OCP_TRIM_170_MA                          0x14
+#define RF_OCP_TRIM_180_MA                          0x15
+#define RF_OCP_TRIM_190_MA                          0x16
+#define RF_OCP_TRIM_200_MA                          0x17
+#define RF_OCP_TRIM_210_MA                          0x18
+#define RF_OCP_TRIM_220_MA                          0x19
+#define RF_OCP_TRIM_230_MA                          0x1A
+#define RF_OCP_TRIM_240_MA                          0x1B
+
+/*!
+ * RegLna
+ */
+#define RF_LNA_GAIN_MASK                            0x1F
+#define RF_LNA_GAIN_G1                              0x20  // Default
+#define RF_LNA_GAIN_G2                              0x40
+#define RF_LNA_GAIN_G3                              0x60
+#define RF_LNA_GAIN_G4                              0x80
+#define RF_LNA_GAIN_G5                              0xA0
+#define RF_LNA_GAIN_G6                              0xC0
+
+#define RF_LNA_BOOST_MASK                           0xFC
+#define RF_LNA_BOOST_OFF                            0x00 // Default
+#define RF_LNA_BOOST_ON                             0x03
+
+/*!
+ * RegRxConfig
+ */
+#define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK       0x7F
+#define RF_RXCONFIG_RESTARTRXONCOLLISION_ON         0x80
+#define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF        0x00 // Default
+
+#define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK         0x40 // Write only
+
+#define RF_RXCONFIG_RESTARTRXWITHPLLLOCK            0x20 // Write only
+
+#define RF_RXCONFIG_AFCAUTO_MASK                    0xEF
+#define RF_RXCONFIG_AFCAUTO_ON                      0x10
+#define RF_RXCONFIG_AFCAUTO_OFF                     0x00 // Default
+
+#define RF_RXCONFIG_AGCAUTO_MASK                    0xF7
+#define RF_RXCONFIG_AGCAUTO_ON                      0x08 // Default
+#define RF_RXCONFIG_AGCAUTO_OFF                     0x00
+
+#define RF_RXCONFIG_RXTRIGER_MASK                   0xF8
+#define RF_RXCONFIG_RXTRIGER_OFF                    0x00
+#define RF_RXCONFIG_RXTRIGER_RSSI                   0x01
+#define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT         0x06 // Default
+#define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT    0x07
+
+/*!
+ * RegRssiConfig
+ */
+#define RF_RSSICONFIG_OFFSET_MASK                   0x07
+#define RF_RSSICONFIG_OFFSET_P_00_DB                0x00  // Default
+#define RF_RSSICONFIG_OFFSET_P_01_DB                0x08
+#define RF_RSSICONFIG_OFFSET_P_02_DB                0x10
+#define RF_RSSICONFIG_OFFSET_P_03_DB                0x18
+#define RF_RSSICONFIG_OFFSET_P_04_DB                0x20
+#define RF_RSSICONFIG_OFFSET_P_05_DB                0x28
+#define RF_RSSICONFIG_OFFSET_P_06_DB                0x30
+#define RF_RSSICONFIG_OFFSET_P_07_DB                0x38
+#define RF_RSSICONFIG_OFFSET_P_08_DB                0x40
+#define RF_RSSICONFIG_OFFSET_P_09_DB                0x48
+#define RF_RSSICONFIG_OFFSET_P_10_DB                0x50
+#define RF_RSSICONFIG_OFFSET_P_11_DB                0x58
+#define RF_RSSICONFIG_OFFSET_P_12_DB                0x60
+#define RF_RSSICONFIG_OFFSET_P_13_DB                0x68
+#define RF_RSSICONFIG_OFFSET_P_14_DB                0x70
+#define RF_RSSICONFIG_OFFSET_P_15_DB                0x78
+#define RF_RSSICONFIG_OFFSET_M_16_DB                0x80
+#define RF_RSSICONFIG_OFFSET_M_15_DB                0x88
+#define RF_RSSICONFIG_OFFSET_M_14_DB                0x90
+#define RF_RSSICONFIG_OFFSET_M_13_DB                0x98
+#define RF_RSSICONFIG_OFFSET_M_12_DB                0xA0
+#define RF_RSSICONFIG_OFFSET_M_11_DB                0xA8
+#define RF_RSSICONFIG_OFFSET_M_10_DB                0xB0
+#define RF_RSSICONFIG_OFFSET_M_09_DB                0xB8
+#define RF_RSSICONFIG_OFFSET_M_08_DB                0xC0
+#define RF_RSSICONFIG_OFFSET_M_07_DB                0xC8
+#define RF_RSSICONFIG_OFFSET_M_06_DB                0xD0
+#define RF_RSSICONFIG_OFFSET_M_05_DB                0xD8
+#define RF_RSSICONFIG_OFFSET_M_04_DB                0xE0
+#define RF_RSSICONFIG_OFFSET_M_03_DB                0xE8
+#define RF_RSSICONFIG_OFFSET_M_02_DB                0xF0
+#define RF_RSSICONFIG_OFFSET_M_01_DB                0xF8
+
+#define RF_RSSICONFIG_SMOOTHING_MASK                0xF8
+#define RF_RSSICONFIG_SMOOTHING_2                   0x00
+#define RF_RSSICONFIG_SMOOTHING_4                   0x01
+#define RF_RSSICONFIG_SMOOTHING_8                   0x02  // Default
+#define RF_RSSICONFIG_SMOOTHING_16                  0x03
+#define RF_RSSICONFIG_SMOOTHING_32                  0x04
+#define RF_RSSICONFIG_SMOOTHING_64                  0x05
+#define RF_RSSICONFIG_SMOOTHING_128                 0x06
+#define RF_RSSICONFIG_SMOOTHING_256                 0x07
+
+/*!
+ * RegRssiCollision
+ */
+#define RF_RSSICOLISION_THRESHOLD                   0x0A  // Default
+
+/*!
+ * RegRssiThresh
+ */
+#define RF_RSSITHRESH_THRESHOLD                     0xFF  // Default
+
+/*!
+ * RegRssiValue (Read Only)
+ */
+
+/*!
+ * RegRxBw
+ */
+#define RF_RXBW_MANT_MASK                           0xE7
+#define RF_RXBW_MANT_16                             0x00
+#define RF_RXBW_MANT_20                             0x08
+#define RF_RXBW_MANT_24                             0x10  // Default
+
+#define RF_RXBW_EXP_MASK                            0xF8
+#define RF_RXBW_EXP_0                               0x00
+#define RF_RXBW_EXP_1                               0x01
+#define RF_RXBW_EXP_2                               0x02
+#define RF_RXBW_EXP_3                               0x03
+#define RF_RXBW_EXP_4                               0x04
+#define RF_RXBW_EXP_5                               0x05  // Default
+#define RF_RXBW_EXP_6                               0x06
+#define RF_RXBW_EXP_7                               0x07
+
+/*!
+ * RegAfcBw
+ */
+#define RF_AFCBW_MANTAFC_MASK                       0xE7
+#define RF_AFCBW_MANTAFC_16                         0x00
+#define RF_AFCBW_MANTAFC_20                         0x08  // Default
+#define RF_AFCBW_MANTAFC_24                         0x10
+
+#define RF_AFCBW_EXPAFC_MASK                        0xF8
+#define RF_AFCBW_EXPAFC_0                           0x00
+#define RF_AFCBW_EXPAFC_1                           0x01
+#define RF_AFCBW_EXPAFC_2                           0x02
+#define RF_AFCBW_EXPAFC_3                           0x03  // Default
+#define RF_AFCBW_EXPAFC_4                           0x04
+#define RF_AFCBW_EXPAFC_5                           0x05
+#define RF_AFCBW_EXPAFC_6                           0x06
+#define RF_AFCBW_EXPAFC_7                           0x07
+
+/*!
+ * RegOokPeak
+ */
+#define RF_OOKPEAK_BITSYNC_MASK                     0xDF  // Default
+#define RF_OOKPEAK_BITSYNC_ON                       0x20  // Default
+#define RF_OOKPEAK_BITSYNC_OFF                      0x00
+
+#define RF_OOKPEAK_OOKTHRESHTYPE_MASK               0xE7
+#define RF_OOKPEAK_OOKTHRESHTYPE_FIXED              0x00
+#define RF_OOKPEAK_OOKTHRESHTYPE_PEAK               0x08  // Default
+#define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE            0x10
+
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK           0xF8
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB         0x00  // Default
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB         0x01
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB         0x02
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB         0x03
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB         0x04
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB         0x05
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB         0x06
+#define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB         0x07
+
+/*!
+ * RegOokFix
+ */
+#define RF_OOKFIX_OOKFIXEDTHRESHOLD                 0x0C  // Default
+
+/*!
+ * RegOokAvg
+ */
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK             0x1F
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_000              0x00  // Default
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_001              0x20
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_010              0x40
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_011              0x60
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_100              0x80
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_101              0xA0
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_110              0xC0
+#define RF_OOKAVG_OOKPEAKTHRESHDEC_111              0xE0
+
+#define RF_OOKAVG_AVERAGEOFFSET_MASK                0xF3
+#define RF_OOKAVG_AVERAGEOFFSET_0_DB                0x00  // Default
+#define RF_OOKAVG_AVERAGEOFFSET_2_DB                0x04
+#define RF_OOKAVG_AVERAGEOFFSET_4_DB                0x08
+#define RF_OOKAVG_AVERAGEOFFSET_6_DB                0x0C
+
+#define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK         0xFC
+#define RF_OOKAVG_OOKAVERAGETHRESHFILT_00           0x00
+#define RF_OOKAVG_OOKAVERAGETHRESHFILT_01           0x01
+#define RF_OOKAVG_OOKAVERAGETHRESHFILT_10           0x02  // Default
+#define RF_OOKAVG_OOKAVERAGETHRESHFILT_11           0x03
+
+/*!
+ * RegAfcFei
+ */
+#define RF_AFCFEI_AGCSTART                          0x10
+
+#define RF_AFCFEI_AFCCLEAR                          0x02
+
+#define RF_AFCFEI_AFCAUTOCLEAR_MASK                 0xFE
+#define RF_AFCFEI_AFCAUTOCLEAR_ON                   0x01
+#define RF_AFCFEI_AFCAUTOCLEAR_OFF                  0x00  // Default
+
+/*!
+ * RegAfcMsb (Read Only)
+ */
+
+/*!
+ * RegAfcLsb (Read Only)
+ */
+
+/*!
+ * RegFeiMsb (Read Only)
+ */
+
+/*!
+ * RegFeiLsb (Read Only)
+ */
+
+/*!
+ * RegPreambleDetect
+ */
+#define RF_PREAMBLEDETECT_DETECTOR_MASK             0x7F
+#define RF_PREAMBLEDETECT_DETECTOR_ON               0x80  // Default
+#define RF_PREAMBLEDETECT_DETECTOR_OFF              0x00
+
+#define RF_PREAMBLEDETECT_DETECTORSIZE_MASK         0x9F
+#define RF_PREAMBLEDETECT_DETECTORSIZE_1            0x00
+#define RF_PREAMBLEDETECT_DETECTORSIZE_2            0x20  // Default
+#define RF_PREAMBLEDETECT_DETECTORSIZE_3            0x40
+#define RF_PREAMBLEDETECT_DETECTORSIZE_4            0x60
+
+#define RF_PREAMBLEDETECT_DETECTORTOL_MASK          0xE0
+#define RF_PREAMBLEDETECT_DETECTORTOL_0             0x00
+#define RF_PREAMBLEDETECT_DETECTORTOL_1             0x01
+#define RF_PREAMBLEDETECT_DETECTORTOL_2             0x02
+#define RF_PREAMBLEDETECT_DETECTORTOL_3             0x03
+#define RF_PREAMBLEDETECT_DETECTORTOL_4             0x04
+#define RF_PREAMBLEDETECT_DETECTORTOL_5             0x05
+#define RF_PREAMBLEDETECT_DETECTORTOL_6             0x06
+#define RF_PREAMBLEDETECT_DETECTORTOL_7             0x07
+#define RF_PREAMBLEDETECT_DETECTORTOL_8             0x08
+#define RF_PREAMBLEDETECT_DETECTORTOL_9             0x09
+#define RF_PREAMBLEDETECT_DETECTORTOL_10            0x0A  // Default
+#define RF_PREAMBLEDETECT_DETECTORTOL_11            0x0B
+#define RF_PREAMBLEDETECT_DETECTORTOL_12            0x0C
+#define RF_PREAMBLEDETECT_DETECTORTOL_13            0x0D
+#define RF_PREAMBLEDETECT_DETECTORTOL_14            0x0E
+#define RF_PREAMBLEDETECT_DETECTORTOL_15            0x0F
+#define RF_PREAMBLEDETECT_DETECTORTOL_16            0x10
+#define RF_PREAMBLEDETECT_DETECTORTOL_17            0x11
+#define RF_PREAMBLEDETECT_DETECTORTOL_18            0x12
+#define RF_PREAMBLEDETECT_DETECTORTOL_19            0x13
+#define RF_PREAMBLEDETECT_DETECTORTOL_20            0x14
+#define RF_PREAMBLEDETECT_DETECTORTOL_21            0x15
+#define RF_PREAMBLEDETECT_DETECTORTOL_22            0x16
+#define RF_PREAMBLEDETECT_DETECTORTOL_23            0x17
+#define RF_PREAMBLEDETECT_DETECTORTOL_24            0x18
+#define RF_PREAMBLEDETECT_DETECTORTOL_25            0x19
+#define RF_PREAMBLEDETECT_DETECTORTOL_26            0x1A
+#define RF_PREAMBLEDETECT_DETECTORTOL_27            0x1B
+#define RF_PREAMBLEDETECT_DETECTORTOL_28            0x1C
+#define RF_PREAMBLEDETECT_DETECTORTOL_29            0x1D
+#define RF_PREAMBLEDETECT_DETECTORTOL_30            0x1E
+#define RF_PREAMBLEDETECT_DETECTORTOL_31            0x1F
+
+/*!
+ * RegRxTimeout1
+ */
+#define RF_RXTIMEOUT1_TIMEOUTRXRSSI                 0x00  // Default
+
+/*!
+ * RegRxTimeout2
+ */
+#define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE             0x00  // Default
+
+/*!
+ * RegRxTimeout3
+ */
+#define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC             0x00  // Default
+
+/*!
+ * RegRxDelay
+ */
+#define RF_RXDELAY_INTERPACKETRXDELAY               0x00  // Default
+
+/*!
+ * RegOsc
+ */
+#define RF_OSC_RCCALSTART                           0x08
+
+#define RF_OSC_CLKOUT_MASK                          0xF8
+#define RF_OSC_CLKOUT_32_MHZ                        0x00
+#define RF_OSC_CLKOUT_16_MHZ                        0x01
+#define RF_OSC_CLKOUT_8_MHZ                         0x02
+#define RF_OSC_CLKOUT_4_MHZ                         0x03
+#define RF_OSC_CLKOUT_2_MHZ                         0x04
+#define RF_OSC_CLKOUT_1_MHZ                         0x05  // Default
+#define RF_OSC_CLKOUT_RC                            0x06
+#define RF_OSC_CLKOUT_OFF                           0x07
+
+/*!
+ * RegPreambleMsb/RegPreambleLsb
+ */
+#define RF_PREAMBLEMSB_SIZE                         0x00  // Default
+#define RF_PREAMBLELSB_SIZE                         0x03  // Default
+
+/*!
+ * RegSyncConfig
+ */
+#define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK        0x3F
+#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON  0x80  // Default
+#define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40
+#define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF         0x00
+
+
+#define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK         0xDF
+#define RF_SYNCCONFIG_PREAMBLEPOLARITY_55           0x20
+#define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA           0x00  // Default
+
+#define RF_SYNCCONFIG_SYNC_MASK                     0xEF
+#define RF_SYNCCONFIG_SYNC_ON                       0x10  // Default
+#define RF_SYNCCONFIG_SYNC_OFF                      0x00
+
+
+#define RF_SYNCCONFIG_SYNCSIZE_MASK                 0xF8
+#define RF_SYNCCONFIG_SYNCSIZE_1                    0x00
+#define RF_SYNCCONFIG_SYNCSIZE_2                    0x01
+#define RF_SYNCCONFIG_SYNCSIZE_3                    0x02
+#define RF_SYNCCONFIG_SYNCSIZE_4                    0x03  // Default
+#define RF_SYNCCONFIG_SYNCSIZE_5                    0x04
+#define RF_SYNCCONFIG_SYNCSIZE_6                    0x05
+#define RF_SYNCCONFIG_SYNCSIZE_7                    0x06
+#define RF_SYNCCONFIG_SYNCSIZE_8                    0x07
+
+/*!
+ * RegSyncValue1-8
+ */
+#define RF_SYNCVALUE1_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE2_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE3_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE4_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE5_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE6_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE7_SYNCVALUE                     0x01  // Default
+#define RF_SYNCVALUE8_SYNCVALUE                     0x01  // Default
+
+/*!
+ * RegPacketConfig1
+ */
+#define RF_PACKETCONFIG1_PACKETFORMAT_MASK          0x7F
+#define RF_PACKETCONFIG1_PACKETFORMAT_FIXED         0x00
+#define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE      0x80  // Default
+
+#define RF_PACKETCONFIG1_DCFREE_MASK                0x9F
+#define RF_PACKETCONFIG1_DCFREE_OFF                 0x00  // Default
+#define RF_PACKETCONFIG1_DCFREE_MANCHESTER          0x20
+#define RF_PACKETCONFIG1_DCFREE_WHITENING           0x40
+
+#define RF_PACKETCONFIG1_CRC_MASK                   0xEF
+#define RF_PACKETCONFIG1_CRC_ON                     0x10  // Default
+#define RF_PACKETCONFIG1_CRC_OFF                    0x00
+
+#define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK          0xF7
+#define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON            0x00  // Default
+#define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF           0x08
+
+#define RF_PACKETCONFIG1_ADDRSFILTERING_MASK         0xF9
+#define RF_PACKETCONFIG1_ADDRSFILTERING_OFF          0x00  // Default
+#define RF_PACKETCONFIG1_ADDRSFILTERING_NODE         0x02
+#define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04
+
+#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK      0xFE
+#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT     0x00  // Default
+#define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM       0x01
+
+/*!
+ * RegPacketConfig2
+ */
+
+#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK      0x7F
+#define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE           0x80
+#define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE          0x00  // Default
+
+#define RF_PACKETCONFIG2_DATAMODE_MASK              0xBF
+#define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS        0x00
+#define RF_PACKETCONFIG2_DATAMODE_PACKET            0x40  // Default
+
+#define RF_PACKETCONFIG2_IOHOME_MASK                0xDF
+#define RF_PACKETCONFIG2_IOHOME_ON                  0x20
+#define RF_PACKETCONFIG2_IOHOME_OFF                 0x00  // Default
+
+#define RF_PACKETCONFIG2_BEACON_MASK                0xF7
+#define RF_PACKETCONFIG2_BEACON_ON                  0x08
+#define RF_PACKETCONFIG2_BEACON_OFF                 0x00  // Default
+
+#define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK     0xF8
+
+/*!
+ * RegPayloadLength
+ */
+#define RF_PAYLOADLENGTH_LENGTH                     0x40  // Default
+
+/*!
+ * RegNodeAdrs
+ */
+#define RF_NODEADDRESS_ADDRESS                      0x00
+
+/*!
+ * RegBroadcastAdrs
+ */
+#define RF_BROADCASTADDRESS_ADDRESS                 0x00
+
+/*!
+ * RegFifoThresh
+ */
+#define RF_FIFOTHRESH_TXSTARTCONDITION_MASK         0x7F
+#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH   0x00  // Default
+#define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80
+
+#define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK            0xC0
+#define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD       0x0F  // Default
+
+/*!
+ * RegSeqConfig1
+ */
+#define RF_SEQCONFIG1_SEQUENCER_START               0x80
+
+#define RF_SEQCONFIG1_SEQUENCER_STOP                0x40
+
+#define RF_SEQCONFIG1_IDLEMODE_MASK                 0xDF
+#define RF_SEQCONFIG1_IDLEMODE_SLEEP                0x20
+#define RF_SEQCONFIG1_IDLEMODE_STANDBY              0x00  // Default
+
+#define RF_SEQCONFIG1_FROMSTART_MASK                0xE7
+#define RF_SEQCONFIG1_FROMSTART_TOLPS               0x00  // Default
+#define RF_SEQCONFIG1_FROMSTART_TORX                0x08
+#define RF_SEQCONFIG1_FROMSTART_TOTX                0x10
+#define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL    0x18
+
+#define RF_SEQCONFIG1_LPS_MASK                      0xFB
+#define RF_SEQCONFIG1_LPS_SEQUENCER_OFF             0x00  // Default
+#define RF_SEQCONFIG1_LPS_IDLE                      0x04
+
+#define RF_SEQCONFIG1_FROMIDLE_MASK                 0xFD
+#define RF_SEQCONFIG1_FROMIDLE_TOTX                 0x00  // Default
+#define RF_SEQCONFIG1_FROMIDLE_TORX                 0x02
+
+#define RF_SEQCONFIG1_FROMTX_MASK                   0xFE
+#define RF_SEQCONFIG1_FROMTX_TOLPS                  0x00  // Default
+#define RF_SEQCONFIG1_FROMTX_TORX                   0x01
+
+/*!
+ * RegSeqConfig2
+ */
+#define RF_SEQCONFIG2_FROMRX_MASK                   0x1F
+#define RF_SEQCONFIG2_FROMRX_TOUNUSED_000           0x00  // Default
+#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY       0x20
+#define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY         0x40
+#define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK        0x60
+#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI  0x80
+#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC  0xA0
+#define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0
+#define RF_SEQCONFIG2_FROMRX_TOUNUSED_111           0xE0
+
+#define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK            0xE7
+#define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART     0x00  // Default
+#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX            0x08
+#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS           0x10
+#define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF  0x18
+
+#define RF_SEQCONFIG2_FROMRXPKT_MASK                0xF8
+#define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF      0x00  // Default
+#define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY    0x01
+#define RF_SEQCONFIG2_FROMRXPKT_TOLPS               0x02
+#define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX     0x03
+#define RF_SEQCONFIG2_FROMRXPKT_TORX                0x04
+
+/*!
+ * RegTimerResol
+ */
+#define RF_TIMERRESOL_TIMER1RESOL_MASK              0xF3
+#define RF_TIMERRESOL_TIMER1RESOL_OFF               0x00  // Default
+#define RF_TIMERRESOL_TIMER1RESOL_000064_US         0x04
+#define RF_TIMERRESOL_TIMER1RESOL_004100_US         0x08
+#define RF_TIMERRESOL_TIMER1RESOL_262000_US         0x0C
+
+#define RF_TIMERRESOL_TIMER2RESOL_MASK              0xFC
+#define RF_TIMERRESOL_TIMER2RESOL_OFF               0x00  // Default
+#define RF_TIMERRESOL_TIMER2RESOL_000064_US         0x01
+#define RF_TIMERRESOL_TIMER2RESOL_004100_US         0x02
+#define RF_TIMERRESOL_TIMER2RESOL_262000_US         0x03
+
+/*!
+ * RegTimer1Coef
+ */
+#define RF_TIMER1COEF_TIMER1COEFFICIENT             0xF5  // Default
+
+/*!
+ * RegTimer2Coef
+ */
+#define RF_TIMER2COEF_TIMER2COEFFICIENT             0x20  // Default
+
+/*!
+ * RegImageCal
+ */
+#define RF_IMAGECAL_AUTOIMAGECAL_MASK               0x7F
+#define RF_IMAGECAL_AUTOIMAGECAL_ON                 0x80
+#define RF_IMAGECAL_AUTOIMAGECAL_OFF                0x00  // Default
+
+#define RF_IMAGECAL_IMAGECAL_MASK                   0xBF
+#define RF_IMAGECAL_IMAGECAL_START                  0x40
+
+#define RF_IMAGECAL_IMAGECAL_RUNNING                0x20
+#define RF_IMAGECAL_IMAGECAL_DONE                   0x00  // Default
+
+#define RF_IMAGECAL_TEMPCHANGE_HIGHER               0x08
+#define RF_IMAGECAL_TEMPCHANGE_LOWER                0x00
+
+#define RF_IMAGECAL_TEMPTHRESHOLD_MASK              0xF9
+#define RF_IMAGECAL_TEMPTHRESHOLD_05                0x00
+#define RF_IMAGECAL_TEMPTHRESHOLD_10                0x02  // Default
+#define RF_IMAGECAL_TEMPTHRESHOLD_15                0x04
+#define RF_IMAGECAL_TEMPTHRESHOLD_20                0x06
+
+#define RF_IMAGECAL_TEMPMONITOR_MASK                0xFE
+#define RF_IMAGECAL_TEMPMONITOR_ON                  0x00 // Default
+#define RF_IMAGECAL_TEMPMONITOR_OFF                 0x01
+
+/*!
+ * RegTemp (Read Only)
+ */
+
+/*!
+ * RegLowBat
+ */
+#define RF_LOWBAT_MASK                              0xF7
+#define RF_LOWBAT_ON                                0x08
+#define RF_LOWBAT_OFF                               0x00  // Default
+
+#define RF_LOWBAT_TRIM_MASK                         0xF8
+#define RF_LOWBAT_TRIM_1695                         0x00
+#define RF_LOWBAT_TRIM_1764                         0x01
+#define RF_LOWBAT_TRIM_1835                         0x02  // Default
+#define RF_LOWBAT_TRIM_1905                         0x03
+#define RF_LOWBAT_TRIM_1976                         0x04
+#define RF_LOWBAT_TRIM_2045                         0x05
+#define RF_LOWBAT_TRIM_2116                         0x06
+#define RF_LOWBAT_TRIM_2185                         0x07
+
+/*!
+ * RegIrqFlags1
+ */
+#define RF_IRQFLAGS1_MODEREADY                      0x80
+
+#define RF_IRQFLAGS1_RXREADY                        0x40
+
+#define RF_IRQFLAGS1_TXREADY                        0x20
+
+#define RF_IRQFLAGS1_PLLLOCK                        0x10
+
+#define RF_IRQFLAGS1_RSSI                           0x08
+
+#define RF_IRQFLAGS1_TIMEOUT                        0x04
+
+#define RF_IRQFLAGS1_PREAMBLEDETECT                 0x02
+
+#define RF_IRQFLAGS1_SYNCADDRESSMATCH               0x01
+
+/*!
+ * RegIrqFlags2
+ */
+#define RF_IRQFLAGS2_FIFOFULL                       0x80
+
+#define RF_IRQFLAGS2_FIFOEMPTY                      0x40
+
+#define RF_IRQFLAGS2_FIFOLEVEL                      0x20
+
+#define RF_IRQFLAGS2_FIFOOVERRUN                    0x10
+
+#define RF_IRQFLAGS2_PACKETSENT                     0x08
+
+#define RF_IRQFLAGS2_PAYLOADREADY                   0x04
+
+#define RF_IRQFLAGS2_CRCOK                          0x02
+
+#define RF_IRQFLAGS2_LOWBAT                         0x01
+
+/*!
+ * RegDioMapping1
+ */
+#define RF_DIOMAPPING1_DIO0_MASK                    0x3F
+#define RF_DIOMAPPING1_DIO0_00                      0x00  // Default
+#define RF_DIOMAPPING1_DIO0_01                      0x40
+#define RF_DIOMAPPING1_DIO0_10                      0x80
+#define RF_DIOMAPPING1_DIO0_11                      0xC0
+
+#define RF_DIOMAPPING1_DIO1_MASK                    0xCF
+#define RF_DIOMAPPING1_DIO1_00                      0x00  // Default
+#define RF_DIOMAPPING1_DIO1_01                      0x10
+#define RF_DIOMAPPING1_DIO1_10                      0x20
+#define RF_DIOMAPPING1_DIO1_11                      0x30
+
+#define RF_DIOMAPPING1_DIO2_MASK                    0xF3
+#define RF_DIOMAPPING1_DIO2_00                      0x00  // Default
+#define RF_DIOMAPPING1_DIO2_01                      0x04
+#define RF_DIOMAPPING1_DIO2_10                      0x08
+#define RF_DIOMAPPING1_DIO2_11                      0x0C
+
+#define RF_DIOMAPPING1_DIO3_MASK                    0xFC
+#define RF_DIOMAPPING1_DIO3_00                      0x00  // Default
+#define RF_DIOMAPPING1_DIO3_01                      0x01
+#define RF_DIOMAPPING1_DIO3_10                      0x02
+#define RF_DIOMAPPING1_DIO3_11                      0x03
+
+/*!
+ * RegDioMapping2
+ */
+#define RF_DIOMAPPING2_DIO4_MASK                    0x3F
+#define RF_DIOMAPPING2_DIO4_00                      0x00  // Default
+#define RF_DIOMAPPING2_DIO4_01                      0x40
+#define RF_DIOMAPPING2_DIO4_10                      0x80
+#define RF_DIOMAPPING2_DIO4_11                      0xC0
+
+#define RF_DIOMAPPING2_DIO5_MASK                    0xCF
+#define RF_DIOMAPPING2_DIO5_00                      0x00  // Default
+#define RF_DIOMAPPING2_DIO5_01                      0x10
+#define RF_DIOMAPPING2_DIO5_10                      0x20
+#define RF_DIOMAPPING2_DIO5_11                      0x30
+
+#define RF_DIOMAPPING2_MAP_MASK                     0xFE
+#define RF_DIOMAPPING2_MAP_PREAMBLEDETECT           0x01
+#define RF_DIOMAPPING2_MAP_RSSI                     0x00  // Default
+
+/*!
+ * RegVersion (Read Only)
+ */
+
+/*!
+ * RegPllHop
+ */
+#define RF_PLLHOP_FASTHOP_MASK                      0x7F
+#define RF_PLLHOP_FASTHOP_ON                        0x80
+#define RF_PLLHOP_FASTHOP_OFF                       0x00 // Default
+
+/*!
+ * RegTcxo
+ */
+#define RF_TCXO_TCXOINPUT_MASK                      0xEF
+#define RF_TCXO_TCXOINPUT_ON                        0x10
+#define RF_TCXO_TCXOINPUT_OFF                       0x00  // Default
+
+/*!
+ * RegPaDac
+ */
+#define RF_PADAC_20DBM_MASK                         0xF8
+#define RF_PADAC_20DBM_ON                           0x07
+#define RF_PADAC_20DBM_OFF                          0x04  // Default
+
+/*!
+ * RegFormerTemp
+ */
+
+/*!
+ * RegBitrateFrac
+ */
+#define RF_BITRATEFRAC_MASK                         0xF0
+
+/*!
+ * RegAgcRef
+ */
+
+/*!
+ * RegAgcThresh1
+ */
+
+/*!
+ * RegAgcThresh2
+ */
+
+/*!
+ * RegAgcThresh3
+ */
+
+/*!
+ * RegPll
+ */
+#define RF_PLL_BANDWIDTH_MASK                       0x3F
+#define RF_PLL_BANDWIDTH_75                         0x00
+#define RF_PLL_BANDWIDTH_150                        0x40
+#define RF_PLL_BANDWIDTH_225                        0x80
+#define RF_PLL_BANDWIDTH_300                        0xC0  // Default
+
+#endif // __SX1276_REGS_FSK_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/lora-radio/sx127x/sx127xRegs-LoRa.h

@@ -0,0 +1,573 @@
+/*!
+ * \file      sx1276Regs-LoRa.h
+ *
+ * \brief     SX1276 LoRa modem registers and bits definitions
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ */
+#ifndef __SX1276_REGS_LORA_H__
+#define __SX1276_REGS_LORA_H__
+
+/*!
+ * ============================================================================
+ * SX1276 Internal registers Address
+ * ============================================================================
+ */
+#define REG_LR_FIFO                                 0x00
+// Common settings
+#define REG_LR_OPMODE                               0x01
+#define REG_LR_FRFMSB                               0x06
+#define REG_LR_FRFMID                               0x07
+#define REG_LR_FRFLSB                               0x08
+// Tx settings
+#define REG_LR_PACONFIG                             0x09
+#define REG_LR_PARAMP                               0x0A
+#define REG_LR_OCP                                  0x0B
+// Rx settings
+#define REG_LR_LNA                                  0x0C
+// LoRa registers
+#define REG_LR_FIFOADDRPTR                          0x0D
+#define REG_LR_FIFOTXBASEADDR                       0x0E
+#define REG_LR_FIFORXBASEADDR                       0x0F
+#define REG_LR_FIFORXCURRENTADDR                    0x10
+#define REG_LR_IRQFLAGSMASK                         0x11
+#define REG_LR_IRQFLAGS                             0x12
+#define REG_LR_RXNBBYTES                            0x13
+#define REG_LR_RXHEADERCNTVALUEMSB                  0x14
+#define REG_LR_RXHEADERCNTVALUELSB                  0x15
+#define REG_LR_RXPACKETCNTVALUEMSB                  0x16
+#define REG_LR_RXPACKETCNTVALUELSB                  0x17
+#define REG_LR_MODEMSTAT                            0x18
+#define REG_LR_PKTSNRVALUE                          0x19
+#define REG_LR_PKTRSSIVALUE                         0x1A
+#define REG_LR_RSSIVALUE                            0x1B
+#define REG_LR_HOPCHANNEL                           0x1C
+#define REG_LR_MODEMCONFIG1                         0x1D
+#define REG_LR_MODEMCONFIG2                         0x1E
+#define REG_LR_SYMBTIMEOUTLSB                       0x1F
+#define REG_LR_PREAMBLEMSB                          0x20
+#define REG_LR_PREAMBLELSB                          0x21
+#define REG_LR_PAYLOADLENGTH                        0x22
+#define REG_LR_PAYLOADMAXLENGTH                     0x23
+#define REG_LR_HOPPERIOD                            0x24
+#define REG_LR_FIFORXBYTEADDR                       0x25
+#define REG_LR_MODEMCONFIG3                         0x26
+#define REG_LR_FEIMSB                               0x28
+#define REG_LR_FEIMID                               0x29
+#define REG_LR_FEILSB                               0x2A
+#define REG_LR_RSSIWIDEBAND                         0x2C
+#define REG_LR_IFFREQ1                              0x2F
+#define REG_LR_IFFREQ2                              0x30
+#define REG_LR_DETECTOPTIMIZE                       0x31
+#define REG_LR_INVERTIQ                             0x33
+#define REG_LR_HIGHBWOPTIMIZE1                      0x36
+#define REG_LR_DETECTIONTHRESHOLD                   0x37
+#define REG_LR_SYNCWORD                             0x39
+#define REG_LR_HIGHBWOPTIMIZE2                      0x3A
+#define REG_LR_INVERTIQ2                            0x3B
+
+// end of documented register in datasheet
+// I/O settings
+#define REG_LR_DIOMAPPING1                          0x40
+#define REG_LR_DIOMAPPING2                          0x41
+// Version
+#define REG_LR_VERSION                              0x42
+// Additional settings
+#define REG_LR_PLLHOP                               0x44
+#define REG_LR_TCXO                                 0x4B
+#define REG_LR_PADAC                                0x4D
+#define REG_LR_FORMERTEMP                           0x5B
+#define REG_LR_BITRATEFRAC                          0x5D
+#define REG_LR_AGCREF                               0x61
+#define REG_LR_AGCTHRESH1                           0x62
+#define REG_LR_AGCTHRESH2                           0x63
+#define REG_LR_AGCTHRESH3                           0x64
+#define REG_LR_PLL                                  0x70
+
+/*!
+ * ============================================================================
+ * SX1276 LoRa bits control definition
+ * ============================================================================
+ */
+
+/*!
+ * RegFifo
+ */
+
+/*!
+ * RegOpMode
+ */
+#define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F
+#define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
+#define RFLR_OPMODE_LONGRANGEMODE_ON                0x80
+
+#define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF
+#define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40
+#define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
+
+#define RFLR_OPMODE_FREQMODE_ACCESS_MASK            0xF7
+#define RFLR_OPMODE_FREQMODE_ACCESS_LF              0x08 // Default
+#define RFLR_OPMODE_FREQMODE_ACCESS_HF              0x00
+
+#define RFLR_OPMODE_MASK                            0xF8
+#define RFLR_OPMODE_SLEEP                           0x00
+#define RFLR_OPMODE_STANDBY                         0x01 // Default
+#define RFLR_OPMODE_SYNTHESIZER_TX                  0x02
+#define RFLR_OPMODE_TRANSMITTER                     0x03
+#define RFLR_OPMODE_SYNTHESIZER_RX                  0x04
+#define RFLR_OPMODE_RECEIVER                        0x05
+// LoRa specific modes
+#define RFLR_OPMODE_RECEIVER_SINGLE                 0x06
+#define RFLR_OPMODE_CAD                             0x07
+
+/*!
+ * RegFrf (MHz)
+ */
+#define RFLR_FRFMSB_434_MHZ                         0x6C // Default
+#define RFLR_FRFMID_434_MHZ                         0x80 // Default
+#define RFLR_FRFLSB_434_MHZ                         0x00 // Default
+
+/*!
+ * RegPaConfig
+ */
+#define RFLR_PACONFIG_PASELECT_MASK                 0x7F
+#define RFLR_PACONFIG_PASELECT_PABOOST              0x80
+#define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
+
+#define RFLR_PACONFIG_MAX_POWER_MASK                0x8F
+
+#define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0
+
+/*!
+ * RegPaRamp
+ */
+#define RFLR_PARAMP_TXBANDFORCE_MASK                0xEF
+#define RFLR_PARAMP_TXBANDFORCE_BAND_SEL            0x10
+#define RFLR_PARAMP_TXBANDFORCE_AUTO                0x00 // Default
+
+#define RFLR_PARAMP_MASK                            0xF0
+#define RFLR_PARAMP_3400_US                         0x00
+#define RFLR_PARAMP_2000_US                         0x01
+#define RFLR_PARAMP_1000_US                         0x02
+#define RFLR_PARAMP_0500_US                         0x03
+#define RFLR_PARAMP_0250_US                         0x04
+#define RFLR_PARAMP_0125_US                         0x05
+#define RFLR_PARAMP_0100_US                         0x06
+#define RFLR_PARAMP_0062_US                         0x07
+#define RFLR_PARAMP_0050_US                         0x08
+#define RFLR_PARAMP_0040_US                         0x09 // Default
+#define RFLR_PARAMP_0031_US                         0x0A
+#define RFLR_PARAMP_0025_US                         0x0B
+#define RFLR_PARAMP_0020_US                         0x0C
+#define RFLR_PARAMP_0015_US                         0x0D
+#define RFLR_PARAMP_0012_US                         0x0E
+#define RFLR_PARAMP_0010_US                         0x0F
+
+/*!
+ * RegOcp
+ */
+#define RFLR_OCP_MASK                               0xDF
+#define RFLR_OCP_ON                                 0x20 // Default
+#define RFLR_OCP_OFF                                0x00
+
+#define RFLR_OCP_TRIM_MASK                          0xE0
+#define RFLR_OCP_TRIM_045_MA                        0x00
+#define RFLR_OCP_TRIM_050_MA                        0x01
+#define RFLR_OCP_TRIM_055_MA                        0x02
+#define RFLR_OCP_TRIM_060_MA                        0x03
+#define RFLR_OCP_TRIM_065_MA                        0x04
+#define RFLR_OCP_TRIM_070_MA                        0x05
+#define RFLR_OCP_TRIM_075_MA                        0x06
+#define RFLR_OCP_TRIM_080_MA                        0x07
+#define RFLR_OCP_TRIM_085_MA                        0x08
+#define RFLR_OCP_TRIM_090_MA                        0x09
+#define RFLR_OCP_TRIM_095_MA                        0x0A
+#define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
+#define RFLR_OCP_TRIM_105_MA                        0x0C
+#define RFLR_OCP_TRIM_110_MA                        0x0D
+#define RFLR_OCP_TRIM_115_MA                        0x0E
+#define RFLR_OCP_TRIM_120_MA                        0x0F
+#define RFLR_OCP_TRIM_130_MA                        0x10
+#define RFLR_OCP_TRIM_140_MA                        0x11
+#define RFLR_OCP_TRIM_150_MA                        0x12
+#define RFLR_OCP_TRIM_160_MA                        0x13
+#define RFLR_OCP_TRIM_170_MA                        0x14
+#define RFLR_OCP_TRIM_180_MA                        0x15
+#define RFLR_OCP_TRIM_190_MA                        0x16
+#define RFLR_OCP_TRIM_200_MA                        0x17
+#define RFLR_OCP_TRIM_210_MA                        0x18
+#define RFLR_OCP_TRIM_220_MA                        0x19
+#define RFLR_OCP_TRIM_230_MA                        0x1A
+#define RFLR_OCP_TRIM_240_MA                        0x1B
+
+/*!
+ * RegLna
+ */
+#define RFLR_LNA_GAIN_MASK                          0x1F
+#define RFLR_LNA_GAIN_G1                            0x20 // Default
+#define RFLR_LNA_GAIN_G2                            0x40
+#define RFLR_LNA_GAIN_G3                            0x60
+#define RFLR_LNA_GAIN_G4                            0x80
+#define RFLR_LNA_GAIN_G5                            0xA0
+#define RFLR_LNA_GAIN_G6                            0xC0
+
+#define RFLR_LNA_BOOST_LF_MASK                      0xE7
+#define RFLR_LNA_BOOST_LF_DEFAULT                   0x00 // Default
+
+#define RFLR_LNA_BOOST_HF_MASK                      0xFC
+#define RFLR_LNA_BOOST_HF_OFF                       0x00 // Default
+#define RFLR_LNA_BOOST_HF_ON                        0x03
+
+/*!
+ * RegFifoAddrPtr
+ */
+#define RFLR_FIFOADDRPTR                            0x00 // Default
+
+/*!
+ * RegFifoTxBaseAddr
+ */
+#define RFLR_FIFOTXBASEADDR                         0x80 // Default
+
+/*!
+ * RegFifoTxBaseAddr
+ */
+#define RFLR_FIFORXBASEADDR                         0x00 // Default
+
+/*!
+ * RegFifoRxCurrentAddr (Read Only)
+ */
+
+/*!
+ * RegIrqFlagsMask
+ */
+#define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80
+#define RFLR_IRQFLAGS_RXDONE_MASK                   0x40
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20
+#define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10
+#define RFLR_IRQFLAGS_TXDONE_MASK                   0x08
+#define RFLR_IRQFLAGS_CADDONE_MASK                  0x04
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02
+#define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01
+
+/*!
+ * RegIrqFlags
+ */
+#define RFLR_IRQFLAGS_RXTIMEOUT                     0x80
+#define RFLR_IRQFLAGS_RXDONE                        0x40
+#define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20
+#define RFLR_IRQFLAGS_VALIDHEADER                   0x10
+#define RFLR_IRQFLAGS_TXDONE                        0x08
+#define RFLR_IRQFLAGS_CADDONE                       0x04
+#define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02
+#define RFLR_IRQFLAGS_CADDETECTED                   0x01
+
+/*!
+ * RegFifoRxNbBytes (Read Only)
+ */
+
+/*!
+ * RegRxHeaderCntValueMsb (Read Only)
+ */
+
+/*!
+ * RegRxHeaderCntValueLsb (Read Only)
+ */
+
+/*!
+ * RegRxPacketCntValueMsb (Read Only)
+ */
+
+/*!
+ * RegRxPacketCntValueLsb (Read Only)
+ */
+
+/*!
+ * RegModemStat (Read Only)
+ */
+#define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F
+#define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0
+
+/*!
+ * RegPktSnrValue (Read Only)
+ */
+
+/*!
+ * RegPktRssiValue (Read Only)
+ */
+
+/*!
+ * RegRssiValue (Read Only)
+ */
+
+/*!
+ * RegHopChannel (Read Only)
+ */
+#define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F
+#define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80
+#define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
+
+#define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK           0xBF
+#define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON             0x40
+#define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF            0x00 // Default
+
+#define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F
+
+/*!
+ * RegModemConfig1
+ */
+#define RFLR_MODEMCONFIG1_BW_MASK                   0x0F
+#define RFLR_MODEMCONFIG1_BW_7_81_KHZ               0x00
+#define RFLR_MODEMCONFIG1_BW_10_41_KHZ              0x10
+#define RFLR_MODEMCONFIG1_BW_15_62_KHZ              0x20
+#define RFLR_MODEMCONFIG1_BW_20_83_KHZ              0x30
+#define RFLR_MODEMCONFIG1_BW_31_25_KHZ              0x40
+#define RFLR_MODEMCONFIG1_BW_41_66_KHZ              0x50
+#define RFLR_MODEMCONFIG1_BW_62_50_KHZ              0x60
+#define RFLR_MODEMCONFIG1_BW_125_KHZ                0x70 // Default
+#define RFLR_MODEMCONFIG1_BW_250_KHZ                0x80
+#define RFLR_MODEMCONFIG1_BW_500_KHZ                0x90
+
+#define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xF1
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x02
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x04 // Default
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x06
+#define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x08
+
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFE
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x01
+#define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
+
+/*!
+ * RegModemConfig2
+ */
+#define RFLR_MODEMCONFIG2_SF_MASK                   0x0F
+#define RFLR_MODEMCONFIG2_SF_6                      0x60
+#define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
+#define RFLR_MODEMCONFIG2_SF_8                      0x80
+#define RFLR_MODEMCONFIG2_SF_9                      0x90
+#define RFLR_MODEMCONFIG2_SF_10                     0xA0
+#define RFLR_MODEMCONFIG2_SF_11                     0xB0
+#define RFLR_MODEMCONFIG2_SF_12                     0xC0
+
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08
+#define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00
+
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK         0xFB
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON           0x04
+#define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF          0x00 // Default
+
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC
+#define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
+
+/*!
+ * RegSymbTimeoutLsb
+ */
+#define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
+
+/*!
+ * RegPreambleLengthMsb
+ */
+#define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
+
+/*!
+ * RegPreambleLengthLsb
+ */
+#define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
+
+/*!
+ * RegPayloadLength
+ */
+#define RFLR_PAYLOADLENGTH                          0x0E // Default
+
+/*!
+ * RegPayloadMaxLength
+ */
+#define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
+
+/*!
+ * RegHopPeriod
+ */
+#define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
+
+/*!
+ * RegFifoRxByteAddr (Read Only)
+ */
+
+/*!
+ * RegModemConfig3
+ */
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK  0xF7
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON    0x08
+#define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
+
+#define RFLR_MODEMCONFIG3_AGCAUTO_MASK              0xFB
+#define RFLR_MODEMCONFIG3_AGCAUTO_ON                0x04 // Default
+#define RFLR_MODEMCONFIG3_AGCAUTO_OFF               0x00
+
+/*!
+ * RegFeiMsb (Read Only)
+ */
+
+/*!
+ * RegFeiMid (Read Only)
+ */
+
+/*!
+ * RegFeiLsb (Read Only)
+ */
+
+/*!
+ * RegRssiWideband (Read Only)
+ */
+
+/*!
+ * RegDetectOptimize
+ */
+#define RFLR_DETECTIONOPTIMIZE_MASK                 0xF8
+#define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12          0x03 // Default
+#define RFLR_DETECTIONOPTIMIZE_SF6                  0x05
+
+/*!
+ * RegInvertIQ
+ */
+#define RFLR_INVERTIQ_RX_MASK                       0xBF
+#define RFLR_INVERTIQ_RX_OFF                        0x00
+#define RFLR_INVERTIQ_RX_ON                         0x40
+#define RFLR_INVERTIQ_TX_MASK                       0xFE
+#define RFLR_INVERTIQ_TX_OFF                        0x01
+#define RFLR_INVERTIQ_TX_ON                         0x00
+
+/*!
+ * RegDetectionThreshold
+ */
+#define RFLR_DETECTIONTHRESH_SF7_TO_SF12            0x0A // Default
+#define RFLR_DETECTIONTHRESH_SF6                    0x0C
+
+/*!
+ * RegInvertIQ2
+ */
+#define RFLR_INVERTIQ2_ON                           0x19
+#define RFLR_INVERTIQ2_OFF                          0x1D
+
+/*!
+ * RegDioMapping1
+ */
+#define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
+#define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO0_01                    0x40
+#define RFLR_DIOMAPPING1_DIO0_10                    0x80
+#define RFLR_DIOMAPPING1_DIO0_11                    0xC0
+
+#define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
+#define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO1_01                    0x10
+#define RFLR_DIOMAPPING1_DIO1_10                    0x20
+#define RFLR_DIOMAPPING1_DIO1_11                    0x30
+
+#define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
+#define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO2_01                    0x04
+#define RFLR_DIOMAPPING1_DIO2_10                    0x08
+#define RFLR_DIOMAPPING1_DIO2_11                    0x0C
+
+#define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
+#define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
+#define RFLR_DIOMAPPING1_DIO3_01                    0x01
+#define RFLR_DIOMAPPING1_DIO3_10                    0x02
+#define RFLR_DIOMAPPING1_DIO3_11                    0x03
+
+/*!
+ * RegDioMapping2
+ */
+#define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
+#define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO4_01                    0x40
+#define RFLR_DIOMAPPING2_DIO4_10                    0x80
+#define RFLR_DIOMAPPING2_DIO4_11                    0xC0
+
+#define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
+#define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
+#define RFLR_DIOMAPPING2_DIO5_01                    0x10
+#define RFLR_DIOMAPPING2_DIO5_10                    0x20
+#define RFLR_DIOMAPPING2_DIO5_11                    0x30
+
+#define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
+#define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
+#define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
+
+/*!
+ * RegVersion (Read Only)
+ */
+
+/*!
+ * RegPllHop
+ */
+#define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
+#define RFLR_PLLHOP_FASTHOP_ON                      0x80
+#define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
+
+/*!
+ * RegTcxo
+ */
+#define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
+#define RFLR_TCXO_TCXOINPUT_ON                      0x10
+#define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
+
+/*!
+ * RegPaDac
+ */
+#define RFLR_PADAC_20DBM_MASK                       0xF8
+#define RFLR_PADAC_20DBM_ON                         0x07
+#define RFLR_PADAC_20DBM_OFF                        0x04  // Default
+
+/*!
+ * RegFormerTemp
+ */
+
+/*!
+ * RegBitrateFrac
+ */
+#define RF_BITRATEFRAC_MASK                         0xF0
+
+/*!
+ * RegAgcRef
+ */
+
+/*!
+ * RegAgcThresh1
+ */
+
+/*!
+ * RegAgcThresh2
+ */
+
+/*!
+ * RegAgcThresh3
+ */
+
+/*!
+ * RegPll
+ */
+#define RF_PLL_BANDWIDTH_MASK                       0x3F
+#define RF_PLL_BANDWIDTH_75                         0x00
+#define RF_PLL_BANDWIDTH_150                        0x40
+#define RF_PLL_BANDWIDTH_225                        0x80
+#define RF_PLL_BANDWIDTH_300                        0xC0  // Default
+
+#endif // __SX1276_REGS_LORA_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/SConscript

@@ -0,0 +1,41 @@
+from building import *
+
+src   = []
+cwd   = GetCurrentDir()
+include_path = [cwd]
+include_path += [cwd+'/lora-module/inc']
+
+# add lora radio driver.
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2F717N30'):
+    src += Split('''
+    lora-module/stm32_adapter/lora-spi-board.c
+    lora-module/stm32_adapter/SX1278_LSD4RF-2F717N30/sx1278-board.c
+    ''')
+
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R822N30'):
+    src += Split('''
+    lora-module/stm32_adapter/lora-spi-board.c
+    lora-module/stm32_adapter/SX1262_LSD4RF-2R822N30/sx1262-board.c
+    ''')
+
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R717N40'):
+    src += Split('''
+    lora-module/stm32_adapter/lora-spi-board.c
+    lora-module/stm32_adapter/SX1268_LSD4RF-2R717N40/sx1268-board.c
+    ''')
+
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_MODULE_RA_01'):
+    src += Split('''
+    lora-module/stm32_adapter/lora-spi-board.c
+    lora-module/stm32_adapter/SX1278_Ra-01/sx1278-board.c
+    ''')
+
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_MODULE_ASR6500S'):
+    src += Split('''
+    lora-module/stm32_adapter/lora-spi-board.c
+    lora-module/stm32_adapter/SX1262_ASR6500S/sx1278-board.c
+    ''')
+
+group = DefineGroup('lora-radio-driver/board', src, depend = ['PKG_USING_LORA_RADIO_DRIVER'], CPPPATH = include_path)
+
+Return('group')

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/inc/sx126x-board.h

@@ -0,0 +1,174 @@
+/*!
+ * \file      sx126x-board.h
+ *
+ * \brief     Target board SX126x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ */
+#ifndef __SX126x_BOARD_H__
+#define __SX126x_BOARD_H__
+
+#include "lora-radio-rtos-config.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include "sx126x/sx126x.h"
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40002 )
+    #define LORA_RADIO_NSS_PIN       stm32_pin_get(LORA_RADIO_NSS_PIN_NAME)
+    #define LORA_RADIO_BUSY_PIN      stm32_pin_get(LORA_RADIO_BUSY_PIN_NAME)
+    #define LORA_RADIO_DIO1_PIN      stm32_pin_get(LORA_RADIO_DIO1_PIN_NAME)
+    #define LORA_RADIO_RESET_PIN     stm32_pin_get(LORA_RADIO_RESET_PIN_NAME)
+    #if defined( LORA_RADIO_DIO2_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      stm32_pin_get(LORA_RADIO_DIO2_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_RFSW1_PIN_NAME ) && defined ( LORA_RADIO_RFSW2_PIN_NAME )  
+    #define LORA_RADIO_RFSW1_PIN     stm32_pin_get(LORA_RADIO_RFSW1_PIN_NAME)
+    #define LORA_RADIO_RFSW2_PIN     stm32_pin_get(LORA_RADIO_RFSW2_PIN_NAME)
+    #endif
+#else
+    #define LORA_RADIO_NSS_PIN       rt_pin_get(LORA_RADIO_NSS_PIN_NAME)
+    #define LORA_RADIO_BUSY_PIN      rt_pin_get(LORA_RADIO_BUSY_PIN_NAME)
+    #define LORA_RADIO_DIO1_PIN      rt_pin_get(LORA_RADIO_DIO1_PIN_NAME)
+    #define LORA_RADIO_RESET_PIN     rt_pin_get(LORA_RADIO_RESET_PIN_NAME)
+    #if defined( LORA_RADIO_DIO2_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      rt_pin_get(LORA_RADIO_DIO2_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_RFSW1_PIN_NAME ) && defined ( LORA_RADIO_RFSW2_PIN_NAME )  
+    #define LORA_RADIO_RFSW1_PIN     rt_pin_get(LORA_RADIO_RFSW1_PIN_NAME)
+    #define LORA_RADIO_RFSW2_PIN     rt_pin_get(LORA_RADIO_RFSW2_PIN_NAME)
+    #endif
+#endif/* ( RT_VER_NUM <= 0x40002) */
+
+#else
+    /* if not use env\menuconfig,define Radio GPIO directly.*/
+    #ifndef LORA_RADIO_NSS_PIN
+    #define LORA_RADIO_NSS_PIN    GET_PIN(A,15)
+    #endif
+    #ifndef LORA_RADIO_RESET_PIN
+    #define LORA_RADIO_RESET_PIN  GET_PIN(A,7)
+    #endif
+    #ifndef LORA_RADIO_DIO1_PIN
+    #define LORA_RADIO_DIO1_PIN   GET_PIN(B,1)
+    #endif
+    #ifndef LORA_RADIO_BUSY_PIN
+    #define LORA_RADIO_BUSY_PIN   GET_PIN(B,2)
+    #endif
+    #ifndef LORA_RADIO_RFSW1_PIN
+    #define LORA_RADIO_RFSW1_PIN   GET_PIN(B,0)
+    #endif
+    #ifndef LORA_RADIO_RFSW2_PIN
+    #define LORA_RADIO_RFSW2_PIN   GET_PIN(C,5)
+    #endif
+#endif // end of LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+
+/*!
+ * Defines the time required for the TCXO to wakeup [ms].
+ */
+#define BOARD_TCXO_WAKEUP_TIME                          2
+
+#define SX126X_DELAY_MS( ms )                           rt_thread_mdelay(ms) 
+#define SX126X_BLOCK_DELAY_1MS()                        rt_hw_us_delay(999)
+
+/*!
+ * \brief Initializes the radio I/Os pins interface
+ */
+void SX126xIoInit( void );
+
+/*!
+ * \brief Initializes DIO IRQ handlers
+ *
+ * \param [IN] irqHandlers Array containing the IRQ callback functions
+ */
+void SX126xIoIrqInit( DioIrqHandler dioIrq );
+
+/*!
+ * \brief De-initializes the radio I/Os pins interface.
+ *
+ * \remark Useful when going in MCU low power modes
+ */
+void SX126xIoDeInit( void );
+
+/*!
+ * \brief Initializes the TCXO power pin.
+ */
+void SX126xIoTcxoInit( void );
+
+/*!
+ * \brief Initializes the radio debug pins.
+ */
+void SX126xIoDbgInit( void );
+
+/*!
+ * \brief HW Reset of the radio
+ */
+void SX126xReset( void );
+
+/*!
+ * \brief Blocking loop to wait while the Busy pin in high
+ */
+void SX126xWaitOnBusy( void );
+
+/*!
+ * \brief Initializes the RF Switch I/Os pins interface
+ */
+void SX126xAntSwOn( void );
+
+/*!
+ * \brief De-initializes the RF Switch I/Os pins interface
+ *
+ * \remark Needed to decrease the power consumption in MCU low power modes
+ */
+void SX126xAntSwOff( void );
+
+/*!
+ * \brief Set the RF Switch I/Os pins interface
+ */
+void SX126xSetAntSw( RadioOperatingModes_t mode );
+
+/*!
+ * \brief Checks if the given RF frequency is supported by the hardware
+ *
+ * \param [IN] frequency RF frequency to be checked
+ * \retval isSupported [true: supported, false: unsupported]
+ */
+bool SX126xCheckRfFrequency( uint32_t frequency );
+
+/*!
+ * \brief Gets the Defines the time required for the TCXO to wakeup [ms].
+ *
+ * \retval time Board TCXO wakeup time in ms.
+ */
+uint32_t SX126xGetBoardTcxoWakeupTime( void );
+
+/*!
+ * \brief Writes new Tx debug pin state
+ *
+ * \param [IN] state Debug pin state
+ */
+void SX126xDbgPinTxWrite( uint8_t state );
+
+/*!
+ * \brief Writes new Rx debug pin state
+ *
+ * \param [IN] state Debug pin state
+ */
+void SX126xDbgPinRxWrite( uint8_t state );
+
+
+#endif // __SX126x_BOARD_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/inc/sx127x-board.h

@@ -0,0 +1,211 @@
+/*!
+ * \file      sx127x-board.h
+ *
+ * \brief     Target board SX127x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#ifndef __SX127x_BOARD_H__
+#define __SX127x_BOARD_H__
+
+#include "lora-radio-rtos-config.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include "SX127x/SX127x.h"
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40002 )
+    #define LORA_RADIO_NSS_PIN       stm32_pin_get(LORA_RADIO_NSS_PIN_NAME)
+    #define LORA_RADIO_RESET_PIN     stm32_pin_get(LORA_RADIO_RESET_PIN_NAME)
+    #define LORA_RADIO_DIO0_PIN      stm32_pin_get(LORA_RADIO_DIO0_PIN_NAME)
+    #if defined( LORA_RADIO_DIO1_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      stm32_pin_get(LORA_RADIO_DIO1_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO2_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      stm32_pin_get(LORA_RADIO_DIO2_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO3_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      stm32_pin_get(LORA_RADIO_DIO3_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO4_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      stm32_pin_get(LORA_RADIO_DIO4_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO5_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      stm32_pin_get(LORA_RADIO_DIO5_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_RFSW1_PIN_NAME ) && defined ( LORA_RADIO_RFSW2_PIN_NAME )  
+    #define LORA_RADIO_RFSW1_PIN     stm32_pin_get(LORA_RADIO_RFSW1_PIN_NAME)
+    #define LORA_RADIO_RFSW2_PIN     stm32_pin_get(LORA_RADIO_RFSW2_PIN_NAME)
+    #endif
+#else
+    #define LORA_RADIO_NSS_PIN       rt_pin_get(LORA_RADIO_NSS_PIN_NAME)
+    #define LORA_RADIO_RESET_PIN     rt_pin_get(LORA_RADIO_RESET_PIN_NAME)
+    #define LORA_RADIO_DIO0_PIN      rt_pin_get(LORA_RADIO_DIO0_PIN_NAME)
+    #if defined( LORA_RADIO_DIO1_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      rt_pin_get(LORA_RADIO_DIO1_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO2_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      rt_pin_get(LORA_RADIO_DIO2_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO3_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      rt_pin_get(LORA_RADIO_DIO3_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO4_PIN_NAME ) 
+    #define LORA_RADIO_DIO2_PIN      rt_pin_get(LORA_RADIO_DIO4_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_DIO5_PIN_NAME ) 
+    #define LORA_RADIO_DIO1_PIN      rt_pin_get(LORA_RADIO_DIO5_PIN_NAME)
+    #endif
+    #if defined( LORA_RADIO_RFSW1_PIN_NAME ) && defined ( LORA_RADIO_RFSW2_PIN_NAME )  
+    #define LORA_RADIO_RFSW1_PIN     rt_pin_get(LORA_RADIO_RFSW1_PIN_NAME)
+    #define LORA_RADIO_RFSW2_PIN     rt_pin_get(LORA_RADIO_RFSW2_PIN_NAME)
+    #endif
+#endif /* ( RT_VER_NUM <= 0x40002) */
+
+#else
+    /* if not use env\menuconfig,define Radio GPIO directly.*/
+    #ifndef LORA_RADIO_NSS_PIN
+    #define LORA_RADIO_NSS_PIN    GET_PIN(A,15)
+    #endif
+    #ifndef LORA_RADIO_RESET_PIN
+    #define LORA_RADIO_RESET_PIN  GET_PIN(A,7)
+    #endif
+    #ifndef LORA_RADIO_DIO0_PIN
+    #define LORA_RADIO_DIO0_PIN   GET_PIN(B,1)
+    #endif
+
+
+#endif // end of LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+
+/*!
+ * \brief delayms for radio access
+ */
+#define SX127X_DELAY_MS(ms)              rt_thread_mdelay(ms) 
+
+/*!
+ * \brief Initializes the radio I/Os pins interface
+ */
+void SX127xIoInit( void );
+
+/*!
+ * \brief De-initializes the radio I/Os pins interface.
+ *
+ * \remark Useful when going in MCU low power modes
+ */
+void SX127xIoDeInit( void );
+
+/*!
+ * \brief Initializes the TCXO power pin.
+ */
+void SX127xIoTcxoInit( void );
+
+/*!
+ * \brief Initializes the radio debug pins.
+ */
+void SX127xIoDbgInit( void );
+
+/*!
+ * \brief Resets the radio
+ */
+void SX127xReset( void );
+
+/*!
+ * \brief Gets the board PA selection configuration
+ *
+ * \param [IN] power Selects the right PA according to the wanted power.
+ * \retval PaSelect RegPaConfig PaSelect value
+ */
+uint8_t SX127xGetPaSelect( int8_t power );
+
+/*!
+ * \brief Set the RF Switch I/Os pins in low power mode
+ *
+ * \param [IN] status enable or disable
+ */
+void SX127xSetAntSwLowPower( bool status );
+
+/*!
+ * \brief Initializes the RF Switch I/Os pins interface
+ */
+void SX127xAntSwInit( void );
+
+/*!
+ * \brief De-initializes the RF Switch I/Os pins interface
+ *
+ * \remark Needed to decrease the power consumption in MCU low power modes
+ */
+void SX127xAntSwDeInit( void );
+
+/*!
+ * \brief Controls the antenna switch if necessary.
+ *
+ * \remark see errata note
+ *
+ * \param [IN] opMode Current radio operating mode
+ */
+void SX127xSetAntSw( uint8_t opMode );
+
+/*!
+ * \brief Checks if the given RF frequency is supported by the hardware
+ *
+ * \param [IN] frequency RF frequency to be checked
+ * \retval isSupported [true: supported, false: unsupported]
+ */
+bool SX127xCheckRfFrequency( uint32_t frequency );
+
+/*!
+ * \brief Enables/disables the TCXO if available on board design.
+ *
+ * \param [IN] state TCXO enabled when true and disabled when false.
+ */
+void SX127xSetBoardTcxo( uint8_t state );
+
+/*!
+ * \brief Gets the Defines the time required for the TCXO to wakeup [ms].
+ *
+ * \retval time Board TCXO wakeup time in ms.
+ */
+uint32_t SX127xGetBoardTcxoWakeupTime( void );
+
+/*!
+ * \brief Writes new Tx debug pin state
+ *
+ * \param [IN] state Debug pin state
+ */
+void SX127xDbgPinTxWrite( uint8_t state );
+
+/*!
+ * \brief Writes new Rx debug pin state
+ *
+ * \param [IN] state Debug pin state
+ */
+void SX127xDbgPinRxWrite( uint8_t state );
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+// todo PR to drv_gpio.c
+int stm32_pin_get(char *pin_name);
+#endif
+
+/*!
+ * Radio hardware and global parameters
+ */
+extern SX127x_t SX127x;
+
+#endif // __SX127x_BOARD_H__

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/SX1262_ASR6500S/sx126x-board.c

@@ -0,0 +1,79 @@
+/*
+ * author    Rick Zhang
+ * date      2020.07.20
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "sx126x-board.h"
+
+#define DRV_DEBUG
+#define LOG_TAG             "LoRa.Board.ASR6500S(SX1262)" // ASR6500S
+#include <drv_log.h>
+
+extern void RadioOnDioIrq( void* context );
+
+void SX126xIoInit( void )
+{
+    rt_pin_mode(LORA_RADIO_NSS_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_BUSY_PIN, PIN_MODE_INPUT);
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT);
+}
+
+void SX126xIoIrqInit( DioIrqHandler dioIrq )
+{
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT);
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING, RadioOnDioIrq,(void*)"callback args");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);
+}
+
+void SX126xIoDeInit( void )
+{
+}
+
+void SX126xIoDbgInit( void )
+{
+}
+
+void SX126xIoTcxoInit( void )
+{
+    CalibrationParams_t calibParam;
+    SX126xSetDio3AsTcxoCtrl( TCXO_CTRL_1_8V, SX126xGetBoardTcxoWakeupTime( ) << 6 ); // convert from ms to SX126x time base
+    calibParam.Value = 0x7F;
+    SX126xCalibrate( calibParam );
+}
+
+uint32_t SX126xGetBoardTcxoWakeupTime( void )
+{
+    return BOARD_TCXO_WAKEUP_TIME;
+}
+
+void SX126xReset( void )
+{
+    SX126X_DELAY_MS( 20 );
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(LORA_RADIO_RESET_PIN, PIN_LOW);
+    SX126X_DELAY_MS( 40 );
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_INPUT);
+    SX126X_DELAY_MS( 20 );
+}
+
+void SX126xWaitOnBusy( void )
+{
+    while( rt_pin_read( LORA_RADIO_BUSY_PIN ) == PIN_HIGH );
+}
+
+void SX126xAntSwOn( void )
+{
+}
+
+void SX126xAntSwOff( void )
+{
+}
+
+bool SX126xCheckRfFrequency( uint32_t frequency )
+{
+    return true;
+}
+void SX126xSetAntSw( RadioOperatingModes_t mode )
+{
+}

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/SX1262_LSD4RF-2R822N30/sx1262-board.c

@@ -0,0 +1,173 @@
+/*!
+ * \file      sx1262-board.c
+ *
+ * \brief     Target board SX126x shield driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "sx126x-board.h"
+
+#define LOG_TAG "LoRa.Board.LSD4RF-2R822N30(SX1262)"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+/*!
+ * Debug GPIO pins objects
+ */
+#if defined( USE_RADIO_DEBUG )
+Gpio_t DbgPinTx;
+Gpio_t DbgPinRx;
+#endif
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40004 )
+int stm32_pin_get(char *pin_name)
+{
+    /* eg: pin_name : "PA.4"  ( GPIOA, GPIO_PIN_4 )--> drv_gpio.c pin */
+    char pin_index = strtol(&pin_name[3],0,10);
+    
+    if(pin_name[1] < 'A' || pin_name[1] > 'Z')
+    {
+        return -1;
+    }
+
+    return (16 * (pin_name[1]-'A') + pin_index);
+}
+#endif 
+#endif /* LORA_RADIO_GPIO_SETUP_BY_PIN_NAME */
+
+void SX126xIoInit( void )
+{
+    rt_pin_mode(LORA_RADIO_NSS_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_BUSY_PIN, PIN_MODE_INPUT);
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+#if defined( LORA_RADIO_DIO2_PIN ) 
+    rt_pin_mode(LORA_RADIO_DIO2_PIN, PIN_MODE_INPUT_PULLDOWN);
+#endif
+#if defined( LORA_RADIO_RFSW1_PIN ) && defined ( LORA_RADIO_RFSW2_PIN )   
+    rt_pin_mode(LORA_RADIO_RFSW1_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_RFSW2_PIN, PIN_MODE_OUTPUT);
+#endif
+
+}
+
+void SX126xIoIrqInit( DioIrqHandler dioIrq )
+{ 
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING, dioIrq,(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);  
+}
+
+void SX126xIoDeInit( void )
+{
+}
+
+void SX126xIoDbgInit( void )
+{
+#if defined( USE_RADIO_DEBUG )
+    GpioInit( &DbgPinTx, RADIO_DBG_PIN_TX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+    GpioInit( &DbgPinRx, RADIO_DBG_PIN_RX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+#endif
+}
+
+void SX126xIoTcxoInit( void )
+{
+    // Initialize TCXO control
+    CalibrationParams_t calibParam;
+    
+    // +clear OSC_START_ERR for reboot or cold-start from sleep
+    SX126xClearDeviceErrors();
+    
+    // TCXO_CTRL_2_7V 64*15.0625US
+    SX126xSetDio3AsTcxoCtrl( TCXO_CTRL_2_7V, 320);//SX126xGetBoardTcxoWakeupTime( ) << 6 ); // convert from ms to SX126x time base
+    
+    calibParam.Value = 0x7F;
+    SX126xCalibrate( calibParam );
+}
+
+uint32_t SX126xGetBoardTcxoWakeupTime( void )
+{
+    return BOARD_TCXO_WAKEUP_TIME;
+}
+
+void SX126xReset( void )
+{   
+    SX126X_DELAY_MS( 10 );
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_OUTPUT); 
+    rt_pin_write(LORA_RADIO_RESET_PIN, PIN_LOW);
+    SX126X_DELAY_MS( 20 );
+     // internal pull-up
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_INPUT); 
+    SX126X_DELAY_MS( 10 ); 
+}
+
+void SX126xWaitOnBusy( void )
+{
+    while( rt_pin_read( LORA_RADIO_BUSY_PIN ) == PIN_HIGH );
+}
+
+void SX126xAntSwOn( void )
+{
+   // No need
+}
+
+void SX126xAntSwOff( void )
+{
+    ////GpioInit( &AntPow, RADIO_ANT_SWITCH_POWER, PIN_ANALOGIC, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+    
+#if defined( LORA_RADIO_RFSW1_PIN ) && defined ( LORA_RADIO_RFSW2_PIN )   
+    rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+    rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+#endif
+}
+
+void SX126xSetAntSw( RadioOperatingModes_t mode )
+{
+    if( mode == MODE_TX )
+    { // Transmit
+        rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_HIGH);
+        rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+    }
+    else 
+    {
+        rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+        rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_HIGH);
+    }
+}
+
+bool SX126xCheckRfFrequency( uint32_t frequency )
+{
+    // Implement check. Currently all frequencies are supported
+    return true;
+}
+
+#if defined( USE_RADIO_DEBUG )
+void SX126xDbgPinTxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinTx, state );
+}
+
+void SX126xDbgPinRxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinRx, state );
+}
+#endif

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/SX1268_LSD4RF-2R717N40/sx1268-board.c

@@ -0,0 +1,176 @@
+/*!
+ * \file      sx1268-board.c
+ *
+ * \brief     Target board SX126x shield driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "sx126x-board.h"
+
+#define LOG_TAG "LoRa.Board.LSD4RF-2R717N40(SX1268)" // LSD4RF-2R717N40
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+/*!
+ * Debug GPIO pins objects
+ */
+#if defined( USE_RADIO_DEBUG )
+Gpio_t DbgPinTx;
+Gpio_t DbgPinRx;
+#endif
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40004 )
+int stm32_pin_get(char *pin_name)
+{
+    /* eg: pin_name : "PA.4"  ( GPIOA, GPIO_PIN_4 )--> drv_gpio.c pin */
+    char pin_index = strtol(&pin_name[3],0,10);
+    
+    if(pin_name[1] < 'A' || pin_name[1] > 'Z')
+    {
+        return -1;
+    }
+
+    return (16 * (pin_name[1]-'A') + pin_index);
+}
+#endif 
+#endif /* LORA_RADIO_GPIO_SETUP_BY_PIN_NAME */
+
+void SX126xIoInit( void )
+{
+    rt_pin_mode(LORA_RADIO_NSS_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_BUSY_PIN, PIN_MODE_INPUT);
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+#if defined( LORA_RADIO_DIO2_PIN ) 
+    rt_pin_mode(LORA_RADIO_DIO2_PIN, PIN_MODE_INPUT_PULLDOWN);
+#endif
+#if defined( LORA_RADIO_RFSW1_PIN ) && defined ( LORA_RADIO_RFSW2_PIN )   
+    rt_pin_mode(LORA_RADIO_RFSW1_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_RFSW2_PIN, PIN_MODE_OUTPUT);
+#endif
+
+}
+
+void SX126xIoIrqInit( DioIrqHandler dioIrq )
+{ 
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING, dioIrq,(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);  
+}
+
+void SX126xIoDeInit( void )
+{
+////    GpioInit( &SX126x.Spi.Nss, RADIO_NSS, PIN_ANALOGIC, PIN_PUSH_PULL, PIN_PULL_UP, 1 );
+////    GpioInit( &SX126x.BUSY, RADIO_BUSY, PIN_ANALOGIC, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+////    GpioInit( &SX126x.DIO1, RADIO_DIO_1, PIN_ANALOGIC, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+}
+
+void SX126xIoDbgInit( void )
+{
+#if defined( USE_RADIO_DEBUG )
+    GpioInit( &DbgPinTx, RADIO_DBG_PIN_TX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+    GpioInit( &DbgPinRx, RADIO_DBG_PIN_RX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+#endif
+}
+
+void SX126xIoTcxoInit( void )
+{
+    // Initialize TCXO control
+    CalibrationParams_t calibParam;
+    
+    // +clear OSC_START_ERR for reboot or cold-start from sleep
+    SX126xClearDeviceErrors();
+    
+    // TCXO_CTRL_1_7V -> TCXO_CTRL_2_7V 64*15.0625US
+    SX126xSetDio3AsTcxoCtrl( TCXO_CTRL_2_7V, 320);//SX126xGetBoardTcxoWakeupTime( ) << 6 ); // convert from ms to SX126x time base
+    
+    calibParam.Value = 0x7F;
+    SX126xCalibrate( calibParam );
+}
+
+uint32_t SX126xGetBoardTcxoWakeupTime( void )
+{
+    return BOARD_TCXO_WAKEUP_TIME;
+}
+
+void SX126xReset( void )
+{   
+    SX126X_DELAY_MS( 10 );
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_OUTPUT); 
+    rt_pin_write(LORA_RADIO_RESET_PIN, PIN_LOW);
+    SX126X_DELAY_MS( 20 );
+     // internal pull-up
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_INPUT); 
+    SX126X_DELAY_MS( 10 ); 
+}
+
+void SX126xWaitOnBusy( void )
+{
+    while( rt_pin_read( LORA_RADIO_BUSY_PIN ) == PIN_HIGH );
+}
+
+void SX126xAntSwOn( void )
+{
+   // No need
+}
+
+void SX126xAntSwOff( void )
+{
+    ////GpioInit( &AntPow, RADIO_ANT_SWITCH_POWER, PIN_ANALOGIC, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+    
+#if defined( LORA_RADIO_RFSW1_PIN ) && defined ( LORA_RADIO_RFSW2_PIN )   
+    rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+    rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+#endif
+}
+
+void SX126xSetAntSw( RadioOperatingModes_t mode )
+{
+    if( mode == MODE_TX )
+    { // Transmit
+        rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_HIGH);
+        rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+    }
+    else 
+    {
+        rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+        rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_HIGH);
+    }
+}
+
+bool SX126xCheckRfFrequency( uint32_t frequency )
+{
+    // Implement check. Currently all frequencies are supported
+    return true;
+}
+
+#if defined( USE_RADIO_DEBUG )
+void SX126xDbgPinTxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinTx, state );
+}
+
+void SX126xDbgPinRxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinRx, state );
+}
+#endif

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/SX1278_LSD4RF-2F717N30/sx1278-board.c

@@ -0,0 +1,291 @@
+/*!
+ * \file      sx1278-board.c
+ *
+ * \brief     Target board SX127x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "sx127x\sx127x.h"
+#include "sx127x-board.h"
+
+#define LOG_TAG "LoRa.Board.LSD4RF-2F717N30(SX1278)"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+/*!
+ * Flag used to set the RF switch control pins in low power mode when the radio is not active.
+ */
+static bool RadioIsActive = false;
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX127xOnDio0IrqEvent( void *args );
+
+/*!
+ * \brief DIO 1 IRQ callback
+ */
+void SX127xOnDio1IrqEvent( void *args );
+
+/*!
+ * \brief DIO 2 IRQ callback
+ */
+void SX127xOnDio2IrqEvent( void *args );
+
+/*!
+ * \brief DIO 3 IRQ callback
+ */
+void SX127xOnDio3IrqEvent( void *args );
+
+/*!
+ * \brief DIO 4 IRQ callback
+ */
+void SX127xOnDio4IrqEvent( void *args );
+
+/*!
+ * \brief DIO 5 IRQ callback
+ */
+void SX127xOnDio5IrqEvent( void *args );
+#endif
+
+/*!
+ * Debug GPIO pins objects
+ */
+#if defined( USE_RADIO_DEBUG )
+Gpio_t DbgPinTx;
+Gpio_t DbgPinRx;
+#endif
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40004 )
+int stm32_pin_get(char *pin_name)
+{
+    /* eg: pin_name : "PA.4"  ( GPIOA, GPIO_PIN_4 )--> drv_gpio.c pin */
+    char pin_index = strtol(&pin_name[3],0,10);
+    
+    if(pin_name[1] < 'A' || pin_name[1] > 'Z')
+    {
+        return -1;
+    }
+
+    return (16 * (pin_name[1]-'A') + pin_index);
+}
+#endif 
+#endif /* LORA_RADIO_GPIO_SETUP_BY_PIN_NAME */
+
+void SX127xIoInit( void )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    rt_pin_mode(LORA_RADIO_NSS_PIN, PIN_MODE_OUTPUT);
+    
+    rt_pin_mode(LORA_RADIO_DIO0_PIN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+    rt_pin_mode(LORA_RADIO_DIO2_PIN, PIN_MODE_INPUT_PULLDOWN);
+#else
+//    GpioInit( &SX127x.Spi.Nss, RADIO_NSS, PIN_OUTPUT, PIN_PUSH_PULL, PIN_PULL_UP, 1 );
+
+//    GpioInit( &SX127x.DIO0, RADIO_DIO_0, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+//    GpioInit( &SX127x.DIO1, RADIO_DIO_1, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+//    GpioInit( &SX127x.DIO2, RADIO_DIO_2, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+//    GpioInit( &SX127x.DIO3, RADIO_DIO_3, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+//    GpioInit( &SX127x.DIO4, RADIO_DIO_4, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+//    GpioInit( &SX127x.DIO5, RADIO_DIO_5, PIN_INPUT, PIN_PUSH_PULL, PIN_PULL_UP, 0 );
+
+#endif
+}
+
+void SX127xIoIrqInit( DioIrqHandler **irqHandlers )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    
+#ifdef LORA_RADIO_DIO0_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO0_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio0IrqEvent,(void*)"rf-dio0");
+    rt_pin_irq_enable(LORA_RADIO_DIO0_PIN, PIN_IRQ_ENABLE);    
+#endif
+
+#ifdef LORA_RADIO_DIO1_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio1IrqEvent,(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);    
+#endif
+    
+#ifdef LORA_RADIO_DIO2_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO2_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio2IrqEvent,(void*)"rf-dio2");
+    rt_pin_irq_enable(LORA_RADIO_DIO2_PIN, PIN_IRQ_ENABLE);    
+#endif
+    
+#else
+    
+#ifdef LORA_RADIO_DIO0_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO0_PIN, PIN_IRQ_MODE_RISING,irqHandlers[0],(void*)"rf-dio0");
+    rt_pin_irq_enable(LORA_RADIO_DIO0_PIN, PIN_IRQ_ENABLE);    
+#endif
+    
+#ifdef LORA_RADIO_DIO1_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING,irqHandlers[1],(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);    
+#endif
+
+#ifdef LORA_RADIO_DIO2_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO2_PIN, PIN_IRQ_MODE_RISING,irqHandlers[2],(void*)"rf-dio2");
+    rt_pin_irq_enable(LORA_RADIO_DIO2_PIN, PIN_IRQ_ENABLE);    
+#endif 
+//    GpioSetInterrupt( &SX127x.DIO0, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[0] );
+//    GpioSetInterrupt( &SX127x.DIO1, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[1] );
+//    GpioSetInterrupt( &SX127x.DIO2, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[2] );
+//    GpioSetInterrupt( &SX127x.DIO3, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[3] );
+//    GpioSetInterrupt( &SX127x.DIO4, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[4] );
+//    GpioSetInterrupt( &SX127x.DIO5, IRQ_RISING_EDGE, IRQ_HIGH_PRIORITY, irqHandlers[5] );  
+#endif /*end of USING_LORA_RADIO_DRIVER_RTOS_SUPPORT */     
+}
+
+void SX127xIoDeInit( void )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+//    rt_pin_mode(LORA_RADIO_DIO0_PIN, PIN_MODE_INPUT);
+//    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT);
+//    rt_pin_mode(LORA_RADIO_DIO2_PIN, PIN_MODE_INPUT);
+#else
+//    GpioInit( &SX127x.Spi.Nss, RADIO_NSS, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 1 );
+
+//    GpioInit( &SX127x.DIO0, RADIO_DIO_0, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+//    GpioInit( &SX127x.DIO1, RADIO_DIO_1, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+//    GpioInit( &SX127x.DIO2, RADIO_DIO_2, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+//    GpioInit( &SX127x.DIO3, RADIO_DIO_3, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+//    GpioInit( &SX127x.DIO4, RADIO_DIO_4, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+//    GpioInit( &SX127x.DIO5, RADIO_DIO_5, PIN_INPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+#endif /*end of USING_LORA_RADIO_DRIVER_RTOS_SUPPORT */
+}
+
+void SX127xIoDbgInit( void )
+{
+#if defined( USE_RADIO_DEBUG )
+    GpioInit( &DbgPinTx, RADIO_DBG_PIN_TX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+    GpioInit( &DbgPinRx, RADIO_DBG_PIN_RX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+#endif
+}
+
+void SX127xReset( void )
+{
+    // Set RESET pin to 0
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(LORA_RADIO_RESET_PIN, PIN_LOW);
+    
+    // Wait 1 ms
+    SX127X_DELAY_MS( 1 );
+
+    // Configure RESET as input
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_INPUT);
+
+    // Wait 6 ms
+    SX127X_DELAY_MS( 6 );
+}
+
+void SX127xSetAntSwLowPower( bool status )
+{
+    if( RadioIsActive != status )
+    {
+        RadioIsActive = status;
+
+        if( status == false )
+        {
+            SX127xAntSwInit( );
+        }
+        else
+        {
+            SX127xAntSwDeInit( );
+        }
+    }
+}
+
+void SX127xAntSwInit( void )
+{
+////    GpioInit( &AntSwitchRx, RADIO_ANT_SWITCH_RX, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+////    GpioInit( &AntSwitchTxBoost, RADIO_ANT_SWITCH_TX_BOOST, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+////    GpioInit( &AntSwitchTxRfo, RADIO_ANT_SWITCH_TX_RFO, PIN_OUTPUT, PIN_PUSH_PULL, PIN_NO_PULL, 0 );
+
+    rt_pin_mode(LORA_RADIO_RFSW1_PIN, PIN_MODE_OUTPUT);
+    rt_pin_mode(LORA_RADIO_RFSW2_PIN, PIN_MODE_OUTPUT);
+    
+    rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+    rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+}
+
+void SX127xAntSwDeInit( void )
+{
+////    GpioInit( &AntSwitchRx, RADIO_ANT_SWITCH_RX, PIN_ANALOGIC, PIN_OPEN_DRAIN, PIN_NO_PULL, 0 );
+////    GpioInit( &AntSwitchTxBoost, RADIO_ANT_SWITCH_TX_BOOST, PIN_ANALOGIC, PIN_OPEN_DRAIN, PIN_NO_PULL, 0 );
+////    GpioInit( &AntSwitchTxRfo, RADIO_ANT_SWITCH_TX_RFO, PIN_ANALOGIC, PIN_OPEN_DRAIN, PIN_NO_PULL, 0 );
+
+    rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+    rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+}
+
+/* TX/RX ANT Swich */
+void SX127xSetAntSw( uint8_t opMode )
+{
+    uint8_t paConfig =  SX127xRead( REG_PACONFIG );
+    switch( opMode )
+    {
+    case RFLR_OPMODE_TRANSMITTER:
+        if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
+        {
+            ///GpioWrite( &AntSwitchTxBoost, 1 );
+            rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_HIGH);
+            rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_LOW);
+        }
+        break;
+    case RFLR_OPMODE_RECEIVER:
+    case RFLR_OPMODE_RECEIVER_SINGLE:
+    case RFLR_OPMODE_CAD:
+    default:
+        ////GpioWrite( &AntSwitchRx, 1 );
+        rt_pin_write(LORA_RADIO_RFSW1_PIN, PIN_LOW);
+        rt_pin_write(LORA_RADIO_RFSW2_PIN, PIN_HIGH);
+        break;
+    }
+}
+
+#if defined( USE_RADIO_DEBUG )
+void SX127xDbgPinTxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinTx, state );
+}
+
+void SX127xDbgPinRxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinRx, state );
+}
+#endif
+
+uint8_t SX127xGetPaSelect( int8_t power )
+{
+    return RF_PACONFIG_PASELECT_PABOOST;
+}
+
+bool SX127xCheckRfFrequency( uint32_t frequency )
+{
+    // Implement check. Currently all frequencies are supported,todo depend on board
+    return true; 
+}
+
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/SX1278_Ra-01/sx1278-board.c

@@ -0,0 +1,225 @@
+/*!
+ * \file      sx1278-board.c
+ *
+ * \brief     Target board SX127x driver implementation
+ *
+ * \copyright Revised BSD License, see section \ref LICENSE.
+ *
+ * \code
+ *                ______                              _
+ *               / _____)             _              | |
+ *              ( (____  _____ ____ _| |_ _____  ____| |__
+ *               \____ \| ___ |    (_   _) ___ |/ ___)  _ \
+ *               _____) ) ____| | | || |_| ____( (___| | | |
+ *              (______/|_____)_|_|_| \__)_____)\____)_| |_|
+ *              (C)2013-2017 Semtech
+ *
+ * \endcode
+ *
+ * \author    Miguel Luis ( Semtech )
+ *
+ * \author    Gregory Cristian ( Semtech )
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "sx127x\sx127x.h"
+#include "sx127x-board.h"
+
+#define LOG_TAG "LoRa.Board.Ra-01(SX1278)"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+/*!
+ * Flag used to set the RF switch control pins in low power mode when the radio is not active.
+ */
+static bool RadioIsActive = false;
+
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+/*!
+ * \brief DIO 0 IRQ callback
+ */
+void SX127xOnDio0IrqEvent( void *args );
+
+/*!
+ * \brief DIO 1 IRQ callback
+ */
+void SX127xOnDio1IrqEvent( void *args );
+
+/*!
+ * \brief DIO 2 IRQ callback
+ */
+void SX127xOnDio2IrqEvent( void *args );
+
+/*!
+ * \brief DIO 3 IRQ callback
+ */
+void SX127xOnDio3IrqEvent( void *args );
+
+/*!
+ * \brief DIO 4 IRQ callback
+ */
+void SX127xOnDio4IrqEvent( void *args );
+
+/*!
+ * \brief DIO 5 IRQ callback
+ */
+void SX127xOnDio5IrqEvent( void *args );
+#endif
+
+/*!
+ * Debug GPIO pins objects
+ */
+#if defined( USE_RADIO_DEBUG )
+Gpio_t DbgPinTx;
+Gpio_t DbgPinRx;
+#endif
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40004 )
+int stm32_pin_get(char *pin_name)
+{
+    /* eg: pin_name : "PA.4"  ( GPIOA, GPIO_PIN_4 )--> drv_gpio.c pin */
+    char pin_index = strtol(&pin_name[3],0,10);
+    
+    if(pin_name[1] < 'A' || pin_name[1] > 'Z')
+    {
+        return -1;
+    }
+
+    return (16 * (pin_name[1]-'A') + pin_index);
+}
+#endif 
+#endif /* LORA_RADIO_GPIO_SETUP_BY_PIN_NAME */
+
+void SX127xIoInit( void )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    // RT-Thread
+    rt_pin_mode(LORA_RADIO_NSS_PIN, PIN_MODE_OUTPUT);
+    
+    rt_pin_mode(LORA_RADIO_DIO0_PIN, PIN_MODE_INPUT_PULLDOWN);
+#ifdef LORA_RADIO_DIO1_PIN     
+    rt_pin_mode(LORA_RADIO_DIO1_PIN, PIN_MODE_INPUT_PULLDOWN);
+#endif    
+#ifdef LORA_RADIO_DIO2_PIN      
+    rt_pin_mode(LORA_RADIO_DIO2_PIN, PIN_MODE_INPUT_PULLDOWN);
+#endif    
+#else
+
+#endif
+}
+
+void SX127xIoIrqInit( DioIrqHandler **irqHandlers )
+{
+#ifdef LORA_RADIO_DRIVER_USING_ON_RTOS_RT_THREAD
+    #ifdef LORA_RADIO_DIO0_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO0_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio0IrqEvent,(void*)"rf-dio0");
+    rt_pin_irq_enable(LORA_RADIO_DIO0_PIN, PIN_IRQ_ENABLE);    
+    #endif
+    #ifdef LORA_RADIO_DIO1_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio1IrqEvent,(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);    
+    #endif
+    #ifdef LORA_RADIO_DIO2_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO2_PIN, PIN_IRQ_MODE_RISING,SX127xOnDio2IrqEvent,(void*)"rf-dio2");
+    rt_pin_irq_enable(LORA_RADIO_DIO2_PIN, PIN_IRQ_ENABLE);    
+    #endif
+#else
+    #ifdef LORA_RADIO_DIO0_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO0_PIN, PIN_IRQ_MODE_RISING,irqHandlers[0],(void*)"rf-dio0");
+    rt_pin_irq_enable(LORA_RADIO_DIO0_PIN, PIN_IRQ_ENABLE);    
+    #endif
+    #ifdef LORA_RADIO_DIO1_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO1_PIN, PIN_IRQ_MODE_RISING,irqHandlers[1],(void*)"rf-dio1");
+    rt_pin_irq_enable(LORA_RADIO_DIO1_PIN, PIN_IRQ_ENABLE);    
+    #endif
+    #ifdef LORA_RADIO_DIO2_PIN
+    rt_pin_attach_irq(LORA_RADIO_DIO2_PIN, PIN_IRQ_MODE_RISING,irqHandlers[2],(void*)"rf-dio2");
+    rt_pin_irq_enable(LORA_RADIO_DIO2_PIN, PIN_IRQ_ENABLE);    
+    #endif
+#endif    
+}
+
+void SX127xIoDeInit( void )
+{
+
+}
+
+void SX127xIoDbgInit( void )
+{
+
+}
+
+
+void SX127xReset( void )
+{
+    // Set RESET pin to 0
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_OUTPUT);
+    rt_pin_write(LORA_RADIO_RESET_PIN, PIN_LOW);
+    
+    // Wait 1 ms
+    SX127X_DELAY_MS( 1 );
+
+    // Configure RESET as input
+    rt_pin_mode(LORA_RADIO_RESET_PIN, PIN_MODE_INPUT);
+
+    // Wait 6 ms
+    SX127X_DELAY_MS( 6 );
+}
+
+void SX127xSetAntSwLowPower( bool status )
+{
+    if( RadioIsActive != status )
+    {
+        RadioIsActive = status;
+
+        if( status == false )
+        {
+            SX127xAntSwInit( );
+        }
+        else
+        {
+            SX127xAntSwDeInit( );
+        }
+    }
+}
+
+void SX127xAntSwInit( void )
+{
+}
+
+void SX127xAntSwDeInit( void )
+{
+}
+
+/* TX and RX ANT switch */
+
+void SX127xSetAntSw( uint8_t opMode )
+{
+}
+
+#if defined( USE_RADIO_DEBUG )
+void SX127xDbgPinTxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinTx, state );
+}
+
+void SX127xDbgPinRxWrite( uint8_t state )
+{
+    GpioWrite( &DbgPinRx, state );
+}
+#endif
+
+uint8_t SX127xGetPaSelect( int8_t power )
+{
+    return RF_PACONFIG_PASELECT_PABOOST;
+}
+
+bool SX127xCheckRfFrequency( uint32_t frequency )
+{
+    // Implement check. Currently all frequencies are supported,todo depend on board
+    return true; 
+}
+
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/ports/lora-module/stm32_adapter/lora-spi-board.c

@@ -0,0 +1,101 @@
+/*!
+ * \file      lora-spi-board.c
+ *
+ * \brief     spi peripheral initlize,it depend on mcu platform.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#ifdef LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X
+#include "sx126x-board.h"
+#elif defined LORA_RADIO_DRIVER_USING_LORA_CHIP_SX127X
+#include "sx127x-board.h"
+#endif
+
+#define LOG_TAG "LoRa.STM32.SPI"
+#define LOG_LEVEL  LOG_LVL_DBG 
+#include "lora-radio-debug.h"
+
+/* for get GPIO fort,eg GPIOA */
+#ifndef GET_GPIO_PORT
+#define GET_GPIO_PORT(pin) (GPIO_TypeDef *)( GPIOA_BASE + (uint32_t) ( pin >> 4 ) * 0x0400UL ) 
+#endif
+#ifndef GET_GPIO_PIN
+#define GET_GPIO_PIN(pin) (rt_uint16_t)( 1 << ( pin & 0x0F ) ) // for get GPIO_PIN, eg: GPIO_PIN_6
+#endif
+
+#ifdef LORA_RADIO_GPIO_SETUP_BY_PIN_NAME
+#if ( RT_VER_NUM <= 0x40002 )
+extern int stm32_pin_get(char *pin_name);
+#endif
+#endif
+
+struct rt_spi_device *lora_radio_spi_init(const char *bus_name, const char *lora_device_name, rt_uint8_t param)
+{
+    rt_err_t res;
+    struct rt_spi_device *lora_radio_spi_device;
+    
+    RT_ASSERT(bus_name);
+    
+    {
+        /* eg: res = rt_hw_spi_device_attach( bus_name, lora_device_name, GPIOA, GPIO_PIN_15); */
+        res = rt_hw_spi_device_attach( bus_name, lora_device_name, GET_GPIO_PORT(LORA_RADIO_NSS_PIN), GET_GPIO_PIN(LORA_RADIO_NSS_PIN));
+        
+        if (res != RT_EOK)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"rt_spi_bus_attach_device failed!\r\n");
+            return RT_NULL;
+        }
+        
+        lora_radio_spi_device = (struct rt_spi_device *)rt_device_find(lora_device_name);
+        if (!lora_radio_spi_device)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"spi sample run failed! cant't find %s device!\n", lora_device_name);
+            return RT_NULL;
+        }
+    }
+    
+    LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"find %s device!\n", lora_device_name);
+    
+    /* config spi */
+    {
+        struct rt_spi_configuration cfg;
+        cfg.data_width = 8;
+        cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0. */
+        cfg.max_hz = 8 * 1000000;             /* max 10M */
+        
+        res = rt_spi_configure(lora_radio_spi_device, &cfg);
+        
+        if (res != RT_EOK)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"rt_spi_configure failed!\r\n");
+        }
+        res = rt_spi_take_bus(lora_radio_spi_device);
+        if (res != RT_EOK)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"rt_spi_take_bus failed!\r\n");
+        }
+        
+        res = rt_spi_release_bus(lora_radio_spi_device);
+        
+        if(res != RT_EOK)
+        {
+            LORA_RADIO_DEBUG_LOG(LR_DBG_SPI, LOG_LEVEL,"rt_spi_release_bus failed!\r\n");
+        }
+    }
+	
+    return lora_radio_spi_device;
+} 
+
+/**
+ * This function releases memory
+ *
+ * @param dev the pointer of device driver structure
+ */
+void lora_radio_spi_deinit(struct rt_spi_device *dev)
+{
+    RT_ASSERT(dev);
+    rt_spi_release_bus(dev);
+}

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/samples/SConscript

@@ -0,0 +1,14 @@
+from building import *
+
+src   = []
+cwd   = GetCurrentDir()
+include_path = [cwd]
+
+
+if GetDepend('LORA_RADIO_DRIVER_USING_LORA_RADIO_TEST_SHELL'):
+    src += Glob('lora-radio-test-shell/lora-radio-test-shell.c')
+
+
+group = DefineGroup('lora-radio-driver/sample', src, depend = ['PKG_USING_LORA_RADIO_DRIVER'], CPPPATH = include_path)
+
+Return('group')

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/samples/lora-radio-test-shell/lora-radio-test-shell.c

@@ -0,0 +1,666 @@
+/*!
+ * \file      lora-radio-test-shell.c
+ *
+ * \brief     lora radio shell for test implementation
+ *
+ * \copyright SPDX-License-Identifier: Apache-2.0
+ *
+ * \author    Forest-Rain
+ */
+#include "lora-radio-rtos-config.h"
+#include "lora-radio.h"
+#include "lora-radio-timer.h"
+#include "lora-radio-test-shell.h"
+
+#define LOG_TAG "APP.LoRa.Radio.Shell"
+#define LOG_LEVEL  LOG_LVL_INFO
+#include "lora-radio-debug.h"
+
+#define TX_LED_TOGGLE
+#define TX_LED_ON
+#define TX_LED_OFF
+
+#define RX_LED_TOGGLE
+#define RX_LED_ON
+#define RX_LED_OFF
+
+static struct rt_event radio_event;
+
+const static uint8_t PingMsg[] = "PING";
+
+static uint16_t BufferSize = BUFFER_SIZE;
+static uint8_t Buffer[BUFFER_SIZE];
+
+static int16_t rssi_value = -255;
+static int16_t rssi_value_min = -255;
+static int16_t rssi_value_max = -255;
+static int32_t rssi_value_total = 0;
+
+static int8_t snr_value = -128;
+static int8_t snr_value_min = -128;
+static int8_t snr_value_max = -128;
+static int32_t snr_value_total = 0;
+
+static uint32_t master_address = LORA_MASTER_DEVADDR;
+static uint32_t slaver_address = LORA_SLAVER_DEVADDR;
+static uint32_t payload_len = 32;
+
+static uint32_t tx_seq_cnt = 0;
+static uint16_t max_tx_nbtrials = 10;
+static uint32_t rx_correct_cnt = 0;
+static uint32_t rx_error_cnt = 0;
+static uint32_t rx_timeout_cnt = 0;
+
+static uint32_t tx_timestamp;
+static uint32_t rx_timestamp;
+
+static uint32_t rx_timeout = RX_TIMEOUT_VALUE;
+static uint8_t lora_chip_initialized;
+static bool master_flag = true;
+static bool rx_only_flag = false;
+
+static lora_radio_test_t lora_radio_test_paras = 
+{
+    .frequency = RF_FREQUENCY,
+    .txpower   = TX_OUTPUT_POWER,
+    
+    // lora
+    .modem     = MODEM_LORA,
+    .sf        = LORA_SPREADING_FACTOR,
+    .bw        = LORA_BANDWIDTH,
+    .cr        = LORA_CODINGRATE,
+    
+     // FSK
+    .fsk_bandwidth = FSK_BANDWIDTH,
+};
+/*!
+ * Radio events function pointer
+ */
+static RadioEvents_t RadioEvents;
+
+/*!
+ * lora radio test thread
+ */
+static rt_thread_t lora_radio_test_thread = RT_NULL; 
+
+/*!
+ * \brief Function to be executed on Radio Tx Done event
+ */
+static void OnTxDone( void );
+
+/*!
+ * \brief Function to be executed on Radio Rx Done event
+ */
+static void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr );
+
+/*!
+ * \brief Function executed on Radio Tx Timeout event
+ */
+static void OnTxTimeout( void );
+
+/*!
+ * \brief Function executed on Radio Rx Timeout event
+ */
+static void OnRxTimeout( void );
+
+/*!
+ * \brief Function executed on Radio Rx Error event
+ */
+static void OnRxError( void );
+
+/*!
+ * \brief thread for ping ping
+ */
+static void lora_radio_test_thread_entry(void* parameter);
+
+static void OnTxDone( void )
+{
+    Radio.Sleep( );
+    rt_event_send(&radio_event, EV_RADIO_TX_DONE);
+}
+
+static void OnRxDone( uint8_t *payload, uint16_t size, int16_t rssi, int8_t snr )
+{
+    Radio.Sleep( );
+    BufferSize = size;
+    rt_memcpy( Buffer, payload, BufferSize );
+    rssi_value = rssi;
+    snr_value = snr;
+ 
+    // first rxdone
+    if( rssi_value_max == -255 )
+    {
+        rssi_value_min = rssi_value_max = rssi;
+    }
+    if( snr_value_max == -128 )
+    {
+        snr_value_min = snr_value_max = snr;
+    }
+    
+    // update
+    if( rssi_value < rssi_value_min )
+    {
+        rssi_value_min = rssi_value;
+    }        
+    else if( rssi_value > rssi_value_max )
+    {
+        rssi_value_max = rssi_value;
+    }        
+    
+    if( snr_value < snr_value_min )
+    {
+        snr_value_min = snr_value;
+    }        
+    else if( snr_value > rssi_value_max )
+    {
+        snr_value_max = snr_value;
+    }   
+    
+    rssi_value_total += rssi_value;
+    snr_value_total += snr_value;
+    rx_timestamp = TimerGetCurrentTime();
+    
+    rt_event_send(&radio_event, EV_RADIO_RX_DONE);
+}
+
+static void OnTxTimeout( void )
+{
+    Radio.Sleep( );
+    rt_event_send(&radio_event, EV_RADIO_TX_TIMEOUT);
+}
+
+static void OnRxTimeout( void )
+{
+    Radio.Sleep( );
+    rx_timestamp = TimerGetCurrentTime();
+    rt_event_send(&radio_event, EV_RADIO_RX_TIMEOUT);
+}
+
+static void OnRxError( void )
+{
+    Radio.Sleep( );
+    rt_event_send(&radio_event, EV_RADIO_RX_ERROR);
+}
+
+static void send_ping_packet(uint32_t src_addr,uint32_t dst_addr,uint8_t len)
+{
+    tx_seq_cnt++;
+                            
+    tx_timestamp = TimerGetCurrentTime();
+    
+    // Send the next PING frame
+    uint8_t index = 0;
+    
+    // header 
+    Buffer[index++] = 0x00; // echo cmd
+    
+    Buffer[index++] = src_addr & 0xFF;
+    Buffer[index++] = src_addr >> 8;
+    Buffer[index++] = src_addr >> 16;
+    Buffer[index++] = src_addr >> 24;
+
+    Buffer[index++] = dst_addr & 0xFF;
+    Buffer[index++] = dst_addr >> 8;
+    Buffer[index++] = dst_addr >> 16;
+    Buffer[index++] = dst_addr >> 24;
+ 
+    Buffer[index++] = tx_seq_cnt & 0xFF;
+    Buffer[index++] = tx_seq_cnt >> 8;
+    Buffer[index++] = tx_seq_cnt >> 16;
+    Buffer[index++] = tx_seq_cnt >> 24;    
+    
+    // data
+    Buffer[index++] = 'P';
+    Buffer[index++] = 'I';
+    Buffer[index++] = 'N';
+    Buffer[index++] = 'G';
+    
+    // 00,01,02...
+    for( uint8_t i = 0; i < len - index ; i++)
+    {
+        Buffer[index + i] = i;
+    }
+    rt_thread_mdelay(1);
+    Radio.Send( Buffer, len );
+}
+
+static bool lora_radio_test_init(void)
+{
+    if( lora_chip_initialized == false )
+    {
+        // Target board initialization
+
+        if( lora_radio_test_thread == RT_NULL )
+        {
+            rt_event_init(&radio_event, "ev_lora_test", RT_IPC_FLAG_FIFO);
+
+            lora_radio_test_thread = rt_thread_create("lora-radio-test",
+                                                        lora_radio_test_thread_entry, 
+                                                        RT_NULL,
+                                                        8096, 
+                                                        2, 
+                                                        10);
+            if (lora_radio_test_thread != RT_NULL)
+            {
+                rt_thread_startup(lora_radio_test_thread);
+            }
+            else
+                rt_kprintf("lora radio test thread create failed!\n");
+        }
+        
+        /* Radio initialization */
+        RadioEvents.TxDone = OnTxDone;
+        RadioEvents.RxDone = OnRxDone;
+        RadioEvents.TxTimeout = OnTxTimeout;
+        RadioEvents.RxTimeout = OnRxTimeout;
+        RadioEvents.RxError = OnRxError;
+
+        if(Radio.Init(&RadioEvents))
+        {
+            /* setup private syncword for p2p test */
+            Radio.SetPublicNetwork( false );
+            
+            lora_chip_initialized = true;
+        }
+        else
+        {
+            rt_kprintf("lora radio Init failed!\n");
+            
+            return false;
+        }
+    }
+    return true;
+}
+
+static void radio_rx(void)
+{
+    rt_uint32_t timeout = 0; 
+    if( master_flag == true )
+    {
+        timeout = rx_timeout;
+    }
+    Radio.Rx( timeout );
+}
+
+static void lora_radio_test_thread_entry(void* parameter)  
+{
+    rt_uint32_t ev = 0;
+
+    while( 1 )                          
+    {
+        if (rt_event_recv(&radio_event, EV_RADIO_ALL,
+                                        RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                                        RT_WAITING_FOREVER, &ev) == RT_EOK)
+        {
+            switch( ev )
+            {
+                case EV_RADIO_INIT:
+                    
+                    Radio.SetChannel( lora_radio_test_paras.frequency );
+
+                    if( lora_radio_test_paras.modem == MODEM_LORA )
+                    {
+                        Radio.SetTxConfig( MODEM_LORA, lora_radio_test_paras.txpower, 0, lora_radio_test_paras.bw,
+                                                       lora_radio_test_paras.sf, lora_radio_test_paras.cr,
+                                                       LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE,
+                                                       true, 0, 0, LORA_IQ_INVERSION_ON_DISABLE, 3000 );
+
+                        Radio.SetRxConfig( MODEM_LORA, lora_radio_test_paras.bw, lora_radio_test_paras.sf,
+                                                       lora_radio_test_paras.cr, 0, LORA_PREAMBLE_LENGTH,
+                                                       LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE,
+                                                       0, true, 0, 0, LORA_IQ_INVERSION_ON_DISABLE, true );                                                                              
+                    }
+                    else
+                    {
+                        Radio.SetTxConfig( MODEM_FSK, lora_radio_test_paras.txpower, FSK_FDEV, 0,
+                                                      FSK_DATARATE, 0,
+                                                      FSK_PREAMBLE_LENGTH, FSK_FIX_LENGTH_PAYLOAD_ON,
+                                                      true, 0, 0, 0, 3000 );
+
+                        Radio.SetRxConfig( MODEM_FSK, FSK_BANDWIDTH, FSK_DATARATE,
+                                                      0, FSK_AFC_BANDWIDTH, FSK_PREAMBLE_LENGTH,
+                                                      0, FSK_FIX_LENGTH_PAYLOAD_ON, 0, true,
+                                                      0, 0,false, true );
+                    }
+
+                    /* initlize the statistics parameters */
+                    rssi_value = -255;
+                    rssi_value_min = -255;
+                    rssi_value_max = -255;
+                    rssi_value_total = 0;
+                    snr_value = -128;
+                    snr_value_min = -128;
+                    snr_value_max = -128;
+                    snr_value_total = 0;
+                
+                    tx_seq_cnt = 0;
+                    rx_timeout_cnt = 0;
+                    rx_error_cnt = 0;
+                    rx_correct_cnt = 0;
+
+                    if( master_flag == 0 )
+                    {
+                        if( rx_only_flag == false )
+                        {
+                            rt_kprintf("Slaver Address(SA):[0x%X]\n",slaver_address);
+                        }
+                        rt_kprintf("Stay to Rx Continuous with freq=%d, SF=%d, CR=%d, BW=%d\n", lora_radio_test_paras.frequency, lora_radio_test_paras.sf, lora_radio_test_paras.cr, lora_radio_test_paras.bw);
+                        
+                        Radio.Rx( 0 );
+                    }
+                    else
+                    {
+                        rt_event_send(&radio_event, EV_RADIO_TX_START);
+                    }
+                    break;
+                  
+                case EV_RADIO_RX_DONE:
+                    if( master_flag == true )
+                    {
+                        if( BufferSize > 0 )
+                        {
+                            if( rt_strncmp( ( const char* )Buffer + MAC_HEADER_OVERHEAD, ( const char* )PingMsg, 4 ) == 0 )
+                            {
+                                /* Indicates on a LED that the received frame is a PING ACK packet */
+                                RX_LED_TOGGLE;
+                                rx_correct_cnt++;
+
+                                uint32_t slaver_addr = 0;
+                                slaver_addr = Buffer[5];
+                                slaver_addr |= Buffer[6] << 8;
+                                slaver_addr |= Buffer[7] << 16;
+                                slaver_addr |= Buffer[8] << 24;
+
+                                uint32_t received_seqno = 0;
+                                received_seqno = Buffer[9];
+                                received_seqno |= Buffer[10] << 8;
+                                received_seqno |= Buffer[11] << 16;
+                                received_seqno |= Buffer[12] << 24;
+                                
+                               rt_kprintf("Reply from [0x%X]:seqno=%d, bytes=%d,total time=%d ms,rssi=%d,snr=%d\n",slaver_addr, received_seqno, BufferSize,( rx_timestamp - tx_timestamp ),rssi_value,snr_value );
+                             
+                               /* Send the next PING frame */
+                               rt_event_send(&radio_event, EV_RADIO_TX_START);
+                               break;
+                            }
+                            else /* valid reception but neither a PING ACK */
+                            {   
+                                Radio.Rx( RX_TIMEOUT_VALUE );
+                            }
+                        }
+                        else
+                        {
+                            rt_kprintf("RX ERR:BufferSize = 0");
+                        }
+                    }
+                    else
+                    {
+                        if( BufferSize > 0 )
+                        {
+                            #define DST_ADDRESS_OFFSET 5
+                            uint32_t dst_address = Buffer[DST_ADDRESS_OFFSET] | \
+                                                 ( Buffer[DST_ADDRESS_OFFSET+1] << 8 ) |\
+                                                 ( Buffer[DST_ADDRESS_OFFSET+2] << 16 )|\
+                                                 ( Buffer[DST_ADDRESS_OFFSET+3] << 24); 
+
+                            if( rx_only_flag == true )
+                            {
+                                /* Indicates on a LED that the received frame */
+                                RX_LED_TOGGLE;
+                            
+                                uint32_t src_addr,dst_addr = 0;
+                                src_addr = Buffer[1];
+                                src_addr |= Buffer[2] << 8;
+                                src_addr |= Buffer[3] << 16;
+                                src_addr |= Buffer[4] << 24;
+
+                                dst_addr = Buffer[5];
+                                dst_addr |= Buffer[6] << 8;
+                                dst_addr |= Buffer[7] << 16;
+                                dst_addr |= Buffer[8] << 24;
+                                
+                                rx_correct_cnt++;
+                                
+                                /* RX continuous */
+                                Radio.Rx( 0 ); 
+              
+                                rt_kprintf("Received: Totals=%d,bytes=%d,timestamp=%d ms,rssi=%d,snr=%d\n",rx_correct_cnt, BufferSize,rx_timestamp,rssi_value,snr_value );
+
+#ifdef RT_USING_ULOG
+                                ulog_hexdump(LOG_TAG,16,Buffer,BufferSize);
+#endif
+                            }   
+                            else if( ( dst_address == slaver_address || dst_address == 0xFFFFFFFF ) && \
+                                ( rt_strncmp( ( const char* )Buffer + MAC_HEADER_OVERHEAD, ( const char* )PingMsg, 4 ) == 0 ))
+                            {
+                                /* Indicates on a LED that the received frame is a PING */
+                                RX_LED_TOGGLE;
+                                /* echo the receive packet to master */
+                                {
+                                    rt_thread_mdelay(1);
+                                    Radio.Send( Buffer, BufferSize );
+                                }
+                            }                            
+                            else /* valid reception but not a PING as expected */
+                            {    
+                                Radio.Rx( 0 ); 
+                            }
+                        }
+                    }
+                    break;
+            case EV_RADIO_TX_DONE:
+                /* Indicates on a LED that we have sent a PING [Master] */
+                /* Indicates on a LED that we have sent a PING ACK [Slave] */
+                TX_LED_TOGGLE;
+                radio_rx();
+
+                break;
+            case EV_RADIO_RX_TIMEOUT:
+                rx_timeout_cnt++;
+                rt_kprintf("Request [SA=0x%X] timed out: seqno=%d, time=%d ms\n", slaver_address, tx_seq_cnt, ( rx_timestamp - tx_timestamp ) );
+             case EV_RADIO_RX_ERROR:
+             case EV_RADIO_TX_START:
+                    if( master_flag == true )
+                    {
+                        /* tx_seq_cnt start from 0 */
+                        if( tx_seq_cnt < max_tx_nbtrials ) 
+                        {
+                            /* for first time to printf some info */
+                            if( !tx_seq_cnt ) 
+                            {
+                                uint32_t packet_toa = Radio.TimeOnAir(lora_radio_test_paras.modem,lora_radio_test_paras.bw,lora_radio_test_paras.sf,lora_radio_test_paras.cr,LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE,payload_len,true);
+                                rt_kprintf("Master Address(MA):[0x%X]\n",master_address);
+                                rt_kprintf("Pinging [SA=0x%X] with %d bytes(ToA=%d ms) of data for %d counters:\n", slaver_address, payload_len, packet_toa, max_tx_nbtrials);
+                                rt_kprintf("With radio parameters: freq=%d, TxPower=%d, SF=%d, CR=%d, BW=%d\n", lora_radio_test_paras.frequency, lora_radio_test_paras.txpower, lora_radio_test_paras.sf, lora_radio_test_paras.cr, lora_radio_test_paras.bw);
+                            }
+    
+                            send_ping_packet(master_address,slaver_address,payload_len);
+                        }
+                        else
+                        {
+                            uint16_t per = 100 - ( (float) rx_correct_cnt / tx_seq_cnt ) * 100;
+                            uint32_t tx_total_byte = tx_seq_cnt * ( payload_len + MAC_HEADER_OVERHEAD );
+                            uint32_t tx_total_kbyte_integer = tx_total_byte >> 10;   // / 1024
+                            uint32_t tx_total_kbyte_decimal = tx_total_byte & 0x3FF; // % 1024
+                            
+                            uint32_t rx_total_byte = rx_correct_cnt * ( payload_len + MAC_HEADER_OVERHEAD );
+                            uint32_t rx_total_kbyte_integer = rx_total_byte >> 10;   // / 1024
+                            uint32_t rx_total_kbyte_decimal = rx_total_byte & 0x3FF; // % 1024
+                            int32_t avg_rssi = -255;
+                            int32_t avg_snr = -128;
+                            if( rx_correct_cnt )
+                            {
+                                avg_rssi = rssi_value_total / (int32_t)rx_correct_cnt;
+                                avg_snr = snr_value_total / (int32_t)rx_correct_cnt;
+                            }
+                            /* wait for PHY log output done */
+                            rt_thread_mdelay(10);
+                            rt_kprintf("\r\n====== LoRa Ping statistics for [MA=0x%X <-> SA=0x%X] with [TxPower=%d,SF=%d] ======\n",master_address, slaver_address, lora_radio_test_paras.txpower, lora_radio_test_paras.sf);
+                            rt_kprintf("-> Tx pakcets: sent = %d, tx_total = %d.%d KByte\n",tx_seq_cnt, tx_total_kbyte_integer, tx_total_kbyte_decimal);
+                            rt_kprintf("-> Rx pakcets: received = %d, lost = %d, per = %d%, rx_total = %d.%d KByte\n",rx_correct_cnt, rx_timeout_cnt + rx_error_cnt, per,rx_total_kbyte_integer,rx_total_kbyte_decimal);
+                            rt_kprintf("--> Rx rssi: max_rssi = %d, min_rssi = %d, avg_rssi = %d\n",rssi_value_max,rssi_value_min,avg_rssi);
+                            rt_kprintf("--> Rx snr: max_snr  = %d, min_snr  = %d, avg_snr  = %d\n",snr_value_max,snr_value_min,avg_snr);
+                            rt_kprintf("====== LoRa Ping Test Finished ======\r\n");
+                        }
+                    }
+                    else
+                    {
+                        Radio.Rx( 0 );
+                    }
+                    break;
+                case EV_RADIO_TX_TIMEOUT:
+                    radio_rx();
+                    break;  
+            }
+        }
+    } 
+}
+
+/* for finish\msh */
+#define CMD_LORA_CHIP_PROBE_INDEX        0 // LoRa Chip probe
+#define CMD_LORA_CHIP_CONFIG_INDEX       1 // tx cw
+#define CMD_TX_CW_INDEX                  2 // tx cw
+#define CMD_PING_INDEX                   3 // ping-pong
+#define CMD_RX_PACKET_INDEX              4 // rx packet only
+
+const char* lora_help_info[] = 
+{
+    [CMD_LORA_CHIP_PROBE_INDEX]       = "lora probe             - lora radio probe",
+    [CMD_LORA_CHIP_CONFIG_INDEX]      = "lora config<modem>     - lora radio config parameters", 
+    [CMD_TX_CW_INDEX]                 = "lora cw <freq>,<power> - tx carrier wave",
+    [CMD_PING_INDEX]                  = "lora ping <para1>      - ping <-m: master,-s: slaver>",   
+    [CMD_RX_PACKET_INDEX]             = "lora rx <timeout>      - rx data only(sniffer)",
+};
+
+/* LoRa Radio Test Shell */
+static int lora(int argc, char *argv[])
+{
+    size_t i = 0;
+    
+    if (argc < 2)
+    {   
+        /* parameter error */
+        rt_kprintf("Usage:\n");
+        for (i = 0; i < sizeof(lora_help_info) / sizeof(char*); i++) 
+        {
+            rt_kprintf("%s\n", lora_help_info[i]);
+        }
+        rt_kprintf("\n");
+    } 
+    else 
+    {
+        const char *cmd = argv[1];
+
+        if( lora_radio_test_init() == false )
+        {
+            rt_kprintf("LoRa Chip Init Failed\n");
+            return 0;
+        }
+
+        if (!rt_strcmp(cmd, "probe")) 
+        {   
+            rt_kprintf("LoRa Chip start to test\n");
+
+            if( Radio.Check() )
+            {
+                rt_kprintf("LoRa Chip Probe ok!\n");
+            }
+            else
+            {
+                rt_kprintf("LoRa Chip Probe failed!\n!");
+            }
+        }
+        else if (!rt_strcmp(cmd, "cw")) 
+        {
+            uint8_t timeout = 0;
+            if (argc >= 3) 
+            {
+                lora_radio_test_paras.frequency = atol(argv[2]);
+            }
+            if (argc >= 4) 
+            {
+                lora_radio_test_paras.txpower = atol(argv[3]);
+            }
+            if (argc >= 5) 
+            {
+                timeout = atol(argv[4]);
+            }
+            Radio.SetTxContinuousWave( lora_radio_test_paras.frequency, lora_radio_test_paras.txpower, timeout);
+        }
+        else if (!rt_strcmp(cmd, "ping")) 
+        {       
+            /* default for slaver */
+            master_flag  = false;  
+            rx_only_flag = false;
+            
+            if (argc >= 3) 
+            {   
+                 const char *cmd1 = argv[2];
+                 if (!rt_strcmp(cmd1, "-m")) 
+                 {
+                     master_flag = true;
+                }
+                else // -s
+                {
+                    master_flag = false;
+                }
+                 
+                if( argc >=4 )
+                 {
+                    /* max_tx_nbtrials for setup tx counter */
+                    max_tx_nbtrials = atol(argv[3]);
+                 }
+            } 
+
+            rt_event_send(&radio_event, EV_RADIO_INIT);
+        }
+        else if( !rt_strcmp(cmd, "rx"))
+        {   
+            /* eg: lora rx 1 0 */
+            master_flag = false;
+            rx_only_flag = true;
+            
+            if (argc >= 3) 
+            {
+                rx_only_flag = atol(argv[2]);
+            }
+            if (argc >= 4) 
+            {
+                rx_timeout = atol(argv[3]);
+            }
+            
+            rt_event_send(&radio_event, EV_RADIO_INIT);
+        }
+        else if (!rt_strcmp(cmd, "config"))
+        {
+            /* config radio paramters, such as frequency,txPower,sf,bw...*/
+            if (argc >= 3) 
+            {
+                lora_radio_test_paras.frequency = atol(argv[2]);
+            }
+            if (argc >= 4) 
+            {
+                lora_radio_test_paras.txpower = atol(argv[3]);
+            }
+            if (argc >= 5) 
+            {
+                lora_radio_test_paras.sf = atol(argv[4]);
+            }
+            if (argc >= 6) 
+            {
+                lora_radio_test_paras.bw = atol(argv[5]);
+            }
+            
+            rt_kprintf("Frequency: %d\n",lora_radio_test_paras.frequency);
+        
+            rt_kprintf("TxPower  : %d\n",lora_radio_test_paras.txpower);
+
+            rt_kprintf("SF: %d\n",lora_radio_test_paras.sf);
+            
+            rt_kprintf("BW: %d\n",lora_radio_test_paras.bw);
+        }
+    }
+    return 1;
+}
+MSH_CMD_EXPORT(lora, lora radio test shell);
+

projects/lrs007_lora_radio/packages/lora_radio_driver-v1.3.0/samples/lora-radio-test-shell/lora-radio-test-shell.h

@@ -0,0 +1,134 @@
+/*!
+ * \file      lora-radio-test-shell.h
+ *
+ * \brief     lora radio test implementation
+ *
+ * \copyright SPDX-License-Identifier: Apache-2.0
+ * 
+ * \author    Forest-Rain
+ */
+
+#ifndef __LORA_RADIO_TEST_SHELL_H__
+#define __LORA_RADIO_TEST_SHELL_H__
+
+
+#if defined( PHY_REGION_AS923 )
+
+#define RF_FREQUENCY                                923000000 // Hz
+
+#elif defined( PHY_REGION_AU915 )
+
+#define RF_FREQUENCY                                915000000 // Hz
+
+#elif defined( PHY_REGION_CN470 ) || defined ( PHY_REGION_CN470S )
+
+#define RF_FREQUENCY                                470300000 // Hz
+
+#elif defined( PHY_REGION_CN779 )
+
+#define RF_FREQUENCY                                779000000 // Hz
+
+#elif defined( PHY_REGION_EU433 )
+
+#define RF_FREQUENCY                                433000000 // Hz
+
+#elif defined( PHY_REGION_EU868 )
+
+#define RF_FREQUENCY                                868000000 // Hz
+
+#elif defined( PHY_REGION_KR920 )
+
+#define RF_FREQUENCY                                920000000 // Hz
+
+#elif defined( PHY_REGION_IN865 )
+
+#define RF_FREQUENCY                                865000000 // Hz
+
+#elif defined( PHY_REGION_US915 )
+
+#define RF_FREQUENCY                                915000000 // Hz
+
+#elif defined( PHY_REGION_RU864 )
+
+#define RF_FREQUENCY                                864000000 // Hz
+
+#else
+    #error "Please define a frequency band in the compiler options."
+#endif
+
+#define TX_OUTPUT_POWER                             14        // dBm
+
+#define LORA_BANDWIDTH                              0         // [0: 125 kHz,
+                                                              //  1: 250 kHz,
+                                                              //  2: 500 kHz,
+                                                              //  3: Reserved]
+#define LORA_SPREADING_FACTOR                       7         // [SF7..SF12]
+#define LORA_CODINGRATE                             1         // [1: 4/5,
+                                                              //  2: 4/6,
+                                                              //  3: 4/7,
+                                                              //  4: 4/8]
+#define LORA_PREAMBLE_LENGTH                        8         // Same for Tx and Rx
+#define LORA_SYMBOL_TIMEOUT                         0         // Symbols
+#define LORA_FIX_LENGTH_PAYLOAD_ON_DISABLE          false
+#define LORA_IQ_INVERSION_ON_DISABLE                false
+
+
+#define FSK_FDEV                                    25000     // Hz
+#define FSK_DATARATE                                50000     // bps
+
+#if defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX127X )
+
+#define FSK_BANDWIDTH                               50000     // Hz >> SSB in sx127x
+#define FSK_AFC_BANDWIDTH                           83333     // Hz
+
+#elif defined( LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X)
+
+#define FSK_BANDWIDTH                               100000    // Hz >> DSB in sx126x
+#define FSK_AFC_BANDWIDTH                           166666    // Hz >> Unused in sx126x
+
+#else
+    #error "Please define a lora-shield in the compiler options."
+#endif
+
+#define FSK_PREAMBLE_LENGTH                         5         // Same for Tx and Rx
+#define FSK_FIX_LENGTH_PAYLOAD_ON                   false
+
+#define RX_TIMEOUT_VALUE                            1000
+#define BUFFER_SIZE                                 64 // Define the payload size here
+
+#define LORA_MASTER_DEVADDR 0x11223344
+#define LORA_SLAVER_DEVADDR 0x01020304
+#define MAC_HEADER_OVERHEAD 13
+
+// Ping pong event
+#define EV_RADIO_INIT            0x0001
+#define EV_RADIO_TX_START        0x0002
+#define EV_RADIO_TX_DONE         0x0004
+#define EV_RADIO_TX_TIMEOUT      0x0008
+#define EV_RADIO_RX_DONE         0x0010
+#define EV_RADIO_RX_TIMEOUT      0x0020
+#define EV_RADIO_RX_ERROR        0x0040
+#define EV_RADIO_ALL             (EV_RADIO_INIT | EV_RADIO_TX_START | EV_RADIO_TX_DONE | EV_RADIO_TX_TIMEOUT | EV_RADIO_RX_DONE | EV_RADIO_RX_TIMEOUT | EV_RADIO_RX_ERROR)
+
+typedef struct 
+{
+    RadioModems_t modem; // LoRa Modem \ FSK modem
+    uint32_t frequency;
+    int8_t txpower;
+    
+    // LoRa
+    uint8_t sf;    // spreadfactor
+    uint8_t bw;    // bandwidth
+    uint8_t cr;    // coderate
+
+    // FSK
+    uint32_t fdev;
+    uint32_t datarate;
+    uint32_t fsk_bandwidth;
+    uint32_t fsk_afc_bandwidth;
+    uint16_t preamble_len;
+
+}lora_radio_test_t;
+
+#endif
+

projects/lrs007_lora_radio/packages/pkgs.json

@@ -0,0 +1,7 @@
+[
+ {
+  "path": "/packages/peripherals/lora_radio_driver", 
+  "ver": "v1.3.0", 
+  "name": "LORA_RADIO_DRIVER"
+ }
+]

projects/lrs007_lora_radio/packages/pkgs_error.json

@@ -0,0 +1 @@
+[]

projects/lrs007_lora_radio/project.uvoptx

@@ -0,0 +1,1541 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>6</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U066CFF393732484257244451 -I0 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0ART-PI_W25Q64 -FS090000000 -FL0800000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0STM32H7x_128k -FL020000 -FS08000000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59700618 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO11 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743IIKx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>cpu</GroupName>
+    <tvExp>0</tvExp>
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+    <cbSel>0</cbSel>
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+      <bDave2>0</bDave2>
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+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
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+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
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+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>1</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <RvdsMve>0</RvdsMve>
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+            <hadIROM2>0</hadIROM2>
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+            <useUlib>1</useUlib>
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+            <RwSelD>4</RwSelD>
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+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
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+            <NoZi5>0</NoZi5>
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+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
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+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
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+            <Ra3Chk>0</Ra3Chk>
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+            <Im2Chk>1</Im2Chk>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x0</StartAddress>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
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+              <IROM>
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+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
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+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x48000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
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+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x48000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x38000000</StartAddress>
+                <Size>0x10000</Size>
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+              <OCR_RVCT8>
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+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
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+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
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+                <Type>0</Type>
+                <StartAddress>0x24000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>1</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>STM32H750xx, USE_HAL_DRIVER, RT_USING_ARM_LIBC</Define>
+              <Undefine></Undefine>
+              <IncludePath>applications;rt-thread\libcpu\arm\common;rt-thread\libcpu\arm\cortex-m7;rt-thread\components\drivers\include;rt-thread\components\drivers\include;rt-thread\components\drivers\spi;rt-thread\components\drivers\include;rt-thread\components\drivers\include;board;board\port;board\CubeMX_Config\Core\Inc;libraries\drivers;libraries\drivers\include;libraries\drivers\include\config;rt-thread\components\dfs\include;rt-thread\components\dfs\filesystems\devfs;rt-thread\components\finsh;.;rt-thread\include;rt-thread\components\libc\compilers\armlibc;rt-thread\components\libc\compilers\common;packages\lora_radio_driver-v1.3.0\lora-radio;packages\lora_radio_driver-v1.3.0\lora-radio\include;packages\lora_radio_driver-v1.3.0\lora-radio\common;packages\lora_radio_driver-v1.3.0\ports;packages\lora_radio_driver-v1.3.0\ports\lora-module\inc;packages\lora_radio_driver-v1.3.0\samples;libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Inc;libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Include;libraries\STM32H7xx_HAL\CMSIS\Include;rt-thread\components\utilities\ulog</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
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+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\STM32H750XBHx\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>cpu</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
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+              <FilePath>rt-thread\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpu_cache.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\libcpu\arm\cortex-m7\cpu_cache.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\libcpu\arm\cortex-m7\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>rt-thread\libcpu\arm\cortex-m7\context_rvds.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>0</GenerateAssemblyFile>
+              <AssembleAssemblyFile>0</AssembleAssemblyFile>
+              <PublicsOnly>0</PublicsOnly>
+              <StopOnExitCode>3</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>0</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
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+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
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+                <v6LangP>0</v6LangP>
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+                <vShortWch>2</vShortWch>
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+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define> </Define>
+                  <Undefine> </Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
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+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <uClangAs>2</uClangAs>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\spi\spi_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\spi\spi_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
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+              <FilePath>rt-thread\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\drivers\src\ringblk_buf.c</FilePath>
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+            <File>
+              <FileName>ringbuffer.c</FileName>
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+              <FilePath>rt-thread\components\drivers\src\ringbuffer.c</FilePath>
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+            <File>
+              <FileName>waitqueue.c</FileName>
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+              <FilePath>rt-thread\components\drivers\src\waitqueue.c</FilePath>
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+              <FileName>workqueue.c</FileName>
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+              <FilePath>rt-thread\components\drivers\src\workqueue.c</FilePath>
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+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_mpu.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\drv_mpu.c</FilePath>
+            </File>
+            <File>
+              <FileName>filesystem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\port\filesystem.c</FilePath>
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+            <File>
+              <FileName>stm32h7xx_hal_msp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>board\CubeMX_Config\Core\Src\stm32h7xx_hal_msp.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_common.c</FileName>
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+              <FilePath>libraries\drivers\drv_common.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_usart.c</FileName>
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+              <FilePath>libraries\drivers\drv_usart.c</FilePath>
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+            <File>
+              <FileName>drv_gpio.c</FileName>
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+              <FilePath>libraries\drivers\drv_gpio.c</FilePath>
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+            <File>
+              <FileName>drv_spi.c</FileName>
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+              <FilePath>libraries\drivers\drv_spi.c</FilePath>
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+            <File>
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+              <FilePath>libraries\drivers\drv_sdio.c</FilePath>
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+            <File>
+              <FileName>drv_wlan.c</FileName>
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+              <FilePath>libraries\drivers\drv_wlan.c</FilePath>
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+            <File>
+              <FileName>drv_sdram.c</FileName>
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+              <FilePath>libraries\drivers\drv_sdram.c</FilePath>
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+            <File>
+              <FileName>drv_lcd.c</FileName>
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+              <FilePath>libraries\drivers\drv_lcd.c</FilePath>
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+        <Group>
+          <GroupName>Filesystem</GroupName>
+          <Files>
+            <File>
+              <FileName>dfs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\src\dfs.c</FilePath>
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+            <File>
+              <FileName>dfs_file.c</FileName>
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+              <FilePath>rt-thread\components\dfs\src\dfs_file.c</FilePath>
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+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\src\dfs_fs.c</FilePath>
+            </File>
+            <File>
+              <FileName>dfs_posix.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\src\dfs_posix.c</FilePath>
+            </File>
+            <File>
+              <FileName>poll.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\src\poll.c</FilePath>
+            </File>
+            <File>
+              <FileName>select.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\src\select.c</FilePath>
+            </File>
+            <File>
+              <FileName>devfs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\dfs\filesystems\devfs\devfs.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh_file.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\msh_file.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_compiler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_compiler.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_error.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_error.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_heap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_heap.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_init.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_init.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_node.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_node.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_parser.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_parser.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_var.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_var.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_vm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_vm.c</FilePath>
+            </File>
+            <File>
+              <FileName>finsh_token.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\finsh\finsh_token.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\components.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>memheap.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\memheap.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>signal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\signal.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\src\timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libc</GroupName>
+          <Files>
+            <File>
+              <FileName>libc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\libc\compilers\armlibc\libc.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem_std.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\libc\compilers\armlibc\mem_std.c</FilePath>
+            </File>
+            <File>
+              <FileName>stdio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\libc\compilers\armlibc\stdio.c</FilePath>
+            </File>
+            <File>
+              <FileName>stubs.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\libc\compilers\armlibc\stubs.c</FilePath>
+            </File>
+            <File>
+              <FileName>time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\libc\compilers\common\time.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>lora-radio-driver</GroupName>
+          <Files>
+            <File>
+              <FileName>lora-radio-sx126x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\lora-radio\sx126x\lora-radio-sx126x.c</FilePath>
+            </File>
+            <File>
+              <FileName>lora-spi-sx126x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\lora-radio\sx126x\lora-spi-sx126x.c</FilePath>
+            </File>
+            <File>
+              <FileName>sx126x.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\lora-radio\sx126x\sx126x.c</FilePath>
+            </File>
+            <File>
+              <FileName>lora-radio-timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\lora-radio\common\lora-radio-timer.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>lora-radio-driver/board</GroupName>
+          <Files>
+            <File>
+              <FileName>lora-spi-board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\ports\lora-module\stm32_adapter\lora-spi-board.c</FilePath>
+            </File>
+            <File>
+              <FileName>sx1268-board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\ports\lora-module\stm32_adapter\SX1268_LSD4RF-2R717N40\sx1268-board.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>lora-radio-driver/sample</GroupName>
+          <Files>
+            <File>
+              <FileName>lora-radio-test-shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>packages\lora_radio_driver-v1.3.0\samples\lora-radio-test-shell\lora-radio-test-shell.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>STM32_HAL</GroupName>
+          <Files>
+            <File>
+              <FileName>system_stm32h7xx.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cec.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cec.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cortex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cortex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_comp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_comp.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_crc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_crc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_crc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cryp.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_cryp_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_cryp_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_dma_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_mdma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_mdma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_pwr_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_pwr_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rcc_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rcc_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_rng.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_rng.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_sram.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_sram.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>startup_stm32h750xx.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\CMSIS\Device\ST\STM32H7xx\Source\Templates\arm\startup_stm32h750xx.s</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_usart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_usart.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_uart_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_uart_ex.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_spi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_spi.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h7xx_hal_qspi.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\STM32H7xx_HAL\STM32H7xx_HAL_Driver\Src\stm32h7xx_hal_qspi.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Utilities</GroupName>
+          <Files>
+            <File>
+              <FileName>ulog.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\utilities\ulog\ulog.c</FilePath>
+            </File>
+            <File>
+              <FileName>console_be.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>rt-thread\components\utilities\ulog\backend\console_be.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

projects/lrs007_lora_radio/rtconfig.h

@@ -0,0 +1,283 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib) */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* end of Inter-Thread communication */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_MEMHEAP
+#define RT_USING_MEMHEAP_AS_HEAP
+#define RT_USING_HEAP
+/* end of Memory Management */
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart4"
+/* end of Kernel Device Object */
+#define RT_VER_NUM 0x40003
+/* end of RT-Thread Kernel */
+#define ARCH_ARM
+#define RT_USING_CPU_FFS
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M7
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+/* end of C++ features */
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+/* end of Command shell */
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 6
+#define DFS_FILESYSTEM_TYPES_MAX 6
+#define DFS_FD_MAX 32
+#define RT_USING_DFS_DEVFS
+/* end of Device virtual file system */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+#define RT_USING_SPI
+
+/* Using USB */
+
+/* end of Using USB */
+/* end of Device Drivers */
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+/* end of POSIX layer and C standard library */
+
+/* Network */
+
+/* Socket abstraction layer */
+
+/* end of Socket abstraction layer */
+
+/* Network interface device */
+
+/* end of Network interface device */
+
+/* light weight TCP/IP stack */
+
+/* end of light weight TCP/IP stack */
+
+/* AT commands */
+
+/* end of AT commands */
+/* end of Network */
+
+/* VBUS(Virtual Software BUS) */
+
+/* end of VBUS(Virtual Software BUS) */
+
+/* Utilities */
+
+#define RT_USING_ULOG
+#define ULOG_OUTPUT_LVL_D
+#define ULOG_OUTPUT_LVL 7
+#define ULOG_ASSERT_ENABLE
+#define ULOG_LINE_BUF_SIZE 384
+
+/* log format */
+
+#define ULOG_USING_COLOR
+#define ULOG_OUTPUT_TIME
+#define ULOG_OUTPUT_LEVEL
+#define ULOG_OUTPUT_TAG
+/* end of log format */
+#define ULOG_BACKEND_USING_CONSOLE
+/* end of Utilities */
+/* end of RT-Thread Components */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* end of Marvell WiFi */
+
+/* Wiced WiFi */
+
+/* end of Wiced WiFi */
+/* end of Wi-Fi */
+
+/* IoT Cloud */
+
+/* end of IoT Cloud */
+/* end of IoT - internet of things */
+
+/* security packages */
+
+/* end of security packages */
+
+/* language packages */
+
+/* end of language packages */
+
+/* multimedia packages */
+
+/* end of multimedia packages */
+
+/* tools packages */
+
+/* end of tools packages */
+
+/* system packages */
+
+/* end of system packages */
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_LORA_RADIO_DRIVER
+#define LORA_RADIO_DRIVER_USING_LORA_CHIP
+#define LORA_RADIO_DRIVER_USING_LORA_RADIO_SINGLE_INSTANCE
+#define LORA_RADIO0_DEVICE_NAME "lora-radio0"
+#define LORA_RADIO0_SPI_BUS_NAME "spi4"
+#define LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X
+
+/* Select Supported LoRa Module [SX126X] */
+
+#define LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R717N40
+
+/* LoRa Chip SX1268 (SPI module) */
+
+#define LORA_RADIO_USE_TCXO
+#define LORA_RADIO_GPIO_SETUP
+
+/* Select Supported Target Borad */
+
+#define LORA_RADIO_SPI_SETUP
+#define LORA_RADIO_GPIO_SETUP_BY_PIN_NUMBER
+#define LORA_RADIO_NSS_PIN 68
+#define LORA_RADIO_RESET_PIN 114
+#define LORA_RADIO_DIO1_PIN 16
+#define LORA_RADIO_DIO2_PIN 115
+#define LORA_RADIO_RFSW1_PIN 17
+#define LORA_RADIO_RFSW2_PIN 18
+#define LORA_RADIO_BUSY_PIN 6
+#define LORA_RADIO_DRIVER_USING_TRAGET_BOARD_ART_PI_AND_LRS007_RF_B
+/* end of Select Supported Target Borad */
+/* end of Select Supported LoRa Module [SX126X] */
+#define LORA_RADIO_DRIVER_USING_LORA_RADIO_DEBUG
+#define LR_DBG_APP_CONFIG
+#define LR_DBG_APP 1
+#define LR_DBG_INTERFACE_CONFIG
+#define LR_DBG_INTERFACE 1
+#define LR_DBG_CHIP_CONFIG
+#define LR_DBG_CHIP 1
+#define LR_DBG_SPI_CONFIG
+#define LR_DBG_SPI 1
+
+/* Select LoRa Radio Driver Example */
+
+#define LORA_RADIO_DRIVER_USING_LORA_RADIO_TEST_SHELL
+#define PHY_REGION_CN470
+#define USE_MODEM_LORA
+/* end of Select LoRa Radio Driver Example */
+#define PKG_USING_LORA_RADIO_DRIVER_V130
+/* end of peripheral libraries and drivers */
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+/* end of samples: kernel and components samples */
+/* end of miscellaneous packages */
+/* end of RT-Thread online packages */
+
+/* Hardware Drivers Config */
+
+#define SOC_STM32H750XB
+#define SOC_SERIES_STM32H7
+
+/* Board extended module */
+
+/* end of Board extended module */
+
+/* Onboard Peripheral */
+
+#define BSP_USING_USB_TO_USART
+/* end of Onboard Peripheral */
+
+/* On-chip Peripheral */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART4
+#define BSP_USING_SPI
+#define BSP_USING_SPI4
+/* end of On-chip Peripheral */
+/* end of Hardware Drivers Config */
+
+/* External Libraries */
+
+/* end of External Libraries */
+#define RT_STUDIO_BUILT_IN
+
+#endif

projects/lrs007_lora_radio/rtconfig.py

@@ -0,0 +1,102 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m7'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'C:\Users\XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/STM32H750XBHx/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M7.fp.sp'
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board/linker_scripts/STM32H750XBHx/link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

projects/lrs007_lora_radio/rtconfig_preinc.h

@@ -0,0 +1,13 @@
+
+#ifndef RTCONFIG_PREINC_H__
+#define RTCONFIG_PREINC_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread pre-include file */
+
+#define HAVE_CCONFIG_H
+#define RT_USING_NEWLIB
+#define STM32H750xx
+#define USE_HAL_DRIVER
+
+#endif /*RTCONFIG_PREINC_H__*/

projects/lrs007_lora_radio/template.uvoptx

@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>0</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>18</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>6</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ST-LINKIII-KEIL_SWO</Key>
+          <Name>-U066CFF393732484257244451 -I0 -O206 -S1 -C0 -A0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC4000 -FN1 -FF0ART-PI_W25Q64 -FS090000000 -FL0800000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 )  -FN1 -FC1000 -FD20000000 -FF0STM32H7x_128k -FL020000 -FS08000000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>JL2CM3</Key>
+          <Name>-U59700618 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO11 -FD20000000 -FC8000 -FN1 -FF0STM32H7x_2048.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H743IIKx$CMSIS\Flash\STM32H7x_2048.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>1</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>10000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

projects/lrs007_lora_radio/template.uvprojx

@@ -0,0 +1,390 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>STM32H750XBHx</Device>
+          <Vendor>STMicroelectronics</Vendor>
+          <PackID>Keil.STM32H7xx_DFP.2.5.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x24000000,0x00080000) IROM(0x08000000,0x00020000) XRAM(0x30000000,0x00048000) XRAM2(0x38000000,0x00010000) CPUTYPE("Cortex-M7") FPU3(DFPU) CLOCK(12000000) ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32H7x_128k -FS08000000 -FL020000 -FP0($$Device:STM32H750XBHx$CMSIS\Flash\STM32H7x_128k.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:STM32H750XBHx$Drivers\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>$$Device:STM32H750XBHx$CMSIS\SVD\STM32H750x.svd</SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM7</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM7</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M7"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>1</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>3</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>1</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </IROM>
+              <XRAM>
+                <Type>1</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x48000</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x8000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x30000000</StartAddress>
+                <Size>0x48000</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x38000000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x24000000</StartAddress>
+                <Size>0x80000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>1</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\STM32H750XBHx\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

projects/lrs007_lorawan_end_device/.config

@@ -0,0 +1,811 @@
+# Generated by Kconfiglib (https://github.com/ulfalizer/Kconfiglib)
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+# end of Inter-Thread communication
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_SMALL_MEM is not set
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
+CONFIG_RT_USING_HEAP=y
+# end of Memory Management
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
+# end of Kernel Device Object
+
+CONFIG_RT_VER_NUM=0x40003
+# end of RT-Thread Kernel
+
+CONFIG_ARCH_ARM=y
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M7=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+# end of C++ features
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+# end of Command shell
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=6
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=6
+CONFIG_DFS_FD_MAX=32
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# end of Device virtual file system
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+# end of Using USB
+# end of Device Drivers
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+# end of POSIX layer and C standard library
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+# end of Socket abstraction layer
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+# end of Network interface device
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+# end of light weight TCP/IP stack
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# end of AT commands
+# end of Network
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+# end of VBUS(Virtual Software BUS)
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_ULOG=y
+# CONFIG_ULOG_OUTPUT_LVL_A is not set
+# CONFIG_ULOG_OUTPUT_LVL_E is not set
+# CONFIG_ULOG_OUTPUT_LVL_W is not set
+# CONFIG_ULOG_OUTPUT_LVL_I is not set
+CONFIG_ULOG_OUTPUT_LVL_D=y
+CONFIG_ULOG_OUTPUT_LVL=7
+CONFIG_ULOG_USING_ISR_LOG=y
+CONFIG_ULOG_ASSERT_ENABLE=y
+CONFIG_ULOG_LINE_BUF_SIZE=384
+# CONFIG_ULOG_USING_ASYNC_OUTPUT is not set
+
+#
+# log format
+#
+# CONFIG_ULOG_OUTPUT_FLOAT is not set
+CONFIG_ULOG_USING_COLOR=y
+CONFIG_ULOG_OUTPUT_TIME=y
+# CONFIG_ULOG_TIME_USING_TIMESTAMP is not set
+CONFIG_ULOG_OUTPUT_LEVEL=y
+CONFIG_ULOG_OUTPUT_TAG=y
+# CONFIG_ULOG_OUTPUT_THREAD_NAME is not set
+# end of log format
+
+CONFIG_ULOG_BACKEND_USING_CONSOLE=y
+# CONFIG_ULOG_USING_FILTER is not set
+# CONFIG_ULOG_USING_SYSLOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# end of Utilities
+
+# CONFIG_RT_USING_LWP is not set
+# end of RT-Thread Components
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+# end of Marvell WiFi
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# end of Wiced WiFi
+
+# CONFIG_PKG_USING_RW007 is not set
+# end of Wi-Fi
+
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# end of IoT Cloud
+
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+CONFIG_PKG_USING_LORAWAN_ED_STACK=y
+CONFIG_PKG_LORAWAN_ED_STACK_PATH="/packages/iot/lorawan_ed_stack"
+CONFIG_LORAWAN_ED_STACK_USING_ON_RTOS_RT_THREAD=y
+CONFIG_LORAWAN_ED_STACK_USING_LORAWAN_SPECIFICATION_V1_0_X=y
+# CONFIG_LORAWAN_ED_STACK_USING_LORAWAN_SPECIFICATION_V1_1_X is not set
+CONFIG_LORAWAN_ED_STACK_USING_LORAWAN_PUBLIC_NETWORK=y
+# CONFIG_LORAWAN_ED_STACK_USING_LORAWAN_PRIVATE_NETWORK is not set
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_LORAWAN_NETWORK_ATTRIBUTE=1
+# CONFIG_LORAWAN_ED_STACK_CERTIFICATE_TEST_ENABLE is not set
+CONFIG_LORAWAN_ED_STACK_CERTIFICATE_TEST_DISABLE=y
+
+#
+# Select LoRaWAN-ED Mac Parameters
+#
+CONFIG_LORAWAN_ED_STACK_USING_DEVICE_TYPE_CLASS_A=y
+# CONFIG_LORAWAN_ED_STACK_USING_DEVICE_TYPE_CLASS_B is not set
+# CONFIG_LORAWAN_ED_STACK_USING_DEVICE_TYPE_CLASS_C is not set
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DEVICE_TYPE=0
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ACTIVATION_TYPE_OTAA=y
+# CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ACTIVATION_TYPE_ABP is not set
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ACTIVATION_TYPE=0
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DATA_MESSAGE_TYPE_UNCONFIRM=y
+# CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DATA_MESSAGE_TYPE_CONFIRM is not set
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DATA_MESSAGE_TYPE=0
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ADR_ON=y
+# CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ADR_OFF is not set
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_ADR=1
+# CONFIG_LORAWAN_MAC_COMMAND_DEVICE_TIME_ENABLE is not set
+CONFIG_LORAWAN_MAC_COMMAND_DEVICE_TIME_DISABLE=y
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_APPLICATION_FPORT=10
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_SYSTEM_MAX_RX_ERROR=10
+
+#
+# Redefine OTAA Device Authentication Infomation
+#
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DEVEUI_REDEFINE=y
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_DEVEUI="00956900000019FD"
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_JOINEUI_REDEFINE=y
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_JOINEUI="1122334455667780"
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_APPKEY_REDEFINE=y
+CONFIG_LORAWAN_ED_STACK_MAC_PARAMETER_APPKEY="00112233445566778899AABBCCDDEEFF"
+# end of Redefine OTAA Device Authentication Infomation
+# end of Select LoRaWAN-ED Mac Parameters
+
+#
+# Select LoRaWAN-ED Phy Parameters
+#
+# CONFIG_REGION_CN470 is not set
+CONFIG_REGION_CN470S=y
+# CONFIG_REGION_EU868 is not set
+# CONFIG_REGION_AS923 is not set
+# CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_0 is not set
+# CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_1 is not set
+# CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_2 is not set
+# CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_3 is not set
+# CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_4 is not set
+CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DR_5=y
+CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_DEFAULT_DATARATE=5
+CONFIG_LORAWAN_ED_STACK_PHY_PARAMETER_CHANNEL_MASK0="00FF"
+# end of Select LoRaWAN-ED Phy Parameters
+
+#
+# Select LoRaWAN-ED Debug
+#
+CONFIG_LORAWAN_ED_STACK_DEBUG=y
+# CONFIG_LORAWAN_ED_STACK_DEBUG_APP_CONFIG is not set
+# CONFIG_LORAWAN_ED_STACK_DEBUG_APP_DATA_CONFIG is not set
+CONFIG_LORAWAN_ED_STACK_DEBUG_APS_CONFIG=y
+CONFIG_LORAWAN_ED_STACK_DEBUG_APS=1
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC_CONFIG=y
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC=1
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC_RX_WIN_TIMESTAMP_CONFIG=y
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC_RX_WINDOW_TIMESTAMP=1
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC_COMMAND_CONFIG=y
+CONFIG_LORAWAN_ED_STACK_DEBUG_MAC_COMMAND=1
+CONFIG_LORAWAN_ED_STACK_DEBUG_PHY_REGION_CONFIG=y
+CONFIG_LORAWAN_ED_STACK_DEBUG_PHY_REGION=1
+# end of Select LoRaWAN-ED Debug
+
+#
+# Select LoRaWAN-ED-Stack Example
+#
+CONFIG_LORAWAN_ED_STACK_APP_SHELL_TEST=y
+
+#
+# Select End-Device Activation Type Support
+#
+CONFIG_LORAWAN_ED_STACK_USING_ACTIVATION_TYPE_OTAA=y
+CONFIG_LORAWAN_ED_STACK_USING_ACTIVATION_TYPE_ABP=y
+# end of Select End-Device Activation Type Support
+# end of Select LoRaWAN-ED-Stack Example
+
+# CONFIG_PKG_USING_LORAWAN_ED_STACK_V100 is not set
+CONFIG_PKG_USING_LORAWAN_ED_STACK_V103=y
+# CONFIG_PKG_USING_LORAWAN_ED_STACK_LATEST_VERSION is not set
+CONFIG_PKG_LORAWAN_ED_STACK_VER="v1.0.3"
+# CONFIG_PKG_USING_LORAGW_PKT_FWD is not set
+# end of IoT - internet of things
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+# end of security packages
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# end of language packages
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# end of multimedia packages
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# end of tools packages
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# end of Micrium: Micrium software products porting for RT-Thread
+
+# CONFIG_PKG_USING_PPOOL is not set
+# end of system packages
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+CONFIG_PKG_USING_LITTLED=y
+CONFIG_PKG_LITTLED_PATH="/packages/peripherals/littled"
+# CONFIG_PKG_USING_LITTLED_DEBUG is not set
+CONFIG_PKG_USING_LITTLED_PERIOD=1000
+CONFIG_PKG_USING_LITTLED_PULSE=500
+CONFIG_PKG_USING_LITTLED_BELL_TIME=50000
+CONFIG_PKG_USING_LITTLED_BEEP_COUNT=3
+# CONFIG_PKG_USING_LITTLED_SAMPLE is not set
+# CONFIG_PKG_USING_LITTLED_V020 is not set
+CONFIG_PKG_USING_LITTLED_LATEST_VERSION=y
+CONFIG_PKG_LITTLED_VER="latest"
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+CONFIG_PKG_USING_MULTI_RTIMER=y
+CONFIG_PKG_MULTI_RTIMER_PATH="/packages/peripherals/multi_rtimer"
+
+#
+# Select Target MCU and Peripheral
+#
+CONFIG_MULTI_RTIMER_USING_TRAGET_MCU_STM32_RTC=y
+# CONFIG_MULTI_RTIMER_USING_RTC_SYSTIME_SERVICE is not set
+# CONFIG_MULTI_RTIMER_USING_RTC_TEMPERTURE_COMPENSATION is not set
+# end of Select Target MCU and Peripheral
+
+# CONFIG_MULTI_RTIMER_USING_TEST_SAMPLE is not set
+# CONFIG_PKG_USING_MULTI_RTIMER_V100 is not set
+CONFIG_PKG_USING_MULTI_RTIMER_V110=y
+# CONFIG_PKG_USING_MULTI_RTIMER_LATEST_VERSION is not set
+CONFIG_PKG_MULTI_RTIMER_VER="v1.1.0"
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+CONFIG_PKG_USING_LORA_RADIO_DRIVER=y
+CONFIG_PKG_LORA_RADIO_DRIVER_PATH="/packages/peripherals/lora_radio_driver"
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP=y
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_SINGLE_INSTANCE=y
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_MULTI_INSTANCE is not set
+CONFIG_LORA_RADIO0_DEVICE_NAME="lora-radio0"
+CONFIG_LORA_RADIO0_SPI_BUS_NAME="spi4"
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP_SX126X=y
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_CHIP_SX127X is not set
+
+#
+# Select Supported LoRa Module [SX126X]
+#
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R717N40=y
+
+#
+# LoRa Chip SX1268 (SPI module)
+#
+CONFIG_LORA_RADIO_USE_TCXO=y
+CONFIG_LORA_RADIO_GPIO_SETUP=y
+
+#
+# Select Supported Target Borad
+#
+# CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_LSD4RF_TEST2002 is not set
+CONFIG_LORA_RADIO_SPI_SETUP=y
+# CONFIG_LORA_RADIO_GPIO_SETUP_BY_PIN_NAME is not set
+CONFIG_LORA_RADIO_GPIO_SETUP_BY_PIN_NUMBER=y
+CONFIG_LORA_RADIO_NSS_PIN=68
+CONFIG_LORA_RADIO_RESET_PIN=114
+CONFIG_LORA_RADIO_DIO1_PIN=16
+CONFIG_LORA_RADIO_DIO2_PIN=115
+CONFIG_LORA_RADIO_RFSW1_PIN=17
+CONFIG_LORA_RADIO_RFSW2_PIN=18
+CONFIG_LORA_RADIO_BUSY_PIN=6
+# CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_ART_PI_AND_LRS007_RF_A is not set
+CONFIG_LORA_RADIO_DRIVER_USING_TRAGET_BOARD_ART_PI_AND_LRS007_RF_B=y
+# end of Select Supported Target Borad
+
+# CONFIG_LORA_RADIO_DRIVER_USING_LORA_MODULE_LSD4RF_2R822N30 is not set
+# end of Select Supported LoRa Module [SX126X]
+
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_DEBUG=y
+# CONFIG_LR_DBG_APP_CONFIG is not set
+CONFIG_LR_DBG_INTERFACE_CONFIG=y
+CONFIG_LR_DBG_INTERFACE=1
+CONFIG_LR_DBG_CHIP_CONFIG=y
+CONFIG_LR_DBG_CHIP=1
+CONFIG_LR_DBG_SPI_CONFIG=y
+CONFIG_LR_DBG_SPI=1
+
+#
+# Select LoRa Radio Driver Example
+#
+CONFIG_LORA_RADIO_DRIVER_USING_LORA_RADIO_TEST_SHELL=y
+CONFIG_PHY_REGION_CN470=y
+# CONFIG_PHY_REGION_EU868 is not set
+# CONFIG_PHY_REGION_KR920 is not set
+CONFIG_USE_MODEM_LORA=y
+# CONFIG_USE_MODEM_FSK is not set
+# end of Select LoRa Radio Driver Example
+
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER_V100 is not set
+CONFIG_PKG_USING_LORA_RADIO_DRIVER_V130=y
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER_LATEST_VERSION is not set
+CONFIG_PKG_LORA_RADIO_DRIVER_VER="v1.3.0"
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_LORAGW_LIB_SX1302 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_NES is not set
+# end of peripheral libraries and drivers
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# end of samples: kernel and components samples
+
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+
+#
+# games: games run on RT-Thread console
+#
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# end of games: games run on RT-Thread console
+
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# end of miscellaneous packages
+# end of RT-Thread online packages
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_STM32H750XB=y
+CONFIG_SOC_SERIES_STM32H7=y
+
+#
+# Board extended module
+#
+# CONFIG_ART_PI_USING_MEDIA_IO is not set
+# CONFIG_ART_PI_USING_INDUSTRY_IO is not set
+# CONFIG_ART_PI_USING_LORA_SHIELD_LRS007 is not set
+# end of Board extended module
+
+#
+# Onboard Peripheral
+#
+CONFIG_BSP_USING_USB_TO_USART=y
+# CONFIG_BSP_USING_SPI_FLASH is not set
+# CONFIG_BSP_USING_WIFI is not set
+# CONFIG_BSP_USING_OV2640 is not set
+# CONFIG_BSP_USING_FS is not set
+# end of Onboard Peripheral
+
+#
+# On-chip Peripheral
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+# CONFIG_BSP_USING_UART6 is not set
+CONFIG_BSP_USING_SPI=y
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_SPI2 is not set
+CONFIG_BSP_USING_SPI4=y
+# CONFIG_BSP_USING_I2C is not set
+# CONFIG_BSP_USING_SDIO is not set
+# CONFIG_BSP_USING_SDRAM is not set
+# CONFIG_BSP_USING_ETH is not set
+# CONFIG_BSP_USING_LCD is not set
+# CONFIG_BSP_USING_DCMI is not set
+# CONFIG_BSP_USING_FDCAN is not set
+# CONFIG_BSP_USING_USBD is not set
+# CONFIG_BSP_USING_USBH is not set
+# CONFIG_BSP_USING_TIM is not set
+CONFIG_BSP_USING_ONCHIP_RTC=y
+# end of On-chip Peripheral
+# end of Hardware Drivers Config
+
+#
+# External Libraries
+#
+# CONFIG_ART_PI_USING_WIFI_6212_LIB is not set
+# CONFIG_ART_PI_USING_OTA_LIB is not set
+# CONFIG_ART_PI_TouchGFX_LIB is not set
+# CONFIG_ART_PI_USING_FTP_LIB is not set
+# end of External Libraries
+
+CONFIG_RT_STUDIO_BUILT_IN=y

projects/lrs007_lorawan_end_device/.gitattributes

@@ -0,0 +1,36 @@
+# Sources
+*.c     text diff=c
+*.cc    text diff=cpp
+*.cxx   text diff=cpp
+*.cpp   text diff=cpp
+*.c++   text diff=cpp
+*.hpp   text diff=cpp
+*.h     text diff=c
+*.h++   text diff=cpp
+*.hh    text diff=cpp
+
+# Compiled Object files
+*.slo   binary
+*.lo    binary
+*.o     binary
+*.obj   binary
+
+# Precompiled Headers
+*.gch   binary
+*.pch   binary
+
+# Compiled Dynamic libraries
+*.so    binary
+*.dylib binary
+*.dll   binary
+
+# Compiled Static libraries
+*.lai   binary
+*.la    binary
+*.a     binary
+*.lib   binary
+
+# Executables
+*.exe   binary
+*.out   binary
+*.app   binary

projects/lrs007_lorawan_end_device/.gitignore

@@ -0,0 +1,37 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.pdb
+*.idb
+*.ilk
+!*.old
+build
+Debug
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*

projects/lrs007_lorawan_end_device/.project

@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+  <name>lrs007_lorawan_end_device</name>
+  <comment />
+  <projects>
+	</projects>
+  <buildSpec>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+      <triggers>clean,full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+    <buildCommand>
+      <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+      <triggers>full,incremental,</triggers>
+      <arguments>
+			</arguments>
+    </buildCommand>
+  </buildSpec>
+  <natures>
+    <nature>org.eclipse.cdt.core.cnature</nature>
+    <nature>org.rt-thread.studio.rttnature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+    <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+  </natures>
+  <linkedResources />
+</projectDescription>

projects/lrs007_lorawan_end_device/.settings/lrs007_lorawan_end_device.STLink.Debug.rttlaunch

@@ -0,0 +1,60 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="org.rtthread.studio.debug.gdbjtag.stlink.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${rtt_install_path}\repo\Extract\Chip_Support_Packages\RealThread\STM32H7\0.1.9\debug\svd\STM32H750x.svd"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.connectMode" value="NORMAL"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.debugInterface" value="SWD"/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="3"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.erase" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.externalLoader" value="${workspace_loc:/${ProjName}/board/stldr/ART-Pi_W25Q64.stldr}"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.externalLoaderButton" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.flashVerify" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.isUseInternal" value="false"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="org.eclipse.cdt.debug.gdbjtag.core.jtagdevice.genericDevice"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherDownloadOption" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.otherGdbserverOption" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61235"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetMode" value=" -hardRst"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.resetRun" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
+<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
+<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
+<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${external_gdb_tool}/arm-none-eabi-gdb.exe"/>
+<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="0"/>
+<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="lrs007_lorawan_end_device"/>
+<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
+<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/lrs007_lorawan_end_device"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="org.eclipse.cdt.debug.core.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#13;&#10;&lt;sourceLookupDirector&gt;&#13;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#13;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#13;&amp;#10;&amp;lt;default/&amp;gt;&amp;#13;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#13;&#10;&lt;/sourceContainers&gt;&#13;&#10;&lt;/sourceLookupDirector&gt;&#13;&#10;"/>
+<stringAttribute key="org.eclipse.debug.ui.ATTR_CONSOLE_ENCODING" value="UTF-8"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.adapterName" value="ST-LINK"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerDeviceName" value="STM32H750XB"/>
+<stringAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.gdbServerExecutable" value="${rtt_install_path}/repo/Extract/Debugger_Support_Packages/STMicroelectronics/ST-LINK_Debugger/1.2.0/ST-LINK_gdbserver.exe"/>
+<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.useRemoteTarget" value="true"/>
+<booleanAttribute key="org.rtthread.studio.debug.gdbjtag.stlink.doContinue" value="true"/>
+</launchConfiguration>

projects/lrs007_lorawan_end_device/.settings/org.eclipse.core.runtime.prefs

@@ -0,0 +1,3 @@
+content-types/enabled=true
+content-types/org.eclipse.cdt.core.asmSource/file-extensions=s
+eclipse.preferences.version=1

projects/lrs007_lorawan_end_device/.settings/projcfg.ini

@@ -0,0 +1,19 @@
+#RT-Thread Studio Project Configuration
+#Sat Dec 12 13:13:11 CST 2020
+cfg_version=v3.0
+board_name=STM32H750-RT-ART-Pi
+example_name=art_pi_blink_led
+hardware_adapter=ST-LINK
+project_type=rt-thread
+board_base_nano_proj=False
+chip_name=STM32H750XBHx
+selected_rtt_version=4.0.3
+bsp_version=1.1.0
+os_branch=full
+output_project_path=F\:/K-Forest/RTOS/RT-Thread/artpi-master/sdk-artpi-pr/sdk-bsp-stm32h750-realthread-artpi/projects
+is_base_example_project=True
+is_use_scons_build=True
+project_base_bsp=true
+project_name=lrs007_lorawan_end_device
+os_version=4.0.3
+bsp_path=repo/Extract/Board_Support_Packages/RealThread/STM32H750-RT-ART-Pi/1.1.0