drv_hwtimer.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612
  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-10 zylx first version
  9. * 2020-06-16 thread-liu Porting for stm32mp1
  10. * 2020-08-25 linyongkang Fix the timer clock frequency doubling problem
  11. */
  12. #include <board.h>
  13. #include <rtthread.h>
  14. #include <rtdevice.h>
  15. #ifdef BSP_USING_TIM
  16. #include "drv_config.h"
  17. //#define DRV_DEBUG
  18. #define LOG_TAG "drv.hwtimer"
  19. #include <drv_log.h>
  20. #ifdef RT_USING_HWTIMER
  21. enum
  22. {
  23. #ifdef BSP_USING_TIM1
  24. TIM1_INDEX,
  25. #endif
  26. #ifdef BSP_USING_TIM2
  27. TIM2_INDEX,
  28. #endif
  29. #ifdef BSP_USING_TIM3
  30. TIM3_INDEX,
  31. #endif
  32. #ifdef BSP_USING_TIM4
  33. TIM4_INDEX,
  34. #endif
  35. #ifdef BSP_USING_TIM5
  36. TIM5_INDEX,
  37. #endif
  38. #ifdef BSP_USING_TIM6
  39. TIM6_INDEX,
  40. #endif
  41. #ifdef BSP_USING_TIM7
  42. TIM7_INDEX,
  43. #endif
  44. #ifdef BSP_USING_TIM8
  45. TIM8_INDEX,
  46. #endif
  47. #ifdef BSP_USING_TIM9
  48. TIM9_INDEX,
  49. #endif
  50. #ifdef BSP_USING_TIM10
  51. TIM10_INDEX,
  52. #endif
  53. #ifdef BSP_USING_TIM11
  54. TIM11_INDEX,
  55. #endif
  56. #ifdef BSP_USING_TIM12
  57. TIM12_INDEX,
  58. #endif
  59. #ifdef BSP_USING_TIM13
  60. TIM13_INDEX,
  61. #endif
  62. #ifdef BSP_USING_TIM14
  63. TIM14_INDEX,
  64. #endif
  65. #ifdef BSP_USING_TIM15
  66. TIM15_INDEX,
  67. #endif
  68. #ifdef BSP_USING_TIM16
  69. TIM16_INDEX,
  70. #endif
  71. #ifdef BSP_USING_TIM17
  72. TIM17_INDEX,
  73. #endif
  74. };
  75. struct stm32_hwtimer
  76. {
  77. rt_hwtimer_t time_device;
  78. TIM_HandleTypeDef tim_handle;
  79. IRQn_Type tim_irqn;
  80. char *name;
  81. };
  82. static struct stm32_hwtimer stm32_hwtimer_obj[] =
  83. {
  84. #ifdef BSP_USING_TIM1
  85. TIM1_CONFIG,
  86. #endif
  87. #ifdef BSP_USING_TIM2
  88. TIM2_CONFIG,
  89. #endif
  90. #ifdef BSP_USING_TIM3
  91. TIM3_CONFIG,
  92. #endif
  93. #ifdef BSP_USING_TIM4
  94. TIM4_CONFIG,
  95. #endif
  96. #ifdef BSP_USING_TIM5
  97. TIM5_CONFIG,
  98. #endif
  99. #ifdef BSP_USING_TIM6
  100. TIM6_CONFIG,
  101. #endif
  102. #ifdef BSP_USING_TIM7
  103. TIM7_CONFIG,
  104. #endif
  105. #ifdef BSP_USING_TIM8
  106. TIM8_CONFIG,
  107. #endif
  108. #ifdef BSP_USING_TIM9
  109. TIM9_CONFIG,
  110. #endif
  111. #ifdef BSP_USING_TIM10
  112. TIM10_CONFIG,
  113. #endif
  114. #ifdef BSP_USING_TIM11
  115. TIM11_CONFIG,
  116. #endif
  117. #ifdef BSP_USING_TIM12
  118. TIM12_CONFIG,
  119. #endif
  120. #ifdef BSP_USING_TIM13
  121. TIM13_CONFIG,
  122. #endif
  123. #ifdef BSP_USING_TIM14
  124. TIM14_CONFIG,
  125. #endif
  126. #ifdef BSP_USING_TIM15
  127. TIM15_CONFIG,
  128. #endif
  129. #ifdef BSP_USING_TIM16
  130. TIM16_CONFIG,
  131. #endif
  132. #ifdef BSP_USING_TIM17
  133. TIM17_CONFIG,
  134. #endif
  135. };
  136. /* APBx timer clocks frequency doubler state related to APB1CLKDivider value */
  137. static void pclkx_doubler_get(uint32_t *pclk1_doubler, uint32_t *pclk2_doubler)
  138. {
  139. uint32_t flatency = 0;
  140. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  141. RT_ASSERT(pclk1_doubler != RT_NULL);
  142. RT_ASSERT(pclk1_doubler != RT_NULL);
  143. HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &flatency);
  144. *pclk1_doubler = 1;
  145. *pclk2_doubler = 1;
  146. #if defined(SOC_SERIES_STM32MP1)
  147. if (RCC_ClkInitStruct.APB1_Div != RCC_APB1_DIV1)
  148. {
  149. *pclk1_doubler = 2;
  150. }
  151. if (RCC_ClkInitStruct.APB2_Div != RCC_APB2_DIV1)
  152. {
  153. *pclk2_doubler = 2;
  154. }
  155. #elif defined(SOC_SERIES_STM32H7)
  156. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_APB1_DIV1)
  157. {
  158. *pclk1_doubler = 2;
  159. }
  160. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_APB2_DIV1)
  161. {
  162. *pclk2_doubler = 2;
  163. }
  164. #else
  165. if (RCC_ClkInitStruct.APB1CLKDivider != RCC_HCLK_DIV1)
  166. {
  167. *pclk1_doubler = 2;
  168. }
  169. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  170. if (RCC_ClkInitStruct.APB2CLKDivider != RCC_HCLK_DIV1)
  171. {
  172. *pclk2_doubler = 2;
  173. }
  174. #endif
  175. #endif
  176. }
  177. static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
  178. {
  179. uint32_t prescaler_value = 0;
  180. uint32_t pclk1_doubler, pclk2_doubler;
  181. TIM_HandleTypeDef *tim = RT_NULL;
  182. struct stm32_hwtimer *tim_device = RT_NULL;
  183. RT_ASSERT(timer != RT_NULL);
  184. if (state)
  185. {
  186. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  187. tim_device = (struct stm32_hwtimer *)timer;
  188. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  189. /* time init */
  190. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  191. if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
  192. #elif defined(SOC_SERIES_STM32L4)
  193. if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
  194. #elif defined(SOC_SERIES_STM32MP1)
  195. if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
  196. #elif defined(SOC_SERIES_STM32H7)
  197. if (tim->Instance == TIM13 || tim->Instance == TIM14)
  198. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  199. if (0)
  200. #endif
  201. {
  202. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0) && !defined(SOC_SERIES_STM32H7)
  203. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK2Freq() * pclk2_doubler / 10000) - 1;
  204. #endif
  205. }
  206. else
  207. {
  208. prescaler_value = (uint32_t)(HAL_RCC_GetPCLK1Freq() * pclk1_doubler / 10000) - 1;
  209. }
  210. tim->Init.Period = 10000 - 1;
  211. tim->Init.Prescaler = prescaler_value;
  212. tim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
  213. if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
  214. {
  215. tim->Init.CounterMode = TIM_COUNTERMODE_UP;
  216. }
  217. else
  218. {
  219. tim->Init.CounterMode = TIM_COUNTERMODE_DOWN;
  220. }
  221. tim->Init.RepetitionCounter = 0;
  222. #if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0) || \
  223. defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  224. tim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
  225. #endif
  226. if (HAL_TIM_Base_Init(tim) != HAL_OK)
  227. {
  228. LOG_E("%s init failed", tim_device->name);
  229. return;
  230. }
  231. else
  232. {
  233. /* set the TIMx priority */
  234. HAL_NVIC_SetPriority(tim_device->tim_irqn, 3, 0);
  235. /* enable the TIMx global Interrupt */
  236. HAL_NVIC_EnableIRQ(tim_device->tim_irqn);
  237. /* clear update flag */
  238. __HAL_TIM_CLEAR_FLAG(tim, TIM_FLAG_UPDATE);
  239. /* enable update request source */
  240. __HAL_TIM_URS_ENABLE(tim);
  241. LOG_D("%s init success", tim_device->name);
  242. }
  243. }
  244. }
  245. static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
  246. {
  247. rt_err_t result = RT_EOK;
  248. TIM_HandleTypeDef *tim = RT_NULL;
  249. RT_ASSERT(timer != RT_NULL);
  250. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  251. /* set tim cnt */
  252. __HAL_TIM_SET_COUNTER(tim, 0);
  253. /* set tim arr */
  254. __HAL_TIM_SET_AUTORELOAD(tim, t - 1);
  255. if (opmode == HWTIMER_MODE_ONESHOT)
  256. {
  257. /* set timer to single mode */
  258. tim->Instance->CR1 |= TIM_OPMODE_SINGLE;
  259. }
  260. else
  261. {
  262. tim->Instance->CR1 &= (~TIM_OPMODE_SINGLE);
  263. }
  264. /* start timer */
  265. if (HAL_TIM_Base_Start_IT(tim) != HAL_OK)
  266. {
  267. LOG_E("TIM start failed");
  268. result = -RT_ERROR;
  269. }
  270. return result;
  271. }
  272. static void timer_stop(rt_hwtimer_t *timer)
  273. {
  274. TIM_HandleTypeDef *tim = RT_NULL;
  275. RT_ASSERT(timer != RT_NULL);
  276. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  277. /* stop timer */
  278. HAL_TIM_Base_Stop_IT(tim);
  279. /* set tim cnt */
  280. __HAL_TIM_SET_COUNTER(tim, 0);
  281. }
  282. static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
  283. {
  284. TIM_HandleTypeDef *tim = RT_NULL;
  285. rt_err_t result = RT_EOK;
  286. uint32_t pclk1_doubler, pclk2_doubler;
  287. RT_ASSERT(timer != RT_NULL);
  288. RT_ASSERT(arg != RT_NULL);
  289. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  290. switch (cmd)
  291. {
  292. case HWTIMER_CTRL_FREQ_SET:
  293. {
  294. rt_uint32_t freq;
  295. rt_uint16_t val;
  296. /* set timer frequence */
  297. freq = *((rt_uint32_t *)arg);
  298. pclkx_doubler_get(&pclk1_doubler, &pclk2_doubler);
  299. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  300. if (tim->Instance == TIM9 || tim->Instance == TIM10 || tim->Instance == TIM11)
  301. #elif defined(SOC_SERIES_STM32L4)
  302. if (tim->Instance == TIM15 || tim->Instance == TIM16 || tim->Instance == TIM17)
  303. #elif defined(SOC_SERIES_STM32MP1)
  304. if(tim->Instance == TIM14 || tim->Instance == TIM16 || tim->Instance == TIM17)
  305. #elif defined(SOC_SERIES_STM32H7)
  306. if (tim->Instance == TIM13 || tim->Instance == TIM14)
  307. #elif defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32G0)
  308. if (0)
  309. #endif
  310. {
  311. #if !defined(SOC_SERIES_STM32F0) && !defined(SOC_SERIES_STM32G0)
  312. val = HAL_RCC_GetPCLK2Freq() * pclk2_doubler / freq;
  313. #endif
  314. }
  315. else
  316. {
  317. val = HAL_RCC_GetPCLK1Freq() * pclk1_doubler / freq;
  318. }
  319. __HAL_TIM_SET_PRESCALER(tim, val - 1);
  320. /* Update frequency value */
  321. tim->Instance->EGR |= TIM_EVENTSOURCE_UPDATE;
  322. }
  323. break;
  324. default:
  325. {
  326. result = -RT_ENOSYS;
  327. }
  328. break;
  329. }
  330. return result;
  331. }
  332. static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
  333. {
  334. TIM_HandleTypeDef *tim = RT_NULL;
  335. RT_ASSERT(timer != RT_NULL);
  336. tim = (TIM_HandleTypeDef *)timer->parent.user_data;
  337. return tim->Instance->CNT;
  338. }
  339. static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
  340. static const struct rt_hwtimer_ops _ops =
  341. {
  342. .init = timer_init,
  343. .start = timer_start,
  344. .stop = timer_stop,
  345. .count_get = timer_counter_get,
  346. .control = timer_ctrl,
  347. };
  348. #ifdef BSP_USING_TIM2
  349. void TIM2_IRQHandler(void)
  350. {
  351. /* enter interrupt */
  352. rt_interrupt_enter();
  353. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM2_INDEX].tim_handle);
  354. /* leave interrupt */
  355. rt_interrupt_leave();
  356. }
  357. #endif
  358. #ifdef BSP_USING_TIM3
  359. void TIM3_IRQHandler(void)
  360. {
  361. /* enter interrupt */
  362. rt_interrupt_enter();
  363. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM3_INDEX].tim_handle);
  364. /* leave interrupt */
  365. rt_interrupt_leave();
  366. }
  367. #endif
  368. #ifdef BSP_USING_TIM4
  369. void TIM4_IRQHandler(void)
  370. {
  371. /* enter interrupt */
  372. rt_interrupt_enter();
  373. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM4_INDEX].tim_handle);
  374. /* leave interrupt */
  375. rt_interrupt_leave();
  376. }
  377. #endif
  378. #ifdef BSP_USING_TIM5
  379. void TIM5_IRQHandler(void)
  380. {
  381. /* enter interrupt */
  382. rt_interrupt_enter();
  383. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM5_INDEX].tim_handle);
  384. /* leave interrupt */
  385. rt_interrupt_leave();
  386. }
  387. #endif
  388. #ifdef BSP_USING_TIM11
  389. void TIM1_TRG_COM_TIM11_IRQHandler(void)
  390. {
  391. /* enter interrupt */
  392. rt_interrupt_enter();
  393. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM11_INDEX].tim_handle);
  394. /* leave interrupt */
  395. rt_interrupt_leave();
  396. }
  397. #endif
  398. #ifdef BSP_USING_TIM13
  399. void TIM8_UP_TIM13_IRQHandler(void)
  400. {
  401. /* enter interrupt */
  402. rt_interrupt_enter();
  403. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM13_INDEX].tim_handle);
  404. /* leave interrupt */
  405. rt_interrupt_leave();
  406. }
  407. #endif
  408. #ifdef BSP_USING_TIM14
  409. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  410. void TIM8_TRG_COM_TIM14_IRQHandler(void)
  411. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  412. void TIM14_IRQHandler(void)
  413. #endif
  414. {
  415. /* enter interrupt */
  416. rt_interrupt_enter();
  417. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM14_INDEX].tim_handle);
  418. /* leave interrupt */
  419. rt_interrupt_leave();
  420. }
  421. #endif
  422. #ifdef BSP_USING_TIM15
  423. void TIM1_BRK_TIM15_IRQHandler(void)
  424. {
  425. /* enter interrupt */
  426. rt_interrupt_enter();
  427. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM15_INDEX].tim_handle);
  428. /* leave interrupt */
  429. rt_interrupt_leave();
  430. }
  431. #endif
  432. #ifdef BSP_USING_TIM16
  433. #if defined(SOC_SERIES_STM32L4)
  434. void TIM1_UP_TIM16_IRQHandler(void)
  435. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  436. void TIM16_IRQHandler(void)
  437. #endif
  438. {
  439. /* enter interrupt */
  440. rt_interrupt_enter();
  441. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM16_INDEX].tim_handle);
  442. /* leave interrupt */
  443. rt_interrupt_leave();
  444. }
  445. #endif
  446. #ifdef BSP_USING_TIM17
  447. #if defined(SOC_SERIES_STM32L4)
  448. void TIM1_TRG_COM_TIM17_IRQHandler(void)
  449. #elif defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32MP1)
  450. void TIM17_IRQHandler(void)
  451. #endif
  452. {
  453. /* enter interrupt */
  454. rt_interrupt_enter();
  455. HAL_TIM_IRQHandler(&stm32_hwtimer_obj[TIM17_INDEX].tim_handle);
  456. /* leave interrupt */
  457. rt_interrupt_leave();
  458. }
  459. #endif
  460. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
  461. {
  462. #ifdef BSP_USING_TIM2
  463. if (htim->Instance == TIM2)
  464. {
  465. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM2_INDEX].time_device);
  466. }
  467. #endif
  468. #ifdef BSP_USING_TIM3
  469. if (htim->Instance == TIM3)
  470. {
  471. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM3_INDEX].time_device);
  472. }
  473. #endif
  474. #ifdef BSP_USING_TIM4
  475. if (htim->Instance == TIM4)
  476. {
  477. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM4_INDEX].time_device);
  478. }
  479. #endif
  480. #ifdef BSP_USING_TIM5
  481. if (htim->Instance == TIM5)
  482. {
  483. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM5_INDEX].time_device);
  484. }
  485. #endif
  486. #ifdef BSP_USING_TIM11
  487. if (htim->Instance == TIM11)
  488. {
  489. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM11_INDEX].time_device);
  490. }
  491. #endif
  492. #ifdef BSP_USING_TIM13
  493. if (htim->Instance == TIM13)
  494. {
  495. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM13_INDEX].time_device);
  496. }
  497. #endif
  498. #ifdef BSP_USING_TIM14
  499. if (htim->Instance == TIM14)
  500. {
  501. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM14_INDEX].time_device);
  502. }
  503. #endif
  504. #ifdef BSP_USING_TIM15
  505. if (htim->Instance == TIM15)
  506. {
  507. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM15_INDEX].time_device);
  508. }
  509. #endif
  510. #ifdef BSP_USING_TIM16
  511. if (htim->Instance == TIM16)
  512. {
  513. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM16_INDEX].time_device);
  514. }
  515. #endif
  516. #ifdef BSP_USING_TIM17
  517. if (htim->Instance == TIM17)
  518. {
  519. rt_device_hwtimer_isr(&stm32_hwtimer_obj[TIM17_INDEX].time_device);
  520. }
  521. #endif
  522. }
  523. static int stm32_hwtimer_init(void)
  524. {
  525. int i = 0;
  526. int result = RT_EOK;
  527. for (i = 0; i < sizeof(stm32_hwtimer_obj) / sizeof(stm32_hwtimer_obj[0]); i++)
  528. {
  529. stm32_hwtimer_obj[i].time_device.info = &_info;
  530. stm32_hwtimer_obj[i].time_device.ops = &_ops;
  531. if (rt_device_hwtimer_register(&stm32_hwtimer_obj[i].time_device, stm32_hwtimer_obj[i].name, &stm32_hwtimer_obj[i].tim_handle) == RT_EOK)
  532. {
  533. LOG_D("%s register success", stm32_hwtimer_obj[i].name);
  534. }
  535. else
  536. {
  537. LOG_E("%s register failed", stm32_hwtimer_obj[i].name);
  538. result = -RT_ERROR;
  539. }
  540. }
  541. return result;
  542. }
  543. INIT_BOARD_EXPORT(stm32_hwtimer_init);
  544. #endif /* RT_USING_HWTIMER */
  545. #endif /* BSP_USING_TIM */