RealThread_GD32F5.yaml 9.8 KB

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  1. vendor: RealThread
  2. dvendor: GigaDevice
  3. name: GD32F5
  4. version: 2.0.0
  5. yaml_version: 1
  6. type: Chip_Support_Packages
  7. family_name: GD32
  8. series:
  9. description: "GigaDevice's GD32F5 series of ARM Cortex-M33 MCUs with TrustZone and\
  10. \ enhanced performance.\n\n - Up to 120MHz CPU frequency\n - ARM TrustZone-M\
  11. \ security\n - DSP instructions\n - Enhanced connectivity\n - Dual memory architecture\
  12. \ (RAM + TCMRAM)"
  13. series_name: GD32F5
  14. peripheral: {}
  15. sub_series:
  16. - sub_series_name: GD32F527
  17. cpu_info:
  18. max_clock: '120000000'
  19. chips:
  20. - chip_name: GD32F527ZM
  21. peripheral: {}
  22. memory:
  23. - id: IROM1
  24. start: '0x8000000'
  25. size: '0x400000'
  26. default: '1'
  27. - id: IRAM1
  28. start: '0x20000000'
  29. size: '0x100000'
  30. init: '0'
  31. default: '1'
  32. - id: IRAM2
  33. start: '0x10000000'
  34. size: '0x10000'
  35. init: '0'
  36. default: '0'
  37. compiler:
  38. gcc:
  39. entry_point: Reset_Handler
  40. link_script: linkscripts/GD32F527ZM/link.ld
  41. marco:
  42. - GD32F527
  43. files:
  44. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  45. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  46. armcc:
  47. entry_point: none
  48. link_script: none
  49. marco: []
  50. files: []
  51. iarcc:
  52. entry_point: none
  53. link_script: none
  54. marco: []
  55. files: []
  56. - chip_name: GD32F527ZS
  57. peripheral: {}
  58. memory:
  59. - id: IROM1
  60. start: '0x8000000'
  61. size: '0x780000'
  62. default: '1'
  63. - id: IRAM1
  64. start: '0x20000000'
  65. size: '0x80000'
  66. init: '0'
  67. default: '1'
  68. - id: IRAM2
  69. start: '0x10000000'
  70. size: '0x10000'
  71. init: '0'
  72. default: '0'
  73. compiler:
  74. gcc:
  75. entry_point: Reset_Handler
  76. link_script: linkscripts/GD32F527ZS/link.ld
  77. marco:
  78. - GD32F527
  79. files:
  80. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  81. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  82. armcc:
  83. entry_point: none
  84. link_script: none
  85. marco: []
  86. files: []
  87. iarcc:
  88. entry_point: none
  89. link_script: none
  90. marco: []
  91. files: []
  92. - chip_name: GD32F527VM
  93. peripheral: {}
  94. memory:
  95. - id: IROM1
  96. start: '0x8000000'
  97. size: '0x400000'
  98. default: '1'
  99. - id: IRAM1
  100. start: '0x20000000'
  101. size: '0x100000'
  102. init: '0'
  103. default: '1'
  104. - id: IRAM2
  105. start: '0x10000000'
  106. size: '0x10000'
  107. init: '0'
  108. default: '0'
  109. compiler:
  110. gcc:
  111. entry_point: Reset_Handler
  112. link_script: linkscripts/GD32F527VM/link.ld
  113. marco:
  114. - GD32F527
  115. files:
  116. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  117. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  118. armcc:
  119. entry_point: none
  120. link_script: none
  121. marco: []
  122. files: []
  123. iarcc:
  124. entry_point: none
  125. link_script: none
  126. marco: []
  127. files: []
  128. - chip_name: GD32F527VS
  129. peripheral: {}
  130. memory:
  131. - id: IROM1
  132. start: '0x8000000'
  133. size: '0x780000'
  134. default: '1'
  135. - id: IRAM1
  136. start: '0x20000000'
  137. size: '0x80000'
  138. init: '0'
  139. default: '1'
  140. - id: IRAM2
  141. start: '0x10000000'
  142. size: '0x10000'
  143. init: '0'
  144. default: '0'
  145. compiler:
  146. gcc:
  147. entry_point: Reset_Handler
  148. link_script: linkscripts/GD32F527VS/link.ld
  149. marco:
  150. - GD32F527
  151. files:
  152. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  153. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  154. armcc:
  155. entry_point: none
  156. link_script: none
  157. marco: []
  158. files: []
  159. iarcc:
  160. entry_point: none
  161. link_script: none
  162. marco: []
  163. files: []
  164. - chip_name: GD32F527RM
  165. peripheral: {}
  166. memory:
  167. - id: IROM1
  168. start: '0x8000000'
  169. size: '0x400000'
  170. default: '1'
  171. - id: IRAM1
  172. start: '0x20000000'
  173. size: '0x100000'
  174. init: '0'
  175. default: '1'
  176. - id: IRAM2
  177. start: '0x10000000'
  178. size: '0x10000'
  179. init: '0'
  180. default: '0'
  181. compiler:
  182. gcc:
  183. entry_point: Reset_Handler
  184. link_script: linkscripts/GD32F527RM/link.ld
  185. marco:
  186. - GD32F527
  187. files:
  188. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  189. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  190. armcc:
  191. entry_point: none
  192. link_script: none
  193. marco: []
  194. files: []
  195. iarcc:
  196. entry_point: none
  197. link_script: none
  198. marco: []
  199. files: []
  200. - chip_name: GD32F527RS
  201. peripheral: {}
  202. memory:
  203. - id: IROM1
  204. start: '0x8000000'
  205. size: '0x780000'
  206. default: '1'
  207. - id: IRAM1
  208. start: '0x20000000'
  209. size: '0x80000'
  210. init: '0'
  211. default: '1'
  212. - id: IRAM2
  213. start: '0x10000000'
  214. size: '0x10000'
  215. init: '0'
  216. default: '0'
  217. compiler:
  218. gcc:
  219. entry_point: Reset_Handler
  220. link_script: linkscripts/GD32F527RS/link.ld
  221. marco:
  222. - GD32F527
  223. files:
  224. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  225. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  226. armcc:
  227. entry_point: none
  228. link_script: none
  229. marco: []
  230. files: []
  231. iarcc:
  232. entry_point: none
  233. link_script: none
  234. marco: []
  235. files: []
  236. - chip_name: GD32F527IM
  237. peripheral: {}
  238. memory:
  239. - id: IROM1
  240. start: '0x8000000'
  241. size: '0x400000'
  242. default: '1'
  243. - id: IRAM1
  244. start: '0x20000000'
  245. size: '0x100000'
  246. init: '0'
  247. default: '1'
  248. - id: IRAM2
  249. start: '0x10000000'
  250. size: '0x10000'
  251. init: '0'
  252. default: '0'
  253. compiler:
  254. gcc:
  255. entry_point: Reset_Handler
  256. link_script: linkscripts/GD32F527IM/link.ld
  257. marco:
  258. - GD32F527
  259. files:
  260. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  261. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  262. armcc:
  263. entry_point: none
  264. link_script: none
  265. marco: []
  266. files: []
  267. iarcc:
  268. entry_point: none
  269. link_script: none
  270. marco: []
  271. files: []
  272. - chip_name: GD32F527IS
  273. peripheral: {}
  274. memory:
  275. - id: IROM1
  276. start: '0x8000000'
  277. size: '0x780000'
  278. default: '1'
  279. - id: IRAM1
  280. start: '0x20000000'
  281. size: '0x80000'
  282. init: '0'
  283. default: '1'
  284. - id: IRAM2
  285. start: '0x10000000'
  286. size: '0x10000'
  287. init: '0'
  288. default: '0'
  289. compiler:
  290. gcc:
  291. entry_point: Reset_Handler
  292. link_script: linkscripts/GD32F527IS/link.ld
  293. marco:
  294. - GD32F527
  295. files:
  296. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  297. - libraries/CMSIS/GD/GD32F527/Source/GCC/startup_gd32f5xx.S
  298. armcc:
  299. entry_point: none
  300. link_script: none
  301. marco: []
  302. files: []
  303. iarcc:
  304. entry_point: none
  305. link_script: none
  306. marco: []
  307. files: []
  308. ui:
  309. uart:
  310. default_value: UART0
  311. prompt_message_en: select one uart as console output interface
  312. prompt_message_zh: 选择一个串口作为控制台信息输出接口
  313. tx_pin:
  314. default_value: PA9
  315. prompt_message_en: 'set the tx pin name of the console device interface, the
  316. value should be with a format"P+[port name][pin number]",eg. PA2,PB6 '
  317. prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式"P+[端口名称][端口编号]", 比如:PA2,
  318. PB6
  319. rx_pin:
  320. default_value: PA10
  321. prompt_message_en: 'set the rx pin name of the console device interface, the
  322. value should be with a format"P+[port name][pin number]", eg. PA3, PB7 '
  323. prompt_message_zh: 设置控制台设备的数据发送引脚的名称,名称应该具有以下格式"P+[端口名称][端口编号]", 比如:PA2, PB6
  324. docs:
  325. - file: documents/GD32F527xx Datasheet_Rev1.6.pdf
  326. title: Gd32F527Xx Datasheet Rev1.6
  327. svd:
  328. file: debug/svd/GD32F527.svd
  329. project_type:
  330. bare_metal:
  331. function_map:
  332. clk_init: none
  333. sysTick: none
  334. marco:
  335. - SOC_FAMILY_GD32
  336. - SOC_SERIES_GD32F5xx
  337. source_files:
  338. - drivers/baremetal
  339. rtt_nano:
  340. function_map:
  341. clk_init: none
  342. heap_init: none
  343. marco:
  344. - SOC_FAMILY_GD32
  345. - SOC_SERIES_GD32F5xx
  346. source_files:
  347. - drivers/nano
  348. rtt:
  349. function_map:
  350. rt_hw_board_init: none
  351. heap_init: none
  352. marco:
  353. - SOC_FAMILY_GD32
  354. - SOC_SERIES_GD32F5xx
  355. source_files:
  356. - drivers/rtt
  357. source_files:
  358. file:
  359. - libraries/GD32F527_standard_peripheral
  360. - libraries/CMSIS/GD/GD32F527/Include/system_gd32f527.h
  361. - libraries/CMSIS/GD/GD32F527/Include/gd32f527.h
  362. - libraries/CMSIS/GD/GD32F527/Source/system_gd32f527.c
  363. - libraries/CMSIS/GD/GD32F527/Include/gd32f527_libopt.h
  364. - libraries/CMSIS/core_cm33.h
  365. - libraries/CMSIS/cmsis_compiler.h
  366. - libraries/CMSIS/cmsis_version.h
  367. - libraries/CMSIS/cmsis_gcc.h
  368. cpu_info:
  369. core: Cortex-M33
  370. fpu: '1'
  371. mpu: '1'
  372. endian: Little-endian