STM32L052x.svd 611 KB

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  1. <?xml version="1.0" encoding="utf-8" standalone="no"?>
  2. <device schemaVersion="1.1"
  3. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
  4. xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  5. <name>STM32L052x</name>
  6. <version>1.0</version>
  7. <description>STM32L052x</description>
  8. <!--Bus Interface Properties-->
  9. <!--Cortex-M3 is byte addressable-->
  10. <addressUnitBits>8</addressUnitBits>
  11. <!--the maximum data bit width accessible within a single transfer-->
  12. <width>32</width>
  13. <!--Register Default Properties-->
  14. <size>0x20</size>
  15. <resetValue>0x0</resetValue>
  16. <resetMask>0xFFFFFFFF</resetMask>
  17. <peripherals>
  18. <peripheral>
  19. <name>DAC</name>
  20. <description>Digital-to-analog converter</description>
  21. <groupName>DAC</groupName>
  22. <baseAddress>0x40007400</baseAddress>
  23. <addressBlock>
  24. <offset>0x0</offset>
  25. <size>0x400</size>
  26. <usage>registers</usage>
  27. </addressBlock>
  28. <registers>
  29. <register>
  30. <name>CR</name>
  31. <displayName>CR</displayName>
  32. <description>control register</description>
  33. <addressOffset>0x0</addressOffset>
  34. <size>0x20</size>
  35. <access>read-write</access>
  36. <resetValue>0x00000000</resetValue>
  37. <fields>
  38. <field>
  39. <name>DMAUDRIE1</name>
  40. <description>DAC channel1 DMA Underrun Interrupt
  41. enable</description>
  42. <bitOffset>13</bitOffset>
  43. <bitWidth>1</bitWidth>
  44. </field>
  45. <field>
  46. <name>DMAEN1</name>
  47. <description>DAC channel1 DMA enable</description>
  48. <bitOffset>12</bitOffset>
  49. <bitWidth>1</bitWidth>
  50. </field>
  51. <field>
  52. <name>MAMP1</name>
  53. <description>DAC channel1 mask/amplitude
  54. selector</description>
  55. <bitOffset>8</bitOffset>
  56. <bitWidth>4</bitWidth>
  57. </field>
  58. <field>
  59. <name>WAVE1</name>
  60. <description>DAC channel1 noise/triangle wave
  61. generation enable</description>
  62. <bitOffset>6</bitOffset>
  63. <bitWidth>2</bitWidth>
  64. </field>
  65. <field>
  66. <name>TSEL1</name>
  67. <description>DAC channel1 trigger
  68. selection</description>
  69. <bitOffset>3</bitOffset>
  70. <bitWidth>3</bitWidth>
  71. </field>
  72. <field>
  73. <name>TEN1</name>
  74. <description>DAC channel1 trigger
  75. enable</description>
  76. <bitOffset>2</bitOffset>
  77. <bitWidth>1</bitWidth>
  78. </field>
  79. <field>
  80. <name>BOFF1</name>
  81. <description>DAC channel1 output buffer
  82. disable</description>
  83. <bitOffset>1</bitOffset>
  84. <bitWidth>1</bitWidth>
  85. </field>
  86. <field>
  87. <name>EN1</name>
  88. <description>DAC channel1 enable</description>
  89. <bitOffset>0</bitOffset>
  90. <bitWidth>1</bitWidth>
  91. </field>
  92. </fields>
  93. </register>
  94. <register>
  95. <name>SWTRIGR</name>
  96. <displayName>SWTRIGR</displayName>
  97. <description>software trigger register</description>
  98. <addressOffset>0x4</addressOffset>
  99. <size>0x20</size>
  100. <access>write-only</access>
  101. <resetValue>0x00000000</resetValue>
  102. <fields>
  103. <field>
  104. <name>SWTRIG1</name>
  105. <description>DAC channel1 software
  106. trigger</description>
  107. <bitOffset>0</bitOffset>
  108. <bitWidth>1</bitWidth>
  109. </field>
  110. </fields>
  111. </register>
  112. <register>
  113. <name>DHR12R1</name>
  114. <displayName>DHR12R1</displayName>
  115. <description>channel1 12-bit right-aligned data holding
  116. register</description>
  117. <addressOffset>0x8</addressOffset>
  118. <size>0x20</size>
  119. <access>read-write</access>
  120. <resetValue>0x00000000</resetValue>
  121. <fields>
  122. <field>
  123. <name>DACC1DHR</name>
  124. <description>DAC channel1 12-bit right-aligned
  125. data</description>
  126. <bitOffset>0</bitOffset>
  127. <bitWidth>12</bitWidth>
  128. </field>
  129. </fields>
  130. </register>
  131. <register>
  132. <name>DHR12L1</name>
  133. <displayName>DHR12L1</displayName>
  134. <description>channel1 12-bit left-aligned data holding
  135. register</description>
  136. <addressOffset>0xC</addressOffset>
  137. <size>0x20</size>
  138. <access>read-write</access>
  139. <resetValue>0x00000000</resetValue>
  140. <fields>
  141. <field>
  142. <name>DACC1DHR</name>
  143. <description>DAC channel1 12-bit left-aligned
  144. data</description>
  145. <bitOffset>4</bitOffset>
  146. <bitWidth>12</bitWidth>
  147. </field>
  148. </fields>
  149. </register>
  150. <register>
  151. <name>DHR8R1</name>
  152. <displayName>DHR8R1</displayName>
  153. <description>channel1 8-bit right-aligned data holding
  154. register</description>
  155. <addressOffset>0x10</addressOffset>
  156. <size>0x20</size>
  157. <access>read-write</access>
  158. <resetValue>0x00000000</resetValue>
  159. <fields>
  160. <field>
  161. <name>DACC1DHR</name>
  162. <description>DAC channel1 8-bit right-aligned
  163. data</description>
  164. <bitOffset>0</bitOffset>
  165. <bitWidth>8</bitWidth>
  166. </field>
  167. </fields>
  168. </register>
  169. <register>
  170. <name>DOR1</name>
  171. <displayName>DOR1</displayName>
  172. <description>channel1 data output register</description>
  173. <addressOffset>0x2C</addressOffset>
  174. <size>0x20</size>
  175. <access>read-only</access>
  176. <resetValue>0x00000000</resetValue>
  177. <fields>
  178. <field>
  179. <name>DACC1DOR</name>
  180. <description>DAC channel1 data output</description>
  181. <bitOffset>0</bitOffset>
  182. <bitWidth>12</bitWidth>
  183. </field>
  184. </fields>
  185. </register>
  186. <register>
  187. <name>SR</name>
  188. <displayName>SR</displayName>
  189. <description>status register</description>
  190. <addressOffset>0x34</addressOffset>
  191. <size>0x20</size>
  192. <access>read-writeOnce</access>
  193. <resetValue>0x00000000</resetValue>
  194. <fields>
  195. <field>
  196. <name>DMAUDR1</name>
  197. <description>DAC channel1 DMA underrun
  198. flag</description>
  199. <bitOffset>13</bitOffset>
  200. <bitWidth>1</bitWidth>
  201. </field>
  202. </fields>
  203. </register>
  204. </registers>
  205. </peripheral>
  206. <peripheral>
  207. <name>DMA1</name>
  208. <description>Direct memory access controller</description>
  209. <groupName>DMA</groupName>
  210. <baseAddress>0x40020000</baseAddress>
  211. <addressBlock>
  212. <offset>0x0</offset>
  213. <size>0x400</size>
  214. <usage>registers</usage>
  215. </addressBlock>
  216. <interrupt>
  217. <name>DMA1_Channel1</name>
  218. <description>DMA1 Channel1 global interrupt</description>
  219. <value>9</value>
  220. </interrupt>
  221. <interrupt>
  222. <name>DMA1_Channel2_3</name>
  223. <description>DMA1 Channel2 and 3 interrupts</description>
  224. <value>10</value>
  225. </interrupt>
  226. <interrupt>
  227. <name>DMA1_Channel4_7</name>
  228. <description>DMA1 Channel4 to 7 interrupts</description>
  229. <value>11</value>
  230. </interrupt>
  231. <registers>
  232. <register>
  233. <name>ISR</name>
  234. <displayName>ISR</displayName>
  235. <description>interrupt status register</description>
  236. <addressOffset>0x0</addressOffset>
  237. <size>0x20</size>
  238. <access>read-only</access>
  239. <resetValue>0x00000000</resetValue>
  240. <fields>
  241. <field>
  242. <name>TEIF7</name>
  243. <description>Channel x transfer error flag (x = 1
  244. ..7)</description>
  245. <bitOffset>27</bitOffset>
  246. <bitWidth>1</bitWidth>
  247. </field>
  248. <field>
  249. <name>HTIF7</name>
  250. <description>Channel x half transfer flag (x = 1
  251. ..7)</description>
  252. <bitOffset>26</bitOffset>
  253. <bitWidth>1</bitWidth>
  254. </field>
  255. <field>
  256. <name>TCIF7</name>
  257. <description>Channel x transfer complete flag (x = 1
  258. ..7)</description>
  259. <bitOffset>25</bitOffset>
  260. <bitWidth>1</bitWidth>
  261. </field>
  262. <field>
  263. <name>GIF7</name>
  264. <description>Channel x global interrupt flag (x = 1
  265. ..7)</description>
  266. <bitOffset>24</bitOffset>
  267. <bitWidth>1</bitWidth>
  268. </field>
  269. <field>
  270. <name>TEIF6</name>
  271. <description>Channel x transfer error flag (x = 1
  272. ..7)</description>
  273. <bitOffset>23</bitOffset>
  274. <bitWidth>1</bitWidth>
  275. </field>
  276. <field>
  277. <name>HTIF6</name>
  278. <description>Channel x half transfer flag (x = 1
  279. ..7)</description>
  280. <bitOffset>22</bitOffset>
  281. <bitWidth>1</bitWidth>
  282. </field>
  283. <field>
  284. <name>TCIF6</name>
  285. <description>Channel x transfer complete flag (x = 1
  286. ..7)</description>
  287. <bitOffset>21</bitOffset>
  288. <bitWidth>1</bitWidth>
  289. </field>
  290. <field>
  291. <name>GIF6</name>
  292. <description>Channel x global interrupt flag (x = 1
  293. ..7)</description>
  294. <bitOffset>20</bitOffset>
  295. <bitWidth>1</bitWidth>
  296. </field>
  297. <field>
  298. <name>TEIF5</name>
  299. <description>Channel x transfer error flag (x = 1
  300. ..7)</description>
  301. <bitOffset>19</bitOffset>
  302. <bitWidth>1</bitWidth>
  303. </field>
  304. <field>
  305. <name>HTIF5</name>
  306. <description>Channel x half transfer flag (x = 1
  307. ..7)</description>
  308. <bitOffset>18</bitOffset>
  309. <bitWidth>1</bitWidth>
  310. </field>
  311. <field>
  312. <name>TCIF5</name>
  313. <description>Channel x transfer complete flag (x = 1
  314. ..7)</description>
  315. <bitOffset>17</bitOffset>
  316. <bitWidth>1</bitWidth>
  317. </field>
  318. <field>
  319. <name>GIF5</name>
  320. <description>Channel x global interrupt flag (x = 1
  321. ..7)</description>
  322. <bitOffset>16</bitOffset>
  323. <bitWidth>1</bitWidth>
  324. </field>
  325. <field>
  326. <name>TEIF4</name>
  327. <description>Channel x transfer error flag (x = 1
  328. ..7)</description>
  329. <bitOffset>15</bitOffset>
  330. <bitWidth>1</bitWidth>
  331. </field>
  332. <field>
  333. <name>HTIF4</name>
  334. <description>Channel x half transfer flag (x = 1
  335. ..7)</description>
  336. <bitOffset>14</bitOffset>
  337. <bitWidth>1</bitWidth>
  338. </field>
  339. <field>
  340. <name>TCIF4</name>
  341. <description>Channel x transfer complete flag (x = 1
  342. ..7)</description>
  343. <bitOffset>13</bitOffset>
  344. <bitWidth>1</bitWidth>
  345. </field>
  346. <field>
  347. <name>GIF4</name>
  348. <description>Channel x global interrupt flag (x = 1
  349. ..7)</description>
  350. <bitOffset>12</bitOffset>
  351. <bitWidth>1</bitWidth>
  352. </field>
  353. <field>
  354. <name>TEIF3</name>
  355. <description>Channel x transfer error flag (x = 1
  356. ..7)</description>
  357. <bitOffset>11</bitOffset>
  358. <bitWidth>1</bitWidth>
  359. </field>
  360. <field>
  361. <name>HTIF3</name>
  362. <description>Channel x half transfer flag (x = 1
  363. ..7)</description>
  364. <bitOffset>10</bitOffset>
  365. <bitWidth>1</bitWidth>
  366. </field>
  367. <field>
  368. <name>TCIF3</name>
  369. <description>Channel x transfer complete flag (x = 1
  370. ..7)</description>
  371. <bitOffset>9</bitOffset>
  372. <bitWidth>1</bitWidth>
  373. </field>
  374. <field>
  375. <name>GIF3</name>
  376. <description>Channel x global interrupt flag (x = 1
  377. ..7)</description>
  378. <bitOffset>8</bitOffset>
  379. <bitWidth>1</bitWidth>
  380. </field>
  381. <field>
  382. <name>TEIF2</name>
  383. <description>Channel x transfer error flag (x = 1
  384. ..7)</description>
  385. <bitOffset>7</bitOffset>
  386. <bitWidth>1</bitWidth>
  387. </field>
  388. <field>
  389. <name>HTIF2</name>
  390. <description>Channel x half transfer flag (x = 1
  391. ..7)</description>
  392. <bitOffset>6</bitOffset>
  393. <bitWidth>1</bitWidth>
  394. </field>
  395. <field>
  396. <name>TCIF2</name>
  397. <description>Channel x transfer complete flag (x = 1
  398. ..7)</description>
  399. <bitOffset>5</bitOffset>
  400. <bitWidth>1</bitWidth>
  401. </field>
  402. <field>
  403. <name>GIF2</name>
  404. <description>Channel x global interrupt flag (x = 1
  405. ..7)</description>
  406. <bitOffset>4</bitOffset>
  407. <bitWidth>1</bitWidth>
  408. </field>
  409. <field>
  410. <name>TEIF1</name>
  411. <description>Channel x transfer error flag (x = 1
  412. ..7)</description>
  413. <bitOffset>3</bitOffset>
  414. <bitWidth>1</bitWidth>
  415. </field>
  416. <field>
  417. <name>HTIF1</name>
  418. <description>Channel x half transfer flag (x = 1
  419. ..7)</description>
  420. <bitOffset>2</bitOffset>
  421. <bitWidth>1</bitWidth>
  422. </field>
  423. <field>
  424. <name>TCIF1</name>
  425. <description>Channel x transfer complete flag (x = 1
  426. ..7)</description>
  427. <bitOffset>1</bitOffset>
  428. <bitWidth>1</bitWidth>
  429. </field>
  430. <field>
  431. <name>GIF1</name>
  432. <description>Channel x global interrupt flag (x = 1
  433. ..7)</description>
  434. <bitOffset>0</bitOffset>
  435. <bitWidth>1</bitWidth>
  436. </field>
  437. </fields>
  438. </register>
  439. <register>
  440. <name>IFCR</name>
  441. <displayName>IFCR</displayName>
  442. <description>interrupt flag clear register</description>
  443. <addressOffset>0x4</addressOffset>
  444. <size>0x20</size>
  445. <access>write-only</access>
  446. <resetValue>0x00000000</resetValue>
  447. <fields>
  448. <field>
  449. <name>CTEIF7</name>
  450. <description>Channel x transfer error clear (x = 1
  451. ..7)</description>
  452. <bitOffset>27</bitOffset>
  453. <bitWidth>1</bitWidth>
  454. </field>
  455. <field>
  456. <name>CHTIF7</name>
  457. <description>Channel x half transfer clear (x = 1
  458. ..7)</description>
  459. <bitOffset>26</bitOffset>
  460. <bitWidth>1</bitWidth>
  461. </field>
  462. <field>
  463. <name>CTCIF7</name>
  464. <description>Channel x transfer complete clear (x = 1
  465. ..7)</description>
  466. <bitOffset>25</bitOffset>
  467. <bitWidth>1</bitWidth>
  468. </field>
  469. <field>
  470. <name>CGIF7</name>
  471. <description>Channel x global interrupt clear (x = 1
  472. ..7)</description>
  473. <bitOffset>24</bitOffset>
  474. <bitWidth>1</bitWidth>
  475. </field>
  476. <field>
  477. <name>CTEIF6</name>
  478. <description>Channel x transfer error clear (x = 1
  479. ..7)</description>
  480. <bitOffset>23</bitOffset>
  481. <bitWidth>1</bitWidth>
  482. </field>
  483. <field>
  484. <name>CHTIF6</name>
  485. <description>Channel x half transfer clear (x = 1
  486. ..7)</description>
  487. <bitOffset>22</bitOffset>
  488. <bitWidth>1</bitWidth>
  489. </field>
  490. <field>
  491. <name>CTCIF6</name>
  492. <description>Channel x transfer complete clear (x = 1
  493. ..7)</description>
  494. <bitOffset>21</bitOffset>
  495. <bitWidth>1</bitWidth>
  496. </field>
  497. <field>
  498. <name>CGIF6</name>
  499. <description>Channel x global interrupt clear (x = 1
  500. ..7)</description>
  501. <bitOffset>20</bitOffset>
  502. <bitWidth>1</bitWidth>
  503. </field>
  504. <field>
  505. <name>CTEIF5</name>
  506. <description>Channel x transfer error clear (x = 1
  507. ..7)</description>
  508. <bitOffset>19</bitOffset>
  509. <bitWidth>1</bitWidth>
  510. </field>
  511. <field>
  512. <name>CHTIF5</name>
  513. <description>Channel x half transfer clear (x = 1
  514. ..7)</description>
  515. <bitOffset>18</bitOffset>
  516. <bitWidth>1</bitWidth>
  517. </field>
  518. <field>
  519. <name>CTCIF5</name>
  520. <description>Channel x transfer complete clear (x = 1
  521. ..7)</description>
  522. <bitOffset>17</bitOffset>
  523. <bitWidth>1</bitWidth>
  524. </field>
  525. <field>
  526. <name>CGIF5</name>
  527. <description>Channel x global interrupt clear (x = 1
  528. ..7)</description>
  529. <bitOffset>16</bitOffset>
  530. <bitWidth>1</bitWidth>
  531. </field>
  532. <field>
  533. <name>CTEIF4</name>
  534. <description>Channel x transfer error clear (x = 1
  535. ..7)</description>
  536. <bitOffset>15</bitOffset>
  537. <bitWidth>1</bitWidth>
  538. </field>
  539. <field>
  540. <name>CHTIF4</name>
  541. <description>Channel x half transfer clear (x = 1
  542. ..7)</description>
  543. <bitOffset>14</bitOffset>
  544. <bitWidth>1</bitWidth>
  545. </field>
  546. <field>
  547. <name>CTCIF4</name>
  548. <description>Channel x transfer complete clear (x = 1
  549. ..7)</description>
  550. <bitOffset>13</bitOffset>
  551. <bitWidth>1</bitWidth>
  552. </field>
  553. <field>
  554. <name>CGIF4</name>
  555. <description>Channel x global interrupt clear (x = 1
  556. ..7)</description>
  557. <bitOffset>12</bitOffset>
  558. <bitWidth>1</bitWidth>
  559. </field>
  560. <field>
  561. <name>CTEIF3</name>
  562. <description>Channel x transfer error clear (x = 1
  563. ..7)</description>
  564. <bitOffset>11</bitOffset>
  565. <bitWidth>1</bitWidth>
  566. </field>
  567. <field>
  568. <name>CHTIF3</name>
  569. <description>Channel x half transfer clear (x = 1
  570. ..7)</description>
  571. <bitOffset>10</bitOffset>
  572. <bitWidth>1</bitWidth>
  573. </field>
  574. <field>
  575. <name>CTCIF3</name>
  576. <description>Channel x transfer complete clear (x = 1
  577. ..7)</description>
  578. <bitOffset>9</bitOffset>
  579. <bitWidth>1</bitWidth>
  580. </field>
  581. <field>
  582. <name>CGIF3</name>
  583. <description>Channel x global interrupt clear (x = 1
  584. ..7)</description>
  585. <bitOffset>8</bitOffset>
  586. <bitWidth>1</bitWidth>
  587. </field>
  588. <field>
  589. <name>CTEIF2</name>
  590. <description>Channel x transfer error clear (x = 1
  591. ..7)</description>
  592. <bitOffset>7</bitOffset>
  593. <bitWidth>1</bitWidth>
  594. </field>
  595. <field>
  596. <name>CHTIF2</name>
  597. <description>Channel x half transfer clear (x = 1
  598. ..7)</description>
  599. <bitOffset>6</bitOffset>
  600. <bitWidth>1</bitWidth>
  601. </field>
  602. <field>
  603. <name>CTCIF2</name>
  604. <description>Channel x transfer complete clear (x = 1
  605. ..7)</description>
  606. <bitOffset>5</bitOffset>
  607. <bitWidth>1</bitWidth>
  608. </field>
  609. <field>
  610. <name>CGIF2</name>
  611. <description>Channel x global interrupt clear (x = 1
  612. ..7)</description>
  613. <bitOffset>4</bitOffset>
  614. <bitWidth>1</bitWidth>
  615. </field>
  616. <field>
  617. <name>CTEIF1</name>
  618. <description>Channel x transfer error clear (x = 1
  619. ..7)</description>
  620. <bitOffset>3</bitOffset>
  621. <bitWidth>1</bitWidth>
  622. </field>
  623. <field>
  624. <name>CHTIF1</name>
  625. <description>Channel x half transfer clear (x = 1
  626. ..7)</description>
  627. <bitOffset>2</bitOffset>
  628. <bitWidth>1</bitWidth>
  629. </field>
  630. <field>
  631. <name>CTCIF1</name>
  632. <description>Channel x transfer complete clear (x = 1
  633. ..7)</description>
  634. <bitOffset>1</bitOffset>
  635. <bitWidth>1</bitWidth>
  636. </field>
  637. <field>
  638. <name>CGIF1</name>
  639. <description>Channel x global interrupt clear (x = 1
  640. ..7)</description>
  641. <bitOffset>0</bitOffset>
  642. <bitWidth>1</bitWidth>
  643. </field>
  644. </fields>
  645. </register>
  646. <register>
  647. <name>CCR1</name>
  648. <displayName>CCR1</displayName>
  649. <description>channel x configuration
  650. register</description>
  651. <addressOffset>0x8</addressOffset>
  652. <size>0x20</size>
  653. <access>read-write</access>
  654. <resetValue>0x00000000</resetValue>
  655. <fields>
  656. <field>
  657. <name>MEM2MEM</name>
  658. <description>Memory to memory mode</description>
  659. <bitOffset>14</bitOffset>
  660. <bitWidth>1</bitWidth>
  661. </field>
  662. <field>
  663. <name>PL</name>
  664. <description>Channel priority level</description>
  665. <bitOffset>12</bitOffset>
  666. <bitWidth>2</bitWidth>
  667. </field>
  668. <field>
  669. <name>MSIZE</name>
  670. <description>Memory size</description>
  671. <bitOffset>10</bitOffset>
  672. <bitWidth>2</bitWidth>
  673. </field>
  674. <field>
  675. <name>PSIZE</name>
  676. <description>Peripheral size</description>
  677. <bitOffset>8</bitOffset>
  678. <bitWidth>2</bitWidth>
  679. </field>
  680. <field>
  681. <name>MINC</name>
  682. <description>Memory increment mode</description>
  683. <bitOffset>7</bitOffset>
  684. <bitWidth>1</bitWidth>
  685. </field>
  686. <field>
  687. <name>PINC</name>
  688. <description>Peripheral increment mode</description>
  689. <bitOffset>6</bitOffset>
  690. <bitWidth>1</bitWidth>
  691. </field>
  692. <field>
  693. <name>CIRC</name>
  694. <description>Circular mode</description>
  695. <bitOffset>5</bitOffset>
  696. <bitWidth>1</bitWidth>
  697. </field>
  698. <field>
  699. <name>DIR</name>
  700. <description>Data transfer direction</description>
  701. <bitOffset>4</bitOffset>
  702. <bitWidth>1</bitWidth>
  703. </field>
  704. <field>
  705. <name>TEIE</name>
  706. <description>Transfer error interrupt
  707. enable</description>
  708. <bitOffset>3</bitOffset>
  709. <bitWidth>1</bitWidth>
  710. </field>
  711. <field>
  712. <name>HTIE</name>
  713. <description>Half transfer interrupt
  714. enable</description>
  715. <bitOffset>2</bitOffset>
  716. <bitWidth>1</bitWidth>
  717. </field>
  718. <field>
  719. <name>TCIE</name>
  720. <description>Transfer complete interrupt
  721. enable</description>
  722. <bitOffset>1</bitOffset>
  723. <bitWidth>1</bitWidth>
  724. </field>
  725. <field>
  726. <name>EN</name>
  727. <description>Channel enable</description>
  728. <bitOffset>0</bitOffset>
  729. <bitWidth>1</bitWidth>
  730. </field>
  731. </fields>
  732. </register>
  733. <register>
  734. <name>CNDTR1</name>
  735. <displayName>CNDTR1</displayName>
  736. <description>channel x number of data
  737. register</description>
  738. <addressOffset>0xC</addressOffset>
  739. <size>0x20</size>
  740. <access>read-write</access>
  741. <resetValue>0x00000000</resetValue>
  742. <fields>
  743. <field>
  744. <name>NDT</name>
  745. <description>Number of data to transfer</description>
  746. <bitOffset>0</bitOffset>
  747. <bitWidth>16</bitWidth>
  748. </field>
  749. </fields>
  750. </register>
  751. <register>
  752. <name>CPAR1</name>
  753. <displayName>CPAR1</displayName>
  754. <description>channel x peripheral address
  755. register</description>
  756. <addressOffset>0x10</addressOffset>
  757. <size>0x20</size>
  758. <access>read-write</access>
  759. <resetValue>0x00000000</resetValue>
  760. <fields>
  761. <field>
  762. <name>PA</name>
  763. <description>Peripheral address</description>
  764. <bitOffset>0</bitOffset>
  765. <bitWidth>32</bitWidth>
  766. </field>
  767. </fields>
  768. </register>
  769. <register>
  770. <name>CMAR1</name>
  771. <displayName>CMAR1</displayName>
  772. <description>channel x memory address
  773. register</description>
  774. <addressOffset>0x14</addressOffset>
  775. <size>0x20</size>
  776. <access>read-write</access>
  777. <resetValue>0x00000000</resetValue>
  778. <fields>
  779. <field>
  780. <name>MA</name>
  781. <description>Memory address</description>
  782. <bitOffset>0</bitOffset>
  783. <bitWidth>32</bitWidth>
  784. </field>
  785. </fields>
  786. </register>
  787. <register>
  788. <name>CCR2</name>
  789. <displayName>CCR2</displayName>
  790. <description>channel x configuration
  791. register</description>
  792. <addressOffset>0x1C</addressOffset>
  793. <size>0x20</size>
  794. <access>read-write</access>
  795. <resetValue>0x00000000</resetValue>
  796. <fields>
  797. <field>
  798. <name>MEM2MEM</name>
  799. <description>Memory to memory mode</description>
  800. <bitOffset>14</bitOffset>
  801. <bitWidth>1</bitWidth>
  802. </field>
  803. <field>
  804. <name>PL</name>
  805. <description>Channel priority level</description>
  806. <bitOffset>12</bitOffset>
  807. <bitWidth>2</bitWidth>
  808. </field>
  809. <field>
  810. <name>MSIZE</name>
  811. <description>Memory size</description>
  812. <bitOffset>10</bitOffset>
  813. <bitWidth>2</bitWidth>
  814. </field>
  815. <field>
  816. <name>PSIZE</name>
  817. <description>Peripheral size</description>
  818. <bitOffset>8</bitOffset>
  819. <bitWidth>2</bitWidth>
  820. </field>
  821. <field>
  822. <name>MINC</name>
  823. <description>Memory increment mode</description>
  824. <bitOffset>7</bitOffset>
  825. <bitWidth>1</bitWidth>
  826. </field>
  827. <field>
  828. <name>PINC</name>
  829. <description>Peripheral increment mode</description>
  830. <bitOffset>6</bitOffset>
  831. <bitWidth>1</bitWidth>
  832. </field>
  833. <field>
  834. <name>CIRC</name>
  835. <description>Circular mode</description>
  836. <bitOffset>5</bitOffset>
  837. <bitWidth>1</bitWidth>
  838. </field>
  839. <field>
  840. <name>DIR</name>
  841. <description>Data transfer direction</description>
  842. <bitOffset>4</bitOffset>
  843. <bitWidth>1</bitWidth>
  844. </field>
  845. <field>
  846. <name>TEIE</name>
  847. <description>Transfer error interrupt
  848. enable</description>
  849. <bitOffset>3</bitOffset>
  850. <bitWidth>1</bitWidth>
  851. </field>
  852. <field>
  853. <name>HTIE</name>
  854. <description>Half transfer interrupt
  855. enable</description>
  856. <bitOffset>2</bitOffset>
  857. <bitWidth>1</bitWidth>
  858. </field>
  859. <field>
  860. <name>TCIE</name>
  861. <description>Transfer complete interrupt
  862. enable</description>
  863. <bitOffset>1</bitOffset>
  864. <bitWidth>1</bitWidth>
  865. </field>
  866. <field>
  867. <name>EN</name>
  868. <description>Channel enable</description>
  869. <bitOffset>0</bitOffset>
  870. <bitWidth>1</bitWidth>
  871. </field>
  872. </fields>
  873. </register>
  874. <register>
  875. <name>CNDTR2</name>
  876. <displayName>CNDTR2</displayName>
  877. <description>channel x number of data
  878. register</description>
  879. <addressOffset>0x20</addressOffset>
  880. <size>0x20</size>
  881. <access>read-write</access>
  882. <resetValue>0x00000000</resetValue>
  883. <fields>
  884. <field>
  885. <name>NDT</name>
  886. <description>Number of data to transfer</description>
  887. <bitOffset>0</bitOffset>
  888. <bitWidth>16</bitWidth>
  889. </field>
  890. </fields>
  891. </register>
  892. <register>
  893. <name>CPAR2</name>
  894. <displayName>CPAR2</displayName>
  895. <description>channel x peripheral address
  896. register</description>
  897. <addressOffset>0x24</addressOffset>
  898. <size>0x20</size>
  899. <access>read-write</access>
  900. <resetValue>0x00000000</resetValue>
  901. <fields>
  902. <field>
  903. <name>PA</name>
  904. <description>Peripheral address</description>
  905. <bitOffset>0</bitOffset>
  906. <bitWidth>32</bitWidth>
  907. </field>
  908. </fields>
  909. </register>
  910. <register>
  911. <name>CMAR2</name>
  912. <displayName>CMAR2</displayName>
  913. <description>channel x memory address
  914. register</description>
  915. <addressOffset>0x28</addressOffset>
  916. <size>0x20</size>
  917. <access>read-write</access>
  918. <resetValue>0x00000000</resetValue>
  919. <fields>
  920. <field>
  921. <name>MA</name>
  922. <description>Memory address</description>
  923. <bitOffset>0</bitOffset>
  924. <bitWidth>32</bitWidth>
  925. </field>
  926. </fields>
  927. </register>
  928. <register>
  929. <name>CCR3</name>
  930. <displayName>CCR3</displayName>
  931. <description>channel x configuration
  932. register</description>
  933. <addressOffset>0x30</addressOffset>
  934. <size>0x20</size>
  935. <access>read-write</access>
  936. <resetValue>0x00000000</resetValue>
  937. <fields>
  938. <field>
  939. <name>MEM2MEM</name>
  940. <description>Memory to memory mode</description>
  941. <bitOffset>14</bitOffset>
  942. <bitWidth>1</bitWidth>
  943. </field>
  944. <field>
  945. <name>PL</name>
  946. <description>Channel priority level</description>
  947. <bitOffset>12</bitOffset>
  948. <bitWidth>2</bitWidth>
  949. </field>
  950. <field>
  951. <name>MSIZE</name>
  952. <description>Memory size</description>
  953. <bitOffset>10</bitOffset>
  954. <bitWidth>2</bitWidth>
  955. </field>
  956. <field>
  957. <name>PSIZE</name>
  958. <description>Peripheral size</description>
  959. <bitOffset>8</bitOffset>
  960. <bitWidth>2</bitWidth>
  961. </field>
  962. <field>
  963. <name>MINC</name>
  964. <description>Memory increment mode</description>
  965. <bitOffset>7</bitOffset>
  966. <bitWidth>1</bitWidth>
  967. </field>
  968. <field>
  969. <name>PINC</name>
  970. <description>Peripheral increment mode</description>
  971. <bitOffset>6</bitOffset>
  972. <bitWidth>1</bitWidth>
  973. </field>
  974. <field>
  975. <name>CIRC</name>
  976. <description>Circular mode</description>
  977. <bitOffset>5</bitOffset>
  978. <bitWidth>1</bitWidth>
  979. </field>
  980. <field>
  981. <name>DIR</name>
  982. <description>Data transfer direction</description>
  983. <bitOffset>4</bitOffset>
  984. <bitWidth>1</bitWidth>
  985. </field>
  986. <field>
  987. <name>TEIE</name>
  988. <description>Transfer error interrupt
  989. enable</description>
  990. <bitOffset>3</bitOffset>
  991. <bitWidth>1</bitWidth>
  992. </field>
  993. <field>
  994. <name>HTIE</name>
  995. <description>Half transfer interrupt
  996. enable</description>
  997. <bitOffset>2</bitOffset>
  998. <bitWidth>1</bitWidth>
  999. </field>
  1000. <field>
  1001. <name>TCIE</name>
  1002. <description>Transfer complete interrupt
  1003. enable</description>
  1004. <bitOffset>1</bitOffset>
  1005. <bitWidth>1</bitWidth>
  1006. </field>
  1007. <field>
  1008. <name>EN</name>
  1009. <description>Channel enable</description>
  1010. <bitOffset>0</bitOffset>
  1011. <bitWidth>1</bitWidth>
  1012. </field>
  1013. </fields>
  1014. </register>
  1015. <register>
  1016. <name>CNDTR3</name>
  1017. <displayName>CNDTR3</displayName>
  1018. <description>channel x number of data
  1019. register</description>
  1020. <addressOffset>0x34</addressOffset>
  1021. <size>0x20</size>
  1022. <access>read-write</access>
  1023. <resetValue>0x00000000</resetValue>
  1024. <fields>
  1025. <field>
  1026. <name>NDT</name>
  1027. <description>Number of data to transfer</description>
  1028. <bitOffset>0</bitOffset>
  1029. <bitWidth>16</bitWidth>
  1030. </field>
  1031. </fields>
  1032. </register>
  1033. <register>
  1034. <name>CPAR3</name>
  1035. <displayName>CPAR3</displayName>
  1036. <description>channel x peripheral address
  1037. register</description>
  1038. <addressOffset>0x38</addressOffset>
  1039. <size>0x20</size>
  1040. <access>read-write</access>
  1041. <resetValue>0x00000000</resetValue>
  1042. <fields>
  1043. <field>
  1044. <name>PA</name>
  1045. <description>Peripheral address</description>
  1046. <bitOffset>0</bitOffset>
  1047. <bitWidth>32</bitWidth>
  1048. </field>
  1049. </fields>
  1050. </register>
  1051. <register>
  1052. <name>CMAR3</name>
  1053. <displayName>CMAR3</displayName>
  1054. <description>channel x memory address
  1055. register</description>
  1056. <addressOffset>0x3C</addressOffset>
  1057. <size>0x20</size>
  1058. <access>read-write</access>
  1059. <resetValue>0x00000000</resetValue>
  1060. <fields>
  1061. <field>
  1062. <name>MA</name>
  1063. <description>Memory address</description>
  1064. <bitOffset>0</bitOffset>
  1065. <bitWidth>32</bitWidth>
  1066. </field>
  1067. </fields>
  1068. </register>
  1069. <register>
  1070. <name>CCR4</name>
  1071. <displayName>CCR4</displayName>
  1072. <description>channel x configuration
  1073. register</description>
  1074. <addressOffset>0x44</addressOffset>
  1075. <size>0x20</size>
  1076. <access>read-write</access>
  1077. <resetValue>0x00000000</resetValue>
  1078. <fields>
  1079. <field>
  1080. <name>MEM2MEM</name>
  1081. <description>Memory to memory mode</description>
  1082. <bitOffset>14</bitOffset>
  1083. <bitWidth>1</bitWidth>
  1084. </field>
  1085. <field>
  1086. <name>PL</name>
  1087. <description>Channel priority level</description>
  1088. <bitOffset>12</bitOffset>
  1089. <bitWidth>2</bitWidth>
  1090. </field>
  1091. <field>
  1092. <name>MSIZE</name>
  1093. <description>Memory size</description>
  1094. <bitOffset>10</bitOffset>
  1095. <bitWidth>2</bitWidth>
  1096. </field>
  1097. <field>
  1098. <name>PSIZE</name>
  1099. <description>Peripheral size</description>
  1100. <bitOffset>8</bitOffset>
  1101. <bitWidth>2</bitWidth>
  1102. </field>
  1103. <field>
  1104. <name>MINC</name>
  1105. <description>Memory increment mode</description>
  1106. <bitOffset>7</bitOffset>
  1107. <bitWidth>1</bitWidth>
  1108. </field>
  1109. <field>
  1110. <name>PINC</name>
  1111. <description>Peripheral increment mode</description>
  1112. <bitOffset>6</bitOffset>
  1113. <bitWidth>1</bitWidth>
  1114. </field>
  1115. <field>
  1116. <name>CIRC</name>
  1117. <description>Circular mode</description>
  1118. <bitOffset>5</bitOffset>
  1119. <bitWidth>1</bitWidth>
  1120. </field>
  1121. <field>
  1122. <name>DIR</name>
  1123. <description>Data transfer direction</description>
  1124. <bitOffset>4</bitOffset>
  1125. <bitWidth>1</bitWidth>
  1126. </field>
  1127. <field>
  1128. <name>TEIE</name>
  1129. <description>Transfer error interrupt
  1130. enable</description>
  1131. <bitOffset>3</bitOffset>
  1132. <bitWidth>1</bitWidth>
  1133. </field>
  1134. <field>
  1135. <name>HTIE</name>
  1136. <description>Half transfer interrupt
  1137. enable</description>
  1138. <bitOffset>2</bitOffset>
  1139. <bitWidth>1</bitWidth>
  1140. </field>
  1141. <field>
  1142. <name>TCIE</name>
  1143. <description>Transfer complete interrupt
  1144. enable</description>
  1145. <bitOffset>1</bitOffset>
  1146. <bitWidth>1</bitWidth>
  1147. </field>
  1148. <field>
  1149. <name>EN</name>
  1150. <description>Channel enable</description>
  1151. <bitOffset>0</bitOffset>
  1152. <bitWidth>1</bitWidth>
  1153. </field>
  1154. </fields>
  1155. </register>
  1156. <register>
  1157. <name>CNDTR4</name>
  1158. <displayName>CNDTR4</displayName>
  1159. <description>channel x number of data
  1160. register</description>
  1161. <addressOffset>0x48</addressOffset>
  1162. <size>0x20</size>
  1163. <access>read-write</access>
  1164. <resetValue>0x00000000</resetValue>
  1165. <fields>
  1166. <field>
  1167. <name>NDT</name>
  1168. <description>Number of data to transfer</description>
  1169. <bitOffset>0</bitOffset>
  1170. <bitWidth>16</bitWidth>
  1171. </field>
  1172. </fields>
  1173. </register>
  1174. <register>
  1175. <name>CPAR4</name>
  1176. <displayName>CPAR4</displayName>
  1177. <description>channel x peripheral address
  1178. register</description>
  1179. <addressOffset>0x4C</addressOffset>
  1180. <size>0x20</size>
  1181. <access>read-write</access>
  1182. <resetValue>0x00000000</resetValue>
  1183. <fields>
  1184. <field>
  1185. <name>PA</name>
  1186. <description>Peripheral address</description>
  1187. <bitOffset>0</bitOffset>
  1188. <bitWidth>32</bitWidth>
  1189. </field>
  1190. </fields>
  1191. </register>
  1192. <register>
  1193. <name>CMAR4</name>
  1194. <displayName>CMAR4</displayName>
  1195. <description>channel x memory address
  1196. register</description>
  1197. <addressOffset>0x50</addressOffset>
  1198. <size>0x20</size>
  1199. <access>read-write</access>
  1200. <resetValue>0x00000000</resetValue>
  1201. <fields>
  1202. <field>
  1203. <name>MA</name>
  1204. <description>Memory address</description>
  1205. <bitOffset>0</bitOffset>
  1206. <bitWidth>32</bitWidth>
  1207. </field>
  1208. </fields>
  1209. </register>
  1210. <register>
  1211. <name>CCR5</name>
  1212. <displayName>CCR5</displayName>
  1213. <description>channel x configuration
  1214. register</description>
  1215. <addressOffset>0x58</addressOffset>
  1216. <size>0x20</size>
  1217. <access>read-write</access>
  1218. <resetValue>0x00000000</resetValue>
  1219. <fields>
  1220. <field>
  1221. <name>MEM2MEM</name>
  1222. <description>Memory to memory mode</description>
  1223. <bitOffset>14</bitOffset>
  1224. <bitWidth>1</bitWidth>
  1225. </field>
  1226. <field>
  1227. <name>PL</name>
  1228. <description>Channel priority level</description>
  1229. <bitOffset>12</bitOffset>
  1230. <bitWidth>2</bitWidth>
  1231. </field>
  1232. <field>
  1233. <name>MSIZE</name>
  1234. <description>Memory size</description>
  1235. <bitOffset>10</bitOffset>
  1236. <bitWidth>2</bitWidth>
  1237. </field>
  1238. <field>
  1239. <name>PSIZE</name>
  1240. <description>Peripheral size</description>
  1241. <bitOffset>8</bitOffset>
  1242. <bitWidth>2</bitWidth>
  1243. </field>
  1244. <field>
  1245. <name>MINC</name>
  1246. <description>Memory increment mode</description>
  1247. <bitOffset>7</bitOffset>
  1248. <bitWidth>1</bitWidth>
  1249. </field>
  1250. <field>
  1251. <name>PINC</name>
  1252. <description>Peripheral increment mode</description>
  1253. <bitOffset>6</bitOffset>
  1254. <bitWidth>1</bitWidth>
  1255. </field>
  1256. <field>
  1257. <name>CIRC</name>
  1258. <description>Circular mode</description>
  1259. <bitOffset>5</bitOffset>
  1260. <bitWidth>1</bitWidth>
  1261. </field>
  1262. <field>
  1263. <name>DIR</name>
  1264. <description>Data transfer direction</description>
  1265. <bitOffset>4</bitOffset>
  1266. <bitWidth>1</bitWidth>
  1267. </field>
  1268. <field>
  1269. <name>TEIE</name>
  1270. <description>Transfer error interrupt
  1271. enable</description>
  1272. <bitOffset>3</bitOffset>
  1273. <bitWidth>1</bitWidth>
  1274. </field>
  1275. <field>
  1276. <name>HTIE</name>
  1277. <description>Half transfer interrupt
  1278. enable</description>
  1279. <bitOffset>2</bitOffset>
  1280. <bitWidth>1</bitWidth>
  1281. </field>
  1282. <field>
  1283. <name>TCIE</name>
  1284. <description>Transfer complete interrupt
  1285. enable</description>
  1286. <bitOffset>1</bitOffset>
  1287. <bitWidth>1</bitWidth>
  1288. </field>
  1289. <field>
  1290. <name>EN</name>
  1291. <description>Channel enable</description>
  1292. <bitOffset>0</bitOffset>
  1293. <bitWidth>1</bitWidth>
  1294. </field>
  1295. </fields>
  1296. </register>
  1297. <register>
  1298. <name>CNDTR5</name>
  1299. <displayName>CNDTR5</displayName>
  1300. <description>channel x number of data
  1301. register</description>
  1302. <addressOffset>0x5C</addressOffset>
  1303. <size>0x20</size>
  1304. <access>read-write</access>
  1305. <resetValue>0x00000000</resetValue>
  1306. <fields>
  1307. <field>
  1308. <name>NDT</name>
  1309. <description>Number of data to transfer</description>
  1310. <bitOffset>0</bitOffset>
  1311. <bitWidth>16</bitWidth>
  1312. </field>
  1313. </fields>
  1314. </register>
  1315. <register>
  1316. <name>CPAR5</name>
  1317. <displayName>CPAR5</displayName>
  1318. <description>channel x peripheral address
  1319. register</description>
  1320. <addressOffset>0x60</addressOffset>
  1321. <size>0x20</size>
  1322. <access>read-write</access>
  1323. <resetValue>0x00000000</resetValue>
  1324. <fields>
  1325. <field>
  1326. <name>PA</name>
  1327. <description>Peripheral address</description>
  1328. <bitOffset>0</bitOffset>
  1329. <bitWidth>32</bitWidth>
  1330. </field>
  1331. </fields>
  1332. </register>
  1333. <register>
  1334. <name>CMAR5</name>
  1335. <displayName>CMAR5</displayName>
  1336. <description>channel x memory address
  1337. register</description>
  1338. <addressOffset>0x64</addressOffset>
  1339. <size>0x20</size>
  1340. <access>read-write</access>
  1341. <resetValue>0x00000000</resetValue>
  1342. <fields>
  1343. <field>
  1344. <name>MA</name>
  1345. <description>Memory address</description>
  1346. <bitOffset>0</bitOffset>
  1347. <bitWidth>32</bitWidth>
  1348. </field>
  1349. </fields>
  1350. </register>
  1351. <register>
  1352. <name>CCR6</name>
  1353. <displayName>CCR6</displayName>
  1354. <description>channel x configuration
  1355. register</description>
  1356. <addressOffset>0x6C</addressOffset>
  1357. <size>0x20</size>
  1358. <access>read-write</access>
  1359. <resetValue>0x00000000</resetValue>
  1360. <fields>
  1361. <field>
  1362. <name>MEM2MEM</name>
  1363. <description>Memory to memory mode</description>
  1364. <bitOffset>14</bitOffset>
  1365. <bitWidth>1</bitWidth>
  1366. </field>
  1367. <field>
  1368. <name>PL</name>
  1369. <description>Channel priority level</description>
  1370. <bitOffset>12</bitOffset>
  1371. <bitWidth>2</bitWidth>
  1372. </field>
  1373. <field>
  1374. <name>MSIZE</name>
  1375. <description>Memory size</description>
  1376. <bitOffset>10</bitOffset>
  1377. <bitWidth>2</bitWidth>
  1378. </field>
  1379. <field>
  1380. <name>PSIZE</name>
  1381. <description>Peripheral size</description>
  1382. <bitOffset>8</bitOffset>
  1383. <bitWidth>2</bitWidth>
  1384. </field>
  1385. <field>
  1386. <name>MINC</name>
  1387. <description>Memory increment mode</description>
  1388. <bitOffset>7</bitOffset>
  1389. <bitWidth>1</bitWidth>
  1390. </field>
  1391. <field>
  1392. <name>PINC</name>
  1393. <description>Peripheral increment mode</description>
  1394. <bitOffset>6</bitOffset>
  1395. <bitWidth>1</bitWidth>
  1396. </field>
  1397. <field>
  1398. <name>CIRC</name>
  1399. <description>Circular mode</description>
  1400. <bitOffset>5</bitOffset>
  1401. <bitWidth>1</bitWidth>
  1402. </field>
  1403. <field>
  1404. <name>DIR</name>
  1405. <description>Data transfer direction</description>
  1406. <bitOffset>4</bitOffset>
  1407. <bitWidth>1</bitWidth>
  1408. </field>
  1409. <field>
  1410. <name>TEIE</name>
  1411. <description>Transfer error interrupt
  1412. enable</description>
  1413. <bitOffset>3</bitOffset>
  1414. <bitWidth>1</bitWidth>
  1415. </field>
  1416. <field>
  1417. <name>HTIE</name>
  1418. <description>Half transfer interrupt
  1419. enable</description>
  1420. <bitOffset>2</bitOffset>
  1421. <bitWidth>1</bitWidth>
  1422. </field>
  1423. <field>
  1424. <name>TCIE</name>
  1425. <description>Transfer complete interrupt
  1426. enable</description>
  1427. <bitOffset>1</bitOffset>
  1428. <bitWidth>1</bitWidth>
  1429. </field>
  1430. <field>
  1431. <name>EN</name>
  1432. <description>Channel enable</description>
  1433. <bitOffset>0</bitOffset>
  1434. <bitWidth>1</bitWidth>
  1435. </field>
  1436. </fields>
  1437. </register>
  1438. <register>
  1439. <name>CNDTR6</name>
  1440. <displayName>CNDTR6</displayName>
  1441. <description>channel x number of data
  1442. register</description>
  1443. <addressOffset>0x70</addressOffset>
  1444. <size>0x20</size>
  1445. <access>read-write</access>
  1446. <resetValue>0x00000000</resetValue>
  1447. <fields>
  1448. <field>
  1449. <name>NDT</name>
  1450. <description>Number of data to transfer</description>
  1451. <bitOffset>0</bitOffset>
  1452. <bitWidth>16</bitWidth>
  1453. </field>
  1454. </fields>
  1455. </register>
  1456. <register>
  1457. <name>CPAR6</name>
  1458. <displayName>CPAR6</displayName>
  1459. <description>channel x peripheral address
  1460. register</description>
  1461. <addressOffset>0x74</addressOffset>
  1462. <size>0x20</size>
  1463. <access>read-write</access>
  1464. <resetValue>0x00000000</resetValue>
  1465. <fields>
  1466. <field>
  1467. <name>PA</name>
  1468. <description>Peripheral address</description>
  1469. <bitOffset>0</bitOffset>
  1470. <bitWidth>32</bitWidth>
  1471. </field>
  1472. </fields>
  1473. </register>
  1474. <register>
  1475. <name>CMAR6</name>
  1476. <displayName>CMAR6</displayName>
  1477. <description>channel x memory address
  1478. register</description>
  1479. <addressOffset>0x78</addressOffset>
  1480. <size>0x20</size>
  1481. <access>read-write</access>
  1482. <resetValue>0x00000000</resetValue>
  1483. <fields>
  1484. <field>
  1485. <name>MA</name>
  1486. <description>Memory address</description>
  1487. <bitOffset>0</bitOffset>
  1488. <bitWidth>32</bitWidth>
  1489. </field>
  1490. </fields>
  1491. </register>
  1492. <register>
  1493. <name>CCR7</name>
  1494. <displayName>CCR7</displayName>
  1495. <description>channel x configuration
  1496. register</description>
  1497. <addressOffset>0x80</addressOffset>
  1498. <size>0x20</size>
  1499. <access>read-write</access>
  1500. <resetValue>0x00000000</resetValue>
  1501. <fields>
  1502. <field>
  1503. <name>MEM2MEM</name>
  1504. <description>Memory to memory mode</description>
  1505. <bitOffset>14</bitOffset>
  1506. <bitWidth>1</bitWidth>
  1507. </field>
  1508. <field>
  1509. <name>PL</name>
  1510. <description>Channel priority level</description>
  1511. <bitOffset>12</bitOffset>
  1512. <bitWidth>2</bitWidth>
  1513. </field>
  1514. <field>
  1515. <name>MSIZE</name>
  1516. <description>Memory size</description>
  1517. <bitOffset>10</bitOffset>
  1518. <bitWidth>2</bitWidth>
  1519. </field>
  1520. <field>
  1521. <name>PSIZE</name>
  1522. <description>Peripheral size</description>
  1523. <bitOffset>8</bitOffset>
  1524. <bitWidth>2</bitWidth>
  1525. </field>
  1526. <field>
  1527. <name>MINC</name>
  1528. <description>Memory increment mode</description>
  1529. <bitOffset>7</bitOffset>
  1530. <bitWidth>1</bitWidth>
  1531. </field>
  1532. <field>
  1533. <name>PINC</name>
  1534. <description>Peripheral increment mode</description>
  1535. <bitOffset>6</bitOffset>
  1536. <bitWidth>1</bitWidth>
  1537. </field>
  1538. <field>
  1539. <name>CIRC</name>
  1540. <description>Circular mode</description>
  1541. <bitOffset>5</bitOffset>
  1542. <bitWidth>1</bitWidth>
  1543. </field>
  1544. <field>
  1545. <name>DIR</name>
  1546. <description>Data transfer direction</description>
  1547. <bitOffset>4</bitOffset>
  1548. <bitWidth>1</bitWidth>
  1549. </field>
  1550. <field>
  1551. <name>TEIE</name>
  1552. <description>Transfer error interrupt
  1553. enable</description>
  1554. <bitOffset>3</bitOffset>
  1555. <bitWidth>1</bitWidth>
  1556. </field>
  1557. <field>
  1558. <name>HTIE</name>
  1559. <description>Half transfer interrupt
  1560. enable</description>
  1561. <bitOffset>2</bitOffset>
  1562. <bitWidth>1</bitWidth>
  1563. </field>
  1564. <field>
  1565. <name>TCIE</name>
  1566. <description>Transfer complete interrupt
  1567. enable</description>
  1568. <bitOffset>1</bitOffset>
  1569. <bitWidth>1</bitWidth>
  1570. </field>
  1571. <field>
  1572. <name>EN</name>
  1573. <description>Channel enable</description>
  1574. <bitOffset>0</bitOffset>
  1575. <bitWidth>1</bitWidth>
  1576. </field>
  1577. </fields>
  1578. </register>
  1579. <register>
  1580. <name>CNDTR7</name>
  1581. <displayName>CNDTR7</displayName>
  1582. <description>channel x number of data
  1583. register</description>
  1584. <addressOffset>0x84</addressOffset>
  1585. <size>0x20</size>
  1586. <access>read-write</access>
  1587. <resetValue>0x00000000</resetValue>
  1588. <fields>
  1589. <field>
  1590. <name>NDT</name>
  1591. <description>Number of data to transfer</description>
  1592. <bitOffset>0</bitOffset>
  1593. <bitWidth>16</bitWidth>
  1594. </field>
  1595. </fields>
  1596. </register>
  1597. <register>
  1598. <name>CPAR7</name>
  1599. <displayName>CPAR7</displayName>
  1600. <description>channel x peripheral address
  1601. register</description>
  1602. <addressOffset>0x88</addressOffset>
  1603. <size>0x20</size>
  1604. <access>read-write</access>
  1605. <resetValue>0x00000000</resetValue>
  1606. <fields>
  1607. <field>
  1608. <name>PA</name>
  1609. <description>Peripheral address</description>
  1610. <bitOffset>0</bitOffset>
  1611. <bitWidth>32</bitWidth>
  1612. </field>
  1613. </fields>
  1614. </register>
  1615. <register>
  1616. <name>CMAR7</name>
  1617. <displayName>CMAR7</displayName>
  1618. <description>channel x memory address
  1619. register</description>
  1620. <addressOffset>0x8C</addressOffset>
  1621. <size>0x20</size>
  1622. <access>read-write</access>
  1623. <resetValue>0x00000000</resetValue>
  1624. <fields>
  1625. <field>
  1626. <name>MA</name>
  1627. <description>Memory address</description>
  1628. <bitOffset>0</bitOffset>
  1629. <bitWidth>32</bitWidth>
  1630. </field>
  1631. </fields>
  1632. </register>
  1633. <register>
  1634. <name>CSELR</name>
  1635. <displayName>CSELR</displayName>
  1636. <description>channel selection register</description>
  1637. <addressOffset>0xA8</addressOffset>
  1638. <size>0x20</size>
  1639. <access>read-write</access>
  1640. <resetValue>0x00000000</resetValue>
  1641. <fields>
  1642. <field>
  1643. <name>C7S</name>
  1644. <description>DMA channel 7 selection</description>
  1645. <bitOffset>24</bitOffset>
  1646. <bitWidth>4</bitWidth>
  1647. </field>
  1648. <field>
  1649. <name>C6S</name>
  1650. <description>DMA channel 6 selection</description>
  1651. <bitOffset>20</bitOffset>
  1652. <bitWidth>4</bitWidth>
  1653. </field>
  1654. <field>
  1655. <name>C5S</name>
  1656. <description>DMA channel 5 selection</description>
  1657. <bitOffset>16</bitOffset>
  1658. <bitWidth>4</bitWidth>
  1659. </field>
  1660. <field>
  1661. <name>C4S</name>
  1662. <description>DMA channel 4 selection</description>
  1663. <bitOffset>12</bitOffset>
  1664. <bitWidth>4</bitWidth>
  1665. </field>
  1666. <field>
  1667. <name>C3S</name>
  1668. <description>DMA channel 3 selection</description>
  1669. <bitOffset>8</bitOffset>
  1670. <bitWidth>4</bitWidth>
  1671. </field>
  1672. <field>
  1673. <name>C2S</name>
  1674. <description>DMA channel 2 selection</description>
  1675. <bitOffset>4</bitOffset>
  1676. <bitWidth>4</bitWidth>
  1677. </field>
  1678. <field>
  1679. <name>C1S</name>
  1680. <description>DMA channel 1 selection</description>
  1681. <bitOffset>0</bitOffset>
  1682. <bitWidth>4</bitWidth>
  1683. </field>
  1684. </fields>
  1685. </register>
  1686. </registers>
  1687. </peripheral>
  1688. <peripheral>
  1689. <name>CRC</name>
  1690. <description>Cyclic redundancy check calculation
  1691. unit</description>
  1692. <groupName>CRC</groupName>
  1693. <baseAddress>0x40023000</baseAddress>
  1694. <addressBlock>
  1695. <offset>0x0</offset>
  1696. <size>0x400</size>
  1697. <usage>registers</usage>
  1698. </addressBlock>
  1699. <registers>
  1700. <register>
  1701. <name>DR</name>
  1702. <displayName>DR</displayName>
  1703. <description>Data register</description>
  1704. <addressOffset>0x0</addressOffset>
  1705. <size>0x20</size>
  1706. <access>read-write</access>
  1707. <resetValue>0xFFFFFFFF</resetValue>
  1708. <fields>
  1709. <field>
  1710. <name>DR</name>
  1711. <description>Data register bits</description>
  1712. <bitOffset>0</bitOffset>
  1713. <bitWidth>32</bitWidth>
  1714. </field>
  1715. </fields>
  1716. </register>
  1717. <register>
  1718. <name>IDR</name>
  1719. <displayName>IDR</displayName>
  1720. <description>Independent data register</description>
  1721. <addressOffset>0x4</addressOffset>
  1722. <size>0x20</size>
  1723. <access>read-write</access>
  1724. <resetValue>0x00000000</resetValue>
  1725. <fields>
  1726. <field>
  1727. <name>IDR</name>
  1728. <description>General-purpose 8-bit data register
  1729. bits</description>
  1730. <bitOffset>0</bitOffset>
  1731. <bitWidth>8</bitWidth>
  1732. </field>
  1733. </fields>
  1734. </register>
  1735. <register>
  1736. <name>CR</name>
  1737. <displayName>CR</displayName>
  1738. <description>Control register</description>
  1739. <addressOffset>0x8</addressOffset>
  1740. <size>0x20</size>
  1741. <resetValue>0x00000000</resetValue>
  1742. <fields>
  1743. <field>
  1744. <name>REV_OUT</name>
  1745. <description>Reverse output data</description>
  1746. <bitOffset>7</bitOffset>
  1747. <bitWidth>1</bitWidth>
  1748. <access>read-write</access>
  1749. </field>
  1750. <field>
  1751. <name>REV_IN</name>
  1752. <description>Reverse input data</description>
  1753. <bitOffset>5</bitOffset>
  1754. <bitWidth>2</bitWidth>
  1755. <access>read-write</access>
  1756. </field>
  1757. <field>
  1758. <name>POLYSIZE</name>
  1759. <description>Polynomial size</description>
  1760. <bitOffset>3</bitOffset>
  1761. <bitWidth>2</bitWidth>
  1762. <access>read-write</access>
  1763. </field>
  1764. <field>
  1765. <name>RESET</name>
  1766. <description>RESET bit</description>
  1767. <bitOffset>0</bitOffset>
  1768. <bitWidth>1</bitWidth>
  1769. <access>write-only</access>
  1770. </field>
  1771. </fields>
  1772. </register>
  1773. <register>
  1774. <name>INIT</name>
  1775. <displayName>INIT</displayName>
  1776. <description>Initial CRC value</description>
  1777. <addressOffset>0x10</addressOffset>
  1778. <size>0x20</size>
  1779. <access>read-write</access>
  1780. <resetValue>0xFFFFFFFF</resetValue>
  1781. <fields>
  1782. <field>
  1783. <name>CRC_INIT</name>
  1784. <description>Programmable initial CRC
  1785. value</description>
  1786. <bitOffset>0</bitOffset>
  1787. <bitWidth>32</bitWidth>
  1788. </field>
  1789. </fields>
  1790. </register>
  1791. <register>
  1792. <name>POL</name>
  1793. <displayName>POL</displayName>
  1794. <description>polynomial</description>
  1795. <addressOffset>0x14</addressOffset>
  1796. <size>0x20</size>
  1797. <access>read-write</access>
  1798. <resetValue>0x04C11DB7</resetValue>
  1799. <fields>
  1800. <field>
  1801. <name>Polynomialcoefficients</name>
  1802. <description>Programmable polynomial</description>
  1803. <bitOffset>0</bitOffset>
  1804. <bitWidth>32</bitWidth>
  1805. </field>
  1806. </fields>
  1807. </register>
  1808. </registers>
  1809. </peripheral>
  1810. <peripheral>
  1811. <name>GPIOA</name>
  1812. <description>General-purpose I/Os</description>
  1813. <groupName>GPIO</groupName>
  1814. <baseAddress>0x50000000</baseAddress>
  1815. <addressBlock>
  1816. <offset>0x0</offset>
  1817. <size>0x400</size>
  1818. <usage>registers</usage>
  1819. </addressBlock>
  1820. <registers>
  1821. <register>
  1822. <name>MODER</name>
  1823. <displayName>MODER</displayName>
  1824. <description>GPIO port mode register</description>
  1825. <addressOffset>0x0</addressOffset>
  1826. <size>0x20</size>
  1827. <access>read-write</access>
  1828. <resetValue>0xEBFFFCFF</resetValue>
  1829. <fields>
  1830. <field>
  1831. <name>MODE0</name>
  1832. <description>Port x configuration bits (y =
  1833. 0..15)</description>
  1834. <bitOffset>0</bitOffset>
  1835. <bitWidth>2</bitWidth>
  1836. </field>
  1837. <field>
  1838. <name>MODE1</name>
  1839. <description>Port x configuration bits (y =
  1840. 0..15)</description>
  1841. <bitOffset>2</bitOffset>
  1842. <bitWidth>2</bitWidth>
  1843. </field>
  1844. <field>
  1845. <name>MODE2</name>
  1846. <description>Port x configuration bits (y =
  1847. 0..15)</description>
  1848. <bitOffset>4</bitOffset>
  1849. <bitWidth>2</bitWidth>
  1850. </field>
  1851. <field>
  1852. <name>MODE3</name>
  1853. <description>Port x configuration bits (y =
  1854. 0..15)</description>
  1855. <bitOffset>6</bitOffset>
  1856. <bitWidth>2</bitWidth>
  1857. </field>
  1858. <field>
  1859. <name>MODE4</name>
  1860. <description>Port x configuration bits (y =
  1861. 0..15)</description>
  1862. <bitOffset>8</bitOffset>
  1863. <bitWidth>2</bitWidth>
  1864. </field>
  1865. <field>
  1866. <name>MODE5</name>
  1867. <description>Port x configuration bits (y =
  1868. 0..15)</description>
  1869. <bitOffset>10</bitOffset>
  1870. <bitWidth>2</bitWidth>
  1871. </field>
  1872. <field>
  1873. <name>MODE6</name>
  1874. <description>Port x configuration bits (y =
  1875. 0..15)</description>
  1876. <bitOffset>12</bitOffset>
  1877. <bitWidth>2</bitWidth>
  1878. </field>
  1879. <field>
  1880. <name>MODE7</name>
  1881. <description>Port x configuration bits (y =
  1882. 0..15)</description>
  1883. <bitOffset>14</bitOffset>
  1884. <bitWidth>2</bitWidth>
  1885. </field>
  1886. <field>
  1887. <name>MODE8</name>
  1888. <description>Port x configuration bits (y =
  1889. 0..15)</description>
  1890. <bitOffset>16</bitOffset>
  1891. <bitWidth>2</bitWidth>
  1892. </field>
  1893. <field>
  1894. <name>MODE9</name>
  1895. <description>Port x configuration bits (y =
  1896. 0..15)</description>
  1897. <bitOffset>18</bitOffset>
  1898. <bitWidth>2</bitWidth>
  1899. </field>
  1900. <field>
  1901. <name>MODE10</name>
  1902. <description>Port x configuration bits (y =
  1903. 0..15)</description>
  1904. <bitOffset>20</bitOffset>
  1905. <bitWidth>2</bitWidth>
  1906. </field>
  1907. <field>
  1908. <name>MODE11</name>
  1909. <description>Port x configuration bits (y =
  1910. 0..15)</description>
  1911. <bitOffset>22</bitOffset>
  1912. <bitWidth>2</bitWidth>
  1913. </field>
  1914. <field>
  1915. <name>MODE12</name>
  1916. <description>Port x configuration bits (y =
  1917. 0..15)</description>
  1918. <bitOffset>24</bitOffset>
  1919. <bitWidth>2</bitWidth>
  1920. </field>
  1921. <field>
  1922. <name>MODE13</name>
  1923. <description>Port x configuration bits (y =
  1924. 0..15)</description>
  1925. <bitOffset>26</bitOffset>
  1926. <bitWidth>2</bitWidth>
  1927. </field>
  1928. <field>
  1929. <name>MODE14</name>
  1930. <description>Port x configuration bits (y =
  1931. 0..15)</description>
  1932. <bitOffset>28</bitOffset>
  1933. <bitWidth>2</bitWidth>
  1934. </field>
  1935. <field>
  1936. <name>MODE15</name>
  1937. <description>Port x configuration bits (y =
  1938. 0..15)</description>
  1939. <bitOffset>30</bitOffset>
  1940. <bitWidth>2</bitWidth>
  1941. </field>
  1942. </fields>
  1943. </register>
  1944. <register>
  1945. <name>OTYPER</name>
  1946. <displayName>OTYPER</displayName>
  1947. <description>GPIO port output type register</description>
  1948. <addressOffset>0x4</addressOffset>
  1949. <size>0x20</size>
  1950. <access>read-write</access>
  1951. <resetValue>0x00000000</resetValue>
  1952. <fields>
  1953. <field>
  1954. <name>OT15</name>
  1955. <description>Port x configuration bits (y =
  1956. 0..15)</description>
  1957. <bitOffset>15</bitOffset>
  1958. <bitWidth>1</bitWidth>
  1959. </field>
  1960. <field>
  1961. <name>OT14</name>
  1962. <description>Port x configuration bits (y =
  1963. 0..15)</description>
  1964. <bitOffset>14</bitOffset>
  1965. <bitWidth>1</bitWidth>
  1966. </field>
  1967. <field>
  1968. <name>OT13</name>
  1969. <description>Port x configuration bits (y =
  1970. 0..15)</description>
  1971. <bitOffset>13</bitOffset>
  1972. <bitWidth>1</bitWidth>
  1973. </field>
  1974. <field>
  1975. <name>OT12</name>
  1976. <description>Port x configuration bits (y =
  1977. 0..15)</description>
  1978. <bitOffset>12</bitOffset>
  1979. <bitWidth>1</bitWidth>
  1980. </field>
  1981. <field>
  1982. <name>OT11</name>
  1983. <description>Port x configuration bits (y =
  1984. 0..15)</description>
  1985. <bitOffset>11</bitOffset>
  1986. <bitWidth>1</bitWidth>
  1987. </field>
  1988. <field>
  1989. <name>OT10</name>
  1990. <description>Port x configuration bits (y =
  1991. 0..15)</description>
  1992. <bitOffset>10</bitOffset>
  1993. <bitWidth>1</bitWidth>
  1994. </field>
  1995. <field>
  1996. <name>OT9</name>
  1997. <description>Port x configuration bits (y =
  1998. 0..15)</description>
  1999. <bitOffset>9</bitOffset>
  2000. <bitWidth>1</bitWidth>
  2001. </field>
  2002. <field>
  2003. <name>OT8</name>
  2004. <description>Port x configuration bits (y =
  2005. 0..15)</description>
  2006. <bitOffset>8</bitOffset>
  2007. <bitWidth>1</bitWidth>
  2008. </field>
  2009. <field>
  2010. <name>OT7</name>
  2011. <description>Port x configuration bits (y =
  2012. 0..15)</description>
  2013. <bitOffset>7</bitOffset>
  2014. <bitWidth>1</bitWidth>
  2015. </field>
  2016. <field>
  2017. <name>OT6</name>
  2018. <description>Port x configuration bits (y =
  2019. 0..15)</description>
  2020. <bitOffset>6</bitOffset>
  2021. <bitWidth>1</bitWidth>
  2022. </field>
  2023. <field>
  2024. <name>OT5</name>
  2025. <description>Port x configuration bits (y =
  2026. 0..15)</description>
  2027. <bitOffset>5</bitOffset>
  2028. <bitWidth>1</bitWidth>
  2029. </field>
  2030. <field>
  2031. <name>OT4</name>
  2032. <description>Port x configuration bits (y =
  2033. 0..15)</description>
  2034. <bitOffset>4</bitOffset>
  2035. <bitWidth>1</bitWidth>
  2036. </field>
  2037. <field>
  2038. <name>OT3</name>
  2039. <description>Port x configuration bits (y =
  2040. 0..15)</description>
  2041. <bitOffset>3</bitOffset>
  2042. <bitWidth>1</bitWidth>
  2043. </field>
  2044. <field>
  2045. <name>OT2</name>
  2046. <description>Port x configuration bits (y =
  2047. 0..15)</description>
  2048. <bitOffset>2</bitOffset>
  2049. <bitWidth>1</bitWidth>
  2050. </field>
  2051. <field>
  2052. <name>OT1</name>
  2053. <description>Port x configuration bits (y =
  2054. 0..15)</description>
  2055. <bitOffset>1</bitOffset>
  2056. <bitWidth>1</bitWidth>
  2057. </field>
  2058. <field>
  2059. <name>OT0</name>
  2060. <description>Port x configuration bits (y =
  2061. 0..15)</description>
  2062. <bitOffset>0</bitOffset>
  2063. <bitWidth>1</bitWidth>
  2064. </field>
  2065. </fields>
  2066. </register>
  2067. <register>
  2068. <name>OSPEEDR</name>
  2069. <displayName>OSPEEDR</displayName>
  2070. <description>GPIO port output speed
  2071. register</description>
  2072. <addressOffset>0x8</addressOffset>
  2073. <size>0x20</size>
  2074. <access>read-write</access>
  2075. <resetValue>0x00000000</resetValue>
  2076. <fields>
  2077. <field>
  2078. <name>OSPEED15</name>
  2079. <description>Port x configuration bits (y =
  2080. 0..15)</description>
  2081. <bitOffset>30</bitOffset>
  2082. <bitWidth>2</bitWidth>
  2083. </field>
  2084. <field>
  2085. <name>OSPEED14</name>
  2086. <description>Port x configuration bits (y =
  2087. 0..15)</description>
  2088. <bitOffset>28</bitOffset>
  2089. <bitWidth>2</bitWidth>
  2090. </field>
  2091. <field>
  2092. <name>OSPEED13</name>
  2093. <description>Port x configuration bits (y =
  2094. 0..15)</description>
  2095. <bitOffset>26</bitOffset>
  2096. <bitWidth>2</bitWidth>
  2097. </field>
  2098. <field>
  2099. <name>OSPEED12</name>
  2100. <description>Port x configuration bits (y =
  2101. 0..15)</description>
  2102. <bitOffset>24</bitOffset>
  2103. <bitWidth>2</bitWidth>
  2104. </field>
  2105. <field>
  2106. <name>OSPEED11</name>
  2107. <description>Port x configuration bits (y =
  2108. 0..15)</description>
  2109. <bitOffset>22</bitOffset>
  2110. <bitWidth>2</bitWidth>
  2111. </field>
  2112. <field>
  2113. <name>OSPEED10</name>
  2114. <description>Port x configuration bits (y =
  2115. 0..15)</description>
  2116. <bitOffset>20</bitOffset>
  2117. <bitWidth>2</bitWidth>
  2118. </field>
  2119. <field>
  2120. <name>OSPEED9</name>
  2121. <description>Port x configuration bits (y =
  2122. 0..15)</description>
  2123. <bitOffset>18</bitOffset>
  2124. <bitWidth>2</bitWidth>
  2125. </field>
  2126. <field>
  2127. <name>OSPEED8</name>
  2128. <description>Port x configuration bits (y =
  2129. 0..15)</description>
  2130. <bitOffset>16</bitOffset>
  2131. <bitWidth>2</bitWidth>
  2132. </field>
  2133. <field>
  2134. <name>OSPEED7</name>
  2135. <description>Port x configuration bits (y =
  2136. 0..15)</description>
  2137. <bitOffset>14</bitOffset>
  2138. <bitWidth>2</bitWidth>
  2139. </field>
  2140. <field>
  2141. <name>OSPEED6</name>
  2142. <description>Port x configuration bits (y =
  2143. 0..15)</description>
  2144. <bitOffset>12</bitOffset>
  2145. <bitWidth>2</bitWidth>
  2146. </field>
  2147. <field>
  2148. <name>OSPEED5</name>
  2149. <description>Port x configuration bits (y =
  2150. 0..15)</description>
  2151. <bitOffset>10</bitOffset>
  2152. <bitWidth>2</bitWidth>
  2153. </field>
  2154. <field>
  2155. <name>OSPEED4</name>
  2156. <description>Port x configuration bits (y =
  2157. 0..15)</description>
  2158. <bitOffset>8</bitOffset>
  2159. <bitWidth>2</bitWidth>
  2160. </field>
  2161. <field>
  2162. <name>OSPEED3</name>
  2163. <description>Port x configuration bits (y =
  2164. 0..15)</description>
  2165. <bitOffset>6</bitOffset>
  2166. <bitWidth>2</bitWidth>
  2167. </field>
  2168. <field>
  2169. <name>OSPEED2</name>
  2170. <description>Port x configuration bits (y =
  2171. 0..15)</description>
  2172. <bitOffset>4</bitOffset>
  2173. <bitWidth>2</bitWidth>
  2174. </field>
  2175. <field>
  2176. <name>OSPEED1</name>
  2177. <description>Port x configuration bits (y =
  2178. 0..15)</description>
  2179. <bitOffset>2</bitOffset>
  2180. <bitWidth>2</bitWidth>
  2181. </field>
  2182. <field>
  2183. <name>OSPEED0</name>
  2184. <description>Port x configuration bits (y =
  2185. 0..15)</description>
  2186. <bitOffset>0</bitOffset>
  2187. <bitWidth>2</bitWidth>
  2188. </field>
  2189. </fields>
  2190. </register>
  2191. <register>
  2192. <name>PUPDR</name>
  2193. <displayName>PUPDR</displayName>
  2194. <description>GPIO port pull-up/pull-down
  2195. register</description>
  2196. <addressOffset>0xC</addressOffset>
  2197. <size>0x20</size>
  2198. <access>read-write</access>
  2199. <resetValue>0x24000000</resetValue>
  2200. <fields>
  2201. <field>
  2202. <name>PUPD15</name>
  2203. <description>Port x configuration bits (y =
  2204. 0..15)</description>
  2205. <bitOffset>30</bitOffset>
  2206. <bitWidth>2</bitWidth>
  2207. </field>
  2208. <field>
  2209. <name>PUPD14</name>
  2210. <description>Port x configuration bits (y =
  2211. 0..15)</description>
  2212. <bitOffset>28</bitOffset>
  2213. <bitWidth>2</bitWidth>
  2214. </field>
  2215. <field>
  2216. <name>PUPD13</name>
  2217. <description>Port x configuration bits (y =
  2218. 0..15)</description>
  2219. <bitOffset>26</bitOffset>
  2220. <bitWidth>2</bitWidth>
  2221. </field>
  2222. <field>
  2223. <name>PUPD12</name>
  2224. <description>Port x configuration bits (y =
  2225. 0..15)</description>
  2226. <bitOffset>24</bitOffset>
  2227. <bitWidth>2</bitWidth>
  2228. </field>
  2229. <field>
  2230. <name>PUPD11</name>
  2231. <description>Port x configuration bits (y =
  2232. 0..15)</description>
  2233. <bitOffset>22</bitOffset>
  2234. <bitWidth>2</bitWidth>
  2235. </field>
  2236. <field>
  2237. <name>PUPD10</name>
  2238. <description>Port x configuration bits (y =
  2239. 0..15)</description>
  2240. <bitOffset>20</bitOffset>
  2241. <bitWidth>2</bitWidth>
  2242. </field>
  2243. <field>
  2244. <name>PUPD9</name>
  2245. <description>Port x configuration bits (y =
  2246. 0..15)</description>
  2247. <bitOffset>18</bitOffset>
  2248. <bitWidth>2</bitWidth>
  2249. </field>
  2250. <field>
  2251. <name>PUPD8</name>
  2252. <description>Port x configuration bits (y =
  2253. 0..15)</description>
  2254. <bitOffset>16</bitOffset>
  2255. <bitWidth>2</bitWidth>
  2256. </field>
  2257. <field>
  2258. <name>PUPD7</name>
  2259. <description>Port x configuration bits (y =
  2260. 0..15)</description>
  2261. <bitOffset>14</bitOffset>
  2262. <bitWidth>2</bitWidth>
  2263. </field>
  2264. <field>
  2265. <name>PUPD6</name>
  2266. <description>Port x configuration bits (y =
  2267. 0..15)</description>
  2268. <bitOffset>12</bitOffset>
  2269. <bitWidth>2</bitWidth>
  2270. </field>
  2271. <field>
  2272. <name>PUPD5</name>
  2273. <description>Port x configuration bits (y =
  2274. 0..15)</description>
  2275. <bitOffset>10</bitOffset>
  2276. <bitWidth>2</bitWidth>
  2277. </field>
  2278. <field>
  2279. <name>PUPD4</name>
  2280. <description>Port x configuration bits (y =
  2281. 0..15)</description>
  2282. <bitOffset>8</bitOffset>
  2283. <bitWidth>2</bitWidth>
  2284. </field>
  2285. <field>
  2286. <name>PUPD3</name>
  2287. <description>Port x configuration bits (y =
  2288. 0..15)</description>
  2289. <bitOffset>6</bitOffset>
  2290. <bitWidth>2</bitWidth>
  2291. </field>
  2292. <field>
  2293. <name>PUPD2</name>
  2294. <description>Port x configuration bits (y =
  2295. 0..15)</description>
  2296. <bitOffset>4</bitOffset>
  2297. <bitWidth>2</bitWidth>
  2298. </field>
  2299. <field>
  2300. <name>PUPD1</name>
  2301. <description>Port x configuration bits (y =
  2302. 0..15)</description>
  2303. <bitOffset>2</bitOffset>
  2304. <bitWidth>2</bitWidth>
  2305. </field>
  2306. <field>
  2307. <name>PUPD0</name>
  2308. <description>Port x configuration bits (y =
  2309. 0..15)</description>
  2310. <bitOffset>0</bitOffset>
  2311. <bitWidth>2</bitWidth>
  2312. </field>
  2313. </fields>
  2314. </register>
  2315. <register>
  2316. <name>IDR</name>
  2317. <displayName>IDR</displayName>
  2318. <description>GPIO port input data register</description>
  2319. <addressOffset>0x10</addressOffset>
  2320. <size>0x20</size>
  2321. <access>read-only</access>
  2322. <resetValue>0x00000000</resetValue>
  2323. <fields>
  2324. <field>
  2325. <name>ID15</name>
  2326. <description>Port input data bit (y =
  2327. 0..15)</description>
  2328. <bitOffset>15</bitOffset>
  2329. <bitWidth>1</bitWidth>
  2330. </field>
  2331. <field>
  2332. <name>ID14</name>
  2333. <description>Port input data bit (y =
  2334. 0..15)</description>
  2335. <bitOffset>14</bitOffset>
  2336. <bitWidth>1</bitWidth>
  2337. </field>
  2338. <field>
  2339. <name>ID13</name>
  2340. <description>Port input data bit (y =
  2341. 0..15)</description>
  2342. <bitOffset>13</bitOffset>
  2343. <bitWidth>1</bitWidth>
  2344. </field>
  2345. <field>
  2346. <name>ID12</name>
  2347. <description>Port input data bit (y =
  2348. 0..15)</description>
  2349. <bitOffset>12</bitOffset>
  2350. <bitWidth>1</bitWidth>
  2351. </field>
  2352. <field>
  2353. <name>ID11</name>
  2354. <description>Port input data bit (y =
  2355. 0..15)</description>
  2356. <bitOffset>11</bitOffset>
  2357. <bitWidth>1</bitWidth>
  2358. </field>
  2359. <field>
  2360. <name>ID10</name>
  2361. <description>Port input data bit (y =
  2362. 0..15)</description>
  2363. <bitOffset>10</bitOffset>
  2364. <bitWidth>1</bitWidth>
  2365. </field>
  2366. <field>
  2367. <name>ID9</name>
  2368. <description>Port input data bit (y =
  2369. 0..15)</description>
  2370. <bitOffset>9</bitOffset>
  2371. <bitWidth>1</bitWidth>
  2372. </field>
  2373. <field>
  2374. <name>ID8</name>
  2375. <description>Port input data bit (y =
  2376. 0..15)</description>
  2377. <bitOffset>8</bitOffset>
  2378. <bitWidth>1</bitWidth>
  2379. </field>
  2380. <field>
  2381. <name>ID7</name>
  2382. <description>Port input data bit (y =
  2383. 0..15)</description>
  2384. <bitOffset>7</bitOffset>
  2385. <bitWidth>1</bitWidth>
  2386. </field>
  2387. <field>
  2388. <name>ID6</name>
  2389. <description>Port input data bit (y =
  2390. 0..15)</description>
  2391. <bitOffset>6</bitOffset>
  2392. <bitWidth>1</bitWidth>
  2393. </field>
  2394. <field>
  2395. <name>ID5</name>
  2396. <description>Port input data bit (y =
  2397. 0..15)</description>
  2398. <bitOffset>5</bitOffset>
  2399. <bitWidth>1</bitWidth>
  2400. </field>
  2401. <field>
  2402. <name>ID4</name>
  2403. <description>Port input data bit (y =
  2404. 0..15)</description>
  2405. <bitOffset>4</bitOffset>
  2406. <bitWidth>1</bitWidth>
  2407. </field>
  2408. <field>
  2409. <name>ID3</name>
  2410. <description>Port input data bit (y =
  2411. 0..15)</description>
  2412. <bitOffset>3</bitOffset>
  2413. <bitWidth>1</bitWidth>
  2414. </field>
  2415. <field>
  2416. <name>ID2</name>
  2417. <description>Port input data bit (y =
  2418. 0..15)</description>
  2419. <bitOffset>2</bitOffset>
  2420. <bitWidth>1</bitWidth>
  2421. </field>
  2422. <field>
  2423. <name>ID1</name>
  2424. <description>Port input data bit (y =
  2425. 0..15)</description>
  2426. <bitOffset>1</bitOffset>
  2427. <bitWidth>1</bitWidth>
  2428. </field>
  2429. <field>
  2430. <name>ID0</name>
  2431. <description>Port input data bit (y =
  2432. 0..15)</description>
  2433. <bitOffset>0</bitOffset>
  2434. <bitWidth>1</bitWidth>
  2435. </field>
  2436. </fields>
  2437. </register>
  2438. <register>
  2439. <name>ODR</name>
  2440. <displayName>ODR</displayName>
  2441. <description>GPIO port output data register</description>
  2442. <addressOffset>0x14</addressOffset>
  2443. <size>0x20</size>
  2444. <access>read-write</access>
  2445. <resetValue>0x00000000</resetValue>
  2446. <fields>
  2447. <field>
  2448. <name>OD15</name>
  2449. <description>Port output data bit (y =
  2450. 0..15)</description>
  2451. <bitOffset>15</bitOffset>
  2452. <bitWidth>1</bitWidth>
  2453. </field>
  2454. <field>
  2455. <name>OD14</name>
  2456. <description>Port output data bit (y =
  2457. 0..15)</description>
  2458. <bitOffset>14</bitOffset>
  2459. <bitWidth>1</bitWidth>
  2460. </field>
  2461. <field>
  2462. <name>OD13</name>
  2463. <description>Port output data bit (y =
  2464. 0..15)</description>
  2465. <bitOffset>13</bitOffset>
  2466. <bitWidth>1</bitWidth>
  2467. </field>
  2468. <field>
  2469. <name>OD12</name>
  2470. <description>Port output data bit (y =
  2471. 0..15)</description>
  2472. <bitOffset>12</bitOffset>
  2473. <bitWidth>1</bitWidth>
  2474. </field>
  2475. <field>
  2476. <name>OD11</name>
  2477. <description>Port output data bit (y =
  2478. 0..15)</description>
  2479. <bitOffset>11</bitOffset>
  2480. <bitWidth>1</bitWidth>
  2481. </field>
  2482. <field>
  2483. <name>OD10</name>
  2484. <description>Port output data bit (y =
  2485. 0..15)</description>
  2486. <bitOffset>10</bitOffset>
  2487. <bitWidth>1</bitWidth>
  2488. </field>
  2489. <field>
  2490. <name>OD9</name>
  2491. <description>Port output data bit (y =
  2492. 0..15)</description>
  2493. <bitOffset>9</bitOffset>
  2494. <bitWidth>1</bitWidth>
  2495. </field>
  2496. <field>
  2497. <name>OD8</name>
  2498. <description>Port output data bit (y =
  2499. 0..15)</description>
  2500. <bitOffset>8</bitOffset>
  2501. <bitWidth>1</bitWidth>
  2502. </field>
  2503. <field>
  2504. <name>OD7</name>
  2505. <description>Port output data bit (y =
  2506. 0..15)</description>
  2507. <bitOffset>7</bitOffset>
  2508. <bitWidth>1</bitWidth>
  2509. </field>
  2510. <field>
  2511. <name>OD6</name>
  2512. <description>Port output data bit (y =
  2513. 0..15)</description>
  2514. <bitOffset>6</bitOffset>
  2515. <bitWidth>1</bitWidth>
  2516. </field>
  2517. <field>
  2518. <name>OD5</name>
  2519. <description>Port output data bit (y =
  2520. 0..15)</description>
  2521. <bitOffset>5</bitOffset>
  2522. <bitWidth>1</bitWidth>
  2523. </field>
  2524. <field>
  2525. <name>OD4</name>
  2526. <description>Port output data bit (y =
  2527. 0..15)</description>
  2528. <bitOffset>4</bitOffset>
  2529. <bitWidth>1</bitWidth>
  2530. </field>
  2531. <field>
  2532. <name>OD3</name>
  2533. <description>Port output data bit (y =
  2534. 0..15)</description>
  2535. <bitOffset>3</bitOffset>
  2536. <bitWidth>1</bitWidth>
  2537. </field>
  2538. <field>
  2539. <name>OD2</name>
  2540. <description>Port output data bit (y =
  2541. 0..15)</description>
  2542. <bitOffset>2</bitOffset>
  2543. <bitWidth>1</bitWidth>
  2544. </field>
  2545. <field>
  2546. <name>OD1</name>
  2547. <description>Port output data bit (y =
  2548. 0..15)</description>
  2549. <bitOffset>1</bitOffset>
  2550. <bitWidth>1</bitWidth>
  2551. </field>
  2552. <field>
  2553. <name>OD0</name>
  2554. <description>Port output data bit (y =
  2555. 0..15)</description>
  2556. <bitOffset>0</bitOffset>
  2557. <bitWidth>1</bitWidth>
  2558. </field>
  2559. </fields>
  2560. </register>
  2561. <register>
  2562. <name>BSRR</name>
  2563. <displayName>BSRR</displayName>
  2564. <description>GPIO port bit set/reset
  2565. register</description>
  2566. <addressOffset>0x18</addressOffset>
  2567. <size>0x20</size>
  2568. <access>write-only</access>
  2569. <resetValue>0x00000000</resetValue>
  2570. <fields>
  2571. <field>
  2572. <name>BR15</name>
  2573. <description>Port x reset bit y (y =
  2574. 0..15)</description>
  2575. <bitOffset>31</bitOffset>
  2576. <bitWidth>1</bitWidth>
  2577. </field>
  2578. <field>
  2579. <name>BR14</name>
  2580. <description>Port x reset bit y (y =
  2581. 0..15)</description>
  2582. <bitOffset>30</bitOffset>
  2583. <bitWidth>1</bitWidth>
  2584. </field>
  2585. <field>
  2586. <name>BR13</name>
  2587. <description>Port x reset bit y (y =
  2588. 0..15)</description>
  2589. <bitOffset>29</bitOffset>
  2590. <bitWidth>1</bitWidth>
  2591. </field>
  2592. <field>
  2593. <name>BR12</name>
  2594. <description>Port x reset bit y (y =
  2595. 0..15)</description>
  2596. <bitOffset>28</bitOffset>
  2597. <bitWidth>1</bitWidth>
  2598. </field>
  2599. <field>
  2600. <name>BR11</name>
  2601. <description>Port x reset bit y (y =
  2602. 0..15)</description>
  2603. <bitOffset>27</bitOffset>
  2604. <bitWidth>1</bitWidth>
  2605. </field>
  2606. <field>
  2607. <name>BR10</name>
  2608. <description>Port x reset bit y (y =
  2609. 0..15)</description>
  2610. <bitOffset>26</bitOffset>
  2611. <bitWidth>1</bitWidth>
  2612. </field>
  2613. <field>
  2614. <name>BR9</name>
  2615. <description>Port x reset bit y (y =
  2616. 0..15)</description>
  2617. <bitOffset>25</bitOffset>
  2618. <bitWidth>1</bitWidth>
  2619. </field>
  2620. <field>
  2621. <name>BR8</name>
  2622. <description>Port x reset bit y (y =
  2623. 0..15)</description>
  2624. <bitOffset>24</bitOffset>
  2625. <bitWidth>1</bitWidth>
  2626. </field>
  2627. <field>
  2628. <name>BR7</name>
  2629. <description>Port x reset bit y (y =
  2630. 0..15)</description>
  2631. <bitOffset>23</bitOffset>
  2632. <bitWidth>1</bitWidth>
  2633. </field>
  2634. <field>
  2635. <name>BR6</name>
  2636. <description>Port x reset bit y (y =
  2637. 0..15)</description>
  2638. <bitOffset>22</bitOffset>
  2639. <bitWidth>1</bitWidth>
  2640. </field>
  2641. <field>
  2642. <name>BR5</name>
  2643. <description>Port x reset bit y (y =
  2644. 0..15)</description>
  2645. <bitOffset>21</bitOffset>
  2646. <bitWidth>1</bitWidth>
  2647. </field>
  2648. <field>
  2649. <name>BR4</name>
  2650. <description>Port x reset bit y (y =
  2651. 0..15)</description>
  2652. <bitOffset>20</bitOffset>
  2653. <bitWidth>1</bitWidth>
  2654. </field>
  2655. <field>
  2656. <name>BR3</name>
  2657. <description>Port x reset bit y (y =
  2658. 0..15)</description>
  2659. <bitOffset>19</bitOffset>
  2660. <bitWidth>1</bitWidth>
  2661. </field>
  2662. <field>
  2663. <name>BR2</name>
  2664. <description>Port x reset bit y (y =
  2665. 0..15)</description>
  2666. <bitOffset>18</bitOffset>
  2667. <bitWidth>1</bitWidth>
  2668. </field>
  2669. <field>
  2670. <name>BR1</name>
  2671. <description>Port x reset bit y (y =
  2672. 0..15)</description>
  2673. <bitOffset>17</bitOffset>
  2674. <bitWidth>1</bitWidth>
  2675. </field>
  2676. <field>
  2677. <name>BR0</name>
  2678. <description>Port x reset bit y (y =
  2679. 0..15)</description>
  2680. <bitOffset>16</bitOffset>
  2681. <bitWidth>1</bitWidth>
  2682. </field>
  2683. <field>
  2684. <name>BS15</name>
  2685. <description>Port x set bit y (y=
  2686. 0..15)</description>
  2687. <bitOffset>15</bitOffset>
  2688. <bitWidth>1</bitWidth>
  2689. </field>
  2690. <field>
  2691. <name>BS14</name>
  2692. <description>Port x set bit y (y=
  2693. 0..15)</description>
  2694. <bitOffset>14</bitOffset>
  2695. <bitWidth>1</bitWidth>
  2696. </field>
  2697. <field>
  2698. <name>BS13</name>
  2699. <description>Port x set bit y (y=
  2700. 0..15)</description>
  2701. <bitOffset>13</bitOffset>
  2702. <bitWidth>1</bitWidth>
  2703. </field>
  2704. <field>
  2705. <name>BS12</name>
  2706. <description>Port x set bit y (y=
  2707. 0..15)</description>
  2708. <bitOffset>12</bitOffset>
  2709. <bitWidth>1</bitWidth>
  2710. </field>
  2711. <field>
  2712. <name>BS11</name>
  2713. <description>Port x set bit y (y=
  2714. 0..15)</description>
  2715. <bitOffset>11</bitOffset>
  2716. <bitWidth>1</bitWidth>
  2717. </field>
  2718. <field>
  2719. <name>BS10</name>
  2720. <description>Port x set bit y (y=
  2721. 0..15)</description>
  2722. <bitOffset>10</bitOffset>
  2723. <bitWidth>1</bitWidth>
  2724. </field>
  2725. <field>
  2726. <name>BS9</name>
  2727. <description>Port x set bit y (y=
  2728. 0..15)</description>
  2729. <bitOffset>9</bitOffset>
  2730. <bitWidth>1</bitWidth>
  2731. </field>
  2732. <field>
  2733. <name>BS8</name>
  2734. <description>Port x set bit y (y=
  2735. 0..15)</description>
  2736. <bitOffset>8</bitOffset>
  2737. <bitWidth>1</bitWidth>
  2738. </field>
  2739. <field>
  2740. <name>BS7</name>
  2741. <description>Port x set bit y (y=
  2742. 0..15)</description>
  2743. <bitOffset>7</bitOffset>
  2744. <bitWidth>1</bitWidth>
  2745. </field>
  2746. <field>
  2747. <name>BS6</name>
  2748. <description>Port x set bit y (y=
  2749. 0..15)</description>
  2750. <bitOffset>6</bitOffset>
  2751. <bitWidth>1</bitWidth>
  2752. </field>
  2753. <field>
  2754. <name>BS5</name>
  2755. <description>Port x set bit y (y=
  2756. 0..15)</description>
  2757. <bitOffset>5</bitOffset>
  2758. <bitWidth>1</bitWidth>
  2759. </field>
  2760. <field>
  2761. <name>BS4</name>
  2762. <description>Port x set bit y (y=
  2763. 0..15)</description>
  2764. <bitOffset>4</bitOffset>
  2765. <bitWidth>1</bitWidth>
  2766. </field>
  2767. <field>
  2768. <name>BS3</name>
  2769. <description>Port x set bit y (y=
  2770. 0..15)</description>
  2771. <bitOffset>3</bitOffset>
  2772. <bitWidth>1</bitWidth>
  2773. </field>
  2774. <field>
  2775. <name>BS2</name>
  2776. <description>Port x set bit y (y=
  2777. 0..15)</description>
  2778. <bitOffset>2</bitOffset>
  2779. <bitWidth>1</bitWidth>
  2780. </field>
  2781. <field>
  2782. <name>BS1</name>
  2783. <description>Port x set bit y (y=
  2784. 0..15)</description>
  2785. <bitOffset>1</bitOffset>
  2786. <bitWidth>1</bitWidth>
  2787. </field>
  2788. <field>
  2789. <name>BS0</name>
  2790. <description>Port x set bit y (y=
  2791. 0..15)</description>
  2792. <bitOffset>0</bitOffset>
  2793. <bitWidth>1</bitWidth>
  2794. </field>
  2795. </fields>
  2796. </register>
  2797. <register>
  2798. <name>LCKR</name>
  2799. <displayName>LCKR</displayName>
  2800. <description>GPIO port configuration lock
  2801. register</description>
  2802. <addressOffset>0x1C</addressOffset>
  2803. <size>0x20</size>
  2804. <access>read-write</access>
  2805. <resetValue>0x00000000</resetValue>
  2806. <fields>
  2807. <field>
  2808. <name>LCKK</name>
  2809. <description>Port x lock bit y (y=
  2810. 0..15)</description>
  2811. <bitOffset>16</bitOffset>
  2812. <bitWidth>1</bitWidth>
  2813. </field>
  2814. <field>
  2815. <name>LCK15</name>
  2816. <description>Port x lock bit y (y=
  2817. 0..15)</description>
  2818. <bitOffset>15</bitOffset>
  2819. <bitWidth>1</bitWidth>
  2820. </field>
  2821. <field>
  2822. <name>LCK14</name>
  2823. <description>Port x lock bit y (y=
  2824. 0..15)</description>
  2825. <bitOffset>14</bitOffset>
  2826. <bitWidth>1</bitWidth>
  2827. </field>
  2828. <field>
  2829. <name>LCK13</name>
  2830. <description>Port x lock bit y (y=
  2831. 0..15)</description>
  2832. <bitOffset>13</bitOffset>
  2833. <bitWidth>1</bitWidth>
  2834. </field>
  2835. <field>
  2836. <name>LCK12</name>
  2837. <description>Port x lock bit y (y=
  2838. 0..15)</description>
  2839. <bitOffset>12</bitOffset>
  2840. <bitWidth>1</bitWidth>
  2841. </field>
  2842. <field>
  2843. <name>LCK11</name>
  2844. <description>Port x lock bit y (y=
  2845. 0..15)</description>
  2846. <bitOffset>11</bitOffset>
  2847. <bitWidth>1</bitWidth>
  2848. </field>
  2849. <field>
  2850. <name>LCK10</name>
  2851. <description>Port x lock bit y (y=
  2852. 0..15)</description>
  2853. <bitOffset>10</bitOffset>
  2854. <bitWidth>1</bitWidth>
  2855. </field>
  2856. <field>
  2857. <name>LCK9</name>
  2858. <description>Port x lock bit y (y=
  2859. 0..15)</description>
  2860. <bitOffset>9</bitOffset>
  2861. <bitWidth>1</bitWidth>
  2862. </field>
  2863. <field>
  2864. <name>LCK8</name>
  2865. <description>Port x lock bit y (y=
  2866. 0..15)</description>
  2867. <bitOffset>8</bitOffset>
  2868. <bitWidth>1</bitWidth>
  2869. </field>
  2870. <field>
  2871. <name>LCK7</name>
  2872. <description>Port x lock bit y (y=
  2873. 0..15)</description>
  2874. <bitOffset>7</bitOffset>
  2875. <bitWidth>1</bitWidth>
  2876. </field>
  2877. <field>
  2878. <name>LCK6</name>
  2879. <description>Port x lock bit y (y=
  2880. 0..15)</description>
  2881. <bitOffset>6</bitOffset>
  2882. <bitWidth>1</bitWidth>
  2883. </field>
  2884. <field>
  2885. <name>LCK5</name>
  2886. <description>Port x lock bit y (y=
  2887. 0..15)</description>
  2888. <bitOffset>5</bitOffset>
  2889. <bitWidth>1</bitWidth>
  2890. </field>
  2891. <field>
  2892. <name>LCK4</name>
  2893. <description>Port x lock bit y (y=
  2894. 0..15)</description>
  2895. <bitOffset>4</bitOffset>
  2896. <bitWidth>1</bitWidth>
  2897. </field>
  2898. <field>
  2899. <name>LCK3</name>
  2900. <description>Port x lock bit y (y=
  2901. 0..15)</description>
  2902. <bitOffset>3</bitOffset>
  2903. <bitWidth>1</bitWidth>
  2904. </field>
  2905. <field>
  2906. <name>LCK2</name>
  2907. <description>Port x lock bit y (y=
  2908. 0..15)</description>
  2909. <bitOffset>2</bitOffset>
  2910. <bitWidth>1</bitWidth>
  2911. </field>
  2912. <field>
  2913. <name>LCK1</name>
  2914. <description>Port x lock bit y (y=
  2915. 0..15)</description>
  2916. <bitOffset>1</bitOffset>
  2917. <bitWidth>1</bitWidth>
  2918. </field>
  2919. <field>
  2920. <name>LCK0</name>
  2921. <description>Port x lock bit y (y=
  2922. 0..15)</description>
  2923. <bitOffset>0</bitOffset>
  2924. <bitWidth>1</bitWidth>
  2925. </field>
  2926. </fields>
  2927. </register>
  2928. <register>
  2929. <name>AFRL</name>
  2930. <displayName>AFRL</displayName>
  2931. <description>GPIO alternate function low
  2932. register</description>
  2933. <addressOffset>0x20</addressOffset>
  2934. <size>0x20</size>
  2935. <access>read-write</access>
  2936. <resetValue>0x00000000</resetValue>
  2937. <fields>
  2938. <field>
  2939. <name>AFSEL7</name>
  2940. <description>Alternate function selection for port x
  2941. pin y (y = 0..7)</description>
  2942. <bitOffset>28</bitOffset>
  2943. <bitWidth>4</bitWidth>
  2944. </field>
  2945. <field>
  2946. <name>AFSEL6</name>
  2947. <description>Alternate function selection for port x
  2948. pin y (y = 0..7)</description>
  2949. <bitOffset>24</bitOffset>
  2950. <bitWidth>4</bitWidth>
  2951. </field>
  2952. <field>
  2953. <name>AFSEL5</name>
  2954. <description>Alternate function selection for port x
  2955. pin y (y = 0..7)</description>
  2956. <bitOffset>20</bitOffset>
  2957. <bitWidth>4</bitWidth>
  2958. </field>
  2959. <field>
  2960. <name>AFSEL4</name>
  2961. <description>Alternate function selection for port x
  2962. pin y (y = 0..7)</description>
  2963. <bitOffset>16</bitOffset>
  2964. <bitWidth>4</bitWidth>
  2965. </field>
  2966. <field>
  2967. <name>AFSEL3</name>
  2968. <description>Alternate function selection for port x
  2969. pin y (y = 0..7)</description>
  2970. <bitOffset>12</bitOffset>
  2971. <bitWidth>4</bitWidth>
  2972. </field>
  2973. <field>
  2974. <name>AFSEL2</name>
  2975. <description>Alternate function selection for port x
  2976. pin y (y = 0..7)</description>
  2977. <bitOffset>8</bitOffset>
  2978. <bitWidth>4</bitWidth>
  2979. </field>
  2980. <field>
  2981. <name>AFSEL1</name>
  2982. <description>Alternate function selection for port x
  2983. pin y (y = 0..7)</description>
  2984. <bitOffset>4</bitOffset>
  2985. <bitWidth>4</bitWidth>
  2986. </field>
  2987. <field>
  2988. <name>AFSEL0</name>
  2989. <description>Alternate function selection for port x
  2990. pin y (y = 0..7)</description>
  2991. <bitOffset>0</bitOffset>
  2992. <bitWidth>4</bitWidth>
  2993. </field>
  2994. </fields>
  2995. </register>
  2996. <register>
  2997. <name>AFRH</name>
  2998. <displayName>AFRH</displayName>
  2999. <description>GPIO alternate function high
  3000. register</description>
  3001. <addressOffset>0x24</addressOffset>
  3002. <size>0x20</size>
  3003. <access>read-write</access>
  3004. <resetValue>0x00000000</resetValue>
  3005. <fields>
  3006. <field>
  3007. <name>AFSEL15</name>
  3008. <description>Alternate function selection for port x
  3009. pin y (y = 8..15)</description>
  3010. <bitOffset>28</bitOffset>
  3011. <bitWidth>4</bitWidth>
  3012. </field>
  3013. <field>
  3014. <name>AFSEL14</name>
  3015. <description>Alternate function selection for port x
  3016. pin y (y = 8..15)</description>
  3017. <bitOffset>24</bitOffset>
  3018. <bitWidth>4</bitWidth>
  3019. </field>
  3020. <field>
  3021. <name>AFSEL13</name>
  3022. <description>Alternate function selection for port x
  3023. pin y (y = 8..15)</description>
  3024. <bitOffset>20</bitOffset>
  3025. <bitWidth>4</bitWidth>
  3026. </field>
  3027. <field>
  3028. <name>AFSEL12</name>
  3029. <description>Alternate function selection for port x
  3030. pin y (y = 8..15)</description>
  3031. <bitOffset>16</bitOffset>
  3032. <bitWidth>4</bitWidth>
  3033. </field>
  3034. <field>
  3035. <name>AFSEL11</name>
  3036. <description>Alternate function selection for port x
  3037. pin y (y = 8..15)</description>
  3038. <bitOffset>12</bitOffset>
  3039. <bitWidth>4</bitWidth>
  3040. </field>
  3041. <field>
  3042. <name>AFSEL10</name>
  3043. <description>Alternate function selection for port x
  3044. pin y (y = 8..15)</description>
  3045. <bitOffset>8</bitOffset>
  3046. <bitWidth>4</bitWidth>
  3047. </field>
  3048. <field>
  3049. <name>AFSEL9</name>
  3050. <description>Alternate function selection for port x
  3051. pin y (y = 8..15)</description>
  3052. <bitOffset>4</bitOffset>
  3053. <bitWidth>4</bitWidth>
  3054. </field>
  3055. <field>
  3056. <name>AFSEL8</name>
  3057. <description>Alternate function selection for port x
  3058. pin y (y = 8..15)</description>
  3059. <bitOffset>0</bitOffset>
  3060. <bitWidth>4</bitWidth>
  3061. </field>
  3062. </fields>
  3063. </register>
  3064. <register>
  3065. <name>BRR</name>
  3066. <displayName>BRR</displayName>
  3067. <description>GPIO port bit reset register</description>
  3068. <addressOffset>0x28</addressOffset>
  3069. <size>0x20</size>
  3070. <access>write-only</access>
  3071. <resetValue>0x00000000</resetValue>
  3072. <fields>
  3073. <field>
  3074. <name>BR15</name>
  3075. <description>Port x Reset bit y (y= 0 ..
  3076. 15)</description>
  3077. <bitOffset>15</bitOffset>
  3078. <bitWidth>1</bitWidth>
  3079. </field>
  3080. <field>
  3081. <name>BR14</name>
  3082. <description>Port x Reset bit y (y= 0 ..
  3083. 15)</description>
  3084. <bitOffset>14</bitOffset>
  3085. <bitWidth>1</bitWidth>
  3086. </field>
  3087. <field>
  3088. <name>BR13</name>
  3089. <description>Port x Reset bit y (y= 0 ..
  3090. 15)</description>
  3091. <bitOffset>13</bitOffset>
  3092. <bitWidth>1</bitWidth>
  3093. </field>
  3094. <field>
  3095. <name>BR12</name>
  3096. <description>Port x Reset bit y (y= 0 ..
  3097. 15)</description>
  3098. <bitOffset>12</bitOffset>
  3099. <bitWidth>1</bitWidth>
  3100. </field>
  3101. <field>
  3102. <name>BR11</name>
  3103. <description>Port x Reset bit y (y= 0 ..
  3104. 15)</description>
  3105. <bitOffset>11</bitOffset>
  3106. <bitWidth>1</bitWidth>
  3107. </field>
  3108. <field>
  3109. <name>BR10</name>
  3110. <description>Port x Reset bit y (y= 0 ..
  3111. 15)</description>
  3112. <bitOffset>10</bitOffset>
  3113. <bitWidth>1</bitWidth>
  3114. </field>
  3115. <field>
  3116. <name>BR9</name>
  3117. <description>Port x Reset bit y (y= 0 ..
  3118. 15)</description>
  3119. <bitOffset>9</bitOffset>
  3120. <bitWidth>1</bitWidth>
  3121. </field>
  3122. <field>
  3123. <name>BR8</name>
  3124. <description>Port x Reset bit y (y= 0 ..
  3125. 15)</description>
  3126. <bitOffset>8</bitOffset>
  3127. <bitWidth>1</bitWidth>
  3128. </field>
  3129. <field>
  3130. <name>BR7</name>
  3131. <description>Port x Reset bit y (y= 0 ..
  3132. 15)</description>
  3133. <bitOffset>7</bitOffset>
  3134. <bitWidth>1</bitWidth>
  3135. </field>
  3136. <field>
  3137. <name>BR6</name>
  3138. <description>Port x Reset bit y (y= 0 ..
  3139. 15)</description>
  3140. <bitOffset>6</bitOffset>
  3141. <bitWidth>1</bitWidth>
  3142. </field>
  3143. <field>
  3144. <name>BR5</name>
  3145. <description>Port x Reset bit y (y= 0 ..
  3146. 15)</description>
  3147. <bitOffset>5</bitOffset>
  3148. <bitWidth>1</bitWidth>
  3149. </field>
  3150. <field>
  3151. <name>BR4</name>
  3152. <description>Port x Reset bit y (y= 0 ..
  3153. 15)</description>
  3154. <bitOffset>4</bitOffset>
  3155. <bitWidth>1</bitWidth>
  3156. </field>
  3157. <field>
  3158. <name>BR3</name>
  3159. <description>Port x Reset bit y (y= 0 ..
  3160. 15)</description>
  3161. <bitOffset>3</bitOffset>
  3162. <bitWidth>1</bitWidth>
  3163. </field>
  3164. <field>
  3165. <name>BR2</name>
  3166. <description>Port x Reset bit y (y= 0 ..
  3167. 15)</description>
  3168. <bitOffset>2</bitOffset>
  3169. <bitWidth>1</bitWidth>
  3170. </field>
  3171. <field>
  3172. <name>BR1</name>
  3173. <description>Port x Reset bit y (y= 0 ..
  3174. 15)</description>
  3175. <bitOffset>1</bitOffset>
  3176. <bitWidth>1</bitWidth>
  3177. </field>
  3178. <field>
  3179. <name>BR0</name>
  3180. <description>Port x Reset bit y (y= 0 ..
  3181. 15)</description>
  3182. <bitOffset>0</bitOffset>
  3183. <bitWidth>1</bitWidth>
  3184. </field>
  3185. </fields>
  3186. </register>
  3187. </registers>
  3188. </peripheral>
  3189. <peripheral>
  3190. <name>GPIOB</name>
  3191. <description>General-purpose I/Os</description>
  3192. <groupName>GPIO</groupName>
  3193. <baseAddress>0x50000400</baseAddress>
  3194. <addressBlock>
  3195. <offset>0x0</offset>
  3196. <size>0x400</size>
  3197. <usage>registers</usage>
  3198. </addressBlock>
  3199. <registers>
  3200. <register>
  3201. <name>MODER</name>
  3202. <displayName>MODER</displayName>
  3203. <description>GPIO port mode register</description>
  3204. <addressOffset>0x0</addressOffset>
  3205. <size>0x20</size>
  3206. <access>read-write</access>
  3207. <resetValue>0xFFFFFFFF</resetValue>
  3208. <fields>
  3209. <field>
  3210. <name>MODE15</name>
  3211. <description>Port x configuration bits (y =
  3212. 0..15)</description>
  3213. <bitOffset>30</bitOffset>
  3214. <bitWidth>2</bitWidth>
  3215. </field>
  3216. <field>
  3217. <name>MODE14</name>
  3218. <description>Port x configuration bits (y =
  3219. 0..15)</description>
  3220. <bitOffset>28</bitOffset>
  3221. <bitWidth>2</bitWidth>
  3222. </field>
  3223. <field>
  3224. <name>MODE13</name>
  3225. <description>Port x configuration bits (y =
  3226. 0..15)</description>
  3227. <bitOffset>26</bitOffset>
  3228. <bitWidth>2</bitWidth>
  3229. </field>
  3230. <field>
  3231. <name>MODE12</name>
  3232. <description>Port x configuration bits (y =
  3233. 0..15)</description>
  3234. <bitOffset>24</bitOffset>
  3235. <bitWidth>2</bitWidth>
  3236. </field>
  3237. <field>
  3238. <name>MODE11</name>
  3239. <description>Port x configuration bits (y =
  3240. 0..15)</description>
  3241. <bitOffset>22</bitOffset>
  3242. <bitWidth>2</bitWidth>
  3243. </field>
  3244. <field>
  3245. <name>MODE10</name>
  3246. <description>Port x configuration bits (y =
  3247. 0..15)</description>
  3248. <bitOffset>20</bitOffset>
  3249. <bitWidth>2</bitWidth>
  3250. </field>
  3251. <field>
  3252. <name>MODE9</name>
  3253. <description>Port x configuration bits (y =
  3254. 0..15)</description>
  3255. <bitOffset>18</bitOffset>
  3256. <bitWidth>2</bitWidth>
  3257. </field>
  3258. <field>
  3259. <name>MODE8</name>
  3260. <description>Port x configuration bits (y =
  3261. 0..15)</description>
  3262. <bitOffset>16</bitOffset>
  3263. <bitWidth>2</bitWidth>
  3264. </field>
  3265. <field>
  3266. <name>MODE7</name>
  3267. <description>Port x configuration bits (y =
  3268. 0..15)</description>
  3269. <bitOffset>14</bitOffset>
  3270. <bitWidth>2</bitWidth>
  3271. </field>
  3272. <field>
  3273. <name>MODE6</name>
  3274. <description>Port x configuration bits (y =
  3275. 0..15)</description>
  3276. <bitOffset>12</bitOffset>
  3277. <bitWidth>2</bitWidth>
  3278. </field>
  3279. <field>
  3280. <name>MODE5</name>
  3281. <description>Port x configuration bits (y =
  3282. 0..15)</description>
  3283. <bitOffset>10</bitOffset>
  3284. <bitWidth>2</bitWidth>
  3285. </field>
  3286. <field>
  3287. <name>MODE4</name>
  3288. <description>Port x configuration bits (y =
  3289. 0..15)</description>
  3290. <bitOffset>8</bitOffset>
  3291. <bitWidth>2</bitWidth>
  3292. </field>
  3293. <field>
  3294. <name>MODE3</name>
  3295. <description>Port x configuration bits (y =
  3296. 0..15)</description>
  3297. <bitOffset>6</bitOffset>
  3298. <bitWidth>2</bitWidth>
  3299. </field>
  3300. <field>
  3301. <name>MODE2</name>
  3302. <description>Port x configuration bits (y =
  3303. 0..15)</description>
  3304. <bitOffset>4</bitOffset>
  3305. <bitWidth>2</bitWidth>
  3306. </field>
  3307. <field>
  3308. <name>MODE1</name>
  3309. <description>Port x configuration bits (y =
  3310. 0..15)</description>
  3311. <bitOffset>2</bitOffset>
  3312. <bitWidth>2</bitWidth>
  3313. </field>
  3314. <field>
  3315. <name>MODE0</name>
  3316. <description>Port x configuration bits (y =
  3317. 0..15)</description>
  3318. <bitOffset>0</bitOffset>
  3319. <bitWidth>2</bitWidth>
  3320. </field>
  3321. </fields>
  3322. </register>
  3323. <register>
  3324. <name>OTYPER</name>
  3325. <displayName>OTYPER</displayName>
  3326. <description>GPIO port output type register</description>
  3327. <addressOffset>0x4</addressOffset>
  3328. <size>0x20</size>
  3329. <access>read-write</access>
  3330. <resetValue>0x00000000</resetValue>
  3331. <fields>
  3332. <field>
  3333. <name>OT15</name>
  3334. <description>Port x configuration bits (y =
  3335. 0..15)</description>
  3336. <bitOffset>15</bitOffset>
  3337. <bitWidth>1</bitWidth>
  3338. </field>
  3339. <field>
  3340. <name>OT14</name>
  3341. <description>Port x configuration bits (y =
  3342. 0..15)</description>
  3343. <bitOffset>14</bitOffset>
  3344. <bitWidth>1</bitWidth>
  3345. </field>
  3346. <field>
  3347. <name>OT13</name>
  3348. <description>Port x configuration bits (y =
  3349. 0..15)</description>
  3350. <bitOffset>13</bitOffset>
  3351. <bitWidth>1</bitWidth>
  3352. </field>
  3353. <field>
  3354. <name>OT12</name>
  3355. <description>Port x configuration bits (y =
  3356. 0..15)</description>
  3357. <bitOffset>12</bitOffset>
  3358. <bitWidth>1</bitWidth>
  3359. </field>
  3360. <field>
  3361. <name>OT11</name>
  3362. <description>Port x configuration bits (y =
  3363. 0..15)</description>
  3364. <bitOffset>11</bitOffset>
  3365. <bitWidth>1</bitWidth>
  3366. </field>
  3367. <field>
  3368. <name>OT10</name>
  3369. <description>Port x configuration bits (y =
  3370. 0..15)</description>
  3371. <bitOffset>10</bitOffset>
  3372. <bitWidth>1</bitWidth>
  3373. </field>
  3374. <field>
  3375. <name>OT9</name>
  3376. <description>Port x configuration bits (y =
  3377. 0..15)</description>
  3378. <bitOffset>9</bitOffset>
  3379. <bitWidth>1</bitWidth>
  3380. </field>
  3381. <field>
  3382. <name>OT8</name>
  3383. <description>Port x configuration bits (y =
  3384. 0..15)</description>
  3385. <bitOffset>8</bitOffset>
  3386. <bitWidth>1</bitWidth>
  3387. </field>
  3388. <field>
  3389. <name>OT7</name>
  3390. <description>Port x configuration bits (y =
  3391. 0..15)</description>
  3392. <bitOffset>7</bitOffset>
  3393. <bitWidth>1</bitWidth>
  3394. </field>
  3395. <field>
  3396. <name>OT6</name>
  3397. <description>Port x configuration bits (y =
  3398. 0..15)</description>
  3399. <bitOffset>6</bitOffset>
  3400. <bitWidth>1</bitWidth>
  3401. </field>
  3402. <field>
  3403. <name>OT5</name>
  3404. <description>Port x configuration bits (y =
  3405. 0..15)</description>
  3406. <bitOffset>5</bitOffset>
  3407. <bitWidth>1</bitWidth>
  3408. </field>
  3409. <field>
  3410. <name>OT4</name>
  3411. <description>Port x configuration bits (y =
  3412. 0..15)</description>
  3413. <bitOffset>4</bitOffset>
  3414. <bitWidth>1</bitWidth>
  3415. </field>
  3416. <field>
  3417. <name>OT3</name>
  3418. <description>Port x configuration bits (y =
  3419. 0..15)</description>
  3420. <bitOffset>3</bitOffset>
  3421. <bitWidth>1</bitWidth>
  3422. </field>
  3423. <field>
  3424. <name>OT2</name>
  3425. <description>Port x configuration bits (y =
  3426. 0..15)</description>
  3427. <bitOffset>2</bitOffset>
  3428. <bitWidth>1</bitWidth>
  3429. </field>
  3430. <field>
  3431. <name>OT1</name>
  3432. <description>Port x configuration bits (y =
  3433. 0..15)</description>
  3434. <bitOffset>1</bitOffset>
  3435. <bitWidth>1</bitWidth>
  3436. </field>
  3437. <field>
  3438. <name>OT0</name>
  3439. <description>Port x configuration bits (y =
  3440. 0..15)</description>
  3441. <bitOffset>0</bitOffset>
  3442. <bitWidth>1</bitWidth>
  3443. </field>
  3444. </fields>
  3445. </register>
  3446. <register>
  3447. <name>OSPEEDR</name>
  3448. <displayName>OSPEEDR</displayName>
  3449. <description>GPIO port output speed
  3450. register</description>
  3451. <addressOffset>0x8</addressOffset>
  3452. <size>0x20</size>
  3453. <access>read-write</access>
  3454. <resetValue>0x00000000</resetValue>
  3455. <fields>
  3456. <field>
  3457. <name>OSPEED15</name>
  3458. <description>Port x configuration bits (y =
  3459. 0..15)</description>
  3460. <bitOffset>30</bitOffset>
  3461. <bitWidth>2</bitWidth>
  3462. </field>
  3463. <field>
  3464. <name>OSPEED14</name>
  3465. <description>Port x configuration bits (y =
  3466. 0..15)</description>
  3467. <bitOffset>28</bitOffset>
  3468. <bitWidth>2</bitWidth>
  3469. </field>
  3470. <field>
  3471. <name>OSPEED13</name>
  3472. <description>Port x configuration bits (y =
  3473. 0..15)</description>
  3474. <bitOffset>26</bitOffset>
  3475. <bitWidth>2</bitWidth>
  3476. </field>
  3477. <field>
  3478. <name>OSPEED12</name>
  3479. <description>Port x configuration bits (y =
  3480. 0..15)</description>
  3481. <bitOffset>24</bitOffset>
  3482. <bitWidth>2</bitWidth>
  3483. </field>
  3484. <field>
  3485. <name>OSPEED11</name>
  3486. <description>Port x configuration bits (y =
  3487. 0..15)</description>
  3488. <bitOffset>22</bitOffset>
  3489. <bitWidth>2</bitWidth>
  3490. </field>
  3491. <field>
  3492. <name>OSPEED10</name>
  3493. <description>Port x configuration bits (y =
  3494. 0..15)</description>
  3495. <bitOffset>20</bitOffset>
  3496. <bitWidth>2</bitWidth>
  3497. </field>
  3498. <field>
  3499. <name>OSPEED9</name>
  3500. <description>Port x configuration bits (y =
  3501. 0..15)</description>
  3502. <bitOffset>18</bitOffset>
  3503. <bitWidth>2</bitWidth>
  3504. </field>
  3505. <field>
  3506. <name>OSPEED8</name>
  3507. <description>Port x configuration bits (y =
  3508. 0..15)</description>
  3509. <bitOffset>16</bitOffset>
  3510. <bitWidth>2</bitWidth>
  3511. </field>
  3512. <field>
  3513. <name>OSPEED7</name>
  3514. <description>Port x configuration bits (y =
  3515. 0..15)</description>
  3516. <bitOffset>14</bitOffset>
  3517. <bitWidth>2</bitWidth>
  3518. </field>
  3519. <field>
  3520. <name>OSPEED6</name>
  3521. <description>Port x configuration bits (y =
  3522. 0..15)</description>
  3523. <bitOffset>12</bitOffset>
  3524. <bitWidth>2</bitWidth>
  3525. </field>
  3526. <field>
  3527. <name>OSPEED5</name>
  3528. <description>Port x configuration bits (y =
  3529. 0..15)</description>
  3530. <bitOffset>10</bitOffset>
  3531. <bitWidth>2</bitWidth>
  3532. </field>
  3533. <field>
  3534. <name>OSPEED4</name>
  3535. <description>Port x configuration bits (y =
  3536. 0..15)</description>
  3537. <bitOffset>8</bitOffset>
  3538. <bitWidth>2</bitWidth>
  3539. </field>
  3540. <field>
  3541. <name>OSPEED3</name>
  3542. <description>Port x configuration bits (y =
  3543. 0..15)</description>
  3544. <bitOffset>6</bitOffset>
  3545. <bitWidth>2</bitWidth>
  3546. </field>
  3547. <field>
  3548. <name>OSPEED2</name>
  3549. <description>Port x configuration bits (y =
  3550. 0..15)</description>
  3551. <bitOffset>4</bitOffset>
  3552. <bitWidth>2</bitWidth>
  3553. </field>
  3554. <field>
  3555. <name>OSPEED1</name>
  3556. <description>Port x configuration bits (y =
  3557. 0..15)</description>
  3558. <bitOffset>2</bitOffset>
  3559. <bitWidth>2</bitWidth>
  3560. </field>
  3561. <field>
  3562. <name>OSPEED0</name>
  3563. <description>Port x configuration bits (y =
  3564. 0..15)</description>
  3565. <bitOffset>0</bitOffset>
  3566. <bitWidth>2</bitWidth>
  3567. </field>
  3568. </fields>
  3569. </register>
  3570. <register>
  3571. <name>PUPDR</name>
  3572. <displayName>PUPDR</displayName>
  3573. <description>GPIO port pull-up/pull-down
  3574. register</description>
  3575. <addressOffset>0xC</addressOffset>
  3576. <size>0x20</size>
  3577. <access>read-write</access>
  3578. <resetValue>0x00000000</resetValue>
  3579. <fields>
  3580. <field>
  3581. <name>PUPD15</name>
  3582. <description>Port x configuration bits (y =
  3583. 0..15)</description>
  3584. <bitOffset>30</bitOffset>
  3585. <bitWidth>2</bitWidth>
  3586. </field>
  3587. <field>
  3588. <name>PUPD14</name>
  3589. <description>Port x configuration bits (y =
  3590. 0..15)</description>
  3591. <bitOffset>28</bitOffset>
  3592. <bitWidth>2</bitWidth>
  3593. </field>
  3594. <field>
  3595. <name>PUPD13</name>
  3596. <description>Port x configuration bits (y =
  3597. 0..15)</description>
  3598. <bitOffset>26</bitOffset>
  3599. <bitWidth>2</bitWidth>
  3600. </field>
  3601. <field>
  3602. <name>PUPD12</name>
  3603. <description>Port x configuration bits (y =
  3604. 0..15)</description>
  3605. <bitOffset>24</bitOffset>
  3606. <bitWidth>2</bitWidth>
  3607. </field>
  3608. <field>
  3609. <name>PUPD11</name>
  3610. <description>Port x configuration bits (y =
  3611. 0..15)</description>
  3612. <bitOffset>22</bitOffset>
  3613. <bitWidth>2</bitWidth>
  3614. </field>
  3615. <field>
  3616. <name>PUPD10</name>
  3617. <description>Port x configuration bits (y =
  3618. 0..15)</description>
  3619. <bitOffset>20</bitOffset>
  3620. <bitWidth>2</bitWidth>
  3621. </field>
  3622. <field>
  3623. <name>PUPD9</name>
  3624. <description>Port x configuration bits (y =
  3625. 0..15)</description>
  3626. <bitOffset>18</bitOffset>
  3627. <bitWidth>2</bitWidth>
  3628. </field>
  3629. <field>
  3630. <name>PUPD8</name>
  3631. <description>Port x configuration bits (y =
  3632. 0..15)</description>
  3633. <bitOffset>16</bitOffset>
  3634. <bitWidth>2</bitWidth>
  3635. </field>
  3636. <field>
  3637. <name>PUPD7</name>
  3638. <description>Port x configuration bits (y =
  3639. 0..15)</description>
  3640. <bitOffset>14</bitOffset>
  3641. <bitWidth>2</bitWidth>
  3642. </field>
  3643. <field>
  3644. <name>PUPD6</name>
  3645. <description>Port x configuration bits (y =
  3646. 0..15)</description>
  3647. <bitOffset>12</bitOffset>
  3648. <bitWidth>2</bitWidth>
  3649. </field>
  3650. <field>
  3651. <name>PUPD5</name>
  3652. <description>Port x configuration bits (y =
  3653. 0..15)</description>
  3654. <bitOffset>10</bitOffset>
  3655. <bitWidth>2</bitWidth>
  3656. </field>
  3657. <field>
  3658. <name>PUPD4</name>
  3659. <description>Port x configuration bits (y =
  3660. 0..15)</description>
  3661. <bitOffset>8</bitOffset>
  3662. <bitWidth>2</bitWidth>
  3663. </field>
  3664. <field>
  3665. <name>PUPD3</name>
  3666. <description>Port x configuration bits (y =
  3667. 0..15)</description>
  3668. <bitOffset>6</bitOffset>
  3669. <bitWidth>2</bitWidth>
  3670. </field>
  3671. <field>
  3672. <name>PUPD2</name>
  3673. <description>Port x configuration bits (y =
  3674. 0..15)</description>
  3675. <bitOffset>4</bitOffset>
  3676. <bitWidth>2</bitWidth>
  3677. </field>
  3678. <field>
  3679. <name>PUPD1</name>
  3680. <description>Port x configuration bits (y =
  3681. 0..15)</description>
  3682. <bitOffset>2</bitOffset>
  3683. <bitWidth>2</bitWidth>
  3684. </field>
  3685. <field>
  3686. <name>PUPD0</name>
  3687. <description>Port x configuration bits (y =
  3688. 0..15)</description>
  3689. <bitOffset>0</bitOffset>
  3690. <bitWidth>2</bitWidth>
  3691. </field>
  3692. </fields>
  3693. </register>
  3694. <register>
  3695. <name>IDR</name>
  3696. <displayName>IDR</displayName>
  3697. <description>GPIO port input data register</description>
  3698. <addressOffset>0x10</addressOffset>
  3699. <size>0x20</size>
  3700. <access>read-only</access>
  3701. <resetValue>0x00000000</resetValue>
  3702. <fields>
  3703. <field>
  3704. <name>ID15</name>
  3705. <description>Port input data bit (y =
  3706. 0..15)</description>
  3707. <bitOffset>15</bitOffset>
  3708. <bitWidth>1</bitWidth>
  3709. </field>
  3710. <field>
  3711. <name>ID14</name>
  3712. <description>Port input data bit (y =
  3713. 0..15)</description>
  3714. <bitOffset>14</bitOffset>
  3715. <bitWidth>1</bitWidth>
  3716. </field>
  3717. <field>
  3718. <name>ID13</name>
  3719. <description>Port input data bit (y =
  3720. 0..15)</description>
  3721. <bitOffset>13</bitOffset>
  3722. <bitWidth>1</bitWidth>
  3723. </field>
  3724. <field>
  3725. <name>ID12</name>
  3726. <description>Port input data bit (y =
  3727. 0..15)</description>
  3728. <bitOffset>12</bitOffset>
  3729. <bitWidth>1</bitWidth>
  3730. </field>
  3731. <field>
  3732. <name>ID11</name>
  3733. <description>Port input data bit (y =
  3734. 0..15)</description>
  3735. <bitOffset>11</bitOffset>
  3736. <bitWidth>1</bitWidth>
  3737. </field>
  3738. <field>
  3739. <name>ID10</name>
  3740. <description>Port input data bit (y =
  3741. 0..15)</description>
  3742. <bitOffset>10</bitOffset>
  3743. <bitWidth>1</bitWidth>
  3744. </field>
  3745. <field>
  3746. <name>ID9</name>
  3747. <description>Port input data bit (y =
  3748. 0..15)</description>
  3749. <bitOffset>9</bitOffset>
  3750. <bitWidth>1</bitWidth>
  3751. </field>
  3752. <field>
  3753. <name>ID8</name>
  3754. <description>Port input data bit (y =
  3755. 0..15)</description>
  3756. <bitOffset>8</bitOffset>
  3757. <bitWidth>1</bitWidth>
  3758. </field>
  3759. <field>
  3760. <name>ID7</name>
  3761. <description>Port input data bit (y =
  3762. 0..15)</description>
  3763. <bitOffset>7</bitOffset>
  3764. <bitWidth>1</bitWidth>
  3765. </field>
  3766. <field>
  3767. <name>ID6</name>
  3768. <description>Port input data bit (y =
  3769. 0..15)</description>
  3770. <bitOffset>6</bitOffset>
  3771. <bitWidth>1</bitWidth>
  3772. </field>
  3773. <field>
  3774. <name>ID5</name>
  3775. <description>Port input data bit (y =
  3776. 0..15)</description>
  3777. <bitOffset>5</bitOffset>
  3778. <bitWidth>1</bitWidth>
  3779. </field>
  3780. <field>
  3781. <name>ID4</name>
  3782. <description>Port input data bit (y =
  3783. 0..15)</description>
  3784. <bitOffset>4</bitOffset>
  3785. <bitWidth>1</bitWidth>
  3786. </field>
  3787. <field>
  3788. <name>ID3</name>
  3789. <description>Port input data bit (y =
  3790. 0..15)</description>
  3791. <bitOffset>3</bitOffset>
  3792. <bitWidth>1</bitWidth>
  3793. </field>
  3794. <field>
  3795. <name>ID2</name>
  3796. <description>Port input data bit (y =
  3797. 0..15)</description>
  3798. <bitOffset>2</bitOffset>
  3799. <bitWidth>1</bitWidth>
  3800. </field>
  3801. <field>
  3802. <name>ID1</name>
  3803. <description>Port input data bit (y =
  3804. 0..15)</description>
  3805. <bitOffset>1</bitOffset>
  3806. <bitWidth>1</bitWidth>
  3807. </field>
  3808. <field>
  3809. <name>ID0</name>
  3810. <description>Port input data bit (y =
  3811. 0..15)</description>
  3812. <bitOffset>0</bitOffset>
  3813. <bitWidth>1</bitWidth>
  3814. </field>
  3815. </fields>
  3816. </register>
  3817. <register>
  3818. <name>ODR</name>
  3819. <displayName>ODR</displayName>
  3820. <description>GPIO port output data register</description>
  3821. <addressOffset>0x14</addressOffset>
  3822. <size>0x20</size>
  3823. <access>read-write</access>
  3824. <resetValue>0x00000000</resetValue>
  3825. <fields>
  3826. <field>
  3827. <name>OD15</name>
  3828. <description>Port output data bit (y =
  3829. 0..15)</description>
  3830. <bitOffset>15</bitOffset>
  3831. <bitWidth>1</bitWidth>
  3832. </field>
  3833. <field>
  3834. <name>OD14</name>
  3835. <description>Port output data bit (y =
  3836. 0..15)</description>
  3837. <bitOffset>14</bitOffset>
  3838. <bitWidth>1</bitWidth>
  3839. </field>
  3840. <field>
  3841. <name>OD13</name>
  3842. <description>Port output data bit (y =
  3843. 0..15)</description>
  3844. <bitOffset>13</bitOffset>
  3845. <bitWidth>1</bitWidth>
  3846. </field>
  3847. <field>
  3848. <name>OD12</name>
  3849. <description>Port output data bit (y =
  3850. 0..15)</description>
  3851. <bitOffset>12</bitOffset>
  3852. <bitWidth>1</bitWidth>
  3853. </field>
  3854. <field>
  3855. <name>OD11</name>
  3856. <description>Port output data bit (y =
  3857. 0..15)</description>
  3858. <bitOffset>11</bitOffset>
  3859. <bitWidth>1</bitWidth>
  3860. </field>
  3861. <field>
  3862. <name>OD10</name>
  3863. <description>Port output data bit (y =
  3864. 0..15)</description>
  3865. <bitOffset>10</bitOffset>
  3866. <bitWidth>1</bitWidth>
  3867. </field>
  3868. <field>
  3869. <name>OD9</name>
  3870. <description>Port output data bit (y =
  3871. 0..15)</description>
  3872. <bitOffset>9</bitOffset>
  3873. <bitWidth>1</bitWidth>
  3874. </field>
  3875. <field>
  3876. <name>OD8</name>
  3877. <description>Port output data bit (y =
  3878. 0..15)</description>
  3879. <bitOffset>8</bitOffset>
  3880. <bitWidth>1</bitWidth>
  3881. </field>
  3882. <field>
  3883. <name>OD7</name>
  3884. <description>Port output data bit (y =
  3885. 0..15)</description>
  3886. <bitOffset>7</bitOffset>
  3887. <bitWidth>1</bitWidth>
  3888. </field>
  3889. <field>
  3890. <name>OD6</name>
  3891. <description>Port output data bit (y =
  3892. 0..15)</description>
  3893. <bitOffset>6</bitOffset>
  3894. <bitWidth>1</bitWidth>
  3895. </field>
  3896. <field>
  3897. <name>OD5</name>
  3898. <description>Port output data bit (y =
  3899. 0..15)</description>
  3900. <bitOffset>5</bitOffset>
  3901. <bitWidth>1</bitWidth>
  3902. </field>
  3903. <field>
  3904. <name>OD4</name>
  3905. <description>Port output data bit (y =
  3906. 0..15)</description>
  3907. <bitOffset>4</bitOffset>
  3908. <bitWidth>1</bitWidth>
  3909. </field>
  3910. <field>
  3911. <name>OD3</name>
  3912. <description>Port output data bit (y =
  3913. 0..15)</description>
  3914. <bitOffset>3</bitOffset>
  3915. <bitWidth>1</bitWidth>
  3916. </field>
  3917. <field>
  3918. <name>OD2</name>
  3919. <description>Port output data bit (y =
  3920. 0..15)</description>
  3921. <bitOffset>2</bitOffset>
  3922. <bitWidth>1</bitWidth>
  3923. </field>
  3924. <field>
  3925. <name>OD1</name>
  3926. <description>Port output data bit (y =
  3927. 0..15)</description>
  3928. <bitOffset>1</bitOffset>
  3929. <bitWidth>1</bitWidth>
  3930. </field>
  3931. <field>
  3932. <name>OD0</name>
  3933. <description>Port output data bit (y =
  3934. 0..15)</description>
  3935. <bitOffset>0</bitOffset>
  3936. <bitWidth>1</bitWidth>
  3937. </field>
  3938. </fields>
  3939. </register>
  3940. <register>
  3941. <name>BSRR</name>
  3942. <displayName>BSRR</displayName>
  3943. <description>GPIO port bit set/reset
  3944. register</description>
  3945. <addressOffset>0x18</addressOffset>
  3946. <size>0x20</size>
  3947. <access>write-only</access>
  3948. <resetValue>0x00000000</resetValue>
  3949. <fields>
  3950. <field>
  3951. <name>BR15</name>
  3952. <description>Port x reset bit y (y =
  3953. 0..15)</description>
  3954. <bitOffset>31</bitOffset>
  3955. <bitWidth>1</bitWidth>
  3956. </field>
  3957. <field>
  3958. <name>BR14</name>
  3959. <description>Port x reset bit y (y =
  3960. 0..15)</description>
  3961. <bitOffset>30</bitOffset>
  3962. <bitWidth>1</bitWidth>
  3963. </field>
  3964. <field>
  3965. <name>BR13</name>
  3966. <description>Port x reset bit y (y =
  3967. 0..15)</description>
  3968. <bitOffset>29</bitOffset>
  3969. <bitWidth>1</bitWidth>
  3970. </field>
  3971. <field>
  3972. <name>BR12</name>
  3973. <description>Port x reset bit y (y =
  3974. 0..15)</description>
  3975. <bitOffset>28</bitOffset>
  3976. <bitWidth>1</bitWidth>
  3977. </field>
  3978. <field>
  3979. <name>BR11</name>
  3980. <description>Port x reset bit y (y =
  3981. 0..15)</description>
  3982. <bitOffset>27</bitOffset>
  3983. <bitWidth>1</bitWidth>
  3984. </field>
  3985. <field>
  3986. <name>BR10</name>
  3987. <description>Port x reset bit y (y =
  3988. 0..15)</description>
  3989. <bitOffset>26</bitOffset>
  3990. <bitWidth>1</bitWidth>
  3991. </field>
  3992. <field>
  3993. <name>BR9</name>
  3994. <description>Port x reset bit y (y =
  3995. 0..15)</description>
  3996. <bitOffset>25</bitOffset>
  3997. <bitWidth>1</bitWidth>
  3998. </field>
  3999. <field>
  4000. <name>BR8</name>
  4001. <description>Port x reset bit y (y =
  4002. 0..15)</description>
  4003. <bitOffset>24</bitOffset>
  4004. <bitWidth>1</bitWidth>
  4005. </field>
  4006. <field>
  4007. <name>BR7</name>
  4008. <description>Port x reset bit y (y =
  4009. 0..15)</description>
  4010. <bitOffset>23</bitOffset>
  4011. <bitWidth>1</bitWidth>
  4012. </field>
  4013. <field>
  4014. <name>BR6</name>
  4015. <description>Port x reset bit y (y =
  4016. 0..15)</description>
  4017. <bitOffset>22</bitOffset>
  4018. <bitWidth>1</bitWidth>
  4019. </field>
  4020. <field>
  4021. <name>BR5</name>
  4022. <description>Port x reset bit y (y =
  4023. 0..15)</description>
  4024. <bitOffset>21</bitOffset>
  4025. <bitWidth>1</bitWidth>
  4026. </field>
  4027. <field>
  4028. <name>BR4</name>
  4029. <description>Port x reset bit y (y =
  4030. 0..15)</description>
  4031. <bitOffset>20</bitOffset>
  4032. <bitWidth>1</bitWidth>
  4033. </field>
  4034. <field>
  4035. <name>BR3</name>
  4036. <description>Port x reset bit y (y =
  4037. 0..15)</description>
  4038. <bitOffset>19</bitOffset>
  4039. <bitWidth>1</bitWidth>
  4040. </field>
  4041. <field>
  4042. <name>BR2</name>
  4043. <description>Port x reset bit y (y =
  4044. 0..15)</description>
  4045. <bitOffset>18</bitOffset>
  4046. <bitWidth>1</bitWidth>
  4047. </field>
  4048. <field>
  4049. <name>BR1</name>
  4050. <description>Port x reset bit y (y =
  4051. 0..15)</description>
  4052. <bitOffset>17</bitOffset>
  4053. <bitWidth>1</bitWidth>
  4054. </field>
  4055. <field>
  4056. <name>BR0</name>
  4057. <description>Port x reset bit y (y =
  4058. 0..15)</description>
  4059. <bitOffset>16</bitOffset>
  4060. <bitWidth>1</bitWidth>
  4061. </field>
  4062. <field>
  4063. <name>BS15</name>
  4064. <description>Port x set bit y (y=
  4065. 0..15)</description>
  4066. <bitOffset>15</bitOffset>
  4067. <bitWidth>1</bitWidth>
  4068. </field>
  4069. <field>
  4070. <name>BS14</name>
  4071. <description>Port x set bit y (y=
  4072. 0..15)</description>
  4073. <bitOffset>14</bitOffset>
  4074. <bitWidth>1</bitWidth>
  4075. </field>
  4076. <field>
  4077. <name>BS13</name>
  4078. <description>Port x set bit y (y=
  4079. 0..15)</description>
  4080. <bitOffset>13</bitOffset>
  4081. <bitWidth>1</bitWidth>
  4082. </field>
  4083. <field>
  4084. <name>BS12</name>
  4085. <description>Port x set bit y (y=
  4086. 0..15)</description>
  4087. <bitOffset>12</bitOffset>
  4088. <bitWidth>1</bitWidth>
  4089. </field>
  4090. <field>
  4091. <name>BS11</name>
  4092. <description>Port x set bit y (y=
  4093. 0..15)</description>
  4094. <bitOffset>11</bitOffset>
  4095. <bitWidth>1</bitWidth>
  4096. </field>
  4097. <field>
  4098. <name>BS10</name>
  4099. <description>Port x set bit y (y=
  4100. 0..15)</description>
  4101. <bitOffset>10</bitOffset>
  4102. <bitWidth>1</bitWidth>
  4103. </field>
  4104. <field>
  4105. <name>BS9</name>
  4106. <description>Port x set bit y (y=
  4107. 0..15)</description>
  4108. <bitOffset>9</bitOffset>
  4109. <bitWidth>1</bitWidth>
  4110. </field>
  4111. <field>
  4112. <name>BS8</name>
  4113. <description>Port x set bit y (y=
  4114. 0..15)</description>
  4115. <bitOffset>8</bitOffset>
  4116. <bitWidth>1</bitWidth>
  4117. </field>
  4118. <field>
  4119. <name>BS7</name>
  4120. <description>Port x set bit y (y=
  4121. 0..15)</description>
  4122. <bitOffset>7</bitOffset>
  4123. <bitWidth>1</bitWidth>
  4124. </field>
  4125. <field>
  4126. <name>BS6</name>
  4127. <description>Port x set bit y (y=
  4128. 0..15)</description>
  4129. <bitOffset>6</bitOffset>
  4130. <bitWidth>1</bitWidth>
  4131. </field>
  4132. <field>
  4133. <name>BS5</name>
  4134. <description>Port x set bit y (y=
  4135. 0..15)</description>
  4136. <bitOffset>5</bitOffset>
  4137. <bitWidth>1</bitWidth>
  4138. </field>
  4139. <field>
  4140. <name>BS4</name>
  4141. <description>Port x set bit y (y=
  4142. 0..15)</description>
  4143. <bitOffset>4</bitOffset>
  4144. <bitWidth>1</bitWidth>
  4145. </field>
  4146. <field>
  4147. <name>BS3</name>
  4148. <description>Port x set bit y (y=
  4149. 0..15)</description>
  4150. <bitOffset>3</bitOffset>
  4151. <bitWidth>1</bitWidth>
  4152. </field>
  4153. <field>
  4154. <name>BS2</name>
  4155. <description>Port x set bit y (y=
  4156. 0..15)</description>
  4157. <bitOffset>2</bitOffset>
  4158. <bitWidth>1</bitWidth>
  4159. </field>
  4160. <field>
  4161. <name>BS1</name>
  4162. <description>Port x set bit y (y=
  4163. 0..15)</description>
  4164. <bitOffset>1</bitOffset>
  4165. <bitWidth>1</bitWidth>
  4166. </field>
  4167. <field>
  4168. <name>BS0</name>
  4169. <description>Port x set bit y (y=
  4170. 0..15)</description>
  4171. <bitOffset>0</bitOffset>
  4172. <bitWidth>1</bitWidth>
  4173. </field>
  4174. </fields>
  4175. </register>
  4176. <register>
  4177. <name>LCKR</name>
  4178. <displayName>LCKR</displayName>
  4179. <description>GPIO port configuration lock
  4180. register</description>
  4181. <addressOffset>0x1C</addressOffset>
  4182. <size>0x20</size>
  4183. <access>read-write</access>
  4184. <resetValue>0x00000000</resetValue>
  4185. <fields>
  4186. <field>
  4187. <name>LCKK</name>
  4188. <description>Port x lock bit y (y=
  4189. 0..15)</description>
  4190. <bitOffset>16</bitOffset>
  4191. <bitWidth>1</bitWidth>
  4192. </field>
  4193. <field>
  4194. <name>LCK15</name>
  4195. <description>Port x lock bit y (y=
  4196. 0..15)</description>
  4197. <bitOffset>15</bitOffset>
  4198. <bitWidth>1</bitWidth>
  4199. </field>
  4200. <field>
  4201. <name>LCK14</name>
  4202. <description>Port x lock bit y (y=
  4203. 0..15)</description>
  4204. <bitOffset>14</bitOffset>
  4205. <bitWidth>1</bitWidth>
  4206. </field>
  4207. <field>
  4208. <name>LCK13</name>
  4209. <description>Port x lock bit y (y=
  4210. 0..15)</description>
  4211. <bitOffset>13</bitOffset>
  4212. <bitWidth>1</bitWidth>
  4213. </field>
  4214. <field>
  4215. <name>LCK12</name>
  4216. <description>Port x lock bit y (y=
  4217. 0..15)</description>
  4218. <bitOffset>12</bitOffset>
  4219. <bitWidth>1</bitWidth>
  4220. </field>
  4221. <field>
  4222. <name>LCK11</name>
  4223. <description>Port x lock bit y (y=
  4224. 0..15)</description>
  4225. <bitOffset>11</bitOffset>
  4226. <bitWidth>1</bitWidth>
  4227. </field>
  4228. <field>
  4229. <name>LCK10</name>
  4230. <description>Port x lock bit y (y=
  4231. 0..15)</description>
  4232. <bitOffset>10</bitOffset>
  4233. <bitWidth>1</bitWidth>
  4234. </field>
  4235. <field>
  4236. <name>LCK9</name>
  4237. <description>Port x lock bit y (y=
  4238. 0..15)</description>
  4239. <bitOffset>9</bitOffset>
  4240. <bitWidth>1</bitWidth>
  4241. </field>
  4242. <field>
  4243. <name>LCK8</name>
  4244. <description>Port x lock bit y (y=
  4245. 0..15)</description>
  4246. <bitOffset>8</bitOffset>
  4247. <bitWidth>1</bitWidth>
  4248. </field>
  4249. <field>
  4250. <name>LCK7</name>
  4251. <description>Port x lock bit y (y=
  4252. 0..15)</description>
  4253. <bitOffset>7</bitOffset>
  4254. <bitWidth>1</bitWidth>
  4255. </field>
  4256. <field>
  4257. <name>LCK6</name>
  4258. <description>Port x lock bit y (y=
  4259. 0..15)</description>
  4260. <bitOffset>6</bitOffset>
  4261. <bitWidth>1</bitWidth>
  4262. </field>
  4263. <field>
  4264. <name>LCK5</name>
  4265. <description>Port x lock bit y (y=
  4266. 0..15)</description>
  4267. <bitOffset>5</bitOffset>
  4268. <bitWidth>1</bitWidth>
  4269. </field>
  4270. <field>
  4271. <name>LCK4</name>
  4272. <description>Port x lock bit y (y=
  4273. 0..15)</description>
  4274. <bitOffset>4</bitOffset>
  4275. <bitWidth>1</bitWidth>
  4276. </field>
  4277. <field>
  4278. <name>LCK3</name>
  4279. <description>Port x lock bit y (y=
  4280. 0..15)</description>
  4281. <bitOffset>3</bitOffset>
  4282. <bitWidth>1</bitWidth>
  4283. </field>
  4284. <field>
  4285. <name>LCK2</name>
  4286. <description>Port x lock bit y (y=
  4287. 0..15)</description>
  4288. <bitOffset>2</bitOffset>
  4289. <bitWidth>1</bitWidth>
  4290. </field>
  4291. <field>
  4292. <name>LCK1</name>
  4293. <description>Port x lock bit y (y=
  4294. 0..15)</description>
  4295. <bitOffset>1</bitOffset>
  4296. <bitWidth>1</bitWidth>
  4297. </field>
  4298. <field>
  4299. <name>LCK0</name>
  4300. <description>Port x lock bit y (y=
  4301. 0..15)</description>
  4302. <bitOffset>0</bitOffset>
  4303. <bitWidth>1</bitWidth>
  4304. </field>
  4305. </fields>
  4306. </register>
  4307. <register>
  4308. <name>AFRL</name>
  4309. <displayName>AFRL</displayName>
  4310. <description>GPIO alternate function low
  4311. register</description>
  4312. <addressOffset>0x20</addressOffset>
  4313. <size>0x20</size>
  4314. <access>read-write</access>
  4315. <resetValue>0x00000000</resetValue>
  4316. <fields>
  4317. <field>
  4318. <name>AFSEL7</name>
  4319. <description>Alternate function selection for port x
  4320. pin y (y = 0..7)</description>
  4321. <bitOffset>28</bitOffset>
  4322. <bitWidth>4</bitWidth>
  4323. </field>
  4324. <field>
  4325. <name>AFSEL6</name>
  4326. <description>Alternate function selection for port x
  4327. pin y (y = 0..7)</description>
  4328. <bitOffset>24</bitOffset>
  4329. <bitWidth>4</bitWidth>
  4330. </field>
  4331. <field>
  4332. <name>AFSEL5</name>
  4333. <description>Alternate function selection for port x
  4334. pin y (y = 0..7)</description>
  4335. <bitOffset>20</bitOffset>
  4336. <bitWidth>4</bitWidth>
  4337. </field>
  4338. <field>
  4339. <name>AFSEL4</name>
  4340. <description>Alternate function selection for port x
  4341. pin y (y = 0..7)</description>
  4342. <bitOffset>16</bitOffset>
  4343. <bitWidth>4</bitWidth>
  4344. </field>
  4345. <field>
  4346. <name>AFSEL3</name>
  4347. <description>Alternate function selection for port x
  4348. pin y (y = 0..7)</description>
  4349. <bitOffset>12</bitOffset>
  4350. <bitWidth>4</bitWidth>
  4351. </field>
  4352. <field>
  4353. <name>AFSEL2</name>
  4354. <description>Alternate function selection for port x
  4355. pin y (y = 0..7)</description>
  4356. <bitOffset>8</bitOffset>
  4357. <bitWidth>4</bitWidth>
  4358. </field>
  4359. <field>
  4360. <name>AFSEL1</name>
  4361. <description>Alternate function selection for port x
  4362. pin y (y = 0..7)</description>
  4363. <bitOffset>4</bitOffset>
  4364. <bitWidth>4</bitWidth>
  4365. </field>
  4366. <field>
  4367. <name>AFSEL0</name>
  4368. <description>Alternate function selection for port x
  4369. pin y (y = 0..7)</description>
  4370. <bitOffset>0</bitOffset>
  4371. <bitWidth>4</bitWidth>
  4372. </field>
  4373. </fields>
  4374. </register>
  4375. <register>
  4376. <name>AFRH</name>
  4377. <displayName>AFRH</displayName>
  4378. <description>GPIO alternate function high
  4379. register</description>
  4380. <addressOffset>0x24</addressOffset>
  4381. <size>0x20</size>
  4382. <access>read-write</access>
  4383. <resetValue>0x00000000</resetValue>
  4384. <fields>
  4385. <field>
  4386. <name>AFSEL15</name>
  4387. <description>Alternate function selection for port x
  4388. pin y (y = 8..15)</description>
  4389. <bitOffset>28</bitOffset>
  4390. <bitWidth>4</bitWidth>
  4391. </field>
  4392. <field>
  4393. <name>AFSEL14</name>
  4394. <description>Alternate function selection for port x
  4395. pin y (y = 8..15)</description>
  4396. <bitOffset>24</bitOffset>
  4397. <bitWidth>4</bitWidth>
  4398. </field>
  4399. <field>
  4400. <name>AFSEL13</name>
  4401. <description>Alternate function selection for port x
  4402. pin y (y = 8..15)</description>
  4403. <bitOffset>20</bitOffset>
  4404. <bitWidth>4</bitWidth>
  4405. </field>
  4406. <field>
  4407. <name>AFSEL12</name>
  4408. <description>Alternate function selection for port x
  4409. pin y (y = 8..15)</description>
  4410. <bitOffset>16</bitOffset>
  4411. <bitWidth>4</bitWidth>
  4412. </field>
  4413. <field>
  4414. <name>AFSEL11</name>
  4415. <description>Alternate function selection for port x
  4416. pin y (y = 8..15)</description>
  4417. <bitOffset>12</bitOffset>
  4418. <bitWidth>4</bitWidth>
  4419. </field>
  4420. <field>
  4421. <name>AFSEL10</name>
  4422. <description>Alternate function selection for port x
  4423. pin y (y = 8..15)</description>
  4424. <bitOffset>8</bitOffset>
  4425. <bitWidth>4</bitWidth>
  4426. </field>
  4427. <field>
  4428. <name>AFSEL9</name>
  4429. <description>Alternate function selection for port x
  4430. pin y (y = 8..15)</description>
  4431. <bitOffset>4</bitOffset>
  4432. <bitWidth>4</bitWidth>
  4433. </field>
  4434. <field>
  4435. <name>AFSEL8</name>
  4436. <description>Alternate function selection for port x
  4437. pin y (y = 8..15)</description>
  4438. <bitOffset>0</bitOffset>
  4439. <bitWidth>4</bitWidth>
  4440. </field>
  4441. </fields>
  4442. </register>
  4443. <register>
  4444. <name>BRR</name>
  4445. <displayName>BRR</displayName>
  4446. <description>GPIO port bit reset register</description>
  4447. <addressOffset>0x28</addressOffset>
  4448. <size>0x20</size>
  4449. <access>write-only</access>
  4450. <resetValue>0x00000000</resetValue>
  4451. <fields>
  4452. <field>
  4453. <name>BR15</name>
  4454. <description>Port x Reset bit y (y= 0 ..
  4455. 15)</description>
  4456. <bitOffset>15</bitOffset>
  4457. <bitWidth>1</bitWidth>
  4458. </field>
  4459. <field>
  4460. <name>BR14</name>
  4461. <description>Port x Reset bit y (y= 0 ..
  4462. 15)</description>
  4463. <bitOffset>14</bitOffset>
  4464. <bitWidth>1</bitWidth>
  4465. </field>
  4466. <field>
  4467. <name>BR13</name>
  4468. <description>Port x Reset bit y (y= 0 ..
  4469. 15)</description>
  4470. <bitOffset>13</bitOffset>
  4471. <bitWidth>1</bitWidth>
  4472. </field>
  4473. <field>
  4474. <name>BR12</name>
  4475. <description>Port x Reset bit y (y= 0 ..
  4476. 15)</description>
  4477. <bitOffset>12</bitOffset>
  4478. <bitWidth>1</bitWidth>
  4479. </field>
  4480. <field>
  4481. <name>BR11</name>
  4482. <description>Port x Reset bit y (y= 0 ..
  4483. 15)</description>
  4484. <bitOffset>11</bitOffset>
  4485. <bitWidth>1</bitWidth>
  4486. </field>
  4487. <field>
  4488. <name>BR10</name>
  4489. <description>Port x Reset bit y (y= 0 ..
  4490. 15)</description>
  4491. <bitOffset>10</bitOffset>
  4492. <bitWidth>1</bitWidth>
  4493. </field>
  4494. <field>
  4495. <name>BR9</name>
  4496. <description>Port x Reset bit y (y= 0 ..
  4497. 15)</description>
  4498. <bitOffset>9</bitOffset>
  4499. <bitWidth>1</bitWidth>
  4500. </field>
  4501. <field>
  4502. <name>BR8</name>
  4503. <description>Port x Reset bit y (y= 0 ..
  4504. 15)</description>
  4505. <bitOffset>8</bitOffset>
  4506. <bitWidth>1</bitWidth>
  4507. </field>
  4508. <field>
  4509. <name>BR7</name>
  4510. <description>Port x Reset bit y (y= 0 ..
  4511. 15)</description>
  4512. <bitOffset>7</bitOffset>
  4513. <bitWidth>1</bitWidth>
  4514. </field>
  4515. <field>
  4516. <name>BR6</name>
  4517. <description>Port x Reset bit y (y= 0 ..
  4518. 15)</description>
  4519. <bitOffset>6</bitOffset>
  4520. <bitWidth>1</bitWidth>
  4521. </field>
  4522. <field>
  4523. <name>BR5</name>
  4524. <description>Port x Reset bit y (y= 0 ..
  4525. 15)</description>
  4526. <bitOffset>5</bitOffset>
  4527. <bitWidth>1</bitWidth>
  4528. </field>
  4529. <field>
  4530. <name>BR4</name>
  4531. <description>Port x Reset bit y (y= 0 ..
  4532. 15)</description>
  4533. <bitOffset>4</bitOffset>
  4534. <bitWidth>1</bitWidth>
  4535. </field>
  4536. <field>
  4537. <name>BR3</name>
  4538. <description>Port x Reset bit y (y= 0 ..
  4539. 15)</description>
  4540. <bitOffset>3</bitOffset>
  4541. <bitWidth>1</bitWidth>
  4542. </field>
  4543. <field>
  4544. <name>BR2</name>
  4545. <description>Port x Reset bit y (y= 0 ..
  4546. 15)</description>
  4547. <bitOffset>2</bitOffset>
  4548. <bitWidth>1</bitWidth>
  4549. </field>
  4550. <field>
  4551. <name>BR1</name>
  4552. <description>Port x Reset bit y (y= 0 ..
  4553. 15)</description>
  4554. <bitOffset>1</bitOffset>
  4555. <bitWidth>1</bitWidth>
  4556. </field>
  4557. <field>
  4558. <name>BR0</name>
  4559. <description>Port x Reset bit y (y= 0 ..
  4560. 15)</description>
  4561. <bitOffset>0</bitOffset>
  4562. <bitWidth>1</bitWidth>
  4563. </field>
  4564. </fields>
  4565. </register>
  4566. </registers>
  4567. </peripheral>
  4568. <peripheral derivedFrom="GPIOB">
  4569. <name>GPIOC</name>
  4570. <baseAddress>0x50000800</baseAddress>
  4571. </peripheral>
  4572. <peripheral derivedFrom="GPIOB">
  4573. <name>GPIOD</name>
  4574. <baseAddress>0x50000C00</baseAddress>
  4575. </peripheral>
  4576. <peripheral derivedFrom="GPIOB">
  4577. <name>GPIOH</name>
  4578. <baseAddress>0x50001C00</baseAddress>
  4579. </peripheral>
  4580. <peripheral>
  4581. <name>LPTIM</name>
  4582. <description>Low power timer</description>
  4583. <groupName>LPTIM</groupName>
  4584. <baseAddress>0x40007C00</baseAddress>
  4585. <addressBlock>
  4586. <offset>0x0</offset>
  4587. <size>0x400</size>
  4588. <usage>registers</usage>
  4589. </addressBlock>
  4590. <interrupt>
  4591. <name>LPTIM1</name>
  4592. <description>LPTIMER1 interrupt through
  4593. EXTI29</description>
  4594. <value>13</value>
  4595. </interrupt>
  4596. <registers>
  4597. <register>
  4598. <name>ISR</name>
  4599. <displayName>ISR</displayName>
  4600. <description>Interrupt and Status Register</description>
  4601. <addressOffset>0x0</addressOffset>
  4602. <size>0x20</size>
  4603. <access>read-only</access>
  4604. <resetValue>0x00000000</resetValue>
  4605. <fields>
  4606. <field>
  4607. <name>DOWN</name>
  4608. <description>Counter direction change up to
  4609. down</description>
  4610. <bitOffset>6</bitOffset>
  4611. <bitWidth>1</bitWidth>
  4612. </field>
  4613. <field>
  4614. <name>UP</name>
  4615. <description>Counter direction change down to
  4616. up</description>
  4617. <bitOffset>5</bitOffset>
  4618. <bitWidth>1</bitWidth>
  4619. </field>
  4620. <field>
  4621. <name>ARROK</name>
  4622. <description>Autoreload register update
  4623. OK</description>
  4624. <bitOffset>4</bitOffset>
  4625. <bitWidth>1</bitWidth>
  4626. </field>
  4627. <field>
  4628. <name>CMPOK</name>
  4629. <description>Compare register update OK</description>
  4630. <bitOffset>3</bitOffset>
  4631. <bitWidth>1</bitWidth>
  4632. </field>
  4633. <field>
  4634. <name>EXTTRIG</name>
  4635. <description>External trigger edge
  4636. event</description>
  4637. <bitOffset>2</bitOffset>
  4638. <bitWidth>1</bitWidth>
  4639. </field>
  4640. <field>
  4641. <name>ARRM</name>
  4642. <description>Autoreload match</description>
  4643. <bitOffset>1</bitOffset>
  4644. <bitWidth>1</bitWidth>
  4645. </field>
  4646. <field>
  4647. <name>CMPM</name>
  4648. <description>Compare match</description>
  4649. <bitOffset>0</bitOffset>
  4650. <bitWidth>1</bitWidth>
  4651. </field>
  4652. </fields>
  4653. </register>
  4654. <register>
  4655. <name>ICR</name>
  4656. <displayName>ICR</displayName>
  4657. <description>Interrupt Clear Register</description>
  4658. <addressOffset>0x4</addressOffset>
  4659. <size>0x20</size>
  4660. <access>write-only</access>
  4661. <resetValue>0x00000000</resetValue>
  4662. <fields>
  4663. <field>
  4664. <name>DOWNCF</name>
  4665. <description>Direction change to down Clear
  4666. Flag</description>
  4667. <bitOffset>6</bitOffset>
  4668. <bitWidth>1</bitWidth>
  4669. </field>
  4670. <field>
  4671. <name>UPCF</name>
  4672. <description>Direction change to UP Clear
  4673. Flag</description>
  4674. <bitOffset>5</bitOffset>
  4675. <bitWidth>1</bitWidth>
  4676. </field>
  4677. <field>
  4678. <name>ARROKCF</name>
  4679. <description>Autoreload register update OK Clear
  4680. Flag</description>
  4681. <bitOffset>4</bitOffset>
  4682. <bitWidth>1</bitWidth>
  4683. </field>
  4684. <field>
  4685. <name>CMPOKCF</name>
  4686. <description>Compare register update OK Clear
  4687. Flag</description>
  4688. <bitOffset>3</bitOffset>
  4689. <bitWidth>1</bitWidth>
  4690. </field>
  4691. <field>
  4692. <name>EXTTRIGCF</name>
  4693. <description>External trigger valid edge Clear
  4694. Flag</description>
  4695. <bitOffset>2</bitOffset>
  4696. <bitWidth>1</bitWidth>
  4697. </field>
  4698. <field>
  4699. <name>ARRMCF</name>
  4700. <description>Autoreload match Clear
  4701. Flag</description>
  4702. <bitOffset>1</bitOffset>
  4703. <bitWidth>1</bitWidth>
  4704. </field>
  4705. <field>
  4706. <name>CMPMCF</name>
  4707. <description>compare match Clear Flag</description>
  4708. <bitOffset>0</bitOffset>
  4709. <bitWidth>1</bitWidth>
  4710. </field>
  4711. </fields>
  4712. </register>
  4713. <register>
  4714. <name>IER</name>
  4715. <displayName>IER</displayName>
  4716. <description>Interrupt Enable Register</description>
  4717. <addressOffset>0x8</addressOffset>
  4718. <size>0x20</size>
  4719. <access>read-write</access>
  4720. <resetValue>0x00000000</resetValue>
  4721. <fields>
  4722. <field>
  4723. <name>DOWNIE</name>
  4724. <description>Direction change to down Interrupt
  4725. Enable</description>
  4726. <bitOffset>6</bitOffset>
  4727. <bitWidth>1</bitWidth>
  4728. </field>
  4729. <field>
  4730. <name>UPIE</name>
  4731. <description>Direction change to UP Interrupt
  4732. Enable</description>
  4733. <bitOffset>5</bitOffset>
  4734. <bitWidth>1</bitWidth>
  4735. </field>
  4736. <field>
  4737. <name>ARROKIE</name>
  4738. <description>Autoreload register update OK Interrupt
  4739. Enable</description>
  4740. <bitOffset>4</bitOffset>
  4741. <bitWidth>1</bitWidth>
  4742. </field>
  4743. <field>
  4744. <name>CMPOKIE</name>
  4745. <description>Compare register update OK Interrupt
  4746. Enable</description>
  4747. <bitOffset>3</bitOffset>
  4748. <bitWidth>1</bitWidth>
  4749. </field>
  4750. <field>
  4751. <name>EXTTRIGIE</name>
  4752. <description>External trigger valid edge Interrupt
  4753. Enable</description>
  4754. <bitOffset>2</bitOffset>
  4755. <bitWidth>1</bitWidth>
  4756. </field>
  4757. <field>
  4758. <name>ARRMIE</name>
  4759. <description>Autoreload match Interrupt
  4760. Enable</description>
  4761. <bitOffset>1</bitOffset>
  4762. <bitWidth>1</bitWidth>
  4763. </field>
  4764. <field>
  4765. <name>CMPMIE</name>
  4766. <description>Compare match Interrupt
  4767. Enable</description>
  4768. <bitOffset>0</bitOffset>
  4769. <bitWidth>1</bitWidth>
  4770. </field>
  4771. </fields>
  4772. </register>
  4773. <register>
  4774. <name>CFGR</name>
  4775. <displayName>CFGR</displayName>
  4776. <description>Configuration Register</description>
  4777. <addressOffset>0xC</addressOffset>
  4778. <size>0x20</size>
  4779. <access>read-write</access>
  4780. <resetValue>0x00000000</resetValue>
  4781. <fields>
  4782. <field>
  4783. <name>ENC</name>
  4784. <description>Encoder mode enable</description>
  4785. <bitOffset>24</bitOffset>
  4786. <bitWidth>1</bitWidth>
  4787. </field>
  4788. <field>
  4789. <name>COUNTMODE</name>
  4790. <description>counter mode enabled</description>
  4791. <bitOffset>23</bitOffset>
  4792. <bitWidth>1</bitWidth>
  4793. </field>
  4794. <field>
  4795. <name>PRELOAD</name>
  4796. <description>Registers update mode</description>
  4797. <bitOffset>22</bitOffset>
  4798. <bitWidth>1</bitWidth>
  4799. </field>
  4800. <field>
  4801. <name>WAVPOL</name>
  4802. <description>Waveform shape polarity</description>
  4803. <bitOffset>21</bitOffset>
  4804. <bitWidth>1</bitWidth>
  4805. </field>
  4806. <field>
  4807. <name>WAVE</name>
  4808. <description>Waveform shape</description>
  4809. <bitOffset>20</bitOffset>
  4810. <bitWidth>1</bitWidth>
  4811. </field>
  4812. <field>
  4813. <name>TIMOUT</name>
  4814. <description>Timeout enable</description>
  4815. <bitOffset>19</bitOffset>
  4816. <bitWidth>1</bitWidth>
  4817. </field>
  4818. <field>
  4819. <name>TRIGEN</name>
  4820. <description>Trigger enable and
  4821. polarity</description>
  4822. <bitOffset>17</bitOffset>
  4823. <bitWidth>2</bitWidth>
  4824. </field>
  4825. <field>
  4826. <name>TRIGSEL</name>
  4827. <description>Trigger selector</description>
  4828. <bitOffset>13</bitOffset>
  4829. <bitWidth>3</bitWidth>
  4830. </field>
  4831. <field>
  4832. <name>PRESC</name>
  4833. <description>Clock prescaler</description>
  4834. <bitOffset>9</bitOffset>
  4835. <bitWidth>3</bitWidth>
  4836. </field>
  4837. <field>
  4838. <name>TRGFLT</name>
  4839. <description>Configurable digital filter for
  4840. trigger</description>
  4841. <bitOffset>6</bitOffset>
  4842. <bitWidth>2</bitWidth>
  4843. </field>
  4844. <field>
  4845. <name>CKFLT</name>
  4846. <description>Configurable digital filter for external
  4847. clock</description>
  4848. <bitOffset>3</bitOffset>
  4849. <bitWidth>2</bitWidth>
  4850. </field>
  4851. <field>
  4852. <name>CKPOL</name>
  4853. <description>Clock Polarity</description>
  4854. <bitOffset>1</bitOffset>
  4855. <bitWidth>2</bitWidth>
  4856. </field>
  4857. <field>
  4858. <name>CKSEL</name>
  4859. <description>Clock selector</description>
  4860. <bitOffset>0</bitOffset>
  4861. <bitWidth>1</bitWidth>
  4862. </field>
  4863. </fields>
  4864. </register>
  4865. <register>
  4866. <name>CR</name>
  4867. <displayName>CR</displayName>
  4868. <description>Control Register</description>
  4869. <addressOffset>0x10</addressOffset>
  4870. <size>0x20</size>
  4871. <access>read-write</access>
  4872. <resetValue>0x00000000</resetValue>
  4873. <fields>
  4874. <field>
  4875. <name>CNTSTRT</name>
  4876. <description>Timer start in continuous
  4877. mode</description>
  4878. <bitOffset>2</bitOffset>
  4879. <bitWidth>1</bitWidth>
  4880. </field>
  4881. <field>
  4882. <name>SNGSTRT</name>
  4883. <description>LPTIM start in single mode</description>
  4884. <bitOffset>1</bitOffset>
  4885. <bitWidth>1</bitWidth>
  4886. </field>
  4887. <field>
  4888. <name>ENABLE</name>
  4889. <description>LPTIM Enable</description>
  4890. <bitOffset>0</bitOffset>
  4891. <bitWidth>1</bitWidth>
  4892. </field>
  4893. </fields>
  4894. </register>
  4895. <register>
  4896. <name>CMP</name>
  4897. <displayName>CMP</displayName>
  4898. <description>Compare Register</description>
  4899. <addressOffset>0x14</addressOffset>
  4900. <size>0x20</size>
  4901. <access>read-write</access>
  4902. <resetValue>0x00000000</resetValue>
  4903. <fields>
  4904. <field>
  4905. <name>CMP</name>
  4906. <description>Compare value.</description>
  4907. <bitOffset>0</bitOffset>
  4908. <bitWidth>16</bitWidth>
  4909. </field>
  4910. </fields>
  4911. </register>
  4912. <register>
  4913. <name>ARR</name>
  4914. <displayName>ARR</displayName>
  4915. <description>Autoreload Register</description>
  4916. <addressOffset>0x18</addressOffset>
  4917. <size>0x20</size>
  4918. <access>read-write</access>
  4919. <resetValue>0x00000001</resetValue>
  4920. <fields>
  4921. <field>
  4922. <name>ARR</name>
  4923. <description>Auto reload value.</description>
  4924. <bitOffset>0</bitOffset>
  4925. <bitWidth>16</bitWidth>
  4926. </field>
  4927. </fields>
  4928. </register>
  4929. <register>
  4930. <name>CNT</name>
  4931. <displayName>CNT</displayName>
  4932. <description>Counter Register</description>
  4933. <addressOffset>0x1C</addressOffset>
  4934. <size>0x20</size>
  4935. <access>read-only</access>
  4936. <resetValue>0x00000000</resetValue>
  4937. <fields>
  4938. <field>
  4939. <name>CNT</name>
  4940. <description>Counter value.</description>
  4941. <bitOffset>0</bitOffset>
  4942. <bitWidth>16</bitWidth>
  4943. </field>
  4944. </fields>
  4945. </register>
  4946. </registers>
  4947. </peripheral>
  4948. <peripheral>
  4949. <name>RNG</name>
  4950. <description>Random number generator</description>
  4951. <groupName>RNG</groupName>
  4952. <baseAddress>0x40025000</baseAddress>
  4953. <addressBlock>
  4954. <offset>0x0</offset>
  4955. <size>0x400</size>
  4956. <usage>registers</usage>
  4957. </addressBlock>
  4958. <registers>
  4959. <register>
  4960. <name>CR</name>
  4961. <displayName>CR</displayName>
  4962. <description>control register</description>
  4963. <addressOffset>0x0</addressOffset>
  4964. <size>0x20</size>
  4965. <access>read-write</access>
  4966. <resetValue>0x00000000</resetValue>
  4967. <fields>
  4968. <field>
  4969. <name>IE</name>
  4970. <description>Interrupt enable</description>
  4971. <bitOffset>3</bitOffset>
  4972. <bitWidth>1</bitWidth>
  4973. </field>
  4974. <field>
  4975. <name>RNGEN</name>
  4976. <description>Random number generator
  4977. enable</description>
  4978. <bitOffset>2</bitOffset>
  4979. <bitWidth>1</bitWidth>
  4980. </field>
  4981. </fields>
  4982. </register>
  4983. <register>
  4984. <name>SR</name>
  4985. <displayName>SR</displayName>
  4986. <description>status register</description>
  4987. <addressOffset>0x4</addressOffset>
  4988. <size>0x20</size>
  4989. <resetValue>0x00000000</resetValue>
  4990. <fields>
  4991. <field>
  4992. <name>SEIS</name>
  4993. <description>Seed error interrupt
  4994. status</description>
  4995. <bitOffset>6</bitOffset>
  4996. <bitWidth>1</bitWidth>
  4997. <access>read-write</access>
  4998. </field>
  4999. <field>
  5000. <name>CEIS</name>
  5001. <description>Clock error interrupt
  5002. status</description>
  5003. <bitOffset>5</bitOffset>
  5004. <bitWidth>1</bitWidth>
  5005. <access>read-write</access>
  5006. </field>
  5007. <field>
  5008. <name>SECS</name>
  5009. <description>Seed error current status</description>
  5010. <bitOffset>2</bitOffset>
  5011. <bitWidth>1</bitWidth>
  5012. <access>read-only</access>
  5013. </field>
  5014. <field>
  5015. <name>CECS</name>
  5016. <description>Clock error current status</description>
  5017. <bitOffset>1</bitOffset>
  5018. <bitWidth>1</bitWidth>
  5019. <access>read-only</access>
  5020. </field>
  5021. <field>
  5022. <name>DRDY</name>
  5023. <description>Data ready</description>
  5024. <bitOffset>0</bitOffset>
  5025. <bitWidth>1</bitWidth>
  5026. <access>read-only</access>
  5027. </field>
  5028. </fields>
  5029. </register>
  5030. <register>
  5031. <name>DR</name>
  5032. <displayName>DR</displayName>
  5033. <description>data register</description>
  5034. <addressOffset>0x8</addressOffset>
  5035. <size>0x20</size>
  5036. <access>read-only</access>
  5037. <resetValue>0x00000000</resetValue>
  5038. <fields>
  5039. <field>
  5040. <name>RNDATA</name>
  5041. <description>Random data</description>
  5042. <bitOffset>0</bitOffset>
  5043. <bitWidth>32</bitWidth>
  5044. </field>
  5045. </fields>
  5046. </register>
  5047. </registers>
  5048. </peripheral>
  5049. <peripheral>
  5050. <name>RTC</name>
  5051. <description>Real-time clock</description>
  5052. <groupName>RTC</groupName>
  5053. <baseAddress>0x40002800</baseAddress>
  5054. <addressBlock>
  5055. <offset>0x0</offset>
  5056. <size>0x400</size>
  5057. <usage>registers</usage>
  5058. </addressBlock>
  5059. <interrupt>
  5060. <name>RTC</name>
  5061. <description>RTC global interrupt</description>
  5062. <value>2</value>
  5063. </interrupt>
  5064. <registers>
  5065. <register>
  5066. <name>TR</name>
  5067. <displayName>TR</displayName>
  5068. <description>RTC time register</description>
  5069. <addressOffset>0x0</addressOffset>
  5070. <size>0x20</size>
  5071. <access>read-write</access>
  5072. <resetValue>0x00000000</resetValue>
  5073. <fields>
  5074. <field>
  5075. <name>PM</name>
  5076. <description>AM/PM notation</description>
  5077. <bitOffset>22</bitOffset>
  5078. <bitWidth>1</bitWidth>
  5079. </field>
  5080. <field>
  5081. <name>HT</name>
  5082. <description>Hour tens in BCD format</description>
  5083. <bitOffset>20</bitOffset>
  5084. <bitWidth>2</bitWidth>
  5085. </field>
  5086. <field>
  5087. <name>HU</name>
  5088. <description>Hour units in BCD format</description>
  5089. <bitOffset>16</bitOffset>
  5090. <bitWidth>4</bitWidth>
  5091. </field>
  5092. <field>
  5093. <name>MNT</name>
  5094. <description>Minute tens in BCD format</description>
  5095. <bitOffset>12</bitOffset>
  5096. <bitWidth>3</bitWidth>
  5097. </field>
  5098. <field>
  5099. <name>MNU</name>
  5100. <description>Minute units in BCD format</description>
  5101. <bitOffset>8</bitOffset>
  5102. <bitWidth>4</bitWidth>
  5103. </field>
  5104. <field>
  5105. <name>ST</name>
  5106. <description>Second tens in BCD format</description>
  5107. <bitOffset>4</bitOffset>
  5108. <bitWidth>3</bitWidth>
  5109. </field>
  5110. <field>
  5111. <name>SU</name>
  5112. <description>Second units in BCD format</description>
  5113. <bitOffset>0</bitOffset>
  5114. <bitWidth>4</bitWidth>
  5115. </field>
  5116. </fields>
  5117. </register>
  5118. <register>
  5119. <name>DR</name>
  5120. <displayName>DR</displayName>
  5121. <description>RTC date register</description>
  5122. <addressOffset>0x4</addressOffset>
  5123. <size>0x20</size>
  5124. <access>read-write</access>
  5125. <resetValue>0x00000000</resetValue>
  5126. <fields>
  5127. <field>
  5128. <name>YT</name>
  5129. <description>Year tens in BCD format</description>
  5130. <bitOffset>20</bitOffset>
  5131. <bitWidth>4</bitWidth>
  5132. </field>
  5133. <field>
  5134. <name>YU</name>
  5135. <description>Year units in BCD format</description>
  5136. <bitOffset>16</bitOffset>
  5137. <bitWidth>4</bitWidth>
  5138. </field>
  5139. <field>
  5140. <name>WDU</name>
  5141. <description>Week day units</description>
  5142. <bitOffset>13</bitOffset>
  5143. <bitWidth>3</bitWidth>
  5144. </field>
  5145. <field>
  5146. <name>MT</name>
  5147. <description>Month tens in BCD format</description>
  5148. <bitOffset>12</bitOffset>
  5149. <bitWidth>1</bitWidth>
  5150. </field>
  5151. <field>
  5152. <name>MU</name>
  5153. <description>Month units in BCD format</description>
  5154. <bitOffset>8</bitOffset>
  5155. <bitWidth>4</bitWidth>
  5156. </field>
  5157. <field>
  5158. <name>DT</name>
  5159. <description>Date tens in BCD format</description>
  5160. <bitOffset>4</bitOffset>
  5161. <bitWidth>2</bitWidth>
  5162. </field>
  5163. <field>
  5164. <name>DU</name>
  5165. <description>Date units in BCD format</description>
  5166. <bitOffset>0</bitOffset>
  5167. <bitWidth>4</bitWidth>
  5168. </field>
  5169. </fields>
  5170. </register>
  5171. <register>
  5172. <name>CR</name>
  5173. <displayName>CR</displayName>
  5174. <description>RTC control register</description>
  5175. <addressOffset>0x8</addressOffset>
  5176. <size>0x20</size>
  5177. <resetValue>0x00000000</resetValue>
  5178. <fields>
  5179. <field>
  5180. <name>COE</name>
  5181. <description>Calibration output enable</description>
  5182. <bitOffset>23</bitOffset>
  5183. <bitWidth>1</bitWidth>
  5184. <access>read-write</access>
  5185. </field>
  5186. <field>
  5187. <name>OSEL</name>
  5188. <description>Output selection</description>
  5189. <bitOffset>21</bitOffset>
  5190. <bitWidth>2</bitWidth>
  5191. <access>read-write</access>
  5192. </field>
  5193. <field>
  5194. <name>POL</name>
  5195. <description>Output polarity</description>
  5196. <bitOffset>20</bitOffset>
  5197. <bitWidth>1</bitWidth>
  5198. <access>read-write</access>
  5199. </field>
  5200. <field>
  5201. <name>COSEL</name>
  5202. <description>Calibration output
  5203. selection</description>
  5204. <bitOffset>19</bitOffset>
  5205. <bitWidth>1</bitWidth>
  5206. <access>read-write</access>
  5207. </field>
  5208. <field>
  5209. <name>BKP</name>
  5210. <description>Backup</description>
  5211. <bitOffset>18</bitOffset>
  5212. <bitWidth>1</bitWidth>
  5213. <access>read-write</access>
  5214. </field>
  5215. <field>
  5216. <name>SUB1H</name>
  5217. <description>Subtract 1 hour (winter time
  5218. change)</description>
  5219. <bitOffset>17</bitOffset>
  5220. <bitWidth>1</bitWidth>
  5221. <access>write-only</access>
  5222. </field>
  5223. <field>
  5224. <name>ADD1H</name>
  5225. <description>Add 1 hour (summer time
  5226. change)</description>
  5227. <bitOffset>16</bitOffset>
  5228. <bitWidth>1</bitWidth>
  5229. <access>write-only</access>
  5230. </field>
  5231. <field>
  5232. <name>TSIE</name>
  5233. <description>Time-stamp interrupt
  5234. enable</description>
  5235. <bitOffset>15</bitOffset>
  5236. <bitWidth>1</bitWidth>
  5237. <access>read-write</access>
  5238. </field>
  5239. <field>
  5240. <name>WUTIE</name>
  5241. <description>Wakeup timer interrupt
  5242. enable</description>
  5243. <bitOffset>14</bitOffset>
  5244. <bitWidth>1</bitWidth>
  5245. <access>read-write</access>
  5246. </field>
  5247. <field>
  5248. <name>ALRBIE</name>
  5249. <description>Alarm B interrupt enable</description>
  5250. <bitOffset>13</bitOffset>
  5251. <bitWidth>1</bitWidth>
  5252. <access>read-write</access>
  5253. </field>
  5254. <field>
  5255. <name>ALRAIE</name>
  5256. <description>Alarm A interrupt enable</description>
  5257. <bitOffset>12</bitOffset>
  5258. <bitWidth>1</bitWidth>
  5259. <access>read-write</access>
  5260. </field>
  5261. <field>
  5262. <name>TSE</name>
  5263. <description>timestamp enable</description>
  5264. <bitOffset>11</bitOffset>
  5265. <bitWidth>1</bitWidth>
  5266. <access>read-write</access>
  5267. </field>
  5268. <field>
  5269. <name>WUTE</name>
  5270. <description>Wakeup timer enable</description>
  5271. <bitOffset>10</bitOffset>
  5272. <bitWidth>1</bitWidth>
  5273. <access>read-write</access>
  5274. </field>
  5275. <field>
  5276. <name>ALRBE</name>
  5277. <description>Alarm B enable</description>
  5278. <bitOffset>9</bitOffset>
  5279. <bitWidth>1</bitWidth>
  5280. <access>read-write</access>
  5281. </field>
  5282. <field>
  5283. <name>ALRAE</name>
  5284. <description>Alarm A enable</description>
  5285. <bitOffset>8</bitOffset>
  5286. <bitWidth>1</bitWidth>
  5287. <access>read-write</access>
  5288. </field>
  5289. <field>
  5290. <name>FMT</name>
  5291. <description>Hour format</description>
  5292. <bitOffset>6</bitOffset>
  5293. <bitWidth>1</bitWidth>
  5294. <access>read-write</access>
  5295. </field>
  5296. <field>
  5297. <name>BYPSHAD</name>
  5298. <description>Bypass the shadow
  5299. registers</description>
  5300. <bitOffset>5</bitOffset>
  5301. <bitWidth>1</bitWidth>
  5302. <access>read-write</access>
  5303. </field>
  5304. <field>
  5305. <name>REFCKON</name>
  5306. <description>RTC_REFIN reference clock detection
  5307. enable (50 or 60 Hz)</description>
  5308. <bitOffset>4</bitOffset>
  5309. <bitWidth>1</bitWidth>
  5310. <access>read-write</access>
  5311. </field>
  5312. <field>
  5313. <name>TSEDGE</name>
  5314. <description>Time-stamp event active
  5315. edge</description>
  5316. <bitOffset>3</bitOffset>
  5317. <bitWidth>1</bitWidth>
  5318. <access>read-write</access>
  5319. </field>
  5320. <field>
  5321. <name>WUCKSEL</name>
  5322. <description>Wakeup clock selection</description>
  5323. <bitOffset>0</bitOffset>
  5324. <bitWidth>3</bitWidth>
  5325. <access>read-write</access>
  5326. </field>
  5327. </fields>
  5328. </register>
  5329. <register>
  5330. <name>ISR</name>
  5331. <displayName>ISR</displayName>
  5332. <description>RTC initialization and status
  5333. register</description>
  5334. <addressOffset>0xC</addressOffset>
  5335. <size>0x20</size>
  5336. <resetValue>0x00000000</resetValue>
  5337. <fields>
  5338. <field>
  5339. <name>TAMP2F</name>
  5340. <description>RTC_TAMP2 detection flag</description>
  5341. <bitOffset>14</bitOffset>
  5342. <bitWidth>1</bitWidth>
  5343. <access>read-write</access>
  5344. </field>
  5345. <field>
  5346. <name>TAMP1F</name>
  5347. <description>RTC_TAMP1 detection flag</description>
  5348. <bitOffset>13</bitOffset>
  5349. <bitWidth>1</bitWidth>
  5350. <access>read-write</access>
  5351. </field>
  5352. <field>
  5353. <name>TSOVF</name>
  5354. <description>Time-stamp overflow flag</description>
  5355. <bitOffset>12</bitOffset>
  5356. <bitWidth>1</bitWidth>
  5357. <access>read-write</access>
  5358. </field>
  5359. <field>
  5360. <name>TSF</name>
  5361. <description>Time-stamp flag</description>
  5362. <bitOffset>11</bitOffset>
  5363. <bitWidth>1</bitWidth>
  5364. <access>read-write</access>
  5365. </field>
  5366. <field>
  5367. <name>WUTF</name>
  5368. <description>Wakeup timer flag</description>
  5369. <bitOffset>10</bitOffset>
  5370. <bitWidth>1</bitWidth>
  5371. <access>read-write</access>
  5372. </field>
  5373. <field>
  5374. <name>ALRBF</name>
  5375. <description>Alarm B flag</description>
  5376. <bitOffset>9</bitOffset>
  5377. <bitWidth>1</bitWidth>
  5378. <access>read-write</access>
  5379. </field>
  5380. <field>
  5381. <name>ALRAF</name>
  5382. <description>Alarm A flag</description>
  5383. <bitOffset>8</bitOffset>
  5384. <bitWidth>1</bitWidth>
  5385. <access>read-write</access>
  5386. </field>
  5387. <field>
  5388. <name>INIT</name>
  5389. <description>Initialization mode</description>
  5390. <bitOffset>7</bitOffset>
  5391. <bitWidth>1</bitWidth>
  5392. <access>read-write</access>
  5393. </field>
  5394. <field>
  5395. <name>INITF</name>
  5396. <description>Initialization flag</description>
  5397. <bitOffset>6</bitOffset>
  5398. <bitWidth>1</bitWidth>
  5399. <access>read-only</access>
  5400. </field>
  5401. <field>
  5402. <name>RSF</name>
  5403. <description>Registers synchronization
  5404. flag</description>
  5405. <bitOffset>5</bitOffset>
  5406. <bitWidth>1</bitWidth>
  5407. <access>read-write</access>
  5408. </field>
  5409. <field>
  5410. <name>INITS</name>
  5411. <description>Initialization status flag</description>
  5412. <bitOffset>4</bitOffset>
  5413. <bitWidth>1</bitWidth>
  5414. <access>read-only</access>
  5415. </field>
  5416. <field>
  5417. <name>SHPF</name>
  5418. <description>Shift operation pending</description>
  5419. <bitOffset>3</bitOffset>
  5420. <bitWidth>1</bitWidth>
  5421. <access>read-only</access>
  5422. </field>
  5423. <field>
  5424. <name>WUTWF</name>
  5425. <description>Wakeup timer write flag</description>
  5426. <bitOffset>2</bitOffset>
  5427. <bitWidth>1</bitWidth>
  5428. <access>read-only</access>
  5429. </field>
  5430. <field>
  5431. <name>ALRBWF</name>
  5432. <description>Alarm B write flag</description>
  5433. <bitOffset>1</bitOffset>
  5434. <bitWidth>1</bitWidth>
  5435. <access>read-only</access>
  5436. </field>
  5437. <field>
  5438. <name>ALRAWF</name>
  5439. <description>Alarm A write flag</description>
  5440. <bitOffset>0</bitOffset>
  5441. <bitWidth>1</bitWidth>
  5442. <access>read-only</access>
  5443. </field>
  5444. </fields>
  5445. </register>
  5446. <register>
  5447. <name>PRER</name>
  5448. <displayName>PRER</displayName>
  5449. <description>RTC prescaler register</description>
  5450. <addressOffset>0x10</addressOffset>
  5451. <size>0x20</size>
  5452. <access>read-write</access>
  5453. <resetValue>0x00000000</resetValue>
  5454. <fields>
  5455. <field>
  5456. <name>PREDIV_A</name>
  5457. <description>Asynchronous prescaler
  5458. factor</description>
  5459. <bitOffset>16</bitOffset>
  5460. <bitWidth>7</bitWidth>
  5461. </field>
  5462. <field>
  5463. <name>PREDIV_S</name>
  5464. <description>Synchronous prescaler
  5465. factor</description>
  5466. <bitOffset>0</bitOffset>
  5467. <bitWidth>16</bitWidth>
  5468. </field>
  5469. </fields>
  5470. </register>
  5471. <register>
  5472. <name>WUTR</name>
  5473. <displayName>WUTR</displayName>
  5474. <description>RTC wakeup timer register</description>
  5475. <addressOffset>0x14</addressOffset>
  5476. <size>0x20</size>
  5477. <access>read-write</access>
  5478. <resetValue>0x00000000</resetValue>
  5479. <fields>
  5480. <field>
  5481. <name>WUT</name>
  5482. <description>Wakeup auto-reload value
  5483. bits</description>
  5484. <bitOffset>0</bitOffset>
  5485. <bitWidth>16</bitWidth>
  5486. </field>
  5487. </fields>
  5488. </register>
  5489. <register>
  5490. <name>ALRMAR</name>
  5491. <displayName>ALRMAR</displayName>
  5492. <description>RTC alarm A register</description>
  5493. <addressOffset>0x1C</addressOffset>
  5494. <size>0x20</size>
  5495. <access>read-write</access>
  5496. <resetValue>0x00000000</resetValue>
  5497. <fields>
  5498. <field>
  5499. <name>MSK4</name>
  5500. <description>Alarm A date mask</description>
  5501. <bitOffset>31</bitOffset>
  5502. <bitWidth>1</bitWidth>
  5503. </field>
  5504. <field>
  5505. <name>WDSEL</name>
  5506. <description>Week day selection</description>
  5507. <bitOffset>30</bitOffset>
  5508. <bitWidth>1</bitWidth>
  5509. </field>
  5510. <field>
  5511. <name>DT</name>
  5512. <description>Date tens in BCD format.</description>
  5513. <bitOffset>28</bitOffset>
  5514. <bitWidth>2</bitWidth>
  5515. </field>
  5516. <field>
  5517. <name>DU</name>
  5518. <description>Date units or day in BCD
  5519. format.</description>
  5520. <bitOffset>24</bitOffset>
  5521. <bitWidth>4</bitWidth>
  5522. </field>
  5523. <field>
  5524. <name>MSK3</name>
  5525. <description>Alarm A hours mask</description>
  5526. <bitOffset>23</bitOffset>
  5527. <bitWidth>1</bitWidth>
  5528. </field>
  5529. <field>
  5530. <name>PM</name>
  5531. <description>AM/PM notation</description>
  5532. <bitOffset>22</bitOffset>
  5533. <bitWidth>1</bitWidth>
  5534. </field>
  5535. <field>
  5536. <name>HT</name>
  5537. <description>Hour tens in BCD format.</description>
  5538. <bitOffset>20</bitOffset>
  5539. <bitWidth>2</bitWidth>
  5540. </field>
  5541. <field>
  5542. <name>HU</name>
  5543. <description>Hour units in BCD format.</description>
  5544. <bitOffset>16</bitOffset>
  5545. <bitWidth>4</bitWidth>
  5546. </field>
  5547. <field>
  5548. <name>MSK2</name>
  5549. <description>Alarm A minutes mask</description>
  5550. <bitOffset>15</bitOffset>
  5551. <bitWidth>1</bitWidth>
  5552. </field>
  5553. <field>
  5554. <name>MNT</name>
  5555. <description>Minute tens in BCD format.</description>
  5556. <bitOffset>12</bitOffset>
  5557. <bitWidth>3</bitWidth>
  5558. </field>
  5559. <field>
  5560. <name>MNU</name>
  5561. <description>Minute units in BCD
  5562. format.</description>
  5563. <bitOffset>8</bitOffset>
  5564. <bitWidth>4</bitWidth>
  5565. </field>
  5566. <field>
  5567. <name>MSK1</name>
  5568. <description>Alarm A seconds mask</description>
  5569. <bitOffset>7</bitOffset>
  5570. <bitWidth>1</bitWidth>
  5571. </field>
  5572. <field>
  5573. <name>ST</name>
  5574. <description>Second tens in BCD format.</description>
  5575. <bitOffset>4</bitOffset>
  5576. <bitWidth>3</bitWidth>
  5577. </field>
  5578. <field>
  5579. <name>SU</name>
  5580. <description>Second units in BCD
  5581. format.</description>
  5582. <bitOffset>0</bitOffset>
  5583. <bitWidth>4</bitWidth>
  5584. </field>
  5585. </fields>
  5586. </register>
  5587. <register>
  5588. <name>ALRMBR</name>
  5589. <displayName>ALRMBR</displayName>
  5590. <description>RTC alarm B register</description>
  5591. <addressOffset>0x20</addressOffset>
  5592. <size>0x20</size>
  5593. <access>read-write</access>
  5594. <resetValue>0x00000000</resetValue>
  5595. <fields>
  5596. <field>
  5597. <name>MSK4</name>
  5598. <description>Alarm B date mask</description>
  5599. <bitOffset>31</bitOffset>
  5600. <bitWidth>1</bitWidth>
  5601. </field>
  5602. <field>
  5603. <name>WDSEL</name>
  5604. <description>Week day selection</description>
  5605. <bitOffset>30</bitOffset>
  5606. <bitWidth>1</bitWidth>
  5607. </field>
  5608. <field>
  5609. <name>DT</name>
  5610. <description>Date tens in BCD format</description>
  5611. <bitOffset>28</bitOffset>
  5612. <bitWidth>2</bitWidth>
  5613. </field>
  5614. <field>
  5615. <name>DU</name>
  5616. <description>Date units or day in BCD
  5617. format</description>
  5618. <bitOffset>24</bitOffset>
  5619. <bitWidth>4</bitWidth>
  5620. </field>
  5621. <field>
  5622. <name>MSK3</name>
  5623. <description>Alarm B hours mask</description>
  5624. <bitOffset>23</bitOffset>
  5625. <bitWidth>1</bitWidth>
  5626. </field>
  5627. <field>
  5628. <name>PM</name>
  5629. <description>AM/PM notation</description>
  5630. <bitOffset>22</bitOffset>
  5631. <bitWidth>1</bitWidth>
  5632. </field>
  5633. <field>
  5634. <name>HT</name>
  5635. <description>Hour tens in BCD format</description>
  5636. <bitOffset>20</bitOffset>
  5637. <bitWidth>2</bitWidth>
  5638. </field>
  5639. <field>
  5640. <name>HU</name>
  5641. <description>Hour units in BCD format</description>
  5642. <bitOffset>16</bitOffset>
  5643. <bitWidth>4</bitWidth>
  5644. </field>
  5645. <field>
  5646. <name>MSK2</name>
  5647. <description>Alarm B minutes mask</description>
  5648. <bitOffset>15</bitOffset>
  5649. <bitWidth>1</bitWidth>
  5650. </field>
  5651. <field>
  5652. <name>MNT</name>
  5653. <description>Minute tens in BCD format</description>
  5654. <bitOffset>12</bitOffset>
  5655. <bitWidth>3</bitWidth>
  5656. </field>
  5657. <field>
  5658. <name>MNU</name>
  5659. <description>Minute units in BCD format</description>
  5660. <bitOffset>8</bitOffset>
  5661. <bitWidth>4</bitWidth>
  5662. </field>
  5663. <field>
  5664. <name>MSK1</name>
  5665. <description>Alarm B seconds mask</description>
  5666. <bitOffset>7</bitOffset>
  5667. <bitWidth>1</bitWidth>
  5668. </field>
  5669. <field>
  5670. <name>ST</name>
  5671. <description>Second tens in BCD format</description>
  5672. <bitOffset>4</bitOffset>
  5673. <bitWidth>3</bitWidth>
  5674. </field>
  5675. <field>
  5676. <name>SU</name>
  5677. <description>Second units in BCD format</description>
  5678. <bitOffset>0</bitOffset>
  5679. <bitWidth>4</bitWidth>
  5680. </field>
  5681. </fields>
  5682. </register>
  5683. <register>
  5684. <name>WPR</name>
  5685. <displayName>WPR</displayName>
  5686. <description>write protection register</description>
  5687. <addressOffset>0x24</addressOffset>
  5688. <size>0x20</size>
  5689. <access>write-only</access>
  5690. <resetValue>0x00000000</resetValue>
  5691. <fields>
  5692. <field>
  5693. <name>KEY</name>
  5694. <description>Write protection key</description>
  5695. <bitOffset>0</bitOffset>
  5696. <bitWidth>8</bitWidth>
  5697. </field>
  5698. </fields>
  5699. </register>
  5700. <register>
  5701. <name>SSR</name>
  5702. <displayName>SSR</displayName>
  5703. <description>RTC sub second register</description>
  5704. <addressOffset>0x28</addressOffset>
  5705. <size>0x20</size>
  5706. <access>read-only</access>
  5707. <resetValue>0x00000000</resetValue>
  5708. <fields>
  5709. <field>
  5710. <name>SS</name>
  5711. <description>Sub second value</description>
  5712. <bitOffset>0</bitOffset>
  5713. <bitWidth>16</bitWidth>
  5714. </field>
  5715. </fields>
  5716. </register>
  5717. <register>
  5718. <name>SHIFTR</name>
  5719. <displayName>SHIFTR</displayName>
  5720. <description>RTC shift control register</description>
  5721. <addressOffset>0x2C</addressOffset>
  5722. <size>0x20</size>
  5723. <access>write-only</access>
  5724. <resetValue>0x00000000</resetValue>
  5725. <fields>
  5726. <field>
  5727. <name>ADD1S</name>
  5728. <description>Add one second</description>
  5729. <bitOffset>31</bitOffset>
  5730. <bitWidth>1</bitWidth>
  5731. </field>
  5732. <field>
  5733. <name>SUBFS</name>
  5734. <description>Subtract a fraction of a
  5735. second</description>
  5736. <bitOffset>0</bitOffset>
  5737. <bitWidth>15</bitWidth>
  5738. </field>
  5739. </fields>
  5740. </register>
  5741. <register>
  5742. <name>TSTR</name>
  5743. <displayName>TSTR</displayName>
  5744. <description>RTC timestamp time register</description>
  5745. <addressOffset>0x30</addressOffset>
  5746. <size>0x20</size>
  5747. <access>read-only</access>
  5748. <resetValue>0x00000000</resetValue>
  5749. <fields>
  5750. <field>
  5751. <name>PM</name>
  5752. <description>AM/PM notation</description>
  5753. <bitOffset>22</bitOffset>
  5754. <bitWidth>1</bitWidth>
  5755. </field>
  5756. <field>
  5757. <name>HT</name>
  5758. <description>Hour tens in BCD format.</description>
  5759. <bitOffset>20</bitOffset>
  5760. <bitWidth>2</bitWidth>
  5761. </field>
  5762. <field>
  5763. <name>HU</name>
  5764. <description>Hour units in BCD format.</description>
  5765. <bitOffset>16</bitOffset>
  5766. <bitWidth>4</bitWidth>
  5767. </field>
  5768. <field>
  5769. <name>MNT</name>
  5770. <description>Minute tens in BCD format.</description>
  5771. <bitOffset>12</bitOffset>
  5772. <bitWidth>3</bitWidth>
  5773. </field>
  5774. <field>
  5775. <name>MNU</name>
  5776. <description>Minute units in BCD
  5777. format.</description>
  5778. <bitOffset>8</bitOffset>
  5779. <bitWidth>4</bitWidth>
  5780. </field>
  5781. <field>
  5782. <name>ST</name>
  5783. <description>Second tens in BCD format.</description>
  5784. <bitOffset>4</bitOffset>
  5785. <bitWidth>3</bitWidth>
  5786. </field>
  5787. <field>
  5788. <name>SU</name>
  5789. <description>Second units in BCD
  5790. format.</description>
  5791. <bitOffset>0</bitOffset>
  5792. <bitWidth>4</bitWidth>
  5793. </field>
  5794. </fields>
  5795. </register>
  5796. <register>
  5797. <name>TSDR</name>
  5798. <displayName>TSDR</displayName>
  5799. <description>RTC timestamp date register</description>
  5800. <addressOffset>0x34</addressOffset>
  5801. <size>0x20</size>
  5802. <access>read-only</access>
  5803. <resetValue>0x00000000</resetValue>
  5804. <fields>
  5805. <field>
  5806. <name>WDU</name>
  5807. <description>Week day units</description>
  5808. <bitOffset>13</bitOffset>
  5809. <bitWidth>3</bitWidth>
  5810. </field>
  5811. <field>
  5812. <name>MT</name>
  5813. <description>Month tens in BCD format</description>
  5814. <bitOffset>12</bitOffset>
  5815. <bitWidth>1</bitWidth>
  5816. </field>
  5817. <field>
  5818. <name>MU</name>
  5819. <description>Month units in BCD format</description>
  5820. <bitOffset>8</bitOffset>
  5821. <bitWidth>4</bitWidth>
  5822. </field>
  5823. <field>
  5824. <name>DT</name>
  5825. <description>Date tens in BCD format</description>
  5826. <bitOffset>4</bitOffset>
  5827. <bitWidth>2</bitWidth>
  5828. </field>
  5829. <field>
  5830. <name>DU</name>
  5831. <description>Date units in BCD format</description>
  5832. <bitOffset>0</bitOffset>
  5833. <bitWidth>4</bitWidth>
  5834. </field>
  5835. </fields>
  5836. </register>
  5837. <register>
  5838. <name>TSSSR</name>
  5839. <displayName>TSSSR</displayName>
  5840. <description>RTC time-stamp sub second
  5841. register</description>
  5842. <addressOffset>0x38</addressOffset>
  5843. <size>0x20</size>
  5844. <access>read-only</access>
  5845. <resetValue>0x00000000</resetValue>
  5846. <fields>
  5847. <field>
  5848. <name>SS</name>
  5849. <description>Sub second value</description>
  5850. <bitOffset>0</bitOffset>
  5851. <bitWidth>16</bitWidth>
  5852. </field>
  5853. </fields>
  5854. </register>
  5855. <register>
  5856. <name>CALR</name>
  5857. <displayName>CALR</displayName>
  5858. <description>RTC calibration register</description>
  5859. <addressOffset>0x3C</addressOffset>
  5860. <size>0x20</size>
  5861. <access>read-write</access>
  5862. <resetValue>0x00000000</resetValue>
  5863. <fields>
  5864. <field>
  5865. <name>CALP</name>
  5866. <description>Use an 8-second calibration cycle
  5867. period</description>
  5868. <bitOffset>15</bitOffset>
  5869. <bitWidth>1</bitWidth>
  5870. </field>
  5871. <field>
  5872. <name>CALW8</name>
  5873. <description>Use a 16-second calibration cycle
  5874. period</description>
  5875. <bitOffset>14</bitOffset>
  5876. <bitWidth>1</bitWidth>
  5877. </field>
  5878. <field>
  5879. <name>CALW16</name>
  5880. <description>Reserved</description>
  5881. <bitOffset>13</bitOffset>
  5882. <bitWidth>1</bitWidth>
  5883. </field>
  5884. <field>
  5885. <name>CALM</name>
  5886. <description>Calibration minus</description>
  5887. <bitOffset>0</bitOffset>
  5888. <bitWidth>9</bitWidth>
  5889. </field>
  5890. </fields>
  5891. </register>
  5892. <register>
  5893. <name>TAMPCR</name>
  5894. <displayName>TAMPCR</displayName>
  5895. <description>RTC tamper configuration
  5896. register</description>
  5897. <addressOffset>0x40</addressOffset>
  5898. <size>0x20</size>
  5899. <access>read-write</access>
  5900. <resetValue>0x00000000</resetValue>
  5901. <fields>
  5902. <field>
  5903. <name>TAMP2MF</name>
  5904. <description>Tamper 2 mask flag</description>
  5905. <bitOffset>21</bitOffset>
  5906. <bitWidth>1</bitWidth>
  5907. </field>
  5908. <field>
  5909. <name>TAMP2NOERASE</name>
  5910. <description>Tamper 2 no erase</description>
  5911. <bitOffset>20</bitOffset>
  5912. <bitWidth>1</bitWidth>
  5913. </field>
  5914. <field>
  5915. <name>TAMP2IE</name>
  5916. <description>Tamper 2 interrupt enable</description>
  5917. <bitOffset>19</bitOffset>
  5918. <bitWidth>1</bitWidth>
  5919. </field>
  5920. <field>
  5921. <name>TAMP1MF</name>
  5922. <description>Tamper 1 mask flag</description>
  5923. <bitOffset>18</bitOffset>
  5924. <bitWidth>1</bitWidth>
  5925. </field>
  5926. <field>
  5927. <name>TAMP1NOERASE</name>
  5928. <description>Tamper 1 no erase</description>
  5929. <bitOffset>17</bitOffset>
  5930. <bitWidth>1</bitWidth>
  5931. </field>
  5932. <field>
  5933. <name>TAMP1IE</name>
  5934. <description>Tamper 1 interrupt enable</description>
  5935. <bitOffset>16</bitOffset>
  5936. <bitWidth>1</bitWidth>
  5937. </field>
  5938. <field>
  5939. <name>TAMPPUDIS</name>
  5940. <description>RTC_TAMPx pull-up disable</description>
  5941. <bitOffset>15</bitOffset>
  5942. <bitWidth>1</bitWidth>
  5943. </field>
  5944. <field>
  5945. <name>TAMPPRCH</name>
  5946. <description>RTC_TAMPx precharge
  5947. duration</description>
  5948. <bitOffset>13</bitOffset>
  5949. <bitWidth>2</bitWidth>
  5950. </field>
  5951. <field>
  5952. <name>TAMPFLT</name>
  5953. <description>RTC_TAMPx filter count</description>
  5954. <bitOffset>11</bitOffset>
  5955. <bitWidth>2</bitWidth>
  5956. </field>
  5957. <field>
  5958. <name>TAMPFREQ</name>
  5959. <description>Tamper sampling frequency</description>
  5960. <bitOffset>8</bitOffset>
  5961. <bitWidth>3</bitWidth>
  5962. </field>
  5963. <field>
  5964. <name>TAMPTS</name>
  5965. <description>Activate timestamp on tamper detection
  5966. event</description>
  5967. <bitOffset>7</bitOffset>
  5968. <bitWidth>1</bitWidth>
  5969. </field>
  5970. <field>
  5971. <name>TAMP2_TRG</name>
  5972. <description>Active level for RTC_TAMP2
  5973. input</description>
  5974. <bitOffset>4</bitOffset>
  5975. <bitWidth>1</bitWidth>
  5976. </field>
  5977. <field>
  5978. <name>TAMP2E</name>
  5979. <description>RTC_TAMP2 input detection
  5980. enable</description>
  5981. <bitOffset>3</bitOffset>
  5982. <bitWidth>1</bitWidth>
  5983. </field>
  5984. <field>
  5985. <name>TAMPIE</name>
  5986. <description>Tamper interrupt enable</description>
  5987. <bitOffset>2</bitOffset>
  5988. <bitWidth>1</bitWidth>
  5989. </field>
  5990. <field>
  5991. <name>TAMP1TRG</name>
  5992. <description>Active level for RTC_TAMP1
  5993. input</description>
  5994. <bitOffset>1</bitOffset>
  5995. <bitWidth>1</bitWidth>
  5996. </field>
  5997. <field>
  5998. <name>TAMP1E</name>
  5999. <description>RTC_TAMP1 input detection
  6000. enable</description>
  6001. <bitOffset>0</bitOffset>
  6002. <bitWidth>1</bitWidth>
  6003. </field>
  6004. </fields>
  6005. </register>
  6006. <register>
  6007. <name>ALRMASSR</name>
  6008. <displayName>ALRMASSR</displayName>
  6009. <description>RTC alarm A sub second
  6010. register</description>
  6011. <addressOffset>0x44</addressOffset>
  6012. <size>0x20</size>
  6013. <access>read-write</access>
  6014. <resetValue>0x00000000</resetValue>
  6015. <fields>
  6016. <field>
  6017. <name>MASKSS</name>
  6018. <description>Mask the most-significant bits starting
  6019. at this bit</description>
  6020. <bitOffset>24</bitOffset>
  6021. <bitWidth>4</bitWidth>
  6022. </field>
  6023. <field>
  6024. <name>SS</name>
  6025. <description>Sub seconds value</description>
  6026. <bitOffset>0</bitOffset>
  6027. <bitWidth>15</bitWidth>
  6028. </field>
  6029. </fields>
  6030. </register>
  6031. <register>
  6032. <name>ALRMBSSR</name>
  6033. <displayName>ALRMBSSR</displayName>
  6034. <description>RTC alarm B sub second
  6035. register</description>
  6036. <addressOffset>0x48</addressOffset>
  6037. <size>0x20</size>
  6038. <access>read-write</access>
  6039. <resetValue>0x00000000</resetValue>
  6040. <fields>
  6041. <field>
  6042. <name>MASKSS</name>
  6043. <description>Mask the most-significant bits starting
  6044. at this bit</description>
  6045. <bitOffset>24</bitOffset>
  6046. <bitWidth>4</bitWidth>
  6047. </field>
  6048. <field>
  6049. <name>SS</name>
  6050. <description>Sub seconds value</description>
  6051. <bitOffset>0</bitOffset>
  6052. <bitWidth>15</bitWidth>
  6053. </field>
  6054. </fields>
  6055. </register>
  6056. <register>
  6057. <name>OR</name>
  6058. <displayName>OR</displayName>
  6059. <description>option register</description>
  6060. <addressOffset>0x4C</addressOffset>
  6061. <size>0x20</size>
  6062. <access>read-write</access>
  6063. <resetValue>0x00000000</resetValue>
  6064. <fields>
  6065. <field>
  6066. <name>RTC_OUT_RMP</name>
  6067. <description>RTC_ALARM on PC13 output
  6068. type</description>
  6069. <bitOffset>1</bitOffset>
  6070. <bitWidth>1</bitWidth>
  6071. </field>
  6072. <field>
  6073. <name>RTC_ALARM_TYPE</name>
  6074. <description>RTC_ALARM on PC13 output
  6075. type</description>
  6076. <bitOffset>0</bitOffset>
  6077. <bitWidth>1</bitWidth>
  6078. </field>
  6079. </fields>
  6080. </register>
  6081. <register>
  6082. <name>BKP0R</name>
  6083. <displayName>BKP0R</displayName>
  6084. <description>RTC backup registers</description>
  6085. <addressOffset>0x50</addressOffset>
  6086. <size>0x20</size>
  6087. <access>read-write</access>
  6088. <resetValue>0x00000000</resetValue>
  6089. <fields>
  6090. <field>
  6091. <name>BKP</name>
  6092. <description>BKP</description>
  6093. <bitOffset>0</bitOffset>
  6094. <bitWidth>32</bitWidth>
  6095. </field>
  6096. </fields>
  6097. </register>
  6098. <register>
  6099. <name>BKP1R</name>
  6100. <displayName>BKP1R</displayName>
  6101. <description>RTC backup registers</description>
  6102. <addressOffset>0x54</addressOffset>
  6103. <size>0x20</size>
  6104. <access>read-write</access>
  6105. <resetValue>0x00000000</resetValue>
  6106. <fields>
  6107. <field>
  6108. <name>BKP</name>
  6109. <description>BKP</description>
  6110. <bitOffset>0</bitOffset>
  6111. <bitWidth>32</bitWidth>
  6112. </field>
  6113. </fields>
  6114. </register>
  6115. <register>
  6116. <name>BKP2R</name>
  6117. <displayName>BKP2R</displayName>
  6118. <description>RTC backup registers</description>
  6119. <addressOffset>0x58</addressOffset>
  6120. <size>0x20</size>
  6121. <access>read-write</access>
  6122. <resetValue>0x00000000</resetValue>
  6123. <fields>
  6124. <field>
  6125. <name>BKP</name>
  6126. <description>BKP</description>
  6127. <bitOffset>0</bitOffset>
  6128. <bitWidth>32</bitWidth>
  6129. </field>
  6130. </fields>
  6131. </register>
  6132. <register>
  6133. <name>BKP3R</name>
  6134. <displayName>BKP3R</displayName>
  6135. <description>RTC backup registers</description>
  6136. <addressOffset>0x5C</addressOffset>
  6137. <size>0x20</size>
  6138. <access>read-write</access>
  6139. <resetValue>0x00000000</resetValue>
  6140. <fields>
  6141. <field>
  6142. <name>BKP</name>
  6143. <description>BKP</description>
  6144. <bitOffset>0</bitOffset>
  6145. <bitWidth>32</bitWidth>
  6146. </field>
  6147. </fields>
  6148. </register>
  6149. <register>
  6150. <name>BKP4R</name>
  6151. <displayName>BKP4R</displayName>
  6152. <description>RTC backup registers</description>
  6153. <addressOffset>0x60</addressOffset>
  6154. <size>0x20</size>
  6155. <access>read-write</access>
  6156. <resetValue>0x00000000</resetValue>
  6157. <fields>
  6158. <field>
  6159. <name>BKP</name>
  6160. <description>BKP</description>
  6161. <bitOffset>0</bitOffset>
  6162. <bitWidth>32</bitWidth>
  6163. </field>
  6164. </fields>
  6165. </register>
  6166. </registers>
  6167. </peripheral>
  6168. <peripheral>
  6169. <name>USART1</name>
  6170. <description>Universal synchronous asynchronous receiver
  6171. transmitter</description>
  6172. <groupName>USART</groupName>
  6173. <baseAddress>0x40013800</baseAddress>
  6174. <addressBlock>
  6175. <offset>0x0</offset>
  6176. <size>0x400</size>
  6177. <usage>registers</usage>
  6178. </addressBlock>
  6179. <interrupt>
  6180. <name>USART1</name>
  6181. <description>USART1 global interrupt</description>
  6182. <value>27</value>
  6183. </interrupt>
  6184. <registers>
  6185. <register>
  6186. <name>CR1</name>
  6187. <displayName>CR1</displayName>
  6188. <description>Control register 1</description>
  6189. <addressOffset>0x0</addressOffset>
  6190. <size>0x20</size>
  6191. <access>read-write</access>
  6192. <resetValue>0x0000</resetValue>
  6193. <fields>
  6194. <field>
  6195. <name>M1</name>
  6196. <description>Word length</description>
  6197. <bitOffset>28</bitOffset>
  6198. <bitWidth>1</bitWidth>
  6199. </field>
  6200. <field>
  6201. <name>EOBIE</name>
  6202. <description>End of Block interrupt
  6203. enable</description>
  6204. <bitOffset>27</bitOffset>
  6205. <bitWidth>1</bitWidth>
  6206. </field>
  6207. <field>
  6208. <name>RTOIE</name>
  6209. <description>Receiver timeout interrupt
  6210. enable</description>
  6211. <bitOffset>26</bitOffset>
  6212. <bitWidth>1</bitWidth>
  6213. </field>
  6214. <field>
  6215. <name>DEAT4</name>
  6216. <description>Driver Enable assertion
  6217. time</description>
  6218. <bitOffset>25</bitOffset>
  6219. <bitWidth>1</bitWidth>
  6220. </field>
  6221. <field>
  6222. <name>DEAT3</name>
  6223. <description>DEAT3</description>
  6224. <bitOffset>24</bitOffset>
  6225. <bitWidth>1</bitWidth>
  6226. </field>
  6227. <field>
  6228. <name>DEAT2</name>
  6229. <description>DEAT2</description>
  6230. <bitOffset>23</bitOffset>
  6231. <bitWidth>1</bitWidth>
  6232. </field>
  6233. <field>
  6234. <name>DEAT1</name>
  6235. <description>DEAT1</description>
  6236. <bitOffset>22</bitOffset>
  6237. <bitWidth>1</bitWidth>
  6238. </field>
  6239. <field>
  6240. <name>DEAT0</name>
  6241. <description>DEAT0</description>
  6242. <bitOffset>21</bitOffset>
  6243. <bitWidth>1</bitWidth>
  6244. </field>
  6245. <field>
  6246. <name>DEDT4</name>
  6247. <description>Driver Enable de-assertion
  6248. time</description>
  6249. <bitOffset>20</bitOffset>
  6250. <bitWidth>1</bitWidth>
  6251. </field>
  6252. <field>
  6253. <name>DEDT3</name>
  6254. <description>DEDT3</description>
  6255. <bitOffset>19</bitOffset>
  6256. <bitWidth>1</bitWidth>
  6257. </field>
  6258. <field>
  6259. <name>DEDT2</name>
  6260. <description>DEDT2</description>
  6261. <bitOffset>18</bitOffset>
  6262. <bitWidth>1</bitWidth>
  6263. </field>
  6264. <field>
  6265. <name>DEDT1</name>
  6266. <description>DEDT1</description>
  6267. <bitOffset>17</bitOffset>
  6268. <bitWidth>1</bitWidth>
  6269. </field>
  6270. <field>
  6271. <name>DEDT0</name>
  6272. <description>DEDT0</description>
  6273. <bitOffset>16</bitOffset>
  6274. <bitWidth>1</bitWidth>
  6275. </field>
  6276. <field>
  6277. <name>OVER8</name>
  6278. <description>Oversampling mode</description>
  6279. <bitOffset>15</bitOffset>
  6280. <bitWidth>1</bitWidth>
  6281. </field>
  6282. <field>
  6283. <name>CMIE</name>
  6284. <description>Character match interrupt
  6285. enable</description>
  6286. <bitOffset>14</bitOffset>
  6287. <bitWidth>1</bitWidth>
  6288. </field>
  6289. <field>
  6290. <name>MME</name>
  6291. <description>Mute mode enable</description>
  6292. <bitOffset>13</bitOffset>
  6293. <bitWidth>1</bitWidth>
  6294. </field>
  6295. <field>
  6296. <name>M0</name>
  6297. <description>Word length</description>
  6298. <bitOffset>12</bitOffset>
  6299. <bitWidth>1</bitWidth>
  6300. </field>
  6301. <field>
  6302. <name>WAKE</name>
  6303. <description>Receiver wakeup method</description>
  6304. <bitOffset>11</bitOffset>
  6305. <bitWidth>1</bitWidth>
  6306. </field>
  6307. <field>
  6308. <name>PCE</name>
  6309. <description>Parity control enable</description>
  6310. <bitOffset>10</bitOffset>
  6311. <bitWidth>1</bitWidth>
  6312. </field>
  6313. <field>
  6314. <name>PS</name>
  6315. <description>Parity selection</description>
  6316. <bitOffset>9</bitOffset>
  6317. <bitWidth>1</bitWidth>
  6318. </field>
  6319. <field>
  6320. <name>PEIE</name>
  6321. <description>PE interrupt enable</description>
  6322. <bitOffset>8</bitOffset>
  6323. <bitWidth>1</bitWidth>
  6324. </field>
  6325. <field>
  6326. <name>TXEIE</name>
  6327. <description>interrupt enable</description>
  6328. <bitOffset>7</bitOffset>
  6329. <bitWidth>1</bitWidth>
  6330. </field>
  6331. <field>
  6332. <name>TCIE</name>
  6333. <description>Transmission complete interrupt
  6334. enable</description>
  6335. <bitOffset>6</bitOffset>
  6336. <bitWidth>1</bitWidth>
  6337. </field>
  6338. <field>
  6339. <name>RXNEIE</name>
  6340. <description>RXNE interrupt enable</description>
  6341. <bitOffset>5</bitOffset>
  6342. <bitWidth>1</bitWidth>
  6343. </field>
  6344. <field>
  6345. <name>IDLEIE</name>
  6346. <description>IDLE interrupt enable</description>
  6347. <bitOffset>4</bitOffset>
  6348. <bitWidth>1</bitWidth>
  6349. </field>
  6350. <field>
  6351. <name>TE</name>
  6352. <description>Transmitter enable</description>
  6353. <bitOffset>3</bitOffset>
  6354. <bitWidth>1</bitWidth>
  6355. </field>
  6356. <field>
  6357. <name>RE</name>
  6358. <description>Receiver enable</description>
  6359. <bitOffset>2</bitOffset>
  6360. <bitWidth>1</bitWidth>
  6361. </field>
  6362. <field>
  6363. <name>UESM</name>
  6364. <description>USART enable in Stop mode</description>
  6365. <bitOffset>1</bitOffset>
  6366. <bitWidth>1</bitWidth>
  6367. </field>
  6368. <field>
  6369. <name>UE</name>
  6370. <description>USART enable</description>
  6371. <bitOffset>0</bitOffset>
  6372. <bitWidth>1</bitWidth>
  6373. </field>
  6374. </fields>
  6375. </register>
  6376. <register>
  6377. <name>CR2</name>
  6378. <displayName>CR2</displayName>
  6379. <description>Control register 2</description>
  6380. <addressOffset>0x4</addressOffset>
  6381. <size>0x20</size>
  6382. <access>read-write</access>
  6383. <resetValue>0x0000</resetValue>
  6384. <fields>
  6385. <field>
  6386. <name>ADD4_7</name>
  6387. <description>Address of the USART node</description>
  6388. <bitOffset>28</bitOffset>
  6389. <bitWidth>4</bitWidth>
  6390. </field>
  6391. <field>
  6392. <name>ADD0_3</name>
  6393. <description>Address of the USART node</description>
  6394. <bitOffset>24</bitOffset>
  6395. <bitWidth>4</bitWidth>
  6396. </field>
  6397. <field>
  6398. <name>RTOEN</name>
  6399. <description>Receiver timeout enable</description>
  6400. <bitOffset>23</bitOffset>
  6401. <bitWidth>1</bitWidth>
  6402. </field>
  6403. <field>
  6404. <name>ABRMOD1</name>
  6405. <description>Auto baud rate mode</description>
  6406. <bitOffset>22</bitOffset>
  6407. <bitWidth>1</bitWidth>
  6408. </field>
  6409. <field>
  6410. <name>ABRMOD0</name>
  6411. <description>ABRMOD0</description>
  6412. <bitOffset>21</bitOffset>
  6413. <bitWidth>1</bitWidth>
  6414. </field>
  6415. <field>
  6416. <name>ABREN</name>
  6417. <description>Auto baud rate enable</description>
  6418. <bitOffset>20</bitOffset>
  6419. <bitWidth>1</bitWidth>
  6420. </field>
  6421. <field>
  6422. <name>MSBFIRST</name>
  6423. <description>Most significant bit first</description>
  6424. <bitOffset>19</bitOffset>
  6425. <bitWidth>1</bitWidth>
  6426. </field>
  6427. <field>
  6428. <name>TAINV</name>
  6429. <description>Binary data inversion</description>
  6430. <bitOffset>18</bitOffset>
  6431. <bitWidth>1</bitWidth>
  6432. </field>
  6433. <field>
  6434. <name>TXINV</name>
  6435. <description>TX pin active level
  6436. inversion</description>
  6437. <bitOffset>17</bitOffset>
  6438. <bitWidth>1</bitWidth>
  6439. </field>
  6440. <field>
  6441. <name>RXINV</name>
  6442. <description>RX pin active level
  6443. inversion</description>
  6444. <bitOffset>16</bitOffset>
  6445. <bitWidth>1</bitWidth>
  6446. </field>
  6447. <field>
  6448. <name>SWAP</name>
  6449. <description>Swap TX/RX pins</description>
  6450. <bitOffset>15</bitOffset>
  6451. <bitWidth>1</bitWidth>
  6452. </field>
  6453. <field>
  6454. <name>LINEN</name>
  6455. <description>LIN mode enable</description>
  6456. <bitOffset>14</bitOffset>
  6457. <bitWidth>1</bitWidth>
  6458. </field>
  6459. <field>
  6460. <name>STOP</name>
  6461. <description>STOP bits</description>
  6462. <bitOffset>12</bitOffset>
  6463. <bitWidth>2</bitWidth>
  6464. </field>
  6465. <field>
  6466. <name>CLKEN</name>
  6467. <description>Clock enable</description>
  6468. <bitOffset>11</bitOffset>
  6469. <bitWidth>1</bitWidth>
  6470. </field>
  6471. <field>
  6472. <name>CPOL</name>
  6473. <description>Clock polarity</description>
  6474. <bitOffset>10</bitOffset>
  6475. <bitWidth>1</bitWidth>
  6476. </field>
  6477. <field>
  6478. <name>CPHA</name>
  6479. <description>Clock phase</description>
  6480. <bitOffset>9</bitOffset>
  6481. <bitWidth>1</bitWidth>
  6482. </field>
  6483. <field>
  6484. <name>LBCL</name>
  6485. <description>Last bit clock pulse</description>
  6486. <bitOffset>8</bitOffset>
  6487. <bitWidth>1</bitWidth>
  6488. </field>
  6489. <field>
  6490. <name>LBDIE</name>
  6491. <description>LIN break detection interrupt
  6492. enable</description>
  6493. <bitOffset>6</bitOffset>
  6494. <bitWidth>1</bitWidth>
  6495. </field>
  6496. <field>
  6497. <name>LBDL</name>
  6498. <description>LIN break detection length</description>
  6499. <bitOffset>5</bitOffset>
  6500. <bitWidth>1</bitWidth>
  6501. </field>
  6502. <field>
  6503. <name>ADDM7</name>
  6504. <description>7-bit Address Detection/4-bit Address
  6505. Detection</description>
  6506. <bitOffset>4</bitOffset>
  6507. <bitWidth>1</bitWidth>
  6508. </field>
  6509. </fields>
  6510. </register>
  6511. <register>
  6512. <name>CR3</name>
  6513. <displayName>CR3</displayName>
  6514. <description>Control register 3</description>
  6515. <addressOffset>0x8</addressOffset>
  6516. <size>0x20</size>
  6517. <access>read-write</access>
  6518. <resetValue>0x0000</resetValue>
  6519. <fields>
  6520. <field>
  6521. <name>WUFIE</name>
  6522. <description>Wakeup from Stop mode interrupt
  6523. enable</description>
  6524. <bitOffset>22</bitOffset>
  6525. <bitWidth>1</bitWidth>
  6526. </field>
  6527. <field>
  6528. <name>WUS</name>
  6529. <description>Wakeup from Stop mode interrupt flag
  6530. selection</description>
  6531. <bitOffset>20</bitOffset>
  6532. <bitWidth>2</bitWidth>
  6533. </field>
  6534. <field>
  6535. <name>SCARCNT</name>
  6536. <description>Smartcard auto-retry count</description>
  6537. <bitOffset>17</bitOffset>
  6538. <bitWidth>3</bitWidth>
  6539. </field>
  6540. <field>
  6541. <name>DEP</name>
  6542. <description>Driver enable polarity
  6543. selection</description>
  6544. <bitOffset>15</bitOffset>
  6545. <bitWidth>1</bitWidth>
  6546. </field>
  6547. <field>
  6548. <name>DEM</name>
  6549. <description>Driver enable mode</description>
  6550. <bitOffset>14</bitOffset>
  6551. <bitWidth>1</bitWidth>
  6552. </field>
  6553. <field>
  6554. <name>DDRE</name>
  6555. <description>DMA Disable on Reception
  6556. Error</description>
  6557. <bitOffset>13</bitOffset>
  6558. <bitWidth>1</bitWidth>
  6559. </field>
  6560. <field>
  6561. <name>OVRDIS</name>
  6562. <description>Overrun Disable</description>
  6563. <bitOffset>12</bitOffset>
  6564. <bitWidth>1</bitWidth>
  6565. </field>
  6566. <field>
  6567. <name>ONEBIT</name>
  6568. <description>One sample bit method
  6569. enable</description>
  6570. <bitOffset>11</bitOffset>
  6571. <bitWidth>1</bitWidth>
  6572. </field>
  6573. <field>
  6574. <name>CTSIE</name>
  6575. <description>CTS interrupt enable</description>
  6576. <bitOffset>10</bitOffset>
  6577. <bitWidth>1</bitWidth>
  6578. </field>
  6579. <field>
  6580. <name>CTSE</name>
  6581. <description>CTS enable</description>
  6582. <bitOffset>9</bitOffset>
  6583. <bitWidth>1</bitWidth>
  6584. </field>
  6585. <field>
  6586. <name>RTSE</name>
  6587. <description>RTS enable</description>
  6588. <bitOffset>8</bitOffset>
  6589. <bitWidth>1</bitWidth>
  6590. </field>
  6591. <field>
  6592. <name>DMAT</name>
  6593. <description>DMA enable transmitter</description>
  6594. <bitOffset>7</bitOffset>
  6595. <bitWidth>1</bitWidth>
  6596. </field>
  6597. <field>
  6598. <name>DMAR</name>
  6599. <description>DMA enable receiver</description>
  6600. <bitOffset>6</bitOffset>
  6601. <bitWidth>1</bitWidth>
  6602. </field>
  6603. <field>
  6604. <name>SCEN</name>
  6605. <description>Smartcard mode enable</description>
  6606. <bitOffset>5</bitOffset>
  6607. <bitWidth>1</bitWidth>
  6608. </field>
  6609. <field>
  6610. <name>NACK</name>
  6611. <description>Smartcard NACK enable</description>
  6612. <bitOffset>4</bitOffset>
  6613. <bitWidth>1</bitWidth>
  6614. </field>
  6615. <field>
  6616. <name>HDSEL</name>
  6617. <description>Half-duplex selection</description>
  6618. <bitOffset>3</bitOffset>
  6619. <bitWidth>1</bitWidth>
  6620. </field>
  6621. <field>
  6622. <name>IRLP</name>
  6623. <description>Ir low-power</description>
  6624. <bitOffset>2</bitOffset>
  6625. <bitWidth>1</bitWidth>
  6626. </field>
  6627. <field>
  6628. <name>IREN</name>
  6629. <description>Ir mode enable</description>
  6630. <bitOffset>1</bitOffset>
  6631. <bitWidth>1</bitWidth>
  6632. </field>
  6633. <field>
  6634. <name>EIE</name>
  6635. <description>Error interrupt enable</description>
  6636. <bitOffset>0</bitOffset>
  6637. <bitWidth>1</bitWidth>
  6638. </field>
  6639. </fields>
  6640. </register>
  6641. <register>
  6642. <name>BRR</name>
  6643. <displayName>BRR</displayName>
  6644. <description>Baud rate register</description>
  6645. <addressOffset>0xC</addressOffset>
  6646. <size>0x20</size>
  6647. <access>read-write</access>
  6648. <resetValue>0x0000</resetValue>
  6649. <fields>
  6650. <field>
  6651. <name>DIV_Mantissa</name>
  6652. <description>DIV_Mantissa</description>
  6653. <bitOffset>4</bitOffset>
  6654. <bitWidth>12</bitWidth>
  6655. </field>
  6656. <field>
  6657. <name>DIV_Fraction</name>
  6658. <description>DIV_Fraction</description>
  6659. <bitOffset>0</bitOffset>
  6660. <bitWidth>4</bitWidth>
  6661. </field>
  6662. </fields>
  6663. </register>
  6664. <register>
  6665. <name>GTPR</name>
  6666. <displayName>GTPR</displayName>
  6667. <description>Guard time and prescaler
  6668. register</description>
  6669. <addressOffset>0x10</addressOffset>
  6670. <size>0x20</size>
  6671. <access>read-write</access>
  6672. <resetValue>0x0000</resetValue>
  6673. <fields>
  6674. <field>
  6675. <name>GT</name>
  6676. <description>Guard time value</description>
  6677. <bitOffset>8</bitOffset>
  6678. <bitWidth>8</bitWidth>
  6679. </field>
  6680. <field>
  6681. <name>PSC</name>
  6682. <description>Prescaler value</description>
  6683. <bitOffset>0</bitOffset>
  6684. <bitWidth>8</bitWidth>
  6685. </field>
  6686. </fields>
  6687. </register>
  6688. <register>
  6689. <name>RTOR</name>
  6690. <displayName>RTOR</displayName>
  6691. <description>Receiver timeout register</description>
  6692. <addressOffset>0x14</addressOffset>
  6693. <size>0x20</size>
  6694. <access>read-write</access>
  6695. <resetValue>0x0000</resetValue>
  6696. <fields>
  6697. <field>
  6698. <name>BLEN</name>
  6699. <description>Block Length</description>
  6700. <bitOffset>24</bitOffset>
  6701. <bitWidth>8</bitWidth>
  6702. </field>
  6703. <field>
  6704. <name>RTO</name>
  6705. <description>Receiver timeout value</description>
  6706. <bitOffset>0</bitOffset>
  6707. <bitWidth>24</bitWidth>
  6708. </field>
  6709. </fields>
  6710. </register>
  6711. <register>
  6712. <name>RQR</name>
  6713. <displayName>RQR</displayName>
  6714. <description>Request register</description>
  6715. <addressOffset>0x18</addressOffset>
  6716. <size>0x20</size>
  6717. <access>write-only</access>
  6718. <resetValue>0x0000</resetValue>
  6719. <fields>
  6720. <field>
  6721. <name>TXFRQ</name>
  6722. <description>Transmit data flush
  6723. request</description>
  6724. <bitOffset>4</bitOffset>
  6725. <bitWidth>1</bitWidth>
  6726. </field>
  6727. <field>
  6728. <name>RXFRQ</name>
  6729. <description>Receive data flush request</description>
  6730. <bitOffset>3</bitOffset>
  6731. <bitWidth>1</bitWidth>
  6732. </field>
  6733. <field>
  6734. <name>MMRQ</name>
  6735. <description>Mute mode request</description>
  6736. <bitOffset>2</bitOffset>
  6737. <bitWidth>1</bitWidth>
  6738. </field>
  6739. <field>
  6740. <name>SBKRQ</name>
  6741. <description>Send break request</description>
  6742. <bitOffset>1</bitOffset>
  6743. <bitWidth>1</bitWidth>
  6744. </field>
  6745. <field>
  6746. <name>ABRRQ</name>
  6747. <description>Auto baud rate request</description>
  6748. <bitOffset>0</bitOffset>
  6749. <bitWidth>1</bitWidth>
  6750. </field>
  6751. </fields>
  6752. </register>
  6753. <register>
  6754. <name>ISR</name>
  6755. <displayName>ISR</displayName>
  6756. <description>Interrupt &amp; status
  6757. register</description>
  6758. <addressOffset>0x1C</addressOffset>
  6759. <size>0x20</size>
  6760. <access>read-only</access>
  6761. <resetValue>0x00C0</resetValue>
  6762. <fields>
  6763. <field>
  6764. <name>REACK</name>
  6765. <description>REACK</description>
  6766. <bitOffset>22</bitOffset>
  6767. <bitWidth>1</bitWidth>
  6768. </field>
  6769. <field>
  6770. <name>TEACK</name>
  6771. <description>TEACK</description>
  6772. <bitOffset>21</bitOffset>
  6773. <bitWidth>1</bitWidth>
  6774. </field>
  6775. <field>
  6776. <name>WUF</name>
  6777. <description>WUF</description>
  6778. <bitOffset>20</bitOffset>
  6779. <bitWidth>1</bitWidth>
  6780. </field>
  6781. <field>
  6782. <name>RWU</name>
  6783. <description>RWU</description>
  6784. <bitOffset>19</bitOffset>
  6785. <bitWidth>1</bitWidth>
  6786. </field>
  6787. <field>
  6788. <name>SBKF</name>
  6789. <description>SBKF</description>
  6790. <bitOffset>18</bitOffset>
  6791. <bitWidth>1</bitWidth>
  6792. </field>
  6793. <field>
  6794. <name>CMF</name>
  6795. <description>CMF</description>
  6796. <bitOffset>17</bitOffset>
  6797. <bitWidth>1</bitWidth>
  6798. </field>
  6799. <field>
  6800. <name>BUSY</name>
  6801. <description>BUSY</description>
  6802. <bitOffset>16</bitOffset>
  6803. <bitWidth>1</bitWidth>
  6804. </field>
  6805. <field>
  6806. <name>ABRF</name>
  6807. <description>ABRF</description>
  6808. <bitOffset>15</bitOffset>
  6809. <bitWidth>1</bitWidth>
  6810. </field>
  6811. <field>
  6812. <name>ABRE</name>
  6813. <description>ABRE</description>
  6814. <bitOffset>14</bitOffset>
  6815. <bitWidth>1</bitWidth>
  6816. </field>
  6817. <field>
  6818. <name>EOBF</name>
  6819. <description>EOBF</description>
  6820. <bitOffset>12</bitOffset>
  6821. <bitWidth>1</bitWidth>
  6822. </field>
  6823. <field>
  6824. <name>RTOF</name>
  6825. <description>RTOF</description>
  6826. <bitOffset>11</bitOffset>
  6827. <bitWidth>1</bitWidth>
  6828. </field>
  6829. <field>
  6830. <name>CTS</name>
  6831. <description>CTS</description>
  6832. <bitOffset>10</bitOffset>
  6833. <bitWidth>1</bitWidth>
  6834. </field>
  6835. <field>
  6836. <name>CTSIF</name>
  6837. <description>CTSIF</description>
  6838. <bitOffset>9</bitOffset>
  6839. <bitWidth>1</bitWidth>
  6840. </field>
  6841. <field>
  6842. <name>LBDF</name>
  6843. <description>LBDF</description>
  6844. <bitOffset>8</bitOffset>
  6845. <bitWidth>1</bitWidth>
  6846. </field>
  6847. <field>
  6848. <name>TXE</name>
  6849. <description>TXE</description>
  6850. <bitOffset>7</bitOffset>
  6851. <bitWidth>1</bitWidth>
  6852. </field>
  6853. <field>
  6854. <name>TC</name>
  6855. <description>TC</description>
  6856. <bitOffset>6</bitOffset>
  6857. <bitWidth>1</bitWidth>
  6858. </field>
  6859. <field>
  6860. <name>RXNE</name>
  6861. <description>RXNE</description>
  6862. <bitOffset>5</bitOffset>
  6863. <bitWidth>1</bitWidth>
  6864. </field>
  6865. <field>
  6866. <name>IDLE</name>
  6867. <description>IDLE</description>
  6868. <bitOffset>4</bitOffset>
  6869. <bitWidth>1</bitWidth>
  6870. </field>
  6871. <field>
  6872. <name>ORE</name>
  6873. <description>ORE</description>
  6874. <bitOffset>3</bitOffset>
  6875. <bitWidth>1</bitWidth>
  6876. </field>
  6877. <field>
  6878. <name>NF</name>
  6879. <description>NF</description>
  6880. <bitOffset>2</bitOffset>
  6881. <bitWidth>1</bitWidth>
  6882. </field>
  6883. <field>
  6884. <name>FE</name>
  6885. <description>FE</description>
  6886. <bitOffset>1</bitOffset>
  6887. <bitWidth>1</bitWidth>
  6888. </field>
  6889. <field>
  6890. <name>PE</name>
  6891. <description>PE</description>
  6892. <bitOffset>0</bitOffset>
  6893. <bitWidth>1</bitWidth>
  6894. </field>
  6895. </fields>
  6896. </register>
  6897. <register>
  6898. <name>ICR</name>
  6899. <displayName>ICR</displayName>
  6900. <description>Interrupt flag clear register</description>
  6901. <addressOffset>0x20</addressOffset>
  6902. <size>0x20</size>
  6903. <access>write-only</access>
  6904. <resetValue>0x0000</resetValue>
  6905. <fields>
  6906. <field>
  6907. <name>WUCF</name>
  6908. <description>Wakeup from Stop mode clear
  6909. flag</description>
  6910. <bitOffset>20</bitOffset>
  6911. <bitWidth>1</bitWidth>
  6912. </field>
  6913. <field>
  6914. <name>CMCF</name>
  6915. <description>Character match clear flag</description>
  6916. <bitOffset>17</bitOffset>
  6917. <bitWidth>1</bitWidth>
  6918. </field>
  6919. <field>
  6920. <name>EOBCF</name>
  6921. <description>End of block clear flag</description>
  6922. <bitOffset>12</bitOffset>
  6923. <bitWidth>1</bitWidth>
  6924. </field>
  6925. <field>
  6926. <name>RTOCF</name>
  6927. <description>Receiver timeout clear
  6928. flag</description>
  6929. <bitOffset>11</bitOffset>
  6930. <bitWidth>1</bitWidth>
  6931. </field>
  6932. <field>
  6933. <name>CTSCF</name>
  6934. <description>CTS clear flag</description>
  6935. <bitOffset>9</bitOffset>
  6936. <bitWidth>1</bitWidth>
  6937. </field>
  6938. <field>
  6939. <name>LBDCF</name>
  6940. <description>LIN break detection clear
  6941. flag</description>
  6942. <bitOffset>8</bitOffset>
  6943. <bitWidth>1</bitWidth>
  6944. </field>
  6945. <field>
  6946. <name>TCCF</name>
  6947. <description>Transmission complete clear
  6948. flag</description>
  6949. <bitOffset>6</bitOffset>
  6950. <bitWidth>1</bitWidth>
  6951. </field>
  6952. <field>
  6953. <name>IDLECF</name>
  6954. <description>Idle line detected clear
  6955. flag</description>
  6956. <bitOffset>4</bitOffset>
  6957. <bitWidth>1</bitWidth>
  6958. </field>
  6959. <field>
  6960. <name>ORECF</name>
  6961. <description>Overrun error clear flag</description>
  6962. <bitOffset>3</bitOffset>
  6963. <bitWidth>1</bitWidth>
  6964. </field>
  6965. <field>
  6966. <name>NCF</name>
  6967. <description>Noise detected clear flag</description>
  6968. <bitOffset>2</bitOffset>
  6969. <bitWidth>1</bitWidth>
  6970. </field>
  6971. <field>
  6972. <name>FECF</name>
  6973. <description>Framing error clear flag</description>
  6974. <bitOffset>1</bitOffset>
  6975. <bitWidth>1</bitWidth>
  6976. </field>
  6977. <field>
  6978. <name>PECF</name>
  6979. <description>Parity error clear flag</description>
  6980. <bitOffset>0</bitOffset>
  6981. <bitWidth>1</bitWidth>
  6982. </field>
  6983. </fields>
  6984. </register>
  6985. <register>
  6986. <name>RDR</name>
  6987. <displayName>RDR</displayName>
  6988. <description>Receive data register</description>
  6989. <addressOffset>0x24</addressOffset>
  6990. <size>0x20</size>
  6991. <access>read-only</access>
  6992. <resetValue>0x0000</resetValue>
  6993. <fields>
  6994. <field>
  6995. <name>RDR</name>
  6996. <description>Receive data value</description>
  6997. <bitOffset>0</bitOffset>
  6998. <bitWidth>9</bitWidth>
  6999. </field>
  7000. </fields>
  7001. </register>
  7002. <register>
  7003. <name>TDR</name>
  7004. <displayName>TDR</displayName>
  7005. <description>Transmit data register</description>
  7006. <addressOffset>0x28</addressOffset>
  7007. <size>0x20</size>
  7008. <access>read-write</access>
  7009. <resetValue>0x0000</resetValue>
  7010. <fields>
  7011. <field>
  7012. <name>TDR</name>
  7013. <description>Transmit data value</description>
  7014. <bitOffset>0</bitOffset>
  7015. <bitWidth>9</bitWidth>
  7016. </field>
  7017. </fields>
  7018. </register>
  7019. </registers>
  7020. </peripheral>
  7021. <peripheral derivedFrom="USART1">
  7022. <name>USART2</name>
  7023. <baseAddress>0x40004400</baseAddress>
  7024. <interrupt>
  7025. <name>USART2</name>
  7026. <description>USART2 global interrupt</description>
  7027. <value>28</value>
  7028. </interrupt>
  7029. </peripheral>
  7030. <peripheral>
  7031. <name>TSC</name>
  7032. <description>Touch sensing controller</description>
  7033. <groupName>TSC</groupName>
  7034. <baseAddress>0x40024000</baseAddress>
  7035. <addressBlock>
  7036. <offset>0x0</offset>
  7037. <size>0x400</size>
  7038. <usage>registers</usage>
  7039. </addressBlock>
  7040. <interrupt>
  7041. <name>TSC</name>
  7042. <description>Touch sensing interrupt</description>
  7043. <value>8</value>
  7044. </interrupt>
  7045. <registers>
  7046. <register>
  7047. <name>CR</name>
  7048. <displayName>CR</displayName>
  7049. <description>control register</description>
  7050. <addressOffset>0x0</addressOffset>
  7051. <size>0x20</size>
  7052. <access>read-write</access>
  7053. <resetValue>0x00000000</resetValue>
  7054. <fields>
  7055. <field>
  7056. <name>CTPH</name>
  7057. <description>Charge transfer pulse high</description>
  7058. <bitOffset>28</bitOffset>
  7059. <bitWidth>4</bitWidth>
  7060. </field>
  7061. <field>
  7062. <name>CTPL</name>
  7063. <description>Charge transfer pulse low</description>
  7064. <bitOffset>24</bitOffset>
  7065. <bitWidth>4</bitWidth>
  7066. </field>
  7067. <field>
  7068. <name>SSD</name>
  7069. <description>Spread spectrum deviation</description>
  7070. <bitOffset>17</bitOffset>
  7071. <bitWidth>7</bitWidth>
  7072. </field>
  7073. <field>
  7074. <name>SSE</name>
  7075. <description>Spread spectrum enable</description>
  7076. <bitOffset>16</bitOffset>
  7077. <bitWidth>1</bitWidth>
  7078. </field>
  7079. <field>
  7080. <name>SSPSC</name>
  7081. <description>Spread spectrum prescaler</description>
  7082. <bitOffset>15</bitOffset>
  7083. <bitWidth>1</bitWidth>
  7084. </field>
  7085. <field>
  7086. <name>PGPSC</name>
  7087. <description>pulse generator prescaler</description>
  7088. <bitOffset>12</bitOffset>
  7089. <bitWidth>3</bitWidth>
  7090. </field>
  7091. <field>
  7092. <name>MCV</name>
  7093. <description>Max count value</description>
  7094. <bitOffset>5</bitOffset>
  7095. <bitWidth>3</bitWidth>
  7096. </field>
  7097. <field>
  7098. <name>IODEF</name>
  7099. <description>I/O Default mode</description>
  7100. <bitOffset>4</bitOffset>
  7101. <bitWidth>1</bitWidth>
  7102. </field>
  7103. <field>
  7104. <name>SYNCPOL</name>
  7105. <description>Synchronization pin
  7106. polarity</description>
  7107. <bitOffset>3</bitOffset>
  7108. <bitWidth>1</bitWidth>
  7109. </field>
  7110. <field>
  7111. <name>AM</name>
  7112. <description>Acquisition mode</description>
  7113. <bitOffset>2</bitOffset>
  7114. <bitWidth>1</bitWidth>
  7115. </field>
  7116. <field>
  7117. <name>START</name>
  7118. <description>Start a new acquisition</description>
  7119. <bitOffset>1</bitOffset>
  7120. <bitWidth>1</bitWidth>
  7121. </field>
  7122. <field>
  7123. <name>TSCE</name>
  7124. <description>Touch sensing controller
  7125. enable</description>
  7126. <bitOffset>0</bitOffset>
  7127. <bitWidth>1</bitWidth>
  7128. </field>
  7129. </fields>
  7130. </register>
  7131. <register>
  7132. <name>IER</name>
  7133. <displayName>IER</displayName>
  7134. <description>interrupt enable register</description>
  7135. <addressOffset>0x4</addressOffset>
  7136. <size>0x20</size>
  7137. <access>read-write</access>
  7138. <resetValue>0x00000000</resetValue>
  7139. <fields>
  7140. <field>
  7141. <name>MCEIE</name>
  7142. <description>Max count error interrupt
  7143. enable</description>
  7144. <bitOffset>1</bitOffset>
  7145. <bitWidth>1</bitWidth>
  7146. </field>
  7147. <field>
  7148. <name>EOAIE</name>
  7149. <description>End of acquisition interrupt
  7150. enable</description>
  7151. <bitOffset>0</bitOffset>
  7152. <bitWidth>1</bitWidth>
  7153. </field>
  7154. </fields>
  7155. </register>
  7156. <register>
  7157. <name>ICR</name>
  7158. <displayName>ICR</displayName>
  7159. <description>interrupt clear register</description>
  7160. <addressOffset>0x8</addressOffset>
  7161. <size>0x20</size>
  7162. <access>read-write</access>
  7163. <resetValue>0x00000000</resetValue>
  7164. <fields>
  7165. <field>
  7166. <name>MCEIC</name>
  7167. <description>Max count error interrupt
  7168. clear</description>
  7169. <bitOffset>1</bitOffset>
  7170. <bitWidth>1</bitWidth>
  7171. </field>
  7172. <field>
  7173. <name>EOAIC</name>
  7174. <description>End of acquisition interrupt
  7175. clear</description>
  7176. <bitOffset>0</bitOffset>
  7177. <bitWidth>1</bitWidth>
  7178. </field>
  7179. </fields>
  7180. </register>
  7181. <register>
  7182. <name>ISR</name>
  7183. <displayName>ISR</displayName>
  7184. <description>interrupt status register</description>
  7185. <addressOffset>0xC</addressOffset>
  7186. <size>0x20</size>
  7187. <access>read-write</access>
  7188. <resetValue>0x00000000</resetValue>
  7189. <fields>
  7190. <field>
  7191. <name>MCEF</name>
  7192. <description>Max count error flag</description>
  7193. <bitOffset>1</bitOffset>
  7194. <bitWidth>1</bitWidth>
  7195. </field>
  7196. <field>
  7197. <name>EOAF</name>
  7198. <description>End of acquisition flag</description>
  7199. <bitOffset>0</bitOffset>
  7200. <bitWidth>1</bitWidth>
  7201. </field>
  7202. </fields>
  7203. </register>
  7204. <register>
  7205. <name>IOHCR</name>
  7206. <displayName>IOHCR</displayName>
  7207. <description>I/O hysteresis control
  7208. register</description>
  7209. <addressOffset>0x10</addressOffset>
  7210. <size>0x20</size>
  7211. <access>read-write</access>
  7212. <resetValue>0xFFFFFFFF</resetValue>
  7213. <fields>
  7214. <field>
  7215. <name>G8_IO4</name>
  7216. <description>G8_IO4</description>
  7217. <bitOffset>31</bitOffset>
  7218. <bitWidth>1</bitWidth>
  7219. </field>
  7220. <field>
  7221. <name>G8_IO3</name>
  7222. <description>G8_IO3</description>
  7223. <bitOffset>30</bitOffset>
  7224. <bitWidth>1</bitWidth>
  7225. </field>
  7226. <field>
  7227. <name>G8_IO2</name>
  7228. <description>G8_IO2</description>
  7229. <bitOffset>29</bitOffset>
  7230. <bitWidth>1</bitWidth>
  7231. </field>
  7232. <field>
  7233. <name>G8_IO1</name>
  7234. <description>G8_IO1</description>
  7235. <bitOffset>28</bitOffset>
  7236. <bitWidth>1</bitWidth>
  7237. </field>
  7238. <field>
  7239. <name>G7_IO4</name>
  7240. <description>G7_IO4</description>
  7241. <bitOffset>27</bitOffset>
  7242. <bitWidth>1</bitWidth>
  7243. </field>
  7244. <field>
  7245. <name>G7_IO3</name>
  7246. <description>G7_IO3</description>
  7247. <bitOffset>26</bitOffset>
  7248. <bitWidth>1</bitWidth>
  7249. </field>
  7250. <field>
  7251. <name>G7_IO2</name>
  7252. <description>G7_IO2</description>
  7253. <bitOffset>25</bitOffset>
  7254. <bitWidth>1</bitWidth>
  7255. </field>
  7256. <field>
  7257. <name>G7_IO1</name>
  7258. <description>G7_IO1</description>
  7259. <bitOffset>24</bitOffset>
  7260. <bitWidth>1</bitWidth>
  7261. </field>
  7262. <field>
  7263. <name>G6_IO4</name>
  7264. <description>G6_IO4</description>
  7265. <bitOffset>23</bitOffset>
  7266. <bitWidth>1</bitWidth>
  7267. </field>
  7268. <field>
  7269. <name>G6_IO3</name>
  7270. <description>G6_IO3</description>
  7271. <bitOffset>22</bitOffset>
  7272. <bitWidth>1</bitWidth>
  7273. </field>
  7274. <field>
  7275. <name>G6_IO2</name>
  7276. <description>G6_IO2</description>
  7277. <bitOffset>21</bitOffset>
  7278. <bitWidth>1</bitWidth>
  7279. </field>
  7280. <field>
  7281. <name>G6_IO1</name>
  7282. <description>G6_IO1</description>
  7283. <bitOffset>20</bitOffset>
  7284. <bitWidth>1</bitWidth>
  7285. </field>
  7286. <field>
  7287. <name>G5_IO4</name>
  7288. <description>G5_IO4</description>
  7289. <bitOffset>19</bitOffset>
  7290. <bitWidth>1</bitWidth>
  7291. </field>
  7292. <field>
  7293. <name>G5_IO3</name>
  7294. <description>G5_IO3</description>
  7295. <bitOffset>18</bitOffset>
  7296. <bitWidth>1</bitWidth>
  7297. </field>
  7298. <field>
  7299. <name>G5_IO2</name>
  7300. <description>G5_IO2</description>
  7301. <bitOffset>17</bitOffset>
  7302. <bitWidth>1</bitWidth>
  7303. </field>
  7304. <field>
  7305. <name>G5_IO1</name>
  7306. <description>G5_IO1</description>
  7307. <bitOffset>16</bitOffset>
  7308. <bitWidth>1</bitWidth>
  7309. </field>
  7310. <field>
  7311. <name>G4_IO4</name>
  7312. <description>G4_IO4</description>
  7313. <bitOffset>15</bitOffset>
  7314. <bitWidth>1</bitWidth>
  7315. </field>
  7316. <field>
  7317. <name>G4_IO3</name>
  7318. <description>G4_IO3</description>
  7319. <bitOffset>14</bitOffset>
  7320. <bitWidth>1</bitWidth>
  7321. </field>
  7322. <field>
  7323. <name>G4_IO2</name>
  7324. <description>G4_IO2</description>
  7325. <bitOffset>13</bitOffset>
  7326. <bitWidth>1</bitWidth>
  7327. </field>
  7328. <field>
  7329. <name>G4_IO1</name>
  7330. <description>G4_IO1</description>
  7331. <bitOffset>12</bitOffset>
  7332. <bitWidth>1</bitWidth>
  7333. </field>
  7334. <field>
  7335. <name>G3_IO4</name>
  7336. <description>G3_IO4</description>
  7337. <bitOffset>11</bitOffset>
  7338. <bitWidth>1</bitWidth>
  7339. </field>
  7340. <field>
  7341. <name>G3_IO3</name>
  7342. <description>G3_IO3</description>
  7343. <bitOffset>10</bitOffset>
  7344. <bitWidth>1</bitWidth>
  7345. </field>
  7346. <field>
  7347. <name>G3_IO2</name>
  7348. <description>G3_IO2</description>
  7349. <bitOffset>9</bitOffset>
  7350. <bitWidth>1</bitWidth>
  7351. </field>
  7352. <field>
  7353. <name>G3_IO1</name>
  7354. <description>G3_IO1</description>
  7355. <bitOffset>8</bitOffset>
  7356. <bitWidth>1</bitWidth>
  7357. </field>
  7358. <field>
  7359. <name>G2_IO4</name>
  7360. <description>G2_IO4</description>
  7361. <bitOffset>7</bitOffset>
  7362. <bitWidth>1</bitWidth>
  7363. </field>
  7364. <field>
  7365. <name>G2_IO3</name>
  7366. <description>G2_IO3</description>
  7367. <bitOffset>6</bitOffset>
  7368. <bitWidth>1</bitWidth>
  7369. </field>
  7370. <field>
  7371. <name>G2_IO2</name>
  7372. <description>G2_IO2</description>
  7373. <bitOffset>5</bitOffset>
  7374. <bitWidth>1</bitWidth>
  7375. </field>
  7376. <field>
  7377. <name>G2_IO1</name>
  7378. <description>G2_IO1</description>
  7379. <bitOffset>4</bitOffset>
  7380. <bitWidth>1</bitWidth>
  7381. </field>
  7382. <field>
  7383. <name>G1_IO4</name>
  7384. <description>G1_IO4</description>
  7385. <bitOffset>3</bitOffset>
  7386. <bitWidth>1</bitWidth>
  7387. </field>
  7388. <field>
  7389. <name>G1_IO3</name>
  7390. <description>G1_IO3</description>
  7391. <bitOffset>2</bitOffset>
  7392. <bitWidth>1</bitWidth>
  7393. </field>
  7394. <field>
  7395. <name>G1_IO2</name>
  7396. <description>G1_IO2</description>
  7397. <bitOffset>1</bitOffset>
  7398. <bitWidth>1</bitWidth>
  7399. </field>
  7400. <field>
  7401. <name>G1_IO1</name>
  7402. <description>G1_IO1</description>
  7403. <bitOffset>0</bitOffset>
  7404. <bitWidth>1</bitWidth>
  7405. </field>
  7406. </fields>
  7407. </register>
  7408. <register>
  7409. <name>IOASCR</name>
  7410. <displayName>IOASCR</displayName>
  7411. <description>I/O analog switch control
  7412. register</description>
  7413. <addressOffset>0x18</addressOffset>
  7414. <size>0x20</size>
  7415. <access>read-write</access>
  7416. <resetValue>0x00000000</resetValue>
  7417. <fields>
  7418. <field>
  7419. <name>G8_IO4</name>
  7420. <description>G8_IO4</description>
  7421. <bitOffset>31</bitOffset>
  7422. <bitWidth>1</bitWidth>
  7423. </field>
  7424. <field>
  7425. <name>G8_IO3</name>
  7426. <description>G8_IO3</description>
  7427. <bitOffset>30</bitOffset>
  7428. <bitWidth>1</bitWidth>
  7429. </field>
  7430. <field>
  7431. <name>G8_IO2</name>
  7432. <description>G8_IO2</description>
  7433. <bitOffset>29</bitOffset>
  7434. <bitWidth>1</bitWidth>
  7435. </field>
  7436. <field>
  7437. <name>G8_IO1</name>
  7438. <description>G8_IO1</description>
  7439. <bitOffset>28</bitOffset>
  7440. <bitWidth>1</bitWidth>
  7441. </field>
  7442. <field>
  7443. <name>G7_IO4</name>
  7444. <description>G7_IO4</description>
  7445. <bitOffset>27</bitOffset>
  7446. <bitWidth>1</bitWidth>
  7447. </field>
  7448. <field>
  7449. <name>G7_IO3</name>
  7450. <description>G7_IO3</description>
  7451. <bitOffset>26</bitOffset>
  7452. <bitWidth>1</bitWidth>
  7453. </field>
  7454. <field>
  7455. <name>G7_IO2</name>
  7456. <description>G7_IO2</description>
  7457. <bitOffset>25</bitOffset>
  7458. <bitWidth>1</bitWidth>
  7459. </field>
  7460. <field>
  7461. <name>G7_IO1</name>
  7462. <description>G7_IO1</description>
  7463. <bitOffset>24</bitOffset>
  7464. <bitWidth>1</bitWidth>
  7465. </field>
  7466. <field>
  7467. <name>G6_IO4</name>
  7468. <description>G6_IO4</description>
  7469. <bitOffset>23</bitOffset>
  7470. <bitWidth>1</bitWidth>
  7471. </field>
  7472. <field>
  7473. <name>G6_IO3</name>
  7474. <description>G6_IO3</description>
  7475. <bitOffset>22</bitOffset>
  7476. <bitWidth>1</bitWidth>
  7477. </field>
  7478. <field>
  7479. <name>G6_IO2</name>
  7480. <description>G6_IO2</description>
  7481. <bitOffset>21</bitOffset>
  7482. <bitWidth>1</bitWidth>
  7483. </field>
  7484. <field>
  7485. <name>G6_IO1</name>
  7486. <description>G6_IO1</description>
  7487. <bitOffset>20</bitOffset>
  7488. <bitWidth>1</bitWidth>
  7489. </field>
  7490. <field>
  7491. <name>G5_IO4</name>
  7492. <description>G5_IO4</description>
  7493. <bitOffset>19</bitOffset>
  7494. <bitWidth>1</bitWidth>
  7495. </field>
  7496. <field>
  7497. <name>G5_IO3</name>
  7498. <description>G5_IO3</description>
  7499. <bitOffset>18</bitOffset>
  7500. <bitWidth>1</bitWidth>
  7501. </field>
  7502. <field>
  7503. <name>G5_IO2</name>
  7504. <description>G5_IO2</description>
  7505. <bitOffset>17</bitOffset>
  7506. <bitWidth>1</bitWidth>
  7507. </field>
  7508. <field>
  7509. <name>G5_IO1</name>
  7510. <description>G5_IO1</description>
  7511. <bitOffset>16</bitOffset>
  7512. <bitWidth>1</bitWidth>
  7513. </field>
  7514. <field>
  7515. <name>G4_IO4</name>
  7516. <description>G4_IO4</description>
  7517. <bitOffset>15</bitOffset>
  7518. <bitWidth>1</bitWidth>
  7519. </field>
  7520. <field>
  7521. <name>G4_IO3</name>
  7522. <description>G4_IO3</description>
  7523. <bitOffset>14</bitOffset>
  7524. <bitWidth>1</bitWidth>
  7525. </field>
  7526. <field>
  7527. <name>G4_IO2</name>
  7528. <description>G4_IO2</description>
  7529. <bitOffset>13</bitOffset>
  7530. <bitWidth>1</bitWidth>
  7531. </field>
  7532. <field>
  7533. <name>G4_IO1</name>
  7534. <description>G4_IO1</description>
  7535. <bitOffset>12</bitOffset>
  7536. <bitWidth>1</bitWidth>
  7537. </field>
  7538. <field>
  7539. <name>G3_IO4</name>
  7540. <description>G3_IO4</description>
  7541. <bitOffset>11</bitOffset>
  7542. <bitWidth>1</bitWidth>
  7543. </field>
  7544. <field>
  7545. <name>G3_IO3</name>
  7546. <description>G3_IO3</description>
  7547. <bitOffset>10</bitOffset>
  7548. <bitWidth>1</bitWidth>
  7549. </field>
  7550. <field>
  7551. <name>G3_IO2</name>
  7552. <description>G3_IO2</description>
  7553. <bitOffset>9</bitOffset>
  7554. <bitWidth>1</bitWidth>
  7555. </field>
  7556. <field>
  7557. <name>G3_IO1</name>
  7558. <description>G3_IO1</description>
  7559. <bitOffset>8</bitOffset>
  7560. <bitWidth>1</bitWidth>
  7561. </field>
  7562. <field>
  7563. <name>G2_IO4</name>
  7564. <description>G2_IO4</description>
  7565. <bitOffset>7</bitOffset>
  7566. <bitWidth>1</bitWidth>
  7567. </field>
  7568. <field>
  7569. <name>G2_IO3</name>
  7570. <description>G2_IO3</description>
  7571. <bitOffset>6</bitOffset>
  7572. <bitWidth>1</bitWidth>
  7573. </field>
  7574. <field>
  7575. <name>G2_IO2</name>
  7576. <description>G2_IO2</description>
  7577. <bitOffset>5</bitOffset>
  7578. <bitWidth>1</bitWidth>
  7579. </field>
  7580. <field>
  7581. <name>G2_IO1</name>
  7582. <description>G2_IO1</description>
  7583. <bitOffset>4</bitOffset>
  7584. <bitWidth>1</bitWidth>
  7585. </field>
  7586. <field>
  7587. <name>G1_IO4</name>
  7588. <description>G1_IO4</description>
  7589. <bitOffset>3</bitOffset>
  7590. <bitWidth>1</bitWidth>
  7591. </field>
  7592. <field>
  7593. <name>G1_IO3</name>
  7594. <description>G1_IO3</description>
  7595. <bitOffset>2</bitOffset>
  7596. <bitWidth>1</bitWidth>
  7597. </field>
  7598. <field>
  7599. <name>G1_IO2</name>
  7600. <description>G1_IO2</description>
  7601. <bitOffset>1</bitOffset>
  7602. <bitWidth>1</bitWidth>
  7603. </field>
  7604. <field>
  7605. <name>G1_IO1</name>
  7606. <description>G1_IO1</description>
  7607. <bitOffset>0</bitOffset>
  7608. <bitWidth>1</bitWidth>
  7609. </field>
  7610. </fields>
  7611. </register>
  7612. <register>
  7613. <name>IOSCR</name>
  7614. <displayName>IOSCR</displayName>
  7615. <description>I/O sampling control register</description>
  7616. <addressOffset>0x20</addressOffset>
  7617. <size>0x20</size>
  7618. <access>read-write</access>
  7619. <resetValue>0x00000000</resetValue>
  7620. <fields>
  7621. <field>
  7622. <name>G8_IO4</name>
  7623. <description>G8_IO4</description>
  7624. <bitOffset>31</bitOffset>
  7625. <bitWidth>1</bitWidth>
  7626. </field>
  7627. <field>
  7628. <name>G8_IO3</name>
  7629. <description>G8_IO3</description>
  7630. <bitOffset>30</bitOffset>
  7631. <bitWidth>1</bitWidth>
  7632. </field>
  7633. <field>
  7634. <name>G8_IO2</name>
  7635. <description>G8_IO2</description>
  7636. <bitOffset>29</bitOffset>
  7637. <bitWidth>1</bitWidth>
  7638. </field>
  7639. <field>
  7640. <name>G8_IO1</name>
  7641. <description>G8_IO1</description>
  7642. <bitOffset>28</bitOffset>
  7643. <bitWidth>1</bitWidth>
  7644. </field>
  7645. <field>
  7646. <name>G7_IO4</name>
  7647. <description>G7_IO4</description>
  7648. <bitOffset>27</bitOffset>
  7649. <bitWidth>1</bitWidth>
  7650. </field>
  7651. <field>
  7652. <name>G7_IO3</name>
  7653. <description>G7_IO3</description>
  7654. <bitOffset>26</bitOffset>
  7655. <bitWidth>1</bitWidth>
  7656. </field>
  7657. <field>
  7658. <name>G7_IO2</name>
  7659. <description>G7_IO2</description>
  7660. <bitOffset>25</bitOffset>
  7661. <bitWidth>1</bitWidth>
  7662. </field>
  7663. <field>
  7664. <name>G7_IO1</name>
  7665. <description>G7_IO1</description>
  7666. <bitOffset>24</bitOffset>
  7667. <bitWidth>1</bitWidth>
  7668. </field>
  7669. <field>
  7670. <name>G6_IO4</name>
  7671. <description>G6_IO4</description>
  7672. <bitOffset>23</bitOffset>
  7673. <bitWidth>1</bitWidth>
  7674. </field>
  7675. <field>
  7676. <name>G6_IO3</name>
  7677. <description>G6_IO3</description>
  7678. <bitOffset>22</bitOffset>
  7679. <bitWidth>1</bitWidth>
  7680. </field>
  7681. <field>
  7682. <name>G6_IO2</name>
  7683. <description>G6_IO2</description>
  7684. <bitOffset>21</bitOffset>
  7685. <bitWidth>1</bitWidth>
  7686. </field>
  7687. <field>
  7688. <name>G6_IO1</name>
  7689. <description>G6_IO1</description>
  7690. <bitOffset>20</bitOffset>
  7691. <bitWidth>1</bitWidth>
  7692. </field>
  7693. <field>
  7694. <name>G5_IO4</name>
  7695. <description>G5_IO4</description>
  7696. <bitOffset>19</bitOffset>
  7697. <bitWidth>1</bitWidth>
  7698. </field>
  7699. <field>
  7700. <name>G5_IO3</name>
  7701. <description>G5_IO3</description>
  7702. <bitOffset>18</bitOffset>
  7703. <bitWidth>1</bitWidth>
  7704. </field>
  7705. <field>
  7706. <name>G5_IO2</name>
  7707. <description>G5_IO2</description>
  7708. <bitOffset>17</bitOffset>
  7709. <bitWidth>1</bitWidth>
  7710. </field>
  7711. <field>
  7712. <name>G5_IO1</name>
  7713. <description>G5_IO1</description>
  7714. <bitOffset>16</bitOffset>
  7715. <bitWidth>1</bitWidth>
  7716. </field>
  7717. <field>
  7718. <name>G4_IO4</name>
  7719. <description>G4_IO4</description>
  7720. <bitOffset>15</bitOffset>
  7721. <bitWidth>1</bitWidth>
  7722. </field>
  7723. <field>
  7724. <name>G4_IO3</name>
  7725. <description>G4_IO3</description>
  7726. <bitOffset>14</bitOffset>
  7727. <bitWidth>1</bitWidth>
  7728. </field>
  7729. <field>
  7730. <name>G4_IO2</name>
  7731. <description>G4_IO2</description>
  7732. <bitOffset>13</bitOffset>
  7733. <bitWidth>1</bitWidth>
  7734. </field>
  7735. <field>
  7736. <name>G4_IO1</name>
  7737. <description>G4_IO1</description>
  7738. <bitOffset>12</bitOffset>
  7739. <bitWidth>1</bitWidth>
  7740. </field>
  7741. <field>
  7742. <name>G3_IO4</name>
  7743. <description>G3_IO4</description>
  7744. <bitOffset>11</bitOffset>
  7745. <bitWidth>1</bitWidth>
  7746. </field>
  7747. <field>
  7748. <name>G3_IO3</name>
  7749. <description>G3_IO3</description>
  7750. <bitOffset>10</bitOffset>
  7751. <bitWidth>1</bitWidth>
  7752. </field>
  7753. <field>
  7754. <name>G3_IO2</name>
  7755. <description>G3_IO2</description>
  7756. <bitOffset>9</bitOffset>
  7757. <bitWidth>1</bitWidth>
  7758. </field>
  7759. <field>
  7760. <name>G3_IO1</name>
  7761. <description>G3_IO1</description>
  7762. <bitOffset>8</bitOffset>
  7763. <bitWidth>1</bitWidth>
  7764. </field>
  7765. <field>
  7766. <name>G2_IO4</name>
  7767. <description>G2_IO4</description>
  7768. <bitOffset>7</bitOffset>
  7769. <bitWidth>1</bitWidth>
  7770. </field>
  7771. <field>
  7772. <name>G2_IO3</name>
  7773. <description>G2_IO3</description>
  7774. <bitOffset>6</bitOffset>
  7775. <bitWidth>1</bitWidth>
  7776. </field>
  7777. <field>
  7778. <name>G2_IO2</name>
  7779. <description>G2_IO2</description>
  7780. <bitOffset>5</bitOffset>
  7781. <bitWidth>1</bitWidth>
  7782. </field>
  7783. <field>
  7784. <name>G2_IO1</name>
  7785. <description>G2_IO1</description>
  7786. <bitOffset>4</bitOffset>
  7787. <bitWidth>1</bitWidth>
  7788. </field>
  7789. <field>
  7790. <name>G1_IO4</name>
  7791. <description>G1_IO4</description>
  7792. <bitOffset>3</bitOffset>
  7793. <bitWidth>1</bitWidth>
  7794. </field>
  7795. <field>
  7796. <name>G1_IO3</name>
  7797. <description>G1_IO3</description>
  7798. <bitOffset>2</bitOffset>
  7799. <bitWidth>1</bitWidth>
  7800. </field>
  7801. <field>
  7802. <name>G1_IO2</name>
  7803. <description>G1_IO2</description>
  7804. <bitOffset>1</bitOffset>
  7805. <bitWidth>1</bitWidth>
  7806. </field>
  7807. <field>
  7808. <name>G1_IO1</name>
  7809. <description>G1_IO1</description>
  7810. <bitOffset>0</bitOffset>
  7811. <bitWidth>1</bitWidth>
  7812. </field>
  7813. </fields>
  7814. </register>
  7815. <register>
  7816. <name>IOCCR</name>
  7817. <displayName>IOCCR</displayName>
  7818. <description>I/O channel control register</description>
  7819. <addressOffset>0x28</addressOffset>
  7820. <size>0x20</size>
  7821. <access>read-write</access>
  7822. <resetValue>0x00000000</resetValue>
  7823. <fields>
  7824. <field>
  7825. <name>G8_IO4</name>
  7826. <description>G8_IO4</description>
  7827. <bitOffset>31</bitOffset>
  7828. <bitWidth>1</bitWidth>
  7829. </field>
  7830. <field>
  7831. <name>G8_IO3</name>
  7832. <description>G8_IO3</description>
  7833. <bitOffset>30</bitOffset>
  7834. <bitWidth>1</bitWidth>
  7835. </field>
  7836. <field>
  7837. <name>G8_IO2</name>
  7838. <description>G8_IO2</description>
  7839. <bitOffset>29</bitOffset>
  7840. <bitWidth>1</bitWidth>
  7841. </field>
  7842. <field>
  7843. <name>G8_IO1</name>
  7844. <description>G8_IO1</description>
  7845. <bitOffset>28</bitOffset>
  7846. <bitWidth>1</bitWidth>
  7847. </field>
  7848. <field>
  7849. <name>G7_IO4</name>
  7850. <description>G7_IO4</description>
  7851. <bitOffset>27</bitOffset>
  7852. <bitWidth>1</bitWidth>
  7853. </field>
  7854. <field>
  7855. <name>G7_IO3</name>
  7856. <description>G7_IO3</description>
  7857. <bitOffset>26</bitOffset>
  7858. <bitWidth>1</bitWidth>
  7859. </field>
  7860. <field>
  7861. <name>G7_IO2</name>
  7862. <description>G7_IO2</description>
  7863. <bitOffset>25</bitOffset>
  7864. <bitWidth>1</bitWidth>
  7865. </field>
  7866. <field>
  7867. <name>G7_IO1</name>
  7868. <description>G7_IO1</description>
  7869. <bitOffset>24</bitOffset>
  7870. <bitWidth>1</bitWidth>
  7871. </field>
  7872. <field>
  7873. <name>G6_IO4</name>
  7874. <description>G6_IO4</description>
  7875. <bitOffset>23</bitOffset>
  7876. <bitWidth>1</bitWidth>
  7877. </field>
  7878. <field>
  7879. <name>G6_IO3</name>
  7880. <description>G6_IO3</description>
  7881. <bitOffset>22</bitOffset>
  7882. <bitWidth>1</bitWidth>
  7883. </field>
  7884. <field>
  7885. <name>G6_IO2</name>
  7886. <description>G6_IO2</description>
  7887. <bitOffset>21</bitOffset>
  7888. <bitWidth>1</bitWidth>
  7889. </field>
  7890. <field>
  7891. <name>G6_IO1</name>
  7892. <description>G6_IO1</description>
  7893. <bitOffset>20</bitOffset>
  7894. <bitWidth>1</bitWidth>
  7895. </field>
  7896. <field>
  7897. <name>G5_IO4</name>
  7898. <description>G5_IO4</description>
  7899. <bitOffset>19</bitOffset>
  7900. <bitWidth>1</bitWidth>
  7901. </field>
  7902. <field>
  7903. <name>G5_IO3</name>
  7904. <description>G5_IO3</description>
  7905. <bitOffset>18</bitOffset>
  7906. <bitWidth>1</bitWidth>
  7907. </field>
  7908. <field>
  7909. <name>G5_IO2</name>
  7910. <description>G5_IO2</description>
  7911. <bitOffset>17</bitOffset>
  7912. <bitWidth>1</bitWidth>
  7913. </field>
  7914. <field>
  7915. <name>G5_IO1</name>
  7916. <description>G5_IO1</description>
  7917. <bitOffset>16</bitOffset>
  7918. <bitWidth>1</bitWidth>
  7919. </field>
  7920. <field>
  7921. <name>G4_IO4</name>
  7922. <description>G4_IO4</description>
  7923. <bitOffset>15</bitOffset>
  7924. <bitWidth>1</bitWidth>
  7925. </field>
  7926. <field>
  7927. <name>G4_IO3</name>
  7928. <description>G4_IO3</description>
  7929. <bitOffset>14</bitOffset>
  7930. <bitWidth>1</bitWidth>
  7931. </field>
  7932. <field>
  7933. <name>G4_IO2</name>
  7934. <description>G4_IO2</description>
  7935. <bitOffset>13</bitOffset>
  7936. <bitWidth>1</bitWidth>
  7937. </field>
  7938. <field>
  7939. <name>G4_IO1</name>
  7940. <description>G4_IO1</description>
  7941. <bitOffset>12</bitOffset>
  7942. <bitWidth>1</bitWidth>
  7943. </field>
  7944. <field>
  7945. <name>G3_IO4</name>
  7946. <description>G3_IO4</description>
  7947. <bitOffset>11</bitOffset>
  7948. <bitWidth>1</bitWidth>
  7949. </field>
  7950. <field>
  7951. <name>G3_IO3</name>
  7952. <description>G3_IO3</description>
  7953. <bitOffset>10</bitOffset>
  7954. <bitWidth>1</bitWidth>
  7955. </field>
  7956. <field>
  7957. <name>G3_IO2</name>
  7958. <description>G3_IO2</description>
  7959. <bitOffset>9</bitOffset>
  7960. <bitWidth>1</bitWidth>
  7961. </field>
  7962. <field>
  7963. <name>G3_IO1</name>
  7964. <description>G3_IO1</description>
  7965. <bitOffset>8</bitOffset>
  7966. <bitWidth>1</bitWidth>
  7967. </field>
  7968. <field>
  7969. <name>G2_IO4</name>
  7970. <description>G2_IO4</description>
  7971. <bitOffset>7</bitOffset>
  7972. <bitWidth>1</bitWidth>
  7973. </field>
  7974. <field>
  7975. <name>G2_IO3</name>
  7976. <description>G2_IO3</description>
  7977. <bitOffset>6</bitOffset>
  7978. <bitWidth>1</bitWidth>
  7979. </field>
  7980. <field>
  7981. <name>G2_IO2</name>
  7982. <description>G2_IO2</description>
  7983. <bitOffset>5</bitOffset>
  7984. <bitWidth>1</bitWidth>
  7985. </field>
  7986. <field>
  7987. <name>G2_IO1</name>
  7988. <description>G2_IO1</description>
  7989. <bitOffset>4</bitOffset>
  7990. <bitWidth>1</bitWidth>
  7991. </field>
  7992. <field>
  7993. <name>G1_IO4</name>
  7994. <description>G1_IO4</description>
  7995. <bitOffset>3</bitOffset>
  7996. <bitWidth>1</bitWidth>
  7997. </field>
  7998. <field>
  7999. <name>G1_IO3</name>
  8000. <description>G1_IO3</description>
  8001. <bitOffset>2</bitOffset>
  8002. <bitWidth>1</bitWidth>
  8003. </field>
  8004. <field>
  8005. <name>G1_IO2</name>
  8006. <description>G1_IO2</description>
  8007. <bitOffset>1</bitOffset>
  8008. <bitWidth>1</bitWidth>
  8009. </field>
  8010. <field>
  8011. <name>G1_IO1</name>
  8012. <description>G1_IO1</description>
  8013. <bitOffset>0</bitOffset>
  8014. <bitWidth>1</bitWidth>
  8015. </field>
  8016. </fields>
  8017. </register>
  8018. <register>
  8019. <name>IOGCSR</name>
  8020. <displayName>IOGCSR</displayName>
  8021. <description>I/O group control status
  8022. register</description>
  8023. <addressOffset>0x30</addressOffset>
  8024. <size>0x20</size>
  8025. <resetValue>0x00000000</resetValue>
  8026. <fields>
  8027. <field>
  8028. <name>G8S</name>
  8029. <description>Analog I/O group x status</description>
  8030. <bitOffset>23</bitOffset>
  8031. <bitWidth>1</bitWidth>
  8032. <access>read-only</access>
  8033. </field>
  8034. <field>
  8035. <name>G7S</name>
  8036. <description>Analog I/O group x status</description>
  8037. <bitOffset>22</bitOffset>
  8038. <bitWidth>1</bitWidth>
  8039. <access>read-only</access>
  8040. </field>
  8041. <field>
  8042. <name>G6S</name>
  8043. <description>Analog I/O group x status</description>
  8044. <bitOffset>21</bitOffset>
  8045. <bitWidth>1</bitWidth>
  8046. <access>read-only</access>
  8047. </field>
  8048. <field>
  8049. <name>G5S</name>
  8050. <description>Analog I/O group x status</description>
  8051. <bitOffset>20</bitOffset>
  8052. <bitWidth>1</bitWidth>
  8053. <access>read-only</access>
  8054. </field>
  8055. <field>
  8056. <name>G4S</name>
  8057. <description>Analog I/O group x status</description>
  8058. <bitOffset>19</bitOffset>
  8059. <bitWidth>1</bitWidth>
  8060. <access>read-only</access>
  8061. </field>
  8062. <field>
  8063. <name>G3S</name>
  8064. <description>Analog I/O group x status</description>
  8065. <bitOffset>18</bitOffset>
  8066. <bitWidth>1</bitWidth>
  8067. <access>read-only</access>
  8068. </field>
  8069. <field>
  8070. <name>G2S</name>
  8071. <description>Analog I/O group x status</description>
  8072. <bitOffset>17</bitOffset>
  8073. <bitWidth>1</bitWidth>
  8074. <access>read-only</access>
  8075. </field>
  8076. <field>
  8077. <name>G1S</name>
  8078. <description>Analog I/O group x status</description>
  8079. <bitOffset>16</bitOffset>
  8080. <bitWidth>1</bitWidth>
  8081. <access>read-only</access>
  8082. </field>
  8083. <field>
  8084. <name>G8E</name>
  8085. <description>Analog I/O group x enable</description>
  8086. <bitOffset>7</bitOffset>
  8087. <bitWidth>1</bitWidth>
  8088. <access>read-write</access>
  8089. </field>
  8090. <field>
  8091. <name>G7E</name>
  8092. <description>Analog I/O group x enable</description>
  8093. <bitOffset>6</bitOffset>
  8094. <bitWidth>1</bitWidth>
  8095. <access>read-write</access>
  8096. </field>
  8097. <field>
  8098. <name>G6E</name>
  8099. <description>Analog I/O group x enable</description>
  8100. <bitOffset>5</bitOffset>
  8101. <bitWidth>1</bitWidth>
  8102. <access>read-write</access>
  8103. </field>
  8104. <field>
  8105. <name>G5E</name>
  8106. <description>Analog I/O group x enable</description>
  8107. <bitOffset>4</bitOffset>
  8108. <bitWidth>1</bitWidth>
  8109. <access>read-write</access>
  8110. </field>
  8111. <field>
  8112. <name>G4E</name>
  8113. <description>Analog I/O group x enable</description>
  8114. <bitOffset>3</bitOffset>
  8115. <bitWidth>1</bitWidth>
  8116. <access>read-write</access>
  8117. </field>
  8118. <field>
  8119. <name>G3E</name>
  8120. <description>Analog I/O group x enable</description>
  8121. <bitOffset>2</bitOffset>
  8122. <bitWidth>1</bitWidth>
  8123. <access>read-write</access>
  8124. </field>
  8125. <field>
  8126. <name>G2E</name>
  8127. <description>Analog I/O group x enable</description>
  8128. <bitOffset>1</bitOffset>
  8129. <bitWidth>1</bitWidth>
  8130. <access>read-write</access>
  8131. </field>
  8132. <field>
  8133. <name>G1E</name>
  8134. <description>Analog I/O group x enable</description>
  8135. <bitOffset>0</bitOffset>
  8136. <bitWidth>1</bitWidth>
  8137. <access>read-write</access>
  8138. </field>
  8139. </fields>
  8140. </register>
  8141. <register>
  8142. <name>IOG1CR</name>
  8143. <displayName>IOG1CR</displayName>
  8144. <description>I/O group x counter register</description>
  8145. <addressOffset>0x34</addressOffset>
  8146. <size>0x20</size>
  8147. <access>read-only</access>
  8148. <resetValue>0x00000000</resetValue>
  8149. <fields>
  8150. <field>
  8151. <name>CNT</name>
  8152. <description>Counter value</description>
  8153. <bitOffset>0</bitOffset>
  8154. <bitWidth>14</bitWidth>
  8155. </field>
  8156. </fields>
  8157. </register>
  8158. <register>
  8159. <name>IOG2CR</name>
  8160. <displayName>IOG2CR</displayName>
  8161. <description>I/O group x counter register</description>
  8162. <addressOffset>0x38</addressOffset>
  8163. <size>0x20</size>
  8164. <access>read-only</access>
  8165. <resetValue>0x00000000</resetValue>
  8166. <fields>
  8167. <field>
  8168. <name>CNT</name>
  8169. <description>Counter value</description>
  8170. <bitOffset>0</bitOffset>
  8171. <bitWidth>14</bitWidth>
  8172. </field>
  8173. </fields>
  8174. </register>
  8175. <register>
  8176. <name>IOG3CR</name>
  8177. <displayName>IOG3CR</displayName>
  8178. <description>I/O group x counter register</description>
  8179. <addressOffset>0x3C</addressOffset>
  8180. <size>0x20</size>
  8181. <access>read-only</access>
  8182. <resetValue>0x00000000</resetValue>
  8183. <fields>
  8184. <field>
  8185. <name>CNT</name>
  8186. <description>Counter value</description>
  8187. <bitOffset>0</bitOffset>
  8188. <bitWidth>14</bitWidth>
  8189. </field>
  8190. </fields>
  8191. </register>
  8192. <register>
  8193. <name>IOG4CR</name>
  8194. <displayName>IOG4CR</displayName>
  8195. <description>I/O group x counter register</description>
  8196. <addressOffset>0x40</addressOffset>
  8197. <size>0x20</size>
  8198. <access>read-only</access>
  8199. <resetValue>0x00000000</resetValue>
  8200. <fields>
  8201. <field>
  8202. <name>CNT</name>
  8203. <description>Counter value</description>
  8204. <bitOffset>0</bitOffset>
  8205. <bitWidth>14</bitWidth>
  8206. </field>
  8207. </fields>
  8208. </register>
  8209. <register>
  8210. <name>IOG5CR</name>
  8211. <displayName>IOG5CR</displayName>
  8212. <description>I/O group x counter register</description>
  8213. <addressOffset>0x44</addressOffset>
  8214. <size>0x20</size>
  8215. <access>read-only</access>
  8216. <resetValue>0x00000000</resetValue>
  8217. <fields>
  8218. <field>
  8219. <name>CNT</name>
  8220. <description>Counter value</description>
  8221. <bitOffset>0</bitOffset>
  8222. <bitWidth>14</bitWidth>
  8223. </field>
  8224. </fields>
  8225. </register>
  8226. <register>
  8227. <name>IOG6CR</name>
  8228. <displayName>IOG6CR</displayName>
  8229. <description>I/O group x counter register</description>
  8230. <addressOffset>0x48</addressOffset>
  8231. <size>0x20</size>
  8232. <access>read-only</access>
  8233. <resetValue>0x00000000</resetValue>
  8234. <fields>
  8235. <field>
  8236. <name>CNT</name>
  8237. <description>Counter value</description>
  8238. <bitOffset>0</bitOffset>
  8239. <bitWidth>14</bitWidth>
  8240. </field>
  8241. </fields>
  8242. </register>
  8243. <register>
  8244. <name>IOG7CR</name>
  8245. <displayName>IOG7CR</displayName>
  8246. <description>I/O group x counter register</description>
  8247. <addressOffset>0x4C</addressOffset>
  8248. <size>0x20</size>
  8249. <access>read-only</access>
  8250. <resetValue>0x00000000</resetValue>
  8251. <fields>
  8252. <field>
  8253. <name>CNT</name>
  8254. <description>Counter value</description>
  8255. <bitOffset>0</bitOffset>
  8256. <bitWidth>14</bitWidth>
  8257. </field>
  8258. </fields>
  8259. </register>
  8260. <register>
  8261. <name>IOG8CR</name>
  8262. <displayName>IOG8CR</displayName>
  8263. <description>I/O group x counter register</description>
  8264. <addressOffset>0x50</addressOffset>
  8265. <size>0x20</size>
  8266. <access>read-only</access>
  8267. <resetValue>0x00000000</resetValue>
  8268. <fields>
  8269. <field>
  8270. <name>CNT</name>
  8271. <description>Counter value</description>
  8272. <bitOffset>0</bitOffset>
  8273. <bitWidth>14</bitWidth>
  8274. </field>
  8275. </fields>
  8276. </register>
  8277. </registers>
  8278. </peripheral>
  8279. <peripheral>
  8280. <name>IWDG</name>
  8281. <description>Independent watchdog</description>
  8282. <groupName>IWDG</groupName>
  8283. <baseAddress>0x40003000</baseAddress>
  8284. <addressBlock>
  8285. <offset>0x0</offset>
  8286. <size>0x400</size>
  8287. <usage>registers</usage>
  8288. </addressBlock>
  8289. <registers>
  8290. <register>
  8291. <name>KR</name>
  8292. <displayName>KR</displayName>
  8293. <description>Key register</description>
  8294. <addressOffset>0x0</addressOffset>
  8295. <size>0x20</size>
  8296. <access>write-only</access>
  8297. <resetValue>0x00000000</resetValue>
  8298. <fields>
  8299. <field>
  8300. <name>KEY</name>
  8301. <description>Key value (write only, read
  8302. 0x0000)</description>
  8303. <bitOffset>0</bitOffset>
  8304. <bitWidth>16</bitWidth>
  8305. </field>
  8306. </fields>
  8307. </register>
  8308. <register>
  8309. <name>PR</name>
  8310. <displayName>PR</displayName>
  8311. <description>Prescaler register</description>
  8312. <addressOffset>0x4</addressOffset>
  8313. <size>0x20</size>
  8314. <access>read-write</access>
  8315. <resetValue>0x00000000</resetValue>
  8316. <fields>
  8317. <field>
  8318. <name>PR</name>
  8319. <description>Prescaler divider</description>
  8320. <bitOffset>0</bitOffset>
  8321. <bitWidth>3</bitWidth>
  8322. </field>
  8323. </fields>
  8324. </register>
  8325. <register>
  8326. <name>RLR</name>
  8327. <displayName>RLR</displayName>
  8328. <description>Reload register</description>
  8329. <addressOffset>0x8</addressOffset>
  8330. <size>0x20</size>
  8331. <access>read-write</access>
  8332. <resetValue>0x00000FFF</resetValue>
  8333. <fields>
  8334. <field>
  8335. <name>RL</name>
  8336. <description>Watchdog counter reload
  8337. value</description>
  8338. <bitOffset>0</bitOffset>
  8339. <bitWidth>12</bitWidth>
  8340. </field>
  8341. </fields>
  8342. </register>
  8343. <register>
  8344. <name>SR</name>
  8345. <displayName>SR</displayName>
  8346. <description>Status register</description>
  8347. <addressOffset>0xC</addressOffset>
  8348. <size>0x20</size>
  8349. <access>read-only</access>
  8350. <resetValue>0x00000000</resetValue>
  8351. <fields>
  8352. <field>
  8353. <name>WVU</name>
  8354. <description>Watchdog counter window value
  8355. update</description>
  8356. <bitOffset>2</bitOffset>
  8357. <bitWidth>1</bitWidth>
  8358. </field>
  8359. <field>
  8360. <name>RVU</name>
  8361. <description>Watchdog counter reload value
  8362. update</description>
  8363. <bitOffset>1</bitOffset>
  8364. <bitWidth>1</bitWidth>
  8365. </field>
  8366. <field>
  8367. <name>PVU</name>
  8368. <description>Watchdog prescaler value
  8369. update</description>
  8370. <bitOffset>0</bitOffset>
  8371. <bitWidth>1</bitWidth>
  8372. </field>
  8373. </fields>
  8374. </register>
  8375. <register>
  8376. <name>WINR</name>
  8377. <displayName>WINR</displayName>
  8378. <description>Window register</description>
  8379. <addressOffset>0x10</addressOffset>
  8380. <size>0x20</size>
  8381. <access>read-write</access>
  8382. <resetValue>0x00000FFF</resetValue>
  8383. <fields>
  8384. <field>
  8385. <name>WIN</name>
  8386. <description>Watchdog counter window
  8387. value</description>
  8388. <bitOffset>0</bitOffset>
  8389. <bitWidth>12</bitWidth>
  8390. </field>
  8391. </fields>
  8392. </register>
  8393. </registers>
  8394. </peripheral>
  8395. <peripheral>
  8396. <name>WWDG</name>
  8397. <description>System window watchdog</description>
  8398. <groupName>WWDG</groupName>
  8399. <baseAddress>0x40002C00</baseAddress>
  8400. <addressBlock>
  8401. <offset>0x0</offset>
  8402. <size>0x400</size>
  8403. <usage>registers</usage>
  8404. </addressBlock>
  8405. <interrupt>
  8406. <name>WWDG</name>
  8407. <description>Window Watchdog interrupt</description>
  8408. <value>0</value>
  8409. </interrupt>
  8410. <registers>
  8411. <register>
  8412. <name>CR</name>
  8413. <displayName>CR</displayName>
  8414. <description>Control register</description>
  8415. <addressOffset>0x0</addressOffset>
  8416. <size>0x20</size>
  8417. <access>read-write</access>
  8418. <resetValue>0x0000007F</resetValue>
  8419. <fields>
  8420. <field>
  8421. <name>WDGA</name>
  8422. <description>Activation bit</description>
  8423. <bitOffset>7</bitOffset>
  8424. <bitWidth>1</bitWidth>
  8425. </field>
  8426. <field>
  8427. <name>T</name>
  8428. <description>7-bit counter (MSB to LSB)</description>
  8429. <bitOffset>0</bitOffset>
  8430. <bitWidth>7</bitWidth>
  8431. </field>
  8432. </fields>
  8433. </register>
  8434. <register>
  8435. <name>CFR</name>
  8436. <displayName>CFR</displayName>
  8437. <description>Configuration register</description>
  8438. <addressOffset>0x4</addressOffset>
  8439. <size>0x20</size>
  8440. <access>read-write</access>
  8441. <resetValue>0x0000007F</resetValue>
  8442. <fields>
  8443. <field>
  8444. <name>EWI</name>
  8445. <description>Early wakeup interrupt</description>
  8446. <bitOffset>9</bitOffset>
  8447. <bitWidth>1</bitWidth>
  8448. </field>
  8449. <field>
  8450. <name>WDGTB1</name>
  8451. <description>Timer base</description>
  8452. <bitOffset>8</bitOffset>
  8453. <bitWidth>1</bitWidth>
  8454. </field>
  8455. <field>
  8456. <name>WDGTB0</name>
  8457. <description>WDGTB0</description>
  8458. <bitOffset>7</bitOffset>
  8459. <bitWidth>1</bitWidth>
  8460. </field>
  8461. <field>
  8462. <name>W</name>
  8463. <description>7-bit window value</description>
  8464. <bitOffset>0</bitOffset>
  8465. <bitWidth>7</bitWidth>
  8466. </field>
  8467. </fields>
  8468. </register>
  8469. <register>
  8470. <name>SR</name>
  8471. <displayName>SR</displayName>
  8472. <description>Status register</description>
  8473. <addressOffset>0x8</addressOffset>
  8474. <size>0x20</size>
  8475. <access>read-writeOnce</access>
  8476. <resetValue>0x00000000</resetValue>
  8477. <fields>
  8478. <field>
  8479. <name>EWIF</name>
  8480. <description>Early wakeup interrupt
  8481. flag</description>
  8482. <bitOffset>0</bitOffset>
  8483. <bitWidth>1</bitWidth>
  8484. </field>
  8485. </fields>
  8486. </register>
  8487. </registers>
  8488. </peripheral>
  8489. <peripheral>
  8490. <name>COMP</name>
  8491. <description>Comparator</description>
  8492. <groupName>COMP</groupName>
  8493. <baseAddress>0x40010018</baseAddress>
  8494. <addressBlock>
  8495. <offset>0x0</offset>
  8496. <size>0x400</size>
  8497. <usage>registers</usage>
  8498. </addressBlock>
  8499. <registers>
  8500. <register>
  8501. <name>COMP1_CSR</name>
  8502. <displayName>COMP1_CSR</displayName>
  8503. <description>Comparator 1 control and status
  8504. register</description>
  8505. <addressOffset>0x18</addressOffset>
  8506. <size>0x20</size>
  8507. <resetValue>0x0</resetValue>
  8508. <fields>
  8509. <field>
  8510. <name>COMP1_EN</name>
  8511. <description>Comparator 1 enable bit</description>
  8512. <bitOffset>0</bitOffset>
  8513. <bitWidth>1</bitWidth>
  8514. <access>read-write</access>
  8515. </field>
  8516. <field>
  8517. <name>COMP1_INN_SEL</name>
  8518. <description>Comparator 1 Input Minus connection
  8519. configuration bit</description>
  8520. <bitOffset>4</bitOffset>
  8521. <bitWidth>2</bitWidth>
  8522. <access>read-write</access>
  8523. </field>
  8524. <field>
  8525. <name>COMP1_WM</name>
  8526. <description>Comparator 1 window mode selection
  8527. bit</description>
  8528. <bitOffset>8</bitOffset>
  8529. <bitWidth>1</bitWidth>
  8530. <access>read-write</access>
  8531. </field>
  8532. <field>
  8533. <name>COMP1_OUT_SEL</name>
  8534. <description>COMP1 output select</description>
  8535. <bitOffset>12</bitOffset>
  8536. <bitWidth>3</bitWidth>
  8537. <access>read-write</access>
  8538. </field>
  8539. <field>
  8540. <name>COMP1_POLARITY</name>
  8541. <description>Comparator 1 polarity selection
  8542. bit</description>
  8543. <bitOffset>15</bitOffset>
  8544. <bitWidth>1</bitWidth>
  8545. <access>read-write</access>
  8546. </field>
  8547. <field>
  8548. <name>COMP1_VALUE</name>
  8549. <description>Comparator 1 output status
  8550. bit</description>
  8551. <bitOffset>30</bitOffset>
  8552. <bitWidth>1</bitWidth>
  8553. <access>read-only</access>
  8554. </field>
  8555. <field>
  8556. <name>COMP1_LOCK</name>
  8557. <description>COMP1_CSR register lock
  8558. bit</description>
  8559. <bitOffset>31</bitOffset>
  8560. <bitWidth>1</bitWidth>
  8561. <access>write-only</access>
  8562. </field>
  8563. </fields>
  8564. </register>
  8565. <register>
  8566. <name>COMP2_CSR</name>
  8567. <displayName>COMP2_CSR</displayName>
  8568. <description>Comparator 2 control and status
  8569. register</description>
  8570. <addressOffset>0x1C</addressOffset>
  8571. <size>0x20</size>
  8572. <resetValue>0x0</resetValue>
  8573. <fields>
  8574. <field>
  8575. <name>COMP2_LOCK</name>
  8576. <description>COMP2_CSR register lock
  8577. bit</description>
  8578. <bitOffset>31</bitOffset>
  8579. <bitWidth>1</bitWidth>
  8580. <access>write-only</access>
  8581. </field>
  8582. <field>
  8583. <name>COMP2_VALUE</name>
  8584. <description>Comparator 2 output status
  8585. bit</description>
  8586. <bitOffset>30</bitOffset>
  8587. <bitWidth>1</bitWidth>
  8588. <access>read-only</access>
  8589. </field>
  8590. <field>
  8591. <name>COMP2_POLARITY</name>
  8592. <description>Comparator 2 polarity selection
  8593. bit</description>
  8594. <bitOffset>15</bitOffset>
  8595. <bitWidth>1</bitWidth>
  8596. <access>read-write</access>
  8597. </field>
  8598. <field>
  8599. <name>COMP2_INP_SEL</name>
  8600. <description>Comparator 2 Input Plus connection
  8601. configuration bit</description>
  8602. <bitOffset>8</bitOffset>
  8603. <bitWidth>3</bitWidth>
  8604. <access>read-write</access>
  8605. </field>
  8606. <field>
  8607. <name>COMP2_INN_SEL</name>
  8608. <description>Comparator 2 Input Minus connection
  8609. configuration bit</description>
  8610. <bitOffset>4</bitOffset>
  8611. <bitWidth>3</bitWidth>
  8612. <access>read-write</access>
  8613. </field>
  8614. <field>
  8615. <name>COMP2_SPEED</name>
  8616. <description>Comparator 2 power mode selection
  8617. bit</description>
  8618. <bitOffset>3</bitOffset>
  8619. <bitWidth>1</bitWidth>
  8620. <access>read-write</access>
  8621. </field>
  8622. <field>
  8623. <name>COMP2_EN</name>
  8624. <description>Comparator 2 enable bit</description>
  8625. <bitOffset>0</bitOffset>
  8626. <bitWidth>1</bitWidth>
  8627. <access>read-write</access>
  8628. </field>
  8629. <field>
  8630. <name>COMP2_OUT_SEL</name>
  8631. <description>COMP2 output select</description>
  8632. <bitOffset>12</bitOffset>
  8633. <bitWidth>3</bitWidth>
  8634. <access>read-write</access>
  8635. </field>
  8636. </fields>
  8637. </register>
  8638. </registers>
  8639. </peripheral>
  8640. <peripheral>
  8641. <name>USB_FS</name>
  8642. <description>Universal serial bus full-speed device
  8643. interface</description>
  8644. <groupName>USB</groupName>
  8645. <baseAddress>0x40005C00</baseAddress>
  8646. <addressBlock>
  8647. <offset>0x0</offset>
  8648. <size>0x400</size>
  8649. <usage>registers</usage>
  8650. </addressBlock>
  8651. <interrupt>
  8652. <name>USB</name>
  8653. <description>USB event interrupt through
  8654. EXTI18</description>
  8655. <value>31</value>
  8656. </interrupt>
  8657. <registers>
  8658. <register>
  8659. <name>EP0R</name>
  8660. <displayName>EP0R</displayName>
  8661. <description>endpoint register</description>
  8662. <addressOffset>0x0</addressOffset>
  8663. <size>0x20</size>
  8664. <access>read-write</access>
  8665. <resetValue>0x0</resetValue>
  8666. <fields>
  8667. <field>
  8668. <name>CTR_RX</name>
  8669. <description>CTR_RX</description>
  8670. <bitOffset>15</bitOffset>
  8671. <bitWidth>1</bitWidth>
  8672. </field>
  8673. <field>
  8674. <name>DTOG_RX</name>
  8675. <description>DTOG_RX</description>
  8676. <bitOffset>14</bitOffset>
  8677. <bitWidth>1</bitWidth>
  8678. </field>
  8679. <field>
  8680. <name>STAT_RX</name>
  8681. <description>STAT_RX</description>
  8682. <bitOffset>12</bitOffset>
  8683. <bitWidth>2</bitWidth>
  8684. </field>
  8685. <field>
  8686. <name>SETUP</name>
  8687. <description>SETUP</description>
  8688. <bitOffset>11</bitOffset>
  8689. <bitWidth>1</bitWidth>
  8690. </field>
  8691. <field>
  8692. <name>EPTYPE</name>
  8693. <description>EPTYPE</description>
  8694. <bitOffset>9</bitOffset>
  8695. <bitWidth>2</bitWidth>
  8696. </field>
  8697. <field>
  8698. <name>EP_KIND</name>
  8699. <description>EP_KIND</description>
  8700. <bitOffset>8</bitOffset>
  8701. <bitWidth>1</bitWidth>
  8702. </field>
  8703. <field>
  8704. <name>CTR_TX</name>
  8705. <description>CTR_TX</description>
  8706. <bitOffset>7</bitOffset>
  8707. <bitWidth>1</bitWidth>
  8708. </field>
  8709. <field>
  8710. <name>DTOG_TX</name>
  8711. <description>DTOG_TX</description>
  8712. <bitOffset>6</bitOffset>
  8713. <bitWidth>1</bitWidth>
  8714. </field>
  8715. <field>
  8716. <name>STAT_TX</name>
  8717. <description>STAT_TX</description>
  8718. <bitOffset>4</bitOffset>
  8719. <bitWidth>2</bitWidth>
  8720. </field>
  8721. <field>
  8722. <name>EA</name>
  8723. <description>EA</description>
  8724. <bitOffset>0</bitOffset>
  8725. <bitWidth>4</bitWidth>
  8726. </field>
  8727. </fields>
  8728. </register>
  8729. <register>
  8730. <name>EP1R</name>
  8731. <displayName>EP1R</displayName>
  8732. <description>endpoint register</description>
  8733. <addressOffset>0x4</addressOffset>
  8734. <size>0x20</size>
  8735. <access>read-write</access>
  8736. <resetValue>0x0</resetValue>
  8737. <fields>
  8738. <field>
  8739. <name>CTR_RX</name>
  8740. <description>CTR_RX</description>
  8741. <bitOffset>15</bitOffset>
  8742. <bitWidth>1</bitWidth>
  8743. </field>
  8744. <field>
  8745. <name>DTOG_RX</name>
  8746. <description>DTOG_RX</description>
  8747. <bitOffset>14</bitOffset>
  8748. <bitWidth>1</bitWidth>
  8749. </field>
  8750. <field>
  8751. <name>STAT_RX</name>
  8752. <description>STAT_RX</description>
  8753. <bitOffset>12</bitOffset>
  8754. <bitWidth>2</bitWidth>
  8755. </field>
  8756. <field>
  8757. <name>SETUP</name>
  8758. <description>SETUP</description>
  8759. <bitOffset>11</bitOffset>
  8760. <bitWidth>1</bitWidth>
  8761. </field>
  8762. <field>
  8763. <name>EPTYPE</name>
  8764. <description>EPTYPE</description>
  8765. <bitOffset>9</bitOffset>
  8766. <bitWidth>2</bitWidth>
  8767. </field>
  8768. <field>
  8769. <name>EP_KIND</name>
  8770. <description>EP_KIND</description>
  8771. <bitOffset>8</bitOffset>
  8772. <bitWidth>1</bitWidth>
  8773. </field>
  8774. <field>
  8775. <name>CTR_TX</name>
  8776. <description>CTR_TX</description>
  8777. <bitOffset>7</bitOffset>
  8778. <bitWidth>1</bitWidth>
  8779. </field>
  8780. <field>
  8781. <name>DTOG_TX</name>
  8782. <description>DTOG_TX</description>
  8783. <bitOffset>6</bitOffset>
  8784. <bitWidth>1</bitWidth>
  8785. </field>
  8786. <field>
  8787. <name>STAT_TX</name>
  8788. <description>STAT_TX</description>
  8789. <bitOffset>4</bitOffset>
  8790. <bitWidth>2</bitWidth>
  8791. </field>
  8792. <field>
  8793. <name>EA</name>
  8794. <description>EA</description>
  8795. <bitOffset>0</bitOffset>
  8796. <bitWidth>4</bitWidth>
  8797. </field>
  8798. </fields>
  8799. </register>
  8800. <register>
  8801. <name>EP2R</name>
  8802. <displayName>EP2R</displayName>
  8803. <description>endpoint register</description>
  8804. <addressOffset>0x8</addressOffset>
  8805. <size>0x20</size>
  8806. <access>read-write</access>
  8807. <resetValue>0x0</resetValue>
  8808. <fields>
  8809. <field>
  8810. <name>CTR_RX</name>
  8811. <description>CTR_RX</description>
  8812. <bitOffset>15</bitOffset>
  8813. <bitWidth>1</bitWidth>
  8814. </field>
  8815. <field>
  8816. <name>DTOG_RX</name>
  8817. <description>DTOG_RX</description>
  8818. <bitOffset>14</bitOffset>
  8819. <bitWidth>1</bitWidth>
  8820. </field>
  8821. <field>
  8822. <name>STAT_RX</name>
  8823. <description>STAT_RX</description>
  8824. <bitOffset>12</bitOffset>
  8825. <bitWidth>2</bitWidth>
  8826. </field>
  8827. <field>
  8828. <name>SETUP</name>
  8829. <description>SETUP</description>
  8830. <bitOffset>11</bitOffset>
  8831. <bitWidth>1</bitWidth>
  8832. </field>
  8833. <field>
  8834. <name>EPTYPE</name>
  8835. <description>EPTYPE</description>
  8836. <bitOffset>9</bitOffset>
  8837. <bitWidth>2</bitWidth>
  8838. </field>
  8839. <field>
  8840. <name>EP_KIND</name>
  8841. <description>EP_KIND</description>
  8842. <bitOffset>8</bitOffset>
  8843. <bitWidth>1</bitWidth>
  8844. </field>
  8845. <field>
  8846. <name>CTR_TX</name>
  8847. <description>CTR_TX</description>
  8848. <bitOffset>7</bitOffset>
  8849. <bitWidth>1</bitWidth>
  8850. </field>
  8851. <field>
  8852. <name>DTOG_TX</name>
  8853. <description>DTOG_TX</description>
  8854. <bitOffset>6</bitOffset>
  8855. <bitWidth>1</bitWidth>
  8856. </field>
  8857. <field>
  8858. <name>STAT_TX</name>
  8859. <description>STAT_TX</description>
  8860. <bitOffset>4</bitOffset>
  8861. <bitWidth>2</bitWidth>
  8862. </field>
  8863. <field>
  8864. <name>EA</name>
  8865. <description>EA</description>
  8866. <bitOffset>0</bitOffset>
  8867. <bitWidth>4</bitWidth>
  8868. </field>
  8869. </fields>
  8870. </register>
  8871. <register>
  8872. <name>EP3R</name>
  8873. <displayName>EP3R</displayName>
  8874. <description>endpoint register</description>
  8875. <addressOffset>0xC</addressOffset>
  8876. <size>0x20</size>
  8877. <access>read-write</access>
  8878. <resetValue>0x0</resetValue>
  8879. <fields>
  8880. <field>
  8881. <name>CTR_RX</name>
  8882. <description>CTR_RX</description>
  8883. <bitOffset>15</bitOffset>
  8884. <bitWidth>1</bitWidth>
  8885. </field>
  8886. <field>
  8887. <name>DTOG_RX</name>
  8888. <description>DTOG_RX</description>
  8889. <bitOffset>14</bitOffset>
  8890. <bitWidth>1</bitWidth>
  8891. </field>
  8892. <field>
  8893. <name>STAT_RX</name>
  8894. <description>STAT_RX</description>
  8895. <bitOffset>12</bitOffset>
  8896. <bitWidth>2</bitWidth>
  8897. </field>
  8898. <field>
  8899. <name>SETUP</name>
  8900. <description>SETUP</description>
  8901. <bitOffset>11</bitOffset>
  8902. <bitWidth>1</bitWidth>
  8903. </field>
  8904. <field>
  8905. <name>EPTYPE</name>
  8906. <description>EPTYPE</description>
  8907. <bitOffset>9</bitOffset>
  8908. <bitWidth>2</bitWidth>
  8909. </field>
  8910. <field>
  8911. <name>EP_KIND</name>
  8912. <description>EP_KIND</description>
  8913. <bitOffset>8</bitOffset>
  8914. <bitWidth>1</bitWidth>
  8915. </field>
  8916. <field>
  8917. <name>CTR_TX</name>
  8918. <description>CTR_TX</description>
  8919. <bitOffset>7</bitOffset>
  8920. <bitWidth>1</bitWidth>
  8921. </field>
  8922. <field>
  8923. <name>DTOG_TX</name>
  8924. <description>DTOG_TX</description>
  8925. <bitOffset>6</bitOffset>
  8926. <bitWidth>1</bitWidth>
  8927. </field>
  8928. <field>
  8929. <name>STAT_TX</name>
  8930. <description>STAT_TX</description>
  8931. <bitOffset>4</bitOffset>
  8932. <bitWidth>2</bitWidth>
  8933. </field>
  8934. <field>
  8935. <name>EA</name>
  8936. <description>EA</description>
  8937. <bitOffset>0</bitOffset>
  8938. <bitWidth>4</bitWidth>
  8939. </field>
  8940. </fields>
  8941. </register>
  8942. <register>
  8943. <name>EP4R</name>
  8944. <displayName>EP4R</displayName>
  8945. <description>endpoint register</description>
  8946. <addressOffset>0x10</addressOffset>
  8947. <size>0x20</size>
  8948. <access>read-write</access>
  8949. <resetValue>0x0</resetValue>
  8950. <fields>
  8951. <field>
  8952. <name>CTR_RX</name>
  8953. <description>CTR_RX</description>
  8954. <bitOffset>15</bitOffset>
  8955. <bitWidth>1</bitWidth>
  8956. </field>
  8957. <field>
  8958. <name>DTOG_RX</name>
  8959. <description>DTOG_RX</description>
  8960. <bitOffset>14</bitOffset>
  8961. <bitWidth>1</bitWidth>
  8962. </field>
  8963. <field>
  8964. <name>STAT_RX</name>
  8965. <description>STAT_RX</description>
  8966. <bitOffset>12</bitOffset>
  8967. <bitWidth>2</bitWidth>
  8968. </field>
  8969. <field>
  8970. <name>SETUP</name>
  8971. <description>SETUP</description>
  8972. <bitOffset>11</bitOffset>
  8973. <bitWidth>1</bitWidth>
  8974. </field>
  8975. <field>
  8976. <name>EPTYPE</name>
  8977. <description>EPTYPE</description>
  8978. <bitOffset>9</bitOffset>
  8979. <bitWidth>2</bitWidth>
  8980. </field>
  8981. <field>
  8982. <name>EP_KIND</name>
  8983. <description>EP_KIND</description>
  8984. <bitOffset>8</bitOffset>
  8985. <bitWidth>1</bitWidth>
  8986. </field>
  8987. <field>
  8988. <name>CTR_TX</name>
  8989. <description>CTR_TX</description>
  8990. <bitOffset>7</bitOffset>
  8991. <bitWidth>1</bitWidth>
  8992. </field>
  8993. <field>
  8994. <name>DTOG_TX</name>
  8995. <description>DTOG_TX</description>
  8996. <bitOffset>6</bitOffset>
  8997. <bitWidth>1</bitWidth>
  8998. </field>
  8999. <field>
  9000. <name>STAT_TX</name>
  9001. <description>STAT_TX</description>
  9002. <bitOffset>4</bitOffset>
  9003. <bitWidth>2</bitWidth>
  9004. </field>
  9005. <field>
  9006. <name>EA</name>
  9007. <description>EA</description>
  9008. <bitOffset>0</bitOffset>
  9009. <bitWidth>4</bitWidth>
  9010. </field>
  9011. </fields>
  9012. </register>
  9013. <register>
  9014. <name>EP5R</name>
  9015. <displayName>EP5R</displayName>
  9016. <description>endpoint register</description>
  9017. <addressOffset>0x14</addressOffset>
  9018. <size>0x20</size>
  9019. <access>read-write</access>
  9020. <resetValue>0x0</resetValue>
  9021. <fields>
  9022. <field>
  9023. <name>CTR_RX</name>
  9024. <description>CTR_RX</description>
  9025. <bitOffset>15</bitOffset>
  9026. <bitWidth>1</bitWidth>
  9027. </field>
  9028. <field>
  9029. <name>DTOG_RX</name>
  9030. <description>DTOG_RX</description>
  9031. <bitOffset>14</bitOffset>
  9032. <bitWidth>1</bitWidth>
  9033. </field>
  9034. <field>
  9035. <name>STAT_RX</name>
  9036. <description>STAT_RX</description>
  9037. <bitOffset>12</bitOffset>
  9038. <bitWidth>2</bitWidth>
  9039. </field>
  9040. <field>
  9041. <name>SETUP</name>
  9042. <description>SETUP</description>
  9043. <bitOffset>11</bitOffset>
  9044. <bitWidth>1</bitWidth>
  9045. </field>
  9046. <field>
  9047. <name>EPTYPE</name>
  9048. <description>EPTYPE</description>
  9049. <bitOffset>9</bitOffset>
  9050. <bitWidth>2</bitWidth>
  9051. </field>
  9052. <field>
  9053. <name>EP_KIND</name>
  9054. <description>EP_KIND</description>
  9055. <bitOffset>8</bitOffset>
  9056. <bitWidth>1</bitWidth>
  9057. </field>
  9058. <field>
  9059. <name>CTR_TX</name>
  9060. <description>CTR_TX</description>
  9061. <bitOffset>7</bitOffset>
  9062. <bitWidth>1</bitWidth>
  9063. </field>
  9064. <field>
  9065. <name>DTOG_TX</name>
  9066. <description>DTOG_TX</description>
  9067. <bitOffset>6</bitOffset>
  9068. <bitWidth>1</bitWidth>
  9069. </field>
  9070. <field>
  9071. <name>STAT_TX</name>
  9072. <description>STAT_TX</description>
  9073. <bitOffset>4</bitOffset>
  9074. <bitWidth>2</bitWidth>
  9075. </field>
  9076. <field>
  9077. <name>EA</name>
  9078. <description>EA</description>
  9079. <bitOffset>0</bitOffset>
  9080. <bitWidth>4</bitWidth>
  9081. </field>
  9082. </fields>
  9083. </register>
  9084. <register>
  9085. <name>EP6R</name>
  9086. <displayName>EP6R</displayName>
  9087. <description>endpoint register</description>
  9088. <addressOffset>0x18</addressOffset>
  9089. <size>0x20</size>
  9090. <access>read-write</access>
  9091. <resetValue>0x0</resetValue>
  9092. <fields>
  9093. <field>
  9094. <name>CTR_RX</name>
  9095. <description>CTR_RX</description>
  9096. <bitOffset>15</bitOffset>
  9097. <bitWidth>1</bitWidth>
  9098. </field>
  9099. <field>
  9100. <name>DTOG_RX</name>
  9101. <description>DTOG_RX</description>
  9102. <bitOffset>14</bitOffset>
  9103. <bitWidth>1</bitWidth>
  9104. </field>
  9105. <field>
  9106. <name>STAT_RX</name>
  9107. <description>STAT_RX</description>
  9108. <bitOffset>12</bitOffset>
  9109. <bitWidth>2</bitWidth>
  9110. </field>
  9111. <field>
  9112. <name>SETUP</name>
  9113. <description>SETUP</description>
  9114. <bitOffset>11</bitOffset>
  9115. <bitWidth>1</bitWidth>
  9116. </field>
  9117. <field>
  9118. <name>EPTYPE</name>
  9119. <description>EPTYPE</description>
  9120. <bitOffset>9</bitOffset>
  9121. <bitWidth>2</bitWidth>
  9122. </field>
  9123. <field>
  9124. <name>EP_KIND</name>
  9125. <description>EP_KIND</description>
  9126. <bitOffset>8</bitOffset>
  9127. <bitWidth>1</bitWidth>
  9128. </field>
  9129. <field>
  9130. <name>CTR_TX</name>
  9131. <description>CTR_TX</description>
  9132. <bitOffset>7</bitOffset>
  9133. <bitWidth>1</bitWidth>
  9134. </field>
  9135. <field>
  9136. <name>DTOG_TX</name>
  9137. <description>DTOG_TX</description>
  9138. <bitOffset>6</bitOffset>
  9139. <bitWidth>1</bitWidth>
  9140. </field>
  9141. <field>
  9142. <name>STAT_TX</name>
  9143. <description>STAT_TX</description>
  9144. <bitOffset>4</bitOffset>
  9145. <bitWidth>2</bitWidth>
  9146. </field>
  9147. <field>
  9148. <name>EA</name>
  9149. <description>EA</description>
  9150. <bitOffset>0</bitOffset>
  9151. <bitWidth>4</bitWidth>
  9152. </field>
  9153. </fields>
  9154. </register>
  9155. <register>
  9156. <name>EP7R</name>
  9157. <displayName>EP7R</displayName>
  9158. <description>endpoint register</description>
  9159. <addressOffset>0x1C</addressOffset>
  9160. <size>0x20</size>
  9161. <access>read-write</access>
  9162. <resetValue>0x0</resetValue>
  9163. <fields>
  9164. <field>
  9165. <name>CTR_RX</name>
  9166. <description>CTR_RX</description>
  9167. <bitOffset>15</bitOffset>
  9168. <bitWidth>1</bitWidth>
  9169. </field>
  9170. <field>
  9171. <name>DTOG_RX</name>
  9172. <description>DTOG_RX</description>
  9173. <bitOffset>14</bitOffset>
  9174. <bitWidth>1</bitWidth>
  9175. </field>
  9176. <field>
  9177. <name>STAT_RX</name>
  9178. <description>STAT_RX</description>
  9179. <bitOffset>12</bitOffset>
  9180. <bitWidth>2</bitWidth>
  9181. </field>
  9182. <field>
  9183. <name>SETUP</name>
  9184. <description>SETUP</description>
  9185. <bitOffset>11</bitOffset>
  9186. <bitWidth>1</bitWidth>
  9187. </field>
  9188. <field>
  9189. <name>EPTYPE</name>
  9190. <description>EPTYPE</description>
  9191. <bitOffset>9</bitOffset>
  9192. <bitWidth>2</bitWidth>
  9193. </field>
  9194. <field>
  9195. <name>EP_KIND</name>
  9196. <description>EP_KIND</description>
  9197. <bitOffset>8</bitOffset>
  9198. <bitWidth>1</bitWidth>
  9199. </field>
  9200. <field>
  9201. <name>CTR_TX</name>
  9202. <description>CTR_TX</description>
  9203. <bitOffset>7</bitOffset>
  9204. <bitWidth>1</bitWidth>
  9205. </field>
  9206. <field>
  9207. <name>DTOG_TX</name>
  9208. <description>DTOG_TX</description>
  9209. <bitOffset>6</bitOffset>
  9210. <bitWidth>1</bitWidth>
  9211. </field>
  9212. <field>
  9213. <name>STAT_TX</name>
  9214. <description>STAT_TX</description>
  9215. <bitOffset>4</bitOffset>
  9216. <bitWidth>2</bitWidth>
  9217. </field>
  9218. <field>
  9219. <name>EA</name>
  9220. <description>EA</description>
  9221. <bitOffset>0</bitOffset>
  9222. <bitWidth>4</bitWidth>
  9223. </field>
  9224. </fields>
  9225. </register>
  9226. <register>
  9227. <name>CNTR</name>
  9228. <displayName>CNTR</displayName>
  9229. <description>control register</description>
  9230. <addressOffset>0x40</addressOffset>
  9231. <size>0x20</size>
  9232. <access>read-write</access>
  9233. <resetValue>0x0</resetValue>
  9234. <fields>
  9235. <field>
  9236. <name>CTRM</name>
  9237. <description>CTRM</description>
  9238. <bitOffset>15</bitOffset>
  9239. <bitWidth>1</bitWidth>
  9240. </field>
  9241. <field>
  9242. <name>PMAOVRM</name>
  9243. <description>PMAOVRM</description>
  9244. <bitOffset>14</bitOffset>
  9245. <bitWidth>1</bitWidth>
  9246. </field>
  9247. <field>
  9248. <name>ERRM</name>
  9249. <description>ERRM</description>
  9250. <bitOffset>13</bitOffset>
  9251. <bitWidth>1</bitWidth>
  9252. </field>
  9253. <field>
  9254. <name>WKUPM</name>
  9255. <description>WKUPM</description>
  9256. <bitOffset>12</bitOffset>
  9257. <bitWidth>1</bitWidth>
  9258. </field>
  9259. <field>
  9260. <name>SUSPM</name>
  9261. <description>SUSPM</description>
  9262. <bitOffset>11</bitOffset>
  9263. <bitWidth>1</bitWidth>
  9264. </field>
  9265. <field>
  9266. <name>RESETM</name>
  9267. <description>RESETM</description>
  9268. <bitOffset>10</bitOffset>
  9269. <bitWidth>1</bitWidth>
  9270. </field>
  9271. <field>
  9272. <name>SOFM</name>
  9273. <description>SOFM</description>
  9274. <bitOffset>9</bitOffset>
  9275. <bitWidth>1</bitWidth>
  9276. </field>
  9277. <field>
  9278. <name>ESOFM</name>
  9279. <description>ESOFM</description>
  9280. <bitOffset>8</bitOffset>
  9281. <bitWidth>1</bitWidth>
  9282. </field>
  9283. <field>
  9284. <name>L1REQM</name>
  9285. <description>L1REQM</description>
  9286. <bitOffset>7</bitOffset>
  9287. <bitWidth>1</bitWidth>
  9288. </field>
  9289. <field>
  9290. <name>L1RESUME</name>
  9291. <description>L1RESUME</description>
  9292. <bitOffset>5</bitOffset>
  9293. <bitWidth>1</bitWidth>
  9294. </field>
  9295. <field>
  9296. <name>RESUME</name>
  9297. <description>RESUME</description>
  9298. <bitOffset>4</bitOffset>
  9299. <bitWidth>1</bitWidth>
  9300. </field>
  9301. <field>
  9302. <name>FSUSP</name>
  9303. <description>FSUSP</description>
  9304. <bitOffset>3</bitOffset>
  9305. <bitWidth>1</bitWidth>
  9306. </field>
  9307. <field>
  9308. <name>LPMODE</name>
  9309. <description>LPMODE</description>
  9310. <bitOffset>2</bitOffset>
  9311. <bitWidth>1</bitWidth>
  9312. </field>
  9313. <field>
  9314. <name>PDWN</name>
  9315. <description>PDWN</description>
  9316. <bitOffset>1</bitOffset>
  9317. <bitWidth>1</bitWidth>
  9318. </field>
  9319. <field>
  9320. <name>FRES</name>
  9321. <description>FRES</description>
  9322. <bitOffset>0</bitOffset>
  9323. <bitWidth>1</bitWidth>
  9324. </field>
  9325. </fields>
  9326. </register>
  9327. <register>
  9328. <name>ISTR</name>
  9329. <displayName>ISTR</displayName>
  9330. <description>interrupt status register</description>
  9331. <addressOffset>0x44</addressOffset>
  9332. <size>0x20</size>
  9333. <access>read-write</access>
  9334. <resetValue>0x0</resetValue>
  9335. <fields>
  9336. <field>
  9337. <name>CTR</name>
  9338. <description>CTR</description>
  9339. <bitOffset>15</bitOffset>
  9340. <bitWidth>1</bitWidth>
  9341. </field>
  9342. <field>
  9343. <name>PMAOVR</name>
  9344. <description>PMAOVR</description>
  9345. <bitOffset>14</bitOffset>
  9346. <bitWidth>1</bitWidth>
  9347. </field>
  9348. <field>
  9349. <name>ERR</name>
  9350. <description>ERR</description>
  9351. <bitOffset>13</bitOffset>
  9352. <bitWidth>1</bitWidth>
  9353. </field>
  9354. <field>
  9355. <name>WKUP</name>
  9356. <description>WKUP</description>
  9357. <bitOffset>12</bitOffset>
  9358. <bitWidth>1</bitWidth>
  9359. </field>
  9360. <field>
  9361. <name>SUSP</name>
  9362. <description>SUSP</description>
  9363. <bitOffset>11</bitOffset>
  9364. <bitWidth>1</bitWidth>
  9365. </field>
  9366. <field>
  9367. <name>RESET</name>
  9368. <description>RESET</description>
  9369. <bitOffset>10</bitOffset>
  9370. <bitWidth>1</bitWidth>
  9371. </field>
  9372. <field>
  9373. <name>SOF</name>
  9374. <description>SOF</description>
  9375. <bitOffset>9</bitOffset>
  9376. <bitWidth>1</bitWidth>
  9377. </field>
  9378. <field>
  9379. <name>ESOF</name>
  9380. <description>ESOF</description>
  9381. <bitOffset>8</bitOffset>
  9382. <bitWidth>1</bitWidth>
  9383. </field>
  9384. <field>
  9385. <name>L1REQ</name>
  9386. <description>L1REQ</description>
  9387. <bitOffset>7</bitOffset>
  9388. <bitWidth>1</bitWidth>
  9389. </field>
  9390. <field>
  9391. <name>DIR</name>
  9392. <description>DIR</description>
  9393. <bitOffset>4</bitOffset>
  9394. <bitWidth>1</bitWidth>
  9395. </field>
  9396. <field>
  9397. <name>EP_ID</name>
  9398. <description>EP_ID</description>
  9399. <bitOffset>0</bitOffset>
  9400. <bitWidth>4</bitWidth>
  9401. </field>
  9402. </fields>
  9403. </register>
  9404. <register>
  9405. <name>FNR</name>
  9406. <displayName>FNR</displayName>
  9407. <description>frame number register</description>
  9408. <addressOffset>0x48</addressOffset>
  9409. <size>0x20</size>
  9410. <access>read-only</access>
  9411. <resetValue>0x0</resetValue>
  9412. <fields>
  9413. <field>
  9414. <name>RXDP</name>
  9415. <description>RXDP</description>
  9416. <bitOffset>15</bitOffset>
  9417. <bitWidth>1</bitWidth>
  9418. </field>
  9419. <field>
  9420. <name>RXDM</name>
  9421. <description>RXDM</description>
  9422. <bitOffset>14</bitOffset>
  9423. <bitWidth>1</bitWidth>
  9424. </field>
  9425. <field>
  9426. <name>LCK</name>
  9427. <description>LCK</description>
  9428. <bitOffset>13</bitOffset>
  9429. <bitWidth>1</bitWidth>
  9430. </field>
  9431. <field>
  9432. <name>LSOF</name>
  9433. <description>LSOF</description>
  9434. <bitOffset>11</bitOffset>
  9435. <bitWidth>2</bitWidth>
  9436. </field>
  9437. <field>
  9438. <name>FN</name>
  9439. <description>FN</description>
  9440. <bitOffset>0</bitOffset>
  9441. <bitWidth>11</bitWidth>
  9442. </field>
  9443. </fields>
  9444. </register>
  9445. <register>
  9446. <name>DADDR</name>
  9447. <displayName>DADDR</displayName>
  9448. <description>device address</description>
  9449. <addressOffset>0x4C</addressOffset>
  9450. <size>0x20</size>
  9451. <access>read-write</access>
  9452. <resetValue>0x0</resetValue>
  9453. <fields>
  9454. <field>
  9455. <name>EF</name>
  9456. <description>EF</description>
  9457. <bitOffset>7</bitOffset>
  9458. <bitWidth>1</bitWidth>
  9459. </field>
  9460. <field>
  9461. <name>ADD</name>
  9462. <description>ADD</description>
  9463. <bitOffset>0</bitOffset>
  9464. <bitWidth>7</bitWidth>
  9465. </field>
  9466. </fields>
  9467. </register>
  9468. <register>
  9469. <name>BTABLE</name>
  9470. <displayName>BTABLE</displayName>
  9471. <description>Buffer table address</description>
  9472. <addressOffset>0x50</addressOffset>
  9473. <size>0x20</size>
  9474. <access>read-write</access>
  9475. <resetValue>0x0</resetValue>
  9476. <fields>
  9477. <field>
  9478. <name>BTABLE</name>
  9479. <description>BTABLE</description>
  9480. <bitOffset>3</bitOffset>
  9481. <bitWidth>13</bitWidth>
  9482. </field>
  9483. </fields>
  9484. </register>
  9485. <register>
  9486. <name>LPMCSR</name>
  9487. <displayName>LPMCSR</displayName>
  9488. <description>LPM control and status
  9489. register</description>
  9490. <addressOffset>0x54</addressOffset>
  9491. <size>0x20</size>
  9492. <resetValue>0x0</resetValue>
  9493. <fields>
  9494. <field>
  9495. <name>BESL</name>
  9496. <description>BESL</description>
  9497. <bitOffset>4</bitOffset>
  9498. <bitWidth>4</bitWidth>
  9499. <access>read-only</access>
  9500. </field>
  9501. <field>
  9502. <name>REMWAKE</name>
  9503. <description>REMWAKE</description>
  9504. <bitOffset>3</bitOffset>
  9505. <bitWidth>1</bitWidth>
  9506. <access>read-only</access>
  9507. </field>
  9508. <field>
  9509. <name>LPMACK</name>
  9510. <description>LPMACK</description>
  9511. <bitOffset>1</bitOffset>
  9512. <bitWidth>1</bitWidth>
  9513. <access>read-write</access>
  9514. </field>
  9515. <field>
  9516. <name>LPMEN</name>
  9517. <description>LPMEN</description>
  9518. <bitOffset>0</bitOffset>
  9519. <bitWidth>1</bitWidth>
  9520. <access>read-write</access>
  9521. </field>
  9522. </fields>
  9523. </register>
  9524. <register>
  9525. <name>BCDR</name>
  9526. <displayName>BCDR</displayName>
  9527. <description>Battery charging detector</description>
  9528. <addressOffset>0x58</addressOffset>
  9529. <size>0x20</size>
  9530. <resetValue>0x0</resetValue>
  9531. <fields>
  9532. <field>
  9533. <name>DPPU</name>
  9534. <description>DPPU</description>
  9535. <bitOffset>15</bitOffset>
  9536. <bitWidth>1</bitWidth>
  9537. <access>read-write</access>
  9538. </field>
  9539. <field>
  9540. <name>PS2DET</name>
  9541. <description>PS2DET</description>
  9542. <bitOffset>7</bitOffset>
  9543. <bitWidth>1</bitWidth>
  9544. <access>read-only</access>
  9545. </field>
  9546. <field>
  9547. <name>SDET</name>
  9548. <description>SDET</description>
  9549. <bitOffset>6</bitOffset>
  9550. <bitWidth>1</bitWidth>
  9551. <access>read-only</access>
  9552. </field>
  9553. <field>
  9554. <name>PDET</name>
  9555. <description>PDET</description>
  9556. <bitOffset>5</bitOffset>
  9557. <bitWidth>1</bitWidth>
  9558. <access>read-only</access>
  9559. </field>
  9560. <field>
  9561. <name>DCDET</name>
  9562. <description>DCDET</description>
  9563. <bitOffset>4</bitOffset>
  9564. <bitWidth>1</bitWidth>
  9565. <access>read-only</access>
  9566. </field>
  9567. <field>
  9568. <name>SDEN</name>
  9569. <description>SDEN</description>
  9570. <bitOffset>3</bitOffset>
  9571. <bitWidth>1</bitWidth>
  9572. <access>read-write</access>
  9573. </field>
  9574. <field>
  9575. <name>PDEN</name>
  9576. <description>PDEN</description>
  9577. <bitOffset>2</bitOffset>
  9578. <bitWidth>1</bitWidth>
  9579. <access>read-write</access>
  9580. </field>
  9581. <field>
  9582. <name>DCDEN</name>
  9583. <description>DCDEN</description>
  9584. <bitOffset>1</bitOffset>
  9585. <bitWidth>1</bitWidth>
  9586. <access>read-write</access>
  9587. </field>
  9588. <field>
  9589. <name>BCDEN</name>
  9590. <description>BCDEN</description>
  9591. <bitOffset>0</bitOffset>
  9592. <bitWidth>1</bitWidth>
  9593. <access>read-write</access>
  9594. </field>
  9595. </fields>
  9596. </register>
  9597. </registers>
  9598. </peripheral>
  9599. <peripheral>
  9600. <name>CRS</name>
  9601. <description>Clock recovery system</description>
  9602. <groupName>CRS</groupName>
  9603. <baseAddress>0x40006C00</baseAddress>
  9604. <addressBlock>
  9605. <offset>0x0</offset>
  9606. <size>0x400</size>
  9607. <usage>registers</usage>
  9608. </addressBlock>
  9609. <registers>
  9610. <register>
  9611. <name>CR</name>
  9612. <displayName>CR</displayName>
  9613. <description>control register</description>
  9614. <addressOffset>0x0</addressOffset>
  9615. <size>0x20</size>
  9616. <access>read-write</access>
  9617. <resetValue>0x00002000</resetValue>
  9618. <fields>
  9619. <field>
  9620. <name>TRIM</name>
  9621. <description>HSI48 oscillator smooth
  9622. trimming</description>
  9623. <bitOffset>8</bitOffset>
  9624. <bitWidth>6</bitWidth>
  9625. </field>
  9626. <field>
  9627. <name>SWSYNC</name>
  9628. <description>Generate software SYNC
  9629. event</description>
  9630. <bitOffset>7</bitOffset>
  9631. <bitWidth>1</bitWidth>
  9632. </field>
  9633. <field>
  9634. <name>AUTOTRIMEN</name>
  9635. <description>Automatic trimming enable</description>
  9636. <bitOffset>6</bitOffset>
  9637. <bitWidth>1</bitWidth>
  9638. </field>
  9639. <field>
  9640. <name>CEN</name>
  9641. <description>Frequency error counter
  9642. enable</description>
  9643. <bitOffset>5</bitOffset>
  9644. <bitWidth>1</bitWidth>
  9645. </field>
  9646. <field>
  9647. <name>ESYNCIE</name>
  9648. <description>Expected SYNC interrupt
  9649. enable</description>
  9650. <bitOffset>3</bitOffset>
  9651. <bitWidth>1</bitWidth>
  9652. </field>
  9653. <field>
  9654. <name>ERRIE</name>
  9655. <description>Synchronization or trimming error
  9656. interrupt enable</description>
  9657. <bitOffset>2</bitOffset>
  9658. <bitWidth>1</bitWidth>
  9659. </field>
  9660. <field>
  9661. <name>SYNCWARNIE</name>
  9662. <description>SYNC warning interrupt
  9663. enable</description>
  9664. <bitOffset>1</bitOffset>
  9665. <bitWidth>1</bitWidth>
  9666. </field>
  9667. <field>
  9668. <name>SYNCOKIE</name>
  9669. <description>SYNC event OK interrupt
  9670. enable</description>
  9671. <bitOffset>0</bitOffset>
  9672. <bitWidth>1</bitWidth>
  9673. </field>
  9674. </fields>
  9675. </register>
  9676. <register>
  9677. <name>CFGR</name>
  9678. <displayName>CFGR</displayName>
  9679. <description>configuration register</description>
  9680. <addressOffset>0x4</addressOffset>
  9681. <size>0x20</size>
  9682. <access>read-write</access>
  9683. <resetValue>0x2022BB7F</resetValue>
  9684. <fields>
  9685. <field>
  9686. <name>SYNCPOL</name>
  9687. <description>SYNC polarity selection</description>
  9688. <bitOffset>31</bitOffset>
  9689. <bitWidth>1</bitWidth>
  9690. </field>
  9691. <field>
  9692. <name>SYNCSRC</name>
  9693. <description>SYNC signal source
  9694. selection</description>
  9695. <bitOffset>28</bitOffset>
  9696. <bitWidth>2</bitWidth>
  9697. </field>
  9698. <field>
  9699. <name>SYNCDIV</name>
  9700. <description>SYNC divider</description>
  9701. <bitOffset>24</bitOffset>
  9702. <bitWidth>3</bitWidth>
  9703. </field>
  9704. <field>
  9705. <name>FELIM</name>
  9706. <description>Frequency error limit</description>
  9707. <bitOffset>16</bitOffset>
  9708. <bitWidth>8</bitWidth>
  9709. </field>
  9710. <field>
  9711. <name>RELOAD</name>
  9712. <description>Counter reload value</description>
  9713. <bitOffset>0</bitOffset>
  9714. <bitWidth>16</bitWidth>
  9715. </field>
  9716. </fields>
  9717. </register>
  9718. <register>
  9719. <name>ISR</name>
  9720. <displayName>ISR</displayName>
  9721. <description>interrupt and status register</description>
  9722. <addressOffset>0x8</addressOffset>
  9723. <size>0x20</size>
  9724. <access>read-only</access>
  9725. <resetValue>0x00000000</resetValue>
  9726. <fields>
  9727. <field>
  9728. <name>FECAP</name>
  9729. <description>Frequency error capture</description>
  9730. <bitOffset>16</bitOffset>
  9731. <bitWidth>16</bitWidth>
  9732. </field>
  9733. <field>
  9734. <name>FEDIR</name>
  9735. <description>Frequency error direction</description>
  9736. <bitOffset>15</bitOffset>
  9737. <bitWidth>1</bitWidth>
  9738. </field>
  9739. <field>
  9740. <name>TRIMOVF</name>
  9741. <description>Trimming overflow or
  9742. underflow</description>
  9743. <bitOffset>10</bitOffset>
  9744. <bitWidth>1</bitWidth>
  9745. </field>
  9746. <field>
  9747. <name>SYNCMISS</name>
  9748. <description>SYNC missed</description>
  9749. <bitOffset>9</bitOffset>
  9750. <bitWidth>1</bitWidth>
  9751. </field>
  9752. <field>
  9753. <name>SYNCERR</name>
  9754. <description>SYNC error</description>
  9755. <bitOffset>8</bitOffset>
  9756. <bitWidth>1</bitWidth>
  9757. </field>
  9758. <field>
  9759. <name>ESYNCF</name>
  9760. <description>Expected SYNC flag</description>
  9761. <bitOffset>3</bitOffset>
  9762. <bitWidth>1</bitWidth>
  9763. </field>
  9764. <field>
  9765. <name>ERRF</name>
  9766. <description>Error flag</description>
  9767. <bitOffset>2</bitOffset>
  9768. <bitWidth>1</bitWidth>
  9769. </field>
  9770. <field>
  9771. <name>SYNCWARNF</name>
  9772. <description>SYNC warning flag</description>
  9773. <bitOffset>1</bitOffset>
  9774. <bitWidth>1</bitWidth>
  9775. </field>
  9776. <field>
  9777. <name>SYNCOKF</name>
  9778. <description>SYNC event OK flag</description>
  9779. <bitOffset>0</bitOffset>
  9780. <bitWidth>1</bitWidth>
  9781. </field>
  9782. </fields>
  9783. </register>
  9784. <register>
  9785. <name>ICR</name>
  9786. <displayName>ICR</displayName>
  9787. <description>interrupt flag clear register</description>
  9788. <addressOffset>0xC</addressOffset>
  9789. <size>0x20</size>
  9790. <access>read-write</access>
  9791. <resetValue>0x00000000</resetValue>
  9792. <fields>
  9793. <field>
  9794. <name>ESYNCC</name>
  9795. <description>Expected SYNC clear flag</description>
  9796. <bitOffset>3</bitOffset>
  9797. <bitWidth>1</bitWidth>
  9798. </field>
  9799. <field>
  9800. <name>ERRC</name>
  9801. <description>Error clear flag</description>
  9802. <bitOffset>2</bitOffset>
  9803. <bitWidth>1</bitWidth>
  9804. </field>
  9805. <field>
  9806. <name>SYNCWARNC</name>
  9807. <description>SYNC warning clear flag</description>
  9808. <bitOffset>1</bitOffset>
  9809. <bitWidth>1</bitWidth>
  9810. </field>
  9811. <field>
  9812. <name>SYNCOKC</name>
  9813. <description>SYNC event OK clear flag</description>
  9814. <bitOffset>0</bitOffset>
  9815. <bitWidth>1</bitWidth>
  9816. </field>
  9817. </fields>
  9818. </register>
  9819. </registers>
  9820. </peripheral>
  9821. <peripheral>
  9822. <name>Firewall</name>
  9823. <description>Firewall</description>
  9824. <groupName>Firewall</groupName>
  9825. <baseAddress>0x40011C00</baseAddress>
  9826. <addressBlock>
  9827. <offset>0x0</offset>
  9828. <size>0x400</size>
  9829. <usage>registers</usage>
  9830. </addressBlock>
  9831. <registers>
  9832. <register>
  9833. <name>FIREWALL_CSSA</name>
  9834. <displayName>FIREWALL_CSSA</displayName>
  9835. <description>Code segment start address</description>
  9836. <addressOffset>0x0</addressOffset>
  9837. <size>0x20</size>
  9838. <access>read-write</access>
  9839. <resetValue>0x00000000</resetValue>
  9840. <fields>
  9841. <field>
  9842. <name>ADD</name>
  9843. <description>code segment start address</description>
  9844. <bitOffset>8</bitOffset>
  9845. <bitWidth>16</bitWidth>
  9846. </field>
  9847. </fields>
  9848. </register>
  9849. <register>
  9850. <name>FIREWALL_CSL</name>
  9851. <displayName>FIREWALL_CSL</displayName>
  9852. <description>Code segment length</description>
  9853. <addressOffset>0x4</addressOffset>
  9854. <size>0x20</size>
  9855. <access>read-write</access>
  9856. <resetValue>0x00000000</resetValue>
  9857. <fields>
  9858. <field>
  9859. <name>LENG</name>
  9860. <description>code segment length</description>
  9861. <bitOffset>8</bitOffset>
  9862. <bitWidth>14</bitWidth>
  9863. </field>
  9864. </fields>
  9865. </register>
  9866. <register>
  9867. <name>FIREWALL_NVDSSA</name>
  9868. <displayName>FIREWALL_NVDSSA</displayName>
  9869. <description>Non-volatile data segment start
  9870. address</description>
  9871. <addressOffset>0x8</addressOffset>
  9872. <size>0x20</size>
  9873. <access>read-write</access>
  9874. <resetValue>0x00000000</resetValue>
  9875. <fields>
  9876. <field>
  9877. <name>ADD</name>
  9878. <description>Non-volatile data segment start
  9879. address</description>
  9880. <bitOffset>8</bitOffset>
  9881. <bitWidth>16</bitWidth>
  9882. </field>
  9883. </fields>
  9884. </register>
  9885. <register>
  9886. <name>FIREWALL_NVDSL</name>
  9887. <displayName>FIREWALL_NVDSL</displayName>
  9888. <description>Non-volatile data segment
  9889. length</description>
  9890. <addressOffset>0xC</addressOffset>
  9891. <size>0x20</size>
  9892. <access>read-write</access>
  9893. <resetValue>0x00000000</resetValue>
  9894. <fields>
  9895. <field>
  9896. <name>LENG</name>
  9897. <description>Non-volatile data segment
  9898. length</description>
  9899. <bitOffset>8</bitOffset>
  9900. <bitWidth>14</bitWidth>
  9901. </field>
  9902. </fields>
  9903. </register>
  9904. <register>
  9905. <name>FIREWALL_VDSSA</name>
  9906. <displayName>FIREWALL_VDSSA</displayName>
  9907. <description>Volatile data segment start
  9908. address</description>
  9909. <addressOffset>0x10</addressOffset>
  9910. <size>0x20</size>
  9911. <access>read-write</access>
  9912. <resetValue>0x00000000</resetValue>
  9913. <fields>
  9914. <field>
  9915. <name>ADD</name>
  9916. <description>Volatile data segment start
  9917. address</description>
  9918. <bitOffset>6</bitOffset>
  9919. <bitWidth>10</bitWidth>
  9920. </field>
  9921. </fields>
  9922. </register>
  9923. <register>
  9924. <name>FIREWALL_VDSL</name>
  9925. <displayName>FIREWALL_VDSL</displayName>
  9926. <description>Volatile data segment length</description>
  9927. <addressOffset>0x14</addressOffset>
  9928. <size>0x20</size>
  9929. <access>read-write</access>
  9930. <resetValue>0x00000000</resetValue>
  9931. <fields>
  9932. <field>
  9933. <name>LENG</name>
  9934. <description>Non-volatile data segment
  9935. length</description>
  9936. <bitOffset>6</bitOffset>
  9937. <bitWidth>10</bitWidth>
  9938. </field>
  9939. </fields>
  9940. </register>
  9941. <register>
  9942. <name>FIREWALL_CR</name>
  9943. <displayName>FIREWALL_CR</displayName>
  9944. <description>Configuration register</description>
  9945. <addressOffset>0x20</addressOffset>
  9946. <size>0x20</size>
  9947. <access>read-write</access>
  9948. <resetValue>0x00000000</resetValue>
  9949. <fields>
  9950. <field>
  9951. <name>VDE</name>
  9952. <description>Volatile data execution</description>
  9953. <bitOffset>2</bitOffset>
  9954. <bitWidth>1</bitWidth>
  9955. </field>
  9956. <field>
  9957. <name>VDS</name>
  9958. <description>Volatile data shared</description>
  9959. <bitOffset>1</bitOffset>
  9960. <bitWidth>1</bitWidth>
  9961. </field>
  9962. <field>
  9963. <name>FPA</name>
  9964. <description>Firewall pre alarm</description>
  9965. <bitOffset>0</bitOffset>
  9966. <bitWidth>1</bitWidth>
  9967. </field>
  9968. </fields>
  9969. </register>
  9970. </registers>
  9971. </peripheral>
  9972. <peripheral>
  9973. <name>RCC</name>
  9974. <description>Reset and clock control</description>
  9975. <groupName>RCC</groupName>
  9976. <baseAddress>0x40021000</baseAddress>
  9977. <addressBlock>
  9978. <offset>0x0</offset>
  9979. <size>0x400</size>
  9980. <usage>registers</usage>
  9981. </addressBlock>
  9982. <interrupt>
  9983. <name>RCC</name>
  9984. <description>RCC global interrupt</description>
  9985. <value>4</value>
  9986. </interrupt>
  9987. <registers>
  9988. <register>
  9989. <name>CR</name>
  9990. <displayName>CR</displayName>
  9991. <description>Clock control register</description>
  9992. <addressOffset>0x0</addressOffset>
  9993. <size>0x20</size>
  9994. <resetValue>0x00000300</resetValue>
  9995. <fields>
  9996. <field>
  9997. <name>PLLRDY</name>
  9998. <description>PLL clock ready flag</description>
  9999. <bitOffset>25</bitOffset>
  10000. <bitWidth>1</bitWidth>
  10001. <access>read-only</access>
  10002. </field>
  10003. <field>
  10004. <name>PLLON</name>
  10005. <description>PLL enable bit</description>
  10006. <bitOffset>24</bitOffset>
  10007. <bitWidth>1</bitWidth>
  10008. <access>read-write</access>
  10009. </field>
  10010. <field>
  10011. <name>RTCPRE</name>
  10012. <description>TC/LCD prescaler</description>
  10013. <bitOffset>20</bitOffset>
  10014. <bitWidth>2</bitWidth>
  10015. <access>read-write</access>
  10016. </field>
  10017. <field>
  10018. <name>CSSLSEON</name>
  10019. <description>Clock security system on HSE enable
  10020. bit</description>
  10021. <bitOffset>19</bitOffset>
  10022. <bitWidth>1</bitWidth>
  10023. <access>read-write</access>
  10024. </field>
  10025. <field>
  10026. <name>HSEBYP</name>
  10027. <description>HSE clock bypass bit</description>
  10028. <bitOffset>18</bitOffset>
  10029. <bitWidth>1</bitWidth>
  10030. <access>read-write</access>
  10031. </field>
  10032. <field>
  10033. <name>HSERDY</name>
  10034. <description>HSE clock ready flag</description>
  10035. <bitOffset>17</bitOffset>
  10036. <bitWidth>1</bitWidth>
  10037. <access>read-only</access>
  10038. </field>
  10039. <field>
  10040. <name>HSEON</name>
  10041. <description>HSE clock enable bit</description>
  10042. <bitOffset>16</bitOffset>
  10043. <bitWidth>1</bitWidth>
  10044. <access>read-write</access>
  10045. </field>
  10046. <field>
  10047. <name>MSIRDY</name>
  10048. <description>MSI clock ready flag</description>
  10049. <bitOffset>9</bitOffset>
  10050. <bitWidth>1</bitWidth>
  10051. <access>read-only</access>
  10052. </field>
  10053. <field>
  10054. <name>MSION</name>
  10055. <description>MSI clock enable bit</description>
  10056. <bitOffset>8</bitOffset>
  10057. <bitWidth>1</bitWidth>
  10058. <access>read-write</access>
  10059. </field>
  10060. <field>
  10061. <name>HSI16DIVF</name>
  10062. <description>HSI16DIVF</description>
  10063. <bitOffset>4</bitOffset>
  10064. <bitWidth>1</bitWidth>
  10065. <access>read-only</access>
  10066. </field>
  10067. <field>
  10068. <name>HSI16DIVEN</name>
  10069. <description>HSI16DIVEN</description>
  10070. <bitOffset>3</bitOffset>
  10071. <bitWidth>1</bitWidth>
  10072. <access>read-write</access>
  10073. </field>
  10074. <field>
  10075. <name>HSI16RDYF</name>
  10076. <description>Internal high-speed clock ready
  10077. flag</description>
  10078. <bitOffset>2</bitOffset>
  10079. <bitWidth>1</bitWidth>
  10080. <access>read-write</access>
  10081. </field>
  10082. <field>
  10083. <name>HSI16KERON</name>
  10084. <description>High-speed internal clock enable bit for
  10085. some IP kernels</description>
  10086. <bitOffset>1</bitOffset>
  10087. <bitWidth>1</bitWidth>
  10088. <access>read-only</access>
  10089. </field>
  10090. <field>
  10091. <name>HSI16ON</name>
  10092. <description>16 MHz high-speed internal clock
  10093. enable</description>
  10094. <bitOffset>0</bitOffset>
  10095. <bitWidth>1</bitWidth>
  10096. <access>read-write</access>
  10097. </field>
  10098. </fields>
  10099. </register>
  10100. <register>
  10101. <name>ICSCR</name>
  10102. <displayName>ICSCR</displayName>
  10103. <description>Internal clock sources calibration
  10104. register</description>
  10105. <addressOffset>0x4</addressOffset>
  10106. <size>0x20</size>
  10107. <resetValue>0x0000B000</resetValue>
  10108. <fields>
  10109. <field>
  10110. <name>MSITRIM</name>
  10111. <description>MSI clock trimming</description>
  10112. <bitOffset>24</bitOffset>
  10113. <bitWidth>8</bitWidth>
  10114. <access>read-write</access>
  10115. </field>
  10116. <field>
  10117. <name>MSICAL</name>
  10118. <description>MSI clock calibration</description>
  10119. <bitOffset>16</bitOffset>
  10120. <bitWidth>8</bitWidth>
  10121. <access>read-only</access>
  10122. </field>
  10123. <field>
  10124. <name>MSIRANGE</name>
  10125. <description>MSI clock ranges</description>
  10126. <bitOffset>13</bitOffset>
  10127. <bitWidth>3</bitWidth>
  10128. <access>read-write</access>
  10129. </field>
  10130. <field>
  10131. <name>HSI16TRIM</name>
  10132. <description>High speed internal clock
  10133. trimming</description>
  10134. <bitOffset>8</bitOffset>
  10135. <bitWidth>5</bitWidth>
  10136. <access>read-write</access>
  10137. </field>
  10138. <field>
  10139. <name>HSI16CAL</name>
  10140. <description>nternal high speed clock
  10141. calibration</description>
  10142. <bitOffset>0</bitOffset>
  10143. <bitWidth>8</bitWidth>
  10144. <access>read-only</access>
  10145. </field>
  10146. </fields>
  10147. </register>
  10148. <register>
  10149. <name>CRRCR</name>
  10150. <displayName>CRRCR</displayName>
  10151. <description>Clock recovery RC register</description>
  10152. <addressOffset>0x8</addressOffset>
  10153. <size>0x20</size>
  10154. <resetValue>0x00000000</resetValue>
  10155. <fields>
  10156. <field>
  10157. <name>HSI48CAL</name>
  10158. <description>48 MHz HSI clock
  10159. calibration</description>
  10160. <bitOffset>8</bitOffset>
  10161. <bitWidth>8</bitWidth>
  10162. <access>read-only</access>
  10163. </field>
  10164. <field>
  10165. <name>HSI48RDY</name>
  10166. <description>48MHz HSI clock ready flag</description>
  10167. <bitOffset>1</bitOffset>
  10168. <bitWidth>1</bitWidth>
  10169. <access>read-only</access>
  10170. </field>
  10171. <field>
  10172. <name>HSI48ON</name>
  10173. <description>48MHz HSI clock enable bit</description>
  10174. <bitOffset>0</bitOffset>
  10175. <bitWidth>1</bitWidth>
  10176. <access>read-write</access>
  10177. </field>
  10178. </fields>
  10179. </register>
  10180. <register>
  10181. <name>CFGR</name>
  10182. <displayName>CFGR</displayName>
  10183. <description>Clock configuration register</description>
  10184. <addressOffset>0xC</addressOffset>
  10185. <size>0x20</size>
  10186. <resetValue>0x00000000</resetValue>
  10187. <fields>
  10188. <field>
  10189. <name>MCOPRE</name>
  10190. <description>Microcontroller clock output
  10191. prescaler</description>
  10192. <bitOffset>28</bitOffset>
  10193. <bitWidth>3</bitWidth>
  10194. <access>read-write</access>
  10195. </field>
  10196. <field>
  10197. <name>MCOSEL</name>
  10198. <description>Microcontroller clock output
  10199. selection</description>
  10200. <bitOffset>24</bitOffset>
  10201. <bitWidth>3</bitWidth>
  10202. <access>read-write</access>
  10203. </field>
  10204. <field>
  10205. <name>PLLDIV</name>
  10206. <description>PLL output division</description>
  10207. <bitOffset>22</bitOffset>
  10208. <bitWidth>2</bitWidth>
  10209. <access>read-write</access>
  10210. </field>
  10211. <field>
  10212. <name>PLLMUL</name>
  10213. <description>PLL multiplication factor</description>
  10214. <bitOffset>18</bitOffset>
  10215. <bitWidth>4</bitWidth>
  10216. <access>read-write</access>
  10217. </field>
  10218. <field>
  10219. <name>PLLSRC</name>
  10220. <description>PLL entry clock source</description>
  10221. <bitOffset>16</bitOffset>
  10222. <bitWidth>1</bitWidth>
  10223. <access>read-write</access>
  10224. </field>
  10225. <field>
  10226. <name>STOPWUCK</name>
  10227. <description>Wake-up from stop clock
  10228. selection</description>
  10229. <bitOffset>15</bitOffset>
  10230. <bitWidth>1</bitWidth>
  10231. <access>read-write</access>
  10232. </field>
  10233. <field>
  10234. <name>PPRE2</name>
  10235. <description>APB high-speed prescaler
  10236. (APB2)</description>
  10237. <bitOffset>11</bitOffset>
  10238. <bitWidth>3</bitWidth>
  10239. <access>read-write</access>
  10240. </field>
  10241. <field>
  10242. <name>PPRE1</name>
  10243. <description>APB low-speed prescaler
  10244. (APB1)</description>
  10245. <bitOffset>8</bitOffset>
  10246. <bitWidth>3</bitWidth>
  10247. <access>read-write</access>
  10248. </field>
  10249. <field>
  10250. <name>HPRE</name>
  10251. <description>AHB prescaler</description>
  10252. <bitOffset>4</bitOffset>
  10253. <bitWidth>4</bitWidth>
  10254. <access>read-write</access>
  10255. </field>
  10256. <field>
  10257. <name>SWS</name>
  10258. <description>System clock switch status</description>
  10259. <bitOffset>2</bitOffset>
  10260. <bitWidth>2</bitWidth>
  10261. <access>read-only</access>
  10262. </field>
  10263. <field>
  10264. <name>SW</name>
  10265. <description>System clock switch</description>
  10266. <bitOffset>0</bitOffset>
  10267. <bitWidth>2</bitWidth>
  10268. <access>read-write</access>
  10269. </field>
  10270. </fields>
  10271. </register>
  10272. <register>
  10273. <name>CIER</name>
  10274. <displayName>CIER</displayName>
  10275. <description>Clock interrupt enable
  10276. register</description>
  10277. <addressOffset>0x10</addressOffset>
  10278. <size>0x20</size>
  10279. <access>read-only</access>
  10280. <resetValue>0x00000000</resetValue>
  10281. <fields>
  10282. <field>
  10283. <name>CSSLSE</name>
  10284. <description>LSE CSS interrupt flag</description>
  10285. <bitOffset>7</bitOffset>
  10286. <bitWidth>1</bitWidth>
  10287. </field>
  10288. <field>
  10289. <name>HSI48RDYIE</name>
  10290. <description>HSI48 ready interrupt flag</description>
  10291. <bitOffset>6</bitOffset>
  10292. <bitWidth>1</bitWidth>
  10293. </field>
  10294. <field>
  10295. <name>MSIRDYIE</name>
  10296. <description>MSI ready interrupt flag</description>
  10297. <bitOffset>5</bitOffset>
  10298. <bitWidth>1</bitWidth>
  10299. </field>
  10300. <field>
  10301. <name>PLLRDYIE</name>
  10302. <description>PLL ready interrupt flag</description>
  10303. <bitOffset>4</bitOffset>
  10304. <bitWidth>1</bitWidth>
  10305. </field>
  10306. <field>
  10307. <name>HSERDYIE</name>
  10308. <description>HSE ready interrupt flag</description>
  10309. <bitOffset>3</bitOffset>
  10310. <bitWidth>1</bitWidth>
  10311. </field>
  10312. <field>
  10313. <name>HSI16RDYIE</name>
  10314. <description>HSI16 ready interrupt flag</description>
  10315. <bitOffset>2</bitOffset>
  10316. <bitWidth>1</bitWidth>
  10317. </field>
  10318. <field>
  10319. <name>LSERDYIE</name>
  10320. <description>LSE ready interrupt flag</description>
  10321. <bitOffset>1</bitOffset>
  10322. <bitWidth>1</bitWidth>
  10323. </field>
  10324. <field>
  10325. <name>LSIRDYIE</name>
  10326. <description>LSI ready interrupt flag</description>
  10327. <bitOffset>0</bitOffset>
  10328. <bitWidth>1</bitWidth>
  10329. </field>
  10330. </fields>
  10331. </register>
  10332. <register>
  10333. <name>CIFR</name>
  10334. <displayName>CIFR</displayName>
  10335. <description>Clock interrupt flag register</description>
  10336. <addressOffset>0x14</addressOffset>
  10337. <size>0x20</size>
  10338. <access>read-only</access>
  10339. <resetValue>0x00000000</resetValue>
  10340. <fields>
  10341. <field>
  10342. <name>CSSHSEF</name>
  10343. <description>Clock Security System Interrupt
  10344. flag</description>
  10345. <bitOffset>8</bitOffset>
  10346. <bitWidth>1</bitWidth>
  10347. </field>
  10348. <field>
  10349. <name>CSSLSEF</name>
  10350. <description>LSE Clock Security System Interrupt
  10351. flag</description>
  10352. <bitOffset>7</bitOffset>
  10353. <bitWidth>1</bitWidth>
  10354. </field>
  10355. <field>
  10356. <name>HSI48RDYF</name>
  10357. <description>HSI48 ready interrupt flag</description>
  10358. <bitOffset>6</bitOffset>
  10359. <bitWidth>1</bitWidth>
  10360. </field>
  10361. <field>
  10362. <name>MSIRDYF</name>
  10363. <description>MSI ready interrupt flag</description>
  10364. <bitOffset>5</bitOffset>
  10365. <bitWidth>1</bitWidth>
  10366. </field>
  10367. <field>
  10368. <name>PLLRDYF</name>
  10369. <description>PLL ready interrupt flag</description>
  10370. <bitOffset>4</bitOffset>
  10371. <bitWidth>1</bitWidth>
  10372. </field>
  10373. <field>
  10374. <name>HSERDYF</name>
  10375. <description>HSE ready interrupt flag</description>
  10376. <bitOffset>3</bitOffset>
  10377. <bitWidth>1</bitWidth>
  10378. </field>
  10379. <field>
  10380. <name>HSI16RDYF</name>
  10381. <description>HSI16 ready interrupt flag</description>
  10382. <bitOffset>2</bitOffset>
  10383. <bitWidth>1</bitWidth>
  10384. </field>
  10385. <field>
  10386. <name>LSERDYF</name>
  10387. <description>LSE ready interrupt flag</description>
  10388. <bitOffset>1</bitOffset>
  10389. <bitWidth>1</bitWidth>
  10390. </field>
  10391. <field>
  10392. <name>LSIRDYF</name>
  10393. <description>LSI ready interrupt flag</description>
  10394. <bitOffset>0</bitOffset>
  10395. <bitWidth>1</bitWidth>
  10396. </field>
  10397. </fields>
  10398. </register>
  10399. <register>
  10400. <name>CICR</name>
  10401. <displayName>CICR</displayName>
  10402. <description>Clock interrupt clear register</description>
  10403. <addressOffset>0x18</addressOffset>
  10404. <size>0x20</size>
  10405. <access>read-only</access>
  10406. <resetValue>0x00000000</resetValue>
  10407. <fields>
  10408. <field>
  10409. <name>CSSHSEC</name>
  10410. <description>Clock Security System Interrupt
  10411. clear</description>
  10412. <bitOffset>8</bitOffset>
  10413. <bitWidth>1</bitWidth>
  10414. </field>
  10415. <field>
  10416. <name>CSSLSEC</name>
  10417. <description>LSE Clock Security System Interrupt
  10418. clear</description>
  10419. <bitOffset>7</bitOffset>
  10420. <bitWidth>1</bitWidth>
  10421. </field>
  10422. <field>
  10423. <name>HSI48RDYC</name>
  10424. <description>HSI48 ready Interrupt
  10425. clear</description>
  10426. <bitOffset>6</bitOffset>
  10427. <bitWidth>1</bitWidth>
  10428. </field>
  10429. <field>
  10430. <name>MSIRDYC</name>
  10431. <description>MSI ready Interrupt clear</description>
  10432. <bitOffset>5</bitOffset>
  10433. <bitWidth>1</bitWidth>
  10434. </field>
  10435. <field>
  10436. <name>PLLRDYC</name>
  10437. <description>PLL ready Interrupt clear</description>
  10438. <bitOffset>4</bitOffset>
  10439. <bitWidth>1</bitWidth>
  10440. </field>
  10441. <field>
  10442. <name>HSERDYC</name>
  10443. <description>HSE ready Interrupt clear</description>
  10444. <bitOffset>3</bitOffset>
  10445. <bitWidth>1</bitWidth>
  10446. </field>
  10447. <field>
  10448. <name>HSI16RDYC</name>
  10449. <description>HSI16 ready Interrupt
  10450. clear</description>
  10451. <bitOffset>2</bitOffset>
  10452. <bitWidth>1</bitWidth>
  10453. </field>
  10454. <field>
  10455. <name>LSERDYC</name>
  10456. <description>LSE ready Interrupt clear</description>
  10457. <bitOffset>1</bitOffset>
  10458. <bitWidth>1</bitWidth>
  10459. </field>
  10460. <field>
  10461. <name>LSIRDYC</name>
  10462. <description>LSI ready Interrupt clear</description>
  10463. <bitOffset>0</bitOffset>
  10464. <bitWidth>1</bitWidth>
  10465. </field>
  10466. </fields>
  10467. </register>
  10468. <register>
  10469. <name>IOPRSTR</name>
  10470. <displayName>IOPRSTR</displayName>
  10471. <description>GPIO reset register</description>
  10472. <addressOffset>0x1C</addressOffset>
  10473. <size>0x20</size>
  10474. <access>read-write</access>
  10475. <resetValue>0x00000000</resetValue>
  10476. <fields>
  10477. <field>
  10478. <name>IOPHRST</name>
  10479. <description>I/O port H reset</description>
  10480. <bitOffset>7</bitOffset>
  10481. <bitWidth>1</bitWidth>
  10482. </field>
  10483. <field>
  10484. <name>IOPDRST</name>
  10485. <description>I/O port D reset</description>
  10486. <bitOffset>3</bitOffset>
  10487. <bitWidth>1</bitWidth>
  10488. </field>
  10489. <field>
  10490. <name>IOPCRST</name>
  10491. <description>I/O port A reset</description>
  10492. <bitOffset>2</bitOffset>
  10493. <bitWidth>1</bitWidth>
  10494. </field>
  10495. <field>
  10496. <name>IOPBRST</name>
  10497. <description>I/O port B reset</description>
  10498. <bitOffset>1</bitOffset>
  10499. <bitWidth>1</bitWidth>
  10500. </field>
  10501. <field>
  10502. <name>IOPARST</name>
  10503. <description>I/O port A reset</description>
  10504. <bitOffset>0</bitOffset>
  10505. <bitWidth>1</bitWidth>
  10506. </field>
  10507. </fields>
  10508. </register>
  10509. <register>
  10510. <name>AHBRSTR</name>
  10511. <displayName>AHBRSTR</displayName>
  10512. <description>AHB peripheral reset register</description>
  10513. <addressOffset>0x20</addressOffset>
  10514. <size>0x20</size>
  10515. <access>read-write</access>
  10516. <resetValue>0x00000000</resetValue>
  10517. <fields>
  10518. <field>
  10519. <name>CRYPRST</name>
  10520. <description>Crypto module reset</description>
  10521. <bitOffset>24</bitOffset>
  10522. <bitWidth>1</bitWidth>
  10523. </field>
  10524. <field>
  10525. <name>RNGRST</name>
  10526. <description>Random Number Generator module
  10527. reset</description>
  10528. <bitOffset>20</bitOffset>
  10529. <bitWidth>1</bitWidth>
  10530. </field>
  10531. <field>
  10532. <name>TOUCHRST</name>
  10533. <description>Touch Sensing reset</description>
  10534. <bitOffset>16</bitOffset>
  10535. <bitWidth>1</bitWidth>
  10536. </field>
  10537. <field>
  10538. <name>CRCRST</name>
  10539. <description>Test integration module
  10540. reset</description>
  10541. <bitOffset>12</bitOffset>
  10542. <bitWidth>1</bitWidth>
  10543. </field>
  10544. <field>
  10545. <name>MIFRST</name>
  10546. <description>Memory interface reset</description>
  10547. <bitOffset>8</bitOffset>
  10548. <bitWidth>1</bitWidth>
  10549. </field>
  10550. <field>
  10551. <name>DMARST</name>
  10552. <description>DMA reset</description>
  10553. <bitOffset>0</bitOffset>
  10554. <bitWidth>1</bitWidth>
  10555. </field>
  10556. </fields>
  10557. </register>
  10558. <register>
  10559. <name>APB2RSTR</name>
  10560. <displayName>APB2RSTR</displayName>
  10561. <description>APB2 peripheral reset register</description>
  10562. <addressOffset>0x24</addressOffset>
  10563. <size>0x20</size>
  10564. <access>read-write</access>
  10565. <resetValue>0x000000000</resetValue>
  10566. <fields>
  10567. <field>
  10568. <name>DBGRST</name>
  10569. <description>DBG reset</description>
  10570. <bitOffset>22</bitOffset>
  10571. <bitWidth>1</bitWidth>
  10572. </field>
  10573. <field>
  10574. <name>USART1RST</name>
  10575. <description>USART1 reset</description>
  10576. <bitOffset>14</bitOffset>
  10577. <bitWidth>1</bitWidth>
  10578. </field>
  10579. <field>
  10580. <name>SPI1RST</name>
  10581. <description>SPI 1 reset</description>
  10582. <bitOffset>12</bitOffset>
  10583. <bitWidth>1</bitWidth>
  10584. </field>
  10585. <field>
  10586. <name>ADCRST</name>
  10587. <description>ADC interface reset</description>
  10588. <bitOffset>9</bitOffset>
  10589. <bitWidth>1</bitWidth>
  10590. </field>
  10591. <field>
  10592. <name>TM12RST</name>
  10593. <description>TIM22 timer reset</description>
  10594. <bitOffset>5</bitOffset>
  10595. <bitWidth>1</bitWidth>
  10596. </field>
  10597. <field>
  10598. <name>TIM21RST</name>
  10599. <description>TIM21 timer reset</description>
  10600. <bitOffset>2</bitOffset>
  10601. <bitWidth>1</bitWidth>
  10602. </field>
  10603. <field>
  10604. <name>SYSCFGRST</name>
  10605. <description>System configuration controller
  10606. reset</description>
  10607. <bitOffset>0</bitOffset>
  10608. <bitWidth>1</bitWidth>
  10609. </field>
  10610. </fields>
  10611. </register>
  10612. <register>
  10613. <name>APB1RSTR</name>
  10614. <displayName>APB1RSTR</displayName>
  10615. <description>APB1 peripheral reset register</description>
  10616. <addressOffset>0x28</addressOffset>
  10617. <size>0x20</size>
  10618. <access>read-write</access>
  10619. <resetValue>0x00000000</resetValue>
  10620. <fields>
  10621. <field>
  10622. <name>LPTIM1RST</name>
  10623. <description>Low power timer reset</description>
  10624. <bitOffset>31</bitOffset>
  10625. <bitWidth>1</bitWidth>
  10626. </field>
  10627. <field>
  10628. <name>DACRST</name>
  10629. <description>DAC interface reset</description>
  10630. <bitOffset>29</bitOffset>
  10631. <bitWidth>1</bitWidth>
  10632. </field>
  10633. <field>
  10634. <name>PWRRST</name>
  10635. <description>Power interface reset</description>
  10636. <bitOffset>28</bitOffset>
  10637. <bitWidth>1</bitWidth>
  10638. </field>
  10639. <field>
  10640. <name>CRSRST</name>
  10641. <description>Clock recovery system
  10642. reset</description>
  10643. <bitOffset>27</bitOffset>
  10644. <bitWidth>1</bitWidth>
  10645. </field>
  10646. <field>
  10647. <name>USBRST</name>
  10648. <description>USB reset</description>
  10649. <bitOffset>23</bitOffset>
  10650. <bitWidth>1</bitWidth>
  10651. </field>
  10652. <field>
  10653. <name>I2C2RST</name>
  10654. <description>I2C2 reset</description>
  10655. <bitOffset>22</bitOffset>
  10656. <bitWidth>1</bitWidth>
  10657. </field>
  10658. <field>
  10659. <name>I2C1RST</name>
  10660. <description>I2C1 reset</description>
  10661. <bitOffset>21</bitOffset>
  10662. <bitWidth>1</bitWidth>
  10663. </field>
  10664. <field>
  10665. <name>LPUART1RST</name>
  10666. <description>LPUART1 reset</description>
  10667. <bitOffset>18</bitOffset>
  10668. <bitWidth>1</bitWidth>
  10669. </field>
  10670. <field>
  10671. <name>LPUART12RST</name>
  10672. <description>UART2 reset</description>
  10673. <bitOffset>17</bitOffset>
  10674. <bitWidth>1</bitWidth>
  10675. </field>
  10676. <field>
  10677. <name>SPI2RST</name>
  10678. <description>SPI2 reset</description>
  10679. <bitOffset>14</bitOffset>
  10680. <bitWidth>1</bitWidth>
  10681. </field>
  10682. <field>
  10683. <name>WWDRST</name>
  10684. <description>Window watchdog reset</description>
  10685. <bitOffset>11</bitOffset>
  10686. <bitWidth>1</bitWidth>
  10687. </field>
  10688. <field>
  10689. <name>TIM6RST</name>
  10690. <description>Timer 6 reset</description>
  10691. <bitOffset>4</bitOffset>
  10692. <bitWidth>1</bitWidth>
  10693. </field>
  10694. <field>
  10695. <name>TIM2RST</name>
  10696. <description>Timer2 reset</description>
  10697. <bitOffset>0</bitOffset>
  10698. <bitWidth>1</bitWidth>
  10699. </field>
  10700. </fields>
  10701. </register>
  10702. <register>
  10703. <name>IOPENR</name>
  10704. <displayName>IOPENR</displayName>
  10705. <description>GPIO clock enable register</description>
  10706. <addressOffset>0x2C</addressOffset>
  10707. <size>0x20</size>
  10708. <access>read-write</access>
  10709. <resetValue>0x00000000</resetValue>
  10710. <fields>
  10711. <field>
  10712. <name>IOPHEN</name>
  10713. <description>I/O port H clock enable
  10714. bit</description>
  10715. <bitOffset>7</bitOffset>
  10716. <bitWidth>1</bitWidth>
  10717. </field>
  10718. <field>
  10719. <name>IOPDEN</name>
  10720. <description>I/O port D clock enable
  10721. bit</description>
  10722. <bitOffset>3</bitOffset>
  10723. <bitWidth>1</bitWidth>
  10724. </field>
  10725. <field>
  10726. <name>IOPCEN</name>
  10727. <description>IO port A clock enable bit</description>
  10728. <bitOffset>2</bitOffset>
  10729. <bitWidth>1</bitWidth>
  10730. </field>
  10731. <field>
  10732. <name>IOPBEN</name>
  10733. <description>IO port B clock enable bit</description>
  10734. <bitOffset>1</bitOffset>
  10735. <bitWidth>1</bitWidth>
  10736. </field>
  10737. <field>
  10738. <name>IOPAEN</name>
  10739. <description>IO port A clock enable bit</description>
  10740. <bitOffset>0</bitOffset>
  10741. <bitWidth>1</bitWidth>
  10742. </field>
  10743. </fields>
  10744. </register>
  10745. <register>
  10746. <name>AHBENR</name>
  10747. <displayName>AHBENR</displayName>
  10748. <description>AHB peripheral clock enable
  10749. register</description>
  10750. <addressOffset>0x30</addressOffset>
  10751. <size>0x20</size>
  10752. <access>read-write</access>
  10753. <resetValue>0x00000100</resetValue>
  10754. <fields>
  10755. <field>
  10756. <name>CRYPEN</name>
  10757. <description>Crypto clock enable bit</description>
  10758. <bitOffset>24</bitOffset>
  10759. <bitWidth>1</bitWidth>
  10760. </field>
  10761. <field>
  10762. <name>RNGEN</name>
  10763. <description>Random Number Generator clock enable
  10764. bit</description>
  10765. <bitOffset>20</bitOffset>
  10766. <bitWidth>1</bitWidth>
  10767. </field>
  10768. <field>
  10769. <name>TOUCHEN</name>
  10770. <description>Touch Sensing clock enable
  10771. bit</description>
  10772. <bitOffset>16</bitOffset>
  10773. <bitWidth>1</bitWidth>
  10774. </field>
  10775. <field>
  10776. <name>CRCEN</name>
  10777. <description>CRC clock enable bit</description>
  10778. <bitOffset>12</bitOffset>
  10779. <bitWidth>1</bitWidth>
  10780. </field>
  10781. <field>
  10782. <name>MIFEN</name>
  10783. <description>NVM interface clock enable
  10784. bit</description>
  10785. <bitOffset>8</bitOffset>
  10786. <bitWidth>1</bitWidth>
  10787. </field>
  10788. <field>
  10789. <name>DMAEN</name>
  10790. <description>DMA clock enable bit</description>
  10791. <bitOffset>0</bitOffset>
  10792. <bitWidth>1</bitWidth>
  10793. </field>
  10794. </fields>
  10795. </register>
  10796. <register>
  10797. <name>APB2ENR</name>
  10798. <displayName>APB2ENR</displayName>
  10799. <description>APB2 peripheral clock enable
  10800. register</description>
  10801. <addressOffset>0x34</addressOffset>
  10802. <size>0x20</size>
  10803. <access>read-write</access>
  10804. <resetValue>0x00000000</resetValue>
  10805. <fields>
  10806. <field>
  10807. <name>DBGEN</name>
  10808. <description>DBG clock enable bit</description>
  10809. <bitOffset>22</bitOffset>
  10810. <bitWidth>1</bitWidth>
  10811. </field>
  10812. <field>
  10813. <name>USART1EN</name>
  10814. <description>USART1 clock enable bit</description>
  10815. <bitOffset>14</bitOffset>
  10816. <bitWidth>1</bitWidth>
  10817. </field>
  10818. <field>
  10819. <name>SPI1EN</name>
  10820. <description>SPI1 clock enable bit</description>
  10821. <bitOffset>12</bitOffset>
  10822. <bitWidth>1</bitWidth>
  10823. </field>
  10824. <field>
  10825. <name>ADCEN</name>
  10826. <description>ADC clock enable bit</description>
  10827. <bitOffset>9</bitOffset>
  10828. <bitWidth>1</bitWidth>
  10829. </field>
  10830. <field>
  10831. <name>MIFIEN</name>
  10832. <description>MiFaRe Firewall clock enable
  10833. bit</description>
  10834. <bitOffset>7</bitOffset>
  10835. <bitWidth>1</bitWidth>
  10836. </field>
  10837. <field>
  10838. <name>TIM22EN</name>
  10839. <description>TIM22 timer clock enable
  10840. bit</description>
  10841. <bitOffset>5</bitOffset>
  10842. <bitWidth>1</bitWidth>
  10843. </field>
  10844. <field>
  10845. <name>TIM21EN</name>
  10846. <description>TIM21 timer clock enable
  10847. bit</description>
  10848. <bitOffset>2</bitOffset>
  10849. <bitWidth>1</bitWidth>
  10850. </field>
  10851. <field>
  10852. <name>SYSCFGEN</name>
  10853. <description>System configuration controller clock
  10854. enable bit</description>
  10855. <bitOffset>0</bitOffset>
  10856. <bitWidth>1</bitWidth>
  10857. </field>
  10858. </fields>
  10859. </register>
  10860. <register>
  10861. <name>APB1ENR</name>
  10862. <displayName>APB1ENR</displayName>
  10863. <description>APB1 peripheral clock enable
  10864. register</description>
  10865. <addressOffset>0x38</addressOffset>
  10866. <size>0x20</size>
  10867. <access>read-write</access>
  10868. <resetValue>0x00000000</resetValue>
  10869. <fields>
  10870. <field>
  10871. <name>LPTIM1EN</name>
  10872. <description>Low power timer clock enable
  10873. bit</description>
  10874. <bitOffset>31</bitOffset>
  10875. <bitWidth>1</bitWidth>
  10876. </field>
  10877. <field>
  10878. <name>DACEN</name>
  10879. <description>DAC interface clock enable
  10880. bit</description>
  10881. <bitOffset>29</bitOffset>
  10882. <bitWidth>1</bitWidth>
  10883. </field>
  10884. <field>
  10885. <name>PWREN</name>
  10886. <description>Power interface clock enable
  10887. bit</description>
  10888. <bitOffset>28</bitOffset>
  10889. <bitWidth>1</bitWidth>
  10890. </field>
  10891. <field>
  10892. <name>CRSEN</name>
  10893. <description>Clock recovery system clock enable
  10894. bit</description>
  10895. <bitOffset>27</bitOffset>
  10896. <bitWidth>1</bitWidth>
  10897. </field>
  10898. <field>
  10899. <name>USBEN</name>
  10900. <description>USB clock enable bit</description>
  10901. <bitOffset>23</bitOffset>
  10902. <bitWidth>1</bitWidth>
  10903. </field>
  10904. <field>
  10905. <name>I2C2EN</name>
  10906. <description>I2C2 clock enable bit</description>
  10907. <bitOffset>22</bitOffset>
  10908. <bitWidth>1</bitWidth>
  10909. </field>
  10910. <field>
  10911. <name>I2C1EN</name>
  10912. <description>I2C1 clock enable bit</description>
  10913. <bitOffset>21</bitOffset>
  10914. <bitWidth>1</bitWidth>
  10915. </field>
  10916. <field>
  10917. <name>LPUART1EN</name>
  10918. <description>LPUART1 clock enable bit</description>
  10919. <bitOffset>18</bitOffset>
  10920. <bitWidth>1</bitWidth>
  10921. </field>
  10922. <field>
  10923. <name>USART2EN</name>
  10924. <description>UART2 clock enable bit</description>
  10925. <bitOffset>17</bitOffset>
  10926. <bitWidth>1</bitWidth>
  10927. </field>
  10928. <field>
  10929. <name>SPI2EN</name>
  10930. <description>SPI2 clock enable bit</description>
  10931. <bitOffset>14</bitOffset>
  10932. <bitWidth>1</bitWidth>
  10933. </field>
  10934. <field>
  10935. <name>WWDGEN</name>
  10936. <description>Window watchdog clock enable
  10937. bit</description>
  10938. <bitOffset>11</bitOffset>
  10939. <bitWidth>1</bitWidth>
  10940. </field>
  10941. <field>
  10942. <name>TIM6EN</name>
  10943. <description>Timer 6 clock enable bit</description>
  10944. <bitOffset>4</bitOffset>
  10945. <bitWidth>1</bitWidth>
  10946. </field>
  10947. <field>
  10948. <name>TIM2EN</name>
  10949. <description>Timer2 clock enable bit</description>
  10950. <bitOffset>0</bitOffset>
  10951. <bitWidth>1</bitWidth>
  10952. </field>
  10953. </fields>
  10954. </register>
  10955. <register>
  10956. <name>IOPSMEN</name>
  10957. <displayName>IOPSMEN</displayName>
  10958. <description>GPIO clock enable in sleep mode
  10959. register</description>
  10960. <addressOffset>0x3C</addressOffset>
  10961. <size>0x20</size>
  10962. <access>read-write</access>
  10963. <resetValue>0x0000008F</resetValue>
  10964. <fields>
  10965. <field>
  10966. <name>IOPHSMEN</name>
  10967. <description>IOPHSMEN</description>
  10968. <bitOffset>7</bitOffset>
  10969. <bitWidth>1</bitWidth>
  10970. </field>
  10971. <field>
  10972. <name>IOPDSMEN</name>
  10973. <description>IOPDSMEN</description>
  10974. <bitOffset>3</bitOffset>
  10975. <bitWidth>1</bitWidth>
  10976. </field>
  10977. <field>
  10978. <name>IOPCSMEN</name>
  10979. <description>IOPCSMEN</description>
  10980. <bitOffset>2</bitOffset>
  10981. <bitWidth>1</bitWidth>
  10982. </field>
  10983. <field>
  10984. <name>IOPBSMEN</name>
  10985. <description>IOPBSMEN</description>
  10986. <bitOffset>1</bitOffset>
  10987. <bitWidth>1</bitWidth>
  10988. </field>
  10989. <field>
  10990. <name>IOPASMEN</name>
  10991. <description>IOPASMEN</description>
  10992. <bitOffset>0</bitOffset>
  10993. <bitWidth>1</bitWidth>
  10994. </field>
  10995. </fields>
  10996. </register>
  10997. <register>
  10998. <name>AHBSMENR</name>
  10999. <displayName>AHBSMENR</displayName>
  11000. <description>AHB peripheral clock enable in sleep mode
  11001. register</description>
  11002. <addressOffset>0x40</addressOffset>
  11003. <size>0x20</size>
  11004. <access>read-write</access>
  11005. <resetValue>0x01111301</resetValue>
  11006. <fields>
  11007. <field>
  11008. <name>CRYPSMEN</name>
  11009. <description>Crypto clock enable during sleep mode
  11010. bit</description>
  11011. <bitOffset>24</bitOffset>
  11012. <bitWidth>1</bitWidth>
  11013. </field>
  11014. <field>
  11015. <name>RNGSMEN</name>
  11016. <description>Random Number Generator clock enable
  11017. during sleep mode bit</description>
  11018. <bitOffset>20</bitOffset>
  11019. <bitWidth>1</bitWidth>
  11020. </field>
  11021. <field>
  11022. <name>TOUCHSMEN</name>
  11023. <description>Touch Sensing clock enable during sleep
  11024. mode bit</description>
  11025. <bitOffset>16</bitOffset>
  11026. <bitWidth>1</bitWidth>
  11027. </field>
  11028. <field>
  11029. <name>CRCSMEN</name>
  11030. <description>CRC clock enable during sleep mode
  11031. bit</description>
  11032. <bitOffset>12</bitOffset>
  11033. <bitWidth>1</bitWidth>
  11034. </field>
  11035. <field>
  11036. <name>SRAMSMEN</name>
  11037. <description>SRAM interface clock enable during sleep
  11038. mode bit</description>
  11039. <bitOffset>9</bitOffset>
  11040. <bitWidth>1</bitWidth>
  11041. </field>
  11042. <field>
  11043. <name>MIFSMEN</name>
  11044. <description>NVM interface clock enable during sleep
  11045. mode bit</description>
  11046. <bitOffset>8</bitOffset>
  11047. <bitWidth>1</bitWidth>
  11048. </field>
  11049. <field>
  11050. <name>DMASMEN</name>
  11051. <description>DMA clock enable during sleep mode
  11052. bit</description>
  11053. <bitOffset>0</bitOffset>
  11054. <bitWidth>1</bitWidth>
  11055. </field>
  11056. </fields>
  11057. </register>
  11058. <register>
  11059. <name>APB2SMENR</name>
  11060. <displayName>APB2SMENR</displayName>
  11061. <description>APB2 peripheral clock enable in sleep mode
  11062. register</description>
  11063. <addressOffset>0x44</addressOffset>
  11064. <size>0x20</size>
  11065. <access>read-write</access>
  11066. <resetValue>0x00405225</resetValue>
  11067. <fields>
  11068. <field>
  11069. <name>DBGSMEN</name>
  11070. <description>DBG clock enable during sleep mode
  11071. bit</description>
  11072. <bitOffset>22</bitOffset>
  11073. <bitWidth>1</bitWidth>
  11074. </field>
  11075. <field>
  11076. <name>USART1SMEN</name>
  11077. <description>USART1 clock enable during sleep mode
  11078. bit</description>
  11079. <bitOffset>14</bitOffset>
  11080. <bitWidth>1</bitWidth>
  11081. </field>
  11082. <field>
  11083. <name>SPI1SMEN</name>
  11084. <description>SPI1 clock enable during sleep mode
  11085. bit</description>
  11086. <bitOffset>12</bitOffset>
  11087. <bitWidth>1</bitWidth>
  11088. </field>
  11089. <field>
  11090. <name>ADCSMEN</name>
  11091. <description>ADC clock enable during sleep mode
  11092. bit</description>
  11093. <bitOffset>9</bitOffset>
  11094. <bitWidth>1</bitWidth>
  11095. </field>
  11096. <field>
  11097. <name>TIM22SMEN</name>
  11098. <description>TIM22 timer clock enable during sleep
  11099. mode bit</description>
  11100. <bitOffset>5</bitOffset>
  11101. <bitWidth>1</bitWidth>
  11102. </field>
  11103. <field>
  11104. <name>TIM21SMEN</name>
  11105. <description>TIM21 timer clock enable during sleep
  11106. mode bit</description>
  11107. <bitOffset>2</bitOffset>
  11108. <bitWidth>1</bitWidth>
  11109. </field>
  11110. <field>
  11111. <name>SYSCFGSMEN</name>
  11112. <description>System configuration controller clock
  11113. enable during sleep mode bit</description>
  11114. <bitOffset>0</bitOffset>
  11115. <bitWidth>1</bitWidth>
  11116. </field>
  11117. </fields>
  11118. </register>
  11119. <register>
  11120. <name>APB1SMENR</name>
  11121. <displayName>APB1SMENR</displayName>
  11122. <description>APB1 peripheral clock enable in sleep mode
  11123. register</description>
  11124. <addressOffset>0x48</addressOffset>
  11125. <size>0x20</size>
  11126. <access>read-write</access>
  11127. <resetValue>0xB8E64A11</resetValue>
  11128. <fields>
  11129. <field>
  11130. <name>LPTIM1SMEN</name>
  11131. <description>Low power timer clock enable during
  11132. sleep mode bit</description>
  11133. <bitOffset>31</bitOffset>
  11134. <bitWidth>1</bitWidth>
  11135. </field>
  11136. <field>
  11137. <name>DACSMEN</name>
  11138. <description>DAC interface clock enable during sleep
  11139. mode bit</description>
  11140. <bitOffset>29</bitOffset>
  11141. <bitWidth>1</bitWidth>
  11142. </field>
  11143. <field>
  11144. <name>PWRSMEN</name>
  11145. <description>Power interface clock enable during
  11146. sleep mode bit</description>
  11147. <bitOffset>28</bitOffset>
  11148. <bitWidth>1</bitWidth>
  11149. </field>
  11150. <field>
  11151. <name>CRSSMEN</name>
  11152. <description>Clock recovery system clock enable
  11153. during sleep mode bit</description>
  11154. <bitOffset>27</bitOffset>
  11155. <bitWidth>1</bitWidth>
  11156. </field>
  11157. <field>
  11158. <name>USBSMEN</name>
  11159. <description>USB clock enable during sleep mode
  11160. bit</description>
  11161. <bitOffset>23</bitOffset>
  11162. <bitWidth>1</bitWidth>
  11163. </field>
  11164. <field>
  11165. <name>I2C2SMEN</name>
  11166. <description>I2C2 clock enable during sleep mode
  11167. bit</description>
  11168. <bitOffset>22</bitOffset>
  11169. <bitWidth>1</bitWidth>
  11170. </field>
  11171. <field>
  11172. <name>I2C1SMEN</name>
  11173. <description>I2C1 clock enable during sleep mode
  11174. bit</description>
  11175. <bitOffset>21</bitOffset>
  11176. <bitWidth>1</bitWidth>
  11177. </field>
  11178. <field>
  11179. <name>LPUART1SMEN</name>
  11180. <description>LPUART1 clock enable during sleep mode
  11181. bit</description>
  11182. <bitOffset>18</bitOffset>
  11183. <bitWidth>1</bitWidth>
  11184. </field>
  11185. <field>
  11186. <name>USART2SMEN</name>
  11187. <description>UART2 clock enable during sleep mode
  11188. bit</description>
  11189. <bitOffset>17</bitOffset>
  11190. <bitWidth>1</bitWidth>
  11191. </field>
  11192. <field>
  11193. <name>SPI2SMEN</name>
  11194. <description>SPI2 clock enable during sleep mode
  11195. bit</description>
  11196. <bitOffset>14</bitOffset>
  11197. <bitWidth>1</bitWidth>
  11198. </field>
  11199. <field>
  11200. <name>WWDGSMEN</name>
  11201. <description>Window watchdog clock enable during
  11202. sleep mode bit</description>
  11203. <bitOffset>11</bitOffset>
  11204. <bitWidth>1</bitWidth>
  11205. </field>
  11206. <field>
  11207. <name>TIM6SMEN</name>
  11208. <description>Timer 6 clock enable during sleep mode
  11209. bit</description>
  11210. <bitOffset>4</bitOffset>
  11211. <bitWidth>1</bitWidth>
  11212. </field>
  11213. <field>
  11214. <name>TIM2SMEN</name>
  11215. <description>Timer2 clock enable during sleep mode
  11216. bit</description>
  11217. <bitOffset>0</bitOffset>
  11218. <bitWidth>1</bitWidth>
  11219. </field>
  11220. </fields>
  11221. </register>
  11222. <register>
  11223. <name>CCIPR</name>
  11224. <displayName>CCIPR</displayName>
  11225. <description>Clock configuration register</description>
  11226. <addressOffset>0x4C</addressOffset>
  11227. <size>0x20</size>
  11228. <access>read-write</access>
  11229. <resetValue>0x00000000</resetValue>
  11230. <fields>
  11231. <field>
  11232. <name>HSI48MSEL</name>
  11233. <description>48 MHz HSI48 clock source selection
  11234. bit</description>
  11235. <bitOffset>26</bitOffset>
  11236. <bitWidth>1</bitWidth>
  11237. </field>
  11238. <field>
  11239. <name>LPTIM1SEL1</name>
  11240. <description>Low Power Timer clock source selection
  11241. bits</description>
  11242. <bitOffset>19</bitOffset>
  11243. <bitWidth>1</bitWidth>
  11244. </field>
  11245. <field>
  11246. <name>LPTIM1SEL0</name>
  11247. <description>LPTIM1SEL0</description>
  11248. <bitOffset>18</bitOffset>
  11249. <bitWidth>1</bitWidth>
  11250. </field>
  11251. <field>
  11252. <name>I2C1SEL1</name>
  11253. <description>I2C1 clock source selection
  11254. bits</description>
  11255. <bitOffset>13</bitOffset>
  11256. <bitWidth>1</bitWidth>
  11257. </field>
  11258. <field>
  11259. <name>I2C1SEL0</name>
  11260. <description>I2C1SEL0</description>
  11261. <bitOffset>12</bitOffset>
  11262. <bitWidth>1</bitWidth>
  11263. </field>
  11264. <field>
  11265. <name>LPUART1SEL1</name>
  11266. <description>LPUART1 clock source selection
  11267. bits</description>
  11268. <bitOffset>11</bitOffset>
  11269. <bitWidth>1</bitWidth>
  11270. </field>
  11271. <field>
  11272. <name>LPUART1SEL0</name>
  11273. <description>LPUART1SEL0</description>
  11274. <bitOffset>10</bitOffset>
  11275. <bitWidth>1</bitWidth>
  11276. </field>
  11277. <field>
  11278. <name>USART2SEL1</name>
  11279. <description>USART2 clock source selection
  11280. bits</description>
  11281. <bitOffset>3</bitOffset>
  11282. <bitWidth>1</bitWidth>
  11283. </field>
  11284. <field>
  11285. <name>USART2SEL0</name>
  11286. <description>USART2SEL0</description>
  11287. <bitOffset>2</bitOffset>
  11288. <bitWidth>1</bitWidth>
  11289. </field>
  11290. <field>
  11291. <name>USART1SEL1</name>
  11292. <description>USART1 clock source selection
  11293. bits</description>
  11294. <bitOffset>1</bitOffset>
  11295. <bitWidth>1</bitWidth>
  11296. </field>
  11297. <field>
  11298. <name>USART1SEL0</name>
  11299. <description>USART1SEL0</description>
  11300. <bitOffset>0</bitOffset>
  11301. <bitWidth>1</bitWidth>
  11302. </field>
  11303. </fields>
  11304. </register>
  11305. <register>
  11306. <name>CSR</name>
  11307. <displayName>CSR</displayName>
  11308. <description>Control and status register</description>
  11309. <addressOffset>0x50</addressOffset>
  11310. <size>0x20</size>
  11311. <resetValue>0x0C000000</resetValue>
  11312. <fields>
  11313. <field>
  11314. <name>LPWRSTF</name>
  11315. <description>Low-power reset flag</description>
  11316. <bitOffset>31</bitOffset>
  11317. <bitWidth>1</bitWidth>
  11318. <access>read-write</access>
  11319. </field>
  11320. <field>
  11321. <name>WWDGRSTF</name>
  11322. <description>Window watchdog reset flag</description>
  11323. <bitOffset>30</bitOffset>
  11324. <bitWidth>1</bitWidth>
  11325. <access>read-write</access>
  11326. </field>
  11327. <field>
  11328. <name>IWDGRSTF</name>
  11329. <description>Independent watchdog reset
  11330. flag</description>
  11331. <bitOffset>29</bitOffset>
  11332. <bitWidth>1</bitWidth>
  11333. <access>read-write</access>
  11334. </field>
  11335. <field>
  11336. <name>SFTRSTF</name>
  11337. <description>Software reset flag</description>
  11338. <bitOffset>28</bitOffset>
  11339. <bitWidth>1</bitWidth>
  11340. <access>read-write</access>
  11341. </field>
  11342. <field>
  11343. <name>PORRSTF</name>
  11344. <description>POR/PDR reset flag</description>
  11345. <bitOffset>27</bitOffset>
  11346. <bitWidth>1</bitWidth>
  11347. <access>read-write</access>
  11348. </field>
  11349. <field>
  11350. <name>PINRSTF</name>
  11351. <description>PIN reset flag</description>
  11352. <bitOffset>26</bitOffset>
  11353. <bitWidth>1</bitWidth>
  11354. <access>read-write</access>
  11355. </field>
  11356. <field>
  11357. <name>OBLRSTF</name>
  11358. <description>OBLRSTF</description>
  11359. <bitOffset>25</bitOffset>
  11360. <bitWidth>1</bitWidth>
  11361. <access>read-write</access>
  11362. </field>
  11363. <field>
  11364. <name>RMVF</name>
  11365. <description>Remove reset flag</description>
  11366. <bitOffset>24</bitOffset>
  11367. <bitWidth>1</bitWidth>
  11368. <access>read-write</access>
  11369. </field>
  11370. <field>
  11371. <name>RTCRST</name>
  11372. <description>RTC software reset bit</description>
  11373. <bitOffset>19</bitOffset>
  11374. <bitWidth>1</bitWidth>
  11375. <access>read-write</access>
  11376. </field>
  11377. <field>
  11378. <name>RTCEN</name>
  11379. <description>RTC clock enable bit</description>
  11380. <bitOffset>18</bitOffset>
  11381. <bitWidth>1</bitWidth>
  11382. <access>read-write</access>
  11383. </field>
  11384. <field>
  11385. <name>RTCSEL</name>
  11386. <description>RTC and LCD clock source selection
  11387. bits</description>
  11388. <bitOffset>16</bitOffset>
  11389. <bitWidth>2</bitWidth>
  11390. <access>read-write</access>
  11391. </field>
  11392. <field>
  11393. <name>CSSLSED</name>
  11394. <description>CSS on LSE failure detection
  11395. flag</description>
  11396. <bitOffset>14</bitOffset>
  11397. <bitWidth>1</bitWidth>
  11398. <access>read-write</access>
  11399. </field>
  11400. <field>
  11401. <name>CSSLSEON</name>
  11402. <description>CSSLSEON</description>
  11403. <bitOffset>13</bitOffset>
  11404. <bitWidth>1</bitWidth>
  11405. <access>read-write</access>
  11406. </field>
  11407. <field>
  11408. <name>LSEDRV</name>
  11409. <description>LSEDRV</description>
  11410. <bitOffset>11</bitOffset>
  11411. <bitWidth>2</bitWidth>
  11412. <access>read-write</access>
  11413. </field>
  11414. <field>
  11415. <name>LSEBYP</name>
  11416. <description>External low-speed oscillator bypass
  11417. bit</description>
  11418. <bitOffset>10</bitOffset>
  11419. <bitWidth>1</bitWidth>
  11420. <access>read-write</access>
  11421. </field>
  11422. <field>
  11423. <name>LSERDY</name>
  11424. <description>External low-speed oscillator ready
  11425. bit</description>
  11426. <bitOffset>9</bitOffset>
  11427. <bitWidth>1</bitWidth>
  11428. <access>read-only</access>
  11429. </field>
  11430. <field>
  11431. <name>LSEON</name>
  11432. <description>External low-speed oscillator enable
  11433. bit</description>
  11434. <bitOffset>8</bitOffset>
  11435. <bitWidth>1</bitWidth>
  11436. <access>read-write</access>
  11437. </field>
  11438. <field>
  11439. <name>LSIRDY</name>
  11440. <description>Internal low-speed oscillator ready
  11441. bit</description>
  11442. <bitOffset>1</bitOffset>
  11443. <bitWidth>1</bitWidth>
  11444. <access>read-write</access>
  11445. </field>
  11446. <field>
  11447. <name>LSION</name>
  11448. <description>Internal low-speed oscillator
  11449. enable</description>
  11450. <bitOffset>0</bitOffset>
  11451. <bitWidth>1</bitWidth>
  11452. <access>read-write</access>
  11453. </field>
  11454. </fields>
  11455. </register>
  11456. </registers>
  11457. </peripheral>
  11458. <peripheral>
  11459. <name>SYSCFG</name>
  11460. <description>System configuration controller</description>
  11461. <groupName>SYSCFG</groupName>
  11462. <baseAddress>0x40010000</baseAddress>
  11463. <addressBlock>
  11464. <offset>0x0</offset>
  11465. <size>0x400</size>
  11466. <usage>registers</usage>
  11467. </addressBlock>
  11468. <registers>
  11469. <register>
  11470. <name>CFGR1</name>
  11471. <displayName>CFGR1</displayName>
  11472. <description>SYSCFG configuration register
  11473. 1</description>
  11474. <addressOffset>0x0</addressOffset>
  11475. <size>0x20</size>
  11476. <resetValue>0x00000000</resetValue>
  11477. <fields>
  11478. <field>
  11479. <name>BOOT_MODE</name>
  11480. <description>Boot mode selected by the boot pins
  11481. status bits</description>
  11482. <bitOffset>8</bitOffset>
  11483. <bitWidth>2</bitWidth>
  11484. <access>read-only</access>
  11485. </field>
  11486. <field>
  11487. <name>MEM_MODE</name>
  11488. <description>Memory mapping selection
  11489. bits</description>
  11490. <bitOffset>0</bitOffset>
  11491. <bitWidth>2</bitWidth>
  11492. <access>read-write</access>
  11493. </field>
  11494. </fields>
  11495. </register>
  11496. <register>
  11497. <name>CFGR2</name>
  11498. <displayName>CFGR2</displayName>
  11499. <description>SYSCFG configuration register
  11500. 2</description>
  11501. <addressOffset>0x4</addressOffset>
  11502. <size>0x20</size>
  11503. <access>read-write</access>
  11504. <resetValue>0x00000000</resetValue>
  11505. <fields>
  11506. <field>
  11507. <name>I2C2_FMP</name>
  11508. <description>I2C2 Fm+ drive capability enable
  11509. bit</description>
  11510. <bitOffset>13</bitOffset>
  11511. <bitWidth>1</bitWidth>
  11512. </field>
  11513. <field>
  11514. <name>I2C1_FMP</name>
  11515. <description>I2C1 Fm+ drive capability enable
  11516. bit</description>
  11517. <bitOffset>12</bitOffset>
  11518. <bitWidth>1</bitWidth>
  11519. </field>
  11520. <field>
  11521. <name>I2C_PB9_FMP</name>
  11522. <description>Fm+ drive capability on PB9 enable
  11523. bit</description>
  11524. <bitOffset>11</bitOffset>
  11525. <bitWidth>1</bitWidth>
  11526. </field>
  11527. <field>
  11528. <name>I2C_PB8_FMP</name>
  11529. <description>Fm+ drive capability on PB8 enable
  11530. bit</description>
  11531. <bitOffset>10</bitOffset>
  11532. <bitWidth>1</bitWidth>
  11533. </field>
  11534. <field>
  11535. <name>I2C_PB7_FMP</name>
  11536. <description>Fm+ drive capability on PB7 enable
  11537. bit</description>
  11538. <bitOffset>9</bitOffset>
  11539. <bitWidth>1</bitWidth>
  11540. </field>
  11541. <field>
  11542. <name>I2C_PB6_FMP</name>
  11543. <description>Fm+ drive capability on PB6 enable
  11544. bit</description>
  11545. <bitOffset>8</bitOffset>
  11546. <bitWidth>1</bitWidth>
  11547. </field>
  11548. <field>
  11549. <name>CAPA</name>
  11550. <description>Configuration of internal VLCD rail
  11551. connection to optional external
  11552. capacitor</description>
  11553. <bitOffset>1</bitOffset>
  11554. <bitWidth>3</bitWidth>
  11555. </field>
  11556. <field>
  11557. <name>FWDISEN</name>
  11558. <description>Firewall disable bit</description>
  11559. <bitOffset>0</bitOffset>
  11560. <bitWidth>1</bitWidth>
  11561. </field>
  11562. </fields>
  11563. </register>
  11564. <register>
  11565. <name>EXTICR1</name>
  11566. <displayName>EXTICR1</displayName>
  11567. <description>external interrupt configuration register
  11568. 1</description>
  11569. <addressOffset>0x8</addressOffset>
  11570. <size>0x20</size>
  11571. <access>read-write</access>
  11572. <resetValue>0x0000</resetValue>
  11573. <fields>
  11574. <field>
  11575. <name>EXTI3</name>
  11576. <description>EXTI x configuration (x = 0 to
  11577. 3)</description>
  11578. <bitOffset>12</bitOffset>
  11579. <bitWidth>4</bitWidth>
  11580. </field>
  11581. <field>
  11582. <name>EXTI2</name>
  11583. <description>EXTI x configuration (x = 0 to
  11584. 3)</description>
  11585. <bitOffset>8</bitOffset>
  11586. <bitWidth>4</bitWidth>
  11587. </field>
  11588. <field>
  11589. <name>EXTI1</name>
  11590. <description>EXTI x configuration (x = 0 to
  11591. 3)</description>
  11592. <bitOffset>4</bitOffset>
  11593. <bitWidth>4</bitWidth>
  11594. </field>
  11595. <field>
  11596. <name>EXTI0</name>
  11597. <description>EXTI x configuration (x = 0 to
  11598. 3)</description>
  11599. <bitOffset>0</bitOffset>
  11600. <bitWidth>4</bitWidth>
  11601. </field>
  11602. </fields>
  11603. </register>
  11604. <register>
  11605. <name>EXTICR2</name>
  11606. <displayName>EXTICR2</displayName>
  11607. <description>external interrupt configuration register
  11608. 2</description>
  11609. <addressOffset>0xC</addressOffset>
  11610. <size>0x20</size>
  11611. <access>read-write</access>
  11612. <resetValue>0x0000</resetValue>
  11613. <fields>
  11614. <field>
  11615. <name>EXTI7</name>
  11616. <description>EXTI x configuration (x = 4 to
  11617. 7)</description>
  11618. <bitOffset>12</bitOffset>
  11619. <bitWidth>4</bitWidth>
  11620. </field>
  11621. <field>
  11622. <name>EXTI6</name>
  11623. <description>EXTI x configuration (x = 4 to
  11624. 7)</description>
  11625. <bitOffset>8</bitOffset>
  11626. <bitWidth>4</bitWidth>
  11627. </field>
  11628. <field>
  11629. <name>EXTI5</name>
  11630. <description>EXTI x configuration (x = 4 to
  11631. 7)</description>
  11632. <bitOffset>4</bitOffset>
  11633. <bitWidth>4</bitWidth>
  11634. </field>
  11635. <field>
  11636. <name>EXTI4</name>
  11637. <description>EXTI x configuration (x = 4 to
  11638. 7)</description>
  11639. <bitOffset>0</bitOffset>
  11640. <bitWidth>4</bitWidth>
  11641. </field>
  11642. </fields>
  11643. </register>
  11644. <register>
  11645. <name>EXTICR3</name>
  11646. <displayName>EXTICR3</displayName>
  11647. <description>external interrupt configuration register
  11648. 3</description>
  11649. <addressOffset>0x10</addressOffset>
  11650. <size>0x20</size>
  11651. <access>read-write</access>
  11652. <resetValue>0x0000</resetValue>
  11653. <fields>
  11654. <field>
  11655. <name>EXTI11</name>
  11656. <description>EXTI x configuration (x = 8 to
  11657. 11)</description>
  11658. <bitOffset>12</bitOffset>
  11659. <bitWidth>4</bitWidth>
  11660. </field>
  11661. <field>
  11662. <name>EXTI10</name>
  11663. <description>EXTI10</description>
  11664. <bitOffset>8</bitOffset>
  11665. <bitWidth>4</bitWidth>
  11666. </field>
  11667. <field>
  11668. <name>EXTI9</name>
  11669. <description>EXTI x configuration (x = 8 to
  11670. 11)</description>
  11671. <bitOffset>4</bitOffset>
  11672. <bitWidth>4</bitWidth>
  11673. </field>
  11674. <field>
  11675. <name>EXTI8</name>
  11676. <description>EXTI x configuration (x = 8 to
  11677. 11)</description>
  11678. <bitOffset>0</bitOffset>
  11679. <bitWidth>4</bitWidth>
  11680. </field>
  11681. </fields>
  11682. </register>
  11683. <register>
  11684. <name>EXTICR4</name>
  11685. <displayName>EXTICR4</displayName>
  11686. <description>external interrupt configuration register
  11687. 4</description>
  11688. <addressOffset>0x14</addressOffset>
  11689. <size>0x20</size>
  11690. <access>read-write</access>
  11691. <resetValue>0x0000</resetValue>
  11692. <fields>
  11693. <field>
  11694. <name>EXTI15</name>
  11695. <description>EXTI x configuration (x = 12 to
  11696. 15)</description>
  11697. <bitOffset>12</bitOffset>
  11698. <bitWidth>4</bitWidth>
  11699. </field>
  11700. <field>
  11701. <name>EXTI14</name>
  11702. <description>EXTI14</description>
  11703. <bitOffset>8</bitOffset>
  11704. <bitWidth>4</bitWidth>
  11705. </field>
  11706. <field>
  11707. <name>EXTI13</name>
  11708. <description>EXTI13</description>
  11709. <bitOffset>4</bitOffset>
  11710. <bitWidth>4</bitWidth>
  11711. </field>
  11712. <field>
  11713. <name>EXTI12</name>
  11714. <description>EXTI12</description>
  11715. <bitOffset>0</bitOffset>
  11716. <bitWidth>4</bitWidth>
  11717. </field>
  11718. </fields>
  11719. </register>
  11720. <register>
  11721. <name>CFGR3</name>
  11722. <displayName>CFGR3</displayName>
  11723. <description>SYSCFG configuration register
  11724. 3</description>
  11725. <addressOffset>0x20</addressOffset>
  11726. <size>0x20</size>
  11727. <resetValue>0x00000000</resetValue>
  11728. <fields>
  11729. <field>
  11730. <name>REF_LOCK</name>
  11731. <description>REF_CTRL lock bit</description>
  11732. <bitOffset>31</bitOffset>
  11733. <bitWidth>1</bitWidth>
  11734. <access>write-only</access>
  11735. </field>
  11736. <field>
  11737. <name>VREFINT_RDYF</name>
  11738. <description>VREFINT ready flag</description>
  11739. <bitOffset>30</bitOffset>
  11740. <bitWidth>1</bitWidth>
  11741. <access>read-only</access>
  11742. </field>
  11743. <field>
  11744. <name>VREFINT_COMP_RDYF</name>
  11745. <description>VREFINT for comparator ready
  11746. flag</description>
  11747. <bitOffset>29</bitOffset>
  11748. <bitWidth>1</bitWidth>
  11749. <access>read-only</access>
  11750. </field>
  11751. <field>
  11752. <name>VREFINT_ADC_RDYF</name>
  11753. <description>VREFINT for ADC ready flag</description>
  11754. <bitOffset>28</bitOffset>
  11755. <bitWidth>1</bitWidth>
  11756. <access>read-only</access>
  11757. </field>
  11758. <field>
  11759. <name>SENSOR_ADC_RDYF</name>
  11760. <description>Sensor for ADC ready flag</description>
  11761. <bitOffset>27</bitOffset>
  11762. <bitWidth>1</bitWidth>
  11763. <access>read-only</access>
  11764. </field>
  11765. <field>
  11766. <name>REF_RC48MHz_RDYF</name>
  11767. <description>VREFINT for 48 MHz RC oscillator ready
  11768. flag</description>
  11769. <bitOffset>26</bitOffset>
  11770. <bitWidth>1</bitWidth>
  11771. <access>read-only</access>
  11772. </field>
  11773. <field>
  11774. <name>ENREF_RC48MHz</name>
  11775. <description>VREFINT reference for 48 MHz RC
  11776. oscillator enable bit</description>
  11777. <bitOffset>13</bitOffset>
  11778. <bitWidth>1</bitWidth>
  11779. <access>read-write</access>
  11780. </field>
  11781. <field>
  11782. <name>ENBUF_VREFINT_COMP</name>
  11783. <description>VREFINT reference for comparator 2
  11784. enable bit</description>
  11785. <bitOffset>12</bitOffset>
  11786. <bitWidth>1</bitWidth>
  11787. <access>read-write</access>
  11788. </field>
  11789. <field>
  11790. <name>ENBUF_SENSOR_ADC</name>
  11791. <description>Sensor reference for ADC enable
  11792. bit</description>
  11793. <bitOffset>9</bitOffset>
  11794. <bitWidth>1</bitWidth>
  11795. <access>read-write</access>
  11796. </field>
  11797. <field>
  11798. <name>ENBUF_BGAP_ADC</name>
  11799. <description>VREFINT reference for ADC enable
  11800. bit</description>
  11801. <bitOffset>8</bitOffset>
  11802. <bitWidth>1</bitWidth>
  11803. <access>read-write</access>
  11804. </field>
  11805. <field>
  11806. <name>SEL_VREF_OUT</name>
  11807. <description>BGAP_ADC connection bit</description>
  11808. <bitOffset>4</bitOffset>
  11809. <bitWidth>2</bitWidth>
  11810. <access>read-write</access>
  11811. </field>
  11812. <field>
  11813. <name>EN_BGAP</name>
  11814. <description>Vref Enable bit</description>
  11815. <bitOffset>0</bitOffset>
  11816. <bitWidth>1</bitWidth>
  11817. <access>read-write</access>
  11818. </field>
  11819. </fields>
  11820. </register>
  11821. </registers>
  11822. </peripheral>
  11823. <peripheral>
  11824. <name>SPI1</name>
  11825. <description>Serial peripheral interface</description>
  11826. <groupName>SPI</groupName>
  11827. <baseAddress>0x40013000</baseAddress>
  11828. <addressBlock>
  11829. <offset>0x0</offset>
  11830. <size>0x400</size>
  11831. <usage>registers</usage>
  11832. </addressBlock>
  11833. <interrupt>
  11834. <name>SPI1</name>
  11835. <description>SPI1_global_interrupt</description>
  11836. <value>25</value>
  11837. </interrupt>
  11838. <registers>
  11839. <register>
  11840. <name>CR1</name>
  11841. <displayName>CR1</displayName>
  11842. <description>control register 1</description>
  11843. <addressOffset>0x0</addressOffset>
  11844. <size>0x20</size>
  11845. <access>read-write</access>
  11846. <resetValue>0x0000</resetValue>
  11847. <fields>
  11848. <field>
  11849. <name>BIDIMODE</name>
  11850. <description>Bidirectional data mode
  11851. enable</description>
  11852. <bitOffset>15</bitOffset>
  11853. <bitWidth>1</bitWidth>
  11854. </field>
  11855. <field>
  11856. <name>BIDIOE</name>
  11857. <description>Output enable in bidirectional
  11858. mode</description>
  11859. <bitOffset>14</bitOffset>
  11860. <bitWidth>1</bitWidth>
  11861. </field>
  11862. <field>
  11863. <name>CRCEN</name>
  11864. <description>Hardware CRC calculation
  11865. enable</description>
  11866. <bitOffset>13</bitOffset>
  11867. <bitWidth>1</bitWidth>
  11868. </field>
  11869. <field>
  11870. <name>CRCNEXT</name>
  11871. <description>CRC transfer next</description>
  11872. <bitOffset>12</bitOffset>
  11873. <bitWidth>1</bitWidth>
  11874. </field>
  11875. <field>
  11876. <name>DFF</name>
  11877. <description>Data frame format</description>
  11878. <bitOffset>11</bitOffset>
  11879. <bitWidth>1</bitWidth>
  11880. </field>
  11881. <field>
  11882. <name>RXONLY</name>
  11883. <description>Receive only</description>
  11884. <bitOffset>10</bitOffset>
  11885. <bitWidth>1</bitWidth>
  11886. </field>
  11887. <field>
  11888. <name>SSM</name>
  11889. <description>Software slave management</description>
  11890. <bitOffset>9</bitOffset>
  11891. <bitWidth>1</bitWidth>
  11892. </field>
  11893. <field>
  11894. <name>SSI</name>
  11895. <description>Internal slave select</description>
  11896. <bitOffset>8</bitOffset>
  11897. <bitWidth>1</bitWidth>
  11898. </field>
  11899. <field>
  11900. <name>LSBFIRST</name>
  11901. <description>Frame format</description>
  11902. <bitOffset>7</bitOffset>
  11903. <bitWidth>1</bitWidth>
  11904. </field>
  11905. <field>
  11906. <name>SPE</name>
  11907. <description>SPI enable</description>
  11908. <bitOffset>6</bitOffset>
  11909. <bitWidth>1</bitWidth>
  11910. </field>
  11911. <field>
  11912. <name>BR</name>
  11913. <description>Baud rate control</description>
  11914. <bitOffset>3</bitOffset>
  11915. <bitWidth>3</bitWidth>
  11916. </field>
  11917. <field>
  11918. <name>MSTR</name>
  11919. <description>Master selection</description>
  11920. <bitOffset>2</bitOffset>
  11921. <bitWidth>1</bitWidth>
  11922. </field>
  11923. <field>
  11924. <name>CPOL</name>
  11925. <description>Clock polarity</description>
  11926. <bitOffset>1</bitOffset>
  11927. <bitWidth>1</bitWidth>
  11928. </field>
  11929. <field>
  11930. <name>CPHA</name>
  11931. <description>Clock phase</description>
  11932. <bitOffset>0</bitOffset>
  11933. <bitWidth>1</bitWidth>
  11934. </field>
  11935. </fields>
  11936. </register>
  11937. <register>
  11938. <name>CR2</name>
  11939. <displayName>CR2</displayName>
  11940. <description>control register 2</description>
  11941. <addressOffset>0x4</addressOffset>
  11942. <size>0x20</size>
  11943. <access>read-write</access>
  11944. <resetValue>0x0000</resetValue>
  11945. <fields>
  11946. <field>
  11947. <name>RXDMAEN</name>
  11948. <description>Rx buffer DMA enable</description>
  11949. <bitOffset>0</bitOffset>
  11950. <bitWidth>1</bitWidth>
  11951. </field>
  11952. <field>
  11953. <name>TXDMAEN</name>
  11954. <description>Tx buffer DMA enable</description>
  11955. <bitOffset>1</bitOffset>
  11956. <bitWidth>1</bitWidth>
  11957. </field>
  11958. <field>
  11959. <name>SSOE</name>
  11960. <description>SS output enable</description>
  11961. <bitOffset>2</bitOffset>
  11962. <bitWidth>1</bitWidth>
  11963. </field>
  11964. <field>
  11965. <name>FRF</name>
  11966. <description>Frame format</description>
  11967. <bitOffset>4</bitOffset>
  11968. <bitWidth>1</bitWidth>
  11969. </field>
  11970. <field>
  11971. <name>ERRIE</name>
  11972. <description>Error interrupt enable</description>
  11973. <bitOffset>5</bitOffset>
  11974. <bitWidth>1</bitWidth>
  11975. </field>
  11976. <field>
  11977. <name>RXNEIE</name>
  11978. <description>RX buffer not empty interrupt
  11979. enable</description>
  11980. <bitOffset>6</bitOffset>
  11981. <bitWidth>1</bitWidth>
  11982. </field>
  11983. <field>
  11984. <name>TXEIE</name>
  11985. <description>Tx buffer empty interrupt
  11986. enable</description>
  11987. <bitOffset>7</bitOffset>
  11988. <bitWidth>1</bitWidth>
  11989. </field>
  11990. </fields>
  11991. </register>
  11992. <register>
  11993. <name>SR</name>
  11994. <displayName>SR</displayName>
  11995. <description>status register</description>
  11996. <addressOffset>0x8</addressOffset>
  11997. <size>0x20</size>
  11998. <resetValue>0x0002</resetValue>
  11999. <fields>
  12000. <field>
  12001. <name>RXNE</name>
  12002. <description>Receive buffer not empty</description>
  12003. <bitOffset>0</bitOffset>
  12004. <bitWidth>1</bitWidth>
  12005. <access>read-only</access>
  12006. </field>
  12007. <field>
  12008. <name>TXE</name>
  12009. <description>Transmit buffer empty</description>
  12010. <bitOffset>1</bitOffset>
  12011. <bitWidth>1</bitWidth>
  12012. <access>read-only</access>
  12013. </field>
  12014. <field>
  12015. <name>CHSIDE</name>
  12016. <description>Channel side</description>
  12017. <bitOffset>2</bitOffset>
  12018. <bitWidth>1</bitWidth>
  12019. <access>read-only</access>
  12020. </field>
  12021. <field>
  12022. <name>UDR</name>
  12023. <description>Underrun flag</description>
  12024. <bitOffset>3</bitOffset>
  12025. <bitWidth>1</bitWidth>
  12026. <access>read-only</access>
  12027. </field>
  12028. <field>
  12029. <name>CRCERR</name>
  12030. <description>CRC error flag</description>
  12031. <bitOffset>4</bitOffset>
  12032. <bitWidth>1</bitWidth>
  12033. <access>read-write</access>
  12034. </field>
  12035. <field>
  12036. <name>MODF</name>
  12037. <description>Mode fault</description>
  12038. <bitOffset>5</bitOffset>
  12039. <bitWidth>1</bitWidth>
  12040. <access>read-only</access>
  12041. </field>
  12042. <field>
  12043. <name>OVR</name>
  12044. <description>Overrun flag</description>
  12045. <bitOffset>6</bitOffset>
  12046. <bitWidth>1</bitWidth>
  12047. <access>read-only</access>
  12048. </field>
  12049. <field>
  12050. <name>BSY</name>
  12051. <description>Busy flag</description>
  12052. <bitOffset>7</bitOffset>
  12053. <bitWidth>1</bitWidth>
  12054. <access>read-only</access>
  12055. </field>
  12056. <field>
  12057. <name>TIFRFE</name>
  12058. <description>TI frame format error</description>
  12059. <bitOffset>8</bitOffset>
  12060. <bitWidth>1</bitWidth>
  12061. <access>read-only</access>
  12062. </field>
  12063. </fields>
  12064. </register>
  12065. <register>
  12066. <name>DR</name>
  12067. <displayName>DR</displayName>
  12068. <description>data register</description>
  12069. <addressOffset>0xC</addressOffset>
  12070. <size>0x20</size>
  12071. <access>read-write</access>
  12072. <resetValue>0x0000</resetValue>
  12073. <fields>
  12074. <field>
  12075. <name>DR</name>
  12076. <description>Data register</description>
  12077. <bitOffset>0</bitOffset>
  12078. <bitWidth>16</bitWidth>
  12079. </field>
  12080. </fields>
  12081. </register>
  12082. <register>
  12083. <name>CRCPR</name>
  12084. <displayName>CRCPR</displayName>
  12085. <description>CRC polynomial register</description>
  12086. <addressOffset>0x10</addressOffset>
  12087. <size>0x20</size>
  12088. <access>read-write</access>
  12089. <resetValue>0x0007</resetValue>
  12090. <fields>
  12091. <field>
  12092. <name>CRCPOLY</name>
  12093. <description>CRC polynomial register</description>
  12094. <bitOffset>0</bitOffset>
  12095. <bitWidth>16</bitWidth>
  12096. </field>
  12097. </fields>
  12098. </register>
  12099. <register>
  12100. <name>RXCRCR</name>
  12101. <displayName>RXCRCR</displayName>
  12102. <description>RX CRC register</description>
  12103. <addressOffset>0x14</addressOffset>
  12104. <size>0x20</size>
  12105. <access>read-only</access>
  12106. <resetValue>0x0000</resetValue>
  12107. <fields>
  12108. <field>
  12109. <name>RxCRC</name>
  12110. <description>Rx CRC register</description>
  12111. <bitOffset>0</bitOffset>
  12112. <bitWidth>16</bitWidth>
  12113. </field>
  12114. </fields>
  12115. </register>
  12116. <register>
  12117. <name>TXCRCR</name>
  12118. <displayName>TXCRCR</displayName>
  12119. <description>TX CRC register</description>
  12120. <addressOffset>0x18</addressOffset>
  12121. <size>0x20</size>
  12122. <access>read-only</access>
  12123. <resetValue>0x0000</resetValue>
  12124. <fields>
  12125. <field>
  12126. <name>TxCRC</name>
  12127. <description>Tx CRC register</description>
  12128. <bitOffset>0</bitOffset>
  12129. <bitWidth>16</bitWidth>
  12130. </field>
  12131. </fields>
  12132. </register>
  12133. <register>
  12134. <name>I2SCFGR</name>
  12135. <displayName>I2SCFGR</displayName>
  12136. <description>I2S configuration register</description>
  12137. <addressOffset>0x1C</addressOffset>
  12138. <size>0x20</size>
  12139. <access>read-write</access>
  12140. <resetValue>0x0000</resetValue>
  12141. <fields>
  12142. <field>
  12143. <name>I2SMOD</name>
  12144. <description>I2S mode selection</description>
  12145. <bitOffset>11</bitOffset>
  12146. <bitWidth>1</bitWidth>
  12147. </field>
  12148. <field>
  12149. <name>I2SE</name>
  12150. <description>I2S Enable</description>
  12151. <bitOffset>10</bitOffset>
  12152. <bitWidth>1</bitWidth>
  12153. </field>
  12154. <field>
  12155. <name>I2SCFG</name>
  12156. <description>I2S configuration mode</description>
  12157. <bitOffset>8</bitOffset>
  12158. <bitWidth>2</bitWidth>
  12159. </field>
  12160. <field>
  12161. <name>PCMSYNC</name>
  12162. <description>PCM frame synchronization</description>
  12163. <bitOffset>7</bitOffset>
  12164. <bitWidth>1</bitWidth>
  12165. </field>
  12166. <field>
  12167. <name>I2SSTD</name>
  12168. <description>I2S standard selection</description>
  12169. <bitOffset>4</bitOffset>
  12170. <bitWidth>2</bitWidth>
  12171. </field>
  12172. <field>
  12173. <name>CKPOL</name>
  12174. <description>Steady state clock
  12175. polarity</description>
  12176. <bitOffset>3</bitOffset>
  12177. <bitWidth>1</bitWidth>
  12178. </field>
  12179. <field>
  12180. <name>DATLEN</name>
  12181. <description>Data length to be
  12182. transferred</description>
  12183. <bitOffset>1</bitOffset>
  12184. <bitWidth>2</bitWidth>
  12185. </field>
  12186. <field>
  12187. <name>CHLEN</name>
  12188. <description>Channel length (number of bits per audio
  12189. channel)</description>
  12190. <bitOffset>0</bitOffset>
  12191. <bitWidth>1</bitWidth>
  12192. </field>
  12193. </fields>
  12194. </register>
  12195. <register>
  12196. <name>I2SPR</name>
  12197. <displayName>I2SPR</displayName>
  12198. <description>I2S prescaler register</description>
  12199. <addressOffset>0x20</addressOffset>
  12200. <size>0x20</size>
  12201. <access>read-write</access>
  12202. <resetValue>0x00000010</resetValue>
  12203. <fields>
  12204. <field>
  12205. <name>MCKOE</name>
  12206. <description>Master clock output enable</description>
  12207. <bitOffset>9</bitOffset>
  12208. <bitWidth>1</bitWidth>
  12209. </field>
  12210. <field>
  12211. <name>ODD</name>
  12212. <description>Odd factor for the
  12213. prescaler</description>
  12214. <bitOffset>8</bitOffset>
  12215. <bitWidth>1</bitWidth>
  12216. </field>
  12217. <field>
  12218. <name>I2SDIV</name>
  12219. <description>I2S Linear prescaler</description>
  12220. <bitOffset>0</bitOffset>
  12221. <bitWidth>8</bitWidth>
  12222. </field>
  12223. </fields>
  12224. </register>
  12225. </registers>
  12226. </peripheral>
  12227. <peripheral derivedFrom="SPI1">
  12228. <name>SPI2</name>
  12229. <baseAddress>0x40003800</baseAddress>
  12230. <interrupt>
  12231. <name>SPI2</name>
  12232. <description>SPI2 global interrupt</description>
  12233. <value>26</value>
  12234. </interrupt>
  12235. </peripheral>
  12236. <peripheral>
  12237. <name>I2C1</name>
  12238. <description>Inter-integrated circuit</description>
  12239. <groupName>I2C</groupName>
  12240. <baseAddress>0x40005400</baseAddress>
  12241. <addressBlock>
  12242. <offset>0x0</offset>
  12243. <size>0x400</size>
  12244. <usage>registers</usage>
  12245. </addressBlock>
  12246. <interrupt>
  12247. <name>I2C1</name>
  12248. <description>I2C1 global interrupt</description>
  12249. <value>23</value>
  12250. </interrupt>
  12251. <registers>
  12252. <register>
  12253. <name>CR1</name>
  12254. <displayName>CR1</displayName>
  12255. <description>Control register 1</description>
  12256. <addressOffset>0x0</addressOffset>
  12257. <size>0x20</size>
  12258. <access>read-write</access>
  12259. <resetValue>0x00000000</resetValue>
  12260. <fields>
  12261. <field>
  12262. <name>PE</name>
  12263. <description>Peripheral enable</description>
  12264. <bitOffset>0</bitOffset>
  12265. <bitWidth>1</bitWidth>
  12266. </field>
  12267. <field>
  12268. <name>TXIE</name>
  12269. <description>TX Interrupt enable</description>
  12270. <bitOffset>1</bitOffset>
  12271. <bitWidth>1</bitWidth>
  12272. </field>
  12273. <field>
  12274. <name>RXIE</name>
  12275. <description>RX Interrupt enable</description>
  12276. <bitOffset>2</bitOffset>
  12277. <bitWidth>1</bitWidth>
  12278. </field>
  12279. <field>
  12280. <name>ADDRIE</name>
  12281. <description>Address match interrupt enable (slave
  12282. only)</description>
  12283. <bitOffset>3</bitOffset>
  12284. <bitWidth>1</bitWidth>
  12285. </field>
  12286. <field>
  12287. <name>NACKIE</name>
  12288. <description>Not acknowledge received interrupt
  12289. enable</description>
  12290. <bitOffset>4</bitOffset>
  12291. <bitWidth>1</bitWidth>
  12292. </field>
  12293. <field>
  12294. <name>STOPIE</name>
  12295. <description>STOP detection Interrupt
  12296. enable</description>
  12297. <bitOffset>5</bitOffset>
  12298. <bitWidth>1</bitWidth>
  12299. </field>
  12300. <field>
  12301. <name>TCIE</name>
  12302. <description>Transfer Complete interrupt
  12303. enable</description>
  12304. <bitOffset>6</bitOffset>
  12305. <bitWidth>1</bitWidth>
  12306. </field>
  12307. <field>
  12308. <name>ERRIE</name>
  12309. <description>Error interrupts enable</description>
  12310. <bitOffset>7</bitOffset>
  12311. <bitWidth>1</bitWidth>
  12312. </field>
  12313. <field>
  12314. <name>DNF</name>
  12315. <description>Digital noise filter</description>
  12316. <bitOffset>8</bitOffset>
  12317. <bitWidth>4</bitWidth>
  12318. </field>
  12319. <field>
  12320. <name>ANFOFF</name>
  12321. <description>Analog noise filter OFF</description>
  12322. <bitOffset>12</bitOffset>
  12323. <bitWidth>1</bitWidth>
  12324. </field>
  12325. <field>
  12326. <name>TXDMAEN</name>
  12327. <description>DMA transmission requests
  12328. enable</description>
  12329. <bitOffset>14</bitOffset>
  12330. <bitWidth>1</bitWidth>
  12331. </field>
  12332. <field>
  12333. <name>RXDMAEN</name>
  12334. <description>DMA reception requests
  12335. enable</description>
  12336. <bitOffset>15</bitOffset>
  12337. <bitWidth>1</bitWidth>
  12338. </field>
  12339. <field>
  12340. <name>SBC</name>
  12341. <description>Slave byte control</description>
  12342. <bitOffset>16</bitOffset>
  12343. <bitWidth>1</bitWidth>
  12344. </field>
  12345. <field>
  12346. <name>NOSTRETCH</name>
  12347. <description>Clock stretching disable</description>
  12348. <bitOffset>17</bitOffset>
  12349. <bitWidth>1</bitWidth>
  12350. </field>
  12351. <field>
  12352. <name>WUPEN</name>
  12353. <description>Wakeup from STOP enable</description>
  12354. <bitOffset>18</bitOffset>
  12355. <bitWidth>1</bitWidth>
  12356. </field>
  12357. <field>
  12358. <name>GCEN</name>
  12359. <description>General call enable</description>
  12360. <bitOffset>19</bitOffset>
  12361. <bitWidth>1</bitWidth>
  12362. </field>
  12363. <field>
  12364. <name>SMBHEN</name>
  12365. <description>SMBus Host address enable</description>
  12366. <bitOffset>20</bitOffset>
  12367. <bitWidth>1</bitWidth>
  12368. </field>
  12369. <field>
  12370. <name>SMBDEN</name>
  12371. <description>SMBus Device Default address
  12372. enable</description>
  12373. <bitOffset>21</bitOffset>
  12374. <bitWidth>1</bitWidth>
  12375. </field>
  12376. <field>
  12377. <name>ALERTEN</name>
  12378. <description>SMBUS alert enable</description>
  12379. <bitOffset>22</bitOffset>
  12380. <bitWidth>1</bitWidth>
  12381. </field>
  12382. <field>
  12383. <name>PECEN</name>
  12384. <description>PEC enable</description>
  12385. <bitOffset>23</bitOffset>
  12386. <bitWidth>1</bitWidth>
  12387. </field>
  12388. </fields>
  12389. </register>
  12390. <register>
  12391. <name>CR2</name>
  12392. <displayName>CR2</displayName>
  12393. <description>Control register 2</description>
  12394. <addressOffset>0x4</addressOffset>
  12395. <size>0x20</size>
  12396. <access>read-write</access>
  12397. <resetValue>0x00000000</resetValue>
  12398. <fields>
  12399. <field>
  12400. <name>PECBYTE</name>
  12401. <description>Packet error checking byte</description>
  12402. <bitOffset>26</bitOffset>
  12403. <bitWidth>1</bitWidth>
  12404. </field>
  12405. <field>
  12406. <name>AUTOEND</name>
  12407. <description>Automatic end mode (master
  12408. mode)</description>
  12409. <bitOffset>25</bitOffset>
  12410. <bitWidth>1</bitWidth>
  12411. </field>
  12412. <field>
  12413. <name>RELOAD</name>
  12414. <description>NBYTES reload mode</description>
  12415. <bitOffset>24</bitOffset>
  12416. <bitWidth>1</bitWidth>
  12417. </field>
  12418. <field>
  12419. <name>NBYTES</name>
  12420. <description>Number of bytes</description>
  12421. <bitOffset>16</bitOffset>
  12422. <bitWidth>8</bitWidth>
  12423. </field>
  12424. <field>
  12425. <name>NACK</name>
  12426. <description>NACK generation (slave
  12427. mode)</description>
  12428. <bitOffset>15</bitOffset>
  12429. <bitWidth>1</bitWidth>
  12430. </field>
  12431. <field>
  12432. <name>STOP</name>
  12433. <description>Stop generation (master
  12434. mode)</description>
  12435. <bitOffset>14</bitOffset>
  12436. <bitWidth>1</bitWidth>
  12437. </field>
  12438. <field>
  12439. <name>START</name>
  12440. <description>Start generation</description>
  12441. <bitOffset>13</bitOffset>
  12442. <bitWidth>1</bitWidth>
  12443. </field>
  12444. <field>
  12445. <name>HEAD10R</name>
  12446. <description>10-bit address header only read
  12447. direction (master receiver mode)</description>
  12448. <bitOffset>12</bitOffset>
  12449. <bitWidth>1</bitWidth>
  12450. </field>
  12451. <field>
  12452. <name>ADD10</name>
  12453. <description>10-bit addressing mode (master
  12454. mode)</description>
  12455. <bitOffset>11</bitOffset>
  12456. <bitWidth>1</bitWidth>
  12457. </field>
  12458. <field>
  12459. <name>RD_WRN</name>
  12460. <description>Transfer direction (master
  12461. mode)</description>
  12462. <bitOffset>10</bitOffset>
  12463. <bitWidth>1</bitWidth>
  12464. </field>
  12465. <field>
  12466. <name>SADD</name>
  12467. <description>Slave address bit (master
  12468. mode)</description>
  12469. <bitOffset>0</bitOffset>
  12470. <bitWidth>10</bitWidth>
  12471. </field>
  12472. </fields>
  12473. </register>
  12474. <register>
  12475. <name>OAR1</name>
  12476. <displayName>OAR1</displayName>
  12477. <description>Own address register 1</description>
  12478. <addressOffset>0x8</addressOffset>
  12479. <size>0x20</size>
  12480. <access>read-write</access>
  12481. <resetValue>0x00000000</resetValue>
  12482. <fields>
  12483. <field>
  12484. <name>OA1</name>
  12485. <description>Interface address</description>
  12486. <bitOffset>0</bitOffset>
  12487. <bitWidth>10</bitWidth>
  12488. </field>
  12489. <field>
  12490. <name>OA1MODE</name>
  12491. <description>Own Address 1 10-bit mode</description>
  12492. <bitOffset>10</bitOffset>
  12493. <bitWidth>1</bitWidth>
  12494. </field>
  12495. <field>
  12496. <name>OA1EN</name>
  12497. <description>Own Address 1 enable</description>
  12498. <bitOffset>15</bitOffset>
  12499. <bitWidth>1</bitWidth>
  12500. </field>
  12501. </fields>
  12502. </register>
  12503. <register>
  12504. <name>OAR2</name>
  12505. <displayName>OAR2</displayName>
  12506. <description>Own address register 2</description>
  12507. <addressOffset>0xC</addressOffset>
  12508. <size>0x20</size>
  12509. <access>read-write</access>
  12510. <resetValue>0x00000000</resetValue>
  12511. <fields>
  12512. <field>
  12513. <name>OA2</name>
  12514. <description>Interface address</description>
  12515. <bitOffset>1</bitOffset>
  12516. <bitWidth>7</bitWidth>
  12517. </field>
  12518. <field>
  12519. <name>OA2MSK</name>
  12520. <description>Own Address 2 masks</description>
  12521. <bitOffset>8</bitOffset>
  12522. <bitWidth>3</bitWidth>
  12523. </field>
  12524. <field>
  12525. <name>OA2EN</name>
  12526. <description>Own Address 2 enable</description>
  12527. <bitOffset>15</bitOffset>
  12528. <bitWidth>1</bitWidth>
  12529. </field>
  12530. </fields>
  12531. </register>
  12532. <register>
  12533. <name>TIMINGR</name>
  12534. <displayName>TIMINGR</displayName>
  12535. <description>Timing register</description>
  12536. <addressOffset>0x10</addressOffset>
  12537. <size>0x20</size>
  12538. <access>read-write</access>
  12539. <resetValue>0x00000000</resetValue>
  12540. <fields>
  12541. <field>
  12542. <name>SCLL</name>
  12543. <description>SCL low period (master
  12544. mode)</description>
  12545. <bitOffset>0</bitOffset>
  12546. <bitWidth>8</bitWidth>
  12547. </field>
  12548. <field>
  12549. <name>SCLH</name>
  12550. <description>SCL high period (master
  12551. mode)</description>
  12552. <bitOffset>8</bitOffset>
  12553. <bitWidth>8</bitWidth>
  12554. </field>
  12555. <field>
  12556. <name>SDADEL</name>
  12557. <description>Data hold time</description>
  12558. <bitOffset>16</bitOffset>
  12559. <bitWidth>4</bitWidth>
  12560. </field>
  12561. <field>
  12562. <name>SCLDEL</name>
  12563. <description>Data setup time</description>
  12564. <bitOffset>20</bitOffset>
  12565. <bitWidth>4</bitWidth>
  12566. </field>
  12567. <field>
  12568. <name>PRESC</name>
  12569. <description>Timing prescaler</description>
  12570. <bitOffset>28</bitOffset>
  12571. <bitWidth>4</bitWidth>
  12572. </field>
  12573. </fields>
  12574. </register>
  12575. <register>
  12576. <name>TIMEOUTR</name>
  12577. <displayName>TIMEOUTR</displayName>
  12578. <description>Status register 1</description>
  12579. <addressOffset>0x14</addressOffset>
  12580. <size>0x20</size>
  12581. <access>read-write</access>
  12582. <resetValue>0x00000000</resetValue>
  12583. <fields>
  12584. <field>
  12585. <name>TIMEOUTA</name>
  12586. <description>Bus timeout A</description>
  12587. <bitOffset>0</bitOffset>
  12588. <bitWidth>12</bitWidth>
  12589. </field>
  12590. <field>
  12591. <name>TIDLE</name>
  12592. <description>Idle clock timeout
  12593. detection</description>
  12594. <bitOffset>12</bitOffset>
  12595. <bitWidth>1</bitWidth>
  12596. </field>
  12597. <field>
  12598. <name>TIMOUTEN</name>
  12599. <description>Clock timeout enable</description>
  12600. <bitOffset>15</bitOffset>
  12601. <bitWidth>1</bitWidth>
  12602. </field>
  12603. <field>
  12604. <name>TIMEOUTB</name>
  12605. <description>Bus timeout B</description>
  12606. <bitOffset>16</bitOffset>
  12607. <bitWidth>12</bitWidth>
  12608. </field>
  12609. <field>
  12610. <name>TEXTEN</name>
  12611. <description>Extended clock timeout
  12612. enable</description>
  12613. <bitOffset>31</bitOffset>
  12614. <bitWidth>1</bitWidth>
  12615. </field>
  12616. </fields>
  12617. </register>
  12618. <register>
  12619. <name>ISR</name>
  12620. <displayName>ISR</displayName>
  12621. <description>Interrupt and Status register</description>
  12622. <addressOffset>0x18</addressOffset>
  12623. <size>0x20</size>
  12624. <resetValue>0x00000001</resetValue>
  12625. <fields>
  12626. <field>
  12627. <name>ADDCODE</name>
  12628. <description>Address match code (Slave
  12629. mode)</description>
  12630. <bitOffset>17</bitOffset>
  12631. <bitWidth>7</bitWidth>
  12632. <access>read-only</access>
  12633. </field>
  12634. <field>
  12635. <name>DIR</name>
  12636. <description>Transfer direction (Slave
  12637. mode)</description>
  12638. <bitOffset>16</bitOffset>
  12639. <bitWidth>1</bitWidth>
  12640. <access>read-only</access>
  12641. </field>
  12642. <field>
  12643. <name>BUSY</name>
  12644. <description>Bus busy</description>
  12645. <bitOffset>15</bitOffset>
  12646. <bitWidth>1</bitWidth>
  12647. <access>read-only</access>
  12648. </field>
  12649. <field>
  12650. <name>ALERT</name>
  12651. <description>SMBus alert</description>
  12652. <bitOffset>13</bitOffset>
  12653. <bitWidth>1</bitWidth>
  12654. <access>read-only</access>
  12655. </field>
  12656. <field>
  12657. <name>TIMEOUT</name>
  12658. <description>Timeout or t_low detection
  12659. flag</description>
  12660. <bitOffset>12</bitOffset>
  12661. <bitWidth>1</bitWidth>
  12662. <access>read-only</access>
  12663. </field>
  12664. <field>
  12665. <name>PECERR</name>
  12666. <description>PEC Error in reception</description>
  12667. <bitOffset>11</bitOffset>
  12668. <bitWidth>1</bitWidth>
  12669. <access>read-only</access>
  12670. </field>
  12671. <field>
  12672. <name>OVR</name>
  12673. <description>Overrun/Underrun (slave
  12674. mode)</description>
  12675. <bitOffset>10</bitOffset>
  12676. <bitWidth>1</bitWidth>
  12677. <access>read-only</access>
  12678. </field>
  12679. <field>
  12680. <name>ARLO</name>
  12681. <description>Arbitration lost</description>
  12682. <bitOffset>9</bitOffset>
  12683. <bitWidth>1</bitWidth>
  12684. <access>read-only</access>
  12685. </field>
  12686. <field>
  12687. <name>BERR</name>
  12688. <description>Bus error</description>
  12689. <bitOffset>8</bitOffset>
  12690. <bitWidth>1</bitWidth>
  12691. <access>read-only</access>
  12692. </field>
  12693. <field>
  12694. <name>TCR</name>
  12695. <description>Transfer Complete Reload</description>
  12696. <bitOffset>7</bitOffset>
  12697. <bitWidth>1</bitWidth>
  12698. <access>read-only</access>
  12699. </field>
  12700. <field>
  12701. <name>TC</name>
  12702. <description>Transfer Complete (master
  12703. mode)</description>
  12704. <bitOffset>6</bitOffset>
  12705. <bitWidth>1</bitWidth>
  12706. <access>read-only</access>
  12707. </field>
  12708. <field>
  12709. <name>STOPF</name>
  12710. <description>Stop detection flag</description>
  12711. <bitOffset>5</bitOffset>
  12712. <bitWidth>1</bitWidth>
  12713. <access>read-only</access>
  12714. </field>
  12715. <field>
  12716. <name>NACKF</name>
  12717. <description>Not acknowledge received
  12718. flag</description>
  12719. <bitOffset>4</bitOffset>
  12720. <bitWidth>1</bitWidth>
  12721. <access>read-only</access>
  12722. </field>
  12723. <field>
  12724. <name>ADDR</name>
  12725. <description>Address matched (slave
  12726. mode)</description>
  12727. <bitOffset>3</bitOffset>
  12728. <bitWidth>1</bitWidth>
  12729. <access>read-only</access>
  12730. </field>
  12731. <field>
  12732. <name>RXNE</name>
  12733. <description>Receive data register not empty
  12734. (receivers)</description>
  12735. <bitOffset>2</bitOffset>
  12736. <bitWidth>1</bitWidth>
  12737. <access>read-only</access>
  12738. </field>
  12739. <field>
  12740. <name>TXIS</name>
  12741. <description>Transmit interrupt status
  12742. (transmitters)</description>
  12743. <bitOffset>1</bitOffset>
  12744. <bitWidth>1</bitWidth>
  12745. <access>read-write</access>
  12746. </field>
  12747. <field>
  12748. <name>TXE</name>
  12749. <description>Transmit data register empty
  12750. (transmitters)</description>
  12751. <bitOffset>0</bitOffset>
  12752. <bitWidth>1</bitWidth>
  12753. <access>read-write</access>
  12754. </field>
  12755. </fields>
  12756. </register>
  12757. <register>
  12758. <name>ICR</name>
  12759. <displayName>ICR</displayName>
  12760. <description>Interrupt clear register</description>
  12761. <addressOffset>0x1C</addressOffset>
  12762. <size>0x20</size>
  12763. <access>write-only</access>
  12764. <resetValue>0x00000000</resetValue>
  12765. <fields>
  12766. <field>
  12767. <name>ALERTCF</name>
  12768. <description>Alert flag clear</description>
  12769. <bitOffset>13</bitOffset>
  12770. <bitWidth>1</bitWidth>
  12771. </field>
  12772. <field>
  12773. <name>TIMOUTCF</name>
  12774. <description>Timeout detection flag
  12775. clear</description>
  12776. <bitOffset>12</bitOffset>
  12777. <bitWidth>1</bitWidth>
  12778. </field>
  12779. <field>
  12780. <name>PECCF</name>
  12781. <description>PEC Error flag clear</description>
  12782. <bitOffset>11</bitOffset>
  12783. <bitWidth>1</bitWidth>
  12784. </field>
  12785. <field>
  12786. <name>OVRCF</name>
  12787. <description>Overrun/Underrun flag
  12788. clear</description>
  12789. <bitOffset>10</bitOffset>
  12790. <bitWidth>1</bitWidth>
  12791. </field>
  12792. <field>
  12793. <name>ARLOCF</name>
  12794. <description>Arbitration lost flag
  12795. clear</description>
  12796. <bitOffset>9</bitOffset>
  12797. <bitWidth>1</bitWidth>
  12798. </field>
  12799. <field>
  12800. <name>BERRCF</name>
  12801. <description>Bus error flag clear</description>
  12802. <bitOffset>8</bitOffset>
  12803. <bitWidth>1</bitWidth>
  12804. </field>
  12805. <field>
  12806. <name>STOPCF</name>
  12807. <description>Stop detection flag clear</description>
  12808. <bitOffset>5</bitOffset>
  12809. <bitWidth>1</bitWidth>
  12810. </field>
  12811. <field>
  12812. <name>NACKCF</name>
  12813. <description>Not Acknowledge flag clear</description>
  12814. <bitOffset>4</bitOffset>
  12815. <bitWidth>1</bitWidth>
  12816. </field>
  12817. <field>
  12818. <name>ADDRCF</name>
  12819. <description>Address Matched flag clear</description>
  12820. <bitOffset>3</bitOffset>
  12821. <bitWidth>1</bitWidth>
  12822. </field>
  12823. </fields>
  12824. </register>
  12825. <register>
  12826. <name>PECR</name>
  12827. <displayName>PECR</displayName>
  12828. <description>PEC register</description>
  12829. <addressOffset>0x20</addressOffset>
  12830. <size>0x20</size>
  12831. <access>read-only</access>
  12832. <resetValue>0x00000000</resetValue>
  12833. <fields>
  12834. <field>
  12835. <name>PEC</name>
  12836. <description>Packet error checking
  12837. register</description>
  12838. <bitOffset>0</bitOffset>
  12839. <bitWidth>8</bitWidth>
  12840. </field>
  12841. </fields>
  12842. </register>
  12843. <register>
  12844. <name>RXDR</name>
  12845. <displayName>RXDR</displayName>
  12846. <description>Receive data register</description>
  12847. <addressOffset>0x24</addressOffset>
  12848. <size>0x20</size>
  12849. <access>read-only</access>
  12850. <resetValue>0x00000000</resetValue>
  12851. <fields>
  12852. <field>
  12853. <name>RXDATA</name>
  12854. <description>8-bit receive data</description>
  12855. <bitOffset>0</bitOffset>
  12856. <bitWidth>8</bitWidth>
  12857. </field>
  12858. </fields>
  12859. </register>
  12860. <register>
  12861. <name>TXDR</name>
  12862. <displayName>TXDR</displayName>
  12863. <description>Transmit data register</description>
  12864. <addressOffset>0x28</addressOffset>
  12865. <size>0x20</size>
  12866. <access>read-write</access>
  12867. <resetValue>0x00000000</resetValue>
  12868. <fields>
  12869. <field>
  12870. <name>TXDATA</name>
  12871. <description>8-bit transmit data</description>
  12872. <bitOffset>0</bitOffset>
  12873. <bitWidth>8</bitWidth>
  12874. </field>
  12875. </fields>
  12876. </register>
  12877. </registers>
  12878. </peripheral>
  12879. <peripheral derivedFrom="I2C1">
  12880. <name>I2C2</name>
  12881. <baseAddress>0x40005800</baseAddress>
  12882. <interrupt>
  12883. <name>I2C2</name>
  12884. <description>I2C2 global interrupt</description>
  12885. <value>24</value>
  12886. </interrupt>
  12887. </peripheral>
  12888. <peripheral>
  12889. <name>PWR</name>
  12890. <description>Power control</description>
  12891. <groupName>PWR</groupName>
  12892. <baseAddress>0x40007000</baseAddress>
  12893. <addressBlock>
  12894. <offset>0x0</offset>
  12895. <size>0x400</size>
  12896. <usage>registers</usage>
  12897. </addressBlock>
  12898. <interrupt>
  12899. <name>PVD</name>
  12900. <description>PVD through EXTI line detection</description>
  12901. <value>1</value>
  12902. </interrupt>
  12903. <registers>
  12904. <register>
  12905. <name>CR</name>
  12906. <displayName>CR</displayName>
  12907. <description>power control register</description>
  12908. <addressOffset>0x0</addressOffset>
  12909. <size>0x20</size>
  12910. <access>read-write</access>
  12911. <resetValue>0x00001000</resetValue>
  12912. <fields>
  12913. <field>
  12914. <name>LPDS</name>
  12915. <description>Low-power deep sleep</description>
  12916. <bitOffset>0</bitOffset>
  12917. <bitWidth>1</bitWidth>
  12918. </field>
  12919. <field>
  12920. <name>PDDS</name>
  12921. <description>Power down deepsleep</description>
  12922. <bitOffset>1</bitOffset>
  12923. <bitWidth>1</bitWidth>
  12924. </field>
  12925. <field>
  12926. <name>CWUF</name>
  12927. <description>Clear wakeup flag</description>
  12928. <bitOffset>2</bitOffset>
  12929. <bitWidth>1</bitWidth>
  12930. </field>
  12931. <field>
  12932. <name>CSBF</name>
  12933. <description>Clear standby flag</description>
  12934. <bitOffset>3</bitOffset>
  12935. <bitWidth>1</bitWidth>
  12936. </field>
  12937. <field>
  12938. <name>PVDE</name>
  12939. <description>Power voltage detector
  12940. enable</description>
  12941. <bitOffset>4</bitOffset>
  12942. <bitWidth>1</bitWidth>
  12943. </field>
  12944. <field>
  12945. <name>PLS</name>
  12946. <description>PVD level selection</description>
  12947. <bitOffset>5</bitOffset>
  12948. <bitWidth>3</bitWidth>
  12949. </field>
  12950. <field>
  12951. <name>DBP</name>
  12952. <description>Disable backup domain write
  12953. protection</description>
  12954. <bitOffset>8</bitOffset>
  12955. <bitWidth>1</bitWidth>
  12956. </field>
  12957. <field>
  12958. <name>ULP</name>
  12959. <description>Ultra-low-power mode</description>
  12960. <bitOffset>9</bitOffset>
  12961. <bitWidth>1</bitWidth>
  12962. </field>
  12963. <field>
  12964. <name>FWU</name>
  12965. <description>Fast wakeup</description>
  12966. <bitOffset>10</bitOffset>
  12967. <bitWidth>1</bitWidth>
  12968. </field>
  12969. <field>
  12970. <name>VOS</name>
  12971. <description>Voltage scaling range
  12972. selection</description>
  12973. <bitOffset>11</bitOffset>
  12974. <bitWidth>2</bitWidth>
  12975. </field>
  12976. <field>
  12977. <name>DS_EE_KOFF</name>
  12978. <description>Deep sleep mode with Flash memory kept
  12979. off</description>
  12980. <bitOffset>13</bitOffset>
  12981. <bitWidth>1</bitWidth>
  12982. </field>
  12983. <field>
  12984. <name>LPRUN</name>
  12985. <description>Low power run mode</description>
  12986. <bitOffset>14</bitOffset>
  12987. <bitWidth>1</bitWidth>
  12988. </field>
  12989. </fields>
  12990. </register>
  12991. <register>
  12992. <name>CSR</name>
  12993. <displayName>CSR</displayName>
  12994. <description>power control/status register</description>
  12995. <addressOffset>0x4</addressOffset>
  12996. <size>0x20</size>
  12997. <resetValue>0x00000000</resetValue>
  12998. <fields>
  12999. <field>
  13000. <name>BRE</name>
  13001. <description>Backup regulator enable</description>
  13002. <bitOffset>9</bitOffset>
  13003. <bitWidth>1</bitWidth>
  13004. <access>read-write</access>
  13005. </field>
  13006. <field>
  13007. <name>EWUP</name>
  13008. <description>Enable WKUP pin</description>
  13009. <bitOffset>8</bitOffset>
  13010. <bitWidth>1</bitWidth>
  13011. <access>read-write</access>
  13012. </field>
  13013. <field>
  13014. <name>BRR</name>
  13015. <description>Backup regulator ready</description>
  13016. <bitOffset>3</bitOffset>
  13017. <bitWidth>1</bitWidth>
  13018. <access>read-only</access>
  13019. </field>
  13020. <field>
  13021. <name>PVDO</name>
  13022. <description>PVD output</description>
  13023. <bitOffset>2</bitOffset>
  13024. <bitWidth>1</bitWidth>
  13025. <access>read-only</access>
  13026. </field>
  13027. <field>
  13028. <name>SBF</name>
  13029. <description>Standby flag</description>
  13030. <bitOffset>1</bitOffset>
  13031. <bitWidth>1</bitWidth>
  13032. <access>read-only</access>
  13033. </field>
  13034. <field>
  13035. <name>WUF</name>
  13036. <description>Wakeup flag</description>
  13037. <bitOffset>0</bitOffset>
  13038. <bitWidth>1</bitWidth>
  13039. <access>read-only</access>
  13040. </field>
  13041. <field>
  13042. <name>VOSF</name>
  13043. <description>Voltage Scaling select
  13044. flag</description>
  13045. <bitOffset>4</bitOffset>
  13046. <bitWidth>1</bitWidth>
  13047. <access>read-only</access>
  13048. </field>
  13049. <field>
  13050. <name>REGLPF</name>
  13051. <description>Regulator LP flag</description>
  13052. <bitOffset>5</bitOffset>
  13053. <bitWidth>1</bitWidth>
  13054. <access>read-only</access>
  13055. </field>
  13056. </fields>
  13057. </register>
  13058. </registers>
  13059. </peripheral>
  13060. <peripheral>
  13061. <name>Flash</name>
  13062. <description>Flash</description>
  13063. <groupName>Flash</groupName>
  13064. <baseAddress>0x40022000</baseAddress>
  13065. <addressBlock>
  13066. <offset>0x0</offset>
  13067. <size>0x400</size>
  13068. <usage>registers</usage>
  13069. </addressBlock>
  13070. <interrupt>
  13071. <name>FLASH</name>
  13072. <description>Flash global interrupt</description>
  13073. <value>3</value>
  13074. </interrupt>
  13075. <registers>
  13076. <register>
  13077. <name>ACR</name>
  13078. <displayName>ACR</displayName>
  13079. <description>Access control register</description>
  13080. <addressOffset>0x0</addressOffset>
  13081. <size>0x20</size>
  13082. <access>read-write</access>
  13083. <resetValue>0x00000000</resetValue>
  13084. <fields>
  13085. <field>
  13086. <name>LATENCY</name>
  13087. <description>Latency</description>
  13088. <bitOffset>0</bitOffset>
  13089. <bitWidth>1</bitWidth>
  13090. </field>
  13091. <field>
  13092. <name>PRFTEN</name>
  13093. <description>Prefetch enable</description>
  13094. <bitOffset>1</bitOffset>
  13095. <bitWidth>1</bitWidth>
  13096. </field>
  13097. <field>
  13098. <name>SLEEP_PD</name>
  13099. <description>Flash mode during Sleep</description>
  13100. <bitOffset>3</bitOffset>
  13101. <bitWidth>1</bitWidth>
  13102. </field>
  13103. <field>
  13104. <name>RUN_PD</name>
  13105. <description>Flash mode during Run</description>
  13106. <bitOffset>4</bitOffset>
  13107. <bitWidth>1</bitWidth>
  13108. </field>
  13109. <field>
  13110. <name>DESAB_BUF</name>
  13111. <description>Disable Buffer</description>
  13112. <bitOffset>5</bitOffset>
  13113. <bitWidth>1</bitWidth>
  13114. </field>
  13115. <field>
  13116. <name>PRE_READ</name>
  13117. <description>Pre-read data address</description>
  13118. <bitOffset>6</bitOffset>
  13119. <bitWidth>1</bitWidth>
  13120. </field>
  13121. </fields>
  13122. </register>
  13123. <register>
  13124. <name>PECR</name>
  13125. <displayName>PECR</displayName>
  13126. <description>Program/erase control register</description>
  13127. <addressOffset>0x4</addressOffset>
  13128. <size>0x20</size>
  13129. <access>read-write</access>
  13130. <resetValue>0x00000007</resetValue>
  13131. <fields>
  13132. <field>
  13133. <name>PELOCK</name>
  13134. <description>FLASH_PECR and data EEPROM
  13135. lock</description>
  13136. <bitOffset>0</bitOffset>
  13137. <bitWidth>1</bitWidth>
  13138. </field>
  13139. <field>
  13140. <name>PRGLOCK</name>
  13141. <description>Program memory lock</description>
  13142. <bitOffset>1</bitOffset>
  13143. <bitWidth>1</bitWidth>
  13144. </field>
  13145. <field>
  13146. <name>OPTLOCK</name>
  13147. <description>Option bytes block lock</description>
  13148. <bitOffset>2</bitOffset>
  13149. <bitWidth>1</bitWidth>
  13150. </field>
  13151. <field>
  13152. <name>PROG</name>
  13153. <description>Program memory selection</description>
  13154. <bitOffset>3</bitOffset>
  13155. <bitWidth>1</bitWidth>
  13156. </field>
  13157. <field>
  13158. <name>DATA</name>
  13159. <description>Data EEPROM selection</description>
  13160. <bitOffset>4</bitOffset>
  13161. <bitWidth>1</bitWidth>
  13162. </field>
  13163. <field>
  13164. <name>FTDW</name>
  13165. <description>Fixed time data write for Byte, Half
  13166. Word and Word programming</description>
  13167. <bitOffset>8</bitOffset>
  13168. <bitWidth>1</bitWidth>
  13169. </field>
  13170. <field>
  13171. <name>ERASE</name>
  13172. <description>Page or Double Word erase
  13173. mode</description>
  13174. <bitOffset>9</bitOffset>
  13175. <bitWidth>1</bitWidth>
  13176. </field>
  13177. <field>
  13178. <name>FPRG</name>
  13179. <description>Half Page/Double Word programming
  13180. mode</description>
  13181. <bitOffset>10</bitOffset>
  13182. <bitWidth>1</bitWidth>
  13183. </field>
  13184. <field>
  13185. <name>PARALLELBANK</name>
  13186. <description>Parallel bank mode</description>
  13187. <bitOffset>15</bitOffset>
  13188. <bitWidth>1</bitWidth>
  13189. </field>
  13190. <field>
  13191. <name>EOPIE</name>
  13192. <description>End of programming interrupt
  13193. enable</description>
  13194. <bitOffset>16</bitOffset>
  13195. <bitWidth>1</bitWidth>
  13196. </field>
  13197. <field>
  13198. <name>ERRIE</name>
  13199. <description>Error interrupt enable</description>
  13200. <bitOffset>17</bitOffset>
  13201. <bitWidth>1</bitWidth>
  13202. </field>
  13203. <field>
  13204. <name>OBL_LAUNCH</name>
  13205. <description>Launch the option byte
  13206. loading</description>
  13207. <bitOffset>18</bitOffset>
  13208. <bitWidth>1</bitWidth>
  13209. </field>
  13210. </fields>
  13211. </register>
  13212. <register>
  13213. <name>PDKEYR</name>
  13214. <displayName>PDKEYR</displayName>
  13215. <description>Power down key register</description>
  13216. <addressOffset>0x8</addressOffset>
  13217. <size>0x20</size>
  13218. <access>write-only</access>
  13219. <resetValue>0x00000000</resetValue>
  13220. <fields>
  13221. <field>
  13222. <name>PDKEYR</name>
  13223. <description>RUN_PD in FLASH_ACR key</description>
  13224. <bitOffset>0</bitOffset>
  13225. <bitWidth>32</bitWidth>
  13226. </field>
  13227. </fields>
  13228. </register>
  13229. <register>
  13230. <name>PEKEYR</name>
  13231. <displayName>PEKEYR</displayName>
  13232. <description>Program/erase key register</description>
  13233. <addressOffset>0xC</addressOffset>
  13234. <size>0x20</size>
  13235. <access>write-only</access>
  13236. <resetValue>0x00000000</resetValue>
  13237. <fields>
  13238. <field>
  13239. <name>PEKEYR</name>
  13240. <description>FLASH_PEC and data EEPROM
  13241. key</description>
  13242. <bitOffset>0</bitOffset>
  13243. <bitWidth>32</bitWidth>
  13244. </field>
  13245. </fields>
  13246. </register>
  13247. <register>
  13248. <name>PRGKEYR</name>
  13249. <displayName>PRGKEYR</displayName>
  13250. <description>Program memory key register</description>
  13251. <addressOffset>0x10</addressOffset>
  13252. <size>0x20</size>
  13253. <access>write-only</access>
  13254. <resetValue>0x00000000</resetValue>
  13255. <fields>
  13256. <field>
  13257. <name>PRGKEYR</name>
  13258. <description>Program memory key</description>
  13259. <bitOffset>0</bitOffset>
  13260. <bitWidth>32</bitWidth>
  13261. </field>
  13262. </fields>
  13263. </register>
  13264. <register>
  13265. <name>OPTKEYR</name>
  13266. <displayName>OPTKEYR</displayName>
  13267. <description>Option byte key register</description>
  13268. <addressOffset>0x14</addressOffset>
  13269. <size>0x20</size>
  13270. <access>write-only</access>
  13271. <resetValue>0x00000000</resetValue>
  13272. <fields>
  13273. <field>
  13274. <name>OPTKEYR</name>
  13275. <description>Option byte key</description>
  13276. <bitOffset>0</bitOffset>
  13277. <bitWidth>32</bitWidth>
  13278. </field>
  13279. </fields>
  13280. </register>
  13281. <register>
  13282. <name>SR</name>
  13283. <displayName>SR</displayName>
  13284. <description>Status register</description>
  13285. <addressOffset>0x18</addressOffset>
  13286. <size>0x20</size>
  13287. <resetValue>0x00000004</resetValue>
  13288. <fields>
  13289. <field>
  13290. <name>BSY</name>
  13291. <description>Write/erase operations in
  13292. progress</description>
  13293. <bitOffset>0</bitOffset>
  13294. <bitWidth>1</bitWidth>
  13295. <access>read-only</access>
  13296. </field>
  13297. <field>
  13298. <name>EOP</name>
  13299. <description>End of operation</description>
  13300. <bitOffset>1</bitOffset>
  13301. <bitWidth>1</bitWidth>
  13302. <access>read-only</access>
  13303. </field>
  13304. <field>
  13305. <name>ENDHV</name>
  13306. <description>End of high voltage</description>
  13307. <bitOffset>2</bitOffset>
  13308. <bitWidth>1</bitWidth>
  13309. <access>read-only</access>
  13310. </field>
  13311. <field>
  13312. <name>READY</name>
  13313. <description>Flash memory module ready after low
  13314. power mode</description>
  13315. <bitOffset>3</bitOffset>
  13316. <bitWidth>1</bitWidth>
  13317. <access>read-only</access>
  13318. </field>
  13319. <field>
  13320. <name>WRPERR</name>
  13321. <description>Write protected error</description>
  13322. <bitOffset>8</bitOffset>
  13323. <bitWidth>1</bitWidth>
  13324. <access>read-write</access>
  13325. </field>
  13326. <field>
  13327. <name>PGAERR</name>
  13328. <description>Programming alignment
  13329. error</description>
  13330. <bitOffset>9</bitOffset>
  13331. <bitWidth>1</bitWidth>
  13332. <access>read-write</access>
  13333. </field>
  13334. <field>
  13335. <name>SIZERR</name>
  13336. <description>Size error</description>
  13337. <bitOffset>10</bitOffset>
  13338. <bitWidth>1</bitWidth>
  13339. <access>read-write</access>
  13340. </field>
  13341. <field>
  13342. <name>OPTVERR</name>
  13343. <description>Option validity error</description>
  13344. <bitOffset>11</bitOffset>
  13345. <bitWidth>1</bitWidth>
  13346. <access>read-write</access>
  13347. </field>
  13348. <field>
  13349. <name>RDERR</name>
  13350. <description>RDERR</description>
  13351. <bitOffset>14</bitOffset>
  13352. <bitWidth>1</bitWidth>
  13353. <access>read-write</access>
  13354. </field>
  13355. <field>
  13356. <name>NOTZEROERR</name>
  13357. <description>NOTZEROERR</description>
  13358. <bitOffset>16</bitOffset>
  13359. <bitWidth>1</bitWidth>
  13360. <access>read-write</access>
  13361. </field>
  13362. <field>
  13363. <name>FWWERR</name>
  13364. <description>FWWERR</description>
  13365. <bitOffset>17</bitOffset>
  13366. <bitWidth>1</bitWidth>
  13367. <access>read-write</access>
  13368. </field>
  13369. </fields>
  13370. </register>
  13371. <register>
  13372. <name>OBR</name>
  13373. <displayName>OBR</displayName>
  13374. <description>Option byte register</description>
  13375. <addressOffset>0x1C</addressOffset>
  13376. <size>0x20</size>
  13377. <access>read-only</access>
  13378. <resetValue>0x00F80000</resetValue>
  13379. <fields>
  13380. <field>
  13381. <name>RDPRT</name>
  13382. <description>Read protection</description>
  13383. <bitOffset>0</bitOffset>
  13384. <bitWidth>8</bitWidth>
  13385. </field>
  13386. <field>
  13387. <name>BOR_LEV</name>
  13388. <description>BOR_LEV</description>
  13389. <bitOffset>16</bitOffset>
  13390. <bitWidth>4</bitWidth>
  13391. </field>
  13392. <field>
  13393. <name>SPRMOD</name>
  13394. <description>Selection of protection mode of WPR
  13395. bits</description>
  13396. <bitOffset>8</bitOffset>
  13397. <bitWidth>1</bitWidth>
  13398. </field>
  13399. </fields>
  13400. </register>
  13401. <register>
  13402. <name>WRPR</name>
  13403. <displayName>WRPR</displayName>
  13404. <description>Write protection register</description>
  13405. <addressOffset>0x20</addressOffset>
  13406. <size>0x20</size>
  13407. <access>read-write</access>
  13408. <resetValue>0x00000000</resetValue>
  13409. <fields>
  13410. <field>
  13411. <name>WRP</name>
  13412. <description>Write protection</description>
  13413. <bitOffset>0</bitOffset>
  13414. <bitWidth>16</bitWidth>
  13415. </field>
  13416. </fields>
  13417. </register>
  13418. </registers>
  13419. </peripheral>
  13420. <peripheral>
  13421. <name>EXTI</name>
  13422. <description>External interrupt/event
  13423. controller</description>
  13424. <groupName>EXTI</groupName>
  13425. <baseAddress>0x40010400</baseAddress>
  13426. <addressBlock>
  13427. <offset>0x0</offset>
  13428. <size>0x400</size>
  13429. <usage>registers</usage>
  13430. </addressBlock>
  13431. <interrupt>
  13432. <name>EXTI0_1</name>
  13433. <description>EXTI Line[1:0] interrupts</description>
  13434. <value>5</value>
  13435. </interrupt>
  13436. <interrupt>
  13437. <name>EXTI2_3</name>
  13438. <description>EXTI Line[3:2] interrupts</description>
  13439. <value>6</value>
  13440. </interrupt>
  13441. <interrupt>
  13442. <name>EXTI4_15</name>
  13443. <description>EXTI Line15 and EXTI4 interrupts</description>
  13444. <value>7</value>
  13445. </interrupt>
  13446. <interrupt>
  13447. <name>RNG_LPUART1</name>
  13448. <description>RNG global interrupt and LPUART1 global
  13449. interrupt through</description>
  13450. <value>29</value>
  13451. </interrupt>
  13452. <registers>
  13453. <register>
  13454. <name>IMR</name>
  13455. <displayName>IMR</displayName>
  13456. <description>Interrupt mask register
  13457. (EXTI_IMR)</description>
  13458. <addressOffset>0x0</addressOffset>
  13459. <size>0x20</size>
  13460. <access>read-write</access>
  13461. <resetValue>0xFF840000</resetValue>
  13462. <fields>
  13463. <field>
  13464. <name>MR0</name>
  13465. <description>Interrupt Mask on line 0</description>
  13466. <bitOffset>0</bitOffset>
  13467. <bitWidth>1</bitWidth>
  13468. </field>
  13469. <field>
  13470. <name>MR1</name>
  13471. <description>Interrupt Mask on line 1</description>
  13472. <bitOffset>1</bitOffset>
  13473. <bitWidth>1</bitWidth>
  13474. </field>
  13475. <field>
  13476. <name>MR2</name>
  13477. <description>Interrupt Mask on line 2</description>
  13478. <bitOffset>2</bitOffset>
  13479. <bitWidth>1</bitWidth>
  13480. </field>
  13481. <field>
  13482. <name>MR3</name>
  13483. <description>Interrupt Mask on line 3</description>
  13484. <bitOffset>3</bitOffset>
  13485. <bitWidth>1</bitWidth>
  13486. </field>
  13487. <field>
  13488. <name>MR4</name>
  13489. <description>Interrupt Mask on line 4</description>
  13490. <bitOffset>4</bitOffset>
  13491. <bitWidth>1</bitWidth>
  13492. </field>
  13493. <field>
  13494. <name>MR5</name>
  13495. <description>Interrupt Mask on line 5</description>
  13496. <bitOffset>5</bitOffset>
  13497. <bitWidth>1</bitWidth>
  13498. </field>
  13499. <field>
  13500. <name>MR6</name>
  13501. <description>Interrupt Mask on line 6</description>
  13502. <bitOffset>6</bitOffset>
  13503. <bitWidth>1</bitWidth>
  13504. </field>
  13505. <field>
  13506. <name>MR7</name>
  13507. <description>Interrupt Mask on line 7</description>
  13508. <bitOffset>7</bitOffset>
  13509. <bitWidth>1</bitWidth>
  13510. </field>
  13511. <field>
  13512. <name>MR8</name>
  13513. <description>Interrupt Mask on line 8</description>
  13514. <bitOffset>8</bitOffset>
  13515. <bitWidth>1</bitWidth>
  13516. </field>
  13517. <field>
  13518. <name>MR9</name>
  13519. <description>Interrupt Mask on line 9</description>
  13520. <bitOffset>9</bitOffset>
  13521. <bitWidth>1</bitWidth>
  13522. </field>
  13523. <field>
  13524. <name>MR10</name>
  13525. <description>Interrupt Mask on line 10</description>
  13526. <bitOffset>10</bitOffset>
  13527. <bitWidth>1</bitWidth>
  13528. </field>
  13529. <field>
  13530. <name>MR11</name>
  13531. <description>Interrupt Mask on line 11</description>
  13532. <bitOffset>11</bitOffset>
  13533. <bitWidth>1</bitWidth>
  13534. </field>
  13535. <field>
  13536. <name>MR12</name>
  13537. <description>Interrupt Mask on line 12</description>
  13538. <bitOffset>12</bitOffset>
  13539. <bitWidth>1</bitWidth>
  13540. </field>
  13541. <field>
  13542. <name>MR13</name>
  13543. <description>Interrupt Mask on line 13</description>
  13544. <bitOffset>13</bitOffset>
  13545. <bitWidth>1</bitWidth>
  13546. </field>
  13547. <field>
  13548. <name>MR14</name>
  13549. <description>Interrupt Mask on line 14</description>
  13550. <bitOffset>14</bitOffset>
  13551. <bitWidth>1</bitWidth>
  13552. </field>
  13553. <field>
  13554. <name>MR15</name>
  13555. <description>Interrupt Mask on line 15</description>
  13556. <bitOffset>15</bitOffset>
  13557. <bitWidth>1</bitWidth>
  13558. </field>
  13559. <field>
  13560. <name>MR16</name>
  13561. <description>Interrupt Mask on line 16</description>
  13562. <bitOffset>16</bitOffset>
  13563. <bitWidth>1</bitWidth>
  13564. </field>
  13565. <field>
  13566. <name>MR17</name>
  13567. <description>Interrupt Mask on line 17</description>
  13568. <bitOffset>17</bitOffset>
  13569. <bitWidth>1</bitWidth>
  13570. </field>
  13571. <field>
  13572. <name>MR19</name>
  13573. <description>Interrupt Mask on line 19</description>
  13574. <bitOffset>19</bitOffset>
  13575. <bitWidth>1</bitWidth>
  13576. </field>
  13577. <field>
  13578. <name>MR21</name>
  13579. <description>Interrupt Mask on line 21</description>
  13580. <bitOffset>21</bitOffset>
  13581. <bitWidth>1</bitWidth>
  13582. </field>
  13583. <field>
  13584. <name>MR22</name>
  13585. <description>Interrupt Mask on line 22</description>
  13586. <bitOffset>22</bitOffset>
  13587. <bitWidth>1</bitWidth>
  13588. </field>
  13589. <field>
  13590. <name>MR23</name>
  13591. <description>Interrupt Mask on line 23</description>
  13592. <bitOffset>23</bitOffset>
  13593. <bitWidth>1</bitWidth>
  13594. </field>
  13595. <field>
  13596. <name>MR25</name>
  13597. <description>Interrupt Mask on line 25</description>
  13598. <bitOffset>25</bitOffset>
  13599. <bitWidth>1</bitWidth>
  13600. </field>
  13601. <field>
  13602. <name>MR27</name>
  13603. <description>Interrupt Mask on line 27</description>
  13604. <bitOffset>27</bitOffset>
  13605. <bitWidth>1</bitWidth>
  13606. </field>
  13607. </fields>
  13608. </register>
  13609. <register>
  13610. <name>EMR</name>
  13611. <displayName>EMR</displayName>
  13612. <description>Event mask register (EXTI_EMR)</description>
  13613. <addressOffset>0x4</addressOffset>
  13614. <size>0x20</size>
  13615. <access>read-write</access>
  13616. <resetValue>0x00000000</resetValue>
  13617. <fields>
  13618. <field>
  13619. <name>MR0</name>
  13620. <description>Event Mask on line 0</description>
  13621. <bitOffset>0</bitOffset>
  13622. <bitWidth>1</bitWidth>
  13623. </field>
  13624. <field>
  13625. <name>MR1</name>
  13626. <description>Event Mask on line 1</description>
  13627. <bitOffset>1</bitOffset>
  13628. <bitWidth>1</bitWidth>
  13629. </field>
  13630. <field>
  13631. <name>MR2</name>
  13632. <description>Event Mask on line 2</description>
  13633. <bitOffset>2</bitOffset>
  13634. <bitWidth>1</bitWidth>
  13635. </field>
  13636. <field>
  13637. <name>MR3</name>
  13638. <description>Event Mask on line 3</description>
  13639. <bitOffset>3</bitOffset>
  13640. <bitWidth>1</bitWidth>
  13641. </field>
  13642. <field>
  13643. <name>MR4</name>
  13644. <description>Event Mask on line 4</description>
  13645. <bitOffset>4</bitOffset>
  13646. <bitWidth>1</bitWidth>
  13647. </field>
  13648. <field>
  13649. <name>MR5</name>
  13650. <description>Event Mask on line 5</description>
  13651. <bitOffset>5</bitOffset>
  13652. <bitWidth>1</bitWidth>
  13653. </field>
  13654. <field>
  13655. <name>MR6</name>
  13656. <description>Event Mask on line 6</description>
  13657. <bitOffset>6</bitOffset>
  13658. <bitWidth>1</bitWidth>
  13659. </field>
  13660. <field>
  13661. <name>MR7</name>
  13662. <description>Event Mask on line 7</description>
  13663. <bitOffset>7</bitOffset>
  13664. <bitWidth>1</bitWidth>
  13665. </field>
  13666. <field>
  13667. <name>MR8</name>
  13668. <description>Event Mask on line 8</description>
  13669. <bitOffset>8</bitOffset>
  13670. <bitWidth>1</bitWidth>
  13671. </field>
  13672. <field>
  13673. <name>MR9</name>
  13674. <description>Event Mask on line 9</description>
  13675. <bitOffset>9</bitOffset>
  13676. <bitWidth>1</bitWidth>
  13677. </field>
  13678. <field>
  13679. <name>MR10</name>
  13680. <description>Event Mask on line 10</description>
  13681. <bitOffset>10</bitOffset>
  13682. <bitWidth>1</bitWidth>
  13683. </field>
  13684. <field>
  13685. <name>MR11</name>
  13686. <description>Event Mask on line 11</description>
  13687. <bitOffset>11</bitOffset>
  13688. <bitWidth>1</bitWidth>
  13689. </field>
  13690. <field>
  13691. <name>MR12</name>
  13692. <description>Event Mask on line 12</description>
  13693. <bitOffset>12</bitOffset>
  13694. <bitWidth>1</bitWidth>
  13695. </field>
  13696. <field>
  13697. <name>MR13</name>
  13698. <description>Event Mask on line 13</description>
  13699. <bitOffset>13</bitOffset>
  13700. <bitWidth>1</bitWidth>
  13701. </field>
  13702. <field>
  13703. <name>MR14</name>
  13704. <description>Event Mask on line 14</description>
  13705. <bitOffset>14</bitOffset>
  13706. <bitWidth>1</bitWidth>
  13707. </field>
  13708. <field>
  13709. <name>MR15</name>
  13710. <description>Event Mask on line 15</description>
  13711. <bitOffset>15</bitOffset>
  13712. <bitWidth>1</bitWidth>
  13713. </field>
  13714. <field>
  13715. <name>MR16</name>
  13716. <description>Event Mask on line 16</description>
  13717. <bitOffset>16</bitOffset>
  13718. <bitWidth>1</bitWidth>
  13719. </field>
  13720. <field>
  13721. <name>MR17</name>
  13722. <description>Event Mask on line 17</description>
  13723. <bitOffset>17</bitOffset>
  13724. <bitWidth>1</bitWidth>
  13725. </field>
  13726. <field>
  13727. <name>MR19</name>
  13728. <description>Event Mask on line 19</description>
  13729. <bitOffset>19</bitOffset>
  13730. <bitWidth>1</bitWidth>
  13731. </field>
  13732. <field>
  13733. <name>MR21</name>
  13734. <description>Event Mask on line 21</description>
  13735. <bitOffset>21</bitOffset>
  13736. <bitWidth>1</bitWidth>
  13737. </field>
  13738. <field>
  13739. <name>MR22</name>
  13740. <description>Event Mask on line 22</description>
  13741. <bitOffset>22</bitOffset>
  13742. <bitWidth>1</bitWidth>
  13743. </field>
  13744. <field>
  13745. <name>MR23</name>
  13746. <description>Event Mask on line 23</description>
  13747. <bitOffset>23</bitOffset>
  13748. <bitWidth>1</bitWidth>
  13749. </field>
  13750. <field>
  13751. <name>MR25</name>
  13752. <description>Event Mask on line 25</description>
  13753. <bitOffset>25</bitOffset>
  13754. <bitWidth>1</bitWidth>
  13755. </field>
  13756. <field>
  13757. <name>MR27</name>
  13758. <description>Event Mask on line 27</description>
  13759. <bitOffset>27</bitOffset>
  13760. <bitWidth>1</bitWidth>
  13761. </field>
  13762. </fields>
  13763. </register>
  13764. <register>
  13765. <name>RTSR</name>
  13766. <displayName>RTSR</displayName>
  13767. <description>Rising Trigger selection register
  13768. (EXTI_RTSR)</description>
  13769. <addressOffset>0x8</addressOffset>
  13770. <size>0x20</size>
  13771. <access>read-write</access>
  13772. <resetValue>0x00000000</resetValue>
  13773. <fields>
  13774. <field>
  13775. <name>TR0</name>
  13776. <description>Rising trigger event configuration of
  13777. line 0</description>
  13778. <bitOffset>0</bitOffset>
  13779. <bitWidth>1</bitWidth>
  13780. </field>
  13781. <field>
  13782. <name>TR1</name>
  13783. <description>Rising trigger event configuration of
  13784. line 1</description>
  13785. <bitOffset>1</bitOffset>
  13786. <bitWidth>1</bitWidth>
  13787. </field>
  13788. <field>
  13789. <name>TR2</name>
  13790. <description>Rising trigger event configuration of
  13791. line 2</description>
  13792. <bitOffset>2</bitOffset>
  13793. <bitWidth>1</bitWidth>
  13794. </field>
  13795. <field>
  13796. <name>TR3</name>
  13797. <description>Rising trigger event configuration of
  13798. line 3</description>
  13799. <bitOffset>3</bitOffset>
  13800. <bitWidth>1</bitWidth>
  13801. </field>
  13802. <field>
  13803. <name>TR4</name>
  13804. <description>Rising trigger event configuration of
  13805. line 4</description>
  13806. <bitOffset>4</bitOffset>
  13807. <bitWidth>1</bitWidth>
  13808. </field>
  13809. <field>
  13810. <name>TR5</name>
  13811. <description>Rising trigger event configuration of
  13812. line 5</description>
  13813. <bitOffset>5</bitOffset>
  13814. <bitWidth>1</bitWidth>
  13815. </field>
  13816. <field>
  13817. <name>TR6</name>
  13818. <description>Rising trigger event configuration of
  13819. line 6</description>
  13820. <bitOffset>6</bitOffset>
  13821. <bitWidth>1</bitWidth>
  13822. </field>
  13823. <field>
  13824. <name>TR7</name>
  13825. <description>Rising trigger event configuration of
  13826. line 7</description>
  13827. <bitOffset>7</bitOffset>
  13828. <bitWidth>1</bitWidth>
  13829. </field>
  13830. <field>
  13831. <name>TR8</name>
  13832. <description>Rising trigger event configuration of
  13833. line 8</description>
  13834. <bitOffset>8</bitOffset>
  13835. <bitWidth>1</bitWidth>
  13836. </field>
  13837. <field>
  13838. <name>TR9</name>
  13839. <description>Rising trigger event configuration of
  13840. line 9</description>
  13841. <bitOffset>9</bitOffset>
  13842. <bitWidth>1</bitWidth>
  13843. </field>
  13844. <field>
  13845. <name>TR10</name>
  13846. <description>Rising trigger event configuration of
  13847. line 10</description>
  13848. <bitOffset>10</bitOffset>
  13849. <bitWidth>1</bitWidth>
  13850. </field>
  13851. <field>
  13852. <name>TR11</name>
  13853. <description>Rising trigger event configuration of
  13854. line 11</description>
  13855. <bitOffset>11</bitOffset>
  13856. <bitWidth>1</bitWidth>
  13857. </field>
  13858. <field>
  13859. <name>TR12</name>
  13860. <description>Rising trigger event configuration of
  13861. line 12</description>
  13862. <bitOffset>12</bitOffset>
  13863. <bitWidth>1</bitWidth>
  13864. </field>
  13865. <field>
  13866. <name>TR13</name>
  13867. <description>Rising trigger event configuration of
  13868. line 13</description>
  13869. <bitOffset>13</bitOffset>
  13870. <bitWidth>1</bitWidth>
  13871. </field>
  13872. <field>
  13873. <name>TR14</name>
  13874. <description>Rising trigger event configuration of
  13875. line 14</description>
  13876. <bitOffset>14</bitOffset>
  13877. <bitWidth>1</bitWidth>
  13878. </field>
  13879. <field>
  13880. <name>TR15</name>
  13881. <description>Rising trigger event configuration of
  13882. line 15</description>
  13883. <bitOffset>15</bitOffset>
  13884. <bitWidth>1</bitWidth>
  13885. </field>
  13886. <field>
  13887. <name>TR16</name>
  13888. <description>Rising trigger event configuration of
  13889. line 16</description>
  13890. <bitOffset>16</bitOffset>
  13891. <bitWidth>1</bitWidth>
  13892. </field>
  13893. <field>
  13894. <name>TR17</name>
  13895. <description>Rising trigger event configuration of
  13896. line 17</description>
  13897. <bitOffset>17</bitOffset>
  13898. <bitWidth>1</bitWidth>
  13899. </field>
  13900. <field>
  13901. <name>TR19</name>
  13902. <description>Rising trigger event configuration of
  13903. line 19</description>
  13904. <bitOffset>19</bitOffset>
  13905. <bitWidth>1</bitWidth>
  13906. </field>
  13907. </fields>
  13908. </register>
  13909. <register>
  13910. <name>FTSR</name>
  13911. <displayName>FTSR</displayName>
  13912. <description>Falling Trigger selection register
  13913. (EXTI_FTSR)</description>
  13914. <addressOffset>0xC</addressOffset>
  13915. <size>0x20</size>
  13916. <access>read-write</access>
  13917. <resetValue>0x00000000</resetValue>
  13918. <fields>
  13919. <field>
  13920. <name>TR0</name>
  13921. <description>Falling trigger event configuration of
  13922. line 0</description>
  13923. <bitOffset>0</bitOffset>
  13924. <bitWidth>1</bitWidth>
  13925. </field>
  13926. <field>
  13927. <name>TR1</name>
  13928. <description>Falling trigger event configuration of
  13929. line 1</description>
  13930. <bitOffset>1</bitOffset>
  13931. <bitWidth>1</bitWidth>
  13932. </field>
  13933. <field>
  13934. <name>TR2</name>
  13935. <description>Falling trigger event configuration of
  13936. line 2</description>
  13937. <bitOffset>2</bitOffset>
  13938. <bitWidth>1</bitWidth>
  13939. </field>
  13940. <field>
  13941. <name>TR3</name>
  13942. <description>Falling trigger event configuration of
  13943. line 3</description>
  13944. <bitOffset>3</bitOffset>
  13945. <bitWidth>1</bitWidth>
  13946. </field>
  13947. <field>
  13948. <name>TR4</name>
  13949. <description>Falling trigger event configuration of
  13950. line 4</description>
  13951. <bitOffset>4</bitOffset>
  13952. <bitWidth>1</bitWidth>
  13953. </field>
  13954. <field>
  13955. <name>TR5</name>
  13956. <description>Falling trigger event configuration of
  13957. line 5</description>
  13958. <bitOffset>5</bitOffset>
  13959. <bitWidth>1</bitWidth>
  13960. </field>
  13961. <field>
  13962. <name>TR6</name>
  13963. <description>Falling trigger event configuration of
  13964. line 6</description>
  13965. <bitOffset>6</bitOffset>
  13966. <bitWidth>1</bitWidth>
  13967. </field>
  13968. <field>
  13969. <name>TR7</name>
  13970. <description>Falling trigger event configuration of
  13971. line 7</description>
  13972. <bitOffset>7</bitOffset>
  13973. <bitWidth>1</bitWidth>
  13974. </field>
  13975. <field>
  13976. <name>TR8</name>
  13977. <description>Falling trigger event configuration of
  13978. line 8</description>
  13979. <bitOffset>8</bitOffset>
  13980. <bitWidth>1</bitWidth>
  13981. </field>
  13982. <field>
  13983. <name>TR9</name>
  13984. <description>Falling trigger event configuration of
  13985. line 9</description>
  13986. <bitOffset>9</bitOffset>
  13987. <bitWidth>1</bitWidth>
  13988. </field>
  13989. <field>
  13990. <name>TR10</name>
  13991. <description>Falling trigger event configuration of
  13992. line 10</description>
  13993. <bitOffset>10</bitOffset>
  13994. <bitWidth>1</bitWidth>
  13995. </field>
  13996. <field>
  13997. <name>TR11</name>
  13998. <description>Falling trigger event configuration of
  13999. line 11</description>
  14000. <bitOffset>11</bitOffset>
  14001. <bitWidth>1</bitWidth>
  14002. </field>
  14003. <field>
  14004. <name>TR12</name>
  14005. <description>Falling trigger event configuration of
  14006. line 12</description>
  14007. <bitOffset>12</bitOffset>
  14008. <bitWidth>1</bitWidth>
  14009. </field>
  14010. <field>
  14011. <name>TR13</name>
  14012. <description>Falling trigger event configuration of
  14013. line 13</description>
  14014. <bitOffset>13</bitOffset>
  14015. <bitWidth>1</bitWidth>
  14016. </field>
  14017. <field>
  14018. <name>TR14</name>
  14019. <description>Falling trigger event configuration of
  14020. line 14</description>
  14021. <bitOffset>14</bitOffset>
  14022. <bitWidth>1</bitWidth>
  14023. </field>
  14024. <field>
  14025. <name>TR15</name>
  14026. <description>Falling trigger event configuration of
  14027. line 15</description>
  14028. <bitOffset>15</bitOffset>
  14029. <bitWidth>1</bitWidth>
  14030. </field>
  14031. <field>
  14032. <name>TR16</name>
  14033. <description>Falling trigger event configuration of
  14034. line 16</description>
  14035. <bitOffset>16</bitOffset>
  14036. <bitWidth>1</bitWidth>
  14037. </field>
  14038. <field>
  14039. <name>TR17</name>
  14040. <description>Falling trigger event configuration of
  14041. line 17</description>
  14042. <bitOffset>17</bitOffset>
  14043. <bitWidth>1</bitWidth>
  14044. </field>
  14045. <field>
  14046. <name>TR19</name>
  14047. <description>Falling trigger event configuration of
  14048. line 19</description>
  14049. <bitOffset>19</bitOffset>
  14050. <bitWidth>1</bitWidth>
  14051. </field>
  14052. </fields>
  14053. </register>
  14054. <register>
  14055. <name>SWIER</name>
  14056. <displayName>SWIER</displayName>
  14057. <description>Software interrupt event register
  14058. (EXTI_SWIER)</description>
  14059. <addressOffset>0x10</addressOffset>
  14060. <size>0x20</size>
  14061. <access>read-write</access>
  14062. <resetValue>0x00000000</resetValue>
  14063. <fields>
  14064. <field>
  14065. <name>SWIER0</name>
  14066. <description>Software Interrupt on line
  14067. 0</description>
  14068. <bitOffset>0</bitOffset>
  14069. <bitWidth>1</bitWidth>
  14070. </field>
  14071. <field>
  14072. <name>SWIER1</name>
  14073. <description>Software Interrupt on line
  14074. 1</description>
  14075. <bitOffset>1</bitOffset>
  14076. <bitWidth>1</bitWidth>
  14077. </field>
  14078. <field>
  14079. <name>SWIER2</name>
  14080. <description>Software Interrupt on line
  14081. 2</description>
  14082. <bitOffset>2</bitOffset>
  14083. <bitWidth>1</bitWidth>
  14084. </field>
  14085. <field>
  14086. <name>SWIER3</name>
  14087. <description>Software Interrupt on line
  14088. 3</description>
  14089. <bitOffset>3</bitOffset>
  14090. <bitWidth>1</bitWidth>
  14091. </field>
  14092. <field>
  14093. <name>SWIER4</name>
  14094. <description>Software Interrupt on line
  14095. 4</description>
  14096. <bitOffset>4</bitOffset>
  14097. <bitWidth>1</bitWidth>
  14098. </field>
  14099. <field>
  14100. <name>SWIER5</name>
  14101. <description>Software Interrupt on line
  14102. 5</description>
  14103. <bitOffset>5</bitOffset>
  14104. <bitWidth>1</bitWidth>
  14105. </field>
  14106. <field>
  14107. <name>SWIER6</name>
  14108. <description>Software Interrupt on line
  14109. 6</description>
  14110. <bitOffset>6</bitOffset>
  14111. <bitWidth>1</bitWidth>
  14112. </field>
  14113. <field>
  14114. <name>SWIER7</name>
  14115. <description>Software Interrupt on line
  14116. 7</description>
  14117. <bitOffset>7</bitOffset>
  14118. <bitWidth>1</bitWidth>
  14119. </field>
  14120. <field>
  14121. <name>SWIER8</name>
  14122. <description>Software Interrupt on line
  14123. 8</description>
  14124. <bitOffset>8</bitOffset>
  14125. <bitWidth>1</bitWidth>
  14126. </field>
  14127. <field>
  14128. <name>SWIER9</name>
  14129. <description>Software Interrupt on line
  14130. 9</description>
  14131. <bitOffset>9</bitOffset>
  14132. <bitWidth>1</bitWidth>
  14133. </field>
  14134. <field>
  14135. <name>SWIER10</name>
  14136. <description>Software Interrupt on line
  14137. 10</description>
  14138. <bitOffset>10</bitOffset>
  14139. <bitWidth>1</bitWidth>
  14140. </field>
  14141. <field>
  14142. <name>SWIER11</name>
  14143. <description>Software Interrupt on line
  14144. 11</description>
  14145. <bitOffset>11</bitOffset>
  14146. <bitWidth>1</bitWidth>
  14147. </field>
  14148. <field>
  14149. <name>SWIER12</name>
  14150. <description>Software Interrupt on line
  14151. 12</description>
  14152. <bitOffset>12</bitOffset>
  14153. <bitWidth>1</bitWidth>
  14154. </field>
  14155. <field>
  14156. <name>SWIER13</name>
  14157. <description>Software Interrupt on line
  14158. 13</description>
  14159. <bitOffset>13</bitOffset>
  14160. <bitWidth>1</bitWidth>
  14161. </field>
  14162. <field>
  14163. <name>SWIER14</name>
  14164. <description>Software Interrupt on line
  14165. 14</description>
  14166. <bitOffset>14</bitOffset>
  14167. <bitWidth>1</bitWidth>
  14168. </field>
  14169. <field>
  14170. <name>SWIER15</name>
  14171. <description>Software Interrupt on line
  14172. 15</description>
  14173. <bitOffset>15</bitOffset>
  14174. <bitWidth>1</bitWidth>
  14175. </field>
  14176. <field>
  14177. <name>SWIER16</name>
  14178. <description>Software Interrupt on line
  14179. 16</description>
  14180. <bitOffset>16</bitOffset>
  14181. <bitWidth>1</bitWidth>
  14182. </field>
  14183. <field>
  14184. <name>SWIER17</name>
  14185. <description>Software Interrupt on line
  14186. 17</description>
  14187. <bitOffset>17</bitOffset>
  14188. <bitWidth>1</bitWidth>
  14189. </field>
  14190. <field>
  14191. <name>SWIER19</name>
  14192. <description>Software Interrupt on line
  14193. 19</description>
  14194. <bitOffset>19</bitOffset>
  14195. <bitWidth>1</bitWidth>
  14196. </field>
  14197. </fields>
  14198. </register>
  14199. <register>
  14200. <name>PR</name>
  14201. <displayName>PR</displayName>
  14202. <description>Pending register (EXTI_PR)</description>
  14203. <addressOffset>0x14</addressOffset>
  14204. <size>0x20</size>
  14205. <access>read-write</access>
  14206. <resetValue>0x00000000</resetValue>
  14207. <fields>
  14208. <field>
  14209. <name>PR0</name>
  14210. <description>Pending bit 0</description>
  14211. <bitOffset>0</bitOffset>
  14212. <bitWidth>1</bitWidth>
  14213. </field>
  14214. <field>
  14215. <name>PR1</name>
  14216. <description>Pending bit 1</description>
  14217. <bitOffset>1</bitOffset>
  14218. <bitWidth>1</bitWidth>
  14219. </field>
  14220. <field>
  14221. <name>PR2</name>
  14222. <description>Pending bit 2</description>
  14223. <bitOffset>2</bitOffset>
  14224. <bitWidth>1</bitWidth>
  14225. </field>
  14226. <field>
  14227. <name>PR3</name>
  14228. <description>Pending bit 3</description>
  14229. <bitOffset>3</bitOffset>
  14230. <bitWidth>1</bitWidth>
  14231. </field>
  14232. <field>
  14233. <name>PR4</name>
  14234. <description>Pending bit 4</description>
  14235. <bitOffset>4</bitOffset>
  14236. <bitWidth>1</bitWidth>
  14237. </field>
  14238. <field>
  14239. <name>PR5</name>
  14240. <description>Pending bit 5</description>
  14241. <bitOffset>5</bitOffset>
  14242. <bitWidth>1</bitWidth>
  14243. </field>
  14244. <field>
  14245. <name>PR6</name>
  14246. <description>Pending bit 6</description>
  14247. <bitOffset>6</bitOffset>
  14248. <bitWidth>1</bitWidth>
  14249. </field>
  14250. <field>
  14251. <name>PR7</name>
  14252. <description>Pending bit 7</description>
  14253. <bitOffset>7</bitOffset>
  14254. <bitWidth>1</bitWidth>
  14255. </field>
  14256. <field>
  14257. <name>PR8</name>
  14258. <description>Pending bit 8</description>
  14259. <bitOffset>8</bitOffset>
  14260. <bitWidth>1</bitWidth>
  14261. </field>
  14262. <field>
  14263. <name>PR9</name>
  14264. <description>Pending bit 9</description>
  14265. <bitOffset>9</bitOffset>
  14266. <bitWidth>1</bitWidth>
  14267. </field>
  14268. <field>
  14269. <name>PR10</name>
  14270. <description>Pending bit 10</description>
  14271. <bitOffset>10</bitOffset>
  14272. <bitWidth>1</bitWidth>
  14273. </field>
  14274. <field>
  14275. <name>PR11</name>
  14276. <description>Pending bit 11</description>
  14277. <bitOffset>11</bitOffset>
  14278. <bitWidth>1</bitWidth>
  14279. </field>
  14280. <field>
  14281. <name>PR12</name>
  14282. <description>Pending bit 12</description>
  14283. <bitOffset>12</bitOffset>
  14284. <bitWidth>1</bitWidth>
  14285. </field>
  14286. <field>
  14287. <name>PR13</name>
  14288. <description>Pending bit 13</description>
  14289. <bitOffset>13</bitOffset>
  14290. <bitWidth>1</bitWidth>
  14291. </field>
  14292. <field>
  14293. <name>PR14</name>
  14294. <description>Pending bit 14</description>
  14295. <bitOffset>14</bitOffset>
  14296. <bitWidth>1</bitWidth>
  14297. </field>
  14298. <field>
  14299. <name>PR15</name>
  14300. <description>Pending bit 15</description>
  14301. <bitOffset>15</bitOffset>
  14302. <bitWidth>1</bitWidth>
  14303. </field>
  14304. <field>
  14305. <name>PR16</name>
  14306. <description>Pending bit 16</description>
  14307. <bitOffset>16</bitOffset>
  14308. <bitWidth>1</bitWidth>
  14309. </field>
  14310. <field>
  14311. <name>PR17</name>
  14312. <description>Pending bit 17</description>
  14313. <bitOffset>17</bitOffset>
  14314. <bitWidth>1</bitWidth>
  14315. </field>
  14316. <field>
  14317. <name>PR19</name>
  14318. <description>Pending bit 19</description>
  14319. <bitOffset>19</bitOffset>
  14320. <bitWidth>1</bitWidth>
  14321. </field>
  14322. </fields>
  14323. </register>
  14324. </registers>
  14325. </peripheral>
  14326. <peripheral>
  14327. <name>ADC</name>
  14328. <description>Analog-to-digital converter</description>
  14329. <groupName>ADC</groupName>
  14330. <baseAddress>0x40012400</baseAddress>
  14331. <addressBlock>
  14332. <offset>0x0</offset>
  14333. <size>0x400</size>
  14334. <usage>registers</usage>
  14335. </addressBlock>
  14336. <interrupt>
  14337. <name>ADC_COMP</name>
  14338. <description>ADC and comparator 1 and 2</description>
  14339. <value>12</value>
  14340. </interrupt>
  14341. <registers>
  14342. <register>
  14343. <name>ISR</name>
  14344. <displayName>ISR</displayName>
  14345. <description>interrupt and status register</description>
  14346. <addressOffset>0x0</addressOffset>
  14347. <size>0x20</size>
  14348. <access>read-write</access>
  14349. <resetValue>0x00000000</resetValue>
  14350. <fields>
  14351. <field>
  14352. <name>ADRDY</name>
  14353. <description>ADC ready</description>
  14354. <bitOffset>0</bitOffset>
  14355. <bitWidth>1</bitWidth>
  14356. </field>
  14357. <field>
  14358. <name>EOSMP</name>
  14359. <description>End of sampling flag</description>
  14360. <bitOffset>1</bitOffset>
  14361. <bitWidth>1</bitWidth>
  14362. </field>
  14363. <field>
  14364. <name>EOC</name>
  14365. <description>End of conversion flag</description>
  14366. <bitOffset>2</bitOffset>
  14367. <bitWidth>1</bitWidth>
  14368. </field>
  14369. <field>
  14370. <name>EOS</name>
  14371. <description>End of sequence flag</description>
  14372. <bitOffset>3</bitOffset>
  14373. <bitWidth>1</bitWidth>
  14374. </field>
  14375. <field>
  14376. <name>OVR</name>
  14377. <description>ADC overrun</description>
  14378. <bitOffset>4</bitOffset>
  14379. <bitWidth>1</bitWidth>
  14380. </field>
  14381. <field>
  14382. <name>AWD</name>
  14383. <description>Analog watchdog flag</description>
  14384. <bitOffset>7</bitOffset>
  14385. <bitWidth>1</bitWidth>
  14386. </field>
  14387. <field>
  14388. <name>EOCAL</name>
  14389. <description>End Of Calibration flag</description>
  14390. <bitOffset>11</bitOffset>
  14391. <bitWidth>1</bitWidth>
  14392. </field>
  14393. </fields>
  14394. </register>
  14395. <register>
  14396. <name>IER</name>
  14397. <displayName>IER</displayName>
  14398. <description>interrupt enable register</description>
  14399. <addressOffset>0x4</addressOffset>
  14400. <size>0x20</size>
  14401. <access>read-write</access>
  14402. <resetValue>0x00000000</resetValue>
  14403. <fields>
  14404. <field>
  14405. <name>ADRDYIE</name>
  14406. <description>ADC ready interrupt enable</description>
  14407. <bitOffset>0</bitOffset>
  14408. <bitWidth>1</bitWidth>
  14409. </field>
  14410. <field>
  14411. <name>EOSMPIE</name>
  14412. <description>End of sampling flag interrupt
  14413. enable</description>
  14414. <bitOffset>1</bitOffset>
  14415. <bitWidth>1</bitWidth>
  14416. </field>
  14417. <field>
  14418. <name>EOCIE</name>
  14419. <description>End of conversion interrupt
  14420. enable</description>
  14421. <bitOffset>2</bitOffset>
  14422. <bitWidth>1</bitWidth>
  14423. </field>
  14424. <field>
  14425. <name>EOSIE</name>
  14426. <description>End of conversion sequence interrupt
  14427. enable</description>
  14428. <bitOffset>3</bitOffset>
  14429. <bitWidth>1</bitWidth>
  14430. </field>
  14431. <field>
  14432. <name>OVRIE</name>
  14433. <description>Overrun interrupt enable</description>
  14434. <bitOffset>4</bitOffset>
  14435. <bitWidth>1</bitWidth>
  14436. </field>
  14437. <field>
  14438. <name>AWDIE</name>
  14439. <description>Analog watchdog interrupt
  14440. enable</description>
  14441. <bitOffset>7</bitOffset>
  14442. <bitWidth>1</bitWidth>
  14443. </field>
  14444. <field>
  14445. <name>EOCALIE</name>
  14446. <description>End of calibration interrupt
  14447. enable</description>
  14448. <bitOffset>11</bitOffset>
  14449. <bitWidth>1</bitWidth>
  14450. </field>
  14451. </fields>
  14452. </register>
  14453. <register>
  14454. <name>CR</name>
  14455. <displayName>CR</displayName>
  14456. <description>control register</description>
  14457. <addressOffset>0x8</addressOffset>
  14458. <size>0x20</size>
  14459. <access>read-write</access>
  14460. <resetValue>0x00000000</resetValue>
  14461. <fields>
  14462. <field>
  14463. <name>ADEN</name>
  14464. <description>ADC enable command</description>
  14465. <bitOffset>0</bitOffset>
  14466. <bitWidth>1</bitWidth>
  14467. </field>
  14468. <field>
  14469. <name>ADDIS</name>
  14470. <description>ADC disable command</description>
  14471. <bitOffset>1</bitOffset>
  14472. <bitWidth>1</bitWidth>
  14473. </field>
  14474. <field>
  14475. <name>ADSTART</name>
  14476. <description>ADC start conversion
  14477. command</description>
  14478. <bitOffset>2</bitOffset>
  14479. <bitWidth>1</bitWidth>
  14480. </field>
  14481. <field>
  14482. <name>ADSTP</name>
  14483. <description>ADC stop conversion
  14484. command</description>
  14485. <bitOffset>4</bitOffset>
  14486. <bitWidth>1</bitWidth>
  14487. </field>
  14488. <field>
  14489. <name>ADVREGEN</name>
  14490. <description>ADC Voltage Regulator
  14491. Enable</description>
  14492. <bitOffset>28</bitOffset>
  14493. <bitWidth>1</bitWidth>
  14494. </field>
  14495. <field>
  14496. <name>ADCAL</name>
  14497. <description>ADC calibration</description>
  14498. <bitOffset>31</bitOffset>
  14499. <bitWidth>1</bitWidth>
  14500. </field>
  14501. </fields>
  14502. </register>
  14503. <register>
  14504. <name>CFGR1</name>
  14505. <displayName>CFGR1</displayName>
  14506. <description>configuration register 1</description>
  14507. <addressOffset>0xC</addressOffset>
  14508. <size>0x20</size>
  14509. <access>read-write</access>
  14510. <resetValue>0x00000000</resetValue>
  14511. <fields>
  14512. <field>
  14513. <name>AWDCH</name>
  14514. <description>Analog watchdog channel
  14515. selection</description>
  14516. <bitOffset>26</bitOffset>
  14517. <bitWidth>5</bitWidth>
  14518. </field>
  14519. <field>
  14520. <name>AWDEN</name>
  14521. <description>Analog watchdog enable</description>
  14522. <bitOffset>23</bitOffset>
  14523. <bitWidth>1</bitWidth>
  14524. </field>
  14525. <field>
  14526. <name>AWDSGL</name>
  14527. <description>Enable the watchdog on a single channel
  14528. or on all channels</description>
  14529. <bitOffset>22</bitOffset>
  14530. <bitWidth>1</bitWidth>
  14531. </field>
  14532. <field>
  14533. <name>DISCEN</name>
  14534. <description>Discontinuous mode</description>
  14535. <bitOffset>16</bitOffset>
  14536. <bitWidth>1</bitWidth>
  14537. </field>
  14538. <field>
  14539. <name>AUTOFF</name>
  14540. <description>Auto-off mode</description>
  14541. <bitOffset>15</bitOffset>
  14542. <bitWidth>1</bitWidth>
  14543. </field>
  14544. <field>
  14545. <name>AUTDLY</name>
  14546. <description>Auto-delayed conversion
  14547. mode</description>
  14548. <bitOffset>14</bitOffset>
  14549. <bitWidth>1</bitWidth>
  14550. </field>
  14551. <field>
  14552. <name>CONT</name>
  14553. <description>Single / continuous conversion
  14554. mode</description>
  14555. <bitOffset>13</bitOffset>
  14556. <bitWidth>1</bitWidth>
  14557. </field>
  14558. <field>
  14559. <name>OVRMOD</name>
  14560. <description>Overrun management mode</description>
  14561. <bitOffset>12</bitOffset>
  14562. <bitWidth>1</bitWidth>
  14563. </field>
  14564. <field>
  14565. <name>EXTEN</name>
  14566. <description>External trigger enable and polarity
  14567. selection</description>
  14568. <bitOffset>10</bitOffset>
  14569. <bitWidth>2</bitWidth>
  14570. </field>
  14571. <field>
  14572. <name>EXTSEL</name>
  14573. <description>External trigger selection</description>
  14574. <bitOffset>6</bitOffset>
  14575. <bitWidth>3</bitWidth>
  14576. </field>
  14577. <field>
  14578. <name>ALIGN</name>
  14579. <description>Data alignment</description>
  14580. <bitOffset>5</bitOffset>
  14581. <bitWidth>1</bitWidth>
  14582. </field>
  14583. <field>
  14584. <name>RES</name>
  14585. <description>Data resolution</description>
  14586. <bitOffset>3</bitOffset>
  14587. <bitWidth>2</bitWidth>
  14588. </field>
  14589. <field>
  14590. <name>SCANDIR</name>
  14591. <description>Scan sequence direction</description>
  14592. <bitOffset>2</bitOffset>
  14593. <bitWidth>1</bitWidth>
  14594. </field>
  14595. <field>
  14596. <name>DMACFG</name>
  14597. <description>Direct memery access
  14598. configuration</description>
  14599. <bitOffset>1</bitOffset>
  14600. <bitWidth>1</bitWidth>
  14601. </field>
  14602. <field>
  14603. <name>DMAEN</name>
  14604. <description>Direct memory access
  14605. enable</description>
  14606. <bitOffset>0</bitOffset>
  14607. <bitWidth>1</bitWidth>
  14608. </field>
  14609. </fields>
  14610. </register>
  14611. <register>
  14612. <name>CFGR2</name>
  14613. <displayName>CFGR2</displayName>
  14614. <description>configuration register 2</description>
  14615. <addressOffset>0x10</addressOffset>
  14616. <size>0x20</size>
  14617. <access>read-write</access>
  14618. <resetValue>0x00000000</resetValue>
  14619. <fields>
  14620. <field>
  14621. <name>OVSE</name>
  14622. <description>Oversampler Enable</description>
  14623. <bitOffset>0</bitOffset>
  14624. <bitWidth>1</bitWidth>
  14625. </field>
  14626. <field>
  14627. <name>OVSR</name>
  14628. <description>Oversampling ratio</description>
  14629. <bitOffset>2</bitOffset>
  14630. <bitWidth>3</bitWidth>
  14631. </field>
  14632. <field>
  14633. <name>OVSS</name>
  14634. <description>Oversampling shift</description>
  14635. <bitOffset>5</bitOffset>
  14636. <bitWidth>4</bitWidth>
  14637. </field>
  14638. <field>
  14639. <name>TOVS</name>
  14640. <description>Triggered Oversampling</description>
  14641. <bitOffset>9</bitOffset>
  14642. <bitWidth>1</bitWidth>
  14643. </field>
  14644. <field>
  14645. <name>CKMODE</name>
  14646. <description>ADC clock mode</description>
  14647. <bitOffset>30</bitOffset>
  14648. <bitWidth>2</bitWidth>
  14649. </field>
  14650. </fields>
  14651. </register>
  14652. <register>
  14653. <name>SMPR</name>
  14654. <displayName>SMPR</displayName>
  14655. <description>sampling time register</description>
  14656. <addressOffset>0x14</addressOffset>
  14657. <size>0x20</size>
  14658. <access>read-write</access>
  14659. <resetValue>0x00000000</resetValue>
  14660. <fields>
  14661. <field>
  14662. <name>SMPR</name>
  14663. <description>Sampling time selection</description>
  14664. <bitOffset>0</bitOffset>
  14665. <bitWidth>3</bitWidth>
  14666. </field>
  14667. </fields>
  14668. </register>
  14669. <register>
  14670. <name>TR</name>
  14671. <displayName>TR</displayName>
  14672. <description>watchdog threshold register</description>
  14673. <addressOffset>0x20</addressOffset>
  14674. <size>0x20</size>
  14675. <access>read-write</access>
  14676. <resetValue>0x0FFF0000</resetValue>
  14677. <fields>
  14678. <field>
  14679. <name>HT</name>
  14680. <description>Analog watchdog higher
  14681. threshold</description>
  14682. <bitOffset>16</bitOffset>
  14683. <bitWidth>12</bitWidth>
  14684. </field>
  14685. <field>
  14686. <name>LT</name>
  14687. <description>Analog watchdog lower
  14688. threshold</description>
  14689. <bitOffset>0</bitOffset>
  14690. <bitWidth>12</bitWidth>
  14691. </field>
  14692. </fields>
  14693. </register>
  14694. <register>
  14695. <name>CHSELR</name>
  14696. <displayName>CHSELR</displayName>
  14697. <description>channel selection register</description>
  14698. <addressOffset>0x28</addressOffset>
  14699. <size>0x20</size>
  14700. <access>read-write</access>
  14701. <resetValue>0x00000000</resetValue>
  14702. <fields>
  14703. <field>
  14704. <name>CHSEL18</name>
  14705. <description>Channel-x selection</description>
  14706. <bitOffset>18</bitOffset>
  14707. <bitWidth>1</bitWidth>
  14708. </field>
  14709. <field>
  14710. <name>CHSEL17</name>
  14711. <description>Channel-x selection</description>
  14712. <bitOffset>17</bitOffset>
  14713. <bitWidth>1</bitWidth>
  14714. </field>
  14715. <field>
  14716. <name>CHSEL16</name>
  14717. <description>Channel-x selection</description>
  14718. <bitOffset>16</bitOffset>
  14719. <bitWidth>1</bitWidth>
  14720. </field>
  14721. <field>
  14722. <name>CHSEL15</name>
  14723. <description>Channel-x selection</description>
  14724. <bitOffset>15</bitOffset>
  14725. <bitWidth>1</bitWidth>
  14726. </field>
  14727. <field>
  14728. <name>CHSEL14</name>
  14729. <description>Channel-x selection</description>
  14730. <bitOffset>14</bitOffset>
  14731. <bitWidth>1</bitWidth>
  14732. </field>
  14733. <field>
  14734. <name>CHSEL13</name>
  14735. <description>Channel-x selection</description>
  14736. <bitOffset>13</bitOffset>
  14737. <bitWidth>1</bitWidth>
  14738. </field>
  14739. <field>
  14740. <name>CHSEL12</name>
  14741. <description>Channel-x selection</description>
  14742. <bitOffset>12</bitOffset>
  14743. <bitWidth>1</bitWidth>
  14744. </field>
  14745. <field>
  14746. <name>CHSEL11</name>
  14747. <description>Channel-x selection</description>
  14748. <bitOffset>11</bitOffset>
  14749. <bitWidth>1</bitWidth>
  14750. </field>
  14751. <field>
  14752. <name>CHSEL10</name>
  14753. <description>Channel-x selection</description>
  14754. <bitOffset>10</bitOffset>
  14755. <bitWidth>1</bitWidth>
  14756. </field>
  14757. <field>
  14758. <name>CHSEL9</name>
  14759. <description>Channel-x selection</description>
  14760. <bitOffset>9</bitOffset>
  14761. <bitWidth>1</bitWidth>
  14762. </field>
  14763. <field>
  14764. <name>CHSEL8</name>
  14765. <description>Channel-x selection</description>
  14766. <bitOffset>8</bitOffset>
  14767. <bitWidth>1</bitWidth>
  14768. </field>
  14769. <field>
  14770. <name>CHSEL7</name>
  14771. <description>Channel-x selection</description>
  14772. <bitOffset>7</bitOffset>
  14773. <bitWidth>1</bitWidth>
  14774. </field>
  14775. <field>
  14776. <name>CHSEL6</name>
  14777. <description>Channel-x selection</description>
  14778. <bitOffset>6</bitOffset>
  14779. <bitWidth>1</bitWidth>
  14780. </field>
  14781. <field>
  14782. <name>CHSEL5</name>
  14783. <description>Channel-x selection</description>
  14784. <bitOffset>5</bitOffset>
  14785. <bitWidth>1</bitWidth>
  14786. </field>
  14787. <field>
  14788. <name>CHSEL4</name>
  14789. <description>Channel-x selection</description>
  14790. <bitOffset>4</bitOffset>
  14791. <bitWidth>1</bitWidth>
  14792. </field>
  14793. <field>
  14794. <name>CHSEL3</name>
  14795. <description>Channel-x selection</description>
  14796. <bitOffset>3</bitOffset>
  14797. <bitWidth>1</bitWidth>
  14798. </field>
  14799. <field>
  14800. <name>CHSEL2</name>
  14801. <description>Channel-x selection</description>
  14802. <bitOffset>2</bitOffset>
  14803. <bitWidth>1</bitWidth>
  14804. </field>
  14805. <field>
  14806. <name>CHSEL1</name>
  14807. <description>Channel-x selection</description>
  14808. <bitOffset>1</bitOffset>
  14809. <bitWidth>1</bitWidth>
  14810. </field>
  14811. <field>
  14812. <name>CHSEL0</name>
  14813. <description>Channel-x selection</description>
  14814. <bitOffset>0</bitOffset>
  14815. <bitWidth>1</bitWidth>
  14816. </field>
  14817. </fields>
  14818. </register>
  14819. <register>
  14820. <name>DR</name>
  14821. <displayName>DR</displayName>
  14822. <description>data register</description>
  14823. <addressOffset>0x40</addressOffset>
  14824. <size>0x20</size>
  14825. <access>read-only</access>
  14826. <resetValue>0x00000000</resetValue>
  14827. <fields>
  14828. <field>
  14829. <name>DATA</name>
  14830. <description>Converted data</description>
  14831. <bitOffset>0</bitOffset>
  14832. <bitWidth>16</bitWidth>
  14833. </field>
  14834. </fields>
  14835. </register>
  14836. <register>
  14837. <name>CALFACT</name>
  14838. <displayName>CALFACT</displayName>
  14839. <description>ADC Calibration factor</description>
  14840. <addressOffset>0xB4</addressOffset>
  14841. <size>0x20</size>
  14842. <access>read-write</access>
  14843. <resetValue>0x00000000</resetValue>
  14844. <fields>
  14845. <field>
  14846. <name>CALFACT</name>
  14847. <description>Calibration factor</description>
  14848. <bitOffset>0</bitOffset>
  14849. <bitWidth>7</bitWidth>
  14850. </field>
  14851. </fields>
  14852. </register>
  14853. <register>
  14854. <name>CCR</name>
  14855. <displayName>CCR</displayName>
  14856. <description>ADC common configuration
  14857. register</description>
  14858. <addressOffset>0x308</addressOffset>
  14859. <size>0x20</size>
  14860. <access>read-write</access>
  14861. <resetValue>0x00000000</resetValue>
  14862. <fields>
  14863. <field>
  14864. <name>PRESC</name>
  14865. <description>ADC prescaler</description>
  14866. <bitOffset>18</bitOffset>
  14867. <bitWidth>4</bitWidth>
  14868. </field>
  14869. <field>
  14870. <name>VREFEN</name>
  14871. <description>VREFINT enable</description>
  14872. <bitOffset>22</bitOffset>
  14873. <bitWidth>1</bitWidth>
  14874. </field>
  14875. <field>
  14876. <name>TSEN</name>
  14877. <description>Temperature sensor enable</description>
  14878. <bitOffset>23</bitOffset>
  14879. <bitWidth>1</bitWidth>
  14880. </field>
  14881. <field>
  14882. <name>VLCDEN</name>
  14883. <description>VLCD enable</description>
  14884. <bitOffset>24</bitOffset>
  14885. <bitWidth>1</bitWidth>
  14886. </field>
  14887. <field>
  14888. <name>LFMEN</name>
  14889. <description>Low Frequency Mode enable</description>
  14890. <bitOffset>25</bitOffset>
  14891. <bitWidth>1</bitWidth>
  14892. </field>
  14893. </fields>
  14894. </register>
  14895. </registers>
  14896. </peripheral>
  14897. <peripheral>
  14898. <name>DBGMCU</name>
  14899. <description>Debug support</description>
  14900. <groupName>DBGMCU</groupName>
  14901. <baseAddress>0x40015800</baseAddress>
  14902. <addressBlock>
  14903. <offset>0x0</offset>
  14904. <size>0x400</size>
  14905. <usage>registers</usage>
  14906. </addressBlock>
  14907. <registers>
  14908. <register>
  14909. <name>IDCODE</name>
  14910. <displayName>IDCODE</displayName>
  14911. <description>MCU Device ID Code Register</description>
  14912. <addressOffset>0x0</addressOffset>
  14913. <size>0x20</size>
  14914. <access>read-only</access>
  14915. <resetValue>0x0</resetValue>
  14916. <fields>
  14917. <field>
  14918. <name>DEV_ID</name>
  14919. <description>Device Identifier</description>
  14920. <bitOffset>0</bitOffset>
  14921. <bitWidth>12</bitWidth>
  14922. </field>
  14923. <field>
  14924. <name>REV_ID</name>
  14925. <description>Revision Identifier</description>
  14926. <bitOffset>16</bitOffset>
  14927. <bitWidth>16</bitWidth>
  14928. </field>
  14929. </fields>
  14930. </register>
  14931. <register>
  14932. <name>CR</name>
  14933. <displayName>CR</displayName>
  14934. <description>Debug MCU Configuration
  14935. Register</description>
  14936. <addressOffset>0x4</addressOffset>
  14937. <size>0x20</size>
  14938. <access>read-write</access>
  14939. <resetValue>0x0</resetValue>
  14940. <fields>
  14941. <field>
  14942. <name>DBG_STOP</name>
  14943. <description>Debug Stop Mode</description>
  14944. <bitOffset>1</bitOffset>
  14945. <bitWidth>1</bitWidth>
  14946. </field>
  14947. <field>
  14948. <name>DBG_STANDBY</name>
  14949. <description>Debug Standby Mode</description>
  14950. <bitOffset>2</bitOffset>
  14951. <bitWidth>1</bitWidth>
  14952. </field>
  14953. <field>
  14954. <name>DBG_SLEEP</name>
  14955. <description>Debug Sleep Mode</description>
  14956. <bitOffset>0</bitOffset>
  14957. <bitWidth>1</bitWidth>
  14958. </field>
  14959. </fields>
  14960. </register>
  14961. <register>
  14962. <name>APB1_FZ</name>
  14963. <displayName>APB1_FZ</displayName>
  14964. <description>APB Low Freeze Register</description>
  14965. <addressOffset>0x8</addressOffset>
  14966. <size>0x20</size>
  14967. <access>read-write</access>
  14968. <resetValue>0x0</resetValue>
  14969. <fields>
  14970. <field>
  14971. <name>DBG_TIMER2_STOP</name>
  14972. <description>Debug Timer 2 stopped when Core is
  14973. halted</description>
  14974. <bitOffset>0</bitOffset>
  14975. <bitWidth>1</bitWidth>
  14976. </field>
  14977. <field>
  14978. <name>DBG_TIMER6_STOP</name>
  14979. <description>Debug Timer 6 stopped when Core is
  14980. halted</description>
  14981. <bitOffset>4</bitOffset>
  14982. <bitWidth>1</bitWidth>
  14983. </field>
  14984. <field>
  14985. <name>DBG_RTC_STOP</name>
  14986. <description>Debug RTC stopped when Core is
  14987. halted</description>
  14988. <bitOffset>10</bitOffset>
  14989. <bitWidth>1</bitWidth>
  14990. </field>
  14991. <field>
  14992. <name>DBG_WWDG_STOP</name>
  14993. <description>Debug Window Wachdog stopped when Core
  14994. is halted</description>
  14995. <bitOffset>11</bitOffset>
  14996. <bitWidth>1</bitWidth>
  14997. </field>
  14998. <field>
  14999. <name>DBG_IWDG_STOP</name>
  15000. <description>Debug Independent Wachdog stopped when
  15001. Core is halted</description>
  15002. <bitOffset>12</bitOffset>
  15003. <bitWidth>1</bitWidth>
  15004. </field>
  15005. <field>
  15006. <name>DBG_I2C1_STOP</name>
  15007. <description>I2C1 SMBUS timeout mode stopped when
  15008. core is halted</description>
  15009. <bitOffset>21</bitOffset>
  15010. <bitWidth>1</bitWidth>
  15011. </field>
  15012. <field>
  15013. <name>DBG_I2C2_STOP</name>
  15014. <description>I2C2 SMBUS timeout mode stopped when
  15015. core is halted</description>
  15016. <bitOffset>22</bitOffset>
  15017. <bitWidth>1</bitWidth>
  15018. </field>
  15019. <field>
  15020. <name>DBG_I2C3_STOP</name>
  15021. <description>I2C3 SMBUS timeout mode stopped when
  15022. core is halted</description>
  15023. <bitOffset>30</bitOffset>
  15024. <bitWidth>1</bitWidth>
  15025. </field>
  15026. <field>
  15027. <name>DBG_LPTIMER_STOP</name>
  15028. <description>LPTIM1 counter stopped when core is
  15029. halted</description>
  15030. <bitOffset>31</bitOffset>
  15031. <bitWidth>1</bitWidth>
  15032. </field>
  15033. </fields>
  15034. </register>
  15035. <register>
  15036. <name>APB2_FZ</name>
  15037. <displayName>APB2_FZ</displayName>
  15038. <description>APB High Freeze Register</description>
  15039. <addressOffset>0xC</addressOffset>
  15040. <size>0x20</size>
  15041. <access>read-write</access>
  15042. <resetValue>0x0</resetValue>
  15043. <fields>
  15044. <field>
  15045. <name>DBG_TIMER21_STOP</name>
  15046. <description>Debug Timer 21 stopped when Core is
  15047. halted</description>
  15048. <bitOffset>2</bitOffset>
  15049. <bitWidth>1</bitWidth>
  15050. </field>
  15051. <field>
  15052. <name>DBG_TIMER22_STOP</name>
  15053. <description>Debug Timer 22 stopped when Core is
  15054. halted</description>
  15055. <bitOffset>5</bitOffset>
  15056. <bitWidth>1</bitWidth>
  15057. </field>
  15058. </fields>
  15059. </register>
  15060. </registers>
  15061. </peripheral>
  15062. <peripheral>
  15063. <name>TIM2</name>
  15064. <description>General-purpose-timers</description>
  15065. <groupName>TIM</groupName>
  15066. <baseAddress>0x40000000</baseAddress>
  15067. <addressBlock>
  15068. <offset>0x0</offset>
  15069. <size>0x400</size>
  15070. <usage>registers</usage>
  15071. </addressBlock>
  15072. <interrupt>
  15073. <name>TIM2</name>
  15074. <description>TIM2 global interrupt</description>
  15075. <value>15</value>
  15076. </interrupt>
  15077. <registers>
  15078. <register>
  15079. <name>CR1</name>
  15080. <displayName>CR1</displayName>
  15081. <description>control register 1</description>
  15082. <addressOffset>0x0</addressOffset>
  15083. <size>0x20</size>
  15084. <access>read-write</access>
  15085. <resetValue>0x0000</resetValue>
  15086. <fields>
  15087. <field>
  15088. <name>CKD</name>
  15089. <description>Clock division</description>
  15090. <bitOffset>8</bitOffset>
  15091. <bitWidth>2</bitWidth>
  15092. </field>
  15093. <field>
  15094. <name>ARPE</name>
  15095. <description>Auto-reload preload enable</description>
  15096. <bitOffset>7</bitOffset>
  15097. <bitWidth>1</bitWidth>
  15098. </field>
  15099. <field>
  15100. <name>CMS</name>
  15101. <description>Center-aligned mode
  15102. selection</description>
  15103. <bitOffset>5</bitOffset>
  15104. <bitWidth>2</bitWidth>
  15105. </field>
  15106. <field>
  15107. <name>DIR</name>
  15108. <description>Direction</description>
  15109. <bitOffset>4</bitOffset>
  15110. <bitWidth>1</bitWidth>
  15111. </field>
  15112. <field>
  15113. <name>OPM</name>
  15114. <description>One-pulse mode</description>
  15115. <bitOffset>3</bitOffset>
  15116. <bitWidth>1</bitWidth>
  15117. </field>
  15118. <field>
  15119. <name>URS</name>
  15120. <description>Update request source</description>
  15121. <bitOffset>2</bitOffset>
  15122. <bitWidth>1</bitWidth>
  15123. </field>
  15124. <field>
  15125. <name>UDIS</name>
  15126. <description>Update disable</description>
  15127. <bitOffset>1</bitOffset>
  15128. <bitWidth>1</bitWidth>
  15129. </field>
  15130. <field>
  15131. <name>CEN</name>
  15132. <description>Counter enable</description>
  15133. <bitOffset>0</bitOffset>
  15134. <bitWidth>1</bitWidth>
  15135. </field>
  15136. </fields>
  15137. </register>
  15138. <register>
  15139. <name>CR2</name>
  15140. <displayName>CR2</displayName>
  15141. <description>control register 2</description>
  15142. <addressOffset>0x4</addressOffset>
  15143. <size>0x20</size>
  15144. <access>read-write</access>
  15145. <resetValue>0x0000</resetValue>
  15146. <fields>
  15147. <field>
  15148. <name>TI1S</name>
  15149. <description>TI1 selection</description>
  15150. <bitOffset>7</bitOffset>
  15151. <bitWidth>1</bitWidth>
  15152. </field>
  15153. <field>
  15154. <name>MMS</name>
  15155. <description>Master mode selection</description>
  15156. <bitOffset>4</bitOffset>
  15157. <bitWidth>3</bitWidth>
  15158. </field>
  15159. <field>
  15160. <name>CCDS</name>
  15161. <description>Capture/compare DMA
  15162. selection</description>
  15163. <bitOffset>3</bitOffset>
  15164. <bitWidth>1</bitWidth>
  15165. </field>
  15166. </fields>
  15167. </register>
  15168. <register>
  15169. <name>SMCR</name>
  15170. <displayName>SMCR</displayName>
  15171. <description>slave mode control register</description>
  15172. <addressOffset>0x8</addressOffset>
  15173. <size>0x20</size>
  15174. <access>read-write</access>
  15175. <resetValue>0x0000</resetValue>
  15176. <fields>
  15177. <field>
  15178. <name>ETP</name>
  15179. <description>External trigger polarity</description>
  15180. <bitOffset>15</bitOffset>
  15181. <bitWidth>1</bitWidth>
  15182. </field>
  15183. <field>
  15184. <name>ECE</name>
  15185. <description>External clock enable</description>
  15186. <bitOffset>14</bitOffset>
  15187. <bitWidth>1</bitWidth>
  15188. </field>
  15189. <field>
  15190. <name>ETPS</name>
  15191. <description>External trigger prescaler</description>
  15192. <bitOffset>12</bitOffset>
  15193. <bitWidth>2</bitWidth>
  15194. </field>
  15195. <field>
  15196. <name>ETF</name>
  15197. <description>External trigger filter</description>
  15198. <bitOffset>8</bitOffset>
  15199. <bitWidth>4</bitWidth>
  15200. </field>
  15201. <field>
  15202. <name>MSM</name>
  15203. <description>Master/Slave mode</description>
  15204. <bitOffset>7</bitOffset>
  15205. <bitWidth>1</bitWidth>
  15206. </field>
  15207. <field>
  15208. <name>TS</name>
  15209. <description>Trigger selection</description>
  15210. <bitOffset>4</bitOffset>
  15211. <bitWidth>3</bitWidth>
  15212. </field>
  15213. <field>
  15214. <name>SMS</name>
  15215. <description>Slave mode selection</description>
  15216. <bitOffset>0</bitOffset>
  15217. <bitWidth>3</bitWidth>
  15218. </field>
  15219. </fields>
  15220. </register>
  15221. <register>
  15222. <name>DIER</name>
  15223. <displayName>DIER</displayName>
  15224. <description>DMA/Interrupt enable register</description>
  15225. <addressOffset>0xC</addressOffset>
  15226. <size>0x20</size>
  15227. <access>read-write</access>
  15228. <resetValue>0x0000</resetValue>
  15229. <fields>
  15230. <field>
  15231. <name>TDE</name>
  15232. <description>Trigger DMA request enable</description>
  15233. <bitOffset>14</bitOffset>
  15234. <bitWidth>1</bitWidth>
  15235. </field>
  15236. <field>
  15237. <name>COMDE</name>
  15238. <description>Reserved</description>
  15239. <bitOffset>13</bitOffset>
  15240. <bitWidth>1</bitWidth>
  15241. </field>
  15242. <field>
  15243. <name>CC4DE</name>
  15244. <description>Capture/Compare 4 DMA request
  15245. enable</description>
  15246. <bitOffset>12</bitOffset>
  15247. <bitWidth>1</bitWidth>
  15248. </field>
  15249. <field>
  15250. <name>CC3DE</name>
  15251. <description>Capture/Compare 3 DMA request
  15252. enable</description>
  15253. <bitOffset>11</bitOffset>
  15254. <bitWidth>1</bitWidth>
  15255. </field>
  15256. <field>
  15257. <name>CC2DE</name>
  15258. <description>Capture/Compare 2 DMA request
  15259. enable</description>
  15260. <bitOffset>10</bitOffset>
  15261. <bitWidth>1</bitWidth>
  15262. </field>
  15263. <field>
  15264. <name>CC1DE</name>
  15265. <description>Capture/Compare 1 DMA request
  15266. enable</description>
  15267. <bitOffset>9</bitOffset>
  15268. <bitWidth>1</bitWidth>
  15269. </field>
  15270. <field>
  15271. <name>UDE</name>
  15272. <description>Update DMA request enable</description>
  15273. <bitOffset>8</bitOffset>
  15274. <bitWidth>1</bitWidth>
  15275. </field>
  15276. <field>
  15277. <name>TIE</name>
  15278. <description>Trigger interrupt enable</description>
  15279. <bitOffset>6</bitOffset>
  15280. <bitWidth>1</bitWidth>
  15281. </field>
  15282. <field>
  15283. <name>CC4IE</name>
  15284. <description>Capture/Compare 4 interrupt
  15285. enable</description>
  15286. <bitOffset>4</bitOffset>
  15287. <bitWidth>1</bitWidth>
  15288. </field>
  15289. <field>
  15290. <name>CC3IE</name>
  15291. <description>Capture/Compare 3 interrupt
  15292. enable</description>
  15293. <bitOffset>3</bitOffset>
  15294. <bitWidth>1</bitWidth>
  15295. </field>
  15296. <field>
  15297. <name>CC2IE</name>
  15298. <description>Capture/Compare 2 interrupt
  15299. enable</description>
  15300. <bitOffset>2</bitOffset>
  15301. <bitWidth>1</bitWidth>
  15302. </field>
  15303. <field>
  15304. <name>CC1IE</name>
  15305. <description>Capture/Compare 1 interrupt
  15306. enable</description>
  15307. <bitOffset>1</bitOffset>
  15308. <bitWidth>1</bitWidth>
  15309. </field>
  15310. <field>
  15311. <name>UIE</name>
  15312. <description>Update interrupt enable</description>
  15313. <bitOffset>0</bitOffset>
  15314. <bitWidth>1</bitWidth>
  15315. </field>
  15316. </fields>
  15317. </register>
  15318. <register>
  15319. <name>SR</name>
  15320. <displayName>SR</displayName>
  15321. <description>status register</description>
  15322. <addressOffset>0x10</addressOffset>
  15323. <size>0x20</size>
  15324. <access>read-write</access>
  15325. <resetValue>0x0000</resetValue>
  15326. <fields>
  15327. <field>
  15328. <name>CC4OF</name>
  15329. <description>Capture/Compare 4 overcapture
  15330. flag</description>
  15331. <bitOffset>12</bitOffset>
  15332. <bitWidth>1</bitWidth>
  15333. </field>
  15334. <field>
  15335. <name>CC3OF</name>
  15336. <description>Capture/Compare 3 overcapture
  15337. flag</description>
  15338. <bitOffset>11</bitOffset>
  15339. <bitWidth>1</bitWidth>
  15340. </field>
  15341. <field>
  15342. <name>CC2OF</name>
  15343. <description>Capture/compare 2 overcapture
  15344. flag</description>
  15345. <bitOffset>10</bitOffset>
  15346. <bitWidth>1</bitWidth>
  15347. </field>
  15348. <field>
  15349. <name>CC1OF</name>
  15350. <description>Capture/Compare 1 overcapture
  15351. flag</description>
  15352. <bitOffset>9</bitOffset>
  15353. <bitWidth>1</bitWidth>
  15354. </field>
  15355. <field>
  15356. <name>TIF</name>
  15357. <description>Trigger interrupt flag</description>
  15358. <bitOffset>6</bitOffset>
  15359. <bitWidth>1</bitWidth>
  15360. </field>
  15361. <field>
  15362. <name>CC4IF</name>
  15363. <description>Capture/Compare 4 interrupt
  15364. flag</description>
  15365. <bitOffset>4</bitOffset>
  15366. <bitWidth>1</bitWidth>
  15367. </field>
  15368. <field>
  15369. <name>CC3IF</name>
  15370. <description>Capture/Compare 3 interrupt
  15371. flag</description>
  15372. <bitOffset>3</bitOffset>
  15373. <bitWidth>1</bitWidth>
  15374. </field>
  15375. <field>
  15376. <name>CC2IF</name>
  15377. <description>Capture/Compare 2 interrupt
  15378. flag</description>
  15379. <bitOffset>2</bitOffset>
  15380. <bitWidth>1</bitWidth>
  15381. </field>
  15382. <field>
  15383. <name>CC1IF</name>
  15384. <description>Capture/compare 1 interrupt
  15385. flag</description>
  15386. <bitOffset>1</bitOffset>
  15387. <bitWidth>1</bitWidth>
  15388. </field>
  15389. <field>
  15390. <name>UIF</name>
  15391. <description>Update interrupt flag</description>
  15392. <bitOffset>0</bitOffset>
  15393. <bitWidth>1</bitWidth>
  15394. </field>
  15395. </fields>
  15396. </register>
  15397. <register>
  15398. <name>EGR</name>
  15399. <displayName>EGR</displayName>
  15400. <description>event generation register</description>
  15401. <addressOffset>0x14</addressOffset>
  15402. <size>0x20</size>
  15403. <access>write-only</access>
  15404. <resetValue>0x0000</resetValue>
  15405. <fields>
  15406. <field>
  15407. <name>TG</name>
  15408. <description>Trigger generation</description>
  15409. <bitOffset>6</bitOffset>
  15410. <bitWidth>1</bitWidth>
  15411. </field>
  15412. <field>
  15413. <name>CC4G</name>
  15414. <description>Capture/compare 4
  15415. generation</description>
  15416. <bitOffset>4</bitOffset>
  15417. <bitWidth>1</bitWidth>
  15418. </field>
  15419. <field>
  15420. <name>CC3G</name>
  15421. <description>Capture/compare 3
  15422. generation</description>
  15423. <bitOffset>3</bitOffset>
  15424. <bitWidth>1</bitWidth>
  15425. </field>
  15426. <field>
  15427. <name>CC2G</name>
  15428. <description>Capture/compare 2
  15429. generation</description>
  15430. <bitOffset>2</bitOffset>
  15431. <bitWidth>1</bitWidth>
  15432. </field>
  15433. <field>
  15434. <name>CC1G</name>
  15435. <description>Capture/compare 1
  15436. generation</description>
  15437. <bitOffset>1</bitOffset>
  15438. <bitWidth>1</bitWidth>
  15439. </field>
  15440. <field>
  15441. <name>UG</name>
  15442. <description>Update generation</description>
  15443. <bitOffset>0</bitOffset>
  15444. <bitWidth>1</bitWidth>
  15445. </field>
  15446. </fields>
  15447. </register>
  15448. <register>
  15449. <name>CCMR1_Output</name>
  15450. <displayName>CCMR1_Output</displayName>
  15451. <description>capture/compare mode register 1 (output
  15452. mode)</description>
  15453. <addressOffset>0x18</addressOffset>
  15454. <size>0x20</size>
  15455. <access>read-write</access>
  15456. <resetValue>0x00000000</resetValue>
  15457. <fields>
  15458. <field>
  15459. <name>OC2CE</name>
  15460. <description>Output compare 2 clear
  15461. enable</description>
  15462. <bitOffset>15</bitOffset>
  15463. <bitWidth>1</bitWidth>
  15464. </field>
  15465. <field>
  15466. <name>OC2M</name>
  15467. <description>Output compare 2 mode</description>
  15468. <bitOffset>12</bitOffset>
  15469. <bitWidth>3</bitWidth>
  15470. </field>
  15471. <field>
  15472. <name>OC2PE</name>
  15473. <description>Output compare 2 preload
  15474. enable</description>
  15475. <bitOffset>11</bitOffset>
  15476. <bitWidth>1</bitWidth>
  15477. </field>
  15478. <field>
  15479. <name>OC2FE</name>
  15480. <description>Output compare 2 fast
  15481. enable</description>
  15482. <bitOffset>10</bitOffset>
  15483. <bitWidth>1</bitWidth>
  15484. </field>
  15485. <field>
  15486. <name>CC2S</name>
  15487. <description>Capture/Compare 2
  15488. selection</description>
  15489. <bitOffset>8</bitOffset>
  15490. <bitWidth>2</bitWidth>
  15491. </field>
  15492. <field>
  15493. <name>OC1CE</name>
  15494. <description>Output compare 1 clear
  15495. enable</description>
  15496. <bitOffset>7</bitOffset>
  15497. <bitWidth>1</bitWidth>
  15498. </field>
  15499. <field>
  15500. <name>OC1M</name>
  15501. <description>Output compare 1 mode</description>
  15502. <bitOffset>4</bitOffset>
  15503. <bitWidth>3</bitWidth>
  15504. </field>
  15505. <field>
  15506. <name>OC1PE</name>
  15507. <description>Output compare 1 preload
  15508. enable</description>
  15509. <bitOffset>3</bitOffset>
  15510. <bitWidth>1</bitWidth>
  15511. </field>
  15512. <field>
  15513. <name>OC1FE</name>
  15514. <description>Output compare 1 fast
  15515. enable</description>
  15516. <bitOffset>2</bitOffset>
  15517. <bitWidth>1</bitWidth>
  15518. </field>
  15519. <field>
  15520. <name>CC1S</name>
  15521. <description>Capture/Compare 1
  15522. selection</description>
  15523. <bitOffset>0</bitOffset>
  15524. <bitWidth>2</bitWidth>
  15525. </field>
  15526. </fields>
  15527. </register>
  15528. <register>
  15529. <name>CCMR1_Input</name>
  15530. <displayName>CCMR1_Input</displayName>
  15531. <description>capture/compare mode register 1 (input
  15532. mode)</description>
  15533. <alternateRegister>CCMR1_Output</alternateRegister>
  15534. <addressOffset>0x18</addressOffset>
  15535. <size>0x20</size>
  15536. <access>read-write</access>
  15537. <resetValue>0x00000000</resetValue>
  15538. <fields>
  15539. <field>
  15540. <name>IC2F</name>
  15541. <description>Input capture 2 filter</description>
  15542. <bitOffset>12</bitOffset>
  15543. <bitWidth>4</bitWidth>
  15544. </field>
  15545. <field>
  15546. <name>IC2PSC</name>
  15547. <description>Input capture 2 prescaler</description>
  15548. <bitOffset>10</bitOffset>
  15549. <bitWidth>2</bitWidth>
  15550. </field>
  15551. <field>
  15552. <name>CC2S</name>
  15553. <description>Capture/compare 2
  15554. selection</description>
  15555. <bitOffset>8</bitOffset>
  15556. <bitWidth>2</bitWidth>
  15557. </field>
  15558. <field>
  15559. <name>IC1F</name>
  15560. <description>Input capture 1 filter</description>
  15561. <bitOffset>4</bitOffset>
  15562. <bitWidth>4</bitWidth>
  15563. </field>
  15564. <field>
  15565. <name>IC1PSC</name>
  15566. <description>Input capture 1 prescaler</description>
  15567. <bitOffset>2</bitOffset>
  15568. <bitWidth>2</bitWidth>
  15569. </field>
  15570. <field>
  15571. <name>CC1S</name>
  15572. <description>Capture/Compare 1
  15573. selection</description>
  15574. <bitOffset>0</bitOffset>
  15575. <bitWidth>2</bitWidth>
  15576. </field>
  15577. </fields>
  15578. </register>
  15579. <register>
  15580. <name>CCMR2_Output</name>
  15581. <displayName>CCMR2_Output</displayName>
  15582. <description>capture/compare mode register 2 (output
  15583. mode)</description>
  15584. <addressOffset>0x1C</addressOffset>
  15585. <size>0x20</size>
  15586. <access>read-write</access>
  15587. <resetValue>0x00000000</resetValue>
  15588. <fields>
  15589. <field>
  15590. <name>OC4CE</name>
  15591. <description>Output compare 4 clear
  15592. enable</description>
  15593. <bitOffset>15</bitOffset>
  15594. <bitWidth>1</bitWidth>
  15595. </field>
  15596. <field>
  15597. <name>OC4M</name>
  15598. <description>Output compare 4 mode</description>
  15599. <bitOffset>12</bitOffset>
  15600. <bitWidth>3</bitWidth>
  15601. </field>
  15602. <field>
  15603. <name>OC4PE</name>
  15604. <description>Output compare 4 preload
  15605. enable</description>
  15606. <bitOffset>11</bitOffset>
  15607. <bitWidth>1</bitWidth>
  15608. </field>
  15609. <field>
  15610. <name>OC4FE</name>
  15611. <description>Output compare 4 fast
  15612. enable</description>
  15613. <bitOffset>10</bitOffset>
  15614. <bitWidth>1</bitWidth>
  15615. </field>
  15616. <field>
  15617. <name>CC4S</name>
  15618. <description>Capture/Compare 4
  15619. selection</description>
  15620. <bitOffset>8</bitOffset>
  15621. <bitWidth>2</bitWidth>
  15622. </field>
  15623. <field>
  15624. <name>OC3CE</name>
  15625. <description>Output compare 3 clear
  15626. enable</description>
  15627. <bitOffset>7</bitOffset>
  15628. <bitWidth>1</bitWidth>
  15629. </field>
  15630. <field>
  15631. <name>OC3M</name>
  15632. <description>Output compare 3 mode</description>
  15633. <bitOffset>4</bitOffset>
  15634. <bitWidth>3</bitWidth>
  15635. </field>
  15636. <field>
  15637. <name>OC3PE</name>
  15638. <description>Output compare 3 preload
  15639. enable</description>
  15640. <bitOffset>3</bitOffset>
  15641. <bitWidth>1</bitWidth>
  15642. </field>
  15643. <field>
  15644. <name>OC3FE</name>
  15645. <description>Output compare 3 fast
  15646. enable</description>
  15647. <bitOffset>2</bitOffset>
  15648. <bitWidth>1</bitWidth>
  15649. </field>
  15650. <field>
  15651. <name>CC3S</name>
  15652. <description>Capture/Compare 3
  15653. selection</description>
  15654. <bitOffset>0</bitOffset>
  15655. <bitWidth>2</bitWidth>
  15656. </field>
  15657. </fields>
  15658. </register>
  15659. <register>
  15660. <name>CCMR2_Input</name>
  15661. <displayName>CCMR2_Input</displayName>
  15662. <description>capture/compare mode register 2 (input
  15663. mode)</description>
  15664. <alternateRegister>CCMR2_Output</alternateRegister>
  15665. <addressOffset>0x1C</addressOffset>
  15666. <size>0x20</size>
  15667. <access>read-write</access>
  15668. <resetValue>0x00000000</resetValue>
  15669. <fields>
  15670. <field>
  15671. <name>IC4F</name>
  15672. <description>Input capture 4 filter</description>
  15673. <bitOffset>12</bitOffset>
  15674. <bitWidth>4</bitWidth>
  15675. </field>
  15676. <field>
  15677. <name>IC4PSC</name>
  15678. <description>Input capture 4 prescaler</description>
  15679. <bitOffset>10</bitOffset>
  15680. <bitWidth>2</bitWidth>
  15681. </field>
  15682. <field>
  15683. <name>CC4S</name>
  15684. <description>Capture/Compare 4
  15685. selection</description>
  15686. <bitOffset>8</bitOffset>
  15687. <bitWidth>2</bitWidth>
  15688. </field>
  15689. <field>
  15690. <name>IC3F</name>
  15691. <description>Input capture 3 filter</description>
  15692. <bitOffset>4</bitOffset>
  15693. <bitWidth>4</bitWidth>
  15694. </field>
  15695. <field>
  15696. <name>IC3PSC</name>
  15697. <description>Input capture 3 prescaler</description>
  15698. <bitOffset>2</bitOffset>
  15699. <bitWidth>2</bitWidth>
  15700. </field>
  15701. <field>
  15702. <name>CC3S</name>
  15703. <description>Capture/Compare 3
  15704. selection</description>
  15705. <bitOffset>0</bitOffset>
  15706. <bitWidth>2</bitWidth>
  15707. </field>
  15708. </fields>
  15709. </register>
  15710. <register>
  15711. <name>CCER</name>
  15712. <displayName>CCER</displayName>
  15713. <description>capture/compare enable
  15714. register</description>
  15715. <addressOffset>0x20</addressOffset>
  15716. <size>0x20</size>
  15717. <access>read-write</access>
  15718. <resetValue>0x0000</resetValue>
  15719. <fields>
  15720. <field>
  15721. <name>CC4NP</name>
  15722. <description>Capture/Compare 4 output
  15723. Polarity</description>
  15724. <bitOffset>15</bitOffset>
  15725. <bitWidth>1</bitWidth>
  15726. </field>
  15727. <field>
  15728. <name>CC4P</name>
  15729. <description>Capture/Compare 3 output
  15730. Polarity</description>
  15731. <bitOffset>13</bitOffset>
  15732. <bitWidth>1</bitWidth>
  15733. </field>
  15734. <field>
  15735. <name>CC4E</name>
  15736. <description>Capture/Compare 4 output
  15737. enable</description>
  15738. <bitOffset>12</bitOffset>
  15739. <bitWidth>1</bitWidth>
  15740. </field>
  15741. <field>
  15742. <name>CC3NP</name>
  15743. <description>Capture/Compare 3 output
  15744. Polarity</description>
  15745. <bitOffset>11</bitOffset>
  15746. <bitWidth>1</bitWidth>
  15747. </field>
  15748. <field>
  15749. <name>CC3P</name>
  15750. <description>Capture/Compare 3 output
  15751. Polarity</description>
  15752. <bitOffset>9</bitOffset>
  15753. <bitWidth>1</bitWidth>
  15754. </field>
  15755. <field>
  15756. <name>CC3E</name>
  15757. <description>Capture/Compare 3 output
  15758. enable</description>
  15759. <bitOffset>8</bitOffset>
  15760. <bitWidth>1</bitWidth>
  15761. </field>
  15762. <field>
  15763. <name>CC2NP</name>
  15764. <description>Capture/Compare 2 output
  15765. Polarity</description>
  15766. <bitOffset>7</bitOffset>
  15767. <bitWidth>1</bitWidth>
  15768. </field>
  15769. <field>
  15770. <name>CC2P</name>
  15771. <description>Capture/Compare 2 output
  15772. Polarity</description>
  15773. <bitOffset>5</bitOffset>
  15774. <bitWidth>1</bitWidth>
  15775. </field>
  15776. <field>
  15777. <name>CC2E</name>
  15778. <description>Capture/Compare 2 output
  15779. enable</description>
  15780. <bitOffset>4</bitOffset>
  15781. <bitWidth>1</bitWidth>
  15782. </field>
  15783. <field>
  15784. <name>CC1NP</name>
  15785. <description>Capture/Compare 1 output
  15786. Polarity</description>
  15787. <bitOffset>3</bitOffset>
  15788. <bitWidth>1</bitWidth>
  15789. </field>
  15790. <field>
  15791. <name>CC1P</name>
  15792. <description>Capture/Compare 1 output
  15793. Polarity</description>
  15794. <bitOffset>1</bitOffset>
  15795. <bitWidth>1</bitWidth>
  15796. </field>
  15797. <field>
  15798. <name>CC1E</name>
  15799. <description>Capture/Compare 1 output
  15800. enable</description>
  15801. <bitOffset>0</bitOffset>
  15802. <bitWidth>1</bitWidth>
  15803. </field>
  15804. </fields>
  15805. </register>
  15806. <register>
  15807. <name>CNT</name>
  15808. <displayName>CNT</displayName>
  15809. <description>counter</description>
  15810. <addressOffset>0x24</addressOffset>
  15811. <size>0x20</size>
  15812. <access>read-write</access>
  15813. <resetValue>0x00000000</resetValue>
  15814. <fields>
  15815. <field>
  15816. <name>CNT_H</name>
  15817. <description>High counter value (TIM2
  15818. only)</description>
  15819. <bitOffset>16</bitOffset>
  15820. <bitWidth>16</bitWidth>
  15821. </field>
  15822. <field>
  15823. <name>CNT_L</name>
  15824. <description>Low counter value</description>
  15825. <bitOffset>0</bitOffset>
  15826. <bitWidth>16</bitWidth>
  15827. </field>
  15828. </fields>
  15829. </register>
  15830. <register>
  15831. <name>PSC</name>
  15832. <displayName>PSC</displayName>
  15833. <description>prescaler</description>
  15834. <addressOffset>0x28</addressOffset>
  15835. <size>0x20</size>
  15836. <access>read-write</access>
  15837. <resetValue>0x0000</resetValue>
  15838. <fields>
  15839. <field>
  15840. <name>PSC</name>
  15841. <description>Prescaler value</description>
  15842. <bitOffset>0</bitOffset>
  15843. <bitWidth>16</bitWidth>
  15844. </field>
  15845. </fields>
  15846. </register>
  15847. <register>
  15848. <name>ARR</name>
  15849. <displayName>ARR</displayName>
  15850. <description>auto-reload register</description>
  15851. <addressOffset>0x2C</addressOffset>
  15852. <size>0x20</size>
  15853. <access>read-write</access>
  15854. <resetValue>0x00000000</resetValue>
  15855. <fields>
  15856. <field>
  15857. <name>ARR_H</name>
  15858. <description>High Auto-reload value (TIM2
  15859. only)</description>
  15860. <bitOffset>16</bitOffset>
  15861. <bitWidth>16</bitWidth>
  15862. </field>
  15863. <field>
  15864. <name>ARR_L</name>
  15865. <description>Low Auto-reload value</description>
  15866. <bitOffset>0</bitOffset>
  15867. <bitWidth>16</bitWidth>
  15868. </field>
  15869. </fields>
  15870. </register>
  15871. <register>
  15872. <name>CCR1</name>
  15873. <displayName>CCR1</displayName>
  15874. <description>capture/compare register 1</description>
  15875. <addressOffset>0x34</addressOffset>
  15876. <size>0x20</size>
  15877. <access>read-write</access>
  15878. <resetValue>0x00000000</resetValue>
  15879. <fields>
  15880. <field>
  15881. <name>CCR1_H</name>
  15882. <description>High Capture/Compare 1 value (TIM2
  15883. only)</description>
  15884. <bitOffset>16</bitOffset>
  15885. <bitWidth>16</bitWidth>
  15886. </field>
  15887. <field>
  15888. <name>CCR1_L</name>
  15889. <description>Low Capture/Compare 1
  15890. value</description>
  15891. <bitOffset>0</bitOffset>
  15892. <bitWidth>16</bitWidth>
  15893. </field>
  15894. </fields>
  15895. </register>
  15896. <register>
  15897. <name>CCR2</name>
  15898. <displayName>CCR2</displayName>
  15899. <description>capture/compare register 2</description>
  15900. <addressOffset>0x38</addressOffset>
  15901. <size>0x20</size>
  15902. <access>read-write</access>
  15903. <resetValue>0x00000000</resetValue>
  15904. <fields>
  15905. <field>
  15906. <name>CCR2_H</name>
  15907. <description>High Capture/Compare 2 value (TIM2
  15908. only)</description>
  15909. <bitOffset>16</bitOffset>
  15910. <bitWidth>16</bitWidth>
  15911. </field>
  15912. <field>
  15913. <name>CCR2_L</name>
  15914. <description>Low Capture/Compare 2
  15915. value</description>
  15916. <bitOffset>0</bitOffset>
  15917. <bitWidth>16</bitWidth>
  15918. </field>
  15919. </fields>
  15920. </register>
  15921. <register>
  15922. <name>CCR3</name>
  15923. <displayName>CCR3</displayName>
  15924. <description>capture/compare register 3</description>
  15925. <addressOffset>0x3C</addressOffset>
  15926. <size>0x20</size>
  15927. <access>read-write</access>
  15928. <resetValue>0x00000000</resetValue>
  15929. <fields>
  15930. <field>
  15931. <name>CCR3_H</name>
  15932. <description>High Capture/Compare value (TIM2
  15933. only)</description>
  15934. <bitOffset>16</bitOffset>
  15935. <bitWidth>16</bitWidth>
  15936. </field>
  15937. <field>
  15938. <name>CCR3_L</name>
  15939. <description>Low Capture/Compare value</description>
  15940. <bitOffset>0</bitOffset>
  15941. <bitWidth>16</bitWidth>
  15942. </field>
  15943. </fields>
  15944. </register>
  15945. <register>
  15946. <name>CCR4</name>
  15947. <displayName>CCR4</displayName>
  15948. <description>capture/compare register 4</description>
  15949. <addressOffset>0x40</addressOffset>
  15950. <size>0x20</size>
  15951. <access>read-write</access>
  15952. <resetValue>0x00000000</resetValue>
  15953. <fields>
  15954. <field>
  15955. <name>CCR4_H</name>
  15956. <description>High Capture/Compare value (TIM2
  15957. only)</description>
  15958. <bitOffset>16</bitOffset>
  15959. <bitWidth>16</bitWidth>
  15960. </field>
  15961. <field>
  15962. <name>CCR4_L</name>
  15963. <description>Low Capture/Compare value</description>
  15964. <bitOffset>0</bitOffset>
  15965. <bitWidth>16</bitWidth>
  15966. </field>
  15967. </fields>
  15968. </register>
  15969. <register>
  15970. <name>DCR</name>
  15971. <displayName>DCR</displayName>
  15972. <description>DMA control register</description>
  15973. <addressOffset>0x48</addressOffset>
  15974. <size>0x20</size>
  15975. <access>read-write</access>
  15976. <resetValue>0x0000</resetValue>
  15977. <fields>
  15978. <field>
  15979. <name>DBL</name>
  15980. <description>DMA burst length</description>
  15981. <bitOffset>8</bitOffset>
  15982. <bitWidth>5</bitWidth>
  15983. </field>
  15984. <field>
  15985. <name>DBA</name>
  15986. <description>DMA base address</description>
  15987. <bitOffset>0</bitOffset>
  15988. <bitWidth>5</bitWidth>
  15989. </field>
  15990. </fields>
  15991. </register>
  15992. <register>
  15993. <name>DMAR</name>
  15994. <displayName>DMAR</displayName>
  15995. <description>DMA address for full transfer</description>
  15996. <addressOffset>0x4C</addressOffset>
  15997. <size>0x20</size>
  15998. <access>read-write</access>
  15999. <resetValue>0x0000</resetValue>
  16000. <fields>
  16001. <field>
  16002. <name>DMAB</name>
  16003. <description>DMA register for burst
  16004. accesses</description>
  16005. <bitOffset>0</bitOffset>
  16006. <bitWidth>16</bitWidth>
  16007. </field>
  16008. </fields>
  16009. </register>
  16010. <register>
  16011. <name>OR</name>
  16012. <displayName>OR</displayName>
  16013. <description>TIM2 option register</description>
  16014. <addressOffset>0x50</addressOffset>
  16015. <size>0x20</size>
  16016. <access>read-write</access>
  16017. <resetValue>0x0000</resetValue>
  16018. <fields>
  16019. <field>
  16020. <name>ETR_RMP</name>
  16021. <description>Timer2 ETR remap</description>
  16022. <bitOffset>0</bitOffset>
  16023. <bitWidth>3</bitWidth>
  16024. </field>
  16025. <field>
  16026. <name>TI4_RMP</name>
  16027. <description>Internal trigger</description>
  16028. <bitOffset>3</bitOffset>
  16029. <bitWidth>2</bitWidth>
  16030. </field>
  16031. </fields>
  16032. </register>
  16033. </registers>
  16034. </peripheral>
  16035. <peripheral>
  16036. <name>TIM6</name>
  16037. <description>Basic-timers</description>
  16038. <groupName>TIM</groupName>
  16039. <baseAddress>0x40001000</baseAddress>
  16040. <addressBlock>
  16041. <offset>0x0</offset>
  16042. <size>0x400</size>
  16043. <usage>registers</usage>
  16044. </addressBlock>
  16045. <interrupt>
  16046. <name>TIM6_DAC</name>
  16047. <description>TIM6 global interrupt and DAC</description>
  16048. <value>17</value>
  16049. </interrupt>
  16050. <registers>
  16051. <register>
  16052. <name>CR1</name>
  16053. <displayName>CR1</displayName>
  16054. <description>control register 1</description>
  16055. <addressOffset>0x0</addressOffset>
  16056. <size>0x20</size>
  16057. <access>read-write</access>
  16058. <resetValue>0x0000</resetValue>
  16059. <fields>
  16060. <field>
  16061. <name>ARPE</name>
  16062. <description>Auto-reload preload enable</description>
  16063. <bitOffset>7</bitOffset>
  16064. <bitWidth>1</bitWidth>
  16065. </field>
  16066. <field>
  16067. <name>OPM</name>
  16068. <description>One-pulse mode</description>
  16069. <bitOffset>3</bitOffset>
  16070. <bitWidth>1</bitWidth>
  16071. </field>
  16072. <field>
  16073. <name>URS</name>
  16074. <description>Update request source</description>
  16075. <bitOffset>2</bitOffset>
  16076. <bitWidth>1</bitWidth>
  16077. </field>
  16078. <field>
  16079. <name>UDIS</name>
  16080. <description>Update disable</description>
  16081. <bitOffset>1</bitOffset>
  16082. <bitWidth>1</bitWidth>
  16083. </field>
  16084. <field>
  16085. <name>CEN</name>
  16086. <description>Counter enable</description>
  16087. <bitOffset>0</bitOffset>
  16088. <bitWidth>1</bitWidth>
  16089. </field>
  16090. </fields>
  16091. </register>
  16092. <register>
  16093. <name>CR2</name>
  16094. <displayName>CR2</displayName>
  16095. <description>control register 2</description>
  16096. <addressOffset>0x4</addressOffset>
  16097. <size>0x20</size>
  16098. <access>read-write</access>
  16099. <resetValue>0x0000</resetValue>
  16100. <fields>
  16101. <field>
  16102. <name>MMS</name>
  16103. <description>Master mode selection</description>
  16104. <bitOffset>4</bitOffset>
  16105. <bitWidth>3</bitWidth>
  16106. </field>
  16107. </fields>
  16108. </register>
  16109. <register>
  16110. <name>DIER</name>
  16111. <displayName>DIER</displayName>
  16112. <description>DMA/Interrupt enable register</description>
  16113. <addressOffset>0xC</addressOffset>
  16114. <size>0x20</size>
  16115. <access>read-write</access>
  16116. <resetValue>0x0000</resetValue>
  16117. <fields>
  16118. <field>
  16119. <name>UDE</name>
  16120. <description>Update DMA request enable</description>
  16121. <bitOffset>8</bitOffset>
  16122. <bitWidth>1</bitWidth>
  16123. </field>
  16124. <field>
  16125. <name>UIE</name>
  16126. <description>Update interrupt enable</description>
  16127. <bitOffset>0</bitOffset>
  16128. <bitWidth>1</bitWidth>
  16129. </field>
  16130. </fields>
  16131. </register>
  16132. <register>
  16133. <name>SR</name>
  16134. <displayName>SR</displayName>
  16135. <description>status register</description>
  16136. <addressOffset>0x10</addressOffset>
  16137. <size>0x20</size>
  16138. <access>read-write</access>
  16139. <resetValue>0x0000</resetValue>
  16140. <fields>
  16141. <field>
  16142. <name>UIF</name>
  16143. <description>Update interrupt flag</description>
  16144. <bitOffset>0</bitOffset>
  16145. <bitWidth>1</bitWidth>
  16146. </field>
  16147. </fields>
  16148. </register>
  16149. <register>
  16150. <name>EGR</name>
  16151. <displayName>EGR</displayName>
  16152. <description>event generation register</description>
  16153. <addressOffset>0x14</addressOffset>
  16154. <size>0x20</size>
  16155. <access>write-only</access>
  16156. <resetValue>0x0000</resetValue>
  16157. <fields>
  16158. <field>
  16159. <name>UG</name>
  16160. <description>Update generation</description>
  16161. <bitOffset>0</bitOffset>
  16162. <bitWidth>1</bitWidth>
  16163. </field>
  16164. </fields>
  16165. </register>
  16166. <register>
  16167. <name>CNT</name>
  16168. <displayName>CNT</displayName>
  16169. <description>counter</description>
  16170. <addressOffset>0x24</addressOffset>
  16171. <size>0x20</size>
  16172. <access>read-write</access>
  16173. <resetValue>0x00000000</resetValue>
  16174. <fields>
  16175. <field>
  16176. <name>CNT</name>
  16177. <description>Low counter value</description>
  16178. <bitOffset>0</bitOffset>
  16179. <bitWidth>16</bitWidth>
  16180. </field>
  16181. </fields>
  16182. </register>
  16183. <register>
  16184. <name>PSC</name>
  16185. <displayName>PSC</displayName>
  16186. <description>prescaler</description>
  16187. <addressOffset>0x28</addressOffset>
  16188. <size>0x20</size>
  16189. <access>read-write</access>
  16190. <resetValue>0x0000</resetValue>
  16191. <fields>
  16192. <field>
  16193. <name>PSC</name>
  16194. <description>Prescaler value</description>
  16195. <bitOffset>0</bitOffset>
  16196. <bitWidth>16</bitWidth>
  16197. </field>
  16198. </fields>
  16199. </register>
  16200. <register>
  16201. <name>ARR</name>
  16202. <displayName>ARR</displayName>
  16203. <description>auto-reload register</description>
  16204. <addressOffset>0x2C</addressOffset>
  16205. <size>0x20</size>
  16206. <access>read-write</access>
  16207. <resetValue>0x00000000</resetValue>
  16208. <fields>
  16209. <field>
  16210. <name>ARR</name>
  16211. <description>Low Auto-reload value</description>
  16212. <bitOffset>0</bitOffset>
  16213. <bitWidth>16</bitWidth>
  16214. </field>
  16215. </fields>
  16216. </register>
  16217. </registers>
  16218. </peripheral>
  16219. <peripheral>
  16220. <name>TIM21</name>
  16221. <description>General-purpose-timers</description>
  16222. <groupName>TIM</groupName>
  16223. <baseAddress>0x40010800</baseAddress>
  16224. <addressBlock>
  16225. <offset>0x0</offset>
  16226. <size>0x400</size>
  16227. <usage>registers</usage>
  16228. </addressBlock>
  16229. <interrupt>
  16230. <name>TIM21</name>
  16231. <description>TIMER21 global interrupt</description>
  16232. <value>20</value>
  16233. </interrupt>
  16234. <registers>
  16235. <register>
  16236. <name>CR1</name>
  16237. <displayName>CR1</displayName>
  16238. <description>control register 1</description>
  16239. <addressOffset>0x0</addressOffset>
  16240. <size>0x20</size>
  16241. <access>read-write</access>
  16242. <resetValue>0x0000</resetValue>
  16243. <fields>
  16244. <field>
  16245. <name>CEN</name>
  16246. <description>Counter enable</description>
  16247. <bitOffset>0</bitOffset>
  16248. <bitWidth>1</bitWidth>
  16249. </field>
  16250. <field>
  16251. <name>UDIS</name>
  16252. <description>Update disable</description>
  16253. <bitOffset>1</bitOffset>
  16254. <bitWidth>1</bitWidth>
  16255. </field>
  16256. <field>
  16257. <name>URS</name>
  16258. <description>Update request source</description>
  16259. <bitOffset>2</bitOffset>
  16260. <bitWidth>1</bitWidth>
  16261. </field>
  16262. <field>
  16263. <name>OPM</name>
  16264. <description>One-pulse mode</description>
  16265. <bitOffset>3</bitOffset>
  16266. <bitWidth>1</bitWidth>
  16267. </field>
  16268. <field>
  16269. <name>DIR</name>
  16270. <description>Direction</description>
  16271. <bitOffset>4</bitOffset>
  16272. <bitWidth>1</bitWidth>
  16273. </field>
  16274. <field>
  16275. <name>CMS</name>
  16276. <description>Center-aligned mode
  16277. selection</description>
  16278. <bitOffset>5</bitOffset>
  16279. <bitWidth>2</bitWidth>
  16280. </field>
  16281. <field>
  16282. <name>ARPE</name>
  16283. <description>Auto-reload preload enable</description>
  16284. <bitOffset>7</bitOffset>
  16285. <bitWidth>1</bitWidth>
  16286. </field>
  16287. <field>
  16288. <name>CKD</name>
  16289. <description>Clock division</description>
  16290. <bitOffset>8</bitOffset>
  16291. <bitWidth>2</bitWidth>
  16292. </field>
  16293. </fields>
  16294. </register>
  16295. <register>
  16296. <name>CR2</name>
  16297. <displayName>CR2</displayName>
  16298. <description>control register 2</description>
  16299. <addressOffset>0x4</addressOffset>
  16300. <size>0x20</size>
  16301. <access>read-write</access>
  16302. <resetValue>0x0000</resetValue>
  16303. <fields>
  16304. <field>
  16305. <name>MMS</name>
  16306. <description>Master mode selection</description>
  16307. <bitOffset>4</bitOffset>
  16308. <bitWidth>3</bitWidth>
  16309. </field>
  16310. </fields>
  16311. </register>
  16312. <register>
  16313. <name>SMCR</name>
  16314. <displayName>SMCR</displayName>
  16315. <description>slave mode control register</description>
  16316. <addressOffset>0x8</addressOffset>
  16317. <size>0x20</size>
  16318. <access>read-write</access>
  16319. <resetValue>0x0000</resetValue>
  16320. <fields>
  16321. <field>
  16322. <name>SMS</name>
  16323. <description>Slave mode selection</description>
  16324. <bitOffset>0</bitOffset>
  16325. <bitWidth>3</bitWidth>
  16326. </field>
  16327. <field>
  16328. <name>TS</name>
  16329. <description>Trigger selection</description>
  16330. <bitOffset>4</bitOffset>
  16331. <bitWidth>3</bitWidth>
  16332. </field>
  16333. <field>
  16334. <name>MSM</name>
  16335. <description>Master/Slave mode</description>
  16336. <bitOffset>7</bitOffset>
  16337. <bitWidth>1</bitWidth>
  16338. </field>
  16339. <field>
  16340. <name>ETF</name>
  16341. <description>External trigger filter</description>
  16342. <bitOffset>8</bitOffset>
  16343. <bitWidth>4</bitWidth>
  16344. </field>
  16345. <field>
  16346. <name>ETPS</name>
  16347. <description>External trigger prescaler</description>
  16348. <bitOffset>12</bitOffset>
  16349. <bitWidth>2</bitWidth>
  16350. </field>
  16351. <field>
  16352. <name>ECE</name>
  16353. <description>External clock enable</description>
  16354. <bitOffset>14</bitOffset>
  16355. <bitWidth>1</bitWidth>
  16356. </field>
  16357. <field>
  16358. <name>ETP</name>
  16359. <description>External trigger polarity</description>
  16360. <bitOffset>15</bitOffset>
  16361. <bitWidth>1</bitWidth>
  16362. </field>
  16363. </fields>
  16364. </register>
  16365. <register>
  16366. <name>DIER</name>
  16367. <displayName>DIER</displayName>
  16368. <description>DMA/Interrupt enable register</description>
  16369. <addressOffset>0xC</addressOffset>
  16370. <size>0x20</size>
  16371. <access>read-write</access>
  16372. <resetValue>0x0000</resetValue>
  16373. <fields>
  16374. <field>
  16375. <name>TIE</name>
  16376. <description>Trigger interrupt enable</description>
  16377. <bitOffset>6</bitOffset>
  16378. <bitWidth>1</bitWidth>
  16379. </field>
  16380. <field>
  16381. <name>CC2IE</name>
  16382. <description>Capture/Compare 2 interrupt
  16383. enable</description>
  16384. <bitOffset>2</bitOffset>
  16385. <bitWidth>1</bitWidth>
  16386. </field>
  16387. <field>
  16388. <name>CC1IE</name>
  16389. <description>Capture/Compare 1 interrupt
  16390. enable</description>
  16391. <bitOffset>1</bitOffset>
  16392. <bitWidth>1</bitWidth>
  16393. </field>
  16394. <field>
  16395. <name>UIE</name>
  16396. <description>Update interrupt enable</description>
  16397. <bitOffset>0</bitOffset>
  16398. <bitWidth>1</bitWidth>
  16399. </field>
  16400. </fields>
  16401. </register>
  16402. <register>
  16403. <name>SR</name>
  16404. <displayName>SR</displayName>
  16405. <description>status register</description>
  16406. <addressOffset>0x10</addressOffset>
  16407. <size>0x20</size>
  16408. <access>read-write</access>
  16409. <resetValue>0x0000</resetValue>
  16410. <fields>
  16411. <field>
  16412. <name>CC2OF</name>
  16413. <description>Capture/compare 2 overcapture
  16414. flag</description>
  16415. <bitOffset>10</bitOffset>
  16416. <bitWidth>1</bitWidth>
  16417. </field>
  16418. <field>
  16419. <name>CC1OF</name>
  16420. <description>Capture/Compare 1 overcapture
  16421. flag</description>
  16422. <bitOffset>9</bitOffset>
  16423. <bitWidth>1</bitWidth>
  16424. </field>
  16425. <field>
  16426. <name>TIF</name>
  16427. <description>Trigger interrupt flag</description>
  16428. <bitOffset>6</bitOffset>
  16429. <bitWidth>1</bitWidth>
  16430. </field>
  16431. <field>
  16432. <name>CC2IF</name>
  16433. <description>Capture/Compare 2 interrupt
  16434. flag</description>
  16435. <bitOffset>2</bitOffset>
  16436. <bitWidth>1</bitWidth>
  16437. </field>
  16438. <field>
  16439. <name>CC1IF</name>
  16440. <description>Capture/compare 1 interrupt
  16441. flag</description>
  16442. <bitOffset>1</bitOffset>
  16443. <bitWidth>1</bitWidth>
  16444. </field>
  16445. <field>
  16446. <name>UIF</name>
  16447. <description>Update interrupt flag</description>
  16448. <bitOffset>0</bitOffset>
  16449. <bitWidth>1</bitWidth>
  16450. </field>
  16451. </fields>
  16452. </register>
  16453. <register>
  16454. <name>EGR</name>
  16455. <displayName>EGR</displayName>
  16456. <description>event generation register</description>
  16457. <addressOffset>0x14</addressOffset>
  16458. <size>0x20</size>
  16459. <access>write-only</access>
  16460. <resetValue>0x0000</resetValue>
  16461. <fields>
  16462. <field>
  16463. <name>TG</name>
  16464. <description>Trigger generation</description>
  16465. <bitOffset>6</bitOffset>
  16466. <bitWidth>1</bitWidth>
  16467. </field>
  16468. <field>
  16469. <name>CC2G</name>
  16470. <description>Capture/compare 2
  16471. generation</description>
  16472. <bitOffset>2</bitOffset>
  16473. <bitWidth>1</bitWidth>
  16474. </field>
  16475. <field>
  16476. <name>CC1G</name>
  16477. <description>Capture/compare 1
  16478. generation</description>
  16479. <bitOffset>1</bitOffset>
  16480. <bitWidth>1</bitWidth>
  16481. </field>
  16482. <field>
  16483. <name>UG</name>
  16484. <description>Update generation</description>
  16485. <bitOffset>0</bitOffset>
  16486. <bitWidth>1</bitWidth>
  16487. </field>
  16488. </fields>
  16489. </register>
  16490. <register>
  16491. <name>CCMR1_Output</name>
  16492. <displayName>CCMR1_Output</displayName>
  16493. <description>capture/compare mode register (output
  16494. mode)</description>
  16495. <addressOffset>0x18</addressOffset>
  16496. <size>0x20</size>
  16497. <access>read-write</access>
  16498. <resetValue>0x00000000</resetValue>
  16499. <fields>
  16500. <field>
  16501. <name>OC2M</name>
  16502. <description>Output Compare 2 mode</description>
  16503. <bitOffset>12</bitOffset>
  16504. <bitWidth>3</bitWidth>
  16505. </field>
  16506. <field>
  16507. <name>OC2PE</name>
  16508. <description>Output Compare 2 preload
  16509. enable</description>
  16510. <bitOffset>11</bitOffset>
  16511. <bitWidth>1</bitWidth>
  16512. </field>
  16513. <field>
  16514. <name>OC2FE</name>
  16515. <description>Output Compare 2 fast
  16516. enable</description>
  16517. <bitOffset>10</bitOffset>
  16518. <bitWidth>1</bitWidth>
  16519. </field>
  16520. <field>
  16521. <name>CC2S</name>
  16522. <description>Capture/Compare 2
  16523. selection</description>
  16524. <bitOffset>8</bitOffset>
  16525. <bitWidth>2</bitWidth>
  16526. </field>
  16527. <field>
  16528. <name>OC1M</name>
  16529. <description>Output Compare 1 mode</description>
  16530. <bitOffset>4</bitOffset>
  16531. <bitWidth>3</bitWidth>
  16532. </field>
  16533. <field>
  16534. <name>OC1PE</name>
  16535. <description>Output Compare 1 preload
  16536. enable</description>
  16537. <bitOffset>3</bitOffset>
  16538. <bitWidth>1</bitWidth>
  16539. </field>
  16540. <field>
  16541. <name>OC1FE</name>
  16542. <description>Output Compare 1 fast
  16543. enable</description>
  16544. <bitOffset>2</bitOffset>
  16545. <bitWidth>1</bitWidth>
  16546. </field>
  16547. <field>
  16548. <name>CC1S</name>
  16549. <description>Capture/Compare 1
  16550. selection</description>
  16551. <bitOffset>0</bitOffset>
  16552. <bitWidth>2</bitWidth>
  16553. </field>
  16554. </fields>
  16555. </register>
  16556. <register>
  16557. <name>CCMR1_Input</name>
  16558. <displayName>CCMR1_Input</displayName>
  16559. <description>capture/compare mode register 1 (input
  16560. mode)</description>
  16561. <alternateRegister>CCMR1_Output</alternateRegister>
  16562. <addressOffset>0x18</addressOffset>
  16563. <size>0x20</size>
  16564. <access>read-write</access>
  16565. <resetValue>0x00000000</resetValue>
  16566. <fields>
  16567. <field>
  16568. <name>IC2F</name>
  16569. <description>Input capture 2 filter</description>
  16570. <bitOffset>12</bitOffset>
  16571. <bitWidth>4</bitWidth>
  16572. </field>
  16573. <field>
  16574. <name>IC2PSC</name>
  16575. <description>Input capture 2 prescaler</description>
  16576. <bitOffset>10</bitOffset>
  16577. <bitWidth>2</bitWidth>
  16578. </field>
  16579. <field>
  16580. <name>CC2S</name>
  16581. <description>Capture/Compare 2
  16582. selection</description>
  16583. <bitOffset>8</bitOffset>
  16584. <bitWidth>2</bitWidth>
  16585. </field>
  16586. <field>
  16587. <name>IC1F</name>
  16588. <description>Input capture 1 filter</description>
  16589. <bitOffset>4</bitOffset>
  16590. <bitWidth>4</bitWidth>
  16591. </field>
  16592. <field>
  16593. <name>IC1PSC</name>
  16594. <description>Input capture 1 prescaler</description>
  16595. <bitOffset>2</bitOffset>
  16596. <bitWidth>2</bitWidth>
  16597. </field>
  16598. <field>
  16599. <name>CC1S</name>
  16600. <description>Capture/Compare 1
  16601. selection</description>
  16602. <bitOffset>0</bitOffset>
  16603. <bitWidth>2</bitWidth>
  16604. </field>
  16605. </fields>
  16606. </register>
  16607. <register>
  16608. <name>CCER</name>
  16609. <displayName>CCER</displayName>
  16610. <description>capture/compare enable
  16611. register</description>
  16612. <addressOffset>0x20</addressOffset>
  16613. <size>0x20</size>
  16614. <access>read-write</access>
  16615. <resetValue>0x0000</resetValue>
  16616. <fields>
  16617. <field>
  16618. <name>CC2NP</name>
  16619. <description>Capture/Compare 2 output
  16620. Polarity</description>
  16621. <bitOffset>7</bitOffset>
  16622. <bitWidth>1</bitWidth>
  16623. </field>
  16624. <field>
  16625. <name>CC2P</name>
  16626. <description>Capture/Compare 2 output
  16627. Polarity</description>
  16628. <bitOffset>5</bitOffset>
  16629. <bitWidth>1</bitWidth>
  16630. </field>
  16631. <field>
  16632. <name>CC2E</name>
  16633. <description>Capture/Compare 2 output
  16634. enable</description>
  16635. <bitOffset>4</bitOffset>
  16636. <bitWidth>1</bitWidth>
  16637. </field>
  16638. <field>
  16639. <name>CC1NP</name>
  16640. <description>Capture/Compare 1 output
  16641. Polarity</description>
  16642. <bitOffset>3</bitOffset>
  16643. <bitWidth>1</bitWidth>
  16644. </field>
  16645. <field>
  16646. <name>CC1P</name>
  16647. <description>Capture/Compare 1 output
  16648. Polarity</description>
  16649. <bitOffset>1</bitOffset>
  16650. <bitWidth>1</bitWidth>
  16651. </field>
  16652. <field>
  16653. <name>CC1E</name>
  16654. <description>Capture/Compare 1 output
  16655. enable</description>
  16656. <bitOffset>0</bitOffset>
  16657. <bitWidth>1</bitWidth>
  16658. </field>
  16659. </fields>
  16660. </register>
  16661. <register>
  16662. <name>CNT</name>
  16663. <displayName>CNT</displayName>
  16664. <description>counter</description>
  16665. <addressOffset>0x24</addressOffset>
  16666. <size>0x20</size>
  16667. <access>read-write</access>
  16668. <resetValue>0x00000000</resetValue>
  16669. <fields>
  16670. <field>
  16671. <name>CNT</name>
  16672. <description>counter value</description>
  16673. <bitOffset>0</bitOffset>
  16674. <bitWidth>16</bitWidth>
  16675. </field>
  16676. </fields>
  16677. </register>
  16678. <register>
  16679. <name>PSC</name>
  16680. <displayName>PSC</displayName>
  16681. <description>prescaler</description>
  16682. <addressOffset>0x28</addressOffset>
  16683. <size>0x20</size>
  16684. <access>read-write</access>
  16685. <resetValue>0x0000</resetValue>
  16686. <fields>
  16687. <field>
  16688. <name>PSC</name>
  16689. <description>Prescaler value</description>
  16690. <bitOffset>0</bitOffset>
  16691. <bitWidth>16</bitWidth>
  16692. </field>
  16693. </fields>
  16694. </register>
  16695. <register>
  16696. <name>ARR</name>
  16697. <displayName>ARR</displayName>
  16698. <description>auto-reload register</description>
  16699. <addressOffset>0x2C</addressOffset>
  16700. <size>0x20</size>
  16701. <access>read-write</access>
  16702. <resetValue>0x00000000</resetValue>
  16703. <fields>
  16704. <field>
  16705. <name>ARR</name>
  16706. <description>Auto-reload value</description>
  16707. <bitOffset>0</bitOffset>
  16708. <bitWidth>16</bitWidth>
  16709. </field>
  16710. </fields>
  16711. </register>
  16712. <register>
  16713. <name>CCR1</name>
  16714. <displayName>CCR1</displayName>
  16715. <description>capture/compare register 1</description>
  16716. <addressOffset>0x34</addressOffset>
  16717. <size>0x20</size>
  16718. <access>read-write</access>
  16719. <resetValue>0x00000000</resetValue>
  16720. <fields>
  16721. <field>
  16722. <name>CCR1</name>
  16723. <description>Capture/Compare 1 value</description>
  16724. <bitOffset>0</bitOffset>
  16725. <bitWidth>16</bitWidth>
  16726. </field>
  16727. </fields>
  16728. </register>
  16729. <register>
  16730. <name>CCR2</name>
  16731. <displayName>CCR2</displayName>
  16732. <description>capture/compare register 2</description>
  16733. <addressOffset>0x38</addressOffset>
  16734. <size>0x20</size>
  16735. <access>read-write</access>
  16736. <resetValue>0x00000000</resetValue>
  16737. <fields>
  16738. <field>
  16739. <name>CCR2</name>
  16740. <description>Capture/Compare 2 value</description>
  16741. <bitOffset>0</bitOffset>
  16742. <bitWidth>16</bitWidth>
  16743. </field>
  16744. </fields>
  16745. </register>
  16746. <register>
  16747. <name>OR</name>
  16748. <displayName>OR</displayName>
  16749. <description>TIM21 option register</description>
  16750. <addressOffset>0x50</addressOffset>
  16751. <size>0x20</size>
  16752. <access>read-write</access>
  16753. <resetValue>0x00000000</resetValue>
  16754. <fields>
  16755. <field>
  16756. <name>ETR_RMP</name>
  16757. <description>Timer21 ETR remap</description>
  16758. <bitOffset>0</bitOffset>
  16759. <bitWidth>2</bitWidth>
  16760. </field>
  16761. <field>
  16762. <name>TI1_RMP</name>
  16763. <description>Timer21 TI1</description>
  16764. <bitOffset>2</bitOffset>
  16765. <bitWidth>3</bitWidth>
  16766. </field>
  16767. <field>
  16768. <name>TI2_RMP</name>
  16769. <description>Timer21 TI2</description>
  16770. <bitOffset>5</bitOffset>
  16771. <bitWidth>1</bitWidth>
  16772. </field>
  16773. </fields>
  16774. </register>
  16775. </registers>
  16776. </peripheral>
  16777. <peripheral>
  16778. <name>TIM22</name>
  16779. <description>General-purpose-timers</description>
  16780. <groupName>TIM</groupName>
  16781. <baseAddress>0x40011400</baseAddress>
  16782. <addressBlock>
  16783. <offset>0x0</offset>
  16784. <size>0x400</size>
  16785. <usage>registers</usage>
  16786. </addressBlock>
  16787. <interrupt>
  16788. <name>TIM22</name>
  16789. <description>TIMER22 global interrupt</description>
  16790. <value>22</value>
  16791. </interrupt>
  16792. <registers>
  16793. <register>
  16794. <name>CR1</name>
  16795. <displayName>CR1</displayName>
  16796. <description>control register 1</description>
  16797. <addressOffset>0x0</addressOffset>
  16798. <size>0x20</size>
  16799. <access>read-write</access>
  16800. <resetValue>0x0000</resetValue>
  16801. <fields>
  16802. <field>
  16803. <name>CEN</name>
  16804. <description>Counter enable</description>
  16805. <bitOffset>0</bitOffset>
  16806. <bitWidth>1</bitWidth>
  16807. </field>
  16808. <field>
  16809. <name>UDIS</name>
  16810. <description>Update disable</description>
  16811. <bitOffset>1</bitOffset>
  16812. <bitWidth>1</bitWidth>
  16813. </field>
  16814. <field>
  16815. <name>URS</name>
  16816. <description>Update request source</description>
  16817. <bitOffset>2</bitOffset>
  16818. <bitWidth>1</bitWidth>
  16819. </field>
  16820. <field>
  16821. <name>OPM</name>
  16822. <description>One-pulse mode</description>
  16823. <bitOffset>3</bitOffset>
  16824. <bitWidth>1</bitWidth>
  16825. </field>
  16826. <field>
  16827. <name>DIR</name>
  16828. <description>Direction</description>
  16829. <bitOffset>4</bitOffset>
  16830. <bitWidth>1</bitWidth>
  16831. </field>
  16832. <field>
  16833. <name>CMS</name>
  16834. <description>Center-aligned mode
  16835. selection</description>
  16836. <bitOffset>5</bitOffset>
  16837. <bitWidth>2</bitWidth>
  16838. </field>
  16839. <field>
  16840. <name>ARPE</name>
  16841. <description>Auto-reload preload enable</description>
  16842. <bitOffset>7</bitOffset>
  16843. <bitWidth>1</bitWidth>
  16844. </field>
  16845. <field>
  16846. <name>CKD</name>
  16847. <description>Clock division</description>
  16848. <bitOffset>8</bitOffset>
  16849. <bitWidth>2</bitWidth>
  16850. </field>
  16851. </fields>
  16852. </register>
  16853. <register>
  16854. <name>CR2</name>
  16855. <displayName>CR2</displayName>
  16856. <description>control register 2</description>
  16857. <addressOffset>0x4</addressOffset>
  16858. <size>0x20</size>
  16859. <access>read-write</access>
  16860. <resetValue>0x0000</resetValue>
  16861. <fields>
  16862. <field>
  16863. <name>MMS</name>
  16864. <description>Master mode selection</description>
  16865. <bitOffset>4</bitOffset>
  16866. <bitWidth>3</bitWidth>
  16867. </field>
  16868. </fields>
  16869. </register>
  16870. <register>
  16871. <name>SMCR</name>
  16872. <displayName>SMCR</displayName>
  16873. <description>slave mode control register</description>
  16874. <addressOffset>0x8</addressOffset>
  16875. <size>0x20</size>
  16876. <access>read-write</access>
  16877. <resetValue>0x0000</resetValue>
  16878. <fields>
  16879. <field>
  16880. <name>SMS</name>
  16881. <description>Slave mode selection</description>
  16882. <bitOffset>0</bitOffset>
  16883. <bitWidth>3</bitWidth>
  16884. </field>
  16885. <field>
  16886. <name>TS</name>
  16887. <description>Trigger selection</description>
  16888. <bitOffset>4</bitOffset>
  16889. <bitWidth>3</bitWidth>
  16890. </field>
  16891. <field>
  16892. <name>MSM</name>
  16893. <description>Master/Slave mode</description>
  16894. <bitOffset>7</bitOffset>
  16895. <bitWidth>1</bitWidth>
  16896. </field>
  16897. <field>
  16898. <name>ETF</name>
  16899. <description>External trigger filter</description>
  16900. <bitOffset>8</bitOffset>
  16901. <bitWidth>4</bitWidth>
  16902. </field>
  16903. <field>
  16904. <name>ETPS</name>
  16905. <description>External trigger prescaler</description>
  16906. <bitOffset>12</bitOffset>
  16907. <bitWidth>2</bitWidth>
  16908. </field>
  16909. <field>
  16910. <name>ECE</name>
  16911. <description>External clock enable</description>
  16912. <bitOffset>14</bitOffset>
  16913. <bitWidth>1</bitWidth>
  16914. </field>
  16915. <field>
  16916. <name>ETP</name>
  16917. <description>External trigger polarity</description>
  16918. <bitOffset>15</bitOffset>
  16919. <bitWidth>1</bitWidth>
  16920. </field>
  16921. </fields>
  16922. </register>
  16923. <register>
  16924. <name>DIER</name>
  16925. <displayName>DIER</displayName>
  16926. <description>DMA/Interrupt enable register</description>
  16927. <addressOffset>0xC</addressOffset>
  16928. <size>0x20</size>
  16929. <access>read-write</access>
  16930. <resetValue>0x0000</resetValue>
  16931. <fields>
  16932. <field>
  16933. <name>TIE</name>
  16934. <description>Trigger interrupt enable</description>
  16935. <bitOffset>6</bitOffset>
  16936. <bitWidth>1</bitWidth>
  16937. </field>
  16938. <field>
  16939. <name>CC2IE</name>
  16940. <description>Capture/Compare 2 interrupt
  16941. enable</description>
  16942. <bitOffset>2</bitOffset>
  16943. <bitWidth>1</bitWidth>
  16944. </field>
  16945. <field>
  16946. <name>CC1IE</name>
  16947. <description>Capture/Compare 1 interrupt
  16948. enable</description>
  16949. <bitOffset>1</bitOffset>
  16950. <bitWidth>1</bitWidth>
  16951. </field>
  16952. <field>
  16953. <name>UIE</name>
  16954. <description>Update interrupt enable</description>
  16955. <bitOffset>0</bitOffset>
  16956. <bitWidth>1</bitWidth>
  16957. </field>
  16958. </fields>
  16959. </register>
  16960. <register>
  16961. <name>SR</name>
  16962. <displayName>SR</displayName>
  16963. <description>status register</description>
  16964. <addressOffset>0x10</addressOffset>
  16965. <size>0x20</size>
  16966. <access>read-write</access>
  16967. <resetValue>0x0000</resetValue>
  16968. <fields>
  16969. <field>
  16970. <name>CC2OF</name>
  16971. <description>Capture/compare 2 overcapture
  16972. flag</description>
  16973. <bitOffset>10</bitOffset>
  16974. <bitWidth>1</bitWidth>
  16975. </field>
  16976. <field>
  16977. <name>CC1OF</name>
  16978. <description>Capture/Compare 1 overcapture
  16979. flag</description>
  16980. <bitOffset>9</bitOffset>
  16981. <bitWidth>1</bitWidth>
  16982. </field>
  16983. <field>
  16984. <name>TIF</name>
  16985. <description>Trigger interrupt flag</description>
  16986. <bitOffset>6</bitOffset>
  16987. <bitWidth>1</bitWidth>
  16988. </field>
  16989. <field>
  16990. <name>CC2IF</name>
  16991. <description>Capture/Compare 2 interrupt
  16992. flag</description>
  16993. <bitOffset>2</bitOffset>
  16994. <bitWidth>1</bitWidth>
  16995. </field>
  16996. <field>
  16997. <name>CC1IF</name>
  16998. <description>Capture/compare 1 interrupt
  16999. flag</description>
  17000. <bitOffset>1</bitOffset>
  17001. <bitWidth>1</bitWidth>
  17002. </field>
  17003. <field>
  17004. <name>UIF</name>
  17005. <description>Update interrupt flag</description>
  17006. <bitOffset>0</bitOffset>
  17007. <bitWidth>1</bitWidth>
  17008. </field>
  17009. </fields>
  17010. </register>
  17011. <register>
  17012. <name>EGR</name>
  17013. <displayName>EGR</displayName>
  17014. <description>event generation register</description>
  17015. <addressOffset>0x14</addressOffset>
  17016. <size>0x20</size>
  17017. <access>write-only</access>
  17018. <resetValue>0x0000</resetValue>
  17019. <fields>
  17020. <field>
  17021. <name>TG</name>
  17022. <description>Trigger generation</description>
  17023. <bitOffset>6</bitOffset>
  17024. <bitWidth>1</bitWidth>
  17025. </field>
  17026. <field>
  17027. <name>CC2G</name>
  17028. <description>Capture/compare 2
  17029. generation</description>
  17030. <bitOffset>2</bitOffset>
  17031. <bitWidth>1</bitWidth>
  17032. </field>
  17033. <field>
  17034. <name>CC1G</name>
  17035. <description>Capture/compare 1
  17036. generation</description>
  17037. <bitOffset>1</bitOffset>
  17038. <bitWidth>1</bitWidth>
  17039. </field>
  17040. <field>
  17041. <name>UG</name>
  17042. <description>Update generation</description>
  17043. <bitOffset>0</bitOffset>
  17044. <bitWidth>1</bitWidth>
  17045. </field>
  17046. </fields>
  17047. </register>
  17048. <register>
  17049. <name>CCMR1_Output</name>
  17050. <displayName>CCMR1_Output</displayName>
  17051. <description>capture/compare mode register (output
  17052. mode)</description>
  17053. <addressOffset>0x18</addressOffset>
  17054. <size>0x20</size>
  17055. <access>read-write</access>
  17056. <resetValue>0x00000000</resetValue>
  17057. <fields>
  17058. <field>
  17059. <name>OC2M</name>
  17060. <description>Output Compare 2 mode</description>
  17061. <bitOffset>12</bitOffset>
  17062. <bitWidth>3</bitWidth>
  17063. </field>
  17064. <field>
  17065. <name>OC2PE</name>
  17066. <description>Output Compare 2 preload
  17067. enable</description>
  17068. <bitOffset>11</bitOffset>
  17069. <bitWidth>1</bitWidth>
  17070. </field>
  17071. <field>
  17072. <name>OC2FE</name>
  17073. <description>Output Compare 2 fast
  17074. enable</description>
  17075. <bitOffset>10</bitOffset>
  17076. <bitWidth>1</bitWidth>
  17077. </field>
  17078. <field>
  17079. <name>CC2S</name>
  17080. <description>Capture/Compare 2
  17081. selection</description>
  17082. <bitOffset>8</bitOffset>
  17083. <bitWidth>2</bitWidth>
  17084. </field>
  17085. <field>
  17086. <name>OC1M</name>
  17087. <description>Output Compare 1 mode</description>
  17088. <bitOffset>4</bitOffset>
  17089. <bitWidth>3</bitWidth>
  17090. </field>
  17091. <field>
  17092. <name>OC1PE</name>
  17093. <description>Output Compare 1 preload
  17094. enable</description>
  17095. <bitOffset>3</bitOffset>
  17096. <bitWidth>1</bitWidth>
  17097. </field>
  17098. <field>
  17099. <name>OC1FE</name>
  17100. <description>Output Compare 1 fast
  17101. enable</description>
  17102. <bitOffset>2</bitOffset>
  17103. <bitWidth>1</bitWidth>
  17104. </field>
  17105. <field>
  17106. <name>CC1S</name>
  17107. <description>Capture/Compare 1
  17108. selection</description>
  17109. <bitOffset>0</bitOffset>
  17110. <bitWidth>2</bitWidth>
  17111. </field>
  17112. </fields>
  17113. </register>
  17114. <register>
  17115. <name>CCMR1_Input</name>
  17116. <displayName>CCMR1_Input</displayName>
  17117. <description>capture/compare mode register 1 (input
  17118. mode)</description>
  17119. <alternateRegister>CCMR1_Output</alternateRegister>
  17120. <addressOffset>0x18</addressOffset>
  17121. <size>0x20</size>
  17122. <access>read-write</access>
  17123. <resetValue>0x00000000</resetValue>
  17124. <fields>
  17125. <field>
  17126. <name>IC2F</name>
  17127. <description>Input capture 2 filter</description>
  17128. <bitOffset>12</bitOffset>
  17129. <bitWidth>4</bitWidth>
  17130. </field>
  17131. <field>
  17132. <name>IC2PSC</name>
  17133. <description>Input capture 2 prescaler</description>
  17134. <bitOffset>10</bitOffset>
  17135. <bitWidth>2</bitWidth>
  17136. </field>
  17137. <field>
  17138. <name>CC2S</name>
  17139. <description>Capture/Compare 2
  17140. selection</description>
  17141. <bitOffset>8</bitOffset>
  17142. <bitWidth>2</bitWidth>
  17143. </field>
  17144. <field>
  17145. <name>IC1F</name>
  17146. <description>Input capture 1 filter</description>
  17147. <bitOffset>4</bitOffset>
  17148. <bitWidth>4</bitWidth>
  17149. </field>
  17150. <field>
  17151. <name>IC1PSC</name>
  17152. <description>Input capture 1 prescaler</description>
  17153. <bitOffset>2</bitOffset>
  17154. <bitWidth>2</bitWidth>
  17155. </field>
  17156. <field>
  17157. <name>CC1S</name>
  17158. <description>Capture/Compare 1
  17159. selection</description>
  17160. <bitOffset>0</bitOffset>
  17161. <bitWidth>2</bitWidth>
  17162. </field>
  17163. </fields>
  17164. </register>
  17165. <register>
  17166. <name>CCER</name>
  17167. <displayName>CCER</displayName>
  17168. <description>capture/compare enable
  17169. register</description>
  17170. <addressOffset>0x20</addressOffset>
  17171. <size>0x20</size>
  17172. <access>read-write</access>
  17173. <resetValue>0x0000</resetValue>
  17174. <fields>
  17175. <field>
  17176. <name>CC2NP</name>
  17177. <description>Capture/Compare 2 output
  17178. Polarity</description>
  17179. <bitOffset>7</bitOffset>
  17180. <bitWidth>1</bitWidth>
  17181. </field>
  17182. <field>
  17183. <name>CC2P</name>
  17184. <description>Capture/Compare 2 output
  17185. Polarity</description>
  17186. <bitOffset>5</bitOffset>
  17187. <bitWidth>1</bitWidth>
  17188. </field>
  17189. <field>
  17190. <name>CC2E</name>
  17191. <description>Capture/Compare 2 output
  17192. enable</description>
  17193. <bitOffset>4</bitOffset>
  17194. <bitWidth>1</bitWidth>
  17195. </field>
  17196. <field>
  17197. <name>CC1NP</name>
  17198. <description>Capture/Compare 1 output
  17199. Polarity</description>
  17200. <bitOffset>3</bitOffset>
  17201. <bitWidth>1</bitWidth>
  17202. </field>
  17203. <field>
  17204. <name>CC1P</name>
  17205. <description>Capture/Compare 1 output
  17206. Polarity</description>
  17207. <bitOffset>1</bitOffset>
  17208. <bitWidth>1</bitWidth>
  17209. </field>
  17210. <field>
  17211. <name>CC1E</name>
  17212. <description>Capture/Compare 1 output
  17213. enable</description>
  17214. <bitOffset>0</bitOffset>
  17215. <bitWidth>1</bitWidth>
  17216. </field>
  17217. </fields>
  17218. </register>
  17219. <register>
  17220. <name>CNT</name>
  17221. <displayName>CNT</displayName>
  17222. <description>counter</description>
  17223. <addressOffset>0x24</addressOffset>
  17224. <size>0x20</size>
  17225. <access>read-write</access>
  17226. <resetValue>0x00000000</resetValue>
  17227. <fields>
  17228. <field>
  17229. <name>CNT</name>
  17230. <description>counter value</description>
  17231. <bitOffset>0</bitOffset>
  17232. <bitWidth>16</bitWidth>
  17233. </field>
  17234. </fields>
  17235. </register>
  17236. <register>
  17237. <name>PSC</name>
  17238. <displayName>PSC</displayName>
  17239. <description>prescaler</description>
  17240. <addressOffset>0x28</addressOffset>
  17241. <size>0x20</size>
  17242. <access>read-write</access>
  17243. <resetValue>0x0000</resetValue>
  17244. <fields>
  17245. <field>
  17246. <name>PSC</name>
  17247. <description>Prescaler value</description>
  17248. <bitOffset>0</bitOffset>
  17249. <bitWidth>16</bitWidth>
  17250. </field>
  17251. </fields>
  17252. </register>
  17253. <register>
  17254. <name>ARR</name>
  17255. <displayName>ARR</displayName>
  17256. <description>auto-reload register</description>
  17257. <addressOffset>0x2C</addressOffset>
  17258. <size>0x20</size>
  17259. <access>read-write</access>
  17260. <resetValue>0x00000000</resetValue>
  17261. <fields>
  17262. <field>
  17263. <name>ARR</name>
  17264. <description>Auto-reload value</description>
  17265. <bitOffset>0</bitOffset>
  17266. <bitWidth>16</bitWidth>
  17267. </field>
  17268. </fields>
  17269. </register>
  17270. <register>
  17271. <name>CCR1</name>
  17272. <displayName>CCR1</displayName>
  17273. <description>capture/compare register 1</description>
  17274. <addressOffset>0x34</addressOffset>
  17275. <size>0x20</size>
  17276. <access>read-write</access>
  17277. <resetValue>0x00000000</resetValue>
  17278. <fields>
  17279. <field>
  17280. <name>CCR1</name>
  17281. <description>Capture/Compare 1 value</description>
  17282. <bitOffset>0</bitOffset>
  17283. <bitWidth>16</bitWidth>
  17284. </field>
  17285. </fields>
  17286. </register>
  17287. <register>
  17288. <name>CCR2</name>
  17289. <displayName>CCR2</displayName>
  17290. <description>capture/compare register 2</description>
  17291. <addressOffset>0x38</addressOffset>
  17292. <size>0x20</size>
  17293. <access>read-write</access>
  17294. <resetValue>0x00000000</resetValue>
  17295. <fields>
  17296. <field>
  17297. <name>CCR2</name>
  17298. <description>Capture/Compare 2 value</description>
  17299. <bitOffset>0</bitOffset>
  17300. <bitWidth>16</bitWidth>
  17301. </field>
  17302. </fields>
  17303. </register>
  17304. <register>
  17305. <name>OR</name>
  17306. <displayName>OR</displayName>
  17307. <description>TIM22 option register</description>
  17308. <addressOffset>0x50</addressOffset>
  17309. <size>0x20</size>
  17310. <access>read-write</access>
  17311. <resetValue>0x00000000</resetValue>
  17312. <fields>
  17313. <field>
  17314. <name>ETR_RMP</name>
  17315. <description>Timer22 ETR remap</description>
  17316. <bitOffset>0</bitOffset>
  17317. <bitWidth>2</bitWidth>
  17318. </field>
  17319. <field>
  17320. <name>TI1_RMP</name>
  17321. <description>Timer22 TI1</description>
  17322. <bitOffset>2</bitOffset>
  17323. <bitWidth>2</bitWidth>
  17324. </field>
  17325. </fields>
  17326. </register>
  17327. </registers>
  17328. </peripheral>
  17329. <peripheral>
  17330. <name>LPUSART1</name>
  17331. <description>Universal synchronous asynchronous receiver
  17332. transmitter</description>
  17333. <groupName>USART</groupName>
  17334. <baseAddress>0x40004800</baseAddress>
  17335. <addressBlock>
  17336. <offset>0x0</offset>
  17337. <size>0x400</size>
  17338. <usage>registers</usage>
  17339. </addressBlock>
  17340. <registers>
  17341. <register>
  17342. <name>CR1</name>
  17343. <displayName>CR1</displayName>
  17344. <description>Control register 1</description>
  17345. <addressOffset>0x0</addressOffset>
  17346. <size>0x20</size>
  17347. <access>read-write</access>
  17348. <resetValue>0x0000</resetValue>
  17349. <fields>
  17350. <field>
  17351. <name>M1</name>
  17352. <description>Word length</description>
  17353. <bitOffset>28</bitOffset>
  17354. <bitWidth>1</bitWidth>
  17355. </field>
  17356. <field>
  17357. <name>DEAT4</name>
  17358. <description>Driver Enable assertion
  17359. time</description>
  17360. <bitOffset>25</bitOffset>
  17361. <bitWidth>1</bitWidth>
  17362. </field>
  17363. <field>
  17364. <name>DEAT3</name>
  17365. <description>DEAT3</description>
  17366. <bitOffset>24</bitOffset>
  17367. <bitWidth>1</bitWidth>
  17368. </field>
  17369. <field>
  17370. <name>DEAT2</name>
  17371. <description>DEAT2</description>
  17372. <bitOffset>23</bitOffset>
  17373. <bitWidth>1</bitWidth>
  17374. </field>
  17375. <field>
  17376. <name>DEAT1</name>
  17377. <description>DEAT1</description>
  17378. <bitOffset>22</bitOffset>
  17379. <bitWidth>1</bitWidth>
  17380. </field>
  17381. <field>
  17382. <name>DEAT0</name>
  17383. <description>DEAT0</description>
  17384. <bitOffset>21</bitOffset>
  17385. <bitWidth>1</bitWidth>
  17386. </field>
  17387. <field>
  17388. <name>DEDT4</name>
  17389. <description>Driver Enable de-assertion
  17390. time</description>
  17391. <bitOffset>20</bitOffset>
  17392. <bitWidth>1</bitWidth>
  17393. </field>
  17394. <field>
  17395. <name>DEDT3</name>
  17396. <description>DEDT3</description>
  17397. <bitOffset>19</bitOffset>
  17398. <bitWidth>1</bitWidth>
  17399. </field>
  17400. <field>
  17401. <name>DEDT2</name>
  17402. <description>DEDT2</description>
  17403. <bitOffset>18</bitOffset>
  17404. <bitWidth>1</bitWidth>
  17405. </field>
  17406. <field>
  17407. <name>DEDT1</name>
  17408. <description>DEDT1</description>
  17409. <bitOffset>17</bitOffset>
  17410. <bitWidth>1</bitWidth>
  17411. </field>
  17412. <field>
  17413. <name>DEDT0</name>
  17414. <description>DEDT0</description>
  17415. <bitOffset>16</bitOffset>
  17416. <bitWidth>1</bitWidth>
  17417. </field>
  17418. <field>
  17419. <name>CMIE</name>
  17420. <description>Character match interrupt
  17421. enable</description>
  17422. <bitOffset>14</bitOffset>
  17423. <bitWidth>1</bitWidth>
  17424. </field>
  17425. <field>
  17426. <name>MME</name>
  17427. <description>Mute mode enable</description>
  17428. <bitOffset>13</bitOffset>
  17429. <bitWidth>1</bitWidth>
  17430. </field>
  17431. <field>
  17432. <name>M0</name>
  17433. <description>Word length</description>
  17434. <bitOffset>12</bitOffset>
  17435. <bitWidth>1</bitWidth>
  17436. </field>
  17437. <field>
  17438. <name>WAKE</name>
  17439. <description>Receiver wakeup method</description>
  17440. <bitOffset>11</bitOffset>
  17441. <bitWidth>1</bitWidth>
  17442. </field>
  17443. <field>
  17444. <name>PCE</name>
  17445. <description>Parity control enable</description>
  17446. <bitOffset>10</bitOffset>
  17447. <bitWidth>1</bitWidth>
  17448. </field>
  17449. <field>
  17450. <name>PS</name>
  17451. <description>Parity selection</description>
  17452. <bitOffset>9</bitOffset>
  17453. <bitWidth>1</bitWidth>
  17454. </field>
  17455. <field>
  17456. <name>PEIE</name>
  17457. <description>PE interrupt enable</description>
  17458. <bitOffset>8</bitOffset>
  17459. <bitWidth>1</bitWidth>
  17460. </field>
  17461. <field>
  17462. <name>TXEIE</name>
  17463. <description>interrupt enable</description>
  17464. <bitOffset>7</bitOffset>
  17465. <bitWidth>1</bitWidth>
  17466. </field>
  17467. <field>
  17468. <name>TCIE</name>
  17469. <description>Transmission complete interrupt
  17470. enable</description>
  17471. <bitOffset>6</bitOffset>
  17472. <bitWidth>1</bitWidth>
  17473. </field>
  17474. <field>
  17475. <name>RXNEIE</name>
  17476. <description>RXNE interrupt enable</description>
  17477. <bitOffset>5</bitOffset>
  17478. <bitWidth>1</bitWidth>
  17479. </field>
  17480. <field>
  17481. <name>IDLEIE</name>
  17482. <description>IDLE interrupt enable</description>
  17483. <bitOffset>4</bitOffset>
  17484. <bitWidth>1</bitWidth>
  17485. </field>
  17486. <field>
  17487. <name>TE</name>
  17488. <description>Transmitter enable</description>
  17489. <bitOffset>3</bitOffset>
  17490. <bitWidth>1</bitWidth>
  17491. </field>
  17492. <field>
  17493. <name>RE</name>
  17494. <description>Receiver enable</description>
  17495. <bitOffset>2</bitOffset>
  17496. <bitWidth>1</bitWidth>
  17497. </field>
  17498. <field>
  17499. <name>UESM</name>
  17500. <description>USART enable in Stop mode</description>
  17501. <bitOffset>1</bitOffset>
  17502. <bitWidth>1</bitWidth>
  17503. </field>
  17504. <field>
  17505. <name>UE</name>
  17506. <description>USART enable</description>
  17507. <bitOffset>0</bitOffset>
  17508. <bitWidth>1</bitWidth>
  17509. </field>
  17510. </fields>
  17511. </register>
  17512. <register>
  17513. <name>CR2</name>
  17514. <displayName>CR2</displayName>
  17515. <description>Control register 2</description>
  17516. <addressOffset>0x4</addressOffset>
  17517. <size>0x20</size>
  17518. <access>read-write</access>
  17519. <resetValue>0x0000</resetValue>
  17520. <fields>
  17521. <field>
  17522. <name>ADD4_7</name>
  17523. <description>Address of the USART node</description>
  17524. <bitOffset>28</bitOffset>
  17525. <bitWidth>4</bitWidth>
  17526. </field>
  17527. <field>
  17528. <name>ADD0_3</name>
  17529. <description>Address of the USART node</description>
  17530. <bitOffset>24</bitOffset>
  17531. <bitWidth>4</bitWidth>
  17532. </field>
  17533. <field>
  17534. <name>MSBFIRST</name>
  17535. <description>Most significant bit first</description>
  17536. <bitOffset>19</bitOffset>
  17537. <bitWidth>1</bitWidth>
  17538. </field>
  17539. <field>
  17540. <name>TAINV</name>
  17541. <description>Binary data inversion</description>
  17542. <bitOffset>18</bitOffset>
  17543. <bitWidth>1</bitWidth>
  17544. </field>
  17545. <field>
  17546. <name>TXINV</name>
  17547. <description>TX pin active level
  17548. inversion</description>
  17549. <bitOffset>17</bitOffset>
  17550. <bitWidth>1</bitWidth>
  17551. </field>
  17552. <field>
  17553. <name>RXINV</name>
  17554. <description>RX pin active level
  17555. inversion</description>
  17556. <bitOffset>16</bitOffset>
  17557. <bitWidth>1</bitWidth>
  17558. </field>
  17559. <field>
  17560. <name>SWAP</name>
  17561. <description>Swap TX/RX pins</description>
  17562. <bitOffset>15</bitOffset>
  17563. <bitWidth>1</bitWidth>
  17564. </field>
  17565. <field>
  17566. <name>STOP</name>
  17567. <description>STOP bits</description>
  17568. <bitOffset>12</bitOffset>
  17569. <bitWidth>2</bitWidth>
  17570. </field>
  17571. <field>
  17572. <name>CLKEN</name>
  17573. <description>Clock enable</description>
  17574. <bitOffset>11</bitOffset>
  17575. <bitWidth>1</bitWidth>
  17576. </field>
  17577. <field>
  17578. <name>ADDM7</name>
  17579. <description>7-bit Address Detection/4-bit Address
  17580. Detection</description>
  17581. <bitOffset>4</bitOffset>
  17582. <bitWidth>1</bitWidth>
  17583. </field>
  17584. </fields>
  17585. </register>
  17586. <register>
  17587. <name>CR3</name>
  17588. <displayName>CR3</displayName>
  17589. <description>Control register 3</description>
  17590. <addressOffset>0x8</addressOffset>
  17591. <size>0x20</size>
  17592. <access>read-write</access>
  17593. <resetValue>0x0000</resetValue>
  17594. <fields>
  17595. <field>
  17596. <name>WUFIE</name>
  17597. <description>Wakeup from Stop mode interrupt
  17598. enable</description>
  17599. <bitOffset>22</bitOffset>
  17600. <bitWidth>1</bitWidth>
  17601. </field>
  17602. <field>
  17603. <name>WUS</name>
  17604. <description>Wakeup from Stop mode interrupt flag
  17605. selection</description>
  17606. <bitOffset>20</bitOffset>
  17607. <bitWidth>2</bitWidth>
  17608. </field>
  17609. <field>
  17610. <name>DEP</name>
  17611. <description>Driver enable polarity
  17612. selection</description>
  17613. <bitOffset>15</bitOffset>
  17614. <bitWidth>1</bitWidth>
  17615. </field>
  17616. <field>
  17617. <name>DEM</name>
  17618. <description>Driver enable mode</description>
  17619. <bitOffset>14</bitOffset>
  17620. <bitWidth>1</bitWidth>
  17621. </field>
  17622. <field>
  17623. <name>DDRE</name>
  17624. <description>DMA Disable on Reception
  17625. Error</description>
  17626. <bitOffset>13</bitOffset>
  17627. <bitWidth>1</bitWidth>
  17628. </field>
  17629. <field>
  17630. <name>OVRDIS</name>
  17631. <description>Overrun Disable</description>
  17632. <bitOffset>12</bitOffset>
  17633. <bitWidth>1</bitWidth>
  17634. </field>
  17635. <field>
  17636. <name>CTSIE</name>
  17637. <description>CTS interrupt enable</description>
  17638. <bitOffset>10</bitOffset>
  17639. <bitWidth>1</bitWidth>
  17640. </field>
  17641. <field>
  17642. <name>CTSE</name>
  17643. <description>CTS enable</description>
  17644. <bitOffset>9</bitOffset>
  17645. <bitWidth>1</bitWidth>
  17646. </field>
  17647. <field>
  17648. <name>RTSE</name>
  17649. <description>RTS enable</description>
  17650. <bitOffset>8</bitOffset>
  17651. <bitWidth>1</bitWidth>
  17652. </field>
  17653. <field>
  17654. <name>DMAT</name>
  17655. <description>DMA enable transmitter</description>
  17656. <bitOffset>7</bitOffset>
  17657. <bitWidth>1</bitWidth>
  17658. </field>
  17659. <field>
  17660. <name>DMAR</name>
  17661. <description>DMA enable receiver</description>
  17662. <bitOffset>6</bitOffset>
  17663. <bitWidth>1</bitWidth>
  17664. </field>
  17665. <field>
  17666. <name>HDSEL</name>
  17667. <description>Half-duplex selection</description>
  17668. <bitOffset>3</bitOffset>
  17669. <bitWidth>1</bitWidth>
  17670. </field>
  17671. <field>
  17672. <name>EIE</name>
  17673. <description>Error interrupt enable</description>
  17674. <bitOffset>0</bitOffset>
  17675. <bitWidth>1</bitWidth>
  17676. </field>
  17677. </fields>
  17678. </register>
  17679. <register>
  17680. <name>BRR</name>
  17681. <displayName>BRR</displayName>
  17682. <description>Baud rate register</description>
  17683. <addressOffset>0xC</addressOffset>
  17684. <size>0x20</size>
  17685. <access>read-write</access>
  17686. <resetValue>0x0000</resetValue>
  17687. <fields>
  17688. <field>
  17689. <name>BRR</name>
  17690. <description>BRR</description>
  17691. <bitOffset>0</bitOffset>
  17692. <bitWidth>20</bitWidth>
  17693. </field>
  17694. </fields>
  17695. </register>
  17696. <register>
  17697. <name>RQR</name>
  17698. <displayName>RQR</displayName>
  17699. <description>Request register</description>
  17700. <addressOffset>0x18</addressOffset>
  17701. <size>0x20</size>
  17702. <access>write-only</access>
  17703. <resetValue>0x0000</resetValue>
  17704. <fields>
  17705. <field>
  17706. <name>RXFRQ</name>
  17707. <description>Receive data flush request</description>
  17708. <bitOffset>3</bitOffset>
  17709. <bitWidth>1</bitWidth>
  17710. </field>
  17711. <field>
  17712. <name>MMRQ</name>
  17713. <description>Mute mode request</description>
  17714. <bitOffset>2</bitOffset>
  17715. <bitWidth>1</bitWidth>
  17716. </field>
  17717. <field>
  17718. <name>SBKRQ</name>
  17719. <description>Send break request</description>
  17720. <bitOffset>1</bitOffset>
  17721. <bitWidth>1</bitWidth>
  17722. </field>
  17723. </fields>
  17724. </register>
  17725. <register>
  17726. <name>ISR</name>
  17727. <displayName>ISR</displayName>
  17728. <description>Interrupt &amp; status
  17729. register</description>
  17730. <addressOffset>0x1C</addressOffset>
  17731. <size>0x20</size>
  17732. <access>read-only</access>
  17733. <resetValue>0x00C0</resetValue>
  17734. <fields>
  17735. <field>
  17736. <name>REACK</name>
  17737. <description>REACK</description>
  17738. <bitOffset>22</bitOffset>
  17739. <bitWidth>1</bitWidth>
  17740. </field>
  17741. <field>
  17742. <name>TEACK</name>
  17743. <description>TEACK</description>
  17744. <bitOffset>21</bitOffset>
  17745. <bitWidth>1</bitWidth>
  17746. </field>
  17747. <field>
  17748. <name>WUF</name>
  17749. <description>WUF</description>
  17750. <bitOffset>20</bitOffset>
  17751. <bitWidth>1</bitWidth>
  17752. </field>
  17753. <field>
  17754. <name>RWU</name>
  17755. <description>RWU</description>
  17756. <bitOffset>19</bitOffset>
  17757. <bitWidth>1</bitWidth>
  17758. </field>
  17759. <field>
  17760. <name>SBKF</name>
  17761. <description>SBKF</description>
  17762. <bitOffset>18</bitOffset>
  17763. <bitWidth>1</bitWidth>
  17764. </field>
  17765. <field>
  17766. <name>CMF</name>
  17767. <description>CMF</description>
  17768. <bitOffset>17</bitOffset>
  17769. <bitWidth>1</bitWidth>
  17770. </field>
  17771. <field>
  17772. <name>BUSY</name>
  17773. <description>BUSY</description>
  17774. <bitOffset>16</bitOffset>
  17775. <bitWidth>1</bitWidth>
  17776. </field>
  17777. <field>
  17778. <name>CTS</name>
  17779. <description>CTS</description>
  17780. <bitOffset>10</bitOffset>
  17781. <bitWidth>1</bitWidth>
  17782. </field>
  17783. <field>
  17784. <name>CTSIF</name>
  17785. <description>CTSIF</description>
  17786. <bitOffset>9</bitOffset>
  17787. <bitWidth>1</bitWidth>
  17788. </field>
  17789. <field>
  17790. <name>TXE</name>
  17791. <description>TXE</description>
  17792. <bitOffset>7</bitOffset>
  17793. <bitWidth>1</bitWidth>
  17794. </field>
  17795. <field>
  17796. <name>TC</name>
  17797. <description>TC</description>
  17798. <bitOffset>6</bitOffset>
  17799. <bitWidth>1</bitWidth>
  17800. </field>
  17801. <field>
  17802. <name>RXNE</name>
  17803. <description>RXNE</description>
  17804. <bitOffset>5</bitOffset>
  17805. <bitWidth>1</bitWidth>
  17806. </field>
  17807. <field>
  17808. <name>IDLE</name>
  17809. <description>IDLE</description>
  17810. <bitOffset>4</bitOffset>
  17811. <bitWidth>1</bitWidth>
  17812. </field>
  17813. <field>
  17814. <name>ORE</name>
  17815. <description>ORE</description>
  17816. <bitOffset>3</bitOffset>
  17817. <bitWidth>1</bitWidth>
  17818. </field>
  17819. <field>
  17820. <name>NF</name>
  17821. <description>NF</description>
  17822. <bitOffset>2</bitOffset>
  17823. <bitWidth>1</bitWidth>
  17824. </field>
  17825. <field>
  17826. <name>FE</name>
  17827. <description>FE</description>
  17828. <bitOffset>1</bitOffset>
  17829. <bitWidth>1</bitWidth>
  17830. </field>
  17831. <field>
  17832. <name>PE</name>
  17833. <description>PE</description>
  17834. <bitOffset>0</bitOffset>
  17835. <bitWidth>1</bitWidth>
  17836. </field>
  17837. </fields>
  17838. </register>
  17839. <register>
  17840. <name>ICR</name>
  17841. <displayName>ICR</displayName>
  17842. <description>Interrupt flag clear register</description>
  17843. <addressOffset>0x20</addressOffset>
  17844. <size>0x20</size>
  17845. <access>write-only</access>
  17846. <resetValue>0x0000</resetValue>
  17847. <fields>
  17848. <field>
  17849. <name>WUCF</name>
  17850. <description>Wakeup from Stop mode clear
  17851. flag</description>
  17852. <bitOffset>20</bitOffset>
  17853. <bitWidth>1</bitWidth>
  17854. </field>
  17855. <field>
  17856. <name>CMCF</name>
  17857. <description>Character match clear flag</description>
  17858. <bitOffset>17</bitOffset>
  17859. <bitWidth>1</bitWidth>
  17860. </field>
  17861. <field>
  17862. <name>CTSCF</name>
  17863. <description>CTS clear flag</description>
  17864. <bitOffset>9</bitOffset>
  17865. <bitWidth>1</bitWidth>
  17866. </field>
  17867. <field>
  17868. <name>TCCF</name>
  17869. <description>Transmission complete clear
  17870. flag</description>
  17871. <bitOffset>6</bitOffset>
  17872. <bitWidth>1</bitWidth>
  17873. </field>
  17874. <field>
  17875. <name>IDLECF</name>
  17876. <description>Idle line detected clear
  17877. flag</description>
  17878. <bitOffset>4</bitOffset>
  17879. <bitWidth>1</bitWidth>
  17880. </field>
  17881. <field>
  17882. <name>ORECF</name>
  17883. <description>Overrun error clear flag</description>
  17884. <bitOffset>3</bitOffset>
  17885. <bitWidth>1</bitWidth>
  17886. </field>
  17887. <field>
  17888. <name>NCF</name>
  17889. <description>Noise detected clear flag</description>
  17890. <bitOffset>2</bitOffset>
  17891. <bitWidth>1</bitWidth>
  17892. </field>
  17893. <field>
  17894. <name>FECF</name>
  17895. <description>Framing error clear flag</description>
  17896. <bitOffset>1</bitOffset>
  17897. <bitWidth>1</bitWidth>
  17898. </field>
  17899. <field>
  17900. <name>PECF</name>
  17901. <description>Parity error clear flag</description>
  17902. <bitOffset>0</bitOffset>
  17903. <bitWidth>1</bitWidth>
  17904. </field>
  17905. </fields>
  17906. </register>
  17907. <register>
  17908. <name>RDR</name>
  17909. <displayName>RDR</displayName>
  17910. <description>Receive data register</description>
  17911. <addressOffset>0x24</addressOffset>
  17912. <size>0x20</size>
  17913. <access>read-only</access>
  17914. <resetValue>0x0000</resetValue>
  17915. <fields>
  17916. <field>
  17917. <name>RDR</name>
  17918. <description>Receive data value</description>
  17919. <bitOffset>0</bitOffset>
  17920. <bitWidth>9</bitWidth>
  17921. </field>
  17922. </fields>
  17923. </register>
  17924. <register>
  17925. <name>TDR</name>
  17926. <displayName>TDR</displayName>
  17927. <description>Transmit data register</description>
  17928. <addressOffset>0x28</addressOffset>
  17929. <size>0x20</size>
  17930. <access>read-write</access>
  17931. <resetValue>0x0000</resetValue>
  17932. <fields>
  17933. <field>
  17934. <name>TDR</name>
  17935. <description>Transmit data value</description>
  17936. <bitOffset>0</bitOffset>
  17937. <bitWidth>9</bitWidth>
  17938. </field>
  17939. </fields>
  17940. </register>
  17941. </registers>
  17942. </peripheral>
  17943. <peripheral>
  17944. <name>NVIC</name>
  17945. <description>Nested Vectored Interrupt
  17946. Controller</description>
  17947. <groupName>NVIC</groupName>
  17948. <baseAddress>0xE000E100</baseAddress>
  17949. <addressBlock>
  17950. <offset>0x0</offset>
  17951. <size>0x33D</size>
  17952. <usage>registers</usage>
  17953. </addressBlock>
  17954. <registers>
  17955. <register>
  17956. <name>ISER</name>
  17957. <displayName>ISER</displayName>
  17958. <description>Interrupt Set Enable Register</description>
  17959. <addressOffset>0x0</addressOffset>
  17960. <size>0x20</size>
  17961. <access>read-write</access>
  17962. <resetValue>0x00000000</resetValue>
  17963. <fields>
  17964. <field>
  17965. <name>SETENA</name>
  17966. <description>SETENA</description>
  17967. <bitOffset>0</bitOffset>
  17968. <bitWidth>32</bitWidth>
  17969. </field>
  17970. </fields>
  17971. </register>
  17972. <register>
  17973. <name>ICER</name>
  17974. <displayName>ICER</displayName>
  17975. <description>Interrupt Clear Enable
  17976. Register</description>
  17977. <addressOffset>0x80</addressOffset>
  17978. <size>0x20</size>
  17979. <access>read-write</access>
  17980. <resetValue>0x00000000</resetValue>
  17981. <fields>
  17982. <field>
  17983. <name>CLRENA</name>
  17984. <description>CLRENA</description>
  17985. <bitOffset>0</bitOffset>
  17986. <bitWidth>32</bitWidth>
  17987. </field>
  17988. </fields>
  17989. </register>
  17990. <register>
  17991. <name>ISPR</name>
  17992. <displayName>ISPR</displayName>
  17993. <description>Interrupt Set-Pending Register</description>
  17994. <addressOffset>0x100</addressOffset>
  17995. <size>0x20</size>
  17996. <access>read-write</access>
  17997. <resetValue>0x00000000</resetValue>
  17998. <fields>
  17999. <field>
  18000. <name>SETPEND</name>
  18001. <description>SETPEND</description>
  18002. <bitOffset>0</bitOffset>
  18003. <bitWidth>32</bitWidth>
  18004. </field>
  18005. </fields>
  18006. </register>
  18007. <register>
  18008. <name>ICPR</name>
  18009. <displayName>ICPR</displayName>
  18010. <description>Interrupt Clear-Pending
  18011. Register</description>
  18012. <addressOffset>0x180</addressOffset>
  18013. <size>0x20</size>
  18014. <access>read-write</access>
  18015. <resetValue>0x00000000</resetValue>
  18016. <fields>
  18017. <field>
  18018. <name>CLRPEND</name>
  18019. <description>CLRPEND</description>
  18020. <bitOffset>0</bitOffset>
  18021. <bitWidth>32</bitWidth>
  18022. </field>
  18023. </fields>
  18024. </register>
  18025. <register>
  18026. <name>IPR0</name>
  18027. <displayName>IPR0</displayName>
  18028. <description>Interrupt Priority Register 0</description>
  18029. <addressOffset>0x300</addressOffset>
  18030. <size>0x20</size>
  18031. <access>read-write</access>
  18032. <resetValue>0x00000000</resetValue>
  18033. <fields>
  18034. <field>
  18035. <name>PRI_0</name>
  18036. <description>priority for interrupt 0</description>
  18037. <bitOffset>0</bitOffset>
  18038. <bitWidth>8</bitWidth>
  18039. </field>
  18040. <field>
  18041. <name>PRI_1</name>
  18042. <description>priority for interrupt 1</description>
  18043. <bitOffset>8</bitOffset>
  18044. <bitWidth>8</bitWidth>
  18045. </field>
  18046. <field>
  18047. <name>PRI_2</name>
  18048. <description>priority for interrupt 2</description>
  18049. <bitOffset>16</bitOffset>
  18050. <bitWidth>8</bitWidth>
  18051. </field>
  18052. <field>
  18053. <name>PRI_3</name>
  18054. <description>priority for interrupt 3</description>
  18055. <bitOffset>24</bitOffset>
  18056. <bitWidth>8</bitWidth>
  18057. </field>
  18058. </fields>
  18059. </register>
  18060. <register>
  18061. <name>IPR1</name>
  18062. <displayName>IPR1</displayName>
  18063. <description>Interrupt Priority Register 1</description>
  18064. <addressOffset>0x304</addressOffset>
  18065. <size>0x20</size>
  18066. <access>read-write</access>
  18067. <resetValue>0x00000000</resetValue>
  18068. <fields>
  18069. <field>
  18070. <name>PRI_4</name>
  18071. <description>priority for interrupt n</description>
  18072. <bitOffset>0</bitOffset>
  18073. <bitWidth>8</bitWidth>
  18074. </field>
  18075. <field>
  18076. <name>PRI_5</name>
  18077. <description>priority for interrupt n</description>
  18078. <bitOffset>8</bitOffset>
  18079. <bitWidth>8</bitWidth>
  18080. </field>
  18081. <field>
  18082. <name>PRI_6</name>
  18083. <description>priority for interrupt n</description>
  18084. <bitOffset>16</bitOffset>
  18085. <bitWidth>8</bitWidth>
  18086. </field>
  18087. <field>
  18088. <name>PRI_7</name>
  18089. <description>priority for interrupt n</description>
  18090. <bitOffset>24</bitOffset>
  18091. <bitWidth>8</bitWidth>
  18092. </field>
  18093. </fields>
  18094. </register>
  18095. <register>
  18096. <name>IPR2</name>
  18097. <displayName>IPR2</displayName>
  18098. <description>Interrupt Priority Register 2</description>
  18099. <addressOffset>0x308</addressOffset>
  18100. <size>0x20</size>
  18101. <access>read-write</access>
  18102. <resetValue>0x00000000</resetValue>
  18103. <fields>
  18104. <field>
  18105. <name>PRI_8</name>
  18106. <description>priority for interrupt n</description>
  18107. <bitOffset>0</bitOffset>
  18108. <bitWidth>8</bitWidth>
  18109. </field>
  18110. <field>
  18111. <name>PRI_9</name>
  18112. <description>priority for interrupt n</description>
  18113. <bitOffset>8</bitOffset>
  18114. <bitWidth>8</bitWidth>
  18115. </field>
  18116. <field>
  18117. <name>PRI_10</name>
  18118. <description>priority for interrupt n</description>
  18119. <bitOffset>16</bitOffset>
  18120. <bitWidth>8</bitWidth>
  18121. </field>
  18122. <field>
  18123. <name>PRI_11</name>
  18124. <description>priority for interrupt n</description>
  18125. <bitOffset>24</bitOffset>
  18126. <bitWidth>8</bitWidth>
  18127. </field>
  18128. </fields>
  18129. </register>
  18130. <register>
  18131. <name>IPR3</name>
  18132. <displayName>IPR3</displayName>
  18133. <description>Interrupt Priority Register 3</description>
  18134. <addressOffset>0x30C</addressOffset>
  18135. <size>0x20</size>
  18136. <access>read-write</access>
  18137. <resetValue>0x00000000</resetValue>
  18138. <fields>
  18139. <field>
  18140. <name>PRI_12</name>
  18141. <description>priority for interrupt n</description>
  18142. <bitOffset>0</bitOffset>
  18143. <bitWidth>8</bitWidth>
  18144. </field>
  18145. <field>
  18146. <name>PRI_13</name>
  18147. <description>priority for interrupt n</description>
  18148. <bitOffset>8</bitOffset>
  18149. <bitWidth>8</bitWidth>
  18150. </field>
  18151. <field>
  18152. <name>PRI_14</name>
  18153. <description>priority for interrupt n</description>
  18154. <bitOffset>16</bitOffset>
  18155. <bitWidth>8</bitWidth>
  18156. </field>
  18157. <field>
  18158. <name>PRI_15</name>
  18159. <description>priority for interrupt n</description>
  18160. <bitOffset>24</bitOffset>
  18161. <bitWidth>8</bitWidth>
  18162. </field>
  18163. </fields>
  18164. </register>
  18165. <register>
  18166. <name>IPR4</name>
  18167. <displayName>IPR4</displayName>
  18168. <description>Interrupt Priority Register 4</description>
  18169. <addressOffset>0x310</addressOffset>
  18170. <size>0x20</size>
  18171. <access>read-write</access>
  18172. <resetValue>0x00000000</resetValue>
  18173. <fields>
  18174. <field>
  18175. <name>PRI_16</name>
  18176. <description>priority for interrupt n</description>
  18177. <bitOffset>0</bitOffset>
  18178. <bitWidth>8</bitWidth>
  18179. </field>
  18180. <field>
  18181. <name>PRI_17</name>
  18182. <description>priority for interrupt n</description>
  18183. <bitOffset>8</bitOffset>
  18184. <bitWidth>8</bitWidth>
  18185. </field>
  18186. <field>
  18187. <name>PRI_18</name>
  18188. <description>priority for interrupt n</description>
  18189. <bitOffset>16</bitOffset>
  18190. <bitWidth>8</bitWidth>
  18191. </field>
  18192. <field>
  18193. <name>PRI_19</name>
  18194. <description>priority for interrupt n</description>
  18195. <bitOffset>24</bitOffset>
  18196. <bitWidth>8</bitWidth>
  18197. </field>
  18198. </fields>
  18199. </register>
  18200. <register>
  18201. <name>IPR5</name>
  18202. <displayName>IPR5</displayName>
  18203. <description>Interrupt Priority Register 5</description>
  18204. <addressOffset>0x314</addressOffset>
  18205. <size>0x20</size>
  18206. <access>read-write</access>
  18207. <resetValue>0x00000000</resetValue>
  18208. <fields>
  18209. <field>
  18210. <name>PRI_20</name>
  18211. <description>priority for interrupt n</description>
  18212. <bitOffset>0</bitOffset>
  18213. <bitWidth>8</bitWidth>
  18214. </field>
  18215. <field>
  18216. <name>PRI_21</name>
  18217. <description>priority for interrupt n</description>
  18218. <bitOffset>8</bitOffset>
  18219. <bitWidth>8</bitWidth>
  18220. </field>
  18221. <field>
  18222. <name>PRI_22</name>
  18223. <description>priority for interrupt n</description>
  18224. <bitOffset>16</bitOffset>
  18225. <bitWidth>8</bitWidth>
  18226. </field>
  18227. <field>
  18228. <name>PRI_23</name>
  18229. <description>priority for interrupt n</description>
  18230. <bitOffset>24</bitOffset>
  18231. <bitWidth>8</bitWidth>
  18232. </field>
  18233. </fields>
  18234. </register>
  18235. <register>
  18236. <name>IPR6</name>
  18237. <displayName>IPR6</displayName>
  18238. <description>Interrupt Priority Register 6</description>
  18239. <addressOffset>0x318</addressOffset>
  18240. <size>0x20</size>
  18241. <access>read-write</access>
  18242. <resetValue>0x00000000</resetValue>
  18243. <fields>
  18244. <field>
  18245. <name>PRI_24</name>
  18246. <description>priority for interrupt n</description>
  18247. <bitOffset>0</bitOffset>
  18248. <bitWidth>8</bitWidth>
  18249. </field>
  18250. <field>
  18251. <name>PRI_25</name>
  18252. <description>priority for interrupt n</description>
  18253. <bitOffset>8</bitOffset>
  18254. <bitWidth>8</bitWidth>
  18255. </field>
  18256. <field>
  18257. <name>PRI_26</name>
  18258. <description>priority for interrupt n</description>
  18259. <bitOffset>16</bitOffset>
  18260. <bitWidth>8</bitWidth>
  18261. </field>
  18262. <field>
  18263. <name>PRI_27</name>
  18264. <description>priority for interrupt n</description>
  18265. <bitOffset>24</bitOffset>
  18266. <bitWidth>8</bitWidth>
  18267. </field>
  18268. </fields>
  18269. </register>
  18270. <register>
  18271. <name>IPR7</name>
  18272. <displayName>IPR7</displayName>
  18273. <description>Interrupt Priority Register 7</description>
  18274. <addressOffset>0x31C</addressOffset>
  18275. <size>0x20</size>
  18276. <access>read-write</access>
  18277. <resetValue>0x00000000</resetValue>
  18278. <fields>
  18279. <field>
  18280. <name>PRI_28</name>
  18281. <description>priority for interrupt n</description>
  18282. <bitOffset>0</bitOffset>
  18283. <bitWidth>8</bitWidth>
  18284. </field>
  18285. <field>
  18286. <name>PRI_29</name>
  18287. <description>priority for interrupt n</description>
  18288. <bitOffset>8</bitOffset>
  18289. <bitWidth>8</bitWidth>
  18290. </field>
  18291. <field>
  18292. <name>PRI_30</name>
  18293. <description>priority for interrupt n</description>
  18294. <bitOffset>16</bitOffset>
  18295. <bitWidth>8</bitWidth>
  18296. </field>
  18297. <field>
  18298. <name>PRI_31</name>
  18299. <description>priority for interrupt n</description>
  18300. <bitOffset>24</bitOffset>
  18301. <bitWidth>8</bitWidth>
  18302. </field>
  18303. </fields>
  18304. </register>
  18305. </registers>
  18306. </peripheral>
  18307. </peripherals>
  18308. </device>