STM32L063x.svd 680 KB

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  1. <?xml version="1.0" encoding="utf-8" standalone="no"?>
  2. <device schemaVersion="1.1"
  3. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
  4. xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  5. <name>STM32L063x</name>
  6. <version>1.0</version>
  7. <description>STM32L063x</description>
  8. <!--Bus Interface Properties-->
  9. <!--Cortex-M3 is byte addressable-->
  10. <addressUnitBits>8</addressUnitBits>
  11. <!--the maximum data bit width accessible within a single transfer-->
  12. <width>32</width>
  13. <!--Register Default Properties-->
  14. <size>0x20</size>
  15. <resetValue>0x0</resetValue>
  16. <resetMask>0xFFFFFFFF</resetMask>
  17. <peripherals>
  18. <peripheral>
  19. <name>AES</name>
  20. <description>Advanced encryption standard hardware
  21. accelerator</description>
  22. <groupName>AES</groupName>
  23. <baseAddress>0x40026000</baseAddress>
  24. <addressBlock>
  25. <offset>0x0</offset>
  26. <size>0x400</size>
  27. <usage>registers</usage>
  28. </addressBlock>
  29. <interrupt>
  30. <name>AES_RNG_LPUART1</name>
  31. <description>AES global interrupt RNG global interrupt and
  32. LPUART1 global interrupt through</description>
  33. <value>29</value>
  34. </interrupt>
  35. <registers>
  36. <register>
  37. <name>CR</name>
  38. <displayName>CR</displayName>
  39. <description>control register</description>
  40. <addressOffset>0x0</addressOffset>
  41. <size>0x20</size>
  42. <access>read-write</access>
  43. <resetValue>0x00000000</resetValue>
  44. <fields>
  45. <field>
  46. <name>DMAOUTEN</name>
  47. <description>Enable DMA management of data output
  48. phase</description>
  49. <bitOffset>12</bitOffset>
  50. <bitWidth>1</bitWidth>
  51. </field>
  52. <field>
  53. <name>DMAINEN</name>
  54. <description>Enable DMA management of data input
  55. phase</description>
  56. <bitOffset>11</bitOffset>
  57. <bitWidth>1</bitWidth>
  58. </field>
  59. <field>
  60. <name>ERRIE</name>
  61. <description>Error interrupt enable</description>
  62. <bitOffset>10</bitOffset>
  63. <bitWidth>1</bitWidth>
  64. </field>
  65. <field>
  66. <name>CCFIE</name>
  67. <description>CCF flag interrupt enable</description>
  68. <bitOffset>9</bitOffset>
  69. <bitWidth>1</bitWidth>
  70. </field>
  71. <field>
  72. <name>ERRC</name>
  73. <description>Error clear</description>
  74. <bitOffset>8</bitOffset>
  75. <bitWidth>1</bitWidth>
  76. </field>
  77. <field>
  78. <name>CCFC</name>
  79. <description>Computation Complete Flag
  80. Clear</description>
  81. <bitOffset>7</bitOffset>
  82. <bitWidth>1</bitWidth>
  83. </field>
  84. <field>
  85. <name>CHMOD</name>
  86. <description>AES chaining mode</description>
  87. <bitOffset>5</bitOffset>
  88. <bitWidth>2</bitWidth>
  89. </field>
  90. <field>
  91. <name>MODE</name>
  92. <description>AES operating mode</description>
  93. <bitOffset>3</bitOffset>
  94. <bitWidth>2</bitWidth>
  95. </field>
  96. <field>
  97. <name>DATATYPE</name>
  98. <description>Data type selection (for data in and
  99. data out to/from the cryptographic
  100. block)</description>
  101. <bitOffset>1</bitOffset>
  102. <bitWidth>2</bitWidth>
  103. </field>
  104. <field>
  105. <name>EN</name>
  106. <description>AES enable</description>
  107. <bitOffset>0</bitOffset>
  108. <bitWidth>1</bitWidth>
  109. </field>
  110. </fields>
  111. </register>
  112. <register>
  113. <name>SR</name>
  114. <displayName>SR</displayName>
  115. <description>status register</description>
  116. <addressOffset>0x4</addressOffset>
  117. <size>0x20</size>
  118. <access>read-only</access>
  119. <resetValue>0x00000000</resetValue>
  120. <fields>
  121. <field>
  122. <name>WRERR</name>
  123. <description>Write error flag</description>
  124. <bitOffset>2</bitOffset>
  125. <bitWidth>1</bitWidth>
  126. </field>
  127. <field>
  128. <name>RDERR</name>
  129. <description>Read error flag</description>
  130. <bitOffset>1</bitOffset>
  131. <bitWidth>1</bitWidth>
  132. </field>
  133. <field>
  134. <name>CCF</name>
  135. <description>Computation complete flag</description>
  136. <bitOffset>0</bitOffset>
  137. <bitWidth>1</bitWidth>
  138. </field>
  139. </fields>
  140. </register>
  141. <register>
  142. <name>DINR</name>
  143. <displayName>DINR</displayName>
  144. <description>data input register</description>
  145. <addressOffset>0x8</addressOffset>
  146. <size>0x20</size>
  147. <access>read-write</access>
  148. <resetValue>0x00000000</resetValue>
  149. <fields>
  150. <field>
  151. <name>AES_DINR</name>
  152. <description>Data Input Register.</description>
  153. <bitOffset>0</bitOffset>
  154. <bitWidth>32</bitWidth>
  155. </field>
  156. </fields>
  157. </register>
  158. <register>
  159. <name>DOUTR</name>
  160. <displayName>DOUTR</displayName>
  161. <description>data output register</description>
  162. <addressOffset>0xC</addressOffset>
  163. <size>0x20</size>
  164. <access>read-only</access>
  165. <resetValue>0x00000000</resetValue>
  166. <fields>
  167. <field>
  168. <name>AES_DOUTR</name>
  169. <description>Data output register</description>
  170. <bitOffset>0</bitOffset>
  171. <bitWidth>32</bitWidth>
  172. </field>
  173. </fields>
  174. </register>
  175. <register>
  176. <name>KEYR0</name>
  177. <displayName>KEYR0</displayName>
  178. <description>key register 0</description>
  179. <addressOffset>0x10</addressOffset>
  180. <size>0x20</size>
  181. <access>read-write</access>
  182. <resetValue>0x00000000</resetValue>
  183. <fields>
  184. <field>
  185. <name>AES_KEYR0</name>
  186. <description>Data Output Register (LSB key
  187. [31:0])</description>
  188. <bitOffset>0</bitOffset>
  189. <bitWidth>32</bitWidth>
  190. </field>
  191. </fields>
  192. </register>
  193. <register>
  194. <name>KEYR1</name>
  195. <displayName>KEYR1</displayName>
  196. <description>key register 1</description>
  197. <addressOffset>0x14</addressOffset>
  198. <size>0x20</size>
  199. <access>read-write</access>
  200. <resetValue>0x00000000</resetValue>
  201. <fields>
  202. <field>
  203. <name>AES_KEYR1</name>
  204. <description>AES key register (key
  205. [63:32])</description>
  206. <bitOffset>0</bitOffset>
  207. <bitWidth>32</bitWidth>
  208. </field>
  209. </fields>
  210. </register>
  211. <register>
  212. <name>KEYR2</name>
  213. <displayName>KEYR2</displayName>
  214. <description>key register 2</description>
  215. <addressOffset>0x18</addressOffset>
  216. <size>0x20</size>
  217. <access>read-write</access>
  218. <resetValue>0x00000000</resetValue>
  219. <fields>
  220. <field>
  221. <name>AES_KEYR2</name>
  222. <description>AES key register (key
  223. [95:64])</description>
  224. <bitOffset>0</bitOffset>
  225. <bitWidth>32</bitWidth>
  226. </field>
  227. </fields>
  228. </register>
  229. <register>
  230. <name>KEYR3</name>
  231. <displayName>KEYR3</displayName>
  232. <description>key register 3</description>
  233. <addressOffset>0x1C</addressOffset>
  234. <size>0x20</size>
  235. <access>read-write</access>
  236. <resetValue>0x00000000</resetValue>
  237. <fields>
  238. <field>
  239. <name>AES_KEYR3</name>
  240. <description>AES key register (MSB key
  241. [127:96])</description>
  242. <bitOffset>0</bitOffset>
  243. <bitWidth>32</bitWidth>
  244. </field>
  245. </fields>
  246. </register>
  247. <register>
  248. <name>IVR0</name>
  249. <displayName>IVR0</displayName>
  250. <description>initialization vector register
  251. 0</description>
  252. <addressOffset>0x20</addressOffset>
  253. <size>0x20</size>
  254. <access>read-write</access>
  255. <resetValue>0x00000000</resetValue>
  256. <fields>
  257. <field>
  258. <name>AES_IVR0</name>
  259. <description>initialization vector register (LSB IVR
  260. [31:0])</description>
  261. <bitOffset>0</bitOffset>
  262. <bitWidth>32</bitWidth>
  263. </field>
  264. </fields>
  265. </register>
  266. <register>
  267. <name>IVR1</name>
  268. <displayName>IVR1</displayName>
  269. <description>initialization vector register
  270. 1</description>
  271. <addressOffset>0x24</addressOffset>
  272. <size>0x20</size>
  273. <access>read-write</access>
  274. <resetValue>0x00000000</resetValue>
  275. <fields>
  276. <field>
  277. <name>AES_IVR1</name>
  278. <description>Initialization Vector Register (IVR
  279. [63:32])</description>
  280. <bitOffset>0</bitOffset>
  281. <bitWidth>32</bitWidth>
  282. </field>
  283. </fields>
  284. </register>
  285. <register>
  286. <name>IVR2</name>
  287. <displayName>IVR2</displayName>
  288. <description>initialization vector register
  289. 2</description>
  290. <addressOffset>0x28</addressOffset>
  291. <size>0x20</size>
  292. <access>read-write</access>
  293. <resetValue>0x00000000</resetValue>
  294. <fields>
  295. <field>
  296. <name>AES_IVR2</name>
  297. <description>Initialization Vector Register (IVR
  298. [95:64])</description>
  299. <bitOffset>0</bitOffset>
  300. <bitWidth>32</bitWidth>
  301. </field>
  302. </fields>
  303. </register>
  304. <register>
  305. <name>IVR3</name>
  306. <displayName>IVR3</displayName>
  307. <description>initialization vector register
  308. 3</description>
  309. <addressOffset>0x2C</addressOffset>
  310. <size>0x20</size>
  311. <access>read-write</access>
  312. <resetValue>0x00000000</resetValue>
  313. <fields>
  314. <field>
  315. <name>AES_IVR3</name>
  316. <description>Initialization Vector Register (MSB IVR
  317. [127:96])</description>
  318. <bitOffset>0</bitOffset>
  319. <bitWidth>32</bitWidth>
  320. </field>
  321. </fields>
  322. </register>
  323. </registers>
  324. </peripheral>
  325. <peripheral>
  326. <name>DAC</name>
  327. <description>Digital-to-analog converter</description>
  328. <groupName>DAC</groupName>
  329. <baseAddress>0x40007400</baseAddress>
  330. <addressBlock>
  331. <offset>0x0</offset>
  332. <size>0x400</size>
  333. <usage>registers</usage>
  334. </addressBlock>
  335. <registers>
  336. <register>
  337. <name>CR</name>
  338. <displayName>CR</displayName>
  339. <description>control register</description>
  340. <addressOffset>0x0</addressOffset>
  341. <size>0x20</size>
  342. <access>read-write</access>
  343. <resetValue>0x00000000</resetValue>
  344. <fields>
  345. <field>
  346. <name>DMAUDRIE1</name>
  347. <description>DAC channel1 DMA Underrun Interrupt
  348. enable</description>
  349. <bitOffset>13</bitOffset>
  350. <bitWidth>1</bitWidth>
  351. </field>
  352. <field>
  353. <name>DMAEN1</name>
  354. <description>DAC channel1 DMA enable</description>
  355. <bitOffset>12</bitOffset>
  356. <bitWidth>1</bitWidth>
  357. </field>
  358. <field>
  359. <name>MAMP1</name>
  360. <description>DAC channel1 mask/amplitude
  361. selector</description>
  362. <bitOffset>8</bitOffset>
  363. <bitWidth>4</bitWidth>
  364. </field>
  365. <field>
  366. <name>WAVE1</name>
  367. <description>DAC channel1 noise/triangle wave
  368. generation enable</description>
  369. <bitOffset>6</bitOffset>
  370. <bitWidth>2</bitWidth>
  371. </field>
  372. <field>
  373. <name>TSEL1</name>
  374. <description>DAC channel1 trigger
  375. selection</description>
  376. <bitOffset>3</bitOffset>
  377. <bitWidth>3</bitWidth>
  378. </field>
  379. <field>
  380. <name>TEN1</name>
  381. <description>DAC channel1 trigger
  382. enable</description>
  383. <bitOffset>2</bitOffset>
  384. <bitWidth>1</bitWidth>
  385. </field>
  386. <field>
  387. <name>BOFF1</name>
  388. <description>DAC channel1 output buffer
  389. disable</description>
  390. <bitOffset>1</bitOffset>
  391. <bitWidth>1</bitWidth>
  392. </field>
  393. <field>
  394. <name>EN1</name>
  395. <description>DAC channel1 enable</description>
  396. <bitOffset>0</bitOffset>
  397. <bitWidth>1</bitWidth>
  398. </field>
  399. </fields>
  400. </register>
  401. <register>
  402. <name>SWTRIGR</name>
  403. <displayName>SWTRIGR</displayName>
  404. <description>software trigger register</description>
  405. <addressOffset>0x4</addressOffset>
  406. <size>0x20</size>
  407. <access>write-only</access>
  408. <resetValue>0x00000000</resetValue>
  409. <fields>
  410. <field>
  411. <name>SWTRIG1</name>
  412. <description>DAC channel1 software
  413. trigger</description>
  414. <bitOffset>0</bitOffset>
  415. <bitWidth>1</bitWidth>
  416. </field>
  417. </fields>
  418. </register>
  419. <register>
  420. <name>DHR12R1</name>
  421. <displayName>DHR12R1</displayName>
  422. <description>channel1 12-bit right-aligned data holding
  423. register</description>
  424. <addressOffset>0x8</addressOffset>
  425. <size>0x20</size>
  426. <access>read-write</access>
  427. <resetValue>0x00000000</resetValue>
  428. <fields>
  429. <field>
  430. <name>DACC1DHR</name>
  431. <description>DAC channel1 12-bit right-aligned
  432. data</description>
  433. <bitOffset>0</bitOffset>
  434. <bitWidth>12</bitWidth>
  435. </field>
  436. </fields>
  437. </register>
  438. <register>
  439. <name>DHR12L1</name>
  440. <displayName>DHR12L1</displayName>
  441. <description>channel1 12-bit left-aligned data holding
  442. register</description>
  443. <addressOffset>0xC</addressOffset>
  444. <size>0x20</size>
  445. <access>read-write</access>
  446. <resetValue>0x00000000</resetValue>
  447. <fields>
  448. <field>
  449. <name>DACC1DHR</name>
  450. <description>DAC channel1 12-bit left-aligned
  451. data</description>
  452. <bitOffset>4</bitOffset>
  453. <bitWidth>12</bitWidth>
  454. </field>
  455. </fields>
  456. </register>
  457. <register>
  458. <name>DHR8R1</name>
  459. <displayName>DHR8R1</displayName>
  460. <description>channel1 8-bit right-aligned data holding
  461. register</description>
  462. <addressOffset>0x10</addressOffset>
  463. <size>0x20</size>
  464. <access>read-write</access>
  465. <resetValue>0x00000000</resetValue>
  466. <fields>
  467. <field>
  468. <name>DACC1DHR</name>
  469. <description>DAC channel1 8-bit right-aligned
  470. data</description>
  471. <bitOffset>0</bitOffset>
  472. <bitWidth>8</bitWidth>
  473. </field>
  474. </fields>
  475. </register>
  476. <register>
  477. <name>DOR1</name>
  478. <displayName>DOR1</displayName>
  479. <description>channel1 data output register</description>
  480. <addressOffset>0x2C</addressOffset>
  481. <size>0x20</size>
  482. <access>read-only</access>
  483. <resetValue>0x00000000</resetValue>
  484. <fields>
  485. <field>
  486. <name>DACC1DOR</name>
  487. <description>DAC channel1 data output</description>
  488. <bitOffset>0</bitOffset>
  489. <bitWidth>12</bitWidth>
  490. </field>
  491. </fields>
  492. </register>
  493. <register>
  494. <name>SR</name>
  495. <displayName>SR</displayName>
  496. <description>status register</description>
  497. <addressOffset>0x34</addressOffset>
  498. <size>0x20</size>
  499. <access>read-writeOnce</access>
  500. <resetValue>0x00000000</resetValue>
  501. <fields>
  502. <field>
  503. <name>DMAUDR1</name>
  504. <description>DAC channel1 DMA underrun
  505. flag</description>
  506. <bitOffset>13</bitOffset>
  507. <bitWidth>1</bitWidth>
  508. </field>
  509. </fields>
  510. </register>
  511. </registers>
  512. </peripheral>
  513. <peripheral>
  514. <name>DMA1</name>
  515. <description>Direct memory access controller</description>
  516. <groupName>DMA</groupName>
  517. <baseAddress>0x40020000</baseAddress>
  518. <addressBlock>
  519. <offset>0x0</offset>
  520. <size>0x400</size>
  521. <usage>registers</usage>
  522. </addressBlock>
  523. <interrupt>
  524. <name>DMA1_Channel1</name>
  525. <description>DMA1 Channel1 global interrupt</description>
  526. <value>9</value>
  527. </interrupt>
  528. <interrupt>
  529. <name>DMA1_Channel2_3</name>
  530. <description>DMA1 Channel2 and 3 interrupts</description>
  531. <value>10</value>
  532. </interrupt>
  533. <interrupt>
  534. <name>DMA1_Channel4_7</name>
  535. <description>DMA1 Channel4 to 7 interrupts</description>
  536. <value>11</value>
  537. </interrupt>
  538. <registers>
  539. <register>
  540. <name>ISR</name>
  541. <displayName>ISR</displayName>
  542. <description>interrupt status register</description>
  543. <addressOffset>0x0</addressOffset>
  544. <size>0x20</size>
  545. <access>read-only</access>
  546. <resetValue>0x00000000</resetValue>
  547. <fields>
  548. <field>
  549. <name>TEIF7</name>
  550. <description>Channel x transfer error flag (x = 1
  551. ..7)</description>
  552. <bitOffset>27</bitOffset>
  553. <bitWidth>1</bitWidth>
  554. </field>
  555. <field>
  556. <name>HTIF7</name>
  557. <description>Channel x half transfer flag (x = 1
  558. ..7)</description>
  559. <bitOffset>26</bitOffset>
  560. <bitWidth>1</bitWidth>
  561. </field>
  562. <field>
  563. <name>TCIF7</name>
  564. <description>Channel x transfer complete flag (x = 1
  565. ..7)</description>
  566. <bitOffset>25</bitOffset>
  567. <bitWidth>1</bitWidth>
  568. </field>
  569. <field>
  570. <name>GIF7</name>
  571. <description>Channel x global interrupt flag (x = 1
  572. ..7)</description>
  573. <bitOffset>24</bitOffset>
  574. <bitWidth>1</bitWidth>
  575. </field>
  576. <field>
  577. <name>TEIF6</name>
  578. <description>Channel x transfer error flag (x = 1
  579. ..7)</description>
  580. <bitOffset>23</bitOffset>
  581. <bitWidth>1</bitWidth>
  582. </field>
  583. <field>
  584. <name>HTIF6</name>
  585. <description>Channel x half transfer flag (x = 1
  586. ..7)</description>
  587. <bitOffset>22</bitOffset>
  588. <bitWidth>1</bitWidth>
  589. </field>
  590. <field>
  591. <name>TCIF6</name>
  592. <description>Channel x transfer complete flag (x = 1
  593. ..7)</description>
  594. <bitOffset>21</bitOffset>
  595. <bitWidth>1</bitWidth>
  596. </field>
  597. <field>
  598. <name>GIF6</name>
  599. <description>Channel x global interrupt flag (x = 1
  600. ..7)</description>
  601. <bitOffset>20</bitOffset>
  602. <bitWidth>1</bitWidth>
  603. </field>
  604. <field>
  605. <name>TEIF5</name>
  606. <description>Channel x transfer error flag (x = 1
  607. ..7)</description>
  608. <bitOffset>19</bitOffset>
  609. <bitWidth>1</bitWidth>
  610. </field>
  611. <field>
  612. <name>HTIF5</name>
  613. <description>Channel x half transfer flag (x = 1
  614. ..7)</description>
  615. <bitOffset>18</bitOffset>
  616. <bitWidth>1</bitWidth>
  617. </field>
  618. <field>
  619. <name>TCIF5</name>
  620. <description>Channel x transfer complete flag (x = 1
  621. ..7)</description>
  622. <bitOffset>17</bitOffset>
  623. <bitWidth>1</bitWidth>
  624. </field>
  625. <field>
  626. <name>GIF5</name>
  627. <description>Channel x global interrupt flag (x = 1
  628. ..7)</description>
  629. <bitOffset>16</bitOffset>
  630. <bitWidth>1</bitWidth>
  631. </field>
  632. <field>
  633. <name>TEIF4</name>
  634. <description>Channel x transfer error flag (x = 1
  635. ..7)</description>
  636. <bitOffset>15</bitOffset>
  637. <bitWidth>1</bitWidth>
  638. </field>
  639. <field>
  640. <name>HTIF4</name>
  641. <description>Channel x half transfer flag (x = 1
  642. ..7)</description>
  643. <bitOffset>14</bitOffset>
  644. <bitWidth>1</bitWidth>
  645. </field>
  646. <field>
  647. <name>TCIF4</name>
  648. <description>Channel x transfer complete flag (x = 1
  649. ..7)</description>
  650. <bitOffset>13</bitOffset>
  651. <bitWidth>1</bitWidth>
  652. </field>
  653. <field>
  654. <name>GIF4</name>
  655. <description>Channel x global interrupt flag (x = 1
  656. ..7)</description>
  657. <bitOffset>12</bitOffset>
  658. <bitWidth>1</bitWidth>
  659. </field>
  660. <field>
  661. <name>TEIF3</name>
  662. <description>Channel x transfer error flag (x = 1
  663. ..7)</description>
  664. <bitOffset>11</bitOffset>
  665. <bitWidth>1</bitWidth>
  666. </field>
  667. <field>
  668. <name>HTIF3</name>
  669. <description>Channel x half transfer flag (x = 1
  670. ..7)</description>
  671. <bitOffset>10</bitOffset>
  672. <bitWidth>1</bitWidth>
  673. </field>
  674. <field>
  675. <name>TCIF3</name>
  676. <description>Channel x transfer complete flag (x = 1
  677. ..7)</description>
  678. <bitOffset>9</bitOffset>
  679. <bitWidth>1</bitWidth>
  680. </field>
  681. <field>
  682. <name>GIF3</name>
  683. <description>Channel x global interrupt flag (x = 1
  684. ..7)</description>
  685. <bitOffset>8</bitOffset>
  686. <bitWidth>1</bitWidth>
  687. </field>
  688. <field>
  689. <name>TEIF2</name>
  690. <description>Channel x transfer error flag (x = 1
  691. ..7)</description>
  692. <bitOffset>7</bitOffset>
  693. <bitWidth>1</bitWidth>
  694. </field>
  695. <field>
  696. <name>HTIF2</name>
  697. <description>Channel x half transfer flag (x = 1
  698. ..7)</description>
  699. <bitOffset>6</bitOffset>
  700. <bitWidth>1</bitWidth>
  701. </field>
  702. <field>
  703. <name>TCIF2</name>
  704. <description>Channel x transfer complete flag (x = 1
  705. ..7)</description>
  706. <bitOffset>5</bitOffset>
  707. <bitWidth>1</bitWidth>
  708. </field>
  709. <field>
  710. <name>GIF2</name>
  711. <description>Channel x global interrupt flag (x = 1
  712. ..7)</description>
  713. <bitOffset>4</bitOffset>
  714. <bitWidth>1</bitWidth>
  715. </field>
  716. <field>
  717. <name>TEIF1</name>
  718. <description>Channel x transfer error flag (x = 1
  719. ..7)</description>
  720. <bitOffset>3</bitOffset>
  721. <bitWidth>1</bitWidth>
  722. </field>
  723. <field>
  724. <name>HTIF1</name>
  725. <description>Channel x half transfer flag (x = 1
  726. ..7)</description>
  727. <bitOffset>2</bitOffset>
  728. <bitWidth>1</bitWidth>
  729. </field>
  730. <field>
  731. <name>TCIF1</name>
  732. <description>Channel x transfer complete flag (x = 1
  733. ..7)</description>
  734. <bitOffset>1</bitOffset>
  735. <bitWidth>1</bitWidth>
  736. </field>
  737. <field>
  738. <name>GIF1</name>
  739. <description>Channel x global interrupt flag (x = 1
  740. ..7)</description>
  741. <bitOffset>0</bitOffset>
  742. <bitWidth>1</bitWidth>
  743. </field>
  744. </fields>
  745. </register>
  746. <register>
  747. <name>IFCR</name>
  748. <displayName>IFCR</displayName>
  749. <description>interrupt flag clear register</description>
  750. <addressOffset>0x4</addressOffset>
  751. <size>0x20</size>
  752. <access>write-only</access>
  753. <resetValue>0x00000000</resetValue>
  754. <fields>
  755. <field>
  756. <name>CTEIF7</name>
  757. <description>Channel x transfer error clear (x = 1
  758. ..7)</description>
  759. <bitOffset>27</bitOffset>
  760. <bitWidth>1</bitWidth>
  761. </field>
  762. <field>
  763. <name>CHTIF7</name>
  764. <description>Channel x half transfer clear (x = 1
  765. ..7)</description>
  766. <bitOffset>26</bitOffset>
  767. <bitWidth>1</bitWidth>
  768. </field>
  769. <field>
  770. <name>CTCIF7</name>
  771. <description>Channel x transfer complete clear (x = 1
  772. ..7)</description>
  773. <bitOffset>25</bitOffset>
  774. <bitWidth>1</bitWidth>
  775. </field>
  776. <field>
  777. <name>CGIF7</name>
  778. <description>Channel x global interrupt clear (x = 1
  779. ..7)</description>
  780. <bitOffset>24</bitOffset>
  781. <bitWidth>1</bitWidth>
  782. </field>
  783. <field>
  784. <name>CTEIF6</name>
  785. <description>Channel x transfer error clear (x = 1
  786. ..7)</description>
  787. <bitOffset>23</bitOffset>
  788. <bitWidth>1</bitWidth>
  789. </field>
  790. <field>
  791. <name>CHTIF6</name>
  792. <description>Channel x half transfer clear (x = 1
  793. ..7)</description>
  794. <bitOffset>22</bitOffset>
  795. <bitWidth>1</bitWidth>
  796. </field>
  797. <field>
  798. <name>CTCIF6</name>
  799. <description>Channel x transfer complete clear (x = 1
  800. ..7)</description>
  801. <bitOffset>21</bitOffset>
  802. <bitWidth>1</bitWidth>
  803. </field>
  804. <field>
  805. <name>CGIF6</name>
  806. <description>Channel x global interrupt clear (x = 1
  807. ..7)</description>
  808. <bitOffset>20</bitOffset>
  809. <bitWidth>1</bitWidth>
  810. </field>
  811. <field>
  812. <name>CTEIF5</name>
  813. <description>Channel x transfer error clear (x = 1
  814. ..7)</description>
  815. <bitOffset>19</bitOffset>
  816. <bitWidth>1</bitWidth>
  817. </field>
  818. <field>
  819. <name>CHTIF5</name>
  820. <description>Channel x half transfer clear (x = 1
  821. ..7)</description>
  822. <bitOffset>18</bitOffset>
  823. <bitWidth>1</bitWidth>
  824. </field>
  825. <field>
  826. <name>CTCIF5</name>
  827. <description>Channel x transfer complete clear (x = 1
  828. ..7)</description>
  829. <bitOffset>17</bitOffset>
  830. <bitWidth>1</bitWidth>
  831. </field>
  832. <field>
  833. <name>CGIF5</name>
  834. <description>Channel x global interrupt clear (x = 1
  835. ..7)</description>
  836. <bitOffset>16</bitOffset>
  837. <bitWidth>1</bitWidth>
  838. </field>
  839. <field>
  840. <name>CTEIF4</name>
  841. <description>Channel x transfer error clear (x = 1
  842. ..7)</description>
  843. <bitOffset>15</bitOffset>
  844. <bitWidth>1</bitWidth>
  845. </field>
  846. <field>
  847. <name>CHTIF4</name>
  848. <description>Channel x half transfer clear (x = 1
  849. ..7)</description>
  850. <bitOffset>14</bitOffset>
  851. <bitWidth>1</bitWidth>
  852. </field>
  853. <field>
  854. <name>CTCIF4</name>
  855. <description>Channel x transfer complete clear (x = 1
  856. ..7)</description>
  857. <bitOffset>13</bitOffset>
  858. <bitWidth>1</bitWidth>
  859. </field>
  860. <field>
  861. <name>CGIF4</name>
  862. <description>Channel x global interrupt clear (x = 1
  863. ..7)</description>
  864. <bitOffset>12</bitOffset>
  865. <bitWidth>1</bitWidth>
  866. </field>
  867. <field>
  868. <name>CTEIF3</name>
  869. <description>Channel x transfer error clear (x = 1
  870. ..7)</description>
  871. <bitOffset>11</bitOffset>
  872. <bitWidth>1</bitWidth>
  873. </field>
  874. <field>
  875. <name>CHTIF3</name>
  876. <description>Channel x half transfer clear (x = 1
  877. ..7)</description>
  878. <bitOffset>10</bitOffset>
  879. <bitWidth>1</bitWidth>
  880. </field>
  881. <field>
  882. <name>CTCIF3</name>
  883. <description>Channel x transfer complete clear (x = 1
  884. ..7)</description>
  885. <bitOffset>9</bitOffset>
  886. <bitWidth>1</bitWidth>
  887. </field>
  888. <field>
  889. <name>CGIF3</name>
  890. <description>Channel x global interrupt clear (x = 1
  891. ..7)</description>
  892. <bitOffset>8</bitOffset>
  893. <bitWidth>1</bitWidth>
  894. </field>
  895. <field>
  896. <name>CTEIF2</name>
  897. <description>Channel x transfer error clear (x = 1
  898. ..7)</description>
  899. <bitOffset>7</bitOffset>
  900. <bitWidth>1</bitWidth>
  901. </field>
  902. <field>
  903. <name>CHTIF2</name>
  904. <description>Channel x half transfer clear (x = 1
  905. ..7)</description>
  906. <bitOffset>6</bitOffset>
  907. <bitWidth>1</bitWidth>
  908. </field>
  909. <field>
  910. <name>CTCIF2</name>
  911. <description>Channel x transfer complete clear (x = 1
  912. ..7)</description>
  913. <bitOffset>5</bitOffset>
  914. <bitWidth>1</bitWidth>
  915. </field>
  916. <field>
  917. <name>CGIF2</name>
  918. <description>Channel x global interrupt clear (x = 1
  919. ..7)</description>
  920. <bitOffset>4</bitOffset>
  921. <bitWidth>1</bitWidth>
  922. </field>
  923. <field>
  924. <name>CTEIF1</name>
  925. <description>Channel x transfer error clear (x = 1
  926. ..7)</description>
  927. <bitOffset>3</bitOffset>
  928. <bitWidth>1</bitWidth>
  929. </field>
  930. <field>
  931. <name>CHTIF1</name>
  932. <description>Channel x half transfer clear (x = 1
  933. ..7)</description>
  934. <bitOffset>2</bitOffset>
  935. <bitWidth>1</bitWidth>
  936. </field>
  937. <field>
  938. <name>CTCIF1</name>
  939. <description>Channel x transfer complete clear (x = 1
  940. ..7)</description>
  941. <bitOffset>1</bitOffset>
  942. <bitWidth>1</bitWidth>
  943. </field>
  944. <field>
  945. <name>CGIF1</name>
  946. <description>Channel x global interrupt clear (x = 1
  947. ..7)</description>
  948. <bitOffset>0</bitOffset>
  949. <bitWidth>1</bitWidth>
  950. </field>
  951. </fields>
  952. </register>
  953. <register>
  954. <name>CCR1</name>
  955. <displayName>CCR1</displayName>
  956. <description>channel x configuration
  957. register</description>
  958. <addressOffset>0x8</addressOffset>
  959. <size>0x20</size>
  960. <access>read-write</access>
  961. <resetValue>0x00000000</resetValue>
  962. <fields>
  963. <field>
  964. <name>MEM2MEM</name>
  965. <description>Memory to memory mode</description>
  966. <bitOffset>14</bitOffset>
  967. <bitWidth>1</bitWidth>
  968. </field>
  969. <field>
  970. <name>PL</name>
  971. <description>Channel priority level</description>
  972. <bitOffset>12</bitOffset>
  973. <bitWidth>2</bitWidth>
  974. </field>
  975. <field>
  976. <name>MSIZE</name>
  977. <description>Memory size</description>
  978. <bitOffset>10</bitOffset>
  979. <bitWidth>2</bitWidth>
  980. </field>
  981. <field>
  982. <name>PSIZE</name>
  983. <description>Peripheral size</description>
  984. <bitOffset>8</bitOffset>
  985. <bitWidth>2</bitWidth>
  986. </field>
  987. <field>
  988. <name>MINC</name>
  989. <description>Memory increment mode</description>
  990. <bitOffset>7</bitOffset>
  991. <bitWidth>1</bitWidth>
  992. </field>
  993. <field>
  994. <name>PINC</name>
  995. <description>Peripheral increment mode</description>
  996. <bitOffset>6</bitOffset>
  997. <bitWidth>1</bitWidth>
  998. </field>
  999. <field>
  1000. <name>CIRC</name>
  1001. <description>Circular mode</description>
  1002. <bitOffset>5</bitOffset>
  1003. <bitWidth>1</bitWidth>
  1004. </field>
  1005. <field>
  1006. <name>DIR</name>
  1007. <description>Data transfer direction</description>
  1008. <bitOffset>4</bitOffset>
  1009. <bitWidth>1</bitWidth>
  1010. </field>
  1011. <field>
  1012. <name>TEIE</name>
  1013. <description>Transfer error interrupt
  1014. enable</description>
  1015. <bitOffset>3</bitOffset>
  1016. <bitWidth>1</bitWidth>
  1017. </field>
  1018. <field>
  1019. <name>HTIE</name>
  1020. <description>Half transfer interrupt
  1021. enable</description>
  1022. <bitOffset>2</bitOffset>
  1023. <bitWidth>1</bitWidth>
  1024. </field>
  1025. <field>
  1026. <name>TCIE</name>
  1027. <description>Transfer complete interrupt
  1028. enable</description>
  1029. <bitOffset>1</bitOffset>
  1030. <bitWidth>1</bitWidth>
  1031. </field>
  1032. <field>
  1033. <name>EN</name>
  1034. <description>Channel enable</description>
  1035. <bitOffset>0</bitOffset>
  1036. <bitWidth>1</bitWidth>
  1037. </field>
  1038. </fields>
  1039. </register>
  1040. <register>
  1041. <name>CNDTR1</name>
  1042. <displayName>CNDTR1</displayName>
  1043. <description>channel x number of data
  1044. register</description>
  1045. <addressOffset>0xC</addressOffset>
  1046. <size>0x20</size>
  1047. <access>read-write</access>
  1048. <resetValue>0x00000000</resetValue>
  1049. <fields>
  1050. <field>
  1051. <name>NDT</name>
  1052. <description>Number of data to transfer</description>
  1053. <bitOffset>0</bitOffset>
  1054. <bitWidth>16</bitWidth>
  1055. </field>
  1056. </fields>
  1057. </register>
  1058. <register>
  1059. <name>CPAR1</name>
  1060. <displayName>CPAR1</displayName>
  1061. <description>channel x peripheral address
  1062. register</description>
  1063. <addressOffset>0x10</addressOffset>
  1064. <size>0x20</size>
  1065. <access>read-write</access>
  1066. <resetValue>0x00000000</resetValue>
  1067. <fields>
  1068. <field>
  1069. <name>PA</name>
  1070. <description>Peripheral address</description>
  1071. <bitOffset>0</bitOffset>
  1072. <bitWidth>32</bitWidth>
  1073. </field>
  1074. </fields>
  1075. </register>
  1076. <register>
  1077. <name>CMAR1</name>
  1078. <displayName>CMAR1</displayName>
  1079. <description>channel x memory address
  1080. register</description>
  1081. <addressOffset>0x14</addressOffset>
  1082. <size>0x20</size>
  1083. <access>read-write</access>
  1084. <resetValue>0x00000000</resetValue>
  1085. <fields>
  1086. <field>
  1087. <name>MA</name>
  1088. <description>Memory address</description>
  1089. <bitOffset>0</bitOffset>
  1090. <bitWidth>32</bitWidth>
  1091. </field>
  1092. </fields>
  1093. </register>
  1094. <register>
  1095. <name>CCR2</name>
  1096. <displayName>CCR2</displayName>
  1097. <description>channel x configuration
  1098. register</description>
  1099. <addressOffset>0x1C</addressOffset>
  1100. <size>0x20</size>
  1101. <access>read-write</access>
  1102. <resetValue>0x00000000</resetValue>
  1103. <fields>
  1104. <field>
  1105. <name>MEM2MEM</name>
  1106. <description>Memory to memory mode</description>
  1107. <bitOffset>14</bitOffset>
  1108. <bitWidth>1</bitWidth>
  1109. </field>
  1110. <field>
  1111. <name>PL</name>
  1112. <description>Channel priority level</description>
  1113. <bitOffset>12</bitOffset>
  1114. <bitWidth>2</bitWidth>
  1115. </field>
  1116. <field>
  1117. <name>MSIZE</name>
  1118. <description>Memory size</description>
  1119. <bitOffset>10</bitOffset>
  1120. <bitWidth>2</bitWidth>
  1121. </field>
  1122. <field>
  1123. <name>PSIZE</name>
  1124. <description>Peripheral size</description>
  1125. <bitOffset>8</bitOffset>
  1126. <bitWidth>2</bitWidth>
  1127. </field>
  1128. <field>
  1129. <name>MINC</name>
  1130. <description>Memory increment mode</description>
  1131. <bitOffset>7</bitOffset>
  1132. <bitWidth>1</bitWidth>
  1133. </field>
  1134. <field>
  1135. <name>PINC</name>
  1136. <description>Peripheral increment mode</description>
  1137. <bitOffset>6</bitOffset>
  1138. <bitWidth>1</bitWidth>
  1139. </field>
  1140. <field>
  1141. <name>CIRC</name>
  1142. <description>Circular mode</description>
  1143. <bitOffset>5</bitOffset>
  1144. <bitWidth>1</bitWidth>
  1145. </field>
  1146. <field>
  1147. <name>DIR</name>
  1148. <description>Data transfer direction</description>
  1149. <bitOffset>4</bitOffset>
  1150. <bitWidth>1</bitWidth>
  1151. </field>
  1152. <field>
  1153. <name>TEIE</name>
  1154. <description>Transfer error interrupt
  1155. enable</description>
  1156. <bitOffset>3</bitOffset>
  1157. <bitWidth>1</bitWidth>
  1158. </field>
  1159. <field>
  1160. <name>HTIE</name>
  1161. <description>Half transfer interrupt
  1162. enable</description>
  1163. <bitOffset>2</bitOffset>
  1164. <bitWidth>1</bitWidth>
  1165. </field>
  1166. <field>
  1167. <name>TCIE</name>
  1168. <description>Transfer complete interrupt
  1169. enable</description>
  1170. <bitOffset>1</bitOffset>
  1171. <bitWidth>1</bitWidth>
  1172. </field>
  1173. <field>
  1174. <name>EN</name>
  1175. <description>Channel enable</description>
  1176. <bitOffset>0</bitOffset>
  1177. <bitWidth>1</bitWidth>
  1178. </field>
  1179. </fields>
  1180. </register>
  1181. <register>
  1182. <name>CNDTR2</name>
  1183. <displayName>CNDTR2</displayName>
  1184. <description>channel x number of data
  1185. register</description>
  1186. <addressOffset>0x20</addressOffset>
  1187. <size>0x20</size>
  1188. <access>read-write</access>
  1189. <resetValue>0x00000000</resetValue>
  1190. <fields>
  1191. <field>
  1192. <name>NDT</name>
  1193. <description>Number of data to transfer</description>
  1194. <bitOffset>0</bitOffset>
  1195. <bitWidth>16</bitWidth>
  1196. </field>
  1197. </fields>
  1198. </register>
  1199. <register>
  1200. <name>CPAR2</name>
  1201. <displayName>CPAR2</displayName>
  1202. <description>channel x peripheral address
  1203. register</description>
  1204. <addressOffset>0x24</addressOffset>
  1205. <size>0x20</size>
  1206. <access>read-write</access>
  1207. <resetValue>0x00000000</resetValue>
  1208. <fields>
  1209. <field>
  1210. <name>PA</name>
  1211. <description>Peripheral address</description>
  1212. <bitOffset>0</bitOffset>
  1213. <bitWidth>32</bitWidth>
  1214. </field>
  1215. </fields>
  1216. </register>
  1217. <register>
  1218. <name>CMAR2</name>
  1219. <displayName>CMAR2</displayName>
  1220. <description>channel x memory address
  1221. register</description>
  1222. <addressOffset>0x28</addressOffset>
  1223. <size>0x20</size>
  1224. <access>read-write</access>
  1225. <resetValue>0x00000000</resetValue>
  1226. <fields>
  1227. <field>
  1228. <name>MA</name>
  1229. <description>Memory address</description>
  1230. <bitOffset>0</bitOffset>
  1231. <bitWidth>32</bitWidth>
  1232. </field>
  1233. </fields>
  1234. </register>
  1235. <register>
  1236. <name>CCR3</name>
  1237. <displayName>CCR3</displayName>
  1238. <description>channel x configuration
  1239. register</description>
  1240. <addressOffset>0x30</addressOffset>
  1241. <size>0x20</size>
  1242. <access>read-write</access>
  1243. <resetValue>0x00000000</resetValue>
  1244. <fields>
  1245. <field>
  1246. <name>MEM2MEM</name>
  1247. <description>Memory to memory mode</description>
  1248. <bitOffset>14</bitOffset>
  1249. <bitWidth>1</bitWidth>
  1250. </field>
  1251. <field>
  1252. <name>PL</name>
  1253. <description>Channel priority level</description>
  1254. <bitOffset>12</bitOffset>
  1255. <bitWidth>2</bitWidth>
  1256. </field>
  1257. <field>
  1258. <name>MSIZE</name>
  1259. <description>Memory size</description>
  1260. <bitOffset>10</bitOffset>
  1261. <bitWidth>2</bitWidth>
  1262. </field>
  1263. <field>
  1264. <name>PSIZE</name>
  1265. <description>Peripheral size</description>
  1266. <bitOffset>8</bitOffset>
  1267. <bitWidth>2</bitWidth>
  1268. </field>
  1269. <field>
  1270. <name>MINC</name>
  1271. <description>Memory increment mode</description>
  1272. <bitOffset>7</bitOffset>
  1273. <bitWidth>1</bitWidth>
  1274. </field>
  1275. <field>
  1276. <name>PINC</name>
  1277. <description>Peripheral increment mode</description>
  1278. <bitOffset>6</bitOffset>
  1279. <bitWidth>1</bitWidth>
  1280. </field>
  1281. <field>
  1282. <name>CIRC</name>
  1283. <description>Circular mode</description>
  1284. <bitOffset>5</bitOffset>
  1285. <bitWidth>1</bitWidth>
  1286. </field>
  1287. <field>
  1288. <name>DIR</name>
  1289. <description>Data transfer direction</description>
  1290. <bitOffset>4</bitOffset>
  1291. <bitWidth>1</bitWidth>
  1292. </field>
  1293. <field>
  1294. <name>TEIE</name>
  1295. <description>Transfer error interrupt
  1296. enable</description>
  1297. <bitOffset>3</bitOffset>
  1298. <bitWidth>1</bitWidth>
  1299. </field>
  1300. <field>
  1301. <name>HTIE</name>
  1302. <description>Half transfer interrupt
  1303. enable</description>
  1304. <bitOffset>2</bitOffset>
  1305. <bitWidth>1</bitWidth>
  1306. </field>
  1307. <field>
  1308. <name>TCIE</name>
  1309. <description>Transfer complete interrupt
  1310. enable</description>
  1311. <bitOffset>1</bitOffset>
  1312. <bitWidth>1</bitWidth>
  1313. </field>
  1314. <field>
  1315. <name>EN</name>
  1316. <description>Channel enable</description>
  1317. <bitOffset>0</bitOffset>
  1318. <bitWidth>1</bitWidth>
  1319. </field>
  1320. </fields>
  1321. </register>
  1322. <register>
  1323. <name>CNDTR3</name>
  1324. <displayName>CNDTR3</displayName>
  1325. <description>channel x number of data
  1326. register</description>
  1327. <addressOffset>0x34</addressOffset>
  1328. <size>0x20</size>
  1329. <access>read-write</access>
  1330. <resetValue>0x00000000</resetValue>
  1331. <fields>
  1332. <field>
  1333. <name>NDT</name>
  1334. <description>Number of data to transfer</description>
  1335. <bitOffset>0</bitOffset>
  1336. <bitWidth>16</bitWidth>
  1337. </field>
  1338. </fields>
  1339. </register>
  1340. <register>
  1341. <name>CPAR3</name>
  1342. <displayName>CPAR3</displayName>
  1343. <description>channel x peripheral address
  1344. register</description>
  1345. <addressOffset>0x38</addressOffset>
  1346. <size>0x20</size>
  1347. <access>read-write</access>
  1348. <resetValue>0x00000000</resetValue>
  1349. <fields>
  1350. <field>
  1351. <name>PA</name>
  1352. <description>Peripheral address</description>
  1353. <bitOffset>0</bitOffset>
  1354. <bitWidth>32</bitWidth>
  1355. </field>
  1356. </fields>
  1357. </register>
  1358. <register>
  1359. <name>CMAR3</name>
  1360. <displayName>CMAR3</displayName>
  1361. <description>channel x memory address
  1362. register</description>
  1363. <addressOffset>0x3C</addressOffset>
  1364. <size>0x20</size>
  1365. <access>read-write</access>
  1366. <resetValue>0x00000000</resetValue>
  1367. <fields>
  1368. <field>
  1369. <name>MA</name>
  1370. <description>Memory address</description>
  1371. <bitOffset>0</bitOffset>
  1372. <bitWidth>32</bitWidth>
  1373. </field>
  1374. </fields>
  1375. </register>
  1376. <register>
  1377. <name>CCR4</name>
  1378. <displayName>CCR4</displayName>
  1379. <description>channel x configuration
  1380. register</description>
  1381. <addressOffset>0x44</addressOffset>
  1382. <size>0x20</size>
  1383. <access>read-write</access>
  1384. <resetValue>0x00000000</resetValue>
  1385. <fields>
  1386. <field>
  1387. <name>MEM2MEM</name>
  1388. <description>Memory to memory mode</description>
  1389. <bitOffset>14</bitOffset>
  1390. <bitWidth>1</bitWidth>
  1391. </field>
  1392. <field>
  1393. <name>PL</name>
  1394. <description>Channel priority level</description>
  1395. <bitOffset>12</bitOffset>
  1396. <bitWidth>2</bitWidth>
  1397. </field>
  1398. <field>
  1399. <name>MSIZE</name>
  1400. <description>Memory size</description>
  1401. <bitOffset>10</bitOffset>
  1402. <bitWidth>2</bitWidth>
  1403. </field>
  1404. <field>
  1405. <name>PSIZE</name>
  1406. <description>Peripheral size</description>
  1407. <bitOffset>8</bitOffset>
  1408. <bitWidth>2</bitWidth>
  1409. </field>
  1410. <field>
  1411. <name>MINC</name>
  1412. <description>Memory increment mode</description>
  1413. <bitOffset>7</bitOffset>
  1414. <bitWidth>1</bitWidth>
  1415. </field>
  1416. <field>
  1417. <name>PINC</name>
  1418. <description>Peripheral increment mode</description>
  1419. <bitOffset>6</bitOffset>
  1420. <bitWidth>1</bitWidth>
  1421. </field>
  1422. <field>
  1423. <name>CIRC</name>
  1424. <description>Circular mode</description>
  1425. <bitOffset>5</bitOffset>
  1426. <bitWidth>1</bitWidth>
  1427. </field>
  1428. <field>
  1429. <name>DIR</name>
  1430. <description>Data transfer direction</description>
  1431. <bitOffset>4</bitOffset>
  1432. <bitWidth>1</bitWidth>
  1433. </field>
  1434. <field>
  1435. <name>TEIE</name>
  1436. <description>Transfer error interrupt
  1437. enable</description>
  1438. <bitOffset>3</bitOffset>
  1439. <bitWidth>1</bitWidth>
  1440. </field>
  1441. <field>
  1442. <name>HTIE</name>
  1443. <description>Half transfer interrupt
  1444. enable</description>
  1445. <bitOffset>2</bitOffset>
  1446. <bitWidth>1</bitWidth>
  1447. </field>
  1448. <field>
  1449. <name>TCIE</name>
  1450. <description>Transfer complete interrupt
  1451. enable</description>
  1452. <bitOffset>1</bitOffset>
  1453. <bitWidth>1</bitWidth>
  1454. </field>
  1455. <field>
  1456. <name>EN</name>
  1457. <description>Channel enable</description>
  1458. <bitOffset>0</bitOffset>
  1459. <bitWidth>1</bitWidth>
  1460. </field>
  1461. </fields>
  1462. </register>
  1463. <register>
  1464. <name>CNDTR4</name>
  1465. <displayName>CNDTR4</displayName>
  1466. <description>channel x number of data
  1467. register</description>
  1468. <addressOffset>0x48</addressOffset>
  1469. <size>0x20</size>
  1470. <access>read-write</access>
  1471. <resetValue>0x00000000</resetValue>
  1472. <fields>
  1473. <field>
  1474. <name>NDT</name>
  1475. <description>Number of data to transfer</description>
  1476. <bitOffset>0</bitOffset>
  1477. <bitWidth>16</bitWidth>
  1478. </field>
  1479. </fields>
  1480. </register>
  1481. <register>
  1482. <name>CPAR4</name>
  1483. <displayName>CPAR4</displayName>
  1484. <description>channel x peripheral address
  1485. register</description>
  1486. <addressOffset>0x4C</addressOffset>
  1487. <size>0x20</size>
  1488. <access>read-write</access>
  1489. <resetValue>0x00000000</resetValue>
  1490. <fields>
  1491. <field>
  1492. <name>PA</name>
  1493. <description>Peripheral address</description>
  1494. <bitOffset>0</bitOffset>
  1495. <bitWidth>32</bitWidth>
  1496. </field>
  1497. </fields>
  1498. </register>
  1499. <register>
  1500. <name>CMAR4</name>
  1501. <displayName>CMAR4</displayName>
  1502. <description>channel x memory address
  1503. register</description>
  1504. <addressOffset>0x50</addressOffset>
  1505. <size>0x20</size>
  1506. <access>read-write</access>
  1507. <resetValue>0x00000000</resetValue>
  1508. <fields>
  1509. <field>
  1510. <name>MA</name>
  1511. <description>Memory address</description>
  1512. <bitOffset>0</bitOffset>
  1513. <bitWidth>32</bitWidth>
  1514. </field>
  1515. </fields>
  1516. </register>
  1517. <register>
  1518. <name>CCR5</name>
  1519. <displayName>CCR5</displayName>
  1520. <description>channel x configuration
  1521. register</description>
  1522. <addressOffset>0x58</addressOffset>
  1523. <size>0x20</size>
  1524. <access>read-write</access>
  1525. <resetValue>0x00000000</resetValue>
  1526. <fields>
  1527. <field>
  1528. <name>MEM2MEM</name>
  1529. <description>Memory to memory mode</description>
  1530. <bitOffset>14</bitOffset>
  1531. <bitWidth>1</bitWidth>
  1532. </field>
  1533. <field>
  1534. <name>PL</name>
  1535. <description>Channel priority level</description>
  1536. <bitOffset>12</bitOffset>
  1537. <bitWidth>2</bitWidth>
  1538. </field>
  1539. <field>
  1540. <name>MSIZE</name>
  1541. <description>Memory size</description>
  1542. <bitOffset>10</bitOffset>
  1543. <bitWidth>2</bitWidth>
  1544. </field>
  1545. <field>
  1546. <name>PSIZE</name>
  1547. <description>Peripheral size</description>
  1548. <bitOffset>8</bitOffset>
  1549. <bitWidth>2</bitWidth>
  1550. </field>
  1551. <field>
  1552. <name>MINC</name>
  1553. <description>Memory increment mode</description>
  1554. <bitOffset>7</bitOffset>
  1555. <bitWidth>1</bitWidth>
  1556. </field>
  1557. <field>
  1558. <name>PINC</name>
  1559. <description>Peripheral increment mode</description>
  1560. <bitOffset>6</bitOffset>
  1561. <bitWidth>1</bitWidth>
  1562. </field>
  1563. <field>
  1564. <name>CIRC</name>
  1565. <description>Circular mode</description>
  1566. <bitOffset>5</bitOffset>
  1567. <bitWidth>1</bitWidth>
  1568. </field>
  1569. <field>
  1570. <name>DIR</name>
  1571. <description>Data transfer direction</description>
  1572. <bitOffset>4</bitOffset>
  1573. <bitWidth>1</bitWidth>
  1574. </field>
  1575. <field>
  1576. <name>TEIE</name>
  1577. <description>Transfer error interrupt
  1578. enable</description>
  1579. <bitOffset>3</bitOffset>
  1580. <bitWidth>1</bitWidth>
  1581. </field>
  1582. <field>
  1583. <name>HTIE</name>
  1584. <description>Half transfer interrupt
  1585. enable</description>
  1586. <bitOffset>2</bitOffset>
  1587. <bitWidth>1</bitWidth>
  1588. </field>
  1589. <field>
  1590. <name>TCIE</name>
  1591. <description>Transfer complete interrupt
  1592. enable</description>
  1593. <bitOffset>1</bitOffset>
  1594. <bitWidth>1</bitWidth>
  1595. </field>
  1596. <field>
  1597. <name>EN</name>
  1598. <description>Channel enable</description>
  1599. <bitOffset>0</bitOffset>
  1600. <bitWidth>1</bitWidth>
  1601. </field>
  1602. </fields>
  1603. </register>
  1604. <register>
  1605. <name>CNDTR5</name>
  1606. <displayName>CNDTR5</displayName>
  1607. <description>channel x number of data
  1608. register</description>
  1609. <addressOffset>0x5C</addressOffset>
  1610. <size>0x20</size>
  1611. <access>read-write</access>
  1612. <resetValue>0x00000000</resetValue>
  1613. <fields>
  1614. <field>
  1615. <name>NDT</name>
  1616. <description>Number of data to transfer</description>
  1617. <bitOffset>0</bitOffset>
  1618. <bitWidth>16</bitWidth>
  1619. </field>
  1620. </fields>
  1621. </register>
  1622. <register>
  1623. <name>CPAR5</name>
  1624. <displayName>CPAR5</displayName>
  1625. <description>channel x peripheral address
  1626. register</description>
  1627. <addressOffset>0x60</addressOffset>
  1628. <size>0x20</size>
  1629. <access>read-write</access>
  1630. <resetValue>0x00000000</resetValue>
  1631. <fields>
  1632. <field>
  1633. <name>PA</name>
  1634. <description>Peripheral address</description>
  1635. <bitOffset>0</bitOffset>
  1636. <bitWidth>32</bitWidth>
  1637. </field>
  1638. </fields>
  1639. </register>
  1640. <register>
  1641. <name>CMAR5</name>
  1642. <displayName>CMAR5</displayName>
  1643. <description>channel x memory address
  1644. register</description>
  1645. <addressOffset>0x64</addressOffset>
  1646. <size>0x20</size>
  1647. <access>read-write</access>
  1648. <resetValue>0x00000000</resetValue>
  1649. <fields>
  1650. <field>
  1651. <name>MA</name>
  1652. <description>Memory address</description>
  1653. <bitOffset>0</bitOffset>
  1654. <bitWidth>32</bitWidth>
  1655. </field>
  1656. </fields>
  1657. </register>
  1658. <register>
  1659. <name>CCR6</name>
  1660. <displayName>CCR6</displayName>
  1661. <description>channel x configuration
  1662. register</description>
  1663. <addressOffset>0x6C</addressOffset>
  1664. <size>0x20</size>
  1665. <access>read-write</access>
  1666. <resetValue>0x00000000</resetValue>
  1667. <fields>
  1668. <field>
  1669. <name>MEM2MEM</name>
  1670. <description>Memory to memory mode</description>
  1671. <bitOffset>14</bitOffset>
  1672. <bitWidth>1</bitWidth>
  1673. </field>
  1674. <field>
  1675. <name>PL</name>
  1676. <description>Channel priority level</description>
  1677. <bitOffset>12</bitOffset>
  1678. <bitWidth>2</bitWidth>
  1679. </field>
  1680. <field>
  1681. <name>MSIZE</name>
  1682. <description>Memory size</description>
  1683. <bitOffset>10</bitOffset>
  1684. <bitWidth>2</bitWidth>
  1685. </field>
  1686. <field>
  1687. <name>PSIZE</name>
  1688. <description>Peripheral size</description>
  1689. <bitOffset>8</bitOffset>
  1690. <bitWidth>2</bitWidth>
  1691. </field>
  1692. <field>
  1693. <name>MINC</name>
  1694. <description>Memory increment mode</description>
  1695. <bitOffset>7</bitOffset>
  1696. <bitWidth>1</bitWidth>
  1697. </field>
  1698. <field>
  1699. <name>PINC</name>
  1700. <description>Peripheral increment mode</description>
  1701. <bitOffset>6</bitOffset>
  1702. <bitWidth>1</bitWidth>
  1703. </field>
  1704. <field>
  1705. <name>CIRC</name>
  1706. <description>Circular mode</description>
  1707. <bitOffset>5</bitOffset>
  1708. <bitWidth>1</bitWidth>
  1709. </field>
  1710. <field>
  1711. <name>DIR</name>
  1712. <description>Data transfer direction</description>
  1713. <bitOffset>4</bitOffset>
  1714. <bitWidth>1</bitWidth>
  1715. </field>
  1716. <field>
  1717. <name>TEIE</name>
  1718. <description>Transfer error interrupt
  1719. enable</description>
  1720. <bitOffset>3</bitOffset>
  1721. <bitWidth>1</bitWidth>
  1722. </field>
  1723. <field>
  1724. <name>HTIE</name>
  1725. <description>Half transfer interrupt
  1726. enable</description>
  1727. <bitOffset>2</bitOffset>
  1728. <bitWidth>1</bitWidth>
  1729. </field>
  1730. <field>
  1731. <name>TCIE</name>
  1732. <description>Transfer complete interrupt
  1733. enable</description>
  1734. <bitOffset>1</bitOffset>
  1735. <bitWidth>1</bitWidth>
  1736. </field>
  1737. <field>
  1738. <name>EN</name>
  1739. <description>Channel enable</description>
  1740. <bitOffset>0</bitOffset>
  1741. <bitWidth>1</bitWidth>
  1742. </field>
  1743. </fields>
  1744. </register>
  1745. <register>
  1746. <name>CNDTR6</name>
  1747. <displayName>CNDTR6</displayName>
  1748. <description>channel x number of data
  1749. register</description>
  1750. <addressOffset>0x70</addressOffset>
  1751. <size>0x20</size>
  1752. <access>read-write</access>
  1753. <resetValue>0x00000000</resetValue>
  1754. <fields>
  1755. <field>
  1756. <name>NDT</name>
  1757. <description>Number of data to transfer</description>
  1758. <bitOffset>0</bitOffset>
  1759. <bitWidth>16</bitWidth>
  1760. </field>
  1761. </fields>
  1762. </register>
  1763. <register>
  1764. <name>CPAR6</name>
  1765. <displayName>CPAR6</displayName>
  1766. <description>channel x peripheral address
  1767. register</description>
  1768. <addressOffset>0x74</addressOffset>
  1769. <size>0x20</size>
  1770. <access>read-write</access>
  1771. <resetValue>0x00000000</resetValue>
  1772. <fields>
  1773. <field>
  1774. <name>PA</name>
  1775. <description>Peripheral address</description>
  1776. <bitOffset>0</bitOffset>
  1777. <bitWidth>32</bitWidth>
  1778. </field>
  1779. </fields>
  1780. </register>
  1781. <register>
  1782. <name>CMAR6</name>
  1783. <displayName>CMAR6</displayName>
  1784. <description>channel x memory address
  1785. register</description>
  1786. <addressOffset>0x78</addressOffset>
  1787. <size>0x20</size>
  1788. <access>read-write</access>
  1789. <resetValue>0x00000000</resetValue>
  1790. <fields>
  1791. <field>
  1792. <name>MA</name>
  1793. <description>Memory address</description>
  1794. <bitOffset>0</bitOffset>
  1795. <bitWidth>32</bitWidth>
  1796. </field>
  1797. </fields>
  1798. </register>
  1799. <register>
  1800. <name>CCR7</name>
  1801. <displayName>CCR7</displayName>
  1802. <description>channel x configuration
  1803. register</description>
  1804. <addressOffset>0x80</addressOffset>
  1805. <size>0x20</size>
  1806. <access>read-write</access>
  1807. <resetValue>0x00000000</resetValue>
  1808. <fields>
  1809. <field>
  1810. <name>MEM2MEM</name>
  1811. <description>Memory to memory mode</description>
  1812. <bitOffset>14</bitOffset>
  1813. <bitWidth>1</bitWidth>
  1814. </field>
  1815. <field>
  1816. <name>PL</name>
  1817. <description>Channel priority level</description>
  1818. <bitOffset>12</bitOffset>
  1819. <bitWidth>2</bitWidth>
  1820. </field>
  1821. <field>
  1822. <name>MSIZE</name>
  1823. <description>Memory size</description>
  1824. <bitOffset>10</bitOffset>
  1825. <bitWidth>2</bitWidth>
  1826. </field>
  1827. <field>
  1828. <name>PSIZE</name>
  1829. <description>Peripheral size</description>
  1830. <bitOffset>8</bitOffset>
  1831. <bitWidth>2</bitWidth>
  1832. </field>
  1833. <field>
  1834. <name>MINC</name>
  1835. <description>Memory increment mode</description>
  1836. <bitOffset>7</bitOffset>
  1837. <bitWidth>1</bitWidth>
  1838. </field>
  1839. <field>
  1840. <name>PINC</name>
  1841. <description>Peripheral increment mode</description>
  1842. <bitOffset>6</bitOffset>
  1843. <bitWidth>1</bitWidth>
  1844. </field>
  1845. <field>
  1846. <name>CIRC</name>
  1847. <description>Circular mode</description>
  1848. <bitOffset>5</bitOffset>
  1849. <bitWidth>1</bitWidth>
  1850. </field>
  1851. <field>
  1852. <name>DIR</name>
  1853. <description>Data transfer direction</description>
  1854. <bitOffset>4</bitOffset>
  1855. <bitWidth>1</bitWidth>
  1856. </field>
  1857. <field>
  1858. <name>TEIE</name>
  1859. <description>Transfer error interrupt
  1860. enable</description>
  1861. <bitOffset>3</bitOffset>
  1862. <bitWidth>1</bitWidth>
  1863. </field>
  1864. <field>
  1865. <name>HTIE</name>
  1866. <description>Half transfer interrupt
  1867. enable</description>
  1868. <bitOffset>2</bitOffset>
  1869. <bitWidth>1</bitWidth>
  1870. </field>
  1871. <field>
  1872. <name>TCIE</name>
  1873. <description>Transfer complete interrupt
  1874. enable</description>
  1875. <bitOffset>1</bitOffset>
  1876. <bitWidth>1</bitWidth>
  1877. </field>
  1878. <field>
  1879. <name>EN</name>
  1880. <description>Channel enable</description>
  1881. <bitOffset>0</bitOffset>
  1882. <bitWidth>1</bitWidth>
  1883. </field>
  1884. </fields>
  1885. </register>
  1886. <register>
  1887. <name>CNDTR7</name>
  1888. <displayName>CNDTR7</displayName>
  1889. <description>channel x number of data
  1890. register</description>
  1891. <addressOffset>0x84</addressOffset>
  1892. <size>0x20</size>
  1893. <access>read-write</access>
  1894. <resetValue>0x00000000</resetValue>
  1895. <fields>
  1896. <field>
  1897. <name>NDT</name>
  1898. <description>Number of data to transfer</description>
  1899. <bitOffset>0</bitOffset>
  1900. <bitWidth>16</bitWidth>
  1901. </field>
  1902. </fields>
  1903. </register>
  1904. <register>
  1905. <name>CPAR7</name>
  1906. <displayName>CPAR7</displayName>
  1907. <description>channel x peripheral address
  1908. register</description>
  1909. <addressOffset>0x88</addressOffset>
  1910. <size>0x20</size>
  1911. <access>read-write</access>
  1912. <resetValue>0x00000000</resetValue>
  1913. <fields>
  1914. <field>
  1915. <name>PA</name>
  1916. <description>Peripheral address</description>
  1917. <bitOffset>0</bitOffset>
  1918. <bitWidth>32</bitWidth>
  1919. </field>
  1920. </fields>
  1921. </register>
  1922. <register>
  1923. <name>CMAR7</name>
  1924. <displayName>CMAR7</displayName>
  1925. <description>channel x memory address
  1926. register</description>
  1927. <addressOffset>0x8C</addressOffset>
  1928. <size>0x20</size>
  1929. <access>read-write</access>
  1930. <resetValue>0x00000000</resetValue>
  1931. <fields>
  1932. <field>
  1933. <name>MA</name>
  1934. <description>Memory address</description>
  1935. <bitOffset>0</bitOffset>
  1936. <bitWidth>32</bitWidth>
  1937. </field>
  1938. </fields>
  1939. </register>
  1940. <register>
  1941. <name>CSELR</name>
  1942. <displayName>CSELR</displayName>
  1943. <description>channel selection register</description>
  1944. <addressOffset>0xA8</addressOffset>
  1945. <size>0x20</size>
  1946. <access>read-write</access>
  1947. <resetValue>0x00000000</resetValue>
  1948. <fields>
  1949. <field>
  1950. <name>C7S</name>
  1951. <description>DMA channel 7 selection</description>
  1952. <bitOffset>24</bitOffset>
  1953. <bitWidth>4</bitWidth>
  1954. </field>
  1955. <field>
  1956. <name>C6S</name>
  1957. <description>DMA channel 6 selection</description>
  1958. <bitOffset>20</bitOffset>
  1959. <bitWidth>4</bitWidth>
  1960. </field>
  1961. <field>
  1962. <name>C5S</name>
  1963. <description>DMA channel 5 selection</description>
  1964. <bitOffset>16</bitOffset>
  1965. <bitWidth>4</bitWidth>
  1966. </field>
  1967. <field>
  1968. <name>C4S</name>
  1969. <description>DMA channel 4 selection</description>
  1970. <bitOffset>12</bitOffset>
  1971. <bitWidth>4</bitWidth>
  1972. </field>
  1973. <field>
  1974. <name>C3S</name>
  1975. <description>DMA channel 3 selection</description>
  1976. <bitOffset>8</bitOffset>
  1977. <bitWidth>4</bitWidth>
  1978. </field>
  1979. <field>
  1980. <name>C2S</name>
  1981. <description>DMA channel 2 selection</description>
  1982. <bitOffset>4</bitOffset>
  1983. <bitWidth>4</bitWidth>
  1984. </field>
  1985. <field>
  1986. <name>C1S</name>
  1987. <description>DMA channel 1 selection</description>
  1988. <bitOffset>0</bitOffset>
  1989. <bitWidth>4</bitWidth>
  1990. </field>
  1991. </fields>
  1992. </register>
  1993. </registers>
  1994. </peripheral>
  1995. <peripheral>
  1996. <name>CRC</name>
  1997. <description>Cyclic redundancy check calculation
  1998. unit</description>
  1999. <groupName>CRC</groupName>
  2000. <baseAddress>0x40023000</baseAddress>
  2001. <addressBlock>
  2002. <offset>0x0</offset>
  2003. <size>0x400</size>
  2004. <usage>registers</usage>
  2005. </addressBlock>
  2006. <registers>
  2007. <register>
  2008. <name>DR</name>
  2009. <displayName>DR</displayName>
  2010. <description>Data register</description>
  2011. <addressOffset>0x0</addressOffset>
  2012. <size>0x20</size>
  2013. <access>read-write</access>
  2014. <resetValue>0xFFFFFFFF</resetValue>
  2015. <fields>
  2016. <field>
  2017. <name>DR</name>
  2018. <description>Data register bits</description>
  2019. <bitOffset>0</bitOffset>
  2020. <bitWidth>32</bitWidth>
  2021. </field>
  2022. </fields>
  2023. </register>
  2024. <register>
  2025. <name>IDR</name>
  2026. <displayName>IDR</displayName>
  2027. <description>Independent data register</description>
  2028. <addressOffset>0x4</addressOffset>
  2029. <size>0x20</size>
  2030. <access>read-write</access>
  2031. <resetValue>0x00000000</resetValue>
  2032. <fields>
  2033. <field>
  2034. <name>IDR</name>
  2035. <description>General-purpose 8-bit data register
  2036. bits</description>
  2037. <bitOffset>0</bitOffset>
  2038. <bitWidth>8</bitWidth>
  2039. </field>
  2040. </fields>
  2041. </register>
  2042. <register>
  2043. <name>CR</name>
  2044. <displayName>CR</displayName>
  2045. <description>Control register</description>
  2046. <addressOffset>0x8</addressOffset>
  2047. <size>0x20</size>
  2048. <resetValue>0x00000000</resetValue>
  2049. <fields>
  2050. <field>
  2051. <name>REV_OUT</name>
  2052. <description>Reverse output data</description>
  2053. <bitOffset>7</bitOffset>
  2054. <bitWidth>1</bitWidth>
  2055. <access>read-write</access>
  2056. </field>
  2057. <field>
  2058. <name>REV_IN</name>
  2059. <description>Reverse input data</description>
  2060. <bitOffset>5</bitOffset>
  2061. <bitWidth>2</bitWidth>
  2062. <access>read-write</access>
  2063. </field>
  2064. <field>
  2065. <name>POLYSIZE</name>
  2066. <description>Polynomial size</description>
  2067. <bitOffset>3</bitOffset>
  2068. <bitWidth>2</bitWidth>
  2069. <access>read-write</access>
  2070. </field>
  2071. <field>
  2072. <name>RESET</name>
  2073. <description>RESET bit</description>
  2074. <bitOffset>0</bitOffset>
  2075. <bitWidth>1</bitWidth>
  2076. <access>write-only</access>
  2077. </field>
  2078. </fields>
  2079. </register>
  2080. <register>
  2081. <name>INIT</name>
  2082. <displayName>INIT</displayName>
  2083. <description>Initial CRC value</description>
  2084. <addressOffset>0x10</addressOffset>
  2085. <size>0x20</size>
  2086. <access>read-write</access>
  2087. <resetValue>0xFFFFFFFF</resetValue>
  2088. <fields>
  2089. <field>
  2090. <name>CRC_INIT</name>
  2091. <description>Programmable initial CRC
  2092. value</description>
  2093. <bitOffset>0</bitOffset>
  2094. <bitWidth>32</bitWidth>
  2095. </field>
  2096. </fields>
  2097. </register>
  2098. <register>
  2099. <name>POL</name>
  2100. <displayName>POL</displayName>
  2101. <description>polynomial</description>
  2102. <addressOffset>0x14</addressOffset>
  2103. <size>0x20</size>
  2104. <access>read-write</access>
  2105. <resetValue>0x04C11DB7</resetValue>
  2106. <fields>
  2107. <field>
  2108. <name>Polynomialcoefficients</name>
  2109. <description>Programmable polynomial</description>
  2110. <bitOffset>0</bitOffset>
  2111. <bitWidth>32</bitWidth>
  2112. </field>
  2113. </fields>
  2114. </register>
  2115. </registers>
  2116. </peripheral>
  2117. <peripheral>
  2118. <name>GPIOA</name>
  2119. <description>General-purpose I/Os</description>
  2120. <groupName>GPIO</groupName>
  2121. <baseAddress>0x50000000</baseAddress>
  2122. <addressBlock>
  2123. <offset>0x0</offset>
  2124. <size>0x400</size>
  2125. <usage>registers</usage>
  2126. </addressBlock>
  2127. <registers>
  2128. <register>
  2129. <name>MODER</name>
  2130. <displayName>MODER</displayName>
  2131. <description>GPIO port mode register</description>
  2132. <addressOffset>0x0</addressOffset>
  2133. <size>0x20</size>
  2134. <access>read-write</access>
  2135. <resetValue>0xEBFFFCFF</resetValue>
  2136. <fields>
  2137. <field>
  2138. <name>MODE0</name>
  2139. <description>Port x configuration bits (y =
  2140. 0..15)</description>
  2141. <bitOffset>0</bitOffset>
  2142. <bitWidth>2</bitWidth>
  2143. </field>
  2144. <field>
  2145. <name>MODE1</name>
  2146. <description>Port x configuration bits (y =
  2147. 0..15)</description>
  2148. <bitOffset>2</bitOffset>
  2149. <bitWidth>2</bitWidth>
  2150. </field>
  2151. <field>
  2152. <name>MODE2</name>
  2153. <description>Port x configuration bits (y =
  2154. 0..15)</description>
  2155. <bitOffset>4</bitOffset>
  2156. <bitWidth>2</bitWidth>
  2157. </field>
  2158. <field>
  2159. <name>MODE3</name>
  2160. <description>Port x configuration bits (y =
  2161. 0..15)</description>
  2162. <bitOffset>6</bitOffset>
  2163. <bitWidth>2</bitWidth>
  2164. </field>
  2165. <field>
  2166. <name>MODE4</name>
  2167. <description>Port x configuration bits (y =
  2168. 0..15)</description>
  2169. <bitOffset>8</bitOffset>
  2170. <bitWidth>2</bitWidth>
  2171. </field>
  2172. <field>
  2173. <name>MODE5</name>
  2174. <description>Port x configuration bits (y =
  2175. 0..15)</description>
  2176. <bitOffset>10</bitOffset>
  2177. <bitWidth>2</bitWidth>
  2178. </field>
  2179. <field>
  2180. <name>MODE6</name>
  2181. <description>Port x configuration bits (y =
  2182. 0..15)</description>
  2183. <bitOffset>12</bitOffset>
  2184. <bitWidth>2</bitWidth>
  2185. </field>
  2186. <field>
  2187. <name>MODE7</name>
  2188. <description>Port x configuration bits (y =
  2189. 0..15)</description>
  2190. <bitOffset>14</bitOffset>
  2191. <bitWidth>2</bitWidth>
  2192. </field>
  2193. <field>
  2194. <name>MODE8</name>
  2195. <description>Port x configuration bits (y =
  2196. 0..15)</description>
  2197. <bitOffset>16</bitOffset>
  2198. <bitWidth>2</bitWidth>
  2199. </field>
  2200. <field>
  2201. <name>MODE9</name>
  2202. <description>Port x configuration bits (y =
  2203. 0..15)</description>
  2204. <bitOffset>18</bitOffset>
  2205. <bitWidth>2</bitWidth>
  2206. </field>
  2207. <field>
  2208. <name>MODE10</name>
  2209. <description>Port x configuration bits (y =
  2210. 0..15)</description>
  2211. <bitOffset>20</bitOffset>
  2212. <bitWidth>2</bitWidth>
  2213. </field>
  2214. <field>
  2215. <name>MODE11</name>
  2216. <description>Port x configuration bits (y =
  2217. 0..15)</description>
  2218. <bitOffset>22</bitOffset>
  2219. <bitWidth>2</bitWidth>
  2220. </field>
  2221. <field>
  2222. <name>MODE12</name>
  2223. <description>Port x configuration bits (y =
  2224. 0..15)</description>
  2225. <bitOffset>24</bitOffset>
  2226. <bitWidth>2</bitWidth>
  2227. </field>
  2228. <field>
  2229. <name>MODE13</name>
  2230. <description>Port x configuration bits (y =
  2231. 0..15)</description>
  2232. <bitOffset>26</bitOffset>
  2233. <bitWidth>2</bitWidth>
  2234. </field>
  2235. <field>
  2236. <name>MODE14</name>
  2237. <description>Port x configuration bits (y =
  2238. 0..15)</description>
  2239. <bitOffset>28</bitOffset>
  2240. <bitWidth>2</bitWidth>
  2241. </field>
  2242. <field>
  2243. <name>MODE15</name>
  2244. <description>Port x configuration bits (y =
  2245. 0..15)</description>
  2246. <bitOffset>30</bitOffset>
  2247. <bitWidth>2</bitWidth>
  2248. </field>
  2249. </fields>
  2250. </register>
  2251. <register>
  2252. <name>OTYPER</name>
  2253. <displayName>OTYPER</displayName>
  2254. <description>GPIO port output type register</description>
  2255. <addressOffset>0x4</addressOffset>
  2256. <size>0x20</size>
  2257. <access>read-write</access>
  2258. <resetValue>0x00000000</resetValue>
  2259. <fields>
  2260. <field>
  2261. <name>OT15</name>
  2262. <description>Port x configuration bits (y =
  2263. 0..15)</description>
  2264. <bitOffset>15</bitOffset>
  2265. <bitWidth>1</bitWidth>
  2266. </field>
  2267. <field>
  2268. <name>OT14</name>
  2269. <description>Port x configuration bits (y =
  2270. 0..15)</description>
  2271. <bitOffset>14</bitOffset>
  2272. <bitWidth>1</bitWidth>
  2273. </field>
  2274. <field>
  2275. <name>OT13</name>
  2276. <description>Port x configuration bits (y =
  2277. 0..15)</description>
  2278. <bitOffset>13</bitOffset>
  2279. <bitWidth>1</bitWidth>
  2280. </field>
  2281. <field>
  2282. <name>OT12</name>
  2283. <description>Port x configuration bits (y =
  2284. 0..15)</description>
  2285. <bitOffset>12</bitOffset>
  2286. <bitWidth>1</bitWidth>
  2287. </field>
  2288. <field>
  2289. <name>OT11</name>
  2290. <description>Port x configuration bits (y =
  2291. 0..15)</description>
  2292. <bitOffset>11</bitOffset>
  2293. <bitWidth>1</bitWidth>
  2294. </field>
  2295. <field>
  2296. <name>OT10</name>
  2297. <description>Port x configuration bits (y =
  2298. 0..15)</description>
  2299. <bitOffset>10</bitOffset>
  2300. <bitWidth>1</bitWidth>
  2301. </field>
  2302. <field>
  2303. <name>OT9</name>
  2304. <description>Port x configuration bits (y =
  2305. 0..15)</description>
  2306. <bitOffset>9</bitOffset>
  2307. <bitWidth>1</bitWidth>
  2308. </field>
  2309. <field>
  2310. <name>OT8</name>
  2311. <description>Port x configuration bits (y =
  2312. 0..15)</description>
  2313. <bitOffset>8</bitOffset>
  2314. <bitWidth>1</bitWidth>
  2315. </field>
  2316. <field>
  2317. <name>OT7</name>
  2318. <description>Port x configuration bits (y =
  2319. 0..15)</description>
  2320. <bitOffset>7</bitOffset>
  2321. <bitWidth>1</bitWidth>
  2322. </field>
  2323. <field>
  2324. <name>OT6</name>
  2325. <description>Port x configuration bits (y =
  2326. 0..15)</description>
  2327. <bitOffset>6</bitOffset>
  2328. <bitWidth>1</bitWidth>
  2329. </field>
  2330. <field>
  2331. <name>OT5</name>
  2332. <description>Port x configuration bits (y =
  2333. 0..15)</description>
  2334. <bitOffset>5</bitOffset>
  2335. <bitWidth>1</bitWidth>
  2336. </field>
  2337. <field>
  2338. <name>OT4</name>
  2339. <description>Port x configuration bits (y =
  2340. 0..15)</description>
  2341. <bitOffset>4</bitOffset>
  2342. <bitWidth>1</bitWidth>
  2343. </field>
  2344. <field>
  2345. <name>OT3</name>
  2346. <description>Port x configuration bits (y =
  2347. 0..15)</description>
  2348. <bitOffset>3</bitOffset>
  2349. <bitWidth>1</bitWidth>
  2350. </field>
  2351. <field>
  2352. <name>OT2</name>
  2353. <description>Port x configuration bits (y =
  2354. 0..15)</description>
  2355. <bitOffset>2</bitOffset>
  2356. <bitWidth>1</bitWidth>
  2357. </field>
  2358. <field>
  2359. <name>OT1</name>
  2360. <description>Port x configuration bits (y =
  2361. 0..15)</description>
  2362. <bitOffset>1</bitOffset>
  2363. <bitWidth>1</bitWidth>
  2364. </field>
  2365. <field>
  2366. <name>OT0</name>
  2367. <description>Port x configuration bits (y =
  2368. 0..15)</description>
  2369. <bitOffset>0</bitOffset>
  2370. <bitWidth>1</bitWidth>
  2371. </field>
  2372. </fields>
  2373. </register>
  2374. <register>
  2375. <name>OSPEEDR</name>
  2376. <displayName>OSPEEDR</displayName>
  2377. <description>GPIO port output speed
  2378. register</description>
  2379. <addressOffset>0x8</addressOffset>
  2380. <size>0x20</size>
  2381. <access>read-write</access>
  2382. <resetValue>0x00000000</resetValue>
  2383. <fields>
  2384. <field>
  2385. <name>OSPEED15</name>
  2386. <description>Port x configuration bits (y =
  2387. 0..15)</description>
  2388. <bitOffset>30</bitOffset>
  2389. <bitWidth>2</bitWidth>
  2390. </field>
  2391. <field>
  2392. <name>OSPEED14</name>
  2393. <description>Port x configuration bits (y =
  2394. 0..15)</description>
  2395. <bitOffset>28</bitOffset>
  2396. <bitWidth>2</bitWidth>
  2397. </field>
  2398. <field>
  2399. <name>OSPEED13</name>
  2400. <description>Port x configuration bits (y =
  2401. 0..15)</description>
  2402. <bitOffset>26</bitOffset>
  2403. <bitWidth>2</bitWidth>
  2404. </field>
  2405. <field>
  2406. <name>OSPEED12</name>
  2407. <description>Port x configuration bits (y =
  2408. 0..15)</description>
  2409. <bitOffset>24</bitOffset>
  2410. <bitWidth>2</bitWidth>
  2411. </field>
  2412. <field>
  2413. <name>OSPEED11</name>
  2414. <description>Port x configuration bits (y =
  2415. 0..15)</description>
  2416. <bitOffset>22</bitOffset>
  2417. <bitWidth>2</bitWidth>
  2418. </field>
  2419. <field>
  2420. <name>OSPEED10</name>
  2421. <description>Port x configuration bits (y =
  2422. 0..15)</description>
  2423. <bitOffset>20</bitOffset>
  2424. <bitWidth>2</bitWidth>
  2425. </field>
  2426. <field>
  2427. <name>OSPEED9</name>
  2428. <description>Port x configuration bits (y =
  2429. 0..15)</description>
  2430. <bitOffset>18</bitOffset>
  2431. <bitWidth>2</bitWidth>
  2432. </field>
  2433. <field>
  2434. <name>OSPEED8</name>
  2435. <description>Port x configuration bits (y =
  2436. 0..15)</description>
  2437. <bitOffset>16</bitOffset>
  2438. <bitWidth>2</bitWidth>
  2439. </field>
  2440. <field>
  2441. <name>OSPEED7</name>
  2442. <description>Port x configuration bits (y =
  2443. 0..15)</description>
  2444. <bitOffset>14</bitOffset>
  2445. <bitWidth>2</bitWidth>
  2446. </field>
  2447. <field>
  2448. <name>OSPEED6</name>
  2449. <description>Port x configuration bits (y =
  2450. 0..15)</description>
  2451. <bitOffset>12</bitOffset>
  2452. <bitWidth>2</bitWidth>
  2453. </field>
  2454. <field>
  2455. <name>OSPEED5</name>
  2456. <description>Port x configuration bits (y =
  2457. 0..15)</description>
  2458. <bitOffset>10</bitOffset>
  2459. <bitWidth>2</bitWidth>
  2460. </field>
  2461. <field>
  2462. <name>OSPEED4</name>
  2463. <description>Port x configuration bits (y =
  2464. 0..15)</description>
  2465. <bitOffset>8</bitOffset>
  2466. <bitWidth>2</bitWidth>
  2467. </field>
  2468. <field>
  2469. <name>OSPEED3</name>
  2470. <description>Port x configuration bits (y =
  2471. 0..15)</description>
  2472. <bitOffset>6</bitOffset>
  2473. <bitWidth>2</bitWidth>
  2474. </field>
  2475. <field>
  2476. <name>OSPEED2</name>
  2477. <description>Port x configuration bits (y =
  2478. 0..15)</description>
  2479. <bitOffset>4</bitOffset>
  2480. <bitWidth>2</bitWidth>
  2481. </field>
  2482. <field>
  2483. <name>OSPEED1</name>
  2484. <description>Port x configuration bits (y =
  2485. 0..15)</description>
  2486. <bitOffset>2</bitOffset>
  2487. <bitWidth>2</bitWidth>
  2488. </field>
  2489. <field>
  2490. <name>OSPEED0</name>
  2491. <description>Port x configuration bits (y =
  2492. 0..15)</description>
  2493. <bitOffset>0</bitOffset>
  2494. <bitWidth>2</bitWidth>
  2495. </field>
  2496. </fields>
  2497. </register>
  2498. <register>
  2499. <name>PUPDR</name>
  2500. <displayName>PUPDR</displayName>
  2501. <description>GPIO port pull-up/pull-down
  2502. register</description>
  2503. <addressOffset>0xC</addressOffset>
  2504. <size>0x20</size>
  2505. <access>read-write</access>
  2506. <resetValue>0x24000000</resetValue>
  2507. <fields>
  2508. <field>
  2509. <name>PUPD15</name>
  2510. <description>Port x configuration bits (y =
  2511. 0..15)</description>
  2512. <bitOffset>30</bitOffset>
  2513. <bitWidth>2</bitWidth>
  2514. </field>
  2515. <field>
  2516. <name>PUPD14</name>
  2517. <description>Port x configuration bits (y =
  2518. 0..15)</description>
  2519. <bitOffset>28</bitOffset>
  2520. <bitWidth>2</bitWidth>
  2521. </field>
  2522. <field>
  2523. <name>PUPD13</name>
  2524. <description>Port x configuration bits (y =
  2525. 0..15)</description>
  2526. <bitOffset>26</bitOffset>
  2527. <bitWidth>2</bitWidth>
  2528. </field>
  2529. <field>
  2530. <name>PUPD12</name>
  2531. <description>Port x configuration bits (y =
  2532. 0..15)</description>
  2533. <bitOffset>24</bitOffset>
  2534. <bitWidth>2</bitWidth>
  2535. </field>
  2536. <field>
  2537. <name>PUPD11</name>
  2538. <description>Port x configuration bits (y =
  2539. 0..15)</description>
  2540. <bitOffset>22</bitOffset>
  2541. <bitWidth>2</bitWidth>
  2542. </field>
  2543. <field>
  2544. <name>PUPD10</name>
  2545. <description>Port x configuration bits (y =
  2546. 0..15)</description>
  2547. <bitOffset>20</bitOffset>
  2548. <bitWidth>2</bitWidth>
  2549. </field>
  2550. <field>
  2551. <name>PUPD9</name>
  2552. <description>Port x configuration bits (y =
  2553. 0..15)</description>
  2554. <bitOffset>18</bitOffset>
  2555. <bitWidth>2</bitWidth>
  2556. </field>
  2557. <field>
  2558. <name>PUPD8</name>
  2559. <description>Port x configuration bits (y =
  2560. 0..15)</description>
  2561. <bitOffset>16</bitOffset>
  2562. <bitWidth>2</bitWidth>
  2563. </field>
  2564. <field>
  2565. <name>PUPD7</name>
  2566. <description>Port x configuration bits (y =
  2567. 0..15)</description>
  2568. <bitOffset>14</bitOffset>
  2569. <bitWidth>2</bitWidth>
  2570. </field>
  2571. <field>
  2572. <name>PUPD6</name>
  2573. <description>Port x configuration bits (y =
  2574. 0..15)</description>
  2575. <bitOffset>12</bitOffset>
  2576. <bitWidth>2</bitWidth>
  2577. </field>
  2578. <field>
  2579. <name>PUPD5</name>
  2580. <description>Port x configuration bits (y =
  2581. 0..15)</description>
  2582. <bitOffset>10</bitOffset>
  2583. <bitWidth>2</bitWidth>
  2584. </field>
  2585. <field>
  2586. <name>PUPD4</name>
  2587. <description>Port x configuration bits (y =
  2588. 0..15)</description>
  2589. <bitOffset>8</bitOffset>
  2590. <bitWidth>2</bitWidth>
  2591. </field>
  2592. <field>
  2593. <name>PUPD3</name>
  2594. <description>Port x configuration bits (y =
  2595. 0..15)</description>
  2596. <bitOffset>6</bitOffset>
  2597. <bitWidth>2</bitWidth>
  2598. </field>
  2599. <field>
  2600. <name>PUPD2</name>
  2601. <description>Port x configuration bits (y =
  2602. 0..15)</description>
  2603. <bitOffset>4</bitOffset>
  2604. <bitWidth>2</bitWidth>
  2605. </field>
  2606. <field>
  2607. <name>PUPD1</name>
  2608. <description>Port x configuration bits (y =
  2609. 0..15)</description>
  2610. <bitOffset>2</bitOffset>
  2611. <bitWidth>2</bitWidth>
  2612. </field>
  2613. <field>
  2614. <name>PUPD0</name>
  2615. <description>Port x configuration bits (y =
  2616. 0..15)</description>
  2617. <bitOffset>0</bitOffset>
  2618. <bitWidth>2</bitWidth>
  2619. </field>
  2620. </fields>
  2621. </register>
  2622. <register>
  2623. <name>IDR</name>
  2624. <displayName>IDR</displayName>
  2625. <description>GPIO port input data register</description>
  2626. <addressOffset>0x10</addressOffset>
  2627. <size>0x20</size>
  2628. <access>read-only</access>
  2629. <resetValue>0x00000000</resetValue>
  2630. <fields>
  2631. <field>
  2632. <name>ID15</name>
  2633. <description>Port input data bit (y =
  2634. 0..15)</description>
  2635. <bitOffset>15</bitOffset>
  2636. <bitWidth>1</bitWidth>
  2637. </field>
  2638. <field>
  2639. <name>ID14</name>
  2640. <description>Port input data bit (y =
  2641. 0..15)</description>
  2642. <bitOffset>14</bitOffset>
  2643. <bitWidth>1</bitWidth>
  2644. </field>
  2645. <field>
  2646. <name>ID13</name>
  2647. <description>Port input data bit (y =
  2648. 0..15)</description>
  2649. <bitOffset>13</bitOffset>
  2650. <bitWidth>1</bitWidth>
  2651. </field>
  2652. <field>
  2653. <name>ID12</name>
  2654. <description>Port input data bit (y =
  2655. 0..15)</description>
  2656. <bitOffset>12</bitOffset>
  2657. <bitWidth>1</bitWidth>
  2658. </field>
  2659. <field>
  2660. <name>ID11</name>
  2661. <description>Port input data bit (y =
  2662. 0..15)</description>
  2663. <bitOffset>11</bitOffset>
  2664. <bitWidth>1</bitWidth>
  2665. </field>
  2666. <field>
  2667. <name>ID10</name>
  2668. <description>Port input data bit (y =
  2669. 0..15)</description>
  2670. <bitOffset>10</bitOffset>
  2671. <bitWidth>1</bitWidth>
  2672. </field>
  2673. <field>
  2674. <name>ID9</name>
  2675. <description>Port input data bit (y =
  2676. 0..15)</description>
  2677. <bitOffset>9</bitOffset>
  2678. <bitWidth>1</bitWidth>
  2679. </field>
  2680. <field>
  2681. <name>ID8</name>
  2682. <description>Port input data bit (y =
  2683. 0..15)</description>
  2684. <bitOffset>8</bitOffset>
  2685. <bitWidth>1</bitWidth>
  2686. </field>
  2687. <field>
  2688. <name>ID7</name>
  2689. <description>Port input data bit (y =
  2690. 0..15)</description>
  2691. <bitOffset>7</bitOffset>
  2692. <bitWidth>1</bitWidth>
  2693. </field>
  2694. <field>
  2695. <name>ID6</name>
  2696. <description>Port input data bit (y =
  2697. 0..15)</description>
  2698. <bitOffset>6</bitOffset>
  2699. <bitWidth>1</bitWidth>
  2700. </field>
  2701. <field>
  2702. <name>ID5</name>
  2703. <description>Port input data bit (y =
  2704. 0..15)</description>
  2705. <bitOffset>5</bitOffset>
  2706. <bitWidth>1</bitWidth>
  2707. </field>
  2708. <field>
  2709. <name>ID4</name>
  2710. <description>Port input data bit (y =
  2711. 0..15)</description>
  2712. <bitOffset>4</bitOffset>
  2713. <bitWidth>1</bitWidth>
  2714. </field>
  2715. <field>
  2716. <name>ID3</name>
  2717. <description>Port input data bit (y =
  2718. 0..15)</description>
  2719. <bitOffset>3</bitOffset>
  2720. <bitWidth>1</bitWidth>
  2721. </field>
  2722. <field>
  2723. <name>ID2</name>
  2724. <description>Port input data bit (y =
  2725. 0..15)</description>
  2726. <bitOffset>2</bitOffset>
  2727. <bitWidth>1</bitWidth>
  2728. </field>
  2729. <field>
  2730. <name>ID1</name>
  2731. <description>Port input data bit (y =
  2732. 0..15)</description>
  2733. <bitOffset>1</bitOffset>
  2734. <bitWidth>1</bitWidth>
  2735. </field>
  2736. <field>
  2737. <name>ID0</name>
  2738. <description>Port input data bit (y =
  2739. 0..15)</description>
  2740. <bitOffset>0</bitOffset>
  2741. <bitWidth>1</bitWidth>
  2742. </field>
  2743. </fields>
  2744. </register>
  2745. <register>
  2746. <name>ODR</name>
  2747. <displayName>ODR</displayName>
  2748. <description>GPIO port output data register</description>
  2749. <addressOffset>0x14</addressOffset>
  2750. <size>0x20</size>
  2751. <access>read-write</access>
  2752. <resetValue>0x00000000</resetValue>
  2753. <fields>
  2754. <field>
  2755. <name>OD15</name>
  2756. <description>Port output data bit (y =
  2757. 0..15)</description>
  2758. <bitOffset>15</bitOffset>
  2759. <bitWidth>1</bitWidth>
  2760. </field>
  2761. <field>
  2762. <name>OD14</name>
  2763. <description>Port output data bit (y =
  2764. 0..15)</description>
  2765. <bitOffset>14</bitOffset>
  2766. <bitWidth>1</bitWidth>
  2767. </field>
  2768. <field>
  2769. <name>OD13</name>
  2770. <description>Port output data bit (y =
  2771. 0..15)</description>
  2772. <bitOffset>13</bitOffset>
  2773. <bitWidth>1</bitWidth>
  2774. </field>
  2775. <field>
  2776. <name>OD12</name>
  2777. <description>Port output data bit (y =
  2778. 0..15)</description>
  2779. <bitOffset>12</bitOffset>
  2780. <bitWidth>1</bitWidth>
  2781. </field>
  2782. <field>
  2783. <name>OD11</name>
  2784. <description>Port output data bit (y =
  2785. 0..15)</description>
  2786. <bitOffset>11</bitOffset>
  2787. <bitWidth>1</bitWidth>
  2788. </field>
  2789. <field>
  2790. <name>OD10</name>
  2791. <description>Port output data bit (y =
  2792. 0..15)</description>
  2793. <bitOffset>10</bitOffset>
  2794. <bitWidth>1</bitWidth>
  2795. </field>
  2796. <field>
  2797. <name>OD9</name>
  2798. <description>Port output data bit (y =
  2799. 0..15)</description>
  2800. <bitOffset>9</bitOffset>
  2801. <bitWidth>1</bitWidth>
  2802. </field>
  2803. <field>
  2804. <name>OD8</name>
  2805. <description>Port output data bit (y =
  2806. 0..15)</description>
  2807. <bitOffset>8</bitOffset>
  2808. <bitWidth>1</bitWidth>
  2809. </field>
  2810. <field>
  2811. <name>OD7</name>
  2812. <description>Port output data bit (y =
  2813. 0..15)</description>
  2814. <bitOffset>7</bitOffset>
  2815. <bitWidth>1</bitWidth>
  2816. </field>
  2817. <field>
  2818. <name>OD6</name>
  2819. <description>Port output data bit (y =
  2820. 0..15)</description>
  2821. <bitOffset>6</bitOffset>
  2822. <bitWidth>1</bitWidth>
  2823. </field>
  2824. <field>
  2825. <name>OD5</name>
  2826. <description>Port output data bit (y =
  2827. 0..15)</description>
  2828. <bitOffset>5</bitOffset>
  2829. <bitWidth>1</bitWidth>
  2830. </field>
  2831. <field>
  2832. <name>OD4</name>
  2833. <description>Port output data bit (y =
  2834. 0..15)</description>
  2835. <bitOffset>4</bitOffset>
  2836. <bitWidth>1</bitWidth>
  2837. </field>
  2838. <field>
  2839. <name>OD3</name>
  2840. <description>Port output data bit (y =
  2841. 0..15)</description>
  2842. <bitOffset>3</bitOffset>
  2843. <bitWidth>1</bitWidth>
  2844. </field>
  2845. <field>
  2846. <name>OD2</name>
  2847. <description>Port output data bit (y =
  2848. 0..15)</description>
  2849. <bitOffset>2</bitOffset>
  2850. <bitWidth>1</bitWidth>
  2851. </field>
  2852. <field>
  2853. <name>OD1</name>
  2854. <description>Port output data bit (y =
  2855. 0..15)</description>
  2856. <bitOffset>1</bitOffset>
  2857. <bitWidth>1</bitWidth>
  2858. </field>
  2859. <field>
  2860. <name>OD0</name>
  2861. <description>Port output data bit (y =
  2862. 0..15)</description>
  2863. <bitOffset>0</bitOffset>
  2864. <bitWidth>1</bitWidth>
  2865. </field>
  2866. </fields>
  2867. </register>
  2868. <register>
  2869. <name>BSRR</name>
  2870. <displayName>BSRR</displayName>
  2871. <description>GPIO port bit set/reset
  2872. register</description>
  2873. <addressOffset>0x18</addressOffset>
  2874. <size>0x20</size>
  2875. <access>write-only</access>
  2876. <resetValue>0x00000000</resetValue>
  2877. <fields>
  2878. <field>
  2879. <name>BR15</name>
  2880. <description>Port x reset bit y (y =
  2881. 0..15)</description>
  2882. <bitOffset>31</bitOffset>
  2883. <bitWidth>1</bitWidth>
  2884. </field>
  2885. <field>
  2886. <name>BR14</name>
  2887. <description>Port x reset bit y (y =
  2888. 0..15)</description>
  2889. <bitOffset>30</bitOffset>
  2890. <bitWidth>1</bitWidth>
  2891. </field>
  2892. <field>
  2893. <name>BR13</name>
  2894. <description>Port x reset bit y (y =
  2895. 0..15)</description>
  2896. <bitOffset>29</bitOffset>
  2897. <bitWidth>1</bitWidth>
  2898. </field>
  2899. <field>
  2900. <name>BR12</name>
  2901. <description>Port x reset bit y (y =
  2902. 0..15)</description>
  2903. <bitOffset>28</bitOffset>
  2904. <bitWidth>1</bitWidth>
  2905. </field>
  2906. <field>
  2907. <name>BR11</name>
  2908. <description>Port x reset bit y (y =
  2909. 0..15)</description>
  2910. <bitOffset>27</bitOffset>
  2911. <bitWidth>1</bitWidth>
  2912. </field>
  2913. <field>
  2914. <name>BR10</name>
  2915. <description>Port x reset bit y (y =
  2916. 0..15)</description>
  2917. <bitOffset>26</bitOffset>
  2918. <bitWidth>1</bitWidth>
  2919. </field>
  2920. <field>
  2921. <name>BR9</name>
  2922. <description>Port x reset bit y (y =
  2923. 0..15)</description>
  2924. <bitOffset>25</bitOffset>
  2925. <bitWidth>1</bitWidth>
  2926. </field>
  2927. <field>
  2928. <name>BR8</name>
  2929. <description>Port x reset bit y (y =
  2930. 0..15)</description>
  2931. <bitOffset>24</bitOffset>
  2932. <bitWidth>1</bitWidth>
  2933. </field>
  2934. <field>
  2935. <name>BR7</name>
  2936. <description>Port x reset bit y (y =
  2937. 0..15)</description>
  2938. <bitOffset>23</bitOffset>
  2939. <bitWidth>1</bitWidth>
  2940. </field>
  2941. <field>
  2942. <name>BR6</name>
  2943. <description>Port x reset bit y (y =
  2944. 0..15)</description>
  2945. <bitOffset>22</bitOffset>
  2946. <bitWidth>1</bitWidth>
  2947. </field>
  2948. <field>
  2949. <name>BR5</name>
  2950. <description>Port x reset bit y (y =
  2951. 0..15)</description>
  2952. <bitOffset>21</bitOffset>
  2953. <bitWidth>1</bitWidth>
  2954. </field>
  2955. <field>
  2956. <name>BR4</name>
  2957. <description>Port x reset bit y (y =
  2958. 0..15)</description>
  2959. <bitOffset>20</bitOffset>
  2960. <bitWidth>1</bitWidth>
  2961. </field>
  2962. <field>
  2963. <name>BR3</name>
  2964. <description>Port x reset bit y (y =
  2965. 0..15)</description>
  2966. <bitOffset>19</bitOffset>
  2967. <bitWidth>1</bitWidth>
  2968. </field>
  2969. <field>
  2970. <name>BR2</name>
  2971. <description>Port x reset bit y (y =
  2972. 0..15)</description>
  2973. <bitOffset>18</bitOffset>
  2974. <bitWidth>1</bitWidth>
  2975. </field>
  2976. <field>
  2977. <name>BR1</name>
  2978. <description>Port x reset bit y (y =
  2979. 0..15)</description>
  2980. <bitOffset>17</bitOffset>
  2981. <bitWidth>1</bitWidth>
  2982. </field>
  2983. <field>
  2984. <name>BR0</name>
  2985. <description>Port x reset bit y (y =
  2986. 0..15)</description>
  2987. <bitOffset>16</bitOffset>
  2988. <bitWidth>1</bitWidth>
  2989. </field>
  2990. <field>
  2991. <name>BS15</name>
  2992. <description>Port x set bit y (y=
  2993. 0..15)</description>
  2994. <bitOffset>15</bitOffset>
  2995. <bitWidth>1</bitWidth>
  2996. </field>
  2997. <field>
  2998. <name>BS14</name>
  2999. <description>Port x set bit y (y=
  3000. 0..15)</description>
  3001. <bitOffset>14</bitOffset>
  3002. <bitWidth>1</bitWidth>
  3003. </field>
  3004. <field>
  3005. <name>BS13</name>
  3006. <description>Port x set bit y (y=
  3007. 0..15)</description>
  3008. <bitOffset>13</bitOffset>
  3009. <bitWidth>1</bitWidth>
  3010. </field>
  3011. <field>
  3012. <name>BS12</name>
  3013. <description>Port x set bit y (y=
  3014. 0..15)</description>
  3015. <bitOffset>12</bitOffset>
  3016. <bitWidth>1</bitWidth>
  3017. </field>
  3018. <field>
  3019. <name>BS11</name>
  3020. <description>Port x set bit y (y=
  3021. 0..15)</description>
  3022. <bitOffset>11</bitOffset>
  3023. <bitWidth>1</bitWidth>
  3024. </field>
  3025. <field>
  3026. <name>BS10</name>
  3027. <description>Port x set bit y (y=
  3028. 0..15)</description>
  3029. <bitOffset>10</bitOffset>
  3030. <bitWidth>1</bitWidth>
  3031. </field>
  3032. <field>
  3033. <name>BS9</name>
  3034. <description>Port x set bit y (y=
  3035. 0..15)</description>
  3036. <bitOffset>9</bitOffset>
  3037. <bitWidth>1</bitWidth>
  3038. </field>
  3039. <field>
  3040. <name>BS8</name>
  3041. <description>Port x set bit y (y=
  3042. 0..15)</description>
  3043. <bitOffset>8</bitOffset>
  3044. <bitWidth>1</bitWidth>
  3045. </field>
  3046. <field>
  3047. <name>BS7</name>
  3048. <description>Port x set bit y (y=
  3049. 0..15)</description>
  3050. <bitOffset>7</bitOffset>
  3051. <bitWidth>1</bitWidth>
  3052. </field>
  3053. <field>
  3054. <name>BS6</name>
  3055. <description>Port x set bit y (y=
  3056. 0..15)</description>
  3057. <bitOffset>6</bitOffset>
  3058. <bitWidth>1</bitWidth>
  3059. </field>
  3060. <field>
  3061. <name>BS5</name>
  3062. <description>Port x set bit y (y=
  3063. 0..15)</description>
  3064. <bitOffset>5</bitOffset>
  3065. <bitWidth>1</bitWidth>
  3066. </field>
  3067. <field>
  3068. <name>BS4</name>
  3069. <description>Port x set bit y (y=
  3070. 0..15)</description>
  3071. <bitOffset>4</bitOffset>
  3072. <bitWidth>1</bitWidth>
  3073. </field>
  3074. <field>
  3075. <name>BS3</name>
  3076. <description>Port x set bit y (y=
  3077. 0..15)</description>
  3078. <bitOffset>3</bitOffset>
  3079. <bitWidth>1</bitWidth>
  3080. </field>
  3081. <field>
  3082. <name>BS2</name>
  3083. <description>Port x set bit y (y=
  3084. 0..15)</description>
  3085. <bitOffset>2</bitOffset>
  3086. <bitWidth>1</bitWidth>
  3087. </field>
  3088. <field>
  3089. <name>BS1</name>
  3090. <description>Port x set bit y (y=
  3091. 0..15)</description>
  3092. <bitOffset>1</bitOffset>
  3093. <bitWidth>1</bitWidth>
  3094. </field>
  3095. <field>
  3096. <name>BS0</name>
  3097. <description>Port x set bit y (y=
  3098. 0..15)</description>
  3099. <bitOffset>0</bitOffset>
  3100. <bitWidth>1</bitWidth>
  3101. </field>
  3102. </fields>
  3103. </register>
  3104. <register>
  3105. <name>LCKR</name>
  3106. <displayName>LCKR</displayName>
  3107. <description>GPIO port configuration lock
  3108. register</description>
  3109. <addressOffset>0x1C</addressOffset>
  3110. <size>0x20</size>
  3111. <access>read-write</access>
  3112. <resetValue>0x00000000</resetValue>
  3113. <fields>
  3114. <field>
  3115. <name>LCKK</name>
  3116. <description>Port x lock bit y (y=
  3117. 0..15)</description>
  3118. <bitOffset>16</bitOffset>
  3119. <bitWidth>1</bitWidth>
  3120. </field>
  3121. <field>
  3122. <name>LCK15</name>
  3123. <description>Port x lock bit y (y=
  3124. 0..15)</description>
  3125. <bitOffset>15</bitOffset>
  3126. <bitWidth>1</bitWidth>
  3127. </field>
  3128. <field>
  3129. <name>LCK14</name>
  3130. <description>Port x lock bit y (y=
  3131. 0..15)</description>
  3132. <bitOffset>14</bitOffset>
  3133. <bitWidth>1</bitWidth>
  3134. </field>
  3135. <field>
  3136. <name>LCK13</name>
  3137. <description>Port x lock bit y (y=
  3138. 0..15)</description>
  3139. <bitOffset>13</bitOffset>
  3140. <bitWidth>1</bitWidth>
  3141. </field>
  3142. <field>
  3143. <name>LCK12</name>
  3144. <description>Port x lock bit y (y=
  3145. 0..15)</description>
  3146. <bitOffset>12</bitOffset>
  3147. <bitWidth>1</bitWidth>
  3148. </field>
  3149. <field>
  3150. <name>LCK11</name>
  3151. <description>Port x lock bit y (y=
  3152. 0..15)</description>
  3153. <bitOffset>11</bitOffset>
  3154. <bitWidth>1</bitWidth>
  3155. </field>
  3156. <field>
  3157. <name>LCK10</name>
  3158. <description>Port x lock bit y (y=
  3159. 0..15)</description>
  3160. <bitOffset>10</bitOffset>
  3161. <bitWidth>1</bitWidth>
  3162. </field>
  3163. <field>
  3164. <name>LCK9</name>
  3165. <description>Port x lock bit y (y=
  3166. 0..15)</description>
  3167. <bitOffset>9</bitOffset>
  3168. <bitWidth>1</bitWidth>
  3169. </field>
  3170. <field>
  3171. <name>LCK8</name>
  3172. <description>Port x lock bit y (y=
  3173. 0..15)</description>
  3174. <bitOffset>8</bitOffset>
  3175. <bitWidth>1</bitWidth>
  3176. </field>
  3177. <field>
  3178. <name>LCK7</name>
  3179. <description>Port x lock bit y (y=
  3180. 0..15)</description>
  3181. <bitOffset>7</bitOffset>
  3182. <bitWidth>1</bitWidth>
  3183. </field>
  3184. <field>
  3185. <name>LCK6</name>
  3186. <description>Port x lock bit y (y=
  3187. 0..15)</description>
  3188. <bitOffset>6</bitOffset>
  3189. <bitWidth>1</bitWidth>
  3190. </field>
  3191. <field>
  3192. <name>LCK5</name>
  3193. <description>Port x lock bit y (y=
  3194. 0..15)</description>
  3195. <bitOffset>5</bitOffset>
  3196. <bitWidth>1</bitWidth>
  3197. </field>
  3198. <field>
  3199. <name>LCK4</name>
  3200. <description>Port x lock bit y (y=
  3201. 0..15)</description>
  3202. <bitOffset>4</bitOffset>
  3203. <bitWidth>1</bitWidth>
  3204. </field>
  3205. <field>
  3206. <name>LCK3</name>
  3207. <description>Port x lock bit y (y=
  3208. 0..15)</description>
  3209. <bitOffset>3</bitOffset>
  3210. <bitWidth>1</bitWidth>
  3211. </field>
  3212. <field>
  3213. <name>LCK2</name>
  3214. <description>Port x lock bit y (y=
  3215. 0..15)</description>
  3216. <bitOffset>2</bitOffset>
  3217. <bitWidth>1</bitWidth>
  3218. </field>
  3219. <field>
  3220. <name>LCK1</name>
  3221. <description>Port x lock bit y (y=
  3222. 0..15)</description>
  3223. <bitOffset>1</bitOffset>
  3224. <bitWidth>1</bitWidth>
  3225. </field>
  3226. <field>
  3227. <name>LCK0</name>
  3228. <description>Port x lock bit y (y=
  3229. 0..15)</description>
  3230. <bitOffset>0</bitOffset>
  3231. <bitWidth>1</bitWidth>
  3232. </field>
  3233. </fields>
  3234. </register>
  3235. <register>
  3236. <name>AFRL</name>
  3237. <displayName>AFRL</displayName>
  3238. <description>GPIO alternate function low
  3239. register</description>
  3240. <addressOffset>0x20</addressOffset>
  3241. <size>0x20</size>
  3242. <access>read-write</access>
  3243. <resetValue>0x00000000</resetValue>
  3244. <fields>
  3245. <field>
  3246. <name>AFSEL7</name>
  3247. <description>Alternate function selection for port x
  3248. pin y (y = 0..7)</description>
  3249. <bitOffset>28</bitOffset>
  3250. <bitWidth>4</bitWidth>
  3251. </field>
  3252. <field>
  3253. <name>AFSEL6</name>
  3254. <description>Alternate function selection for port x
  3255. pin y (y = 0..7)</description>
  3256. <bitOffset>24</bitOffset>
  3257. <bitWidth>4</bitWidth>
  3258. </field>
  3259. <field>
  3260. <name>AFSEL5</name>
  3261. <description>Alternate function selection for port x
  3262. pin y (y = 0..7)</description>
  3263. <bitOffset>20</bitOffset>
  3264. <bitWidth>4</bitWidth>
  3265. </field>
  3266. <field>
  3267. <name>AFSEL4</name>
  3268. <description>Alternate function selection for port x
  3269. pin y (y = 0..7)</description>
  3270. <bitOffset>16</bitOffset>
  3271. <bitWidth>4</bitWidth>
  3272. </field>
  3273. <field>
  3274. <name>AFSEL3</name>
  3275. <description>Alternate function selection for port x
  3276. pin y (y = 0..7)</description>
  3277. <bitOffset>12</bitOffset>
  3278. <bitWidth>4</bitWidth>
  3279. </field>
  3280. <field>
  3281. <name>AFSEL2</name>
  3282. <description>Alternate function selection for port x
  3283. pin y (y = 0..7)</description>
  3284. <bitOffset>8</bitOffset>
  3285. <bitWidth>4</bitWidth>
  3286. </field>
  3287. <field>
  3288. <name>AFSEL1</name>
  3289. <description>Alternate function selection for port x
  3290. pin y (y = 0..7)</description>
  3291. <bitOffset>4</bitOffset>
  3292. <bitWidth>4</bitWidth>
  3293. </field>
  3294. <field>
  3295. <name>AFSEL0</name>
  3296. <description>Alternate function selection for port x
  3297. pin y (y = 0..7)</description>
  3298. <bitOffset>0</bitOffset>
  3299. <bitWidth>4</bitWidth>
  3300. </field>
  3301. </fields>
  3302. </register>
  3303. <register>
  3304. <name>AFRH</name>
  3305. <displayName>AFRH</displayName>
  3306. <description>GPIO alternate function high
  3307. register</description>
  3308. <addressOffset>0x24</addressOffset>
  3309. <size>0x20</size>
  3310. <access>read-write</access>
  3311. <resetValue>0x00000000</resetValue>
  3312. <fields>
  3313. <field>
  3314. <name>AFSEL15</name>
  3315. <description>Alternate function selection for port x
  3316. pin y (y = 8..15)</description>
  3317. <bitOffset>28</bitOffset>
  3318. <bitWidth>4</bitWidth>
  3319. </field>
  3320. <field>
  3321. <name>AFSEL14</name>
  3322. <description>Alternate function selection for port x
  3323. pin y (y = 8..15)</description>
  3324. <bitOffset>24</bitOffset>
  3325. <bitWidth>4</bitWidth>
  3326. </field>
  3327. <field>
  3328. <name>AFSEL13</name>
  3329. <description>Alternate function selection for port x
  3330. pin y (y = 8..15)</description>
  3331. <bitOffset>20</bitOffset>
  3332. <bitWidth>4</bitWidth>
  3333. </field>
  3334. <field>
  3335. <name>AFSEL12</name>
  3336. <description>Alternate function selection for port x
  3337. pin y (y = 8..15)</description>
  3338. <bitOffset>16</bitOffset>
  3339. <bitWidth>4</bitWidth>
  3340. </field>
  3341. <field>
  3342. <name>AFSEL11</name>
  3343. <description>Alternate function selection for port x
  3344. pin y (y = 8..15)</description>
  3345. <bitOffset>12</bitOffset>
  3346. <bitWidth>4</bitWidth>
  3347. </field>
  3348. <field>
  3349. <name>AFSEL10</name>
  3350. <description>Alternate function selection for port x
  3351. pin y (y = 8..15)</description>
  3352. <bitOffset>8</bitOffset>
  3353. <bitWidth>4</bitWidth>
  3354. </field>
  3355. <field>
  3356. <name>AFSEL9</name>
  3357. <description>Alternate function selection for port x
  3358. pin y (y = 8..15)</description>
  3359. <bitOffset>4</bitOffset>
  3360. <bitWidth>4</bitWidth>
  3361. </field>
  3362. <field>
  3363. <name>AFSEL8</name>
  3364. <description>Alternate function selection for port x
  3365. pin y (y = 8..15)</description>
  3366. <bitOffset>0</bitOffset>
  3367. <bitWidth>4</bitWidth>
  3368. </field>
  3369. </fields>
  3370. </register>
  3371. <register>
  3372. <name>BRR</name>
  3373. <displayName>BRR</displayName>
  3374. <description>GPIO port bit reset register</description>
  3375. <addressOffset>0x28</addressOffset>
  3376. <size>0x20</size>
  3377. <access>write-only</access>
  3378. <resetValue>0x00000000</resetValue>
  3379. <fields>
  3380. <field>
  3381. <name>BR15</name>
  3382. <description>Port x Reset bit y (y= 0 ..
  3383. 15)</description>
  3384. <bitOffset>15</bitOffset>
  3385. <bitWidth>1</bitWidth>
  3386. </field>
  3387. <field>
  3388. <name>BR14</name>
  3389. <description>Port x Reset bit y (y= 0 ..
  3390. 15)</description>
  3391. <bitOffset>14</bitOffset>
  3392. <bitWidth>1</bitWidth>
  3393. </field>
  3394. <field>
  3395. <name>BR13</name>
  3396. <description>Port x Reset bit y (y= 0 ..
  3397. 15)</description>
  3398. <bitOffset>13</bitOffset>
  3399. <bitWidth>1</bitWidth>
  3400. </field>
  3401. <field>
  3402. <name>BR12</name>
  3403. <description>Port x Reset bit y (y= 0 ..
  3404. 15)</description>
  3405. <bitOffset>12</bitOffset>
  3406. <bitWidth>1</bitWidth>
  3407. </field>
  3408. <field>
  3409. <name>BR11</name>
  3410. <description>Port x Reset bit y (y= 0 ..
  3411. 15)</description>
  3412. <bitOffset>11</bitOffset>
  3413. <bitWidth>1</bitWidth>
  3414. </field>
  3415. <field>
  3416. <name>BR10</name>
  3417. <description>Port x Reset bit y (y= 0 ..
  3418. 15)</description>
  3419. <bitOffset>10</bitOffset>
  3420. <bitWidth>1</bitWidth>
  3421. </field>
  3422. <field>
  3423. <name>BR9</name>
  3424. <description>Port x Reset bit y (y= 0 ..
  3425. 15)</description>
  3426. <bitOffset>9</bitOffset>
  3427. <bitWidth>1</bitWidth>
  3428. </field>
  3429. <field>
  3430. <name>BR8</name>
  3431. <description>Port x Reset bit y (y= 0 ..
  3432. 15)</description>
  3433. <bitOffset>8</bitOffset>
  3434. <bitWidth>1</bitWidth>
  3435. </field>
  3436. <field>
  3437. <name>BR7</name>
  3438. <description>Port x Reset bit y (y= 0 ..
  3439. 15)</description>
  3440. <bitOffset>7</bitOffset>
  3441. <bitWidth>1</bitWidth>
  3442. </field>
  3443. <field>
  3444. <name>BR6</name>
  3445. <description>Port x Reset bit y (y= 0 ..
  3446. 15)</description>
  3447. <bitOffset>6</bitOffset>
  3448. <bitWidth>1</bitWidth>
  3449. </field>
  3450. <field>
  3451. <name>BR5</name>
  3452. <description>Port x Reset bit y (y= 0 ..
  3453. 15)</description>
  3454. <bitOffset>5</bitOffset>
  3455. <bitWidth>1</bitWidth>
  3456. </field>
  3457. <field>
  3458. <name>BR4</name>
  3459. <description>Port x Reset bit y (y= 0 ..
  3460. 15)</description>
  3461. <bitOffset>4</bitOffset>
  3462. <bitWidth>1</bitWidth>
  3463. </field>
  3464. <field>
  3465. <name>BR3</name>
  3466. <description>Port x Reset bit y (y= 0 ..
  3467. 15)</description>
  3468. <bitOffset>3</bitOffset>
  3469. <bitWidth>1</bitWidth>
  3470. </field>
  3471. <field>
  3472. <name>BR2</name>
  3473. <description>Port x Reset bit y (y= 0 ..
  3474. 15)</description>
  3475. <bitOffset>2</bitOffset>
  3476. <bitWidth>1</bitWidth>
  3477. </field>
  3478. <field>
  3479. <name>BR1</name>
  3480. <description>Port x Reset bit y (y= 0 ..
  3481. 15)</description>
  3482. <bitOffset>1</bitOffset>
  3483. <bitWidth>1</bitWidth>
  3484. </field>
  3485. <field>
  3486. <name>BR0</name>
  3487. <description>Port x Reset bit y (y= 0 ..
  3488. 15)</description>
  3489. <bitOffset>0</bitOffset>
  3490. <bitWidth>1</bitWidth>
  3491. </field>
  3492. </fields>
  3493. </register>
  3494. </registers>
  3495. </peripheral>
  3496. <peripheral>
  3497. <name>GPIOB</name>
  3498. <description>General-purpose I/Os</description>
  3499. <groupName>GPIO</groupName>
  3500. <baseAddress>0x50000400</baseAddress>
  3501. <addressBlock>
  3502. <offset>0x0</offset>
  3503. <size>0x400</size>
  3504. <usage>registers</usage>
  3505. </addressBlock>
  3506. <registers>
  3507. <register>
  3508. <name>MODER</name>
  3509. <displayName>MODER</displayName>
  3510. <description>GPIO port mode register</description>
  3511. <addressOffset>0x0</addressOffset>
  3512. <size>0x20</size>
  3513. <access>read-write</access>
  3514. <resetValue>0xFFFFFFFF</resetValue>
  3515. <fields>
  3516. <field>
  3517. <name>MODE15</name>
  3518. <description>Port x configuration bits (y =
  3519. 0..15)</description>
  3520. <bitOffset>30</bitOffset>
  3521. <bitWidth>2</bitWidth>
  3522. </field>
  3523. <field>
  3524. <name>MODE14</name>
  3525. <description>Port x configuration bits (y =
  3526. 0..15)</description>
  3527. <bitOffset>28</bitOffset>
  3528. <bitWidth>2</bitWidth>
  3529. </field>
  3530. <field>
  3531. <name>MODE13</name>
  3532. <description>Port x configuration bits (y =
  3533. 0..15)</description>
  3534. <bitOffset>26</bitOffset>
  3535. <bitWidth>2</bitWidth>
  3536. </field>
  3537. <field>
  3538. <name>MODE12</name>
  3539. <description>Port x configuration bits (y =
  3540. 0..15)</description>
  3541. <bitOffset>24</bitOffset>
  3542. <bitWidth>2</bitWidth>
  3543. </field>
  3544. <field>
  3545. <name>MODE11</name>
  3546. <description>Port x configuration bits (y =
  3547. 0..15)</description>
  3548. <bitOffset>22</bitOffset>
  3549. <bitWidth>2</bitWidth>
  3550. </field>
  3551. <field>
  3552. <name>MODE10</name>
  3553. <description>Port x configuration bits (y =
  3554. 0..15)</description>
  3555. <bitOffset>20</bitOffset>
  3556. <bitWidth>2</bitWidth>
  3557. </field>
  3558. <field>
  3559. <name>MODE9</name>
  3560. <description>Port x configuration bits (y =
  3561. 0..15)</description>
  3562. <bitOffset>18</bitOffset>
  3563. <bitWidth>2</bitWidth>
  3564. </field>
  3565. <field>
  3566. <name>MODE8</name>
  3567. <description>Port x configuration bits (y =
  3568. 0..15)</description>
  3569. <bitOffset>16</bitOffset>
  3570. <bitWidth>2</bitWidth>
  3571. </field>
  3572. <field>
  3573. <name>MODE7</name>
  3574. <description>Port x configuration bits (y =
  3575. 0..15)</description>
  3576. <bitOffset>14</bitOffset>
  3577. <bitWidth>2</bitWidth>
  3578. </field>
  3579. <field>
  3580. <name>MODE6</name>
  3581. <description>Port x configuration bits (y =
  3582. 0..15)</description>
  3583. <bitOffset>12</bitOffset>
  3584. <bitWidth>2</bitWidth>
  3585. </field>
  3586. <field>
  3587. <name>MODE5</name>
  3588. <description>Port x configuration bits (y =
  3589. 0..15)</description>
  3590. <bitOffset>10</bitOffset>
  3591. <bitWidth>2</bitWidth>
  3592. </field>
  3593. <field>
  3594. <name>MODE4</name>
  3595. <description>Port x configuration bits (y =
  3596. 0..15)</description>
  3597. <bitOffset>8</bitOffset>
  3598. <bitWidth>2</bitWidth>
  3599. </field>
  3600. <field>
  3601. <name>MODE3</name>
  3602. <description>Port x configuration bits (y =
  3603. 0..15)</description>
  3604. <bitOffset>6</bitOffset>
  3605. <bitWidth>2</bitWidth>
  3606. </field>
  3607. <field>
  3608. <name>MODE2</name>
  3609. <description>Port x configuration bits (y =
  3610. 0..15)</description>
  3611. <bitOffset>4</bitOffset>
  3612. <bitWidth>2</bitWidth>
  3613. </field>
  3614. <field>
  3615. <name>MODE1</name>
  3616. <description>Port x configuration bits (y =
  3617. 0..15)</description>
  3618. <bitOffset>2</bitOffset>
  3619. <bitWidth>2</bitWidth>
  3620. </field>
  3621. <field>
  3622. <name>MODE0</name>
  3623. <description>Port x configuration bits (y =
  3624. 0..15)</description>
  3625. <bitOffset>0</bitOffset>
  3626. <bitWidth>2</bitWidth>
  3627. </field>
  3628. </fields>
  3629. </register>
  3630. <register>
  3631. <name>OTYPER</name>
  3632. <displayName>OTYPER</displayName>
  3633. <description>GPIO port output type register</description>
  3634. <addressOffset>0x4</addressOffset>
  3635. <size>0x20</size>
  3636. <access>read-write</access>
  3637. <resetValue>0x00000000</resetValue>
  3638. <fields>
  3639. <field>
  3640. <name>OT15</name>
  3641. <description>Port x configuration bits (y =
  3642. 0..15)</description>
  3643. <bitOffset>15</bitOffset>
  3644. <bitWidth>1</bitWidth>
  3645. </field>
  3646. <field>
  3647. <name>OT14</name>
  3648. <description>Port x configuration bits (y =
  3649. 0..15)</description>
  3650. <bitOffset>14</bitOffset>
  3651. <bitWidth>1</bitWidth>
  3652. </field>
  3653. <field>
  3654. <name>OT13</name>
  3655. <description>Port x configuration bits (y =
  3656. 0..15)</description>
  3657. <bitOffset>13</bitOffset>
  3658. <bitWidth>1</bitWidth>
  3659. </field>
  3660. <field>
  3661. <name>OT12</name>
  3662. <description>Port x configuration bits (y =
  3663. 0..15)</description>
  3664. <bitOffset>12</bitOffset>
  3665. <bitWidth>1</bitWidth>
  3666. </field>
  3667. <field>
  3668. <name>OT11</name>
  3669. <description>Port x configuration bits (y =
  3670. 0..15)</description>
  3671. <bitOffset>11</bitOffset>
  3672. <bitWidth>1</bitWidth>
  3673. </field>
  3674. <field>
  3675. <name>OT10</name>
  3676. <description>Port x configuration bits (y =
  3677. 0..15)</description>
  3678. <bitOffset>10</bitOffset>
  3679. <bitWidth>1</bitWidth>
  3680. </field>
  3681. <field>
  3682. <name>OT9</name>
  3683. <description>Port x configuration bits (y =
  3684. 0..15)</description>
  3685. <bitOffset>9</bitOffset>
  3686. <bitWidth>1</bitWidth>
  3687. </field>
  3688. <field>
  3689. <name>OT8</name>
  3690. <description>Port x configuration bits (y =
  3691. 0..15)</description>
  3692. <bitOffset>8</bitOffset>
  3693. <bitWidth>1</bitWidth>
  3694. </field>
  3695. <field>
  3696. <name>OT7</name>
  3697. <description>Port x configuration bits (y =
  3698. 0..15)</description>
  3699. <bitOffset>7</bitOffset>
  3700. <bitWidth>1</bitWidth>
  3701. </field>
  3702. <field>
  3703. <name>OT6</name>
  3704. <description>Port x configuration bits (y =
  3705. 0..15)</description>
  3706. <bitOffset>6</bitOffset>
  3707. <bitWidth>1</bitWidth>
  3708. </field>
  3709. <field>
  3710. <name>OT5</name>
  3711. <description>Port x configuration bits (y =
  3712. 0..15)</description>
  3713. <bitOffset>5</bitOffset>
  3714. <bitWidth>1</bitWidth>
  3715. </field>
  3716. <field>
  3717. <name>OT4</name>
  3718. <description>Port x configuration bits (y =
  3719. 0..15)</description>
  3720. <bitOffset>4</bitOffset>
  3721. <bitWidth>1</bitWidth>
  3722. </field>
  3723. <field>
  3724. <name>OT3</name>
  3725. <description>Port x configuration bits (y =
  3726. 0..15)</description>
  3727. <bitOffset>3</bitOffset>
  3728. <bitWidth>1</bitWidth>
  3729. </field>
  3730. <field>
  3731. <name>OT2</name>
  3732. <description>Port x configuration bits (y =
  3733. 0..15)</description>
  3734. <bitOffset>2</bitOffset>
  3735. <bitWidth>1</bitWidth>
  3736. </field>
  3737. <field>
  3738. <name>OT1</name>
  3739. <description>Port x configuration bits (y =
  3740. 0..15)</description>
  3741. <bitOffset>1</bitOffset>
  3742. <bitWidth>1</bitWidth>
  3743. </field>
  3744. <field>
  3745. <name>OT0</name>
  3746. <description>Port x configuration bits (y =
  3747. 0..15)</description>
  3748. <bitOffset>0</bitOffset>
  3749. <bitWidth>1</bitWidth>
  3750. </field>
  3751. </fields>
  3752. </register>
  3753. <register>
  3754. <name>OSPEEDR</name>
  3755. <displayName>OSPEEDR</displayName>
  3756. <description>GPIO port output speed
  3757. register</description>
  3758. <addressOffset>0x8</addressOffset>
  3759. <size>0x20</size>
  3760. <access>read-write</access>
  3761. <resetValue>0x00000000</resetValue>
  3762. <fields>
  3763. <field>
  3764. <name>OSPEED15</name>
  3765. <description>Port x configuration bits (y =
  3766. 0..15)</description>
  3767. <bitOffset>30</bitOffset>
  3768. <bitWidth>2</bitWidth>
  3769. </field>
  3770. <field>
  3771. <name>OSPEED14</name>
  3772. <description>Port x configuration bits (y =
  3773. 0..15)</description>
  3774. <bitOffset>28</bitOffset>
  3775. <bitWidth>2</bitWidth>
  3776. </field>
  3777. <field>
  3778. <name>OSPEED13</name>
  3779. <description>Port x configuration bits (y =
  3780. 0..15)</description>
  3781. <bitOffset>26</bitOffset>
  3782. <bitWidth>2</bitWidth>
  3783. </field>
  3784. <field>
  3785. <name>OSPEED12</name>
  3786. <description>Port x configuration bits (y =
  3787. 0..15)</description>
  3788. <bitOffset>24</bitOffset>
  3789. <bitWidth>2</bitWidth>
  3790. </field>
  3791. <field>
  3792. <name>OSPEED11</name>
  3793. <description>Port x configuration bits (y =
  3794. 0..15)</description>
  3795. <bitOffset>22</bitOffset>
  3796. <bitWidth>2</bitWidth>
  3797. </field>
  3798. <field>
  3799. <name>OSPEED10</name>
  3800. <description>Port x configuration bits (y =
  3801. 0..15)</description>
  3802. <bitOffset>20</bitOffset>
  3803. <bitWidth>2</bitWidth>
  3804. </field>
  3805. <field>
  3806. <name>OSPEED9</name>
  3807. <description>Port x configuration bits (y =
  3808. 0..15)</description>
  3809. <bitOffset>18</bitOffset>
  3810. <bitWidth>2</bitWidth>
  3811. </field>
  3812. <field>
  3813. <name>OSPEED8</name>
  3814. <description>Port x configuration bits (y =
  3815. 0..15)</description>
  3816. <bitOffset>16</bitOffset>
  3817. <bitWidth>2</bitWidth>
  3818. </field>
  3819. <field>
  3820. <name>OSPEED7</name>
  3821. <description>Port x configuration bits (y =
  3822. 0..15)</description>
  3823. <bitOffset>14</bitOffset>
  3824. <bitWidth>2</bitWidth>
  3825. </field>
  3826. <field>
  3827. <name>OSPEED6</name>
  3828. <description>Port x configuration bits (y =
  3829. 0..15)</description>
  3830. <bitOffset>12</bitOffset>
  3831. <bitWidth>2</bitWidth>
  3832. </field>
  3833. <field>
  3834. <name>OSPEED5</name>
  3835. <description>Port x configuration bits (y =
  3836. 0..15)</description>
  3837. <bitOffset>10</bitOffset>
  3838. <bitWidth>2</bitWidth>
  3839. </field>
  3840. <field>
  3841. <name>OSPEED4</name>
  3842. <description>Port x configuration bits (y =
  3843. 0..15)</description>
  3844. <bitOffset>8</bitOffset>
  3845. <bitWidth>2</bitWidth>
  3846. </field>
  3847. <field>
  3848. <name>OSPEED3</name>
  3849. <description>Port x configuration bits (y =
  3850. 0..15)</description>
  3851. <bitOffset>6</bitOffset>
  3852. <bitWidth>2</bitWidth>
  3853. </field>
  3854. <field>
  3855. <name>OSPEED2</name>
  3856. <description>Port x configuration bits (y =
  3857. 0..15)</description>
  3858. <bitOffset>4</bitOffset>
  3859. <bitWidth>2</bitWidth>
  3860. </field>
  3861. <field>
  3862. <name>OSPEED1</name>
  3863. <description>Port x configuration bits (y =
  3864. 0..15)</description>
  3865. <bitOffset>2</bitOffset>
  3866. <bitWidth>2</bitWidth>
  3867. </field>
  3868. <field>
  3869. <name>OSPEED0</name>
  3870. <description>Port x configuration bits (y =
  3871. 0..15)</description>
  3872. <bitOffset>0</bitOffset>
  3873. <bitWidth>2</bitWidth>
  3874. </field>
  3875. </fields>
  3876. </register>
  3877. <register>
  3878. <name>PUPDR</name>
  3879. <displayName>PUPDR</displayName>
  3880. <description>GPIO port pull-up/pull-down
  3881. register</description>
  3882. <addressOffset>0xC</addressOffset>
  3883. <size>0x20</size>
  3884. <access>read-write</access>
  3885. <resetValue>0x00000000</resetValue>
  3886. <fields>
  3887. <field>
  3888. <name>PUPD15</name>
  3889. <description>Port x configuration bits (y =
  3890. 0..15)</description>
  3891. <bitOffset>30</bitOffset>
  3892. <bitWidth>2</bitWidth>
  3893. </field>
  3894. <field>
  3895. <name>PUPD14</name>
  3896. <description>Port x configuration bits (y =
  3897. 0..15)</description>
  3898. <bitOffset>28</bitOffset>
  3899. <bitWidth>2</bitWidth>
  3900. </field>
  3901. <field>
  3902. <name>PUPD13</name>
  3903. <description>Port x configuration bits (y =
  3904. 0..15)</description>
  3905. <bitOffset>26</bitOffset>
  3906. <bitWidth>2</bitWidth>
  3907. </field>
  3908. <field>
  3909. <name>PUPD12</name>
  3910. <description>Port x configuration bits (y =
  3911. 0..15)</description>
  3912. <bitOffset>24</bitOffset>
  3913. <bitWidth>2</bitWidth>
  3914. </field>
  3915. <field>
  3916. <name>PUPD11</name>
  3917. <description>Port x configuration bits (y =
  3918. 0..15)</description>
  3919. <bitOffset>22</bitOffset>
  3920. <bitWidth>2</bitWidth>
  3921. </field>
  3922. <field>
  3923. <name>PUPD10</name>
  3924. <description>Port x configuration bits (y =
  3925. 0..15)</description>
  3926. <bitOffset>20</bitOffset>
  3927. <bitWidth>2</bitWidth>
  3928. </field>
  3929. <field>
  3930. <name>PUPD9</name>
  3931. <description>Port x configuration bits (y =
  3932. 0..15)</description>
  3933. <bitOffset>18</bitOffset>
  3934. <bitWidth>2</bitWidth>
  3935. </field>
  3936. <field>
  3937. <name>PUPD8</name>
  3938. <description>Port x configuration bits (y =
  3939. 0..15)</description>
  3940. <bitOffset>16</bitOffset>
  3941. <bitWidth>2</bitWidth>
  3942. </field>
  3943. <field>
  3944. <name>PUPD7</name>
  3945. <description>Port x configuration bits (y =
  3946. 0..15)</description>
  3947. <bitOffset>14</bitOffset>
  3948. <bitWidth>2</bitWidth>
  3949. </field>
  3950. <field>
  3951. <name>PUPD6</name>
  3952. <description>Port x configuration bits (y =
  3953. 0..15)</description>
  3954. <bitOffset>12</bitOffset>
  3955. <bitWidth>2</bitWidth>
  3956. </field>
  3957. <field>
  3958. <name>PUPD5</name>
  3959. <description>Port x configuration bits (y =
  3960. 0..15)</description>
  3961. <bitOffset>10</bitOffset>
  3962. <bitWidth>2</bitWidth>
  3963. </field>
  3964. <field>
  3965. <name>PUPD4</name>
  3966. <description>Port x configuration bits (y =
  3967. 0..15)</description>
  3968. <bitOffset>8</bitOffset>
  3969. <bitWidth>2</bitWidth>
  3970. </field>
  3971. <field>
  3972. <name>PUPD3</name>
  3973. <description>Port x configuration bits (y =
  3974. 0..15)</description>
  3975. <bitOffset>6</bitOffset>
  3976. <bitWidth>2</bitWidth>
  3977. </field>
  3978. <field>
  3979. <name>PUPD2</name>
  3980. <description>Port x configuration bits (y =
  3981. 0..15)</description>
  3982. <bitOffset>4</bitOffset>
  3983. <bitWidth>2</bitWidth>
  3984. </field>
  3985. <field>
  3986. <name>PUPD1</name>
  3987. <description>Port x configuration bits (y =
  3988. 0..15)</description>
  3989. <bitOffset>2</bitOffset>
  3990. <bitWidth>2</bitWidth>
  3991. </field>
  3992. <field>
  3993. <name>PUPD0</name>
  3994. <description>Port x configuration bits (y =
  3995. 0..15)</description>
  3996. <bitOffset>0</bitOffset>
  3997. <bitWidth>2</bitWidth>
  3998. </field>
  3999. </fields>
  4000. </register>
  4001. <register>
  4002. <name>IDR</name>
  4003. <displayName>IDR</displayName>
  4004. <description>GPIO port input data register</description>
  4005. <addressOffset>0x10</addressOffset>
  4006. <size>0x20</size>
  4007. <access>read-only</access>
  4008. <resetValue>0x00000000</resetValue>
  4009. <fields>
  4010. <field>
  4011. <name>ID15</name>
  4012. <description>Port input data bit (y =
  4013. 0..15)</description>
  4014. <bitOffset>15</bitOffset>
  4015. <bitWidth>1</bitWidth>
  4016. </field>
  4017. <field>
  4018. <name>ID14</name>
  4019. <description>Port input data bit (y =
  4020. 0..15)</description>
  4021. <bitOffset>14</bitOffset>
  4022. <bitWidth>1</bitWidth>
  4023. </field>
  4024. <field>
  4025. <name>ID13</name>
  4026. <description>Port input data bit (y =
  4027. 0..15)</description>
  4028. <bitOffset>13</bitOffset>
  4029. <bitWidth>1</bitWidth>
  4030. </field>
  4031. <field>
  4032. <name>ID12</name>
  4033. <description>Port input data bit (y =
  4034. 0..15)</description>
  4035. <bitOffset>12</bitOffset>
  4036. <bitWidth>1</bitWidth>
  4037. </field>
  4038. <field>
  4039. <name>ID11</name>
  4040. <description>Port input data bit (y =
  4041. 0..15)</description>
  4042. <bitOffset>11</bitOffset>
  4043. <bitWidth>1</bitWidth>
  4044. </field>
  4045. <field>
  4046. <name>ID10</name>
  4047. <description>Port input data bit (y =
  4048. 0..15)</description>
  4049. <bitOffset>10</bitOffset>
  4050. <bitWidth>1</bitWidth>
  4051. </field>
  4052. <field>
  4053. <name>ID9</name>
  4054. <description>Port input data bit (y =
  4055. 0..15)</description>
  4056. <bitOffset>9</bitOffset>
  4057. <bitWidth>1</bitWidth>
  4058. </field>
  4059. <field>
  4060. <name>ID8</name>
  4061. <description>Port input data bit (y =
  4062. 0..15)</description>
  4063. <bitOffset>8</bitOffset>
  4064. <bitWidth>1</bitWidth>
  4065. </field>
  4066. <field>
  4067. <name>ID7</name>
  4068. <description>Port input data bit (y =
  4069. 0..15)</description>
  4070. <bitOffset>7</bitOffset>
  4071. <bitWidth>1</bitWidth>
  4072. </field>
  4073. <field>
  4074. <name>ID6</name>
  4075. <description>Port input data bit (y =
  4076. 0..15)</description>
  4077. <bitOffset>6</bitOffset>
  4078. <bitWidth>1</bitWidth>
  4079. </field>
  4080. <field>
  4081. <name>ID5</name>
  4082. <description>Port input data bit (y =
  4083. 0..15)</description>
  4084. <bitOffset>5</bitOffset>
  4085. <bitWidth>1</bitWidth>
  4086. </field>
  4087. <field>
  4088. <name>ID4</name>
  4089. <description>Port input data bit (y =
  4090. 0..15)</description>
  4091. <bitOffset>4</bitOffset>
  4092. <bitWidth>1</bitWidth>
  4093. </field>
  4094. <field>
  4095. <name>ID3</name>
  4096. <description>Port input data bit (y =
  4097. 0..15)</description>
  4098. <bitOffset>3</bitOffset>
  4099. <bitWidth>1</bitWidth>
  4100. </field>
  4101. <field>
  4102. <name>ID2</name>
  4103. <description>Port input data bit (y =
  4104. 0..15)</description>
  4105. <bitOffset>2</bitOffset>
  4106. <bitWidth>1</bitWidth>
  4107. </field>
  4108. <field>
  4109. <name>ID1</name>
  4110. <description>Port input data bit (y =
  4111. 0..15)</description>
  4112. <bitOffset>1</bitOffset>
  4113. <bitWidth>1</bitWidth>
  4114. </field>
  4115. <field>
  4116. <name>ID0</name>
  4117. <description>Port input data bit (y =
  4118. 0..15)</description>
  4119. <bitOffset>0</bitOffset>
  4120. <bitWidth>1</bitWidth>
  4121. </field>
  4122. </fields>
  4123. </register>
  4124. <register>
  4125. <name>ODR</name>
  4126. <displayName>ODR</displayName>
  4127. <description>GPIO port output data register</description>
  4128. <addressOffset>0x14</addressOffset>
  4129. <size>0x20</size>
  4130. <access>read-write</access>
  4131. <resetValue>0x00000000</resetValue>
  4132. <fields>
  4133. <field>
  4134. <name>OD15</name>
  4135. <description>Port output data bit (y =
  4136. 0..15)</description>
  4137. <bitOffset>15</bitOffset>
  4138. <bitWidth>1</bitWidth>
  4139. </field>
  4140. <field>
  4141. <name>OD14</name>
  4142. <description>Port output data bit (y =
  4143. 0..15)</description>
  4144. <bitOffset>14</bitOffset>
  4145. <bitWidth>1</bitWidth>
  4146. </field>
  4147. <field>
  4148. <name>OD13</name>
  4149. <description>Port output data bit (y =
  4150. 0..15)</description>
  4151. <bitOffset>13</bitOffset>
  4152. <bitWidth>1</bitWidth>
  4153. </field>
  4154. <field>
  4155. <name>OD12</name>
  4156. <description>Port output data bit (y =
  4157. 0..15)</description>
  4158. <bitOffset>12</bitOffset>
  4159. <bitWidth>1</bitWidth>
  4160. </field>
  4161. <field>
  4162. <name>OD11</name>
  4163. <description>Port output data bit (y =
  4164. 0..15)</description>
  4165. <bitOffset>11</bitOffset>
  4166. <bitWidth>1</bitWidth>
  4167. </field>
  4168. <field>
  4169. <name>OD10</name>
  4170. <description>Port output data bit (y =
  4171. 0..15)</description>
  4172. <bitOffset>10</bitOffset>
  4173. <bitWidth>1</bitWidth>
  4174. </field>
  4175. <field>
  4176. <name>OD9</name>
  4177. <description>Port output data bit (y =
  4178. 0..15)</description>
  4179. <bitOffset>9</bitOffset>
  4180. <bitWidth>1</bitWidth>
  4181. </field>
  4182. <field>
  4183. <name>OD8</name>
  4184. <description>Port output data bit (y =
  4185. 0..15)</description>
  4186. <bitOffset>8</bitOffset>
  4187. <bitWidth>1</bitWidth>
  4188. </field>
  4189. <field>
  4190. <name>OD7</name>
  4191. <description>Port output data bit (y =
  4192. 0..15)</description>
  4193. <bitOffset>7</bitOffset>
  4194. <bitWidth>1</bitWidth>
  4195. </field>
  4196. <field>
  4197. <name>OD6</name>
  4198. <description>Port output data bit (y =
  4199. 0..15)</description>
  4200. <bitOffset>6</bitOffset>
  4201. <bitWidth>1</bitWidth>
  4202. </field>
  4203. <field>
  4204. <name>OD5</name>
  4205. <description>Port output data bit (y =
  4206. 0..15)</description>
  4207. <bitOffset>5</bitOffset>
  4208. <bitWidth>1</bitWidth>
  4209. </field>
  4210. <field>
  4211. <name>OD4</name>
  4212. <description>Port output data bit (y =
  4213. 0..15)</description>
  4214. <bitOffset>4</bitOffset>
  4215. <bitWidth>1</bitWidth>
  4216. </field>
  4217. <field>
  4218. <name>OD3</name>
  4219. <description>Port output data bit (y =
  4220. 0..15)</description>
  4221. <bitOffset>3</bitOffset>
  4222. <bitWidth>1</bitWidth>
  4223. </field>
  4224. <field>
  4225. <name>OD2</name>
  4226. <description>Port output data bit (y =
  4227. 0..15)</description>
  4228. <bitOffset>2</bitOffset>
  4229. <bitWidth>1</bitWidth>
  4230. </field>
  4231. <field>
  4232. <name>OD1</name>
  4233. <description>Port output data bit (y =
  4234. 0..15)</description>
  4235. <bitOffset>1</bitOffset>
  4236. <bitWidth>1</bitWidth>
  4237. </field>
  4238. <field>
  4239. <name>OD0</name>
  4240. <description>Port output data bit (y =
  4241. 0..15)</description>
  4242. <bitOffset>0</bitOffset>
  4243. <bitWidth>1</bitWidth>
  4244. </field>
  4245. </fields>
  4246. </register>
  4247. <register>
  4248. <name>BSRR</name>
  4249. <displayName>BSRR</displayName>
  4250. <description>GPIO port bit set/reset
  4251. register</description>
  4252. <addressOffset>0x18</addressOffset>
  4253. <size>0x20</size>
  4254. <access>write-only</access>
  4255. <resetValue>0x00000000</resetValue>
  4256. <fields>
  4257. <field>
  4258. <name>BR15</name>
  4259. <description>Port x reset bit y (y =
  4260. 0..15)</description>
  4261. <bitOffset>31</bitOffset>
  4262. <bitWidth>1</bitWidth>
  4263. </field>
  4264. <field>
  4265. <name>BR14</name>
  4266. <description>Port x reset bit y (y =
  4267. 0..15)</description>
  4268. <bitOffset>30</bitOffset>
  4269. <bitWidth>1</bitWidth>
  4270. </field>
  4271. <field>
  4272. <name>BR13</name>
  4273. <description>Port x reset bit y (y =
  4274. 0..15)</description>
  4275. <bitOffset>29</bitOffset>
  4276. <bitWidth>1</bitWidth>
  4277. </field>
  4278. <field>
  4279. <name>BR12</name>
  4280. <description>Port x reset bit y (y =
  4281. 0..15)</description>
  4282. <bitOffset>28</bitOffset>
  4283. <bitWidth>1</bitWidth>
  4284. </field>
  4285. <field>
  4286. <name>BR11</name>
  4287. <description>Port x reset bit y (y =
  4288. 0..15)</description>
  4289. <bitOffset>27</bitOffset>
  4290. <bitWidth>1</bitWidth>
  4291. </field>
  4292. <field>
  4293. <name>BR10</name>
  4294. <description>Port x reset bit y (y =
  4295. 0..15)</description>
  4296. <bitOffset>26</bitOffset>
  4297. <bitWidth>1</bitWidth>
  4298. </field>
  4299. <field>
  4300. <name>BR9</name>
  4301. <description>Port x reset bit y (y =
  4302. 0..15)</description>
  4303. <bitOffset>25</bitOffset>
  4304. <bitWidth>1</bitWidth>
  4305. </field>
  4306. <field>
  4307. <name>BR8</name>
  4308. <description>Port x reset bit y (y =
  4309. 0..15)</description>
  4310. <bitOffset>24</bitOffset>
  4311. <bitWidth>1</bitWidth>
  4312. </field>
  4313. <field>
  4314. <name>BR7</name>
  4315. <description>Port x reset bit y (y =
  4316. 0..15)</description>
  4317. <bitOffset>23</bitOffset>
  4318. <bitWidth>1</bitWidth>
  4319. </field>
  4320. <field>
  4321. <name>BR6</name>
  4322. <description>Port x reset bit y (y =
  4323. 0..15)</description>
  4324. <bitOffset>22</bitOffset>
  4325. <bitWidth>1</bitWidth>
  4326. </field>
  4327. <field>
  4328. <name>BR5</name>
  4329. <description>Port x reset bit y (y =
  4330. 0..15)</description>
  4331. <bitOffset>21</bitOffset>
  4332. <bitWidth>1</bitWidth>
  4333. </field>
  4334. <field>
  4335. <name>BR4</name>
  4336. <description>Port x reset bit y (y =
  4337. 0..15)</description>
  4338. <bitOffset>20</bitOffset>
  4339. <bitWidth>1</bitWidth>
  4340. </field>
  4341. <field>
  4342. <name>BR3</name>
  4343. <description>Port x reset bit y (y =
  4344. 0..15)</description>
  4345. <bitOffset>19</bitOffset>
  4346. <bitWidth>1</bitWidth>
  4347. </field>
  4348. <field>
  4349. <name>BR2</name>
  4350. <description>Port x reset bit y (y =
  4351. 0..15)</description>
  4352. <bitOffset>18</bitOffset>
  4353. <bitWidth>1</bitWidth>
  4354. </field>
  4355. <field>
  4356. <name>BR1</name>
  4357. <description>Port x reset bit y (y =
  4358. 0..15)</description>
  4359. <bitOffset>17</bitOffset>
  4360. <bitWidth>1</bitWidth>
  4361. </field>
  4362. <field>
  4363. <name>BR0</name>
  4364. <description>Port x reset bit y (y =
  4365. 0..15)</description>
  4366. <bitOffset>16</bitOffset>
  4367. <bitWidth>1</bitWidth>
  4368. </field>
  4369. <field>
  4370. <name>BS15</name>
  4371. <description>Port x set bit y (y=
  4372. 0..15)</description>
  4373. <bitOffset>15</bitOffset>
  4374. <bitWidth>1</bitWidth>
  4375. </field>
  4376. <field>
  4377. <name>BS14</name>
  4378. <description>Port x set bit y (y=
  4379. 0..15)</description>
  4380. <bitOffset>14</bitOffset>
  4381. <bitWidth>1</bitWidth>
  4382. </field>
  4383. <field>
  4384. <name>BS13</name>
  4385. <description>Port x set bit y (y=
  4386. 0..15)</description>
  4387. <bitOffset>13</bitOffset>
  4388. <bitWidth>1</bitWidth>
  4389. </field>
  4390. <field>
  4391. <name>BS12</name>
  4392. <description>Port x set bit y (y=
  4393. 0..15)</description>
  4394. <bitOffset>12</bitOffset>
  4395. <bitWidth>1</bitWidth>
  4396. </field>
  4397. <field>
  4398. <name>BS11</name>
  4399. <description>Port x set bit y (y=
  4400. 0..15)</description>
  4401. <bitOffset>11</bitOffset>
  4402. <bitWidth>1</bitWidth>
  4403. </field>
  4404. <field>
  4405. <name>BS10</name>
  4406. <description>Port x set bit y (y=
  4407. 0..15)</description>
  4408. <bitOffset>10</bitOffset>
  4409. <bitWidth>1</bitWidth>
  4410. </field>
  4411. <field>
  4412. <name>BS9</name>
  4413. <description>Port x set bit y (y=
  4414. 0..15)</description>
  4415. <bitOffset>9</bitOffset>
  4416. <bitWidth>1</bitWidth>
  4417. </field>
  4418. <field>
  4419. <name>BS8</name>
  4420. <description>Port x set bit y (y=
  4421. 0..15)</description>
  4422. <bitOffset>8</bitOffset>
  4423. <bitWidth>1</bitWidth>
  4424. </field>
  4425. <field>
  4426. <name>BS7</name>
  4427. <description>Port x set bit y (y=
  4428. 0..15)</description>
  4429. <bitOffset>7</bitOffset>
  4430. <bitWidth>1</bitWidth>
  4431. </field>
  4432. <field>
  4433. <name>BS6</name>
  4434. <description>Port x set bit y (y=
  4435. 0..15)</description>
  4436. <bitOffset>6</bitOffset>
  4437. <bitWidth>1</bitWidth>
  4438. </field>
  4439. <field>
  4440. <name>BS5</name>
  4441. <description>Port x set bit y (y=
  4442. 0..15)</description>
  4443. <bitOffset>5</bitOffset>
  4444. <bitWidth>1</bitWidth>
  4445. </field>
  4446. <field>
  4447. <name>BS4</name>
  4448. <description>Port x set bit y (y=
  4449. 0..15)</description>
  4450. <bitOffset>4</bitOffset>
  4451. <bitWidth>1</bitWidth>
  4452. </field>
  4453. <field>
  4454. <name>BS3</name>
  4455. <description>Port x set bit y (y=
  4456. 0..15)</description>
  4457. <bitOffset>3</bitOffset>
  4458. <bitWidth>1</bitWidth>
  4459. </field>
  4460. <field>
  4461. <name>BS2</name>
  4462. <description>Port x set bit y (y=
  4463. 0..15)</description>
  4464. <bitOffset>2</bitOffset>
  4465. <bitWidth>1</bitWidth>
  4466. </field>
  4467. <field>
  4468. <name>BS1</name>
  4469. <description>Port x set bit y (y=
  4470. 0..15)</description>
  4471. <bitOffset>1</bitOffset>
  4472. <bitWidth>1</bitWidth>
  4473. </field>
  4474. <field>
  4475. <name>BS0</name>
  4476. <description>Port x set bit y (y=
  4477. 0..15)</description>
  4478. <bitOffset>0</bitOffset>
  4479. <bitWidth>1</bitWidth>
  4480. </field>
  4481. </fields>
  4482. </register>
  4483. <register>
  4484. <name>LCKR</name>
  4485. <displayName>LCKR</displayName>
  4486. <description>GPIO port configuration lock
  4487. register</description>
  4488. <addressOffset>0x1C</addressOffset>
  4489. <size>0x20</size>
  4490. <access>read-write</access>
  4491. <resetValue>0x00000000</resetValue>
  4492. <fields>
  4493. <field>
  4494. <name>LCKK</name>
  4495. <description>Port x lock bit y (y=
  4496. 0..15)</description>
  4497. <bitOffset>16</bitOffset>
  4498. <bitWidth>1</bitWidth>
  4499. </field>
  4500. <field>
  4501. <name>LCK15</name>
  4502. <description>Port x lock bit y (y=
  4503. 0..15)</description>
  4504. <bitOffset>15</bitOffset>
  4505. <bitWidth>1</bitWidth>
  4506. </field>
  4507. <field>
  4508. <name>LCK14</name>
  4509. <description>Port x lock bit y (y=
  4510. 0..15)</description>
  4511. <bitOffset>14</bitOffset>
  4512. <bitWidth>1</bitWidth>
  4513. </field>
  4514. <field>
  4515. <name>LCK13</name>
  4516. <description>Port x lock bit y (y=
  4517. 0..15)</description>
  4518. <bitOffset>13</bitOffset>
  4519. <bitWidth>1</bitWidth>
  4520. </field>
  4521. <field>
  4522. <name>LCK12</name>
  4523. <description>Port x lock bit y (y=
  4524. 0..15)</description>
  4525. <bitOffset>12</bitOffset>
  4526. <bitWidth>1</bitWidth>
  4527. </field>
  4528. <field>
  4529. <name>LCK11</name>
  4530. <description>Port x lock bit y (y=
  4531. 0..15)</description>
  4532. <bitOffset>11</bitOffset>
  4533. <bitWidth>1</bitWidth>
  4534. </field>
  4535. <field>
  4536. <name>LCK10</name>
  4537. <description>Port x lock bit y (y=
  4538. 0..15)</description>
  4539. <bitOffset>10</bitOffset>
  4540. <bitWidth>1</bitWidth>
  4541. </field>
  4542. <field>
  4543. <name>LCK9</name>
  4544. <description>Port x lock bit y (y=
  4545. 0..15)</description>
  4546. <bitOffset>9</bitOffset>
  4547. <bitWidth>1</bitWidth>
  4548. </field>
  4549. <field>
  4550. <name>LCK8</name>
  4551. <description>Port x lock bit y (y=
  4552. 0..15)</description>
  4553. <bitOffset>8</bitOffset>
  4554. <bitWidth>1</bitWidth>
  4555. </field>
  4556. <field>
  4557. <name>LCK7</name>
  4558. <description>Port x lock bit y (y=
  4559. 0..15)</description>
  4560. <bitOffset>7</bitOffset>
  4561. <bitWidth>1</bitWidth>
  4562. </field>
  4563. <field>
  4564. <name>LCK6</name>
  4565. <description>Port x lock bit y (y=
  4566. 0..15)</description>
  4567. <bitOffset>6</bitOffset>
  4568. <bitWidth>1</bitWidth>
  4569. </field>
  4570. <field>
  4571. <name>LCK5</name>
  4572. <description>Port x lock bit y (y=
  4573. 0..15)</description>
  4574. <bitOffset>5</bitOffset>
  4575. <bitWidth>1</bitWidth>
  4576. </field>
  4577. <field>
  4578. <name>LCK4</name>
  4579. <description>Port x lock bit y (y=
  4580. 0..15)</description>
  4581. <bitOffset>4</bitOffset>
  4582. <bitWidth>1</bitWidth>
  4583. </field>
  4584. <field>
  4585. <name>LCK3</name>
  4586. <description>Port x lock bit y (y=
  4587. 0..15)</description>
  4588. <bitOffset>3</bitOffset>
  4589. <bitWidth>1</bitWidth>
  4590. </field>
  4591. <field>
  4592. <name>LCK2</name>
  4593. <description>Port x lock bit y (y=
  4594. 0..15)</description>
  4595. <bitOffset>2</bitOffset>
  4596. <bitWidth>1</bitWidth>
  4597. </field>
  4598. <field>
  4599. <name>LCK1</name>
  4600. <description>Port x lock bit y (y=
  4601. 0..15)</description>
  4602. <bitOffset>1</bitOffset>
  4603. <bitWidth>1</bitWidth>
  4604. </field>
  4605. <field>
  4606. <name>LCK0</name>
  4607. <description>Port x lock bit y (y=
  4608. 0..15)</description>
  4609. <bitOffset>0</bitOffset>
  4610. <bitWidth>1</bitWidth>
  4611. </field>
  4612. </fields>
  4613. </register>
  4614. <register>
  4615. <name>AFRL</name>
  4616. <displayName>AFRL</displayName>
  4617. <description>GPIO alternate function low
  4618. register</description>
  4619. <addressOffset>0x20</addressOffset>
  4620. <size>0x20</size>
  4621. <access>read-write</access>
  4622. <resetValue>0x00000000</resetValue>
  4623. <fields>
  4624. <field>
  4625. <name>AFSEL7</name>
  4626. <description>Alternate function selection for port x
  4627. pin y (y = 0..7)</description>
  4628. <bitOffset>28</bitOffset>
  4629. <bitWidth>4</bitWidth>
  4630. </field>
  4631. <field>
  4632. <name>AFSEL6</name>
  4633. <description>Alternate function selection for port x
  4634. pin y (y = 0..7)</description>
  4635. <bitOffset>24</bitOffset>
  4636. <bitWidth>4</bitWidth>
  4637. </field>
  4638. <field>
  4639. <name>AFSEL5</name>
  4640. <description>Alternate function selection for port x
  4641. pin y (y = 0..7)</description>
  4642. <bitOffset>20</bitOffset>
  4643. <bitWidth>4</bitWidth>
  4644. </field>
  4645. <field>
  4646. <name>AFSEL4</name>
  4647. <description>Alternate function selection for port x
  4648. pin y (y = 0..7)</description>
  4649. <bitOffset>16</bitOffset>
  4650. <bitWidth>4</bitWidth>
  4651. </field>
  4652. <field>
  4653. <name>AFSEL3</name>
  4654. <description>Alternate function selection for port x
  4655. pin y (y = 0..7)</description>
  4656. <bitOffset>12</bitOffset>
  4657. <bitWidth>4</bitWidth>
  4658. </field>
  4659. <field>
  4660. <name>AFSEL2</name>
  4661. <description>Alternate function selection for port x
  4662. pin y (y = 0..7)</description>
  4663. <bitOffset>8</bitOffset>
  4664. <bitWidth>4</bitWidth>
  4665. </field>
  4666. <field>
  4667. <name>AFSEL1</name>
  4668. <description>Alternate function selection for port x
  4669. pin y (y = 0..7)</description>
  4670. <bitOffset>4</bitOffset>
  4671. <bitWidth>4</bitWidth>
  4672. </field>
  4673. <field>
  4674. <name>AFSEL0</name>
  4675. <description>Alternate function selection for port x
  4676. pin y (y = 0..7)</description>
  4677. <bitOffset>0</bitOffset>
  4678. <bitWidth>4</bitWidth>
  4679. </field>
  4680. </fields>
  4681. </register>
  4682. <register>
  4683. <name>AFRH</name>
  4684. <displayName>AFRH</displayName>
  4685. <description>GPIO alternate function high
  4686. register</description>
  4687. <addressOffset>0x24</addressOffset>
  4688. <size>0x20</size>
  4689. <access>read-write</access>
  4690. <resetValue>0x00000000</resetValue>
  4691. <fields>
  4692. <field>
  4693. <name>AFSEL15</name>
  4694. <description>Alternate function selection for port x
  4695. pin y (y = 8..15)</description>
  4696. <bitOffset>28</bitOffset>
  4697. <bitWidth>4</bitWidth>
  4698. </field>
  4699. <field>
  4700. <name>AFSEL14</name>
  4701. <description>Alternate function selection for port x
  4702. pin y (y = 8..15)</description>
  4703. <bitOffset>24</bitOffset>
  4704. <bitWidth>4</bitWidth>
  4705. </field>
  4706. <field>
  4707. <name>AFSEL13</name>
  4708. <description>Alternate function selection for port x
  4709. pin y (y = 8..15)</description>
  4710. <bitOffset>20</bitOffset>
  4711. <bitWidth>4</bitWidth>
  4712. </field>
  4713. <field>
  4714. <name>AFSEL12</name>
  4715. <description>Alternate function selection for port x
  4716. pin y (y = 8..15)</description>
  4717. <bitOffset>16</bitOffset>
  4718. <bitWidth>4</bitWidth>
  4719. </field>
  4720. <field>
  4721. <name>AFSEL11</name>
  4722. <description>Alternate function selection for port x
  4723. pin y (y = 8..15)</description>
  4724. <bitOffset>12</bitOffset>
  4725. <bitWidth>4</bitWidth>
  4726. </field>
  4727. <field>
  4728. <name>AFSEL10</name>
  4729. <description>Alternate function selection for port x
  4730. pin y (y = 8..15)</description>
  4731. <bitOffset>8</bitOffset>
  4732. <bitWidth>4</bitWidth>
  4733. </field>
  4734. <field>
  4735. <name>AFSEL9</name>
  4736. <description>Alternate function selection for port x
  4737. pin y (y = 8..15)</description>
  4738. <bitOffset>4</bitOffset>
  4739. <bitWidth>4</bitWidth>
  4740. </field>
  4741. <field>
  4742. <name>AFSEL8</name>
  4743. <description>Alternate function selection for port x
  4744. pin y (y = 8..15)</description>
  4745. <bitOffset>0</bitOffset>
  4746. <bitWidth>4</bitWidth>
  4747. </field>
  4748. </fields>
  4749. </register>
  4750. <register>
  4751. <name>BRR</name>
  4752. <displayName>BRR</displayName>
  4753. <description>GPIO port bit reset register</description>
  4754. <addressOffset>0x28</addressOffset>
  4755. <size>0x20</size>
  4756. <access>write-only</access>
  4757. <resetValue>0x00000000</resetValue>
  4758. <fields>
  4759. <field>
  4760. <name>BR15</name>
  4761. <description>Port x Reset bit y (y= 0 ..
  4762. 15)</description>
  4763. <bitOffset>15</bitOffset>
  4764. <bitWidth>1</bitWidth>
  4765. </field>
  4766. <field>
  4767. <name>BR14</name>
  4768. <description>Port x Reset bit y (y= 0 ..
  4769. 15)</description>
  4770. <bitOffset>14</bitOffset>
  4771. <bitWidth>1</bitWidth>
  4772. </field>
  4773. <field>
  4774. <name>BR13</name>
  4775. <description>Port x Reset bit y (y= 0 ..
  4776. 15)</description>
  4777. <bitOffset>13</bitOffset>
  4778. <bitWidth>1</bitWidth>
  4779. </field>
  4780. <field>
  4781. <name>BR12</name>
  4782. <description>Port x Reset bit y (y= 0 ..
  4783. 15)</description>
  4784. <bitOffset>12</bitOffset>
  4785. <bitWidth>1</bitWidth>
  4786. </field>
  4787. <field>
  4788. <name>BR11</name>
  4789. <description>Port x Reset bit y (y= 0 ..
  4790. 15)</description>
  4791. <bitOffset>11</bitOffset>
  4792. <bitWidth>1</bitWidth>
  4793. </field>
  4794. <field>
  4795. <name>BR10</name>
  4796. <description>Port x Reset bit y (y= 0 ..
  4797. 15)</description>
  4798. <bitOffset>10</bitOffset>
  4799. <bitWidth>1</bitWidth>
  4800. </field>
  4801. <field>
  4802. <name>BR9</name>
  4803. <description>Port x Reset bit y (y= 0 ..
  4804. 15)</description>
  4805. <bitOffset>9</bitOffset>
  4806. <bitWidth>1</bitWidth>
  4807. </field>
  4808. <field>
  4809. <name>BR8</name>
  4810. <description>Port x Reset bit y (y= 0 ..
  4811. 15)</description>
  4812. <bitOffset>8</bitOffset>
  4813. <bitWidth>1</bitWidth>
  4814. </field>
  4815. <field>
  4816. <name>BR7</name>
  4817. <description>Port x Reset bit y (y= 0 ..
  4818. 15)</description>
  4819. <bitOffset>7</bitOffset>
  4820. <bitWidth>1</bitWidth>
  4821. </field>
  4822. <field>
  4823. <name>BR6</name>
  4824. <description>Port x Reset bit y (y= 0 ..
  4825. 15)</description>
  4826. <bitOffset>6</bitOffset>
  4827. <bitWidth>1</bitWidth>
  4828. </field>
  4829. <field>
  4830. <name>BR5</name>
  4831. <description>Port x Reset bit y (y= 0 ..
  4832. 15)</description>
  4833. <bitOffset>5</bitOffset>
  4834. <bitWidth>1</bitWidth>
  4835. </field>
  4836. <field>
  4837. <name>BR4</name>
  4838. <description>Port x Reset bit y (y= 0 ..
  4839. 15)</description>
  4840. <bitOffset>4</bitOffset>
  4841. <bitWidth>1</bitWidth>
  4842. </field>
  4843. <field>
  4844. <name>BR3</name>
  4845. <description>Port x Reset bit y (y= 0 ..
  4846. 15)</description>
  4847. <bitOffset>3</bitOffset>
  4848. <bitWidth>1</bitWidth>
  4849. </field>
  4850. <field>
  4851. <name>BR2</name>
  4852. <description>Port x Reset bit y (y= 0 ..
  4853. 15)</description>
  4854. <bitOffset>2</bitOffset>
  4855. <bitWidth>1</bitWidth>
  4856. </field>
  4857. <field>
  4858. <name>BR1</name>
  4859. <description>Port x Reset bit y (y= 0 ..
  4860. 15)</description>
  4861. <bitOffset>1</bitOffset>
  4862. <bitWidth>1</bitWidth>
  4863. </field>
  4864. <field>
  4865. <name>BR0</name>
  4866. <description>Port x Reset bit y (y= 0 ..
  4867. 15)</description>
  4868. <bitOffset>0</bitOffset>
  4869. <bitWidth>1</bitWidth>
  4870. </field>
  4871. </fields>
  4872. </register>
  4873. </registers>
  4874. </peripheral>
  4875. <peripheral derivedFrom="GPIOB">
  4876. <name>GPIOC</name>
  4877. <baseAddress>0x50000800</baseAddress>
  4878. </peripheral>
  4879. <peripheral derivedFrom="GPIOB">
  4880. <name>GPIOD</name>
  4881. <baseAddress>0x50000C00</baseAddress>
  4882. </peripheral>
  4883. <peripheral derivedFrom="GPIOB">
  4884. <name>GPIOH</name>
  4885. <baseAddress>0x50001C00</baseAddress>
  4886. </peripheral>
  4887. <peripheral>
  4888. <name>LCD</name>
  4889. <description>Liquid crystal display controller</description>
  4890. <groupName>LCD</groupName>
  4891. <baseAddress>0x40002400</baseAddress>
  4892. <addressBlock>
  4893. <offset>0x0</offset>
  4894. <size>0x400</size>
  4895. <usage>registers</usage>
  4896. </addressBlock>
  4897. <interrupt>
  4898. <name>LCD</name>
  4899. <description>LCD global interrupt</description>
  4900. <value>30</value>
  4901. </interrupt>
  4902. <registers>
  4903. <register>
  4904. <name>CR</name>
  4905. <displayName>CR</displayName>
  4906. <description>control register</description>
  4907. <addressOffset>0x0</addressOffset>
  4908. <size>0x20</size>
  4909. <access>read-write</access>
  4910. <resetValue>0x00000000</resetValue>
  4911. <fields>
  4912. <field>
  4913. <name>BIAS</name>
  4914. <description>Bias selector</description>
  4915. <bitOffset>5</bitOffset>
  4916. <bitWidth>2</bitWidth>
  4917. </field>
  4918. <field>
  4919. <name>DUTY</name>
  4920. <description>Duty selection</description>
  4921. <bitOffset>2</bitOffset>
  4922. <bitWidth>3</bitWidth>
  4923. </field>
  4924. <field>
  4925. <name>VSEL</name>
  4926. <description>Voltage source selection</description>
  4927. <bitOffset>1</bitOffset>
  4928. <bitWidth>1</bitWidth>
  4929. </field>
  4930. <field>
  4931. <name>LCDEN</name>
  4932. <description>LCD controller enable</description>
  4933. <bitOffset>0</bitOffset>
  4934. <bitWidth>1</bitWidth>
  4935. </field>
  4936. </fields>
  4937. </register>
  4938. <register>
  4939. <name>FCR</name>
  4940. <displayName>FCR</displayName>
  4941. <description>frame control register</description>
  4942. <addressOffset>0x4</addressOffset>
  4943. <size>0x20</size>
  4944. <access>read-write</access>
  4945. <resetValue>0x00000000</resetValue>
  4946. <fields>
  4947. <field>
  4948. <name>PS</name>
  4949. <description>PS 16-bit prescaler</description>
  4950. <bitOffset>22</bitOffset>
  4951. <bitWidth>4</bitWidth>
  4952. </field>
  4953. <field>
  4954. <name>DIV</name>
  4955. <description>DIV clock divider</description>
  4956. <bitOffset>18</bitOffset>
  4957. <bitWidth>4</bitWidth>
  4958. </field>
  4959. <field>
  4960. <name>BLINK</name>
  4961. <description>Blink mode selection</description>
  4962. <bitOffset>16</bitOffset>
  4963. <bitWidth>2</bitWidth>
  4964. </field>
  4965. <field>
  4966. <name>BLINKF</name>
  4967. <description>Blink frequency selection</description>
  4968. <bitOffset>13</bitOffset>
  4969. <bitWidth>3</bitWidth>
  4970. </field>
  4971. <field>
  4972. <name>CC</name>
  4973. <description>Contrast control</description>
  4974. <bitOffset>10</bitOffset>
  4975. <bitWidth>3</bitWidth>
  4976. </field>
  4977. <field>
  4978. <name>DEAD</name>
  4979. <description>Dead time duration</description>
  4980. <bitOffset>7</bitOffset>
  4981. <bitWidth>3</bitWidth>
  4982. </field>
  4983. <field>
  4984. <name>PON</name>
  4985. <description>Pulse ON duration</description>
  4986. <bitOffset>4</bitOffset>
  4987. <bitWidth>3</bitWidth>
  4988. </field>
  4989. <field>
  4990. <name>UDDIE</name>
  4991. <description>Update display done interrupt
  4992. enable</description>
  4993. <bitOffset>3</bitOffset>
  4994. <bitWidth>1</bitWidth>
  4995. </field>
  4996. <field>
  4997. <name>SOFIE</name>
  4998. <description>Start of frame interrupt
  4999. enable</description>
  5000. <bitOffset>1</bitOffset>
  5001. <bitWidth>1</bitWidth>
  5002. </field>
  5003. <field>
  5004. <name>HD</name>
  5005. <description>High drive enable</description>
  5006. <bitOffset>0</bitOffset>
  5007. <bitWidth>1</bitWidth>
  5008. </field>
  5009. </fields>
  5010. </register>
  5011. <register>
  5012. <name>SR</name>
  5013. <displayName>SR</displayName>
  5014. <description>status register</description>
  5015. <addressOffset>0x8</addressOffset>
  5016. <size>0x20</size>
  5017. <resetValue>0x00000020</resetValue>
  5018. <fields>
  5019. <field>
  5020. <name>FCRSF</name>
  5021. <description>LCD Frame Control Register
  5022. Synchronization flag</description>
  5023. <bitOffset>5</bitOffset>
  5024. <bitWidth>1</bitWidth>
  5025. <access>read-only</access>
  5026. </field>
  5027. <field>
  5028. <name>RDY</name>
  5029. <description>Ready flag</description>
  5030. <bitOffset>4</bitOffset>
  5031. <bitWidth>1</bitWidth>
  5032. <access>read-only</access>
  5033. </field>
  5034. <field>
  5035. <name>UDD</name>
  5036. <description>Update Display Done</description>
  5037. <bitOffset>3</bitOffset>
  5038. <bitWidth>1</bitWidth>
  5039. <access>read-only</access>
  5040. </field>
  5041. <field>
  5042. <name>UDR</name>
  5043. <description>Update display request</description>
  5044. <bitOffset>2</bitOffset>
  5045. <bitWidth>1</bitWidth>
  5046. <access>write-only</access>
  5047. </field>
  5048. <field>
  5049. <name>SOF</name>
  5050. <description>Start of frame flag</description>
  5051. <bitOffset>1</bitOffset>
  5052. <bitWidth>1</bitWidth>
  5053. <access>read-only</access>
  5054. </field>
  5055. <field>
  5056. <name>ENS</name>
  5057. <description>ENS</description>
  5058. <bitOffset>0</bitOffset>
  5059. <bitWidth>1</bitWidth>
  5060. <access>read-only</access>
  5061. </field>
  5062. </fields>
  5063. </register>
  5064. <register>
  5065. <name>CLR</name>
  5066. <displayName>CLR</displayName>
  5067. <description>clear register</description>
  5068. <addressOffset>0xC</addressOffset>
  5069. <size>0x20</size>
  5070. <access>write-only</access>
  5071. <resetValue>0x00000000</resetValue>
  5072. <fields>
  5073. <field>
  5074. <name>UDDC</name>
  5075. <description>Update display done clear</description>
  5076. <bitOffset>3</bitOffset>
  5077. <bitWidth>1</bitWidth>
  5078. </field>
  5079. <field>
  5080. <name>SOFC</name>
  5081. <description>Start of frame flag clear</description>
  5082. <bitOffset>1</bitOffset>
  5083. <bitWidth>1</bitWidth>
  5084. </field>
  5085. </fields>
  5086. </register>
  5087. <register>
  5088. <name>RAM_COM0</name>
  5089. <displayName>RAM_COM0</displayName>
  5090. <description>display memory</description>
  5091. <addressOffset>0x14</addressOffset>
  5092. <size>0x20</size>
  5093. <access>read-write</access>
  5094. <resetValue>0x00000000</resetValue>
  5095. <fields>
  5096. <field>
  5097. <name>S30</name>
  5098. <description>S30</description>
  5099. <bitOffset>30</bitOffset>
  5100. <bitWidth>1</bitWidth>
  5101. </field>
  5102. <field>
  5103. <name>S29</name>
  5104. <description>S29</description>
  5105. <bitOffset>29</bitOffset>
  5106. <bitWidth>1</bitWidth>
  5107. </field>
  5108. <field>
  5109. <name>S28</name>
  5110. <description>S28</description>
  5111. <bitOffset>28</bitOffset>
  5112. <bitWidth>1</bitWidth>
  5113. </field>
  5114. <field>
  5115. <name>S27</name>
  5116. <description>S27</description>
  5117. <bitOffset>27</bitOffset>
  5118. <bitWidth>1</bitWidth>
  5119. </field>
  5120. <field>
  5121. <name>S26</name>
  5122. <description>S26</description>
  5123. <bitOffset>26</bitOffset>
  5124. <bitWidth>1</bitWidth>
  5125. </field>
  5126. <field>
  5127. <name>S25</name>
  5128. <description>S25</description>
  5129. <bitOffset>25</bitOffset>
  5130. <bitWidth>1</bitWidth>
  5131. </field>
  5132. <field>
  5133. <name>S24</name>
  5134. <description>S24</description>
  5135. <bitOffset>24</bitOffset>
  5136. <bitWidth>1</bitWidth>
  5137. </field>
  5138. <field>
  5139. <name>S23</name>
  5140. <description>S23</description>
  5141. <bitOffset>23</bitOffset>
  5142. <bitWidth>1</bitWidth>
  5143. </field>
  5144. <field>
  5145. <name>S22</name>
  5146. <description>S22</description>
  5147. <bitOffset>22</bitOffset>
  5148. <bitWidth>1</bitWidth>
  5149. </field>
  5150. <field>
  5151. <name>S21</name>
  5152. <description>S21</description>
  5153. <bitOffset>21</bitOffset>
  5154. <bitWidth>1</bitWidth>
  5155. </field>
  5156. <field>
  5157. <name>S20</name>
  5158. <description>S20</description>
  5159. <bitOffset>20</bitOffset>
  5160. <bitWidth>1</bitWidth>
  5161. </field>
  5162. <field>
  5163. <name>S19</name>
  5164. <description>S19</description>
  5165. <bitOffset>19</bitOffset>
  5166. <bitWidth>1</bitWidth>
  5167. </field>
  5168. <field>
  5169. <name>S18</name>
  5170. <description>S18</description>
  5171. <bitOffset>18</bitOffset>
  5172. <bitWidth>1</bitWidth>
  5173. </field>
  5174. <field>
  5175. <name>S17</name>
  5176. <description>S17</description>
  5177. <bitOffset>17</bitOffset>
  5178. <bitWidth>1</bitWidth>
  5179. </field>
  5180. <field>
  5181. <name>S16</name>
  5182. <description>S16</description>
  5183. <bitOffset>16</bitOffset>
  5184. <bitWidth>1</bitWidth>
  5185. </field>
  5186. <field>
  5187. <name>S15</name>
  5188. <description>S15</description>
  5189. <bitOffset>15</bitOffset>
  5190. <bitWidth>1</bitWidth>
  5191. </field>
  5192. <field>
  5193. <name>S14</name>
  5194. <description>S14</description>
  5195. <bitOffset>14</bitOffset>
  5196. <bitWidth>1</bitWidth>
  5197. </field>
  5198. <field>
  5199. <name>S13</name>
  5200. <description>S13</description>
  5201. <bitOffset>13</bitOffset>
  5202. <bitWidth>1</bitWidth>
  5203. </field>
  5204. <field>
  5205. <name>S12</name>
  5206. <description>S12</description>
  5207. <bitOffset>12</bitOffset>
  5208. <bitWidth>1</bitWidth>
  5209. </field>
  5210. <field>
  5211. <name>S11</name>
  5212. <description>S11</description>
  5213. <bitOffset>11</bitOffset>
  5214. <bitWidth>1</bitWidth>
  5215. </field>
  5216. <field>
  5217. <name>S10</name>
  5218. <description>S10</description>
  5219. <bitOffset>10</bitOffset>
  5220. <bitWidth>1</bitWidth>
  5221. </field>
  5222. <field>
  5223. <name>S09</name>
  5224. <description>S09</description>
  5225. <bitOffset>9</bitOffset>
  5226. <bitWidth>1</bitWidth>
  5227. </field>
  5228. <field>
  5229. <name>S08</name>
  5230. <description>S08</description>
  5231. <bitOffset>8</bitOffset>
  5232. <bitWidth>1</bitWidth>
  5233. </field>
  5234. <field>
  5235. <name>S07</name>
  5236. <description>S07</description>
  5237. <bitOffset>7</bitOffset>
  5238. <bitWidth>1</bitWidth>
  5239. </field>
  5240. <field>
  5241. <name>S06</name>
  5242. <description>S06</description>
  5243. <bitOffset>6</bitOffset>
  5244. <bitWidth>1</bitWidth>
  5245. </field>
  5246. <field>
  5247. <name>S05</name>
  5248. <description>S05</description>
  5249. <bitOffset>5</bitOffset>
  5250. <bitWidth>1</bitWidth>
  5251. </field>
  5252. <field>
  5253. <name>S04</name>
  5254. <description>S04</description>
  5255. <bitOffset>4</bitOffset>
  5256. <bitWidth>1</bitWidth>
  5257. </field>
  5258. <field>
  5259. <name>S03</name>
  5260. <description>S03</description>
  5261. <bitOffset>3</bitOffset>
  5262. <bitWidth>1</bitWidth>
  5263. </field>
  5264. <field>
  5265. <name>S02</name>
  5266. <description>S02</description>
  5267. <bitOffset>2</bitOffset>
  5268. <bitWidth>1</bitWidth>
  5269. </field>
  5270. <field>
  5271. <name>S01</name>
  5272. <description>S01</description>
  5273. <bitOffset>1</bitOffset>
  5274. <bitWidth>1</bitWidth>
  5275. </field>
  5276. <field>
  5277. <name>S00</name>
  5278. <description>S00</description>
  5279. <bitOffset>0</bitOffset>
  5280. <bitWidth>1</bitWidth>
  5281. </field>
  5282. </fields>
  5283. </register>
  5284. <register>
  5285. <name>RAM_COM1</name>
  5286. <displayName>RAM_COM1</displayName>
  5287. <description>display memory</description>
  5288. <addressOffset>0x1C</addressOffset>
  5289. <size>0x20</size>
  5290. <access>read-write</access>
  5291. <resetValue>0x00000000</resetValue>
  5292. <fields>
  5293. <field>
  5294. <name>S31</name>
  5295. <description>S31</description>
  5296. <bitOffset>31</bitOffset>
  5297. <bitWidth>1</bitWidth>
  5298. </field>
  5299. <field>
  5300. <name>S30</name>
  5301. <description>S30</description>
  5302. <bitOffset>30</bitOffset>
  5303. <bitWidth>1</bitWidth>
  5304. </field>
  5305. <field>
  5306. <name>S29</name>
  5307. <description>S29</description>
  5308. <bitOffset>29</bitOffset>
  5309. <bitWidth>1</bitWidth>
  5310. </field>
  5311. <field>
  5312. <name>S28</name>
  5313. <description>S28</description>
  5314. <bitOffset>28</bitOffset>
  5315. <bitWidth>1</bitWidth>
  5316. </field>
  5317. <field>
  5318. <name>S27</name>
  5319. <description>S27</description>
  5320. <bitOffset>27</bitOffset>
  5321. <bitWidth>1</bitWidth>
  5322. </field>
  5323. <field>
  5324. <name>S26</name>
  5325. <description>S26</description>
  5326. <bitOffset>26</bitOffset>
  5327. <bitWidth>1</bitWidth>
  5328. </field>
  5329. <field>
  5330. <name>S25</name>
  5331. <description>S25</description>
  5332. <bitOffset>25</bitOffset>
  5333. <bitWidth>1</bitWidth>
  5334. </field>
  5335. <field>
  5336. <name>S24</name>
  5337. <description>S24</description>
  5338. <bitOffset>24</bitOffset>
  5339. <bitWidth>1</bitWidth>
  5340. </field>
  5341. <field>
  5342. <name>S23</name>
  5343. <description>S23</description>
  5344. <bitOffset>23</bitOffset>
  5345. <bitWidth>1</bitWidth>
  5346. </field>
  5347. <field>
  5348. <name>S22</name>
  5349. <description>S22</description>
  5350. <bitOffset>22</bitOffset>
  5351. <bitWidth>1</bitWidth>
  5352. </field>
  5353. <field>
  5354. <name>S21</name>
  5355. <description>S21</description>
  5356. <bitOffset>21</bitOffset>
  5357. <bitWidth>1</bitWidth>
  5358. </field>
  5359. <field>
  5360. <name>S20</name>
  5361. <description>S20</description>
  5362. <bitOffset>20</bitOffset>
  5363. <bitWidth>1</bitWidth>
  5364. </field>
  5365. <field>
  5366. <name>S19</name>
  5367. <description>S19</description>
  5368. <bitOffset>19</bitOffset>
  5369. <bitWidth>1</bitWidth>
  5370. </field>
  5371. <field>
  5372. <name>S18</name>
  5373. <description>S18</description>
  5374. <bitOffset>18</bitOffset>
  5375. <bitWidth>1</bitWidth>
  5376. </field>
  5377. <field>
  5378. <name>S17</name>
  5379. <description>S17</description>
  5380. <bitOffset>17</bitOffset>
  5381. <bitWidth>1</bitWidth>
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  5422. <bitOffset>10</bitOffset>
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  5488. <name>RAM_COM2</name>
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  5517. <bitOffset>28</bitOffset>
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  5523. <bitOffset>27</bitOffset>
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  5528. <description>S26</description>
  5529. <bitOffset>26</bitOffset>
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  5535. <bitOffset>25</bitOffset>
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  5541. <bitOffset>24</bitOffset>
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  5547. <bitOffset>23</bitOffset>
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  5553. <bitOffset>22</bitOffset>
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  5559. <bitOffset>21</bitOffset>
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  5565. <bitOffset>20</bitOffset>
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  5571. <bitOffset>19</bitOffset>
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  5577. <bitOffset>18</bitOffset>
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  5583. <bitOffset>17</bitOffset>
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  5595. <bitOffset>15</bitOffset>
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  5601. <bitOffset>14</bitOffset>
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  5613. <bitOffset>12</bitOffset>
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  5624. <description>S10</description>
  5625. <bitOffset>10</bitOffset>
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  5631. <bitOffset>9</bitOffset>
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  5636. <description>S08</description>
  5637. <bitOffset>8</bitOffset>
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  5643. <bitOffset>7</bitOffset>
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  5691. <name>RAM_COM3</name>
  5692. <displayName>RAM_COM3</displayName>
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  5695. <size>0x20</size>
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  5720. <bitOffset>28</bitOffset>
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  5726. <bitOffset>27</bitOffset>
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  5731. <description>S26</description>
  5732. <bitOffset>26</bitOffset>
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  5738. <bitOffset>25</bitOffset>
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  5740. </field>
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  5744. <bitOffset>24</bitOffset>
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  5750. <bitOffset>23</bitOffset>
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  5756. <bitOffset>22</bitOffset>
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  5762. <bitOffset>21</bitOffset>
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  5768. <bitOffset>20</bitOffset>
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  5898. <size>0x20</size>
  5899. <access>read-write</access>
  5900. <resetValue>0x00000000</resetValue>
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  6023. <name>S11</name>
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  6028. <field>
  6029. <name>S10</name>
  6030. <description>S10</description>
  6031. <bitOffset>10</bitOffset>
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  6034. <field>
  6035. <name>S09</name>
  6036. <description>S09</description>
  6037. <bitOffset>9</bitOffset>
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  6040. <field>
  6041. <name>S08</name>
  6042. <description>S08</description>
  6043. <bitOffset>8</bitOffset>
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  6047. <name>S07</name>
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  6049. <bitOffset>7</bitOffset>
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  6054. <description>S06</description>
  6055. <bitOffset>6</bitOffset>
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  6058. <field>
  6059. <name>S05</name>
  6060. <description>S05</description>
  6061. <bitOffset>5</bitOffset>
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  6064. <field>
  6065. <name>S04</name>
  6066. <description>S04</description>
  6067. <bitOffset>4</bitOffset>
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  6070. <field>
  6071. <name>S03</name>
  6072. <description>S03</description>
  6073. <bitOffset>3</bitOffset>
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  6076. <field>
  6077. <name>S02</name>
  6078. <description>S02</description>
  6079. <bitOffset>2</bitOffset>
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  6082. <field>
  6083. <name>S01</name>
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  6090. <description>S00</description>
  6091. <bitOffset>0</bitOffset>
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  6096. <register>
  6097. <name>RAM_COM5</name>
  6098. <displayName>RAM_COM5</displayName>
  6099. <description>display memory</description>
  6100. <addressOffset>0x3C</addressOffset>
  6101. <size>0x20</size>
  6102. <access>read-write</access>
  6103. <resetValue>0x00000000</resetValue>
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  6105. <field>
  6106. <name>S31</name>
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  6108. <bitOffset>31</bitOffset>
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  6111. <field>
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  6114. <bitOffset>30</bitOffset>
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  6118. <name>S29</name>
  6119. <description>S29</description>
  6120. <bitOffset>29</bitOffset>
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  6123. <field>
  6124. <name>S28</name>
  6125. <description>S28</description>
  6126. <bitOffset>28</bitOffset>
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  6129. <field>
  6130. <name>S27</name>
  6131. <description>S27</description>
  6132. <bitOffset>27</bitOffset>
  6133. <bitWidth>1</bitWidth>
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  6135. <field>
  6136. <name>S26</name>
  6137. <description>S26</description>
  6138. <bitOffset>26</bitOffset>
  6139. <bitWidth>1</bitWidth>
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  6141. <field>
  6142. <name>S25</name>
  6143. <description>S25</description>
  6144. <bitOffset>25</bitOffset>
  6145. <bitWidth>1</bitWidth>
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  6147. <field>
  6148. <name>S24</name>
  6149. <description>S24</description>
  6150. <bitOffset>24</bitOffset>
  6151. <bitWidth>1</bitWidth>
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  6153. <field>
  6154. <name>S23</name>
  6155. <description>S23</description>
  6156. <bitOffset>23</bitOffset>
  6157. <bitWidth>1</bitWidth>
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  6159. <field>
  6160. <name>S22</name>
  6161. <description>S22</description>
  6162. <bitOffset>22</bitOffset>
  6163. <bitWidth>1</bitWidth>
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  6165. <field>
  6166. <name>S21</name>
  6167. <description>S21</description>
  6168. <bitOffset>21</bitOffset>
  6169. <bitWidth>1</bitWidth>
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  6171. <field>
  6172. <name>S20</name>
  6173. <description>S20</description>
  6174. <bitOffset>20</bitOffset>
  6175. <bitWidth>1</bitWidth>
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  6177. <field>
  6178. <name>S19</name>
  6179. <description>S19</description>
  6180. <bitOffset>19</bitOffset>
  6181. <bitWidth>1</bitWidth>
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  6183. <field>
  6184. <name>S18</name>
  6185. <description>S18</description>
  6186. <bitOffset>18</bitOffset>
  6187. <bitWidth>1</bitWidth>
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  6189. <field>
  6190. <name>S17</name>
  6191. <description>S17</description>
  6192. <bitOffset>17</bitOffset>
  6193. <bitWidth>1</bitWidth>
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  6195. <field>
  6196. <name>S16</name>
  6197. <description>S16</description>
  6198. <bitOffset>16</bitOffset>
  6199. <bitWidth>1</bitWidth>
  6200. </field>
  6201. <field>
  6202. <name>S15</name>
  6203. <description>S15</description>
  6204. <bitOffset>15</bitOffset>
  6205. <bitWidth>1</bitWidth>
  6206. </field>
  6207. <field>
  6208. <name>S14</name>
  6209. <description>S14</description>
  6210. <bitOffset>14</bitOffset>
  6211. <bitWidth>1</bitWidth>
  6212. </field>
  6213. <field>
  6214. <name>S13</name>
  6215. <description>S13</description>
  6216. <bitOffset>13</bitOffset>
  6217. <bitWidth>1</bitWidth>
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  6219. <field>
  6220. <name>S12</name>
  6221. <description>S12</description>
  6222. <bitOffset>12</bitOffset>
  6223. <bitWidth>1</bitWidth>
  6224. </field>
  6225. <field>
  6226. <name>S11</name>
  6227. <description>S11</description>
  6228. <bitOffset>11</bitOffset>
  6229. <bitWidth>1</bitWidth>
  6230. </field>
  6231. <field>
  6232. <name>S10</name>
  6233. <description>S10</description>
  6234. <bitOffset>10</bitOffset>
  6235. <bitWidth>1</bitWidth>
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  6237. <field>
  6238. <name>S09</name>
  6239. <description>S09</description>
  6240. <bitOffset>9</bitOffset>
  6241. <bitWidth>1</bitWidth>
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  6243. <field>
  6244. <name>S08</name>
  6245. <description>S08</description>
  6246. <bitOffset>8</bitOffset>
  6247. <bitWidth>1</bitWidth>
  6248. </field>
  6249. <field>
  6250. <name>S07</name>
  6251. <description>S07</description>
  6252. <bitOffset>7</bitOffset>
  6253. <bitWidth>1</bitWidth>
  6254. </field>
  6255. <field>
  6256. <name>S06</name>
  6257. <description>S06</description>
  6258. <bitOffset>6</bitOffset>
  6259. <bitWidth>1</bitWidth>
  6260. </field>
  6261. <field>
  6262. <name>S05</name>
  6263. <description>S05</description>
  6264. <bitOffset>5</bitOffset>
  6265. <bitWidth>1</bitWidth>
  6266. </field>
  6267. <field>
  6268. <name>S04</name>
  6269. <description>S04</description>
  6270. <bitOffset>4</bitOffset>
  6271. <bitWidth>1</bitWidth>
  6272. </field>
  6273. <field>
  6274. <name>S03</name>
  6275. <description>S03</description>
  6276. <bitOffset>3</bitOffset>
  6277. <bitWidth>1</bitWidth>
  6278. </field>
  6279. <field>
  6280. <name>S02</name>
  6281. <description>S02</description>
  6282. <bitOffset>2</bitOffset>
  6283. <bitWidth>1</bitWidth>
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  6285. <field>
  6286. <name>S01</name>
  6287. <description>S01</description>
  6288. <bitOffset>1</bitOffset>
  6289. <bitWidth>1</bitWidth>
  6290. </field>
  6291. <field>
  6292. <name>S00</name>
  6293. <description>S00</description>
  6294. <bitOffset>0</bitOffset>
  6295. <bitWidth>1</bitWidth>
  6296. </field>
  6297. </fields>
  6298. </register>
  6299. <register>
  6300. <name>RAM_COM6</name>
  6301. <displayName>RAM_COM6</displayName>
  6302. <description>display memory</description>
  6303. <addressOffset>0x44</addressOffset>
  6304. <size>0x20</size>
  6305. <access>read-write</access>
  6306. <resetValue>0x00000000</resetValue>
  6307. <fields>
  6308. <field>
  6309. <name>S31</name>
  6310. <description>S31</description>
  6311. <bitOffset>31</bitOffset>
  6312. <bitWidth>1</bitWidth>
  6313. </field>
  6314. <field>
  6315. <name>S30</name>
  6316. <description>S30</description>
  6317. <bitOffset>30</bitOffset>
  6318. <bitWidth>1</bitWidth>
  6319. </field>
  6320. <field>
  6321. <name>S29</name>
  6322. <description>S29</description>
  6323. <bitOffset>29</bitOffset>
  6324. <bitWidth>1</bitWidth>
  6325. </field>
  6326. <field>
  6327. <name>S28</name>
  6328. <description>S28</description>
  6329. <bitOffset>28</bitOffset>
  6330. <bitWidth>1</bitWidth>
  6331. </field>
  6332. <field>
  6333. <name>S27</name>
  6334. <description>S27</description>
  6335. <bitOffset>27</bitOffset>
  6336. <bitWidth>1</bitWidth>
  6337. </field>
  6338. <field>
  6339. <name>S26</name>
  6340. <description>S26</description>
  6341. <bitOffset>26</bitOffset>
  6342. <bitWidth>1</bitWidth>
  6343. </field>
  6344. <field>
  6345. <name>S25</name>
  6346. <description>S25</description>
  6347. <bitOffset>25</bitOffset>
  6348. <bitWidth>1</bitWidth>
  6349. </field>
  6350. <field>
  6351. <name>S24</name>
  6352. <description>S24</description>
  6353. <bitOffset>24</bitOffset>
  6354. <bitWidth>1</bitWidth>
  6355. </field>
  6356. <field>
  6357. <name>S23</name>
  6358. <description>S23</description>
  6359. <bitOffset>23</bitOffset>
  6360. <bitWidth>1</bitWidth>
  6361. </field>
  6362. <field>
  6363. <name>S22</name>
  6364. <description>S22</description>
  6365. <bitOffset>22</bitOffset>
  6366. <bitWidth>1</bitWidth>
  6367. </field>
  6368. <field>
  6369. <name>S21</name>
  6370. <description>S21</description>
  6371. <bitOffset>21</bitOffset>
  6372. <bitWidth>1</bitWidth>
  6373. </field>
  6374. <field>
  6375. <name>S20</name>
  6376. <description>S20</description>
  6377. <bitOffset>20</bitOffset>
  6378. <bitWidth>1</bitWidth>
  6379. </field>
  6380. <field>
  6381. <name>S19</name>
  6382. <description>S19</description>
  6383. <bitOffset>19</bitOffset>
  6384. <bitWidth>1</bitWidth>
  6385. </field>
  6386. <field>
  6387. <name>S18</name>
  6388. <description>S18</description>
  6389. <bitOffset>18</bitOffset>
  6390. <bitWidth>1</bitWidth>
  6391. </field>
  6392. <field>
  6393. <name>S17</name>
  6394. <description>S17</description>
  6395. <bitOffset>17</bitOffset>
  6396. <bitWidth>1</bitWidth>
  6397. </field>
  6398. <field>
  6399. <name>S16</name>
  6400. <description>S16</description>
  6401. <bitOffset>16</bitOffset>
  6402. <bitWidth>1</bitWidth>
  6403. </field>
  6404. <field>
  6405. <name>S15</name>
  6406. <description>S15</description>
  6407. <bitOffset>15</bitOffset>
  6408. <bitWidth>1</bitWidth>
  6409. </field>
  6410. <field>
  6411. <name>S14</name>
  6412. <description>S14</description>
  6413. <bitOffset>14</bitOffset>
  6414. <bitWidth>1</bitWidth>
  6415. </field>
  6416. <field>
  6417. <name>S13</name>
  6418. <description>S13</description>
  6419. <bitOffset>13</bitOffset>
  6420. <bitWidth>1</bitWidth>
  6421. </field>
  6422. <field>
  6423. <name>S12</name>
  6424. <description>S12</description>
  6425. <bitOffset>12</bitOffset>
  6426. <bitWidth>1</bitWidth>
  6427. </field>
  6428. <field>
  6429. <name>S11</name>
  6430. <description>S11</description>
  6431. <bitOffset>11</bitOffset>
  6432. <bitWidth>1</bitWidth>
  6433. </field>
  6434. <field>
  6435. <name>S10</name>
  6436. <description>S10</description>
  6437. <bitOffset>10</bitOffset>
  6438. <bitWidth>1</bitWidth>
  6439. </field>
  6440. <field>
  6441. <name>S09</name>
  6442. <description>S09</description>
  6443. <bitOffset>9</bitOffset>
  6444. <bitWidth>1</bitWidth>
  6445. </field>
  6446. <field>
  6447. <name>S08</name>
  6448. <description>S08</description>
  6449. <bitOffset>8</bitOffset>
  6450. <bitWidth>1</bitWidth>
  6451. </field>
  6452. <field>
  6453. <name>S07</name>
  6454. <description>S07</description>
  6455. <bitOffset>7</bitOffset>
  6456. <bitWidth>1</bitWidth>
  6457. </field>
  6458. <field>
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  6460. <description>S06</description>
  6461. <bitOffset>6</bitOffset>
  6462. <bitWidth>1</bitWidth>
  6463. </field>
  6464. <field>
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  6466. <description>S05</description>
  6467. <bitOffset>5</bitOffset>
  6468. <bitWidth>1</bitWidth>
  6469. </field>
  6470. <field>
  6471. <name>S04</name>
  6472. <description>S04</description>
  6473. <bitOffset>4</bitOffset>
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  6475. </field>
  6476. <field>
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  6478. <description>S03</description>
  6479. <bitOffset>3</bitOffset>
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  6481. </field>
  6482. <field>
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  6488. <field>
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  6491. <bitOffset>1</bitOffset>
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  6496. <description>S00</description>
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  6498. <bitWidth>1</bitWidth>
  6499. </field>
  6500. </fields>
  6501. </register>
  6502. <register>
  6503. <name>RAM_COM7</name>
  6504. <displayName>RAM_COM7</displayName>
  6505. <description>display memory</description>
  6506. <addressOffset>0x4C</addressOffset>
  6507. <size>0x20</size>
  6508. <access>read-write</access>
  6509. <resetValue>0x00000000</resetValue>
  6510. <fields>
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  6513. <description>S31</description>
  6514. <bitOffset>31</bitOffset>
  6515. <bitWidth>1</bitWidth>
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  6517. <field>
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  6519. <description>S30</description>
  6520. <bitOffset>30</bitOffset>
  6521. <bitWidth>1</bitWidth>
  6522. </field>
  6523. <field>
  6524. <name>S29</name>
  6525. <description>S29</description>
  6526. <bitOffset>29</bitOffset>
  6527. <bitWidth>1</bitWidth>
  6528. </field>
  6529. <field>
  6530. <name>S28</name>
  6531. <description>S28</description>
  6532. <bitOffset>28</bitOffset>
  6533. <bitWidth>1</bitWidth>
  6534. </field>
  6535. <field>
  6536. <name>S27</name>
  6537. <description>S27</description>
  6538. <bitOffset>27</bitOffset>
  6539. <bitWidth>1</bitWidth>
  6540. </field>
  6541. <field>
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  6543. <description>S26</description>
  6544. <bitOffset>26</bitOffset>
  6545. <bitWidth>1</bitWidth>
  6546. </field>
  6547. <field>
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  6549. <description>S25</description>
  6550. <bitOffset>25</bitOffset>
  6551. <bitWidth>1</bitWidth>
  6552. </field>
  6553. <field>
  6554. <name>S24</name>
  6555. <description>S24</description>
  6556. <bitOffset>24</bitOffset>
  6557. <bitWidth>1</bitWidth>
  6558. </field>
  6559. <field>
  6560. <name>S23</name>
  6561. <description>S23</description>
  6562. <bitOffset>23</bitOffset>
  6563. <bitWidth>1</bitWidth>
  6564. </field>
  6565. <field>
  6566. <name>S22</name>
  6567. <description>S22</description>
  6568. <bitOffset>22</bitOffset>
  6569. <bitWidth>1</bitWidth>
  6570. </field>
  6571. <field>
  6572. <name>S21</name>
  6573. <description>S21</description>
  6574. <bitOffset>21</bitOffset>
  6575. <bitWidth>1</bitWidth>
  6576. </field>
  6577. <field>
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  6579. <description>S20</description>
  6580. <bitOffset>20</bitOffset>
  6581. <bitWidth>1</bitWidth>
  6582. </field>
  6583. <field>
  6584. <name>S19</name>
  6585. <description>S19</description>
  6586. <bitOffset>19</bitOffset>
  6587. <bitWidth>1</bitWidth>
  6588. </field>
  6589. <field>
  6590. <name>S18</name>
  6591. <description>S18</description>
  6592. <bitOffset>18</bitOffset>
  6593. <bitWidth>1</bitWidth>
  6594. </field>
  6595. <field>
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  6597. <description>S17</description>
  6598. <bitOffset>17</bitOffset>
  6599. <bitWidth>1</bitWidth>
  6600. </field>
  6601. <field>
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  6604. <bitOffset>16</bitOffset>
  6605. <bitWidth>1</bitWidth>
  6606. </field>
  6607. <field>
  6608. <name>S15</name>
  6609. <description>S15</description>
  6610. <bitOffset>15</bitOffset>
  6611. <bitWidth>1</bitWidth>
  6612. </field>
  6613. <field>
  6614. <name>S14</name>
  6615. <description>S14</description>
  6616. <bitOffset>14</bitOffset>
  6617. <bitWidth>1</bitWidth>
  6618. </field>
  6619. <field>
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  6621. <description>S13</description>
  6622. <bitOffset>13</bitOffset>
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  6624. </field>
  6625. <field>
  6626. <name>S12</name>
  6627. <description>S12</description>
  6628. <bitOffset>12</bitOffset>
  6629. <bitWidth>1</bitWidth>
  6630. </field>
  6631. <field>
  6632. <name>S11</name>
  6633. <description>S11</description>
  6634. <bitOffset>11</bitOffset>
  6635. <bitWidth>1</bitWidth>
  6636. </field>
  6637. <field>
  6638. <name>S10</name>
  6639. <description>S10</description>
  6640. <bitOffset>10</bitOffset>
  6641. <bitWidth>1</bitWidth>
  6642. </field>
  6643. <field>
  6644. <name>S09</name>
  6645. <description>S09</description>
  6646. <bitOffset>9</bitOffset>
  6647. <bitWidth>1</bitWidth>
  6648. </field>
  6649. <field>
  6650. <name>S08</name>
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  6652. <bitOffset>8</bitOffset>
  6653. <bitWidth>1</bitWidth>
  6654. </field>
  6655. <field>
  6656. <name>S07</name>
  6657. <description>S07</description>
  6658. <bitOffset>7</bitOffset>
  6659. <bitWidth>1</bitWidth>
  6660. </field>
  6661. <field>
  6662. <name>S06</name>
  6663. <description>S06</description>
  6664. <bitOffset>6</bitOffset>
  6665. <bitWidth>1</bitWidth>
  6666. </field>
  6667. <field>
  6668. <name>S05</name>
  6669. <description>S05</description>
  6670. <bitOffset>5</bitOffset>
  6671. <bitWidth>1</bitWidth>
  6672. </field>
  6673. <field>
  6674. <name>S04</name>
  6675. <description>S04</description>
  6676. <bitOffset>4</bitOffset>
  6677. <bitWidth>1</bitWidth>
  6678. </field>
  6679. <field>
  6680. <name>S03</name>
  6681. <description>S03</description>
  6682. <bitOffset>3</bitOffset>
  6683. <bitWidth>1</bitWidth>
  6684. </field>
  6685. <field>
  6686. <name>S02</name>
  6687. <description>S02</description>
  6688. <bitOffset>2</bitOffset>
  6689. <bitWidth>1</bitWidth>
  6690. </field>
  6691. <field>
  6692. <name>S01</name>
  6693. <description>S01</description>
  6694. <bitOffset>1</bitOffset>
  6695. <bitWidth>1</bitWidth>
  6696. </field>
  6697. <field>
  6698. <name>S00</name>
  6699. <description>S00</description>
  6700. <bitOffset>0</bitOffset>
  6701. <bitWidth>1</bitWidth>
  6702. </field>
  6703. </fields>
  6704. </register>
  6705. </registers>
  6706. </peripheral>
  6707. <peripheral>
  6708. <name>LPTIM</name>
  6709. <description>Low power timer</description>
  6710. <groupName>LPTIM</groupName>
  6711. <baseAddress>0x40007C00</baseAddress>
  6712. <addressBlock>
  6713. <offset>0x0</offset>
  6714. <size>0x400</size>
  6715. <usage>registers</usage>
  6716. </addressBlock>
  6717. <interrupt>
  6718. <name>LPTIM1</name>
  6719. <description>LPTIMER1 interrupt through
  6720. EXTI29</description>
  6721. <value>13</value>
  6722. </interrupt>
  6723. <registers>
  6724. <register>
  6725. <name>ISR</name>
  6726. <displayName>ISR</displayName>
  6727. <description>Interrupt and Status Register</description>
  6728. <addressOffset>0x0</addressOffset>
  6729. <size>0x20</size>
  6730. <access>read-only</access>
  6731. <resetValue>0x00000000</resetValue>
  6732. <fields>
  6733. <field>
  6734. <name>DOWN</name>
  6735. <description>Counter direction change up to
  6736. down</description>
  6737. <bitOffset>6</bitOffset>
  6738. <bitWidth>1</bitWidth>
  6739. </field>
  6740. <field>
  6741. <name>UP</name>
  6742. <description>Counter direction change down to
  6743. up</description>
  6744. <bitOffset>5</bitOffset>
  6745. <bitWidth>1</bitWidth>
  6746. </field>
  6747. <field>
  6748. <name>ARROK</name>
  6749. <description>Autoreload register update
  6750. OK</description>
  6751. <bitOffset>4</bitOffset>
  6752. <bitWidth>1</bitWidth>
  6753. </field>
  6754. <field>
  6755. <name>CMPOK</name>
  6756. <description>Compare register update OK</description>
  6757. <bitOffset>3</bitOffset>
  6758. <bitWidth>1</bitWidth>
  6759. </field>
  6760. <field>
  6761. <name>EXTTRIG</name>
  6762. <description>External trigger edge
  6763. event</description>
  6764. <bitOffset>2</bitOffset>
  6765. <bitWidth>1</bitWidth>
  6766. </field>
  6767. <field>
  6768. <name>ARRM</name>
  6769. <description>Autoreload match</description>
  6770. <bitOffset>1</bitOffset>
  6771. <bitWidth>1</bitWidth>
  6772. </field>
  6773. <field>
  6774. <name>CMPM</name>
  6775. <description>Compare match</description>
  6776. <bitOffset>0</bitOffset>
  6777. <bitWidth>1</bitWidth>
  6778. </field>
  6779. </fields>
  6780. </register>
  6781. <register>
  6782. <name>ICR</name>
  6783. <displayName>ICR</displayName>
  6784. <description>Interrupt Clear Register</description>
  6785. <addressOffset>0x4</addressOffset>
  6786. <size>0x20</size>
  6787. <access>write-only</access>
  6788. <resetValue>0x00000000</resetValue>
  6789. <fields>
  6790. <field>
  6791. <name>DOWNCF</name>
  6792. <description>Direction change to down Clear
  6793. Flag</description>
  6794. <bitOffset>6</bitOffset>
  6795. <bitWidth>1</bitWidth>
  6796. </field>
  6797. <field>
  6798. <name>UPCF</name>
  6799. <description>Direction change to UP Clear
  6800. Flag</description>
  6801. <bitOffset>5</bitOffset>
  6802. <bitWidth>1</bitWidth>
  6803. </field>
  6804. <field>
  6805. <name>ARROKCF</name>
  6806. <description>Autoreload register update OK Clear
  6807. Flag</description>
  6808. <bitOffset>4</bitOffset>
  6809. <bitWidth>1</bitWidth>
  6810. </field>
  6811. <field>
  6812. <name>CMPOKCF</name>
  6813. <description>Compare register update OK Clear
  6814. Flag</description>
  6815. <bitOffset>3</bitOffset>
  6816. <bitWidth>1</bitWidth>
  6817. </field>
  6818. <field>
  6819. <name>EXTTRIGCF</name>
  6820. <description>External trigger valid edge Clear
  6821. Flag</description>
  6822. <bitOffset>2</bitOffset>
  6823. <bitWidth>1</bitWidth>
  6824. </field>
  6825. <field>
  6826. <name>ARRMCF</name>
  6827. <description>Autoreload match Clear
  6828. Flag</description>
  6829. <bitOffset>1</bitOffset>
  6830. <bitWidth>1</bitWidth>
  6831. </field>
  6832. <field>
  6833. <name>CMPMCF</name>
  6834. <description>compare match Clear Flag</description>
  6835. <bitOffset>0</bitOffset>
  6836. <bitWidth>1</bitWidth>
  6837. </field>
  6838. </fields>
  6839. </register>
  6840. <register>
  6841. <name>IER</name>
  6842. <displayName>IER</displayName>
  6843. <description>Interrupt Enable Register</description>
  6844. <addressOffset>0x8</addressOffset>
  6845. <size>0x20</size>
  6846. <access>read-write</access>
  6847. <resetValue>0x00000000</resetValue>
  6848. <fields>
  6849. <field>
  6850. <name>DOWNIE</name>
  6851. <description>Direction change to down Interrupt
  6852. Enable</description>
  6853. <bitOffset>6</bitOffset>
  6854. <bitWidth>1</bitWidth>
  6855. </field>
  6856. <field>
  6857. <name>UPIE</name>
  6858. <description>Direction change to UP Interrupt
  6859. Enable</description>
  6860. <bitOffset>5</bitOffset>
  6861. <bitWidth>1</bitWidth>
  6862. </field>
  6863. <field>
  6864. <name>ARROKIE</name>
  6865. <description>Autoreload register update OK Interrupt
  6866. Enable</description>
  6867. <bitOffset>4</bitOffset>
  6868. <bitWidth>1</bitWidth>
  6869. </field>
  6870. <field>
  6871. <name>CMPOKIE</name>
  6872. <description>Compare register update OK Interrupt
  6873. Enable</description>
  6874. <bitOffset>3</bitOffset>
  6875. <bitWidth>1</bitWidth>
  6876. </field>
  6877. <field>
  6878. <name>EXTTRIGIE</name>
  6879. <description>External trigger valid edge Interrupt
  6880. Enable</description>
  6881. <bitOffset>2</bitOffset>
  6882. <bitWidth>1</bitWidth>
  6883. </field>
  6884. <field>
  6885. <name>ARRMIE</name>
  6886. <description>Autoreload match Interrupt
  6887. Enable</description>
  6888. <bitOffset>1</bitOffset>
  6889. <bitWidth>1</bitWidth>
  6890. </field>
  6891. <field>
  6892. <name>CMPMIE</name>
  6893. <description>Compare match Interrupt
  6894. Enable</description>
  6895. <bitOffset>0</bitOffset>
  6896. <bitWidth>1</bitWidth>
  6897. </field>
  6898. </fields>
  6899. </register>
  6900. <register>
  6901. <name>CFGR</name>
  6902. <displayName>CFGR</displayName>
  6903. <description>Configuration Register</description>
  6904. <addressOffset>0xC</addressOffset>
  6905. <size>0x20</size>
  6906. <access>read-write</access>
  6907. <resetValue>0x00000000</resetValue>
  6908. <fields>
  6909. <field>
  6910. <name>ENC</name>
  6911. <description>Encoder mode enable</description>
  6912. <bitOffset>24</bitOffset>
  6913. <bitWidth>1</bitWidth>
  6914. </field>
  6915. <field>
  6916. <name>COUNTMODE</name>
  6917. <description>counter mode enabled</description>
  6918. <bitOffset>23</bitOffset>
  6919. <bitWidth>1</bitWidth>
  6920. </field>
  6921. <field>
  6922. <name>PRELOAD</name>
  6923. <description>Registers update mode</description>
  6924. <bitOffset>22</bitOffset>
  6925. <bitWidth>1</bitWidth>
  6926. </field>
  6927. <field>
  6928. <name>WAVPOL</name>
  6929. <description>Waveform shape polarity</description>
  6930. <bitOffset>21</bitOffset>
  6931. <bitWidth>1</bitWidth>
  6932. </field>
  6933. <field>
  6934. <name>WAVE</name>
  6935. <description>Waveform shape</description>
  6936. <bitOffset>20</bitOffset>
  6937. <bitWidth>1</bitWidth>
  6938. </field>
  6939. <field>
  6940. <name>TIMOUT</name>
  6941. <description>Timeout enable</description>
  6942. <bitOffset>19</bitOffset>
  6943. <bitWidth>1</bitWidth>
  6944. </field>
  6945. <field>
  6946. <name>TRIGEN</name>
  6947. <description>Trigger enable and
  6948. polarity</description>
  6949. <bitOffset>17</bitOffset>
  6950. <bitWidth>2</bitWidth>
  6951. </field>
  6952. <field>
  6953. <name>TRIGSEL</name>
  6954. <description>Trigger selector</description>
  6955. <bitOffset>13</bitOffset>
  6956. <bitWidth>3</bitWidth>
  6957. </field>
  6958. <field>
  6959. <name>PRESC</name>
  6960. <description>Clock prescaler</description>
  6961. <bitOffset>9</bitOffset>
  6962. <bitWidth>3</bitWidth>
  6963. </field>
  6964. <field>
  6965. <name>TRGFLT</name>
  6966. <description>Configurable digital filter for
  6967. trigger</description>
  6968. <bitOffset>6</bitOffset>
  6969. <bitWidth>2</bitWidth>
  6970. </field>
  6971. <field>
  6972. <name>CKFLT</name>
  6973. <description>Configurable digital filter for external
  6974. clock</description>
  6975. <bitOffset>3</bitOffset>
  6976. <bitWidth>2</bitWidth>
  6977. </field>
  6978. <field>
  6979. <name>CKPOL</name>
  6980. <description>Clock Polarity</description>
  6981. <bitOffset>1</bitOffset>
  6982. <bitWidth>2</bitWidth>
  6983. </field>
  6984. <field>
  6985. <name>CKSEL</name>
  6986. <description>Clock selector</description>
  6987. <bitOffset>0</bitOffset>
  6988. <bitWidth>1</bitWidth>
  6989. </field>
  6990. </fields>
  6991. </register>
  6992. <register>
  6993. <name>CR</name>
  6994. <displayName>CR</displayName>
  6995. <description>Control Register</description>
  6996. <addressOffset>0x10</addressOffset>
  6997. <size>0x20</size>
  6998. <access>read-write</access>
  6999. <resetValue>0x00000000</resetValue>
  7000. <fields>
  7001. <field>
  7002. <name>CNTSTRT</name>
  7003. <description>Timer start in continuous
  7004. mode</description>
  7005. <bitOffset>2</bitOffset>
  7006. <bitWidth>1</bitWidth>
  7007. </field>
  7008. <field>
  7009. <name>SNGSTRT</name>
  7010. <description>LPTIM start in single mode</description>
  7011. <bitOffset>1</bitOffset>
  7012. <bitWidth>1</bitWidth>
  7013. </field>
  7014. <field>
  7015. <name>ENABLE</name>
  7016. <description>LPTIM Enable</description>
  7017. <bitOffset>0</bitOffset>
  7018. <bitWidth>1</bitWidth>
  7019. </field>
  7020. </fields>
  7021. </register>
  7022. <register>
  7023. <name>CMP</name>
  7024. <displayName>CMP</displayName>
  7025. <description>Compare Register</description>
  7026. <addressOffset>0x14</addressOffset>
  7027. <size>0x20</size>
  7028. <access>read-write</access>
  7029. <resetValue>0x00000000</resetValue>
  7030. <fields>
  7031. <field>
  7032. <name>CMP</name>
  7033. <description>Compare value.</description>
  7034. <bitOffset>0</bitOffset>
  7035. <bitWidth>16</bitWidth>
  7036. </field>
  7037. </fields>
  7038. </register>
  7039. <register>
  7040. <name>ARR</name>
  7041. <displayName>ARR</displayName>
  7042. <description>Autoreload Register</description>
  7043. <addressOffset>0x18</addressOffset>
  7044. <size>0x20</size>
  7045. <access>read-write</access>
  7046. <resetValue>0x00000001</resetValue>
  7047. <fields>
  7048. <field>
  7049. <name>ARR</name>
  7050. <description>Auto reload value.</description>
  7051. <bitOffset>0</bitOffset>
  7052. <bitWidth>16</bitWidth>
  7053. </field>
  7054. </fields>
  7055. </register>
  7056. <register>
  7057. <name>CNT</name>
  7058. <displayName>CNT</displayName>
  7059. <description>Counter Register</description>
  7060. <addressOffset>0x1C</addressOffset>
  7061. <size>0x20</size>
  7062. <access>read-only</access>
  7063. <resetValue>0x00000000</resetValue>
  7064. <fields>
  7065. <field>
  7066. <name>CNT</name>
  7067. <description>Counter value.</description>
  7068. <bitOffset>0</bitOffset>
  7069. <bitWidth>16</bitWidth>
  7070. </field>
  7071. </fields>
  7072. </register>
  7073. </registers>
  7074. </peripheral>
  7075. <peripheral>
  7076. <name>RNG</name>
  7077. <description>Random number generator</description>
  7078. <groupName>RNG</groupName>
  7079. <baseAddress>0x40025000</baseAddress>
  7080. <addressBlock>
  7081. <offset>0x0</offset>
  7082. <size>0x400</size>
  7083. <usage>registers</usage>
  7084. </addressBlock>
  7085. <registers>
  7086. <register>
  7087. <name>CR</name>
  7088. <displayName>CR</displayName>
  7089. <description>control register</description>
  7090. <addressOffset>0x0</addressOffset>
  7091. <size>0x20</size>
  7092. <access>read-write</access>
  7093. <resetValue>0x00000000</resetValue>
  7094. <fields>
  7095. <field>
  7096. <name>IE</name>
  7097. <description>Interrupt enable</description>
  7098. <bitOffset>3</bitOffset>
  7099. <bitWidth>1</bitWidth>
  7100. </field>
  7101. <field>
  7102. <name>RNGEN</name>
  7103. <description>Random number generator
  7104. enable</description>
  7105. <bitOffset>2</bitOffset>
  7106. <bitWidth>1</bitWidth>
  7107. </field>
  7108. </fields>
  7109. </register>
  7110. <register>
  7111. <name>SR</name>
  7112. <displayName>SR</displayName>
  7113. <description>status register</description>
  7114. <addressOffset>0x4</addressOffset>
  7115. <size>0x20</size>
  7116. <resetValue>0x00000000</resetValue>
  7117. <fields>
  7118. <field>
  7119. <name>SEIS</name>
  7120. <description>Seed error interrupt
  7121. status</description>
  7122. <bitOffset>6</bitOffset>
  7123. <bitWidth>1</bitWidth>
  7124. <access>read-write</access>
  7125. </field>
  7126. <field>
  7127. <name>CEIS</name>
  7128. <description>Clock error interrupt
  7129. status</description>
  7130. <bitOffset>5</bitOffset>
  7131. <bitWidth>1</bitWidth>
  7132. <access>read-write</access>
  7133. </field>
  7134. <field>
  7135. <name>SECS</name>
  7136. <description>Seed error current status</description>
  7137. <bitOffset>2</bitOffset>
  7138. <bitWidth>1</bitWidth>
  7139. <access>read-only</access>
  7140. </field>
  7141. <field>
  7142. <name>CECS</name>
  7143. <description>Clock error current status</description>
  7144. <bitOffset>1</bitOffset>
  7145. <bitWidth>1</bitWidth>
  7146. <access>read-only</access>
  7147. </field>
  7148. <field>
  7149. <name>DRDY</name>
  7150. <description>Data ready</description>
  7151. <bitOffset>0</bitOffset>
  7152. <bitWidth>1</bitWidth>
  7153. <access>read-only</access>
  7154. </field>
  7155. </fields>
  7156. </register>
  7157. <register>
  7158. <name>DR</name>
  7159. <displayName>DR</displayName>
  7160. <description>data register</description>
  7161. <addressOffset>0x8</addressOffset>
  7162. <size>0x20</size>
  7163. <access>read-only</access>
  7164. <resetValue>0x00000000</resetValue>
  7165. <fields>
  7166. <field>
  7167. <name>RNDATA</name>
  7168. <description>Random data</description>
  7169. <bitOffset>0</bitOffset>
  7170. <bitWidth>32</bitWidth>
  7171. </field>
  7172. </fields>
  7173. </register>
  7174. </registers>
  7175. </peripheral>
  7176. <peripheral>
  7177. <name>RTC</name>
  7178. <description>Real-time clock</description>
  7179. <groupName>RTC</groupName>
  7180. <baseAddress>0x40002800</baseAddress>
  7181. <addressBlock>
  7182. <offset>0x0</offset>
  7183. <size>0x400</size>
  7184. <usage>registers</usage>
  7185. </addressBlock>
  7186. <interrupt>
  7187. <name>RTC</name>
  7188. <description>RTC global interrupt</description>
  7189. <value>2</value>
  7190. </interrupt>
  7191. <registers>
  7192. <register>
  7193. <name>TR</name>
  7194. <displayName>TR</displayName>
  7195. <description>RTC time register</description>
  7196. <addressOffset>0x0</addressOffset>
  7197. <size>0x20</size>
  7198. <access>read-write</access>
  7199. <resetValue>0x00000000</resetValue>
  7200. <fields>
  7201. <field>
  7202. <name>PM</name>
  7203. <description>AM/PM notation</description>
  7204. <bitOffset>22</bitOffset>
  7205. <bitWidth>1</bitWidth>
  7206. </field>
  7207. <field>
  7208. <name>HT</name>
  7209. <description>Hour tens in BCD format</description>
  7210. <bitOffset>20</bitOffset>
  7211. <bitWidth>2</bitWidth>
  7212. </field>
  7213. <field>
  7214. <name>HU</name>
  7215. <description>Hour units in BCD format</description>
  7216. <bitOffset>16</bitOffset>
  7217. <bitWidth>4</bitWidth>
  7218. </field>
  7219. <field>
  7220. <name>MNT</name>
  7221. <description>Minute tens in BCD format</description>
  7222. <bitOffset>12</bitOffset>
  7223. <bitWidth>3</bitWidth>
  7224. </field>
  7225. <field>
  7226. <name>MNU</name>
  7227. <description>Minute units in BCD format</description>
  7228. <bitOffset>8</bitOffset>
  7229. <bitWidth>4</bitWidth>
  7230. </field>
  7231. <field>
  7232. <name>ST</name>
  7233. <description>Second tens in BCD format</description>
  7234. <bitOffset>4</bitOffset>
  7235. <bitWidth>3</bitWidth>
  7236. </field>
  7237. <field>
  7238. <name>SU</name>
  7239. <description>Second units in BCD format</description>
  7240. <bitOffset>0</bitOffset>
  7241. <bitWidth>4</bitWidth>
  7242. </field>
  7243. </fields>
  7244. </register>
  7245. <register>
  7246. <name>DR</name>
  7247. <displayName>DR</displayName>
  7248. <description>RTC date register</description>
  7249. <addressOffset>0x4</addressOffset>
  7250. <size>0x20</size>
  7251. <access>read-write</access>
  7252. <resetValue>0x00000000</resetValue>
  7253. <fields>
  7254. <field>
  7255. <name>YT</name>
  7256. <description>Year tens in BCD format</description>
  7257. <bitOffset>20</bitOffset>
  7258. <bitWidth>4</bitWidth>
  7259. </field>
  7260. <field>
  7261. <name>YU</name>
  7262. <description>Year units in BCD format</description>
  7263. <bitOffset>16</bitOffset>
  7264. <bitWidth>4</bitWidth>
  7265. </field>
  7266. <field>
  7267. <name>WDU</name>
  7268. <description>Week day units</description>
  7269. <bitOffset>13</bitOffset>
  7270. <bitWidth>3</bitWidth>
  7271. </field>
  7272. <field>
  7273. <name>MT</name>
  7274. <description>Month tens in BCD format</description>
  7275. <bitOffset>12</bitOffset>
  7276. <bitWidth>1</bitWidth>
  7277. </field>
  7278. <field>
  7279. <name>MU</name>
  7280. <description>Month units in BCD format</description>
  7281. <bitOffset>8</bitOffset>
  7282. <bitWidth>4</bitWidth>
  7283. </field>
  7284. <field>
  7285. <name>DT</name>
  7286. <description>Date tens in BCD format</description>
  7287. <bitOffset>4</bitOffset>
  7288. <bitWidth>2</bitWidth>
  7289. </field>
  7290. <field>
  7291. <name>DU</name>
  7292. <description>Date units in BCD format</description>
  7293. <bitOffset>0</bitOffset>
  7294. <bitWidth>4</bitWidth>
  7295. </field>
  7296. </fields>
  7297. </register>
  7298. <register>
  7299. <name>CR</name>
  7300. <displayName>CR</displayName>
  7301. <description>RTC control register</description>
  7302. <addressOffset>0x8</addressOffset>
  7303. <size>0x20</size>
  7304. <resetValue>0x00000000</resetValue>
  7305. <fields>
  7306. <field>
  7307. <name>COE</name>
  7308. <description>Calibration output enable</description>
  7309. <bitOffset>23</bitOffset>
  7310. <bitWidth>1</bitWidth>
  7311. <access>read-write</access>
  7312. </field>
  7313. <field>
  7314. <name>OSEL</name>
  7315. <description>Output selection</description>
  7316. <bitOffset>21</bitOffset>
  7317. <bitWidth>2</bitWidth>
  7318. <access>read-write</access>
  7319. </field>
  7320. <field>
  7321. <name>POL</name>
  7322. <description>Output polarity</description>
  7323. <bitOffset>20</bitOffset>
  7324. <bitWidth>1</bitWidth>
  7325. <access>read-write</access>
  7326. </field>
  7327. <field>
  7328. <name>COSEL</name>
  7329. <description>Calibration output
  7330. selection</description>
  7331. <bitOffset>19</bitOffset>
  7332. <bitWidth>1</bitWidth>
  7333. <access>read-write</access>
  7334. </field>
  7335. <field>
  7336. <name>BKP</name>
  7337. <description>Backup</description>
  7338. <bitOffset>18</bitOffset>
  7339. <bitWidth>1</bitWidth>
  7340. <access>read-write</access>
  7341. </field>
  7342. <field>
  7343. <name>SUB1H</name>
  7344. <description>Subtract 1 hour (winter time
  7345. change)</description>
  7346. <bitOffset>17</bitOffset>
  7347. <bitWidth>1</bitWidth>
  7348. <access>write-only</access>
  7349. </field>
  7350. <field>
  7351. <name>ADD1H</name>
  7352. <description>Add 1 hour (summer time
  7353. change)</description>
  7354. <bitOffset>16</bitOffset>
  7355. <bitWidth>1</bitWidth>
  7356. <access>write-only</access>
  7357. </field>
  7358. <field>
  7359. <name>TSIE</name>
  7360. <description>Time-stamp interrupt
  7361. enable</description>
  7362. <bitOffset>15</bitOffset>
  7363. <bitWidth>1</bitWidth>
  7364. <access>read-write</access>
  7365. </field>
  7366. <field>
  7367. <name>WUTIE</name>
  7368. <description>Wakeup timer interrupt
  7369. enable</description>
  7370. <bitOffset>14</bitOffset>
  7371. <bitWidth>1</bitWidth>
  7372. <access>read-write</access>
  7373. </field>
  7374. <field>
  7375. <name>ALRBIE</name>
  7376. <description>Alarm B interrupt enable</description>
  7377. <bitOffset>13</bitOffset>
  7378. <bitWidth>1</bitWidth>
  7379. <access>read-write</access>
  7380. </field>
  7381. <field>
  7382. <name>ALRAIE</name>
  7383. <description>Alarm A interrupt enable</description>
  7384. <bitOffset>12</bitOffset>
  7385. <bitWidth>1</bitWidth>
  7386. <access>read-write</access>
  7387. </field>
  7388. <field>
  7389. <name>TSE</name>
  7390. <description>timestamp enable</description>
  7391. <bitOffset>11</bitOffset>
  7392. <bitWidth>1</bitWidth>
  7393. <access>read-write</access>
  7394. </field>
  7395. <field>
  7396. <name>WUTE</name>
  7397. <description>Wakeup timer enable</description>
  7398. <bitOffset>10</bitOffset>
  7399. <bitWidth>1</bitWidth>
  7400. <access>read-write</access>
  7401. </field>
  7402. <field>
  7403. <name>ALRBE</name>
  7404. <description>Alarm B enable</description>
  7405. <bitOffset>9</bitOffset>
  7406. <bitWidth>1</bitWidth>
  7407. <access>read-write</access>
  7408. </field>
  7409. <field>
  7410. <name>ALRAE</name>
  7411. <description>Alarm A enable</description>
  7412. <bitOffset>8</bitOffset>
  7413. <bitWidth>1</bitWidth>
  7414. <access>read-write</access>
  7415. </field>
  7416. <field>
  7417. <name>FMT</name>
  7418. <description>Hour format</description>
  7419. <bitOffset>6</bitOffset>
  7420. <bitWidth>1</bitWidth>
  7421. <access>read-write</access>
  7422. </field>
  7423. <field>
  7424. <name>BYPSHAD</name>
  7425. <description>Bypass the shadow
  7426. registers</description>
  7427. <bitOffset>5</bitOffset>
  7428. <bitWidth>1</bitWidth>
  7429. <access>read-write</access>
  7430. </field>
  7431. <field>
  7432. <name>REFCKON</name>
  7433. <description>RTC_REFIN reference clock detection
  7434. enable (50 or 60 Hz)</description>
  7435. <bitOffset>4</bitOffset>
  7436. <bitWidth>1</bitWidth>
  7437. <access>read-write</access>
  7438. </field>
  7439. <field>
  7440. <name>TSEDGE</name>
  7441. <description>Time-stamp event active
  7442. edge</description>
  7443. <bitOffset>3</bitOffset>
  7444. <bitWidth>1</bitWidth>
  7445. <access>read-write</access>
  7446. </field>
  7447. <field>
  7448. <name>WUCKSEL</name>
  7449. <description>Wakeup clock selection</description>
  7450. <bitOffset>0</bitOffset>
  7451. <bitWidth>3</bitWidth>
  7452. <access>read-write</access>
  7453. </field>
  7454. </fields>
  7455. </register>
  7456. <register>
  7457. <name>ISR</name>
  7458. <displayName>ISR</displayName>
  7459. <description>RTC initialization and status
  7460. register</description>
  7461. <addressOffset>0xC</addressOffset>
  7462. <size>0x20</size>
  7463. <resetValue>0x00000000</resetValue>
  7464. <fields>
  7465. <field>
  7466. <name>TAMP2F</name>
  7467. <description>RTC_TAMP2 detection flag</description>
  7468. <bitOffset>14</bitOffset>
  7469. <bitWidth>1</bitWidth>
  7470. <access>read-write</access>
  7471. </field>
  7472. <field>
  7473. <name>TAMP1F</name>
  7474. <description>RTC_TAMP1 detection flag</description>
  7475. <bitOffset>13</bitOffset>
  7476. <bitWidth>1</bitWidth>
  7477. <access>read-write</access>
  7478. </field>
  7479. <field>
  7480. <name>TSOVF</name>
  7481. <description>Time-stamp overflow flag</description>
  7482. <bitOffset>12</bitOffset>
  7483. <bitWidth>1</bitWidth>
  7484. <access>read-write</access>
  7485. </field>
  7486. <field>
  7487. <name>TSF</name>
  7488. <description>Time-stamp flag</description>
  7489. <bitOffset>11</bitOffset>
  7490. <bitWidth>1</bitWidth>
  7491. <access>read-write</access>
  7492. </field>
  7493. <field>
  7494. <name>WUTF</name>
  7495. <description>Wakeup timer flag</description>
  7496. <bitOffset>10</bitOffset>
  7497. <bitWidth>1</bitWidth>
  7498. <access>read-write</access>
  7499. </field>
  7500. <field>
  7501. <name>ALRBF</name>
  7502. <description>Alarm B flag</description>
  7503. <bitOffset>9</bitOffset>
  7504. <bitWidth>1</bitWidth>
  7505. <access>read-write</access>
  7506. </field>
  7507. <field>
  7508. <name>ALRAF</name>
  7509. <description>Alarm A flag</description>
  7510. <bitOffset>8</bitOffset>
  7511. <bitWidth>1</bitWidth>
  7512. <access>read-write</access>
  7513. </field>
  7514. <field>
  7515. <name>INIT</name>
  7516. <description>Initialization mode</description>
  7517. <bitOffset>7</bitOffset>
  7518. <bitWidth>1</bitWidth>
  7519. <access>read-write</access>
  7520. </field>
  7521. <field>
  7522. <name>INITF</name>
  7523. <description>Initialization flag</description>
  7524. <bitOffset>6</bitOffset>
  7525. <bitWidth>1</bitWidth>
  7526. <access>read-only</access>
  7527. </field>
  7528. <field>
  7529. <name>RSF</name>
  7530. <description>Registers synchronization
  7531. flag</description>
  7532. <bitOffset>5</bitOffset>
  7533. <bitWidth>1</bitWidth>
  7534. <access>read-write</access>
  7535. </field>
  7536. <field>
  7537. <name>INITS</name>
  7538. <description>Initialization status flag</description>
  7539. <bitOffset>4</bitOffset>
  7540. <bitWidth>1</bitWidth>
  7541. <access>read-only</access>
  7542. </field>
  7543. <field>
  7544. <name>SHPF</name>
  7545. <description>Shift operation pending</description>
  7546. <bitOffset>3</bitOffset>
  7547. <bitWidth>1</bitWidth>
  7548. <access>read-only</access>
  7549. </field>
  7550. <field>
  7551. <name>WUTWF</name>
  7552. <description>Wakeup timer write flag</description>
  7553. <bitOffset>2</bitOffset>
  7554. <bitWidth>1</bitWidth>
  7555. <access>read-only</access>
  7556. </field>
  7557. <field>
  7558. <name>ALRBWF</name>
  7559. <description>Alarm B write flag</description>
  7560. <bitOffset>1</bitOffset>
  7561. <bitWidth>1</bitWidth>
  7562. <access>read-only</access>
  7563. </field>
  7564. <field>
  7565. <name>ALRAWF</name>
  7566. <description>Alarm A write flag</description>
  7567. <bitOffset>0</bitOffset>
  7568. <bitWidth>1</bitWidth>
  7569. <access>read-only</access>
  7570. </field>
  7571. </fields>
  7572. </register>
  7573. <register>
  7574. <name>PRER</name>
  7575. <displayName>PRER</displayName>
  7576. <description>RTC prescaler register</description>
  7577. <addressOffset>0x10</addressOffset>
  7578. <size>0x20</size>
  7579. <access>read-write</access>
  7580. <resetValue>0x00000000</resetValue>
  7581. <fields>
  7582. <field>
  7583. <name>PREDIV_A</name>
  7584. <description>Asynchronous prescaler
  7585. factor</description>
  7586. <bitOffset>16</bitOffset>
  7587. <bitWidth>7</bitWidth>
  7588. </field>
  7589. <field>
  7590. <name>PREDIV_S</name>
  7591. <description>Synchronous prescaler
  7592. factor</description>
  7593. <bitOffset>0</bitOffset>
  7594. <bitWidth>16</bitWidth>
  7595. </field>
  7596. </fields>
  7597. </register>
  7598. <register>
  7599. <name>WUTR</name>
  7600. <displayName>WUTR</displayName>
  7601. <description>RTC wakeup timer register</description>
  7602. <addressOffset>0x14</addressOffset>
  7603. <size>0x20</size>
  7604. <access>read-write</access>
  7605. <resetValue>0x00000000</resetValue>
  7606. <fields>
  7607. <field>
  7608. <name>WUT</name>
  7609. <description>Wakeup auto-reload value
  7610. bits</description>
  7611. <bitOffset>0</bitOffset>
  7612. <bitWidth>16</bitWidth>
  7613. </field>
  7614. </fields>
  7615. </register>
  7616. <register>
  7617. <name>ALRMAR</name>
  7618. <displayName>ALRMAR</displayName>
  7619. <description>RTC alarm A register</description>
  7620. <addressOffset>0x1C</addressOffset>
  7621. <size>0x20</size>
  7622. <access>read-write</access>
  7623. <resetValue>0x00000000</resetValue>
  7624. <fields>
  7625. <field>
  7626. <name>MSK4</name>
  7627. <description>Alarm A date mask</description>
  7628. <bitOffset>31</bitOffset>
  7629. <bitWidth>1</bitWidth>
  7630. </field>
  7631. <field>
  7632. <name>WDSEL</name>
  7633. <description>Week day selection</description>
  7634. <bitOffset>30</bitOffset>
  7635. <bitWidth>1</bitWidth>
  7636. </field>
  7637. <field>
  7638. <name>DT</name>
  7639. <description>Date tens in BCD format.</description>
  7640. <bitOffset>28</bitOffset>
  7641. <bitWidth>2</bitWidth>
  7642. </field>
  7643. <field>
  7644. <name>DU</name>
  7645. <description>Date units or day in BCD
  7646. format.</description>
  7647. <bitOffset>24</bitOffset>
  7648. <bitWidth>4</bitWidth>
  7649. </field>
  7650. <field>
  7651. <name>MSK3</name>
  7652. <description>Alarm A hours mask</description>
  7653. <bitOffset>23</bitOffset>
  7654. <bitWidth>1</bitWidth>
  7655. </field>
  7656. <field>
  7657. <name>PM</name>
  7658. <description>AM/PM notation</description>
  7659. <bitOffset>22</bitOffset>
  7660. <bitWidth>1</bitWidth>
  7661. </field>
  7662. <field>
  7663. <name>HT</name>
  7664. <description>Hour tens in BCD format.</description>
  7665. <bitOffset>20</bitOffset>
  7666. <bitWidth>2</bitWidth>
  7667. </field>
  7668. <field>
  7669. <name>HU</name>
  7670. <description>Hour units in BCD format.</description>
  7671. <bitOffset>16</bitOffset>
  7672. <bitWidth>4</bitWidth>
  7673. </field>
  7674. <field>
  7675. <name>MSK2</name>
  7676. <description>Alarm A minutes mask</description>
  7677. <bitOffset>15</bitOffset>
  7678. <bitWidth>1</bitWidth>
  7679. </field>
  7680. <field>
  7681. <name>MNT</name>
  7682. <description>Minute tens in BCD format.</description>
  7683. <bitOffset>12</bitOffset>
  7684. <bitWidth>3</bitWidth>
  7685. </field>
  7686. <field>
  7687. <name>MNU</name>
  7688. <description>Minute units in BCD
  7689. format.</description>
  7690. <bitOffset>8</bitOffset>
  7691. <bitWidth>4</bitWidth>
  7692. </field>
  7693. <field>
  7694. <name>MSK1</name>
  7695. <description>Alarm A seconds mask</description>
  7696. <bitOffset>7</bitOffset>
  7697. <bitWidth>1</bitWidth>
  7698. </field>
  7699. <field>
  7700. <name>ST</name>
  7701. <description>Second tens in BCD format.</description>
  7702. <bitOffset>4</bitOffset>
  7703. <bitWidth>3</bitWidth>
  7704. </field>
  7705. <field>
  7706. <name>SU</name>
  7707. <description>Second units in BCD
  7708. format.</description>
  7709. <bitOffset>0</bitOffset>
  7710. <bitWidth>4</bitWidth>
  7711. </field>
  7712. </fields>
  7713. </register>
  7714. <register>
  7715. <name>ALRMBR</name>
  7716. <displayName>ALRMBR</displayName>
  7717. <description>RTC alarm B register</description>
  7718. <addressOffset>0x20</addressOffset>
  7719. <size>0x20</size>
  7720. <access>read-write</access>
  7721. <resetValue>0x00000000</resetValue>
  7722. <fields>
  7723. <field>
  7724. <name>MSK4</name>
  7725. <description>Alarm B date mask</description>
  7726. <bitOffset>31</bitOffset>
  7727. <bitWidth>1</bitWidth>
  7728. </field>
  7729. <field>
  7730. <name>WDSEL</name>
  7731. <description>Week day selection</description>
  7732. <bitOffset>30</bitOffset>
  7733. <bitWidth>1</bitWidth>
  7734. </field>
  7735. <field>
  7736. <name>DT</name>
  7737. <description>Date tens in BCD format</description>
  7738. <bitOffset>28</bitOffset>
  7739. <bitWidth>2</bitWidth>
  7740. </field>
  7741. <field>
  7742. <name>DU</name>
  7743. <description>Date units or day in BCD
  7744. format</description>
  7745. <bitOffset>24</bitOffset>
  7746. <bitWidth>4</bitWidth>
  7747. </field>
  7748. <field>
  7749. <name>MSK3</name>
  7750. <description>Alarm B hours mask</description>
  7751. <bitOffset>23</bitOffset>
  7752. <bitWidth>1</bitWidth>
  7753. </field>
  7754. <field>
  7755. <name>PM</name>
  7756. <description>AM/PM notation</description>
  7757. <bitOffset>22</bitOffset>
  7758. <bitWidth>1</bitWidth>
  7759. </field>
  7760. <field>
  7761. <name>HT</name>
  7762. <description>Hour tens in BCD format</description>
  7763. <bitOffset>20</bitOffset>
  7764. <bitWidth>2</bitWidth>
  7765. </field>
  7766. <field>
  7767. <name>HU</name>
  7768. <description>Hour units in BCD format</description>
  7769. <bitOffset>16</bitOffset>
  7770. <bitWidth>4</bitWidth>
  7771. </field>
  7772. <field>
  7773. <name>MSK2</name>
  7774. <description>Alarm B minutes mask</description>
  7775. <bitOffset>15</bitOffset>
  7776. <bitWidth>1</bitWidth>
  7777. </field>
  7778. <field>
  7779. <name>MNT</name>
  7780. <description>Minute tens in BCD format</description>
  7781. <bitOffset>12</bitOffset>
  7782. <bitWidth>3</bitWidth>
  7783. </field>
  7784. <field>
  7785. <name>MNU</name>
  7786. <description>Minute units in BCD format</description>
  7787. <bitOffset>8</bitOffset>
  7788. <bitWidth>4</bitWidth>
  7789. </field>
  7790. <field>
  7791. <name>MSK1</name>
  7792. <description>Alarm B seconds mask</description>
  7793. <bitOffset>7</bitOffset>
  7794. <bitWidth>1</bitWidth>
  7795. </field>
  7796. <field>
  7797. <name>ST</name>
  7798. <description>Second tens in BCD format</description>
  7799. <bitOffset>4</bitOffset>
  7800. <bitWidth>3</bitWidth>
  7801. </field>
  7802. <field>
  7803. <name>SU</name>
  7804. <description>Second units in BCD format</description>
  7805. <bitOffset>0</bitOffset>
  7806. <bitWidth>4</bitWidth>
  7807. </field>
  7808. </fields>
  7809. </register>
  7810. <register>
  7811. <name>WPR</name>
  7812. <displayName>WPR</displayName>
  7813. <description>write protection register</description>
  7814. <addressOffset>0x24</addressOffset>
  7815. <size>0x20</size>
  7816. <access>write-only</access>
  7817. <resetValue>0x00000000</resetValue>
  7818. <fields>
  7819. <field>
  7820. <name>KEY</name>
  7821. <description>Write protection key</description>
  7822. <bitOffset>0</bitOffset>
  7823. <bitWidth>8</bitWidth>
  7824. </field>
  7825. </fields>
  7826. </register>
  7827. <register>
  7828. <name>SSR</name>
  7829. <displayName>SSR</displayName>
  7830. <description>RTC sub second register</description>
  7831. <addressOffset>0x28</addressOffset>
  7832. <size>0x20</size>
  7833. <access>read-only</access>
  7834. <resetValue>0x00000000</resetValue>
  7835. <fields>
  7836. <field>
  7837. <name>SS</name>
  7838. <description>Sub second value</description>
  7839. <bitOffset>0</bitOffset>
  7840. <bitWidth>16</bitWidth>
  7841. </field>
  7842. </fields>
  7843. </register>
  7844. <register>
  7845. <name>SHIFTR</name>
  7846. <displayName>SHIFTR</displayName>
  7847. <description>RTC shift control register</description>
  7848. <addressOffset>0x2C</addressOffset>
  7849. <size>0x20</size>
  7850. <access>write-only</access>
  7851. <resetValue>0x00000000</resetValue>
  7852. <fields>
  7853. <field>
  7854. <name>ADD1S</name>
  7855. <description>Add one second</description>
  7856. <bitOffset>31</bitOffset>
  7857. <bitWidth>1</bitWidth>
  7858. </field>
  7859. <field>
  7860. <name>SUBFS</name>
  7861. <description>Subtract a fraction of a
  7862. second</description>
  7863. <bitOffset>0</bitOffset>
  7864. <bitWidth>15</bitWidth>
  7865. </field>
  7866. </fields>
  7867. </register>
  7868. <register>
  7869. <name>TSTR</name>
  7870. <displayName>TSTR</displayName>
  7871. <description>RTC timestamp time register</description>
  7872. <addressOffset>0x30</addressOffset>
  7873. <size>0x20</size>
  7874. <access>read-only</access>
  7875. <resetValue>0x00000000</resetValue>
  7876. <fields>
  7877. <field>
  7878. <name>PM</name>
  7879. <description>AM/PM notation</description>
  7880. <bitOffset>22</bitOffset>
  7881. <bitWidth>1</bitWidth>
  7882. </field>
  7883. <field>
  7884. <name>HT</name>
  7885. <description>Hour tens in BCD format.</description>
  7886. <bitOffset>20</bitOffset>
  7887. <bitWidth>2</bitWidth>
  7888. </field>
  7889. <field>
  7890. <name>HU</name>
  7891. <description>Hour units in BCD format.</description>
  7892. <bitOffset>16</bitOffset>
  7893. <bitWidth>4</bitWidth>
  7894. </field>
  7895. <field>
  7896. <name>MNT</name>
  7897. <description>Minute tens in BCD format.</description>
  7898. <bitOffset>12</bitOffset>
  7899. <bitWidth>3</bitWidth>
  7900. </field>
  7901. <field>
  7902. <name>MNU</name>
  7903. <description>Minute units in BCD
  7904. format.</description>
  7905. <bitOffset>8</bitOffset>
  7906. <bitWidth>4</bitWidth>
  7907. </field>
  7908. <field>
  7909. <name>ST</name>
  7910. <description>Second tens in BCD format.</description>
  7911. <bitOffset>4</bitOffset>
  7912. <bitWidth>3</bitWidth>
  7913. </field>
  7914. <field>
  7915. <name>SU</name>
  7916. <description>Second units in BCD
  7917. format.</description>
  7918. <bitOffset>0</bitOffset>
  7919. <bitWidth>4</bitWidth>
  7920. </field>
  7921. </fields>
  7922. </register>
  7923. <register>
  7924. <name>TSDR</name>
  7925. <displayName>TSDR</displayName>
  7926. <description>RTC timestamp date register</description>
  7927. <addressOffset>0x34</addressOffset>
  7928. <size>0x20</size>
  7929. <access>read-only</access>
  7930. <resetValue>0x00000000</resetValue>
  7931. <fields>
  7932. <field>
  7933. <name>WDU</name>
  7934. <description>Week day units</description>
  7935. <bitOffset>13</bitOffset>
  7936. <bitWidth>3</bitWidth>
  7937. </field>
  7938. <field>
  7939. <name>MT</name>
  7940. <description>Month tens in BCD format</description>
  7941. <bitOffset>12</bitOffset>
  7942. <bitWidth>1</bitWidth>
  7943. </field>
  7944. <field>
  7945. <name>MU</name>
  7946. <description>Month units in BCD format</description>
  7947. <bitOffset>8</bitOffset>
  7948. <bitWidth>4</bitWidth>
  7949. </field>
  7950. <field>
  7951. <name>DT</name>
  7952. <description>Date tens in BCD format</description>
  7953. <bitOffset>4</bitOffset>
  7954. <bitWidth>2</bitWidth>
  7955. </field>
  7956. <field>
  7957. <name>DU</name>
  7958. <description>Date units in BCD format</description>
  7959. <bitOffset>0</bitOffset>
  7960. <bitWidth>4</bitWidth>
  7961. </field>
  7962. </fields>
  7963. </register>
  7964. <register>
  7965. <name>TSSSR</name>
  7966. <displayName>TSSSR</displayName>
  7967. <description>RTC time-stamp sub second
  7968. register</description>
  7969. <addressOffset>0x38</addressOffset>
  7970. <size>0x20</size>
  7971. <access>read-only</access>
  7972. <resetValue>0x00000000</resetValue>
  7973. <fields>
  7974. <field>
  7975. <name>SS</name>
  7976. <description>Sub second value</description>
  7977. <bitOffset>0</bitOffset>
  7978. <bitWidth>16</bitWidth>
  7979. </field>
  7980. </fields>
  7981. </register>
  7982. <register>
  7983. <name>CALR</name>
  7984. <displayName>CALR</displayName>
  7985. <description>RTC calibration register</description>
  7986. <addressOffset>0x3C</addressOffset>
  7987. <size>0x20</size>
  7988. <access>read-write</access>
  7989. <resetValue>0x00000000</resetValue>
  7990. <fields>
  7991. <field>
  7992. <name>CALP</name>
  7993. <description>Use an 8-second calibration cycle
  7994. period</description>
  7995. <bitOffset>15</bitOffset>
  7996. <bitWidth>1</bitWidth>
  7997. </field>
  7998. <field>
  7999. <name>CALW8</name>
  8000. <description>Use a 16-second calibration cycle
  8001. period</description>
  8002. <bitOffset>14</bitOffset>
  8003. <bitWidth>1</bitWidth>
  8004. </field>
  8005. <field>
  8006. <name>CALW16</name>
  8007. <description>Reserved</description>
  8008. <bitOffset>13</bitOffset>
  8009. <bitWidth>1</bitWidth>
  8010. </field>
  8011. <field>
  8012. <name>CALM</name>
  8013. <description>Calibration minus</description>
  8014. <bitOffset>0</bitOffset>
  8015. <bitWidth>9</bitWidth>
  8016. </field>
  8017. </fields>
  8018. </register>
  8019. <register>
  8020. <name>TAMPCR</name>
  8021. <displayName>TAMPCR</displayName>
  8022. <description>RTC tamper configuration
  8023. register</description>
  8024. <addressOffset>0x40</addressOffset>
  8025. <size>0x20</size>
  8026. <access>read-write</access>
  8027. <resetValue>0x00000000</resetValue>
  8028. <fields>
  8029. <field>
  8030. <name>TAMP2MF</name>
  8031. <description>Tamper 2 mask flag</description>
  8032. <bitOffset>21</bitOffset>
  8033. <bitWidth>1</bitWidth>
  8034. </field>
  8035. <field>
  8036. <name>TAMP2NOERASE</name>
  8037. <description>Tamper 2 no erase</description>
  8038. <bitOffset>20</bitOffset>
  8039. <bitWidth>1</bitWidth>
  8040. </field>
  8041. <field>
  8042. <name>TAMP2IE</name>
  8043. <description>Tamper 2 interrupt enable</description>
  8044. <bitOffset>19</bitOffset>
  8045. <bitWidth>1</bitWidth>
  8046. </field>
  8047. <field>
  8048. <name>TAMP1MF</name>
  8049. <description>Tamper 1 mask flag</description>
  8050. <bitOffset>18</bitOffset>
  8051. <bitWidth>1</bitWidth>
  8052. </field>
  8053. <field>
  8054. <name>TAMP1NOERASE</name>
  8055. <description>Tamper 1 no erase</description>
  8056. <bitOffset>17</bitOffset>
  8057. <bitWidth>1</bitWidth>
  8058. </field>
  8059. <field>
  8060. <name>TAMP1IE</name>
  8061. <description>Tamper 1 interrupt enable</description>
  8062. <bitOffset>16</bitOffset>
  8063. <bitWidth>1</bitWidth>
  8064. </field>
  8065. <field>
  8066. <name>TAMPPUDIS</name>
  8067. <description>RTC_TAMPx pull-up disable</description>
  8068. <bitOffset>15</bitOffset>
  8069. <bitWidth>1</bitWidth>
  8070. </field>
  8071. <field>
  8072. <name>TAMPPRCH</name>
  8073. <description>RTC_TAMPx precharge
  8074. duration</description>
  8075. <bitOffset>13</bitOffset>
  8076. <bitWidth>2</bitWidth>
  8077. </field>
  8078. <field>
  8079. <name>TAMPFLT</name>
  8080. <description>RTC_TAMPx filter count</description>
  8081. <bitOffset>11</bitOffset>
  8082. <bitWidth>2</bitWidth>
  8083. </field>
  8084. <field>
  8085. <name>TAMPFREQ</name>
  8086. <description>Tamper sampling frequency</description>
  8087. <bitOffset>8</bitOffset>
  8088. <bitWidth>3</bitWidth>
  8089. </field>
  8090. <field>
  8091. <name>TAMPTS</name>
  8092. <description>Activate timestamp on tamper detection
  8093. event</description>
  8094. <bitOffset>7</bitOffset>
  8095. <bitWidth>1</bitWidth>
  8096. </field>
  8097. <field>
  8098. <name>TAMP2_TRG</name>
  8099. <description>Active level for RTC_TAMP2
  8100. input</description>
  8101. <bitOffset>4</bitOffset>
  8102. <bitWidth>1</bitWidth>
  8103. </field>
  8104. <field>
  8105. <name>TAMP2E</name>
  8106. <description>RTC_TAMP2 input detection
  8107. enable</description>
  8108. <bitOffset>3</bitOffset>
  8109. <bitWidth>1</bitWidth>
  8110. </field>
  8111. <field>
  8112. <name>TAMPIE</name>
  8113. <description>Tamper interrupt enable</description>
  8114. <bitOffset>2</bitOffset>
  8115. <bitWidth>1</bitWidth>
  8116. </field>
  8117. <field>
  8118. <name>TAMP1TRG</name>
  8119. <description>Active level for RTC_TAMP1
  8120. input</description>
  8121. <bitOffset>1</bitOffset>
  8122. <bitWidth>1</bitWidth>
  8123. </field>
  8124. <field>
  8125. <name>TAMP1E</name>
  8126. <description>RTC_TAMP1 input detection
  8127. enable</description>
  8128. <bitOffset>0</bitOffset>
  8129. <bitWidth>1</bitWidth>
  8130. </field>
  8131. </fields>
  8132. </register>
  8133. <register>
  8134. <name>ALRMASSR</name>
  8135. <displayName>ALRMASSR</displayName>
  8136. <description>RTC alarm A sub second
  8137. register</description>
  8138. <addressOffset>0x44</addressOffset>
  8139. <size>0x20</size>
  8140. <access>read-write</access>
  8141. <resetValue>0x00000000</resetValue>
  8142. <fields>
  8143. <field>
  8144. <name>MASKSS</name>
  8145. <description>Mask the most-significant bits starting
  8146. at this bit</description>
  8147. <bitOffset>24</bitOffset>
  8148. <bitWidth>4</bitWidth>
  8149. </field>
  8150. <field>
  8151. <name>SS</name>
  8152. <description>Sub seconds value</description>
  8153. <bitOffset>0</bitOffset>
  8154. <bitWidth>15</bitWidth>
  8155. </field>
  8156. </fields>
  8157. </register>
  8158. <register>
  8159. <name>ALRMBSSR</name>
  8160. <displayName>ALRMBSSR</displayName>
  8161. <description>RTC alarm B sub second
  8162. register</description>
  8163. <addressOffset>0x48</addressOffset>
  8164. <size>0x20</size>
  8165. <access>read-write</access>
  8166. <resetValue>0x00000000</resetValue>
  8167. <fields>
  8168. <field>
  8169. <name>MASKSS</name>
  8170. <description>Mask the most-significant bits starting
  8171. at this bit</description>
  8172. <bitOffset>24</bitOffset>
  8173. <bitWidth>4</bitWidth>
  8174. </field>
  8175. <field>
  8176. <name>SS</name>
  8177. <description>Sub seconds value</description>
  8178. <bitOffset>0</bitOffset>
  8179. <bitWidth>15</bitWidth>
  8180. </field>
  8181. </fields>
  8182. </register>
  8183. <register>
  8184. <name>OR</name>
  8185. <displayName>OR</displayName>
  8186. <description>option register</description>
  8187. <addressOffset>0x4C</addressOffset>
  8188. <size>0x20</size>
  8189. <access>read-write</access>
  8190. <resetValue>0x00000000</resetValue>
  8191. <fields>
  8192. <field>
  8193. <name>RTC_OUT_RMP</name>
  8194. <description>RTC_ALARM on PC13 output
  8195. type</description>
  8196. <bitOffset>1</bitOffset>
  8197. <bitWidth>1</bitWidth>
  8198. </field>
  8199. <field>
  8200. <name>RTC_ALARM_TYPE</name>
  8201. <description>RTC_ALARM on PC13 output
  8202. type</description>
  8203. <bitOffset>0</bitOffset>
  8204. <bitWidth>1</bitWidth>
  8205. </field>
  8206. </fields>
  8207. </register>
  8208. <register>
  8209. <name>BKP0R</name>
  8210. <displayName>BKP0R</displayName>
  8211. <description>RTC backup registers</description>
  8212. <addressOffset>0x50</addressOffset>
  8213. <size>0x20</size>
  8214. <access>read-write</access>
  8215. <resetValue>0x00000000</resetValue>
  8216. <fields>
  8217. <field>
  8218. <name>BKP</name>
  8219. <description>BKP</description>
  8220. <bitOffset>0</bitOffset>
  8221. <bitWidth>32</bitWidth>
  8222. </field>
  8223. </fields>
  8224. </register>
  8225. <register>
  8226. <name>BKP1R</name>
  8227. <displayName>BKP1R</displayName>
  8228. <description>RTC backup registers</description>
  8229. <addressOffset>0x54</addressOffset>
  8230. <size>0x20</size>
  8231. <access>read-write</access>
  8232. <resetValue>0x00000000</resetValue>
  8233. <fields>
  8234. <field>
  8235. <name>BKP</name>
  8236. <description>BKP</description>
  8237. <bitOffset>0</bitOffset>
  8238. <bitWidth>32</bitWidth>
  8239. </field>
  8240. </fields>
  8241. </register>
  8242. <register>
  8243. <name>BKP2R</name>
  8244. <displayName>BKP2R</displayName>
  8245. <description>RTC backup registers</description>
  8246. <addressOffset>0x58</addressOffset>
  8247. <size>0x20</size>
  8248. <access>read-write</access>
  8249. <resetValue>0x00000000</resetValue>
  8250. <fields>
  8251. <field>
  8252. <name>BKP</name>
  8253. <description>BKP</description>
  8254. <bitOffset>0</bitOffset>
  8255. <bitWidth>32</bitWidth>
  8256. </field>
  8257. </fields>
  8258. </register>
  8259. <register>
  8260. <name>BKP3R</name>
  8261. <displayName>BKP3R</displayName>
  8262. <description>RTC backup registers</description>
  8263. <addressOffset>0x5C</addressOffset>
  8264. <size>0x20</size>
  8265. <access>read-write</access>
  8266. <resetValue>0x00000000</resetValue>
  8267. <fields>
  8268. <field>
  8269. <name>BKP</name>
  8270. <description>BKP</description>
  8271. <bitOffset>0</bitOffset>
  8272. <bitWidth>32</bitWidth>
  8273. </field>
  8274. </fields>
  8275. </register>
  8276. <register>
  8277. <name>BKP4R</name>
  8278. <displayName>BKP4R</displayName>
  8279. <description>RTC backup registers</description>
  8280. <addressOffset>0x60</addressOffset>
  8281. <size>0x20</size>
  8282. <access>read-write</access>
  8283. <resetValue>0x00000000</resetValue>
  8284. <fields>
  8285. <field>
  8286. <name>BKP</name>
  8287. <description>BKP</description>
  8288. <bitOffset>0</bitOffset>
  8289. <bitWidth>32</bitWidth>
  8290. </field>
  8291. </fields>
  8292. </register>
  8293. </registers>
  8294. </peripheral>
  8295. <peripheral>
  8296. <name>USART1</name>
  8297. <description>Universal synchronous asynchronous receiver
  8298. transmitter</description>
  8299. <groupName>USART</groupName>
  8300. <baseAddress>0x40013800</baseAddress>
  8301. <addressBlock>
  8302. <offset>0x0</offset>
  8303. <size>0x400</size>
  8304. <usage>registers</usage>
  8305. </addressBlock>
  8306. <interrupt>
  8307. <name>USART1</name>
  8308. <description>USART1 global interrupt</description>
  8309. <value>27</value>
  8310. </interrupt>
  8311. <registers>
  8312. <register>
  8313. <name>CR1</name>
  8314. <displayName>CR1</displayName>
  8315. <description>Control register 1</description>
  8316. <addressOffset>0x0</addressOffset>
  8317. <size>0x20</size>
  8318. <access>read-write</access>
  8319. <resetValue>0x0000</resetValue>
  8320. <fields>
  8321. <field>
  8322. <name>M1</name>
  8323. <description>Word length</description>
  8324. <bitOffset>28</bitOffset>
  8325. <bitWidth>1</bitWidth>
  8326. </field>
  8327. <field>
  8328. <name>EOBIE</name>
  8329. <description>End of Block interrupt
  8330. enable</description>
  8331. <bitOffset>27</bitOffset>
  8332. <bitWidth>1</bitWidth>
  8333. </field>
  8334. <field>
  8335. <name>RTOIE</name>
  8336. <description>Receiver timeout interrupt
  8337. enable</description>
  8338. <bitOffset>26</bitOffset>
  8339. <bitWidth>1</bitWidth>
  8340. </field>
  8341. <field>
  8342. <name>DEAT4</name>
  8343. <description>Driver Enable assertion
  8344. time</description>
  8345. <bitOffset>25</bitOffset>
  8346. <bitWidth>1</bitWidth>
  8347. </field>
  8348. <field>
  8349. <name>DEAT3</name>
  8350. <description>DEAT3</description>
  8351. <bitOffset>24</bitOffset>
  8352. <bitWidth>1</bitWidth>
  8353. </field>
  8354. <field>
  8355. <name>DEAT2</name>
  8356. <description>DEAT2</description>
  8357. <bitOffset>23</bitOffset>
  8358. <bitWidth>1</bitWidth>
  8359. </field>
  8360. <field>
  8361. <name>DEAT1</name>
  8362. <description>DEAT1</description>
  8363. <bitOffset>22</bitOffset>
  8364. <bitWidth>1</bitWidth>
  8365. </field>
  8366. <field>
  8367. <name>DEAT0</name>
  8368. <description>DEAT0</description>
  8369. <bitOffset>21</bitOffset>
  8370. <bitWidth>1</bitWidth>
  8371. </field>
  8372. <field>
  8373. <name>DEDT4</name>
  8374. <description>Driver Enable de-assertion
  8375. time</description>
  8376. <bitOffset>20</bitOffset>
  8377. <bitWidth>1</bitWidth>
  8378. </field>
  8379. <field>
  8380. <name>DEDT3</name>
  8381. <description>DEDT3</description>
  8382. <bitOffset>19</bitOffset>
  8383. <bitWidth>1</bitWidth>
  8384. </field>
  8385. <field>
  8386. <name>DEDT2</name>
  8387. <description>DEDT2</description>
  8388. <bitOffset>18</bitOffset>
  8389. <bitWidth>1</bitWidth>
  8390. </field>
  8391. <field>
  8392. <name>DEDT1</name>
  8393. <description>DEDT1</description>
  8394. <bitOffset>17</bitOffset>
  8395. <bitWidth>1</bitWidth>
  8396. </field>
  8397. <field>
  8398. <name>DEDT0</name>
  8399. <description>DEDT0</description>
  8400. <bitOffset>16</bitOffset>
  8401. <bitWidth>1</bitWidth>
  8402. </field>
  8403. <field>
  8404. <name>OVER8</name>
  8405. <description>Oversampling mode</description>
  8406. <bitOffset>15</bitOffset>
  8407. <bitWidth>1</bitWidth>
  8408. </field>
  8409. <field>
  8410. <name>CMIE</name>
  8411. <description>Character match interrupt
  8412. enable</description>
  8413. <bitOffset>14</bitOffset>
  8414. <bitWidth>1</bitWidth>
  8415. </field>
  8416. <field>
  8417. <name>MME</name>
  8418. <description>Mute mode enable</description>
  8419. <bitOffset>13</bitOffset>
  8420. <bitWidth>1</bitWidth>
  8421. </field>
  8422. <field>
  8423. <name>M0</name>
  8424. <description>Word length</description>
  8425. <bitOffset>12</bitOffset>
  8426. <bitWidth>1</bitWidth>
  8427. </field>
  8428. <field>
  8429. <name>WAKE</name>
  8430. <description>Receiver wakeup method</description>
  8431. <bitOffset>11</bitOffset>
  8432. <bitWidth>1</bitWidth>
  8433. </field>
  8434. <field>
  8435. <name>PCE</name>
  8436. <description>Parity control enable</description>
  8437. <bitOffset>10</bitOffset>
  8438. <bitWidth>1</bitWidth>
  8439. </field>
  8440. <field>
  8441. <name>PS</name>
  8442. <description>Parity selection</description>
  8443. <bitOffset>9</bitOffset>
  8444. <bitWidth>1</bitWidth>
  8445. </field>
  8446. <field>
  8447. <name>PEIE</name>
  8448. <description>PE interrupt enable</description>
  8449. <bitOffset>8</bitOffset>
  8450. <bitWidth>1</bitWidth>
  8451. </field>
  8452. <field>
  8453. <name>TXEIE</name>
  8454. <description>interrupt enable</description>
  8455. <bitOffset>7</bitOffset>
  8456. <bitWidth>1</bitWidth>
  8457. </field>
  8458. <field>
  8459. <name>TCIE</name>
  8460. <description>Transmission complete interrupt
  8461. enable</description>
  8462. <bitOffset>6</bitOffset>
  8463. <bitWidth>1</bitWidth>
  8464. </field>
  8465. <field>
  8466. <name>RXNEIE</name>
  8467. <description>RXNE interrupt enable</description>
  8468. <bitOffset>5</bitOffset>
  8469. <bitWidth>1</bitWidth>
  8470. </field>
  8471. <field>
  8472. <name>IDLEIE</name>
  8473. <description>IDLE interrupt enable</description>
  8474. <bitOffset>4</bitOffset>
  8475. <bitWidth>1</bitWidth>
  8476. </field>
  8477. <field>
  8478. <name>TE</name>
  8479. <description>Transmitter enable</description>
  8480. <bitOffset>3</bitOffset>
  8481. <bitWidth>1</bitWidth>
  8482. </field>
  8483. <field>
  8484. <name>RE</name>
  8485. <description>Receiver enable</description>
  8486. <bitOffset>2</bitOffset>
  8487. <bitWidth>1</bitWidth>
  8488. </field>
  8489. <field>
  8490. <name>UESM</name>
  8491. <description>USART enable in Stop mode</description>
  8492. <bitOffset>1</bitOffset>
  8493. <bitWidth>1</bitWidth>
  8494. </field>
  8495. <field>
  8496. <name>UE</name>
  8497. <description>USART enable</description>
  8498. <bitOffset>0</bitOffset>
  8499. <bitWidth>1</bitWidth>
  8500. </field>
  8501. </fields>
  8502. </register>
  8503. <register>
  8504. <name>CR2</name>
  8505. <displayName>CR2</displayName>
  8506. <description>Control register 2</description>
  8507. <addressOffset>0x4</addressOffset>
  8508. <size>0x20</size>
  8509. <access>read-write</access>
  8510. <resetValue>0x0000</resetValue>
  8511. <fields>
  8512. <field>
  8513. <name>ADD4_7</name>
  8514. <description>Address of the USART node</description>
  8515. <bitOffset>28</bitOffset>
  8516. <bitWidth>4</bitWidth>
  8517. </field>
  8518. <field>
  8519. <name>ADD0_3</name>
  8520. <description>Address of the USART node</description>
  8521. <bitOffset>24</bitOffset>
  8522. <bitWidth>4</bitWidth>
  8523. </field>
  8524. <field>
  8525. <name>RTOEN</name>
  8526. <description>Receiver timeout enable</description>
  8527. <bitOffset>23</bitOffset>
  8528. <bitWidth>1</bitWidth>
  8529. </field>
  8530. <field>
  8531. <name>ABRMOD1</name>
  8532. <description>Auto baud rate mode</description>
  8533. <bitOffset>22</bitOffset>
  8534. <bitWidth>1</bitWidth>
  8535. </field>
  8536. <field>
  8537. <name>ABRMOD0</name>
  8538. <description>ABRMOD0</description>
  8539. <bitOffset>21</bitOffset>
  8540. <bitWidth>1</bitWidth>
  8541. </field>
  8542. <field>
  8543. <name>ABREN</name>
  8544. <description>Auto baud rate enable</description>
  8545. <bitOffset>20</bitOffset>
  8546. <bitWidth>1</bitWidth>
  8547. </field>
  8548. <field>
  8549. <name>MSBFIRST</name>
  8550. <description>Most significant bit first</description>
  8551. <bitOffset>19</bitOffset>
  8552. <bitWidth>1</bitWidth>
  8553. </field>
  8554. <field>
  8555. <name>TAINV</name>
  8556. <description>Binary data inversion</description>
  8557. <bitOffset>18</bitOffset>
  8558. <bitWidth>1</bitWidth>
  8559. </field>
  8560. <field>
  8561. <name>TXINV</name>
  8562. <description>TX pin active level
  8563. inversion</description>
  8564. <bitOffset>17</bitOffset>
  8565. <bitWidth>1</bitWidth>
  8566. </field>
  8567. <field>
  8568. <name>RXINV</name>
  8569. <description>RX pin active level
  8570. inversion</description>
  8571. <bitOffset>16</bitOffset>
  8572. <bitWidth>1</bitWidth>
  8573. </field>
  8574. <field>
  8575. <name>SWAP</name>
  8576. <description>Swap TX/RX pins</description>
  8577. <bitOffset>15</bitOffset>
  8578. <bitWidth>1</bitWidth>
  8579. </field>
  8580. <field>
  8581. <name>LINEN</name>
  8582. <description>LIN mode enable</description>
  8583. <bitOffset>14</bitOffset>
  8584. <bitWidth>1</bitWidth>
  8585. </field>
  8586. <field>
  8587. <name>STOP</name>
  8588. <description>STOP bits</description>
  8589. <bitOffset>12</bitOffset>
  8590. <bitWidth>2</bitWidth>
  8591. </field>
  8592. <field>
  8593. <name>CLKEN</name>
  8594. <description>Clock enable</description>
  8595. <bitOffset>11</bitOffset>
  8596. <bitWidth>1</bitWidth>
  8597. </field>
  8598. <field>
  8599. <name>CPOL</name>
  8600. <description>Clock polarity</description>
  8601. <bitOffset>10</bitOffset>
  8602. <bitWidth>1</bitWidth>
  8603. </field>
  8604. <field>
  8605. <name>CPHA</name>
  8606. <description>Clock phase</description>
  8607. <bitOffset>9</bitOffset>
  8608. <bitWidth>1</bitWidth>
  8609. </field>
  8610. <field>
  8611. <name>LBCL</name>
  8612. <description>Last bit clock pulse</description>
  8613. <bitOffset>8</bitOffset>
  8614. <bitWidth>1</bitWidth>
  8615. </field>
  8616. <field>
  8617. <name>LBDIE</name>
  8618. <description>LIN break detection interrupt
  8619. enable</description>
  8620. <bitOffset>6</bitOffset>
  8621. <bitWidth>1</bitWidth>
  8622. </field>
  8623. <field>
  8624. <name>LBDL</name>
  8625. <description>LIN break detection length</description>
  8626. <bitOffset>5</bitOffset>
  8627. <bitWidth>1</bitWidth>
  8628. </field>
  8629. <field>
  8630. <name>ADDM7</name>
  8631. <description>7-bit Address Detection/4-bit Address
  8632. Detection</description>
  8633. <bitOffset>4</bitOffset>
  8634. <bitWidth>1</bitWidth>
  8635. </field>
  8636. </fields>
  8637. </register>
  8638. <register>
  8639. <name>CR3</name>
  8640. <displayName>CR3</displayName>
  8641. <description>Control register 3</description>
  8642. <addressOffset>0x8</addressOffset>
  8643. <size>0x20</size>
  8644. <access>read-write</access>
  8645. <resetValue>0x0000</resetValue>
  8646. <fields>
  8647. <field>
  8648. <name>WUFIE</name>
  8649. <description>Wakeup from Stop mode interrupt
  8650. enable</description>
  8651. <bitOffset>22</bitOffset>
  8652. <bitWidth>1</bitWidth>
  8653. </field>
  8654. <field>
  8655. <name>WUS</name>
  8656. <description>Wakeup from Stop mode interrupt flag
  8657. selection</description>
  8658. <bitOffset>20</bitOffset>
  8659. <bitWidth>2</bitWidth>
  8660. </field>
  8661. <field>
  8662. <name>SCARCNT</name>
  8663. <description>Smartcard auto-retry count</description>
  8664. <bitOffset>17</bitOffset>
  8665. <bitWidth>3</bitWidth>
  8666. </field>
  8667. <field>
  8668. <name>DEP</name>
  8669. <description>Driver enable polarity
  8670. selection</description>
  8671. <bitOffset>15</bitOffset>
  8672. <bitWidth>1</bitWidth>
  8673. </field>
  8674. <field>
  8675. <name>DEM</name>
  8676. <description>Driver enable mode</description>
  8677. <bitOffset>14</bitOffset>
  8678. <bitWidth>1</bitWidth>
  8679. </field>
  8680. <field>
  8681. <name>DDRE</name>
  8682. <description>DMA Disable on Reception
  8683. Error</description>
  8684. <bitOffset>13</bitOffset>
  8685. <bitWidth>1</bitWidth>
  8686. </field>
  8687. <field>
  8688. <name>OVRDIS</name>
  8689. <description>Overrun Disable</description>
  8690. <bitOffset>12</bitOffset>
  8691. <bitWidth>1</bitWidth>
  8692. </field>
  8693. <field>
  8694. <name>ONEBIT</name>
  8695. <description>One sample bit method
  8696. enable</description>
  8697. <bitOffset>11</bitOffset>
  8698. <bitWidth>1</bitWidth>
  8699. </field>
  8700. <field>
  8701. <name>CTSIE</name>
  8702. <description>CTS interrupt enable</description>
  8703. <bitOffset>10</bitOffset>
  8704. <bitWidth>1</bitWidth>
  8705. </field>
  8706. <field>
  8707. <name>CTSE</name>
  8708. <description>CTS enable</description>
  8709. <bitOffset>9</bitOffset>
  8710. <bitWidth>1</bitWidth>
  8711. </field>
  8712. <field>
  8713. <name>RTSE</name>
  8714. <description>RTS enable</description>
  8715. <bitOffset>8</bitOffset>
  8716. <bitWidth>1</bitWidth>
  8717. </field>
  8718. <field>
  8719. <name>DMAT</name>
  8720. <description>DMA enable transmitter</description>
  8721. <bitOffset>7</bitOffset>
  8722. <bitWidth>1</bitWidth>
  8723. </field>
  8724. <field>
  8725. <name>DMAR</name>
  8726. <description>DMA enable receiver</description>
  8727. <bitOffset>6</bitOffset>
  8728. <bitWidth>1</bitWidth>
  8729. </field>
  8730. <field>
  8731. <name>SCEN</name>
  8732. <description>Smartcard mode enable</description>
  8733. <bitOffset>5</bitOffset>
  8734. <bitWidth>1</bitWidth>
  8735. </field>
  8736. <field>
  8737. <name>NACK</name>
  8738. <description>Smartcard NACK enable</description>
  8739. <bitOffset>4</bitOffset>
  8740. <bitWidth>1</bitWidth>
  8741. </field>
  8742. <field>
  8743. <name>HDSEL</name>
  8744. <description>Half-duplex selection</description>
  8745. <bitOffset>3</bitOffset>
  8746. <bitWidth>1</bitWidth>
  8747. </field>
  8748. <field>
  8749. <name>IRLP</name>
  8750. <description>Ir low-power</description>
  8751. <bitOffset>2</bitOffset>
  8752. <bitWidth>1</bitWidth>
  8753. </field>
  8754. <field>
  8755. <name>IREN</name>
  8756. <description>Ir mode enable</description>
  8757. <bitOffset>1</bitOffset>
  8758. <bitWidth>1</bitWidth>
  8759. </field>
  8760. <field>
  8761. <name>EIE</name>
  8762. <description>Error interrupt enable</description>
  8763. <bitOffset>0</bitOffset>
  8764. <bitWidth>1</bitWidth>
  8765. </field>
  8766. </fields>
  8767. </register>
  8768. <register>
  8769. <name>BRR</name>
  8770. <displayName>BRR</displayName>
  8771. <description>Baud rate register</description>
  8772. <addressOffset>0xC</addressOffset>
  8773. <size>0x20</size>
  8774. <access>read-write</access>
  8775. <resetValue>0x0000</resetValue>
  8776. <fields>
  8777. <field>
  8778. <name>DIV_Mantissa</name>
  8779. <description>DIV_Mantissa</description>
  8780. <bitOffset>4</bitOffset>
  8781. <bitWidth>12</bitWidth>
  8782. </field>
  8783. <field>
  8784. <name>DIV_Fraction</name>
  8785. <description>DIV_Fraction</description>
  8786. <bitOffset>0</bitOffset>
  8787. <bitWidth>4</bitWidth>
  8788. </field>
  8789. </fields>
  8790. </register>
  8791. <register>
  8792. <name>GTPR</name>
  8793. <displayName>GTPR</displayName>
  8794. <description>Guard time and prescaler
  8795. register</description>
  8796. <addressOffset>0x10</addressOffset>
  8797. <size>0x20</size>
  8798. <access>read-write</access>
  8799. <resetValue>0x0000</resetValue>
  8800. <fields>
  8801. <field>
  8802. <name>GT</name>
  8803. <description>Guard time value</description>
  8804. <bitOffset>8</bitOffset>
  8805. <bitWidth>8</bitWidth>
  8806. </field>
  8807. <field>
  8808. <name>PSC</name>
  8809. <description>Prescaler value</description>
  8810. <bitOffset>0</bitOffset>
  8811. <bitWidth>8</bitWidth>
  8812. </field>
  8813. </fields>
  8814. </register>
  8815. <register>
  8816. <name>RTOR</name>
  8817. <displayName>RTOR</displayName>
  8818. <description>Receiver timeout register</description>
  8819. <addressOffset>0x14</addressOffset>
  8820. <size>0x20</size>
  8821. <access>read-write</access>
  8822. <resetValue>0x0000</resetValue>
  8823. <fields>
  8824. <field>
  8825. <name>BLEN</name>
  8826. <description>Block Length</description>
  8827. <bitOffset>24</bitOffset>
  8828. <bitWidth>8</bitWidth>
  8829. </field>
  8830. <field>
  8831. <name>RTO</name>
  8832. <description>Receiver timeout value</description>
  8833. <bitOffset>0</bitOffset>
  8834. <bitWidth>24</bitWidth>
  8835. </field>
  8836. </fields>
  8837. </register>
  8838. <register>
  8839. <name>RQR</name>
  8840. <displayName>RQR</displayName>
  8841. <description>Request register</description>
  8842. <addressOffset>0x18</addressOffset>
  8843. <size>0x20</size>
  8844. <access>write-only</access>
  8845. <resetValue>0x0000</resetValue>
  8846. <fields>
  8847. <field>
  8848. <name>TXFRQ</name>
  8849. <description>Transmit data flush
  8850. request</description>
  8851. <bitOffset>4</bitOffset>
  8852. <bitWidth>1</bitWidth>
  8853. </field>
  8854. <field>
  8855. <name>RXFRQ</name>
  8856. <description>Receive data flush request</description>
  8857. <bitOffset>3</bitOffset>
  8858. <bitWidth>1</bitWidth>
  8859. </field>
  8860. <field>
  8861. <name>MMRQ</name>
  8862. <description>Mute mode request</description>
  8863. <bitOffset>2</bitOffset>
  8864. <bitWidth>1</bitWidth>
  8865. </field>
  8866. <field>
  8867. <name>SBKRQ</name>
  8868. <description>Send break request</description>
  8869. <bitOffset>1</bitOffset>
  8870. <bitWidth>1</bitWidth>
  8871. </field>
  8872. <field>
  8873. <name>ABRRQ</name>
  8874. <description>Auto baud rate request</description>
  8875. <bitOffset>0</bitOffset>
  8876. <bitWidth>1</bitWidth>
  8877. </field>
  8878. </fields>
  8879. </register>
  8880. <register>
  8881. <name>ISR</name>
  8882. <displayName>ISR</displayName>
  8883. <description>Interrupt &amp; status
  8884. register</description>
  8885. <addressOffset>0x1C</addressOffset>
  8886. <size>0x20</size>
  8887. <access>read-only</access>
  8888. <resetValue>0x00C0</resetValue>
  8889. <fields>
  8890. <field>
  8891. <name>REACK</name>
  8892. <description>REACK</description>
  8893. <bitOffset>22</bitOffset>
  8894. <bitWidth>1</bitWidth>
  8895. </field>
  8896. <field>
  8897. <name>TEACK</name>
  8898. <description>TEACK</description>
  8899. <bitOffset>21</bitOffset>
  8900. <bitWidth>1</bitWidth>
  8901. </field>
  8902. <field>
  8903. <name>WUF</name>
  8904. <description>WUF</description>
  8905. <bitOffset>20</bitOffset>
  8906. <bitWidth>1</bitWidth>
  8907. </field>
  8908. <field>
  8909. <name>RWU</name>
  8910. <description>RWU</description>
  8911. <bitOffset>19</bitOffset>
  8912. <bitWidth>1</bitWidth>
  8913. </field>
  8914. <field>
  8915. <name>SBKF</name>
  8916. <description>SBKF</description>
  8917. <bitOffset>18</bitOffset>
  8918. <bitWidth>1</bitWidth>
  8919. </field>
  8920. <field>
  8921. <name>CMF</name>
  8922. <description>CMF</description>
  8923. <bitOffset>17</bitOffset>
  8924. <bitWidth>1</bitWidth>
  8925. </field>
  8926. <field>
  8927. <name>BUSY</name>
  8928. <description>BUSY</description>
  8929. <bitOffset>16</bitOffset>
  8930. <bitWidth>1</bitWidth>
  8931. </field>
  8932. <field>
  8933. <name>ABRF</name>
  8934. <description>ABRF</description>
  8935. <bitOffset>15</bitOffset>
  8936. <bitWidth>1</bitWidth>
  8937. </field>
  8938. <field>
  8939. <name>ABRE</name>
  8940. <description>ABRE</description>
  8941. <bitOffset>14</bitOffset>
  8942. <bitWidth>1</bitWidth>
  8943. </field>
  8944. <field>
  8945. <name>EOBF</name>
  8946. <description>EOBF</description>
  8947. <bitOffset>12</bitOffset>
  8948. <bitWidth>1</bitWidth>
  8949. </field>
  8950. <field>
  8951. <name>RTOF</name>
  8952. <description>RTOF</description>
  8953. <bitOffset>11</bitOffset>
  8954. <bitWidth>1</bitWidth>
  8955. </field>
  8956. <field>
  8957. <name>CTS</name>
  8958. <description>CTS</description>
  8959. <bitOffset>10</bitOffset>
  8960. <bitWidth>1</bitWidth>
  8961. </field>
  8962. <field>
  8963. <name>CTSIF</name>
  8964. <description>CTSIF</description>
  8965. <bitOffset>9</bitOffset>
  8966. <bitWidth>1</bitWidth>
  8967. </field>
  8968. <field>
  8969. <name>LBDF</name>
  8970. <description>LBDF</description>
  8971. <bitOffset>8</bitOffset>
  8972. <bitWidth>1</bitWidth>
  8973. </field>
  8974. <field>
  8975. <name>TXE</name>
  8976. <description>TXE</description>
  8977. <bitOffset>7</bitOffset>
  8978. <bitWidth>1</bitWidth>
  8979. </field>
  8980. <field>
  8981. <name>TC</name>
  8982. <description>TC</description>
  8983. <bitOffset>6</bitOffset>
  8984. <bitWidth>1</bitWidth>
  8985. </field>
  8986. <field>
  8987. <name>RXNE</name>
  8988. <description>RXNE</description>
  8989. <bitOffset>5</bitOffset>
  8990. <bitWidth>1</bitWidth>
  8991. </field>
  8992. <field>
  8993. <name>IDLE</name>
  8994. <description>IDLE</description>
  8995. <bitOffset>4</bitOffset>
  8996. <bitWidth>1</bitWidth>
  8997. </field>
  8998. <field>
  8999. <name>ORE</name>
  9000. <description>ORE</description>
  9001. <bitOffset>3</bitOffset>
  9002. <bitWidth>1</bitWidth>
  9003. </field>
  9004. <field>
  9005. <name>NF</name>
  9006. <description>NF</description>
  9007. <bitOffset>2</bitOffset>
  9008. <bitWidth>1</bitWidth>
  9009. </field>
  9010. <field>
  9011. <name>FE</name>
  9012. <description>FE</description>
  9013. <bitOffset>1</bitOffset>
  9014. <bitWidth>1</bitWidth>
  9015. </field>
  9016. <field>
  9017. <name>PE</name>
  9018. <description>PE</description>
  9019. <bitOffset>0</bitOffset>
  9020. <bitWidth>1</bitWidth>
  9021. </field>
  9022. </fields>
  9023. </register>
  9024. <register>
  9025. <name>ICR</name>
  9026. <displayName>ICR</displayName>
  9027. <description>Interrupt flag clear register</description>
  9028. <addressOffset>0x20</addressOffset>
  9029. <size>0x20</size>
  9030. <access>write-only</access>
  9031. <resetValue>0x0000</resetValue>
  9032. <fields>
  9033. <field>
  9034. <name>WUCF</name>
  9035. <description>Wakeup from Stop mode clear
  9036. flag</description>
  9037. <bitOffset>20</bitOffset>
  9038. <bitWidth>1</bitWidth>
  9039. </field>
  9040. <field>
  9041. <name>CMCF</name>
  9042. <description>Character match clear flag</description>
  9043. <bitOffset>17</bitOffset>
  9044. <bitWidth>1</bitWidth>
  9045. </field>
  9046. <field>
  9047. <name>EOBCF</name>
  9048. <description>End of block clear flag</description>
  9049. <bitOffset>12</bitOffset>
  9050. <bitWidth>1</bitWidth>
  9051. </field>
  9052. <field>
  9053. <name>RTOCF</name>
  9054. <description>Receiver timeout clear
  9055. flag</description>
  9056. <bitOffset>11</bitOffset>
  9057. <bitWidth>1</bitWidth>
  9058. </field>
  9059. <field>
  9060. <name>CTSCF</name>
  9061. <description>CTS clear flag</description>
  9062. <bitOffset>9</bitOffset>
  9063. <bitWidth>1</bitWidth>
  9064. </field>
  9065. <field>
  9066. <name>LBDCF</name>
  9067. <description>LIN break detection clear
  9068. flag</description>
  9069. <bitOffset>8</bitOffset>
  9070. <bitWidth>1</bitWidth>
  9071. </field>
  9072. <field>
  9073. <name>TCCF</name>
  9074. <description>Transmission complete clear
  9075. flag</description>
  9076. <bitOffset>6</bitOffset>
  9077. <bitWidth>1</bitWidth>
  9078. </field>
  9079. <field>
  9080. <name>IDLECF</name>
  9081. <description>Idle line detected clear
  9082. flag</description>
  9083. <bitOffset>4</bitOffset>
  9084. <bitWidth>1</bitWidth>
  9085. </field>
  9086. <field>
  9087. <name>ORECF</name>
  9088. <description>Overrun error clear flag</description>
  9089. <bitOffset>3</bitOffset>
  9090. <bitWidth>1</bitWidth>
  9091. </field>
  9092. <field>
  9093. <name>NCF</name>
  9094. <description>Noise detected clear flag</description>
  9095. <bitOffset>2</bitOffset>
  9096. <bitWidth>1</bitWidth>
  9097. </field>
  9098. <field>
  9099. <name>FECF</name>
  9100. <description>Framing error clear flag</description>
  9101. <bitOffset>1</bitOffset>
  9102. <bitWidth>1</bitWidth>
  9103. </field>
  9104. <field>
  9105. <name>PECF</name>
  9106. <description>Parity error clear flag</description>
  9107. <bitOffset>0</bitOffset>
  9108. <bitWidth>1</bitWidth>
  9109. </field>
  9110. </fields>
  9111. </register>
  9112. <register>
  9113. <name>RDR</name>
  9114. <displayName>RDR</displayName>
  9115. <description>Receive data register</description>
  9116. <addressOffset>0x24</addressOffset>
  9117. <size>0x20</size>
  9118. <access>read-only</access>
  9119. <resetValue>0x0000</resetValue>
  9120. <fields>
  9121. <field>
  9122. <name>RDR</name>
  9123. <description>Receive data value</description>
  9124. <bitOffset>0</bitOffset>
  9125. <bitWidth>9</bitWidth>
  9126. </field>
  9127. </fields>
  9128. </register>
  9129. <register>
  9130. <name>TDR</name>
  9131. <displayName>TDR</displayName>
  9132. <description>Transmit data register</description>
  9133. <addressOffset>0x28</addressOffset>
  9134. <size>0x20</size>
  9135. <access>read-write</access>
  9136. <resetValue>0x0000</resetValue>
  9137. <fields>
  9138. <field>
  9139. <name>TDR</name>
  9140. <description>Transmit data value</description>
  9141. <bitOffset>0</bitOffset>
  9142. <bitWidth>9</bitWidth>
  9143. </field>
  9144. </fields>
  9145. </register>
  9146. </registers>
  9147. </peripheral>
  9148. <peripheral derivedFrom="USART1">
  9149. <name>USART2</name>
  9150. <baseAddress>0x40004400</baseAddress>
  9151. <interrupt>
  9152. <name>USART2</name>
  9153. <description>USART2 global interrupt</description>
  9154. <value>28</value>
  9155. </interrupt>
  9156. </peripheral>
  9157. <peripheral>
  9158. <name>TSC</name>
  9159. <description>Touch sensing controller</description>
  9160. <groupName>TSC</groupName>
  9161. <baseAddress>0x40024000</baseAddress>
  9162. <addressBlock>
  9163. <offset>0x0</offset>
  9164. <size>0x400</size>
  9165. <usage>registers</usage>
  9166. </addressBlock>
  9167. <interrupt>
  9168. <name>TSC</name>
  9169. <description>Touch sensing interrupt</description>
  9170. <value>8</value>
  9171. </interrupt>
  9172. <registers>
  9173. <register>
  9174. <name>CR</name>
  9175. <displayName>CR</displayName>
  9176. <description>control register</description>
  9177. <addressOffset>0x0</addressOffset>
  9178. <size>0x20</size>
  9179. <access>read-write</access>
  9180. <resetValue>0x00000000</resetValue>
  9181. <fields>
  9182. <field>
  9183. <name>CTPH</name>
  9184. <description>Charge transfer pulse high</description>
  9185. <bitOffset>28</bitOffset>
  9186. <bitWidth>4</bitWidth>
  9187. </field>
  9188. <field>
  9189. <name>CTPL</name>
  9190. <description>Charge transfer pulse low</description>
  9191. <bitOffset>24</bitOffset>
  9192. <bitWidth>4</bitWidth>
  9193. </field>
  9194. <field>
  9195. <name>SSD</name>
  9196. <description>Spread spectrum deviation</description>
  9197. <bitOffset>17</bitOffset>
  9198. <bitWidth>7</bitWidth>
  9199. </field>
  9200. <field>
  9201. <name>SSE</name>
  9202. <description>Spread spectrum enable</description>
  9203. <bitOffset>16</bitOffset>
  9204. <bitWidth>1</bitWidth>
  9205. </field>
  9206. <field>
  9207. <name>SSPSC</name>
  9208. <description>Spread spectrum prescaler</description>
  9209. <bitOffset>15</bitOffset>
  9210. <bitWidth>1</bitWidth>
  9211. </field>
  9212. <field>
  9213. <name>PGPSC</name>
  9214. <description>pulse generator prescaler</description>
  9215. <bitOffset>12</bitOffset>
  9216. <bitWidth>3</bitWidth>
  9217. </field>
  9218. <field>
  9219. <name>MCV</name>
  9220. <description>Max count value</description>
  9221. <bitOffset>5</bitOffset>
  9222. <bitWidth>3</bitWidth>
  9223. </field>
  9224. <field>
  9225. <name>IODEF</name>
  9226. <description>I/O Default mode</description>
  9227. <bitOffset>4</bitOffset>
  9228. <bitWidth>1</bitWidth>
  9229. </field>
  9230. <field>
  9231. <name>SYNCPOL</name>
  9232. <description>Synchronization pin
  9233. polarity</description>
  9234. <bitOffset>3</bitOffset>
  9235. <bitWidth>1</bitWidth>
  9236. </field>
  9237. <field>
  9238. <name>AM</name>
  9239. <description>Acquisition mode</description>
  9240. <bitOffset>2</bitOffset>
  9241. <bitWidth>1</bitWidth>
  9242. </field>
  9243. <field>
  9244. <name>START</name>
  9245. <description>Start a new acquisition</description>
  9246. <bitOffset>1</bitOffset>
  9247. <bitWidth>1</bitWidth>
  9248. </field>
  9249. <field>
  9250. <name>TSCE</name>
  9251. <description>Touch sensing controller
  9252. enable</description>
  9253. <bitOffset>0</bitOffset>
  9254. <bitWidth>1</bitWidth>
  9255. </field>
  9256. </fields>
  9257. </register>
  9258. <register>
  9259. <name>IER</name>
  9260. <displayName>IER</displayName>
  9261. <description>interrupt enable register</description>
  9262. <addressOffset>0x4</addressOffset>
  9263. <size>0x20</size>
  9264. <access>read-write</access>
  9265. <resetValue>0x00000000</resetValue>
  9266. <fields>
  9267. <field>
  9268. <name>MCEIE</name>
  9269. <description>Max count error interrupt
  9270. enable</description>
  9271. <bitOffset>1</bitOffset>
  9272. <bitWidth>1</bitWidth>
  9273. </field>
  9274. <field>
  9275. <name>EOAIE</name>
  9276. <description>End of acquisition interrupt
  9277. enable</description>
  9278. <bitOffset>0</bitOffset>
  9279. <bitWidth>1</bitWidth>
  9280. </field>
  9281. </fields>
  9282. </register>
  9283. <register>
  9284. <name>ICR</name>
  9285. <displayName>ICR</displayName>
  9286. <description>interrupt clear register</description>
  9287. <addressOffset>0x8</addressOffset>
  9288. <size>0x20</size>
  9289. <access>read-write</access>
  9290. <resetValue>0x00000000</resetValue>
  9291. <fields>
  9292. <field>
  9293. <name>MCEIC</name>
  9294. <description>Max count error interrupt
  9295. clear</description>
  9296. <bitOffset>1</bitOffset>
  9297. <bitWidth>1</bitWidth>
  9298. </field>
  9299. <field>
  9300. <name>EOAIC</name>
  9301. <description>End of acquisition interrupt
  9302. clear</description>
  9303. <bitOffset>0</bitOffset>
  9304. <bitWidth>1</bitWidth>
  9305. </field>
  9306. </fields>
  9307. </register>
  9308. <register>
  9309. <name>ISR</name>
  9310. <displayName>ISR</displayName>
  9311. <description>interrupt status register</description>
  9312. <addressOffset>0xC</addressOffset>
  9313. <size>0x20</size>
  9314. <access>read-write</access>
  9315. <resetValue>0x00000000</resetValue>
  9316. <fields>
  9317. <field>
  9318. <name>MCEF</name>
  9319. <description>Max count error flag</description>
  9320. <bitOffset>1</bitOffset>
  9321. <bitWidth>1</bitWidth>
  9322. </field>
  9323. <field>
  9324. <name>EOAF</name>
  9325. <description>End of acquisition flag</description>
  9326. <bitOffset>0</bitOffset>
  9327. <bitWidth>1</bitWidth>
  9328. </field>
  9329. </fields>
  9330. </register>
  9331. <register>
  9332. <name>IOHCR</name>
  9333. <displayName>IOHCR</displayName>
  9334. <description>I/O hysteresis control
  9335. register</description>
  9336. <addressOffset>0x10</addressOffset>
  9337. <size>0x20</size>
  9338. <access>read-write</access>
  9339. <resetValue>0xFFFFFFFF</resetValue>
  9340. <fields>
  9341. <field>
  9342. <name>G8_IO4</name>
  9343. <description>G8_IO4</description>
  9344. <bitOffset>31</bitOffset>
  9345. <bitWidth>1</bitWidth>
  9346. </field>
  9347. <field>
  9348. <name>G8_IO3</name>
  9349. <description>G8_IO3</description>
  9350. <bitOffset>30</bitOffset>
  9351. <bitWidth>1</bitWidth>
  9352. </field>
  9353. <field>
  9354. <name>G8_IO2</name>
  9355. <description>G8_IO2</description>
  9356. <bitOffset>29</bitOffset>
  9357. <bitWidth>1</bitWidth>
  9358. </field>
  9359. <field>
  9360. <name>G8_IO1</name>
  9361. <description>G8_IO1</description>
  9362. <bitOffset>28</bitOffset>
  9363. <bitWidth>1</bitWidth>
  9364. </field>
  9365. <field>
  9366. <name>G7_IO4</name>
  9367. <description>G7_IO4</description>
  9368. <bitOffset>27</bitOffset>
  9369. <bitWidth>1</bitWidth>
  9370. </field>
  9371. <field>
  9372. <name>G7_IO3</name>
  9373. <description>G7_IO3</description>
  9374. <bitOffset>26</bitOffset>
  9375. <bitWidth>1</bitWidth>
  9376. </field>
  9377. <field>
  9378. <name>G7_IO2</name>
  9379. <description>G7_IO2</description>
  9380. <bitOffset>25</bitOffset>
  9381. <bitWidth>1</bitWidth>
  9382. </field>
  9383. <field>
  9384. <name>G7_IO1</name>
  9385. <description>G7_IO1</description>
  9386. <bitOffset>24</bitOffset>
  9387. <bitWidth>1</bitWidth>
  9388. </field>
  9389. <field>
  9390. <name>G6_IO4</name>
  9391. <description>G6_IO4</description>
  9392. <bitOffset>23</bitOffset>
  9393. <bitWidth>1</bitWidth>
  9394. </field>
  9395. <field>
  9396. <name>G6_IO3</name>
  9397. <description>G6_IO3</description>
  9398. <bitOffset>22</bitOffset>
  9399. <bitWidth>1</bitWidth>
  9400. </field>
  9401. <field>
  9402. <name>G6_IO2</name>
  9403. <description>G6_IO2</description>
  9404. <bitOffset>21</bitOffset>
  9405. <bitWidth>1</bitWidth>
  9406. </field>
  9407. <field>
  9408. <name>G6_IO1</name>
  9409. <description>G6_IO1</description>
  9410. <bitOffset>20</bitOffset>
  9411. <bitWidth>1</bitWidth>
  9412. </field>
  9413. <field>
  9414. <name>G5_IO4</name>
  9415. <description>G5_IO4</description>
  9416. <bitOffset>19</bitOffset>
  9417. <bitWidth>1</bitWidth>
  9418. </field>
  9419. <field>
  9420. <name>G5_IO3</name>
  9421. <description>G5_IO3</description>
  9422. <bitOffset>18</bitOffset>
  9423. <bitWidth>1</bitWidth>
  9424. </field>
  9425. <field>
  9426. <name>G5_IO2</name>
  9427. <description>G5_IO2</description>
  9428. <bitOffset>17</bitOffset>
  9429. <bitWidth>1</bitWidth>
  9430. </field>
  9431. <field>
  9432. <name>G5_IO1</name>
  9433. <description>G5_IO1</description>
  9434. <bitOffset>16</bitOffset>
  9435. <bitWidth>1</bitWidth>
  9436. </field>
  9437. <field>
  9438. <name>G4_IO4</name>
  9439. <description>G4_IO4</description>
  9440. <bitOffset>15</bitOffset>
  9441. <bitWidth>1</bitWidth>
  9442. </field>
  9443. <field>
  9444. <name>G4_IO3</name>
  9445. <description>G4_IO3</description>
  9446. <bitOffset>14</bitOffset>
  9447. <bitWidth>1</bitWidth>
  9448. </field>
  9449. <field>
  9450. <name>G4_IO2</name>
  9451. <description>G4_IO2</description>
  9452. <bitOffset>13</bitOffset>
  9453. <bitWidth>1</bitWidth>
  9454. </field>
  9455. <field>
  9456. <name>G4_IO1</name>
  9457. <description>G4_IO1</description>
  9458. <bitOffset>12</bitOffset>
  9459. <bitWidth>1</bitWidth>
  9460. </field>
  9461. <field>
  9462. <name>G3_IO4</name>
  9463. <description>G3_IO4</description>
  9464. <bitOffset>11</bitOffset>
  9465. <bitWidth>1</bitWidth>
  9466. </field>
  9467. <field>
  9468. <name>G3_IO3</name>
  9469. <description>G3_IO3</description>
  9470. <bitOffset>10</bitOffset>
  9471. <bitWidth>1</bitWidth>
  9472. </field>
  9473. <field>
  9474. <name>G3_IO2</name>
  9475. <description>G3_IO2</description>
  9476. <bitOffset>9</bitOffset>
  9477. <bitWidth>1</bitWidth>
  9478. </field>
  9479. <field>
  9480. <name>G3_IO1</name>
  9481. <description>G3_IO1</description>
  9482. <bitOffset>8</bitOffset>
  9483. <bitWidth>1</bitWidth>
  9484. </field>
  9485. <field>
  9486. <name>G2_IO4</name>
  9487. <description>G2_IO4</description>
  9488. <bitOffset>7</bitOffset>
  9489. <bitWidth>1</bitWidth>
  9490. </field>
  9491. <field>
  9492. <name>G2_IO3</name>
  9493. <description>G2_IO3</description>
  9494. <bitOffset>6</bitOffset>
  9495. <bitWidth>1</bitWidth>
  9496. </field>
  9497. <field>
  9498. <name>G2_IO2</name>
  9499. <description>G2_IO2</description>
  9500. <bitOffset>5</bitOffset>
  9501. <bitWidth>1</bitWidth>
  9502. </field>
  9503. <field>
  9504. <name>G2_IO1</name>
  9505. <description>G2_IO1</description>
  9506. <bitOffset>4</bitOffset>
  9507. <bitWidth>1</bitWidth>
  9508. </field>
  9509. <field>
  9510. <name>G1_IO4</name>
  9511. <description>G1_IO4</description>
  9512. <bitOffset>3</bitOffset>
  9513. <bitWidth>1</bitWidth>
  9514. </field>
  9515. <field>
  9516. <name>G1_IO3</name>
  9517. <description>G1_IO3</description>
  9518. <bitOffset>2</bitOffset>
  9519. <bitWidth>1</bitWidth>
  9520. </field>
  9521. <field>
  9522. <name>G1_IO2</name>
  9523. <description>G1_IO2</description>
  9524. <bitOffset>1</bitOffset>
  9525. <bitWidth>1</bitWidth>
  9526. </field>
  9527. <field>
  9528. <name>G1_IO1</name>
  9529. <description>G1_IO1</description>
  9530. <bitOffset>0</bitOffset>
  9531. <bitWidth>1</bitWidth>
  9532. </field>
  9533. </fields>
  9534. </register>
  9535. <register>
  9536. <name>IOASCR</name>
  9537. <displayName>IOASCR</displayName>
  9538. <description>I/O analog switch control
  9539. register</description>
  9540. <addressOffset>0x18</addressOffset>
  9541. <size>0x20</size>
  9542. <access>read-write</access>
  9543. <resetValue>0x00000000</resetValue>
  9544. <fields>
  9545. <field>
  9546. <name>G8_IO4</name>
  9547. <description>G8_IO4</description>
  9548. <bitOffset>31</bitOffset>
  9549. <bitWidth>1</bitWidth>
  9550. </field>
  9551. <field>
  9552. <name>G8_IO3</name>
  9553. <description>G8_IO3</description>
  9554. <bitOffset>30</bitOffset>
  9555. <bitWidth>1</bitWidth>
  9556. </field>
  9557. <field>
  9558. <name>G8_IO2</name>
  9559. <description>G8_IO2</description>
  9560. <bitOffset>29</bitOffset>
  9561. <bitWidth>1</bitWidth>
  9562. </field>
  9563. <field>
  9564. <name>G8_IO1</name>
  9565. <description>G8_IO1</description>
  9566. <bitOffset>28</bitOffset>
  9567. <bitWidth>1</bitWidth>
  9568. </field>
  9569. <field>
  9570. <name>G7_IO4</name>
  9571. <description>G7_IO4</description>
  9572. <bitOffset>27</bitOffset>
  9573. <bitWidth>1</bitWidth>
  9574. </field>
  9575. <field>
  9576. <name>G7_IO3</name>
  9577. <description>G7_IO3</description>
  9578. <bitOffset>26</bitOffset>
  9579. <bitWidth>1</bitWidth>
  9580. </field>
  9581. <field>
  9582. <name>G7_IO2</name>
  9583. <description>G7_IO2</description>
  9584. <bitOffset>25</bitOffset>
  9585. <bitWidth>1</bitWidth>
  9586. </field>
  9587. <field>
  9588. <name>G7_IO1</name>
  9589. <description>G7_IO1</description>
  9590. <bitOffset>24</bitOffset>
  9591. <bitWidth>1</bitWidth>
  9592. </field>
  9593. <field>
  9594. <name>G6_IO4</name>
  9595. <description>G6_IO4</description>
  9596. <bitOffset>23</bitOffset>
  9597. <bitWidth>1</bitWidth>
  9598. </field>
  9599. <field>
  9600. <name>G6_IO3</name>
  9601. <description>G6_IO3</description>
  9602. <bitOffset>22</bitOffset>
  9603. <bitWidth>1</bitWidth>
  9604. </field>
  9605. <field>
  9606. <name>G6_IO2</name>
  9607. <description>G6_IO2</description>
  9608. <bitOffset>21</bitOffset>
  9609. <bitWidth>1</bitWidth>
  9610. </field>
  9611. <field>
  9612. <name>G6_IO1</name>
  9613. <description>G6_IO1</description>
  9614. <bitOffset>20</bitOffset>
  9615. <bitWidth>1</bitWidth>
  9616. </field>
  9617. <field>
  9618. <name>G5_IO4</name>
  9619. <description>G5_IO4</description>
  9620. <bitOffset>19</bitOffset>
  9621. <bitWidth>1</bitWidth>
  9622. </field>
  9623. <field>
  9624. <name>G5_IO3</name>
  9625. <description>G5_IO3</description>
  9626. <bitOffset>18</bitOffset>
  9627. <bitWidth>1</bitWidth>
  9628. </field>
  9629. <field>
  9630. <name>G5_IO2</name>
  9631. <description>G5_IO2</description>
  9632. <bitOffset>17</bitOffset>
  9633. <bitWidth>1</bitWidth>
  9634. </field>
  9635. <field>
  9636. <name>G5_IO1</name>
  9637. <description>G5_IO1</description>
  9638. <bitOffset>16</bitOffset>
  9639. <bitWidth>1</bitWidth>
  9640. </field>
  9641. <field>
  9642. <name>G4_IO4</name>
  9643. <description>G4_IO4</description>
  9644. <bitOffset>15</bitOffset>
  9645. <bitWidth>1</bitWidth>
  9646. </field>
  9647. <field>
  9648. <name>G4_IO3</name>
  9649. <description>G4_IO3</description>
  9650. <bitOffset>14</bitOffset>
  9651. <bitWidth>1</bitWidth>
  9652. </field>
  9653. <field>
  9654. <name>G4_IO2</name>
  9655. <description>G4_IO2</description>
  9656. <bitOffset>13</bitOffset>
  9657. <bitWidth>1</bitWidth>
  9658. </field>
  9659. <field>
  9660. <name>G4_IO1</name>
  9661. <description>G4_IO1</description>
  9662. <bitOffset>12</bitOffset>
  9663. <bitWidth>1</bitWidth>
  9664. </field>
  9665. <field>
  9666. <name>G3_IO4</name>
  9667. <description>G3_IO4</description>
  9668. <bitOffset>11</bitOffset>
  9669. <bitWidth>1</bitWidth>
  9670. </field>
  9671. <field>
  9672. <name>G3_IO3</name>
  9673. <description>G3_IO3</description>
  9674. <bitOffset>10</bitOffset>
  9675. <bitWidth>1</bitWidth>
  9676. </field>
  9677. <field>
  9678. <name>G3_IO2</name>
  9679. <description>G3_IO2</description>
  9680. <bitOffset>9</bitOffset>
  9681. <bitWidth>1</bitWidth>
  9682. </field>
  9683. <field>
  9684. <name>G3_IO1</name>
  9685. <description>G3_IO1</description>
  9686. <bitOffset>8</bitOffset>
  9687. <bitWidth>1</bitWidth>
  9688. </field>
  9689. <field>
  9690. <name>G2_IO4</name>
  9691. <description>G2_IO4</description>
  9692. <bitOffset>7</bitOffset>
  9693. <bitWidth>1</bitWidth>
  9694. </field>
  9695. <field>
  9696. <name>G2_IO3</name>
  9697. <description>G2_IO3</description>
  9698. <bitOffset>6</bitOffset>
  9699. <bitWidth>1</bitWidth>
  9700. </field>
  9701. <field>
  9702. <name>G2_IO2</name>
  9703. <description>G2_IO2</description>
  9704. <bitOffset>5</bitOffset>
  9705. <bitWidth>1</bitWidth>
  9706. </field>
  9707. <field>
  9708. <name>G2_IO1</name>
  9709. <description>G2_IO1</description>
  9710. <bitOffset>4</bitOffset>
  9711. <bitWidth>1</bitWidth>
  9712. </field>
  9713. <field>
  9714. <name>G1_IO4</name>
  9715. <description>G1_IO4</description>
  9716. <bitOffset>3</bitOffset>
  9717. <bitWidth>1</bitWidth>
  9718. </field>
  9719. <field>
  9720. <name>G1_IO3</name>
  9721. <description>G1_IO3</description>
  9722. <bitOffset>2</bitOffset>
  9723. <bitWidth>1</bitWidth>
  9724. </field>
  9725. <field>
  9726. <name>G1_IO2</name>
  9727. <description>G1_IO2</description>
  9728. <bitOffset>1</bitOffset>
  9729. <bitWidth>1</bitWidth>
  9730. </field>
  9731. <field>
  9732. <name>G1_IO1</name>
  9733. <description>G1_IO1</description>
  9734. <bitOffset>0</bitOffset>
  9735. <bitWidth>1</bitWidth>
  9736. </field>
  9737. </fields>
  9738. </register>
  9739. <register>
  9740. <name>IOSCR</name>
  9741. <displayName>IOSCR</displayName>
  9742. <description>I/O sampling control register</description>
  9743. <addressOffset>0x20</addressOffset>
  9744. <size>0x20</size>
  9745. <access>read-write</access>
  9746. <resetValue>0x00000000</resetValue>
  9747. <fields>
  9748. <field>
  9749. <name>G8_IO4</name>
  9750. <description>G8_IO4</description>
  9751. <bitOffset>31</bitOffset>
  9752. <bitWidth>1</bitWidth>
  9753. </field>
  9754. <field>
  9755. <name>G8_IO3</name>
  9756. <description>G8_IO3</description>
  9757. <bitOffset>30</bitOffset>
  9758. <bitWidth>1</bitWidth>
  9759. </field>
  9760. <field>
  9761. <name>G8_IO2</name>
  9762. <description>G8_IO2</description>
  9763. <bitOffset>29</bitOffset>
  9764. <bitWidth>1</bitWidth>
  9765. </field>
  9766. <field>
  9767. <name>G8_IO1</name>
  9768. <description>G8_IO1</description>
  9769. <bitOffset>28</bitOffset>
  9770. <bitWidth>1</bitWidth>
  9771. </field>
  9772. <field>
  9773. <name>G7_IO4</name>
  9774. <description>G7_IO4</description>
  9775. <bitOffset>27</bitOffset>
  9776. <bitWidth>1</bitWidth>
  9777. </field>
  9778. <field>
  9779. <name>G7_IO3</name>
  9780. <description>G7_IO3</description>
  9781. <bitOffset>26</bitOffset>
  9782. <bitWidth>1</bitWidth>
  9783. </field>
  9784. <field>
  9785. <name>G7_IO2</name>
  9786. <description>G7_IO2</description>
  9787. <bitOffset>25</bitOffset>
  9788. <bitWidth>1</bitWidth>
  9789. </field>
  9790. <field>
  9791. <name>G7_IO1</name>
  9792. <description>G7_IO1</description>
  9793. <bitOffset>24</bitOffset>
  9794. <bitWidth>1</bitWidth>
  9795. </field>
  9796. <field>
  9797. <name>G6_IO4</name>
  9798. <description>G6_IO4</description>
  9799. <bitOffset>23</bitOffset>
  9800. <bitWidth>1</bitWidth>
  9801. </field>
  9802. <field>
  9803. <name>G6_IO3</name>
  9804. <description>G6_IO3</description>
  9805. <bitOffset>22</bitOffset>
  9806. <bitWidth>1</bitWidth>
  9807. </field>
  9808. <field>
  9809. <name>G6_IO2</name>
  9810. <description>G6_IO2</description>
  9811. <bitOffset>21</bitOffset>
  9812. <bitWidth>1</bitWidth>
  9813. </field>
  9814. <field>
  9815. <name>G6_IO1</name>
  9816. <description>G6_IO1</description>
  9817. <bitOffset>20</bitOffset>
  9818. <bitWidth>1</bitWidth>
  9819. </field>
  9820. <field>
  9821. <name>G5_IO4</name>
  9822. <description>G5_IO4</description>
  9823. <bitOffset>19</bitOffset>
  9824. <bitWidth>1</bitWidth>
  9825. </field>
  9826. <field>
  9827. <name>G5_IO3</name>
  9828. <description>G5_IO3</description>
  9829. <bitOffset>18</bitOffset>
  9830. <bitWidth>1</bitWidth>
  9831. </field>
  9832. <field>
  9833. <name>G5_IO2</name>
  9834. <description>G5_IO2</description>
  9835. <bitOffset>17</bitOffset>
  9836. <bitWidth>1</bitWidth>
  9837. </field>
  9838. <field>
  9839. <name>G5_IO1</name>
  9840. <description>G5_IO1</description>
  9841. <bitOffset>16</bitOffset>
  9842. <bitWidth>1</bitWidth>
  9843. </field>
  9844. <field>
  9845. <name>G4_IO4</name>
  9846. <description>G4_IO4</description>
  9847. <bitOffset>15</bitOffset>
  9848. <bitWidth>1</bitWidth>
  9849. </field>
  9850. <field>
  9851. <name>G4_IO3</name>
  9852. <description>G4_IO3</description>
  9853. <bitOffset>14</bitOffset>
  9854. <bitWidth>1</bitWidth>
  9855. </field>
  9856. <field>
  9857. <name>G4_IO2</name>
  9858. <description>G4_IO2</description>
  9859. <bitOffset>13</bitOffset>
  9860. <bitWidth>1</bitWidth>
  9861. </field>
  9862. <field>
  9863. <name>G4_IO1</name>
  9864. <description>G4_IO1</description>
  9865. <bitOffset>12</bitOffset>
  9866. <bitWidth>1</bitWidth>
  9867. </field>
  9868. <field>
  9869. <name>G3_IO4</name>
  9870. <description>G3_IO4</description>
  9871. <bitOffset>11</bitOffset>
  9872. <bitWidth>1</bitWidth>
  9873. </field>
  9874. <field>
  9875. <name>G3_IO3</name>
  9876. <description>G3_IO3</description>
  9877. <bitOffset>10</bitOffset>
  9878. <bitWidth>1</bitWidth>
  9879. </field>
  9880. <field>
  9881. <name>G3_IO2</name>
  9882. <description>G3_IO2</description>
  9883. <bitOffset>9</bitOffset>
  9884. <bitWidth>1</bitWidth>
  9885. </field>
  9886. <field>
  9887. <name>G3_IO1</name>
  9888. <description>G3_IO1</description>
  9889. <bitOffset>8</bitOffset>
  9890. <bitWidth>1</bitWidth>
  9891. </field>
  9892. <field>
  9893. <name>G2_IO4</name>
  9894. <description>G2_IO4</description>
  9895. <bitOffset>7</bitOffset>
  9896. <bitWidth>1</bitWidth>
  9897. </field>
  9898. <field>
  9899. <name>G2_IO3</name>
  9900. <description>G2_IO3</description>
  9901. <bitOffset>6</bitOffset>
  9902. <bitWidth>1</bitWidth>
  9903. </field>
  9904. <field>
  9905. <name>G2_IO2</name>
  9906. <description>G2_IO2</description>
  9907. <bitOffset>5</bitOffset>
  9908. <bitWidth>1</bitWidth>
  9909. </field>
  9910. <field>
  9911. <name>G2_IO1</name>
  9912. <description>G2_IO1</description>
  9913. <bitOffset>4</bitOffset>
  9914. <bitWidth>1</bitWidth>
  9915. </field>
  9916. <field>
  9917. <name>G1_IO4</name>
  9918. <description>G1_IO4</description>
  9919. <bitOffset>3</bitOffset>
  9920. <bitWidth>1</bitWidth>
  9921. </field>
  9922. <field>
  9923. <name>G1_IO3</name>
  9924. <description>G1_IO3</description>
  9925. <bitOffset>2</bitOffset>
  9926. <bitWidth>1</bitWidth>
  9927. </field>
  9928. <field>
  9929. <name>G1_IO2</name>
  9930. <description>G1_IO2</description>
  9931. <bitOffset>1</bitOffset>
  9932. <bitWidth>1</bitWidth>
  9933. </field>
  9934. <field>
  9935. <name>G1_IO1</name>
  9936. <description>G1_IO1</description>
  9937. <bitOffset>0</bitOffset>
  9938. <bitWidth>1</bitWidth>
  9939. </field>
  9940. </fields>
  9941. </register>
  9942. <register>
  9943. <name>IOCCR</name>
  9944. <displayName>IOCCR</displayName>
  9945. <description>I/O channel control register</description>
  9946. <addressOffset>0x28</addressOffset>
  9947. <size>0x20</size>
  9948. <access>read-write</access>
  9949. <resetValue>0x00000000</resetValue>
  9950. <fields>
  9951. <field>
  9952. <name>G8_IO4</name>
  9953. <description>G8_IO4</description>
  9954. <bitOffset>31</bitOffset>
  9955. <bitWidth>1</bitWidth>
  9956. </field>
  9957. <field>
  9958. <name>G8_IO3</name>
  9959. <description>G8_IO3</description>
  9960. <bitOffset>30</bitOffset>
  9961. <bitWidth>1</bitWidth>
  9962. </field>
  9963. <field>
  9964. <name>G8_IO2</name>
  9965. <description>G8_IO2</description>
  9966. <bitOffset>29</bitOffset>
  9967. <bitWidth>1</bitWidth>
  9968. </field>
  9969. <field>
  9970. <name>G8_IO1</name>
  9971. <description>G8_IO1</description>
  9972. <bitOffset>28</bitOffset>
  9973. <bitWidth>1</bitWidth>
  9974. </field>
  9975. <field>
  9976. <name>G7_IO4</name>
  9977. <description>G7_IO4</description>
  9978. <bitOffset>27</bitOffset>
  9979. <bitWidth>1</bitWidth>
  9980. </field>
  9981. <field>
  9982. <name>G7_IO3</name>
  9983. <description>G7_IO3</description>
  9984. <bitOffset>26</bitOffset>
  9985. <bitWidth>1</bitWidth>
  9986. </field>
  9987. <field>
  9988. <name>G7_IO2</name>
  9989. <description>G7_IO2</description>
  9990. <bitOffset>25</bitOffset>
  9991. <bitWidth>1</bitWidth>
  9992. </field>
  9993. <field>
  9994. <name>G7_IO1</name>
  9995. <description>G7_IO1</description>
  9996. <bitOffset>24</bitOffset>
  9997. <bitWidth>1</bitWidth>
  9998. </field>
  9999. <field>
  10000. <name>G6_IO4</name>
  10001. <description>G6_IO4</description>
  10002. <bitOffset>23</bitOffset>
  10003. <bitWidth>1</bitWidth>
  10004. </field>
  10005. <field>
  10006. <name>G6_IO3</name>
  10007. <description>G6_IO3</description>
  10008. <bitOffset>22</bitOffset>
  10009. <bitWidth>1</bitWidth>
  10010. </field>
  10011. <field>
  10012. <name>G6_IO2</name>
  10013. <description>G6_IO2</description>
  10014. <bitOffset>21</bitOffset>
  10015. <bitWidth>1</bitWidth>
  10016. </field>
  10017. <field>
  10018. <name>G6_IO1</name>
  10019. <description>G6_IO1</description>
  10020. <bitOffset>20</bitOffset>
  10021. <bitWidth>1</bitWidth>
  10022. </field>
  10023. <field>
  10024. <name>G5_IO4</name>
  10025. <description>G5_IO4</description>
  10026. <bitOffset>19</bitOffset>
  10027. <bitWidth>1</bitWidth>
  10028. </field>
  10029. <field>
  10030. <name>G5_IO3</name>
  10031. <description>G5_IO3</description>
  10032. <bitOffset>18</bitOffset>
  10033. <bitWidth>1</bitWidth>
  10034. </field>
  10035. <field>
  10036. <name>G5_IO2</name>
  10037. <description>G5_IO2</description>
  10038. <bitOffset>17</bitOffset>
  10039. <bitWidth>1</bitWidth>
  10040. </field>
  10041. <field>
  10042. <name>G5_IO1</name>
  10043. <description>G5_IO1</description>
  10044. <bitOffset>16</bitOffset>
  10045. <bitWidth>1</bitWidth>
  10046. </field>
  10047. <field>
  10048. <name>G4_IO4</name>
  10049. <description>G4_IO4</description>
  10050. <bitOffset>15</bitOffset>
  10051. <bitWidth>1</bitWidth>
  10052. </field>
  10053. <field>
  10054. <name>G4_IO3</name>
  10055. <description>G4_IO3</description>
  10056. <bitOffset>14</bitOffset>
  10057. <bitWidth>1</bitWidth>
  10058. </field>
  10059. <field>
  10060. <name>G4_IO2</name>
  10061. <description>G4_IO2</description>
  10062. <bitOffset>13</bitOffset>
  10063. <bitWidth>1</bitWidth>
  10064. </field>
  10065. <field>
  10066. <name>G4_IO1</name>
  10067. <description>G4_IO1</description>
  10068. <bitOffset>12</bitOffset>
  10069. <bitWidth>1</bitWidth>
  10070. </field>
  10071. <field>
  10072. <name>G3_IO4</name>
  10073. <description>G3_IO4</description>
  10074. <bitOffset>11</bitOffset>
  10075. <bitWidth>1</bitWidth>
  10076. </field>
  10077. <field>
  10078. <name>G3_IO3</name>
  10079. <description>G3_IO3</description>
  10080. <bitOffset>10</bitOffset>
  10081. <bitWidth>1</bitWidth>
  10082. </field>
  10083. <field>
  10084. <name>G3_IO2</name>
  10085. <description>G3_IO2</description>
  10086. <bitOffset>9</bitOffset>
  10087. <bitWidth>1</bitWidth>
  10088. </field>
  10089. <field>
  10090. <name>G3_IO1</name>
  10091. <description>G3_IO1</description>
  10092. <bitOffset>8</bitOffset>
  10093. <bitWidth>1</bitWidth>
  10094. </field>
  10095. <field>
  10096. <name>G2_IO4</name>
  10097. <description>G2_IO4</description>
  10098. <bitOffset>7</bitOffset>
  10099. <bitWidth>1</bitWidth>
  10100. </field>
  10101. <field>
  10102. <name>G2_IO3</name>
  10103. <description>G2_IO3</description>
  10104. <bitOffset>6</bitOffset>
  10105. <bitWidth>1</bitWidth>
  10106. </field>
  10107. <field>
  10108. <name>G2_IO2</name>
  10109. <description>G2_IO2</description>
  10110. <bitOffset>5</bitOffset>
  10111. <bitWidth>1</bitWidth>
  10112. </field>
  10113. <field>
  10114. <name>G2_IO1</name>
  10115. <description>G2_IO1</description>
  10116. <bitOffset>4</bitOffset>
  10117. <bitWidth>1</bitWidth>
  10118. </field>
  10119. <field>
  10120. <name>G1_IO4</name>
  10121. <description>G1_IO4</description>
  10122. <bitOffset>3</bitOffset>
  10123. <bitWidth>1</bitWidth>
  10124. </field>
  10125. <field>
  10126. <name>G1_IO3</name>
  10127. <description>G1_IO3</description>
  10128. <bitOffset>2</bitOffset>
  10129. <bitWidth>1</bitWidth>
  10130. </field>
  10131. <field>
  10132. <name>G1_IO2</name>
  10133. <description>G1_IO2</description>
  10134. <bitOffset>1</bitOffset>
  10135. <bitWidth>1</bitWidth>
  10136. </field>
  10137. <field>
  10138. <name>G1_IO1</name>
  10139. <description>G1_IO1</description>
  10140. <bitOffset>0</bitOffset>
  10141. <bitWidth>1</bitWidth>
  10142. </field>
  10143. </fields>
  10144. </register>
  10145. <register>
  10146. <name>IOGCSR</name>
  10147. <displayName>IOGCSR</displayName>
  10148. <description>I/O group control status
  10149. register</description>
  10150. <addressOffset>0x30</addressOffset>
  10151. <size>0x20</size>
  10152. <resetValue>0x00000000</resetValue>
  10153. <fields>
  10154. <field>
  10155. <name>G8S</name>
  10156. <description>Analog I/O group x status</description>
  10157. <bitOffset>23</bitOffset>
  10158. <bitWidth>1</bitWidth>
  10159. <access>read-only</access>
  10160. </field>
  10161. <field>
  10162. <name>G7S</name>
  10163. <description>Analog I/O group x status</description>
  10164. <bitOffset>22</bitOffset>
  10165. <bitWidth>1</bitWidth>
  10166. <access>read-only</access>
  10167. </field>
  10168. <field>
  10169. <name>G6S</name>
  10170. <description>Analog I/O group x status</description>
  10171. <bitOffset>21</bitOffset>
  10172. <bitWidth>1</bitWidth>
  10173. <access>read-only</access>
  10174. </field>
  10175. <field>
  10176. <name>G5S</name>
  10177. <description>Analog I/O group x status</description>
  10178. <bitOffset>20</bitOffset>
  10179. <bitWidth>1</bitWidth>
  10180. <access>read-only</access>
  10181. </field>
  10182. <field>
  10183. <name>G4S</name>
  10184. <description>Analog I/O group x status</description>
  10185. <bitOffset>19</bitOffset>
  10186. <bitWidth>1</bitWidth>
  10187. <access>read-only</access>
  10188. </field>
  10189. <field>
  10190. <name>G3S</name>
  10191. <description>Analog I/O group x status</description>
  10192. <bitOffset>18</bitOffset>
  10193. <bitWidth>1</bitWidth>
  10194. <access>read-only</access>
  10195. </field>
  10196. <field>
  10197. <name>G2S</name>
  10198. <description>Analog I/O group x status</description>
  10199. <bitOffset>17</bitOffset>
  10200. <bitWidth>1</bitWidth>
  10201. <access>read-only</access>
  10202. </field>
  10203. <field>
  10204. <name>G1S</name>
  10205. <description>Analog I/O group x status</description>
  10206. <bitOffset>16</bitOffset>
  10207. <bitWidth>1</bitWidth>
  10208. <access>read-only</access>
  10209. </field>
  10210. <field>
  10211. <name>G8E</name>
  10212. <description>Analog I/O group x enable</description>
  10213. <bitOffset>7</bitOffset>
  10214. <bitWidth>1</bitWidth>
  10215. <access>read-write</access>
  10216. </field>
  10217. <field>
  10218. <name>G7E</name>
  10219. <description>Analog I/O group x enable</description>
  10220. <bitOffset>6</bitOffset>
  10221. <bitWidth>1</bitWidth>
  10222. <access>read-write</access>
  10223. </field>
  10224. <field>
  10225. <name>G6E</name>
  10226. <description>Analog I/O group x enable</description>
  10227. <bitOffset>5</bitOffset>
  10228. <bitWidth>1</bitWidth>
  10229. <access>read-write</access>
  10230. </field>
  10231. <field>
  10232. <name>G5E</name>
  10233. <description>Analog I/O group x enable</description>
  10234. <bitOffset>4</bitOffset>
  10235. <bitWidth>1</bitWidth>
  10236. <access>read-write</access>
  10237. </field>
  10238. <field>
  10239. <name>G4E</name>
  10240. <description>Analog I/O group x enable</description>
  10241. <bitOffset>3</bitOffset>
  10242. <bitWidth>1</bitWidth>
  10243. <access>read-write</access>
  10244. </field>
  10245. <field>
  10246. <name>G3E</name>
  10247. <description>Analog I/O group x enable</description>
  10248. <bitOffset>2</bitOffset>
  10249. <bitWidth>1</bitWidth>
  10250. <access>read-write</access>
  10251. </field>
  10252. <field>
  10253. <name>G2E</name>
  10254. <description>Analog I/O group x enable</description>
  10255. <bitOffset>1</bitOffset>
  10256. <bitWidth>1</bitWidth>
  10257. <access>read-write</access>
  10258. </field>
  10259. <field>
  10260. <name>G1E</name>
  10261. <description>Analog I/O group x enable</description>
  10262. <bitOffset>0</bitOffset>
  10263. <bitWidth>1</bitWidth>
  10264. <access>read-write</access>
  10265. </field>
  10266. </fields>
  10267. </register>
  10268. <register>
  10269. <name>IOG1CR</name>
  10270. <displayName>IOG1CR</displayName>
  10271. <description>I/O group x counter register</description>
  10272. <addressOffset>0x34</addressOffset>
  10273. <size>0x20</size>
  10274. <access>read-only</access>
  10275. <resetValue>0x00000000</resetValue>
  10276. <fields>
  10277. <field>
  10278. <name>CNT</name>
  10279. <description>Counter value</description>
  10280. <bitOffset>0</bitOffset>
  10281. <bitWidth>14</bitWidth>
  10282. </field>
  10283. </fields>
  10284. </register>
  10285. <register>
  10286. <name>IOG2CR</name>
  10287. <displayName>IOG2CR</displayName>
  10288. <description>I/O group x counter register</description>
  10289. <addressOffset>0x38</addressOffset>
  10290. <size>0x20</size>
  10291. <access>read-only</access>
  10292. <resetValue>0x00000000</resetValue>
  10293. <fields>
  10294. <field>
  10295. <name>CNT</name>
  10296. <description>Counter value</description>
  10297. <bitOffset>0</bitOffset>
  10298. <bitWidth>14</bitWidth>
  10299. </field>
  10300. </fields>
  10301. </register>
  10302. <register>
  10303. <name>IOG3CR</name>
  10304. <displayName>IOG3CR</displayName>
  10305. <description>I/O group x counter register</description>
  10306. <addressOffset>0x3C</addressOffset>
  10307. <size>0x20</size>
  10308. <access>read-only</access>
  10309. <resetValue>0x00000000</resetValue>
  10310. <fields>
  10311. <field>
  10312. <name>CNT</name>
  10313. <description>Counter value</description>
  10314. <bitOffset>0</bitOffset>
  10315. <bitWidth>14</bitWidth>
  10316. </field>
  10317. </fields>
  10318. </register>
  10319. <register>
  10320. <name>IOG4CR</name>
  10321. <displayName>IOG4CR</displayName>
  10322. <description>I/O group x counter register</description>
  10323. <addressOffset>0x40</addressOffset>
  10324. <size>0x20</size>
  10325. <access>read-only</access>
  10326. <resetValue>0x00000000</resetValue>
  10327. <fields>
  10328. <field>
  10329. <name>CNT</name>
  10330. <description>Counter value</description>
  10331. <bitOffset>0</bitOffset>
  10332. <bitWidth>14</bitWidth>
  10333. </field>
  10334. </fields>
  10335. </register>
  10336. <register>
  10337. <name>IOG5CR</name>
  10338. <displayName>IOG5CR</displayName>
  10339. <description>I/O group x counter register</description>
  10340. <addressOffset>0x44</addressOffset>
  10341. <size>0x20</size>
  10342. <access>read-only</access>
  10343. <resetValue>0x00000000</resetValue>
  10344. <fields>
  10345. <field>
  10346. <name>CNT</name>
  10347. <description>Counter value</description>
  10348. <bitOffset>0</bitOffset>
  10349. <bitWidth>14</bitWidth>
  10350. </field>
  10351. </fields>
  10352. </register>
  10353. <register>
  10354. <name>IOG6CR</name>
  10355. <displayName>IOG6CR</displayName>
  10356. <description>I/O group x counter register</description>
  10357. <addressOffset>0x48</addressOffset>
  10358. <size>0x20</size>
  10359. <access>read-only</access>
  10360. <resetValue>0x00000000</resetValue>
  10361. <fields>
  10362. <field>
  10363. <name>CNT</name>
  10364. <description>Counter value</description>
  10365. <bitOffset>0</bitOffset>
  10366. <bitWidth>14</bitWidth>
  10367. </field>
  10368. </fields>
  10369. </register>
  10370. <register>
  10371. <name>IOG7CR</name>
  10372. <displayName>IOG7CR</displayName>
  10373. <description>I/O group x counter register</description>
  10374. <addressOffset>0x4C</addressOffset>
  10375. <size>0x20</size>
  10376. <access>read-only</access>
  10377. <resetValue>0x00000000</resetValue>
  10378. <fields>
  10379. <field>
  10380. <name>CNT</name>
  10381. <description>Counter value</description>
  10382. <bitOffset>0</bitOffset>
  10383. <bitWidth>14</bitWidth>
  10384. </field>
  10385. </fields>
  10386. </register>
  10387. <register>
  10388. <name>IOG8CR</name>
  10389. <displayName>IOG8CR</displayName>
  10390. <description>I/O group x counter register</description>
  10391. <addressOffset>0x50</addressOffset>
  10392. <size>0x20</size>
  10393. <access>read-only</access>
  10394. <resetValue>0x00000000</resetValue>
  10395. <fields>
  10396. <field>
  10397. <name>CNT</name>
  10398. <description>Counter value</description>
  10399. <bitOffset>0</bitOffset>
  10400. <bitWidth>14</bitWidth>
  10401. </field>
  10402. </fields>
  10403. </register>
  10404. </registers>
  10405. </peripheral>
  10406. <peripheral>
  10407. <name>IWDG</name>
  10408. <description>Independent watchdog</description>
  10409. <groupName>IWDG</groupName>
  10410. <baseAddress>0x40003000</baseAddress>
  10411. <addressBlock>
  10412. <offset>0x0</offset>
  10413. <size>0x400</size>
  10414. <usage>registers</usage>
  10415. </addressBlock>
  10416. <registers>
  10417. <register>
  10418. <name>KR</name>
  10419. <displayName>KR</displayName>
  10420. <description>Key register</description>
  10421. <addressOffset>0x0</addressOffset>
  10422. <size>0x20</size>
  10423. <access>write-only</access>
  10424. <resetValue>0x00000000</resetValue>
  10425. <fields>
  10426. <field>
  10427. <name>KEY</name>
  10428. <description>Key value (write only, read
  10429. 0x0000)</description>
  10430. <bitOffset>0</bitOffset>
  10431. <bitWidth>16</bitWidth>
  10432. </field>
  10433. </fields>
  10434. </register>
  10435. <register>
  10436. <name>PR</name>
  10437. <displayName>PR</displayName>
  10438. <description>Prescaler register</description>
  10439. <addressOffset>0x4</addressOffset>
  10440. <size>0x20</size>
  10441. <access>read-write</access>
  10442. <resetValue>0x00000000</resetValue>
  10443. <fields>
  10444. <field>
  10445. <name>PR</name>
  10446. <description>Prescaler divider</description>
  10447. <bitOffset>0</bitOffset>
  10448. <bitWidth>3</bitWidth>
  10449. </field>
  10450. </fields>
  10451. </register>
  10452. <register>
  10453. <name>RLR</name>
  10454. <displayName>RLR</displayName>
  10455. <description>Reload register</description>
  10456. <addressOffset>0x8</addressOffset>
  10457. <size>0x20</size>
  10458. <access>read-write</access>
  10459. <resetValue>0x00000FFF</resetValue>
  10460. <fields>
  10461. <field>
  10462. <name>RL</name>
  10463. <description>Watchdog counter reload
  10464. value</description>
  10465. <bitOffset>0</bitOffset>
  10466. <bitWidth>12</bitWidth>
  10467. </field>
  10468. </fields>
  10469. </register>
  10470. <register>
  10471. <name>SR</name>
  10472. <displayName>SR</displayName>
  10473. <description>Status register</description>
  10474. <addressOffset>0xC</addressOffset>
  10475. <size>0x20</size>
  10476. <access>read-only</access>
  10477. <resetValue>0x00000000</resetValue>
  10478. <fields>
  10479. <field>
  10480. <name>WVU</name>
  10481. <description>Watchdog counter window value
  10482. update</description>
  10483. <bitOffset>2</bitOffset>
  10484. <bitWidth>1</bitWidth>
  10485. </field>
  10486. <field>
  10487. <name>RVU</name>
  10488. <description>Watchdog counter reload value
  10489. update</description>
  10490. <bitOffset>1</bitOffset>
  10491. <bitWidth>1</bitWidth>
  10492. </field>
  10493. <field>
  10494. <name>PVU</name>
  10495. <description>Watchdog prescaler value
  10496. update</description>
  10497. <bitOffset>0</bitOffset>
  10498. <bitWidth>1</bitWidth>
  10499. </field>
  10500. </fields>
  10501. </register>
  10502. <register>
  10503. <name>WINR</name>
  10504. <displayName>WINR</displayName>
  10505. <description>Window register</description>
  10506. <addressOffset>0x10</addressOffset>
  10507. <size>0x20</size>
  10508. <access>read-write</access>
  10509. <resetValue>0x00000FFF</resetValue>
  10510. <fields>
  10511. <field>
  10512. <name>WIN</name>
  10513. <description>Watchdog counter window
  10514. value</description>
  10515. <bitOffset>0</bitOffset>
  10516. <bitWidth>12</bitWidth>
  10517. </field>
  10518. </fields>
  10519. </register>
  10520. </registers>
  10521. </peripheral>
  10522. <peripheral>
  10523. <name>WWDG</name>
  10524. <description>System window watchdog</description>
  10525. <groupName>WWDG</groupName>
  10526. <baseAddress>0x40002C00</baseAddress>
  10527. <addressBlock>
  10528. <offset>0x0</offset>
  10529. <size>0x400</size>
  10530. <usage>registers</usage>
  10531. </addressBlock>
  10532. <interrupt>
  10533. <name>WWDG</name>
  10534. <description>Window Watchdog interrupt</description>
  10535. <value>0</value>
  10536. </interrupt>
  10537. <registers>
  10538. <register>
  10539. <name>CR</name>
  10540. <displayName>CR</displayName>
  10541. <description>Control register</description>
  10542. <addressOffset>0x0</addressOffset>
  10543. <size>0x20</size>
  10544. <access>read-write</access>
  10545. <resetValue>0x0000007F</resetValue>
  10546. <fields>
  10547. <field>
  10548. <name>WDGA</name>
  10549. <description>Activation bit</description>
  10550. <bitOffset>7</bitOffset>
  10551. <bitWidth>1</bitWidth>
  10552. </field>
  10553. <field>
  10554. <name>T</name>
  10555. <description>7-bit counter (MSB to LSB)</description>
  10556. <bitOffset>0</bitOffset>
  10557. <bitWidth>7</bitWidth>
  10558. </field>
  10559. </fields>
  10560. </register>
  10561. <register>
  10562. <name>CFR</name>
  10563. <displayName>CFR</displayName>
  10564. <description>Configuration register</description>
  10565. <addressOffset>0x4</addressOffset>
  10566. <size>0x20</size>
  10567. <access>read-write</access>
  10568. <resetValue>0x0000007F</resetValue>
  10569. <fields>
  10570. <field>
  10571. <name>EWI</name>
  10572. <description>Early wakeup interrupt</description>
  10573. <bitOffset>9</bitOffset>
  10574. <bitWidth>1</bitWidth>
  10575. </field>
  10576. <field>
  10577. <name>WDGTB1</name>
  10578. <description>Timer base</description>
  10579. <bitOffset>8</bitOffset>
  10580. <bitWidth>1</bitWidth>
  10581. </field>
  10582. <field>
  10583. <name>WDGTB0</name>
  10584. <description>WDGTB0</description>
  10585. <bitOffset>7</bitOffset>
  10586. <bitWidth>1</bitWidth>
  10587. </field>
  10588. <field>
  10589. <name>W</name>
  10590. <description>7-bit window value</description>
  10591. <bitOffset>0</bitOffset>
  10592. <bitWidth>7</bitWidth>
  10593. </field>
  10594. </fields>
  10595. </register>
  10596. <register>
  10597. <name>SR</name>
  10598. <displayName>SR</displayName>
  10599. <description>Status register</description>
  10600. <addressOffset>0x8</addressOffset>
  10601. <size>0x20</size>
  10602. <access>read-writeOnce</access>
  10603. <resetValue>0x00000000</resetValue>
  10604. <fields>
  10605. <field>
  10606. <name>EWIF</name>
  10607. <description>Early wakeup interrupt
  10608. flag</description>
  10609. <bitOffset>0</bitOffset>
  10610. <bitWidth>1</bitWidth>
  10611. </field>
  10612. </fields>
  10613. </register>
  10614. </registers>
  10615. </peripheral>
  10616. <peripheral>
  10617. <name>COMP</name>
  10618. <description>Comparator</description>
  10619. <groupName>COMP</groupName>
  10620. <baseAddress>0x40010018</baseAddress>
  10621. <addressBlock>
  10622. <offset>0x0</offset>
  10623. <size>0x400</size>
  10624. <usage>registers</usage>
  10625. </addressBlock>
  10626. <registers>
  10627. <register>
  10628. <name>COMP1_CSR</name>
  10629. <displayName>COMP1_CSR</displayName>
  10630. <description>Comparator 1 control and status
  10631. register</description>
  10632. <addressOffset>0x18</addressOffset>
  10633. <size>0x20</size>
  10634. <resetValue>0x0</resetValue>
  10635. <fields>
  10636. <field>
  10637. <name>COMP1_EN</name>
  10638. <description>Comparator 1 enable bit</description>
  10639. <bitOffset>0</bitOffset>
  10640. <bitWidth>1</bitWidth>
  10641. <access>read-write</access>
  10642. </field>
  10643. <field>
  10644. <name>COMP1_INN_SEL</name>
  10645. <description>Comparator 1 Input Minus connection
  10646. configuration bit</description>
  10647. <bitOffset>4</bitOffset>
  10648. <bitWidth>2</bitWidth>
  10649. <access>read-write</access>
  10650. </field>
  10651. <field>
  10652. <name>COMP1_WM</name>
  10653. <description>Comparator 1 window mode selection
  10654. bit</description>
  10655. <bitOffset>8</bitOffset>
  10656. <bitWidth>1</bitWidth>
  10657. <access>read-write</access>
  10658. </field>
  10659. <field>
  10660. <name>COMP1_OUT_SEL</name>
  10661. <description>COMP1 output select</description>
  10662. <bitOffset>12</bitOffset>
  10663. <bitWidth>3</bitWidth>
  10664. <access>read-write</access>
  10665. </field>
  10666. <field>
  10667. <name>COMP1_POLARITY</name>
  10668. <description>Comparator 1 polarity selection
  10669. bit</description>
  10670. <bitOffset>15</bitOffset>
  10671. <bitWidth>1</bitWidth>
  10672. <access>read-write</access>
  10673. </field>
  10674. <field>
  10675. <name>COMP1_VALUE</name>
  10676. <description>Comparator 1 output status
  10677. bit</description>
  10678. <bitOffset>30</bitOffset>
  10679. <bitWidth>1</bitWidth>
  10680. <access>read-only</access>
  10681. </field>
  10682. <field>
  10683. <name>COMP1_LOCK</name>
  10684. <description>COMP1_CSR register lock
  10685. bit</description>
  10686. <bitOffset>31</bitOffset>
  10687. <bitWidth>1</bitWidth>
  10688. <access>write-only</access>
  10689. </field>
  10690. </fields>
  10691. </register>
  10692. <register>
  10693. <name>COMP2_CSR</name>
  10694. <displayName>COMP2_CSR</displayName>
  10695. <description>Comparator 2 control and status
  10696. register</description>
  10697. <addressOffset>0x1C</addressOffset>
  10698. <size>0x20</size>
  10699. <resetValue>0x0</resetValue>
  10700. <fields>
  10701. <field>
  10702. <name>COMP2_LOCK</name>
  10703. <description>COMP2_CSR register lock
  10704. bit</description>
  10705. <bitOffset>31</bitOffset>
  10706. <bitWidth>1</bitWidth>
  10707. <access>write-only</access>
  10708. </field>
  10709. <field>
  10710. <name>COMP2_VALUE</name>
  10711. <description>Comparator 2 output status
  10712. bit</description>
  10713. <bitOffset>30</bitOffset>
  10714. <bitWidth>1</bitWidth>
  10715. <access>read-only</access>
  10716. </field>
  10717. <field>
  10718. <name>COMP2_POLARITY</name>
  10719. <description>Comparator 2 polarity selection
  10720. bit</description>
  10721. <bitOffset>15</bitOffset>
  10722. <bitWidth>1</bitWidth>
  10723. <access>read-write</access>
  10724. </field>
  10725. <field>
  10726. <name>COMP2_INP_SEL</name>
  10727. <description>Comparator 2 Input Plus connection
  10728. configuration bit</description>
  10729. <bitOffset>8</bitOffset>
  10730. <bitWidth>3</bitWidth>
  10731. <access>read-write</access>
  10732. </field>
  10733. <field>
  10734. <name>COMP2_INN_SEL</name>
  10735. <description>Comparator 2 Input Minus connection
  10736. configuration bit</description>
  10737. <bitOffset>4</bitOffset>
  10738. <bitWidth>3</bitWidth>
  10739. <access>read-write</access>
  10740. </field>
  10741. <field>
  10742. <name>COMP2_SPEED</name>
  10743. <description>Comparator 2 power mode selection
  10744. bit</description>
  10745. <bitOffset>3</bitOffset>
  10746. <bitWidth>1</bitWidth>
  10747. <access>read-write</access>
  10748. </field>
  10749. <field>
  10750. <name>COMP2_EN</name>
  10751. <description>Comparator 2 enable bit</description>
  10752. <bitOffset>0</bitOffset>
  10753. <bitWidth>1</bitWidth>
  10754. <access>read-write</access>
  10755. </field>
  10756. <field>
  10757. <name>COMP2_OUT_SEL</name>
  10758. <description>COMP2 output select</description>
  10759. <bitOffset>12</bitOffset>
  10760. <bitWidth>3</bitWidth>
  10761. <access>read-write</access>
  10762. </field>
  10763. </fields>
  10764. </register>
  10765. </registers>
  10766. </peripheral>
  10767. <peripheral>
  10768. <name>USB_FS</name>
  10769. <description>Universal serial bus full-speed device
  10770. interface</description>
  10771. <groupName>USB</groupName>
  10772. <baseAddress>0x40005C00</baseAddress>
  10773. <addressBlock>
  10774. <offset>0x0</offset>
  10775. <size>0x400</size>
  10776. <usage>registers</usage>
  10777. </addressBlock>
  10778. <interrupt>
  10779. <name>USB</name>
  10780. <description>USB event interrupt through
  10781. EXTI18</description>
  10782. <value>31</value>
  10783. </interrupt>
  10784. <registers>
  10785. <register>
  10786. <name>EP0R</name>
  10787. <displayName>EP0R</displayName>
  10788. <description>endpoint register</description>
  10789. <addressOffset>0x0</addressOffset>
  10790. <size>0x20</size>
  10791. <access>read-write</access>
  10792. <resetValue>0x0</resetValue>
  10793. <fields>
  10794. <field>
  10795. <name>CTR_RX</name>
  10796. <description>CTR_RX</description>
  10797. <bitOffset>15</bitOffset>
  10798. <bitWidth>1</bitWidth>
  10799. </field>
  10800. <field>
  10801. <name>DTOG_RX</name>
  10802. <description>DTOG_RX</description>
  10803. <bitOffset>14</bitOffset>
  10804. <bitWidth>1</bitWidth>
  10805. </field>
  10806. <field>
  10807. <name>STAT_RX</name>
  10808. <description>STAT_RX</description>
  10809. <bitOffset>12</bitOffset>
  10810. <bitWidth>2</bitWidth>
  10811. </field>
  10812. <field>
  10813. <name>SETUP</name>
  10814. <description>SETUP</description>
  10815. <bitOffset>11</bitOffset>
  10816. <bitWidth>1</bitWidth>
  10817. </field>
  10818. <field>
  10819. <name>EPTYPE</name>
  10820. <description>EPTYPE</description>
  10821. <bitOffset>9</bitOffset>
  10822. <bitWidth>2</bitWidth>
  10823. </field>
  10824. <field>
  10825. <name>EP_KIND</name>
  10826. <description>EP_KIND</description>
  10827. <bitOffset>8</bitOffset>
  10828. <bitWidth>1</bitWidth>
  10829. </field>
  10830. <field>
  10831. <name>CTR_TX</name>
  10832. <description>CTR_TX</description>
  10833. <bitOffset>7</bitOffset>
  10834. <bitWidth>1</bitWidth>
  10835. </field>
  10836. <field>
  10837. <name>DTOG_TX</name>
  10838. <description>DTOG_TX</description>
  10839. <bitOffset>6</bitOffset>
  10840. <bitWidth>1</bitWidth>
  10841. </field>
  10842. <field>
  10843. <name>STAT_TX</name>
  10844. <description>STAT_TX</description>
  10845. <bitOffset>4</bitOffset>
  10846. <bitWidth>2</bitWidth>
  10847. </field>
  10848. <field>
  10849. <name>EA</name>
  10850. <description>EA</description>
  10851. <bitOffset>0</bitOffset>
  10852. <bitWidth>4</bitWidth>
  10853. </field>
  10854. </fields>
  10855. </register>
  10856. <register>
  10857. <name>EP1R</name>
  10858. <displayName>EP1R</displayName>
  10859. <description>endpoint register</description>
  10860. <addressOffset>0x4</addressOffset>
  10861. <size>0x20</size>
  10862. <access>read-write</access>
  10863. <resetValue>0x0</resetValue>
  10864. <fields>
  10865. <field>
  10866. <name>CTR_RX</name>
  10867. <description>CTR_RX</description>
  10868. <bitOffset>15</bitOffset>
  10869. <bitWidth>1</bitWidth>
  10870. </field>
  10871. <field>
  10872. <name>DTOG_RX</name>
  10873. <description>DTOG_RX</description>
  10874. <bitOffset>14</bitOffset>
  10875. <bitWidth>1</bitWidth>
  10876. </field>
  10877. <field>
  10878. <name>STAT_RX</name>
  10879. <description>STAT_RX</description>
  10880. <bitOffset>12</bitOffset>
  10881. <bitWidth>2</bitWidth>
  10882. </field>
  10883. <field>
  10884. <name>SETUP</name>
  10885. <description>SETUP</description>
  10886. <bitOffset>11</bitOffset>
  10887. <bitWidth>1</bitWidth>
  10888. </field>
  10889. <field>
  10890. <name>EPTYPE</name>
  10891. <description>EPTYPE</description>
  10892. <bitOffset>9</bitOffset>
  10893. <bitWidth>2</bitWidth>
  10894. </field>
  10895. <field>
  10896. <name>EP_KIND</name>
  10897. <description>EP_KIND</description>
  10898. <bitOffset>8</bitOffset>
  10899. <bitWidth>1</bitWidth>
  10900. </field>
  10901. <field>
  10902. <name>CTR_TX</name>
  10903. <description>CTR_TX</description>
  10904. <bitOffset>7</bitOffset>
  10905. <bitWidth>1</bitWidth>
  10906. </field>
  10907. <field>
  10908. <name>DTOG_TX</name>
  10909. <description>DTOG_TX</description>
  10910. <bitOffset>6</bitOffset>
  10911. <bitWidth>1</bitWidth>
  10912. </field>
  10913. <field>
  10914. <name>STAT_TX</name>
  10915. <description>STAT_TX</description>
  10916. <bitOffset>4</bitOffset>
  10917. <bitWidth>2</bitWidth>
  10918. </field>
  10919. <field>
  10920. <name>EA</name>
  10921. <description>EA</description>
  10922. <bitOffset>0</bitOffset>
  10923. <bitWidth>4</bitWidth>
  10924. </field>
  10925. </fields>
  10926. </register>
  10927. <register>
  10928. <name>EP2R</name>
  10929. <displayName>EP2R</displayName>
  10930. <description>endpoint register</description>
  10931. <addressOffset>0x8</addressOffset>
  10932. <size>0x20</size>
  10933. <access>read-write</access>
  10934. <resetValue>0x0</resetValue>
  10935. <fields>
  10936. <field>
  10937. <name>CTR_RX</name>
  10938. <description>CTR_RX</description>
  10939. <bitOffset>15</bitOffset>
  10940. <bitWidth>1</bitWidth>
  10941. </field>
  10942. <field>
  10943. <name>DTOG_RX</name>
  10944. <description>DTOG_RX</description>
  10945. <bitOffset>14</bitOffset>
  10946. <bitWidth>1</bitWidth>
  10947. </field>
  10948. <field>
  10949. <name>STAT_RX</name>
  10950. <description>STAT_RX</description>
  10951. <bitOffset>12</bitOffset>
  10952. <bitWidth>2</bitWidth>
  10953. </field>
  10954. <field>
  10955. <name>SETUP</name>
  10956. <description>SETUP</description>
  10957. <bitOffset>11</bitOffset>
  10958. <bitWidth>1</bitWidth>
  10959. </field>
  10960. <field>
  10961. <name>EPTYPE</name>
  10962. <description>EPTYPE</description>
  10963. <bitOffset>9</bitOffset>
  10964. <bitWidth>2</bitWidth>
  10965. </field>
  10966. <field>
  10967. <name>EP_KIND</name>
  10968. <description>EP_KIND</description>
  10969. <bitOffset>8</bitOffset>
  10970. <bitWidth>1</bitWidth>
  10971. </field>
  10972. <field>
  10973. <name>CTR_TX</name>
  10974. <description>CTR_TX</description>
  10975. <bitOffset>7</bitOffset>
  10976. <bitWidth>1</bitWidth>
  10977. </field>
  10978. <field>
  10979. <name>DTOG_TX</name>
  10980. <description>DTOG_TX</description>
  10981. <bitOffset>6</bitOffset>
  10982. <bitWidth>1</bitWidth>
  10983. </field>
  10984. <field>
  10985. <name>STAT_TX</name>
  10986. <description>STAT_TX</description>
  10987. <bitOffset>4</bitOffset>
  10988. <bitWidth>2</bitWidth>
  10989. </field>
  10990. <field>
  10991. <name>EA</name>
  10992. <description>EA</description>
  10993. <bitOffset>0</bitOffset>
  10994. <bitWidth>4</bitWidth>
  10995. </field>
  10996. </fields>
  10997. </register>
  10998. <register>
  10999. <name>EP3R</name>
  11000. <displayName>EP3R</displayName>
  11001. <description>endpoint register</description>
  11002. <addressOffset>0xC</addressOffset>
  11003. <size>0x20</size>
  11004. <access>read-write</access>
  11005. <resetValue>0x0</resetValue>
  11006. <fields>
  11007. <field>
  11008. <name>CTR_RX</name>
  11009. <description>CTR_RX</description>
  11010. <bitOffset>15</bitOffset>
  11011. <bitWidth>1</bitWidth>
  11012. </field>
  11013. <field>
  11014. <name>DTOG_RX</name>
  11015. <description>DTOG_RX</description>
  11016. <bitOffset>14</bitOffset>
  11017. <bitWidth>1</bitWidth>
  11018. </field>
  11019. <field>
  11020. <name>STAT_RX</name>
  11021. <description>STAT_RX</description>
  11022. <bitOffset>12</bitOffset>
  11023. <bitWidth>2</bitWidth>
  11024. </field>
  11025. <field>
  11026. <name>SETUP</name>
  11027. <description>SETUP</description>
  11028. <bitOffset>11</bitOffset>
  11029. <bitWidth>1</bitWidth>
  11030. </field>
  11031. <field>
  11032. <name>EPTYPE</name>
  11033. <description>EPTYPE</description>
  11034. <bitOffset>9</bitOffset>
  11035. <bitWidth>2</bitWidth>
  11036. </field>
  11037. <field>
  11038. <name>EP_KIND</name>
  11039. <description>EP_KIND</description>
  11040. <bitOffset>8</bitOffset>
  11041. <bitWidth>1</bitWidth>
  11042. </field>
  11043. <field>
  11044. <name>CTR_TX</name>
  11045. <description>CTR_TX</description>
  11046. <bitOffset>7</bitOffset>
  11047. <bitWidth>1</bitWidth>
  11048. </field>
  11049. <field>
  11050. <name>DTOG_TX</name>
  11051. <description>DTOG_TX</description>
  11052. <bitOffset>6</bitOffset>
  11053. <bitWidth>1</bitWidth>
  11054. </field>
  11055. <field>
  11056. <name>STAT_TX</name>
  11057. <description>STAT_TX</description>
  11058. <bitOffset>4</bitOffset>
  11059. <bitWidth>2</bitWidth>
  11060. </field>
  11061. <field>
  11062. <name>EA</name>
  11063. <description>EA</description>
  11064. <bitOffset>0</bitOffset>
  11065. <bitWidth>4</bitWidth>
  11066. </field>
  11067. </fields>
  11068. </register>
  11069. <register>
  11070. <name>EP4R</name>
  11071. <displayName>EP4R</displayName>
  11072. <description>endpoint register</description>
  11073. <addressOffset>0x10</addressOffset>
  11074. <size>0x20</size>
  11075. <access>read-write</access>
  11076. <resetValue>0x0</resetValue>
  11077. <fields>
  11078. <field>
  11079. <name>CTR_RX</name>
  11080. <description>CTR_RX</description>
  11081. <bitOffset>15</bitOffset>
  11082. <bitWidth>1</bitWidth>
  11083. </field>
  11084. <field>
  11085. <name>DTOG_RX</name>
  11086. <description>DTOG_RX</description>
  11087. <bitOffset>14</bitOffset>
  11088. <bitWidth>1</bitWidth>
  11089. </field>
  11090. <field>
  11091. <name>STAT_RX</name>
  11092. <description>STAT_RX</description>
  11093. <bitOffset>12</bitOffset>
  11094. <bitWidth>2</bitWidth>
  11095. </field>
  11096. <field>
  11097. <name>SETUP</name>
  11098. <description>SETUP</description>
  11099. <bitOffset>11</bitOffset>
  11100. <bitWidth>1</bitWidth>
  11101. </field>
  11102. <field>
  11103. <name>EPTYPE</name>
  11104. <description>EPTYPE</description>
  11105. <bitOffset>9</bitOffset>
  11106. <bitWidth>2</bitWidth>
  11107. </field>
  11108. <field>
  11109. <name>EP_KIND</name>
  11110. <description>EP_KIND</description>
  11111. <bitOffset>8</bitOffset>
  11112. <bitWidth>1</bitWidth>
  11113. </field>
  11114. <field>
  11115. <name>CTR_TX</name>
  11116. <description>CTR_TX</description>
  11117. <bitOffset>7</bitOffset>
  11118. <bitWidth>1</bitWidth>
  11119. </field>
  11120. <field>
  11121. <name>DTOG_TX</name>
  11122. <description>DTOG_TX</description>
  11123. <bitOffset>6</bitOffset>
  11124. <bitWidth>1</bitWidth>
  11125. </field>
  11126. <field>
  11127. <name>STAT_TX</name>
  11128. <description>STAT_TX</description>
  11129. <bitOffset>4</bitOffset>
  11130. <bitWidth>2</bitWidth>
  11131. </field>
  11132. <field>
  11133. <name>EA</name>
  11134. <description>EA</description>
  11135. <bitOffset>0</bitOffset>
  11136. <bitWidth>4</bitWidth>
  11137. </field>
  11138. </fields>
  11139. </register>
  11140. <register>
  11141. <name>EP5R</name>
  11142. <displayName>EP5R</displayName>
  11143. <description>endpoint register</description>
  11144. <addressOffset>0x14</addressOffset>
  11145. <size>0x20</size>
  11146. <access>read-write</access>
  11147. <resetValue>0x0</resetValue>
  11148. <fields>
  11149. <field>
  11150. <name>CTR_RX</name>
  11151. <description>CTR_RX</description>
  11152. <bitOffset>15</bitOffset>
  11153. <bitWidth>1</bitWidth>
  11154. </field>
  11155. <field>
  11156. <name>DTOG_RX</name>
  11157. <description>DTOG_RX</description>
  11158. <bitOffset>14</bitOffset>
  11159. <bitWidth>1</bitWidth>
  11160. </field>
  11161. <field>
  11162. <name>STAT_RX</name>
  11163. <description>STAT_RX</description>
  11164. <bitOffset>12</bitOffset>
  11165. <bitWidth>2</bitWidth>
  11166. </field>
  11167. <field>
  11168. <name>SETUP</name>
  11169. <description>SETUP</description>
  11170. <bitOffset>11</bitOffset>
  11171. <bitWidth>1</bitWidth>
  11172. </field>
  11173. <field>
  11174. <name>EPTYPE</name>
  11175. <description>EPTYPE</description>
  11176. <bitOffset>9</bitOffset>
  11177. <bitWidth>2</bitWidth>
  11178. </field>
  11179. <field>
  11180. <name>EP_KIND</name>
  11181. <description>EP_KIND</description>
  11182. <bitOffset>8</bitOffset>
  11183. <bitWidth>1</bitWidth>
  11184. </field>
  11185. <field>
  11186. <name>CTR_TX</name>
  11187. <description>CTR_TX</description>
  11188. <bitOffset>7</bitOffset>
  11189. <bitWidth>1</bitWidth>
  11190. </field>
  11191. <field>
  11192. <name>DTOG_TX</name>
  11193. <description>DTOG_TX</description>
  11194. <bitOffset>6</bitOffset>
  11195. <bitWidth>1</bitWidth>
  11196. </field>
  11197. <field>
  11198. <name>STAT_TX</name>
  11199. <description>STAT_TX</description>
  11200. <bitOffset>4</bitOffset>
  11201. <bitWidth>2</bitWidth>
  11202. </field>
  11203. <field>
  11204. <name>EA</name>
  11205. <description>EA</description>
  11206. <bitOffset>0</bitOffset>
  11207. <bitWidth>4</bitWidth>
  11208. </field>
  11209. </fields>
  11210. </register>
  11211. <register>
  11212. <name>EP6R</name>
  11213. <displayName>EP6R</displayName>
  11214. <description>endpoint register</description>
  11215. <addressOffset>0x18</addressOffset>
  11216. <size>0x20</size>
  11217. <access>read-write</access>
  11218. <resetValue>0x0</resetValue>
  11219. <fields>
  11220. <field>
  11221. <name>CTR_RX</name>
  11222. <description>CTR_RX</description>
  11223. <bitOffset>15</bitOffset>
  11224. <bitWidth>1</bitWidth>
  11225. </field>
  11226. <field>
  11227. <name>DTOG_RX</name>
  11228. <description>DTOG_RX</description>
  11229. <bitOffset>14</bitOffset>
  11230. <bitWidth>1</bitWidth>
  11231. </field>
  11232. <field>
  11233. <name>STAT_RX</name>
  11234. <description>STAT_RX</description>
  11235. <bitOffset>12</bitOffset>
  11236. <bitWidth>2</bitWidth>
  11237. </field>
  11238. <field>
  11239. <name>SETUP</name>
  11240. <description>SETUP</description>
  11241. <bitOffset>11</bitOffset>
  11242. <bitWidth>1</bitWidth>
  11243. </field>
  11244. <field>
  11245. <name>EPTYPE</name>
  11246. <description>EPTYPE</description>
  11247. <bitOffset>9</bitOffset>
  11248. <bitWidth>2</bitWidth>
  11249. </field>
  11250. <field>
  11251. <name>EP_KIND</name>
  11252. <description>EP_KIND</description>
  11253. <bitOffset>8</bitOffset>
  11254. <bitWidth>1</bitWidth>
  11255. </field>
  11256. <field>
  11257. <name>CTR_TX</name>
  11258. <description>CTR_TX</description>
  11259. <bitOffset>7</bitOffset>
  11260. <bitWidth>1</bitWidth>
  11261. </field>
  11262. <field>
  11263. <name>DTOG_TX</name>
  11264. <description>DTOG_TX</description>
  11265. <bitOffset>6</bitOffset>
  11266. <bitWidth>1</bitWidth>
  11267. </field>
  11268. <field>
  11269. <name>STAT_TX</name>
  11270. <description>STAT_TX</description>
  11271. <bitOffset>4</bitOffset>
  11272. <bitWidth>2</bitWidth>
  11273. </field>
  11274. <field>
  11275. <name>EA</name>
  11276. <description>EA</description>
  11277. <bitOffset>0</bitOffset>
  11278. <bitWidth>4</bitWidth>
  11279. </field>
  11280. </fields>
  11281. </register>
  11282. <register>
  11283. <name>EP7R</name>
  11284. <displayName>EP7R</displayName>
  11285. <description>endpoint register</description>
  11286. <addressOffset>0x1C</addressOffset>
  11287. <size>0x20</size>
  11288. <access>read-write</access>
  11289. <resetValue>0x0</resetValue>
  11290. <fields>
  11291. <field>
  11292. <name>CTR_RX</name>
  11293. <description>CTR_RX</description>
  11294. <bitOffset>15</bitOffset>
  11295. <bitWidth>1</bitWidth>
  11296. </field>
  11297. <field>
  11298. <name>DTOG_RX</name>
  11299. <description>DTOG_RX</description>
  11300. <bitOffset>14</bitOffset>
  11301. <bitWidth>1</bitWidth>
  11302. </field>
  11303. <field>
  11304. <name>STAT_RX</name>
  11305. <description>STAT_RX</description>
  11306. <bitOffset>12</bitOffset>
  11307. <bitWidth>2</bitWidth>
  11308. </field>
  11309. <field>
  11310. <name>SETUP</name>
  11311. <description>SETUP</description>
  11312. <bitOffset>11</bitOffset>
  11313. <bitWidth>1</bitWidth>
  11314. </field>
  11315. <field>
  11316. <name>EPTYPE</name>
  11317. <description>EPTYPE</description>
  11318. <bitOffset>9</bitOffset>
  11319. <bitWidth>2</bitWidth>
  11320. </field>
  11321. <field>
  11322. <name>EP_KIND</name>
  11323. <description>EP_KIND</description>
  11324. <bitOffset>8</bitOffset>
  11325. <bitWidth>1</bitWidth>
  11326. </field>
  11327. <field>
  11328. <name>CTR_TX</name>
  11329. <description>CTR_TX</description>
  11330. <bitOffset>7</bitOffset>
  11331. <bitWidth>1</bitWidth>
  11332. </field>
  11333. <field>
  11334. <name>DTOG_TX</name>
  11335. <description>DTOG_TX</description>
  11336. <bitOffset>6</bitOffset>
  11337. <bitWidth>1</bitWidth>
  11338. </field>
  11339. <field>
  11340. <name>STAT_TX</name>
  11341. <description>STAT_TX</description>
  11342. <bitOffset>4</bitOffset>
  11343. <bitWidth>2</bitWidth>
  11344. </field>
  11345. <field>
  11346. <name>EA</name>
  11347. <description>EA</description>
  11348. <bitOffset>0</bitOffset>
  11349. <bitWidth>4</bitWidth>
  11350. </field>
  11351. </fields>
  11352. </register>
  11353. <register>
  11354. <name>CNTR</name>
  11355. <displayName>CNTR</displayName>
  11356. <description>control register</description>
  11357. <addressOffset>0x40</addressOffset>
  11358. <size>0x20</size>
  11359. <access>read-write</access>
  11360. <resetValue>0x0</resetValue>
  11361. <fields>
  11362. <field>
  11363. <name>CTRM</name>
  11364. <description>CTRM</description>
  11365. <bitOffset>15</bitOffset>
  11366. <bitWidth>1</bitWidth>
  11367. </field>
  11368. <field>
  11369. <name>PMAOVRM</name>
  11370. <description>PMAOVRM</description>
  11371. <bitOffset>14</bitOffset>
  11372. <bitWidth>1</bitWidth>
  11373. </field>
  11374. <field>
  11375. <name>ERRM</name>
  11376. <description>ERRM</description>
  11377. <bitOffset>13</bitOffset>
  11378. <bitWidth>1</bitWidth>
  11379. </field>
  11380. <field>
  11381. <name>WKUPM</name>
  11382. <description>WKUPM</description>
  11383. <bitOffset>12</bitOffset>
  11384. <bitWidth>1</bitWidth>
  11385. </field>
  11386. <field>
  11387. <name>SUSPM</name>
  11388. <description>SUSPM</description>
  11389. <bitOffset>11</bitOffset>
  11390. <bitWidth>1</bitWidth>
  11391. </field>
  11392. <field>
  11393. <name>RESETM</name>
  11394. <description>RESETM</description>
  11395. <bitOffset>10</bitOffset>
  11396. <bitWidth>1</bitWidth>
  11397. </field>
  11398. <field>
  11399. <name>SOFM</name>
  11400. <description>SOFM</description>
  11401. <bitOffset>9</bitOffset>
  11402. <bitWidth>1</bitWidth>
  11403. </field>
  11404. <field>
  11405. <name>ESOFM</name>
  11406. <description>ESOFM</description>
  11407. <bitOffset>8</bitOffset>
  11408. <bitWidth>1</bitWidth>
  11409. </field>
  11410. <field>
  11411. <name>L1REQM</name>
  11412. <description>L1REQM</description>
  11413. <bitOffset>7</bitOffset>
  11414. <bitWidth>1</bitWidth>
  11415. </field>
  11416. <field>
  11417. <name>L1RESUME</name>
  11418. <description>L1RESUME</description>
  11419. <bitOffset>5</bitOffset>
  11420. <bitWidth>1</bitWidth>
  11421. </field>
  11422. <field>
  11423. <name>RESUME</name>
  11424. <description>RESUME</description>
  11425. <bitOffset>4</bitOffset>
  11426. <bitWidth>1</bitWidth>
  11427. </field>
  11428. <field>
  11429. <name>FSUSP</name>
  11430. <description>FSUSP</description>
  11431. <bitOffset>3</bitOffset>
  11432. <bitWidth>1</bitWidth>
  11433. </field>
  11434. <field>
  11435. <name>LPMODE</name>
  11436. <description>LPMODE</description>
  11437. <bitOffset>2</bitOffset>
  11438. <bitWidth>1</bitWidth>
  11439. </field>
  11440. <field>
  11441. <name>PDWN</name>
  11442. <description>PDWN</description>
  11443. <bitOffset>1</bitOffset>
  11444. <bitWidth>1</bitWidth>
  11445. </field>
  11446. <field>
  11447. <name>FRES</name>
  11448. <description>FRES</description>
  11449. <bitOffset>0</bitOffset>
  11450. <bitWidth>1</bitWidth>
  11451. </field>
  11452. </fields>
  11453. </register>
  11454. <register>
  11455. <name>ISTR</name>
  11456. <displayName>ISTR</displayName>
  11457. <description>interrupt status register</description>
  11458. <addressOffset>0x44</addressOffset>
  11459. <size>0x20</size>
  11460. <access>read-write</access>
  11461. <resetValue>0x0</resetValue>
  11462. <fields>
  11463. <field>
  11464. <name>CTR</name>
  11465. <description>CTR</description>
  11466. <bitOffset>15</bitOffset>
  11467. <bitWidth>1</bitWidth>
  11468. </field>
  11469. <field>
  11470. <name>PMAOVR</name>
  11471. <description>PMAOVR</description>
  11472. <bitOffset>14</bitOffset>
  11473. <bitWidth>1</bitWidth>
  11474. </field>
  11475. <field>
  11476. <name>ERR</name>
  11477. <description>ERR</description>
  11478. <bitOffset>13</bitOffset>
  11479. <bitWidth>1</bitWidth>
  11480. </field>
  11481. <field>
  11482. <name>WKUP</name>
  11483. <description>WKUP</description>
  11484. <bitOffset>12</bitOffset>
  11485. <bitWidth>1</bitWidth>
  11486. </field>
  11487. <field>
  11488. <name>SUSP</name>
  11489. <description>SUSP</description>
  11490. <bitOffset>11</bitOffset>
  11491. <bitWidth>1</bitWidth>
  11492. </field>
  11493. <field>
  11494. <name>RESET</name>
  11495. <description>RESET</description>
  11496. <bitOffset>10</bitOffset>
  11497. <bitWidth>1</bitWidth>
  11498. </field>
  11499. <field>
  11500. <name>SOF</name>
  11501. <description>SOF</description>
  11502. <bitOffset>9</bitOffset>
  11503. <bitWidth>1</bitWidth>
  11504. </field>
  11505. <field>
  11506. <name>ESOF</name>
  11507. <description>ESOF</description>
  11508. <bitOffset>8</bitOffset>
  11509. <bitWidth>1</bitWidth>
  11510. </field>
  11511. <field>
  11512. <name>L1REQ</name>
  11513. <description>L1REQ</description>
  11514. <bitOffset>7</bitOffset>
  11515. <bitWidth>1</bitWidth>
  11516. </field>
  11517. <field>
  11518. <name>DIR</name>
  11519. <description>DIR</description>
  11520. <bitOffset>4</bitOffset>
  11521. <bitWidth>1</bitWidth>
  11522. </field>
  11523. <field>
  11524. <name>EP_ID</name>
  11525. <description>EP_ID</description>
  11526. <bitOffset>0</bitOffset>
  11527. <bitWidth>4</bitWidth>
  11528. </field>
  11529. </fields>
  11530. </register>
  11531. <register>
  11532. <name>FNR</name>
  11533. <displayName>FNR</displayName>
  11534. <description>frame number register</description>
  11535. <addressOffset>0x48</addressOffset>
  11536. <size>0x20</size>
  11537. <access>read-only</access>
  11538. <resetValue>0x0</resetValue>
  11539. <fields>
  11540. <field>
  11541. <name>RXDP</name>
  11542. <description>RXDP</description>
  11543. <bitOffset>15</bitOffset>
  11544. <bitWidth>1</bitWidth>
  11545. </field>
  11546. <field>
  11547. <name>RXDM</name>
  11548. <description>RXDM</description>
  11549. <bitOffset>14</bitOffset>
  11550. <bitWidth>1</bitWidth>
  11551. </field>
  11552. <field>
  11553. <name>LCK</name>
  11554. <description>LCK</description>
  11555. <bitOffset>13</bitOffset>
  11556. <bitWidth>1</bitWidth>
  11557. </field>
  11558. <field>
  11559. <name>LSOF</name>
  11560. <description>LSOF</description>
  11561. <bitOffset>11</bitOffset>
  11562. <bitWidth>2</bitWidth>
  11563. </field>
  11564. <field>
  11565. <name>FN</name>
  11566. <description>FN</description>
  11567. <bitOffset>0</bitOffset>
  11568. <bitWidth>11</bitWidth>
  11569. </field>
  11570. </fields>
  11571. </register>
  11572. <register>
  11573. <name>DADDR</name>
  11574. <displayName>DADDR</displayName>
  11575. <description>device address</description>
  11576. <addressOffset>0x4C</addressOffset>
  11577. <size>0x20</size>
  11578. <access>read-write</access>
  11579. <resetValue>0x0</resetValue>
  11580. <fields>
  11581. <field>
  11582. <name>EF</name>
  11583. <description>EF</description>
  11584. <bitOffset>7</bitOffset>
  11585. <bitWidth>1</bitWidth>
  11586. </field>
  11587. <field>
  11588. <name>ADD</name>
  11589. <description>ADD</description>
  11590. <bitOffset>0</bitOffset>
  11591. <bitWidth>7</bitWidth>
  11592. </field>
  11593. </fields>
  11594. </register>
  11595. <register>
  11596. <name>BTABLE</name>
  11597. <displayName>BTABLE</displayName>
  11598. <description>Buffer table address</description>
  11599. <addressOffset>0x50</addressOffset>
  11600. <size>0x20</size>
  11601. <access>read-write</access>
  11602. <resetValue>0x0</resetValue>
  11603. <fields>
  11604. <field>
  11605. <name>BTABLE</name>
  11606. <description>BTABLE</description>
  11607. <bitOffset>3</bitOffset>
  11608. <bitWidth>13</bitWidth>
  11609. </field>
  11610. </fields>
  11611. </register>
  11612. <register>
  11613. <name>LPMCSR</name>
  11614. <displayName>LPMCSR</displayName>
  11615. <description>LPM control and status
  11616. register</description>
  11617. <addressOffset>0x54</addressOffset>
  11618. <size>0x20</size>
  11619. <resetValue>0x0</resetValue>
  11620. <fields>
  11621. <field>
  11622. <name>BESL</name>
  11623. <description>BESL</description>
  11624. <bitOffset>4</bitOffset>
  11625. <bitWidth>4</bitWidth>
  11626. <access>read-only</access>
  11627. </field>
  11628. <field>
  11629. <name>REMWAKE</name>
  11630. <description>REMWAKE</description>
  11631. <bitOffset>3</bitOffset>
  11632. <bitWidth>1</bitWidth>
  11633. <access>read-only</access>
  11634. </field>
  11635. <field>
  11636. <name>LPMACK</name>
  11637. <description>LPMACK</description>
  11638. <bitOffset>1</bitOffset>
  11639. <bitWidth>1</bitWidth>
  11640. <access>read-write</access>
  11641. </field>
  11642. <field>
  11643. <name>LPMEN</name>
  11644. <description>LPMEN</description>
  11645. <bitOffset>0</bitOffset>
  11646. <bitWidth>1</bitWidth>
  11647. <access>read-write</access>
  11648. </field>
  11649. </fields>
  11650. </register>
  11651. <register>
  11652. <name>BCDR</name>
  11653. <displayName>BCDR</displayName>
  11654. <description>Battery charging detector</description>
  11655. <addressOffset>0x58</addressOffset>
  11656. <size>0x20</size>
  11657. <resetValue>0x0</resetValue>
  11658. <fields>
  11659. <field>
  11660. <name>DPPU</name>
  11661. <description>DPPU</description>
  11662. <bitOffset>15</bitOffset>
  11663. <bitWidth>1</bitWidth>
  11664. <access>read-write</access>
  11665. </field>
  11666. <field>
  11667. <name>PS2DET</name>
  11668. <description>PS2DET</description>
  11669. <bitOffset>7</bitOffset>
  11670. <bitWidth>1</bitWidth>
  11671. <access>read-only</access>
  11672. </field>
  11673. <field>
  11674. <name>SDET</name>
  11675. <description>SDET</description>
  11676. <bitOffset>6</bitOffset>
  11677. <bitWidth>1</bitWidth>
  11678. <access>read-only</access>
  11679. </field>
  11680. <field>
  11681. <name>PDET</name>
  11682. <description>PDET</description>
  11683. <bitOffset>5</bitOffset>
  11684. <bitWidth>1</bitWidth>
  11685. <access>read-only</access>
  11686. </field>
  11687. <field>
  11688. <name>DCDET</name>
  11689. <description>DCDET</description>
  11690. <bitOffset>4</bitOffset>
  11691. <bitWidth>1</bitWidth>
  11692. <access>read-only</access>
  11693. </field>
  11694. <field>
  11695. <name>SDEN</name>
  11696. <description>SDEN</description>
  11697. <bitOffset>3</bitOffset>
  11698. <bitWidth>1</bitWidth>
  11699. <access>read-write</access>
  11700. </field>
  11701. <field>
  11702. <name>PDEN</name>
  11703. <description>PDEN</description>
  11704. <bitOffset>2</bitOffset>
  11705. <bitWidth>1</bitWidth>
  11706. <access>read-write</access>
  11707. </field>
  11708. <field>
  11709. <name>DCDEN</name>
  11710. <description>DCDEN</description>
  11711. <bitOffset>1</bitOffset>
  11712. <bitWidth>1</bitWidth>
  11713. <access>read-write</access>
  11714. </field>
  11715. <field>
  11716. <name>BCDEN</name>
  11717. <description>BCDEN</description>
  11718. <bitOffset>0</bitOffset>
  11719. <bitWidth>1</bitWidth>
  11720. <access>read-write</access>
  11721. </field>
  11722. </fields>
  11723. </register>
  11724. </registers>
  11725. </peripheral>
  11726. <peripheral>
  11727. <name>CRS</name>
  11728. <description>Clock recovery system</description>
  11729. <groupName>CRS</groupName>
  11730. <baseAddress>0x40006C00</baseAddress>
  11731. <addressBlock>
  11732. <offset>0x0</offset>
  11733. <size>0x400</size>
  11734. <usage>registers</usage>
  11735. </addressBlock>
  11736. <registers>
  11737. <register>
  11738. <name>CR</name>
  11739. <displayName>CR</displayName>
  11740. <description>control register</description>
  11741. <addressOffset>0x0</addressOffset>
  11742. <size>0x20</size>
  11743. <access>read-write</access>
  11744. <resetValue>0x00002000</resetValue>
  11745. <fields>
  11746. <field>
  11747. <name>TRIM</name>
  11748. <description>HSI48 oscillator smooth
  11749. trimming</description>
  11750. <bitOffset>8</bitOffset>
  11751. <bitWidth>6</bitWidth>
  11752. </field>
  11753. <field>
  11754. <name>SWSYNC</name>
  11755. <description>Generate software SYNC
  11756. event</description>
  11757. <bitOffset>7</bitOffset>
  11758. <bitWidth>1</bitWidth>
  11759. </field>
  11760. <field>
  11761. <name>AUTOTRIMEN</name>
  11762. <description>Automatic trimming enable</description>
  11763. <bitOffset>6</bitOffset>
  11764. <bitWidth>1</bitWidth>
  11765. </field>
  11766. <field>
  11767. <name>CEN</name>
  11768. <description>Frequency error counter
  11769. enable</description>
  11770. <bitOffset>5</bitOffset>
  11771. <bitWidth>1</bitWidth>
  11772. </field>
  11773. <field>
  11774. <name>ESYNCIE</name>
  11775. <description>Expected SYNC interrupt
  11776. enable</description>
  11777. <bitOffset>3</bitOffset>
  11778. <bitWidth>1</bitWidth>
  11779. </field>
  11780. <field>
  11781. <name>ERRIE</name>
  11782. <description>Synchronization or trimming error
  11783. interrupt enable</description>
  11784. <bitOffset>2</bitOffset>
  11785. <bitWidth>1</bitWidth>
  11786. </field>
  11787. <field>
  11788. <name>SYNCWARNIE</name>
  11789. <description>SYNC warning interrupt
  11790. enable</description>
  11791. <bitOffset>1</bitOffset>
  11792. <bitWidth>1</bitWidth>
  11793. </field>
  11794. <field>
  11795. <name>SYNCOKIE</name>
  11796. <description>SYNC event OK interrupt
  11797. enable</description>
  11798. <bitOffset>0</bitOffset>
  11799. <bitWidth>1</bitWidth>
  11800. </field>
  11801. </fields>
  11802. </register>
  11803. <register>
  11804. <name>CFGR</name>
  11805. <displayName>CFGR</displayName>
  11806. <description>configuration register</description>
  11807. <addressOffset>0x4</addressOffset>
  11808. <size>0x20</size>
  11809. <access>read-write</access>
  11810. <resetValue>0x2022BB7F</resetValue>
  11811. <fields>
  11812. <field>
  11813. <name>SYNCPOL</name>
  11814. <description>SYNC polarity selection</description>
  11815. <bitOffset>31</bitOffset>
  11816. <bitWidth>1</bitWidth>
  11817. </field>
  11818. <field>
  11819. <name>SYNCSRC</name>
  11820. <description>SYNC signal source
  11821. selection</description>
  11822. <bitOffset>28</bitOffset>
  11823. <bitWidth>2</bitWidth>
  11824. </field>
  11825. <field>
  11826. <name>SYNCDIV</name>
  11827. <description>SYNC divider</description>
  11828. <bitOffset>24</bitOffset>
  11829. <bitWidth>3</bitWidth>
  11830. </field>
  11831. <field>
  11832. <name>FELIM</name>
  11833. <description>Frequency error limit</description>
  11834. <bitOffset>16</bitOffset>
  11835. <bitWidth>8</bitWidth>
  11836. </field>
  11837. <field>
  11838. <name>RELOAD</name>
  11839. <description>Counter reload value</description>
  11840. <bitOffset>0</bitOffset>
  11841. <bitWidth>16</bitWidth>
  11842. </field>
  11843. </fields>
  11844. </register>
  11845. <register>
  11846. <name>ISR</name>
  11847. <displayName>ISR</displayName>
  11848. <description>interrupt and status register</description>
  11849. <addressOffset>0x8</addressOffset>
  11850. <size>0x20</size>
  11851. <access>read-only</access>
  11852. <resetValue>0x00000000</resetValue>
  11853. <fields>
  11854. <field>
  11855. <name>FECAP</name>
  11856. <description>Frequency error capture</description>
  11857. <bitOffset>16</bitOffset>
  11858. <bitWidth>16</bitWidth>
  11859. </field>
  11860. <field>
  11861. <name>FEDIR</name>
  11862. <description>Frequency error direction</description>
  11863. <bitOffset>15</bitOffset>
  11864. <bitWidth>1</bitWidth>
  11865. </field>
  11866. <field>
  11867. <name>TRIMOVF</name>
  11868. <description>Trimming overflow or
  11869. underflow</description>
  11870. <bitOffset>10</bitOffset>
  11871. <bitWidth>1</bitWidth>
  11872. </field>
  11873. <field>
  11874. <name>SYNCMISS</name>
  11875. <description>SYNC missed</description>
  11876. <bitOffset>9</bitOffset>
  11877. <bitWidth>1</bitWidth>
  11878. </field>
  11879. <field>
  11880. <name>SYNCERR</name>
  11881. <description>SYNC error</description>
  11882. <bitOffset>8</bitOffset>
  11883. <bitWidth>1</bitWidth>
  11884. </field>
  11885. <field>
  11886. <name>ESYNCF</name>
  11887. <description>Expected SYNC flag</description>
  11888. <bitOffset>3</bitOffset>
  11889. <bitWidth>1</bitWidth>
  11890. </field>
  11891. <field>
  11892. <name>ERRF</name>
  11893. <description>Error flag</description>
  11894. <bitOffset>2</bitOffset>
  11895. <bitWidth>1</bitWidth>
  11896. </field>
  11897. <field>
  11898. <name>SYNCWARNF</name>
  11899. <description>SYNC warning flag</description>
  11900. <bitOffset>1</bitOffset>
  11901. <bitWidth>1</bitWidth>
  11902. </field>
  11903. <field>
  11904. <name>SYNCOKF</name>
  11905. <description>SYNC event OK flag</description>
  11906. <bitOffset>0</bitOffset>
  11907. <bitWidth>1</bitWidth>
  11908. </field>
  11909. </fields>
  11910. </register>
  11911. <register>
  11912. <name>ICR</name>
  11913. <displayName>ICR</displayName>
  11914. <description>interrupt flag clear register</description>
  11915. <addressOffset>0xC</addressOffset>
  11916. <size>0x20</size>
  11917. <access>read-write</access>
  11918. <resetValue>0x00000000</resetValue>
  11919. <fields>
  11920. <field>
  11921. <name>ESYNCC</name>
  11922. <description>Expected SYNC clear flag</description>
  11923. <bitOffset>3</bitOffset>
  11924. <bitWidth>1</bitWidth>
  11925. </field>
  11926. <field>
  11927. <name>ERRC</name>
  11928. <description>Error clear flag</description>
  11929. <bitOffset>2</bitOffset>
  11930. <bitWidth>1</bitWidth>
  11931. </field>
  11932. <field>
  11933. <name>SYNCWARNC</name>
  11934. <description>SYNC warning clear flag</description>
  11935. <bitOffset>1</bitOffset>
  11936. <bitWidth>1</bitWidth>
  11937. </field>
  11938. <field>
  11939. <name>SYNCOKC</name>
  11940. <description>SYNC event OK clear flag</description>
  11941. <bitOffset>0</bitOffset>
  11942. <bitWidth>1</bitWidth>
  11943. </field>
  11944. </fields>
  11945. </register>
  11946. </registers>
  11947. </peripheral>
  11948. <peripheral>
  11949. <name>Firewall</name>
  11950. <description>Firewall</description>
  11951. <groupName>Firewall</groupName>
  11952. <baseAddress>0x40011C00</baseAddress>
  11953. <addressBlock>
  11954. <offset>0x0</offset>
  11955. <size>0x400</size>
  11956. <usage>registers</usage>
  11957. </addressBlock>
  11958. <registers>
  11959. <register>
  11960. <name>FIREWALL_CSSA</name>
  11961. <displayName>FIREWALL_CSSA</displayName>
  11962. <description>Code segment start address</description>
  11963. <addressOffset>0x0</addressOffset>
  11964. <size>0x20</size>
  11965. <access>read-write</access>
  11966. <resetValue>0x00000000</resetValue>
  11967. <fields>
  11968. <field>
  11969. <name>ADD</name>
  11970. <description>code segment start address</description>
  11971. <bitOffset>8</bitOffset>
  11972. <bitWidth>16</bitWidth>
  11973. </field>
  11974. </fields>
  11975. </register>
  11976. <register>
  11977. <name>FIREWALL_CSL</name>
  11978. <displayName>FIREWALL_CSL</displayName>
  11979. <description>Code segment length</description>
  11980. <addressOffset>0x4</addressOffset>
  11981. <size>0x20</size>
  11982. <access>read-write</access>
  11983. <resetValue>0x00000000</resetValue>
  11984. <fields>
  11985. <field>
  11986. <name>LENG</name>
  11987. <description>code segment length</description>
  11988. <bitOffset>8</bitOffset>
  11989. <bitWidth>14</bitWidth>
  11990. </field>
  11991. </fields>
  11992. </register>
  11993. <register>
  11994. <name>FIREWALL_NVDSSA</name>
  11995. <displayName>FIREWALL_NVDSSA</displayName>
  11996. <description>Non-volatile data segment start
  11997. address</description>
  11998. <addressOffset>0x8</addressOffset>
  11999. <size>0x20</size>
  12000. <access>read-write</access>
  12001. <resetValue>0x00000000</resetValue>
  12002. <fields>
  12003. <field>
  12004. <name>ADD</name>
  12005. <description>Non-volatile data segment start
  12006. address</description>
  12007. <bitOffset>8</bitOffset>
  12008. <bitWidth>16</bitWidth>
  12009. </field>
  12010. </fields>
  12011. </register>
  12012. <register>
  12013. <name>FIREWALL_NVDSL</name>
  12014. <displayName>FIREWALL_NVDSL</displayName>
  12015. <description>Non-volatile data segment
  12016. length</description>
  12017. <addressOffset>0xC</addressOffset>
  12018. <size>0x20</size>
  12019. <access>read-write</access>
  12020. <resetValue>0x00000000</resetValue>
  12021. <fields>
  12022. <field>
  12023. <name>LENG</name>
  12024. <description>Non-volatile data segment
  12025. length</description>
  12026. <bitOffset>8</bitOffset>
  12027. <bitWidth>14</bitWidth>
  12028. </field>
  12029. </fields>
  12030. </register>
  12031. <register>
  12032. <name>FIREWALL_VDSSA</name>
  12033. <displayName>FIREWALL_VDSSA</displayName>
  12034. <description>Volatile data segment start
  12035. address</description>
  12036. <addressOffset>0x10</addressOffset>
  12037. <size>0x20</size>
  12038. <access>read-write</access>
  12039. <resetValue>0x00000000</resetValue>
  12040. <fields>
  12041. <field>
  12042. <name>ADD</name>
  12043. <description>Volatile data segment start
  12044. address</description>
  12045. <bitOffset>6</bitOffset>
  12046. <bitWidth>10</bitWidth>
  12047. </field>
  12048. </fields>
  12049. </register>
  12050. <register>
  12051. <name>FIREWALL_VDSL</name>
  12052. <displayName>FIREWALL_VDSL</displayName>
  12053. <description>Volatile data segment length</description>
  12054. <addressOffset>0x14</addressOffset>
  12055. <size>0x20</size>
  12056. <access>read-write</access>
  12057. <resetValue>0x00000000</resetValue>
  12058. <fields>
  12059. <field>
  12060. <name>LENG</name>
  12061. <description>Non-volatile data segment
  12062. length</description>
  12063. <bitOffset>6</bitOffset>
  12064. <bitWidth>10</bitWidth>
  12065. </field>
  12066. </fields>
  12067. </register>
  12068. <register>
  12069. <name>FIREWALL_CR</name>
  12070. <displayName>FIREWALL_CR</displayName>
  12071. <description>Configuration register</description>
  12072. <addressOffset>0x20</addressOffset>
  12073. <size>0x20</size>
  12074. <access>read-write</access>
  12075. <resetValue>0x00000000</resetValue>
  12076. <fields>
  12077. <field>
  12078. <name>VDE</name>
  12079. <description>Volatile data execution</description>
  12080. <bitOffset>2</bitOffset>
  12081. <bitWidth>1</bitWidth>
  12082. </field>
  12083. <field>
  12084. <name>VDS</name>
  12085. <description>Volatile data shared</description>
  12086. <bitOffset>1</bitOffset>
  12087. <bitWidth>1</bitWidth>
  12088. </field>
  12089. <field>
  12090. <name>FPA</name>
  12091. <description>Firewall pre alarm</description>
  12092. <bitOffset>0</bitOffset>
  12093. <bitWidth>1</bitWidth>
  12094. </field>
  12095. </fields>
  12096. </register>
  12097. </registers>
  12098. </peripheral>
  12099. <peripheral>
  12100. <name>RCC</name>
  12101. <description>Reset and clock control</description>
  12102. <groupName>RCC</groupName>
  12103. <baseAddress>0x40021000</baseAddress>
  12104. <addressBlock>
  12105. <offset>0x0</offset>
  12106. <size>0x400</size>
  12107. <usage>registers</usage>
  12108. </addressBlock>
  12109. <interrupt>
  12110. <name>RCC</name>
  12111. <description>RCC global interrupt</description>
  12112. <value>4</value>
  12113. </interrupt>
  12114. <registers>
  12115. <register>
  12116. <name>CR</name>
  12117. <displayName>CR</displayName>
  12118. <description>Clock control register</description>
  12119. <addressOffset>0x0</addressOffset>
  12120. <size>0x20</size>
  12121. <resetValue>0x00000300</resetValue>
  12122. <fields>
  12123. <field>
  12124. <name>PLLRDY</name>
  12125. <description>PLL clock ready flag</description>
  12126. <bitOffset>25</bitOffset>
  12127. <bitWidth>1</bitWidth>
  12128. <access>read-only</access>
  12129. </field>
  12130. <field>
  12131. <name>PLLON</name>
  12132. <description>PLL enable bit</description>
  12133. <bitOffset>24</bitOffset>
  12134. <bitWidth>1</bitWidth>
  12135. <access>read-write</access>
  12136. </field>
  12137. <field>
  12138. <name>RTCPRE</name>
  12139. <description>TC/LCD prescaler</description>
  12140. <bitOffset>20</bitOffset>
  12141. <bitWidth>2</bitWidth>
  12142. <access>read-write</access>
  12143. </field>
  12144. <field>
  12145. <name>CSSLSEON</name>
  12146. <description>Clock security system on HSE enable
  12147. bit</description>
  12148. <bitOffset>19</bitOffset>
  12149. <bitWidth>1</bitWidth>
  12150. <access>read-write</access>
  12151. </field>
  12152. <field>
  12153. <name>HSEBYP</name>
  12154. <description>HSE clock bypass bit</description>
  12155. <bitOffset>18</bitOffset>
  12156. <bitWidth>1</bitWidth>
  12157. <access>read-write</access>
  12158. </field>
  12159. <field>
  12160. <name>HSERDY</name>
  12161. <description>HSE clock ready flag</description>
  12162. <bitOffset>17</bitOffset>
  12163. <bitWidth>1</bitWidth>
  12164. <access>read-only</access>
  12165. </field>
  12166. <field>
  12167. <name>HSEON</name>
  12168. <description>HSE clock enable bit</description>
  12169. <bitOffset>16</bitOffset>
  12170. <bitWidth>1</bitWidth>
  12171. <access>read-write</access>
  12172. </field>
  12173. <field>
  12174. <name>MSIRDY</name>
  12175. <description>MSI clock ready flag</description>
  12176. <bitOffset>9</bitOffset>
  12177. <bitWidth>1</bitWidth>
  12178. <access>read-only</access>
  12179. </field>
  12180. <field>
  12181. <name>MSION</name>
  12182. <description>MSI clock enable bit</description>
  12183. <bitOffset>8</bitOffset>
  12184. <bitWidth>1</bitWidth>
  12185. <access>read-write</access>
  12186. </field>
  12187. <field>
  12188. <name>HSI16DIVF</name>
  12189. <description>HSI16DIVF</description>
  12190. <bitOffset>4</bitOffset>
  12191. <bitWidth>1</bitWidth>
  12192. <access>read-only</access>
  12193. </field>
  12194. <field>
  12195. <name>HSI16DIVEN</name>
  12196. <description>HSI16DIVEN</description>
  12197. <bitOffset>3</bitOffset>
  12198. <bitWidth>1</bitWidth>
  12199. <access>read-write</access>
  12200. </field>
  12201. <field>
  12202. <name>HSI16RDYF</name>
  12203. <description>Internal high-speed clock ready
  12204. flag</description>
  12205. <bitOffset>2</bitOffset>
  12206. <bitWidth>1</bitWidth>
  12207. <access>read-write</access>
  12208. </field>
  12209. <field>
  12210. <name>HSI16KERON</name>
  12211. <description>High-speed internal clock enable bit for
  12212. some IP kernels</description>
  12213. <bitOffset>1</bitOffset>
  12214. <bitWidth>1</bitWidth>
  12215. <access>read-only</access>
  12216. </field>
  12217. <field>
  12218. <name>HSI16ON</name>
  12219. <description>16 MHz high-speed internal clock
  12220. enable</description>
  12221. <bitOffset>0</bitOffset>
  12222. <bitWidth>1</bitWidth>
  12223. <access>read-write</access>
  12224. </field>
  12225. </fields>
  12226. </register>
  12227. <register>
  12228. <name>ICSCR</name>
  12229. <displayName>ICSCR</displayName>
  12230. <description>Internal clock sources calibration
  12231. register</description>
  12232. <addressOffset>0x4</addressOffset>
  12233. <size>0x20</size>
  12234. <resetValue>0x0000B000</resetValue>
  12235. <fields>
  12236. <field>
  12237. <name>MSITRIM</name>
  12238. <description>MSI clock trimming</description>
  12239. <bitOffset>24</bitOffset>
  12240. <bitWidth>8</bitWidth>
  12241. <access>read-write</access>
  12242. </field>
  12243. <field>
  12244. <name>MSICAL</name>
  12245. <description>MSI clock calibration</description>
  12246. <bitOffset>16</bitOffset>
  12247. <bitWidth>8</bitWidth>
  12248. <access>read-only</access>
  12249. </field>
  12250. <field>
  12251. <name>MSIRANGE</name>
  12252. <description>MSI clock ranges</description>
  12253. <bitOffset>13</bitOffset>
  12254. <bitWidth>3</bitWidth>
  12255. <access>read-write</access>
  12256. </field>
  12257. <field>
  12258. <name>HSI16TRIM</name>
  12259. <description>High speed internal clock
  12260. trimming</description>
  12261. <bitOffset>8</bitOffset>
  12262. <bitWidth>5</bitWidth>
  12263. <access>read-write</access>
  12264. </field>
  12265. <field>
  12266. <name>HSI16CAL</name>
  12267. <description>nternal high speed clock
  12268. calibration</description>
  12269. <bitOffset>0</bitOffset>
  12270. <bitWidth>8</bitWidth>
  12271. <access>read-only</access>
  12272. </field>
  12273. </fields>
  12274. </register>
  12275. <register>
  12276. <name>CRRCR</name>
  12277. <displayName>CRRCR</displayName>
  12278. <description>Clock recovery RC register</description>
  12279. <addressOffset>0x8</addressOffset>
  12280. <size>0x20</size>
  12281. <resetValue>0x00000000</resetValue>
  12282. <fields>
  12283. <field>
  12284. <name>HSI48CAL</name>
  12285. <description>48 MHz HSI clock
  12286. calibration</description>
  12287. <bitOffset>8</bitOffset>
  12288. <bitWidth>8</bitWidth>
  12289. <access>read-only</access>
  12290. </field>
  12291. <field>
  12292. <name>HSI48RDY</name>
  12293. <description>48MHz HSI clock ready flag</description>
  12294. <bitOffset>1</bitOffset>
  12295. <bitWidth>1</bitWidth>
  12296. <access>read-only</access>
  12297. </field>
  12298. <field>
  12299. <name>HSI48ON</name>
  12300. <description>48MHz HSI clock enable bit</description>
  12301. <bitOffset>0</bitOffset>
  12302. <bitWidth>1</bitWidth>
  12303. <access>read-write</access>
  12304. </field>
  12305. </fields>
  12306. </register>
  12307. <register>
  12308. <name>CFGR</name>
  12309. <displayName>CFGR</displayName>
  12310. <description>Clock configuration register</description>
  12311. <addressOffset>0xC</addressOffset>
  12312. <size>0x20</size>
  12313. <resetValue>0x00000000</resetValue>
  12314. <fields>
  12315. <field>
  12316. <name>MCOPRE</name>
  12317. <description>Microcontroller clock output
  12318. prescaler</description>
  12319. <bitOffset>28</bitOffset>
  12320. <bitWidth>3</bitWidth>
  12321. <access>read-write</access>
  12322. </field>
  12323. <field>
  12324. <name>MCOSEL</name>
  12325. <description>Microcontroller clock output
  12326. selection</description>
  12327. <bitOffset>24</bitOffset>
  12328. <bitWidth>3</bitWidth>
  12329. <access>read-write</access>
  12330. </field>
  12331. <field>
  12332. <name>PLLDIV</name>
  12333. <description>PLL output division</description>
  12334. <bitOffset>22</bitOffset>
  12335. <bitWidth>2</bitWidth>
  12336. <access>read-write</access>
  12337. </field>
  12338. <field>
  12339. <name>PLLMUL</name>
  12340. <description>PLL multiplication factor</description>
  12341. <bitOffset>18</bitOffset>
  12342. <bitWidth>4</bitWidth>
  12343. <access>read-write</access>
  12344. </field>
  12345. <field>
  12346. <name>PLLSRC</name>
  12347. <description>PLL entry clock source</description>
  12348. <bitOffset>16</bitOffset>
  12349. <bitWidth>1</bitWidth>
  12350. <access>read-write</access>
  12351. </field>
  12352. <field>
  12353. <name>STOPWUCK</name>
  12354. <description>Wake-up from stop clock
  12355. selection</description>
  12356. <bitOffset>15</bitOffset>
  12357. <bitWidth>1</bitWidth>
  12358. <access>read-write</access>
  12359. </field>
  12360. <field>
  12361. <name>PPRE2</name>
  12362. <description>APB high-speed prescaler
  12363. (APB2)</description>
  12364. <bitOffset>11</bitOffset>
  12365. <bitWidth>3</bitWidth>
  12366. <access>read-write</access>
  12367. </field>
  12368. <field>
  12369. <name>PPRE1</name>
  12370. <description>APB low-speed prescaler
  12371. (APB1)</description>
  12372. <bitOffset>8</bitOffset>
  12373. <bitWidth>3</bitWidth>
  12374. <access>read-write</access>
  12375. </field>
  12376. <field>
  12377. <name>HPRE</name>
  12378. <description>AHB prescaler</description>
  12379. <bitOffset>4</bitOffset>
  12380. <bitWidth>4</bitWidth>
  12381. <access>read-write</access>
  12382. </field>
  12383. <field>
  12384. <name>SWS</name>
  12385. <description>System clock switch status</description>
  12386. <bitOffset>2</bitOffset>
  12387. <bitWidth>2</bitWidth>
  12388. <access>read-only</access>
  12389. </field>
  12390. <field>
  12391. <name>SW</name>
  12392. <description>System clock switch</description>
  12393. <bitOffset>0</bitOffset>
  12394. <bitWidth>2</bitWidth>
  12395. <access>read-write</access>
  12396. </field>
  12397. </fields>
  12398. </register>
  12399. <register>
  12400. <name>CIER</name>
  12401. <displayName>CIER</displayName>
  12402. <description>Clock interrupt enable
  12403. register</description>
  12404. <addressOffset>0x10</addressOffset>
  12405. <size>0x20</size>
  12406. <access>read-only</access>
  12407. <resetValue>0x00000000</resetValue>
  12408. <fields>
  12409. <field>
  12410. <name>CSSLSE</name>
  12411. <description>LSE CSS interrupt flag</description>
  12412. <bitOffset>7</bitOffset>
  12413. <bitWidth>1</bitWidth>
  12414. </field>
  12415. <field>
  12416. <name>HSI48RDYIE</name>
  12417. <description>HSI48 ready interrupt flag</description>
  12418. <bitOffset>6</bitOffset>
  12419. <bitWidth>1</bitWidth>
  12420. </field>
  12421. <field>
  12422. <name>MSIRDYIE</name>
  12423. <description>MSI ready interrupt flag</description>
  12424. <bitOffset>5</bitOffset>
  12425. <bitWidth>1</bitWidth>
  12426. </field>
  12427. <field>
  12428. <name>PLLRDYIE</name>
  12429. <description>PLL ready interrupt flag</description>
  12430. <bitOffset>4</bitOffset>
  12431. <bitWidth>1</bitWidth>
  12432. </field>
  12433. <field>
  12434. <name>HSERDYIE</name>
  12435. <description>HSE ready interrupt flag</description>
  12436. <bitOffset>3</bitOffset>
  12437. <bitWidth>1</bitWidth>
  12438. </field>
  12439. <field>
  12440. <name>HSI16RDYIE</name>
  12441. <description>HSI16 ready interrupt flag</description>
  12442. <bitOffset>2</bitOffset>
  12443. <bitWidth>1</bitWidth>
  12444. </field>
  12445. <field>
  12446. <name>LSERDYIE</name>
  12447. <description>LSE ready interrupt flag</description>
  12448. <bitOffset>1</bitOffset>
  12449. <bitWidth>1</bitWidth>
  12450. </field>
  12451. <field>
  12452. <name>LSIRDYIE</name>
  12453. <description>LSI ready interrupt flag</description>
  12454. <bitOffset>0</bitOffset>
  12455. <bitWidth>1</bitWidth>
  12456. </field>
  12457. </fields>
  12458. </register>
  12459. <register>
  12460. <name>CIFR</name>
  12461. <displayName>CIFR</displayName>
  12462. <description>Clock interrupt flag register</description>
  12463. <addressOffset>0x14</addressOffset>
  12464. <size>0x20</size>
  12465. <access>read-only</access>
  12466. <resetValue>0x00000000</resetValue>
  12467. <fields>
  12468. <field>
  12469. <name>CSSHSEF</name>
  12470. <description>Clock Security System Interrupt
  12471. flag</description>
  12472. <bitOffset>8</bitOffset>
  12473. <bitWidth>1</bitWidth>
  12474. </field>
  12475. <field>
  12476. <name>CSSLSEF</name>
  12477. <description>LSE Clock Security System Interrupt
  12478. flag</description>
  12479. <bitOffset>7</bitOffset>
  12480. <bitWidth>1</bitWidth>
  12481. </field>
  12482. <field>
  12483. <name>HSI48RDYF</name>
  12484. <description>HSI48 ready interrupt flag</description>
  12485. <bitOffset>6</bitOffset>
  12486. <bitWidth>1</bitWidth>
  12487. </field>
  12488. <field>
  12489. <name>MSIRDYF</name>
  12490. <description>MSI ready interrupt flag</description>
  12491. <bitOffset>5</bitOffset>
  12492. <bitWidth>1</bitWidth>
  12493. </field>
  12494. <field>
  12495. <name>PLLRDYF</name>
  12496. <description>PLL ready interrupt flag</description>
  12497. <bitOffset>4</bitOffset>
  12498. <bitWidth>1</bitWidth>
  12499. </field>
  12500. <field>
  12501. <name>HSERDYF</name>
  12502. <description>HSE ready interrupt flag</description>
  12503. <bitOffset>3</bitOffset>
  12504. <bitWidth>1</bitWidth>
  12505. </field>
  12506. <field>
  12507. <name>HSI16RDYF</name>
  12508. <description>HSI16 ready interrupt flag</description>
  12509. <bitOffset>2</bitOffset>
  12510. <bitWidth>1</bitWidth>
  12511. </field>
  12512. <field>
  12513. <name>LSERDYF</name>
  12514. <description>LSE ready interrupt flag</description>
  12515. <bitOffset>1</bitOffset>
  12516. <bitWidth>1</bitWidth>
  12517. </field>
  12518. <field>
  12519. <name>LSIRDYF</name>
  12520. <description>LSI ready interrupt flag</description>
  12521. <bitOffset>0</bitOffset>
  12522. <bitWidth>1</bitWidth>
  12523. </field>
  12524. </fields>
  12525. </register>
  12526. <register>
  12527. <name>CICR</name>
  12528. <displayName>CICR</displayName>
  12529. <description>Clock interrupt clear register</description>
  12530. <addressOffset>0x18</addressOffset>
  12531. <size>0x20</size>
  12532. <access>read-only</access>
  12533. <resetValue>0x00000000</resetValue>
  12534. <fields>
  12535. <field>
  12536. <name>CSSHSEC</name>
  12537. <description>Clock Security System Interrupt
  12538. clear</description>
  12539. <bitOffset>8</bitOffset>
  12540. <bitWidth>1</bitWidth>
  12541. </field>
  12542. <field>
  12543. <name>CSSLSEC</name>
  12544. <description>LSE Clock Security System Interrupt
  12545. clear</description>
  12546. <bitOffset>7</bitOffset>
  12547. <bitWidth>1</bitWidth>
  12548. </field>
  12549. <field>
  12550. <name>HSI48RDYC</name>
  12551. <description>HSI48 ready Interrupt
  12552. clear</description>
  12553. <bitOffset>6</bitOffset>
  12554. <bitWidth>1</bitWidth>
  12555. </field>
  12556. <field>
  12557. <name>MSIRDYC</name>
  12558. <description>MSI ready Interrupt clear</description>
  12559. <bitOffset>5</bitOffset>
  12560. <bitWidth>1</bitWidth>
  12561. </field>
  12562. <field>
  12563. <name>PLLRDYC</name>
  12564. <description>PLL ready Interrupt clear</description>
  12565. <bitOffset>4</bitOffset>
  12566. <bitWidth>1</bitWidth>
  12567. </field>
  12568. <field>
  12569. <name>HSERDYC</name>
  12570. <description>HSE ready Interrupt clear</description>
  12571. <bitOffset>3</bitOffset>
  12572. <bitWidth>1</bitWidth>
  12573. </field>
  12574. <field>
  12575. <name>HSI16RDYC</name>
  12576. <description>HSI16 ready Interrupt
  12577. clear</description>
  12578. <bitOffset>2</bitOffset>
  12579. <bitWidth>1</bitWidth>
  12580. </field>
  12581. <field>
  12582. <name>LSERDYC</name>
  12583. <description>LSE ready Interrupt clear</description>
  12584. <bitOffset>1</bitOffset>
  12585. <bitWidth>1</bitWidth>
  12586. </field>
  12587. <field>
  12588. <name>LSIRDYC</name>
  12589. <description>LSI ready Interrupt clear</description>
  12590. <bitOffset>0</bitOffset>
  12591. <bitWidth>1</bitWidth>
  12592. </field>
  12593. </fields>
  12594. </register>
  12595. <register>
  12596. <name>IOPRSTR</name>
  12597. <displayName>IOPRSTR</displayName>
  12598. <description>GPIO reset register</description>
  12599. <addressOffset>0x1C</addressOffset>
  12600. <size>0x20</size>
  12601. <access>read-write</access>
  12602. <resetValue>0x00000000</resetValue>
  12603. <fields>
  12604. <field>
  12605. <name>IOPHRST</name>
  12606. <description>I/O port H reset</description>
  12607. <bitOffset>7</bitOffset>
  12608. <bitWidth>1</bitWidth>
  12609. </field>
  12610. <field>
  12611. <name>IOPDRST</name>
  12612. <description>I/O port D reset</description>
  12613. <bitOffset>3</bitOffset>
  12614. <bitWidth>1</bitWidth>
  12615. </field>
  12616. <field>
  12617. <name>IOPCRST</name>
  12618. <description>I/O port A reset</description>
  12619. <bitOffset>2</bitOffset>
  12620. <bitWidth>1</bitWidth>
  12621. </field>
  12622. <field>
  12623. <name>IOPBRST</name>
  12624. <description>I/O port B reset</description>
  12625. <bitOffset>1</bitOffset>
  12626. <bitWidth>1</bitWidth>
  12627. </field>
  12628. <field>
  12629. <name>IOPARST</name>
  12630. <description>I/O port A reset</description>
  12631. <bitOffset>0</bitOffset>
  12632. <bitWidth>1</bitWidth>
  12633. </field>
  12634. </fields>
  12635. </register>
  12636. <register>
  12637. <name>AHBRSTR</name>
  12638. <displayName>AHBRSTR</displayName>
  12639. <description>AHB peripheral reset register</description>
  12640. <addressOffset>0x20</addressOffset>
  12641. <size>0x20</size>
  12642. <access>read-write</access>
  12643. <resetValue>0x00000000</resetValue>
  12644. <fields>
  12645. <field>
  12646. <name>CRYPRST</name>
  12647. <description>Crypto module reset</description>
  12648. <bitOffset>24</bitOffset>
  12649. <bitWidth>1</bitWidth>
  12650. </field>
  12651. <field>
  12652. <name>RNGRST</name>
  12653. <description>Random Number Generator module
  12654. reset</description>
  12655. <bitOffset>20</bitOffset>
  12656. <bitWidth>1</bitWidth>
  12657. </field>
  12658. <field>
  12659. <name>TOUCHRST</name>
  12660. <description>Touch Sensing reset</description>
  12661. <bitOffset>16</bitOffset>
  12662. <bitWidth>1</bitWidth>
  12663. </field>
  12664. <field>
  12665. <name>CRCRST</name>
  12666. <description>Test integration module
  12667. reset</description>
  12668. <bitOffset>12</bitOffset>
  12669. <bitWidth>1</bitWidth>
  12670. </field>
  12671. <field>
  12672. <name>MIFRST</name>
  12673. <description>Memory interface reset</description>
  12674. <bitOffset>8</bitOffset>
  12675. <bitWidth>1</bitWidth>
  12676. </field>
  12677. <field>
  12678. <name>DMARST</name>
  12679. <description>DMA reset</description>
  12680. <bitOffset>0</bitOffset>
  12681. <bitWidth>1</bitWidth>
  12682. </field>
  12683. </fields>
  12684. </register>
  12685. <register>
  12686. <name>APB2RSTR</name>
  12687. <displayName>APB2RSTR</displayName>
  12688. <description>APB2 peripheral reset register</description>
  12689. <addressOffset>0x24</addressOffset>
  12690. <size>0x20</size>
  12691. <access>read-write</access>
  12692. <resetValue>0x000000000</resetValue>
  12693. <fields>
  12694. <field>
  12695. <name>DBGRST</name>
  12696. <description>DBG reset</description>
  12697. <bitOffset>22</bitOffset>
  12698. <bitWidth>1</bitWidth>
  12699. </field>
  12700. <field>
  12701. <name>USART1RST</name>
  12702. <description>USART1 reset</description>
  12703. <bitOffset>14</bitOffset>
  12704. <bitWidth>1</bitWidth>
  12705. </field>
  12706. <field>
  12707. <name>SPI1RST</name>
  12708. <description>SPI 1 reset</description>
  12709. <bitOffset>12</bitOffset>
  12710. <bitWidth>1</bitWidth>
  12711. </field>
  12712. <field>
  12713. <name>ADCRST</name>
  12714. <description>ADC interface reset</description>
  12715. <bitOffset>9</bitOffset>
  12716. <bitWidth>1</bitWidth>
  12717. </field>
  12718. <field>
  12719. <name>TM12RST</name>
  12720. <description>TIM22 timer reset</description>
  12721. <bitOffset>5</bitOffset>
  12722. <bitWidth>1</bitWidth>
  12723. </field>
  12724. <field>
  12725. <name>TIM21RST</name>
  12726. <description>TIM21 timer reset</description>
  12727. <bitOffset>2</bitOffset>
  12728. <bitWidth>1</bitWidth>
  12729. </field>
  12730. <field>
  12731. <name>SYSCFGRST</name>
  12732. <description>System configuration controller
  12733. reset</description>
  12734. <bitOffset>0</bitOffset>
  12735. <bitWidth>1</bitWidth>
  12736. </field>
  12737. </fields>
  12738. </register>
  12739. <register>
  12740. <name>APB1RSTR</name>
  12741. <displayName>APB1RSTR</displayName>
  12742. <description>APB1 peripheral reset register</description>
  12743. <addressOffset>0x28</addressOffset>
  12744. <size>0x20</size>
  12745. <access>read-write</access>
  12746. <resetValue>0x00000000</resetValue>
  12747. <fields>
  12748. <field>
  12749. <name>LPTIM1RST</name>
  12750. <description>Low power timer reset</description>
  12751. <bitOffset>31</bitOffset>
  12752. <bitWidth>1</bitWidth>
  12753. </field>
  12754. <field>
  12755. <name>DACRST</name>
  12756. <description>DAC interface reset</description>
  12757. <bitOffset>29</bitOffset>
  12758. <bitWidth>1</bitWidth>
  12759. </field>
  12760. <field>
  12761. <name>PWRRST</name>
  12762. <description>Power interface reset</description>
  12763. <bitOffset>28</bitOffset>
  12764. <bitWidth>1</bitWidth>
  12765. </field>
  12766. <field>
  12767. <name>CRSRST</name>
  12768. <description>Clock recovery system
  12769. reset</description>
  12770. <bitOffset>27</bitOffset>
  12771. <bitWidth>1</bitWidth>
  12772. </field>
  12773. <field>
  12774. <name>USBRST</name>
  12775. <description>USB reset</description>
  12776. <bitOffset>23</bitOffset>
  12777. <bitWidth>1</bitWidth>
  12778. </field>
  12779. <field>
  12780. <name>I2C2RST</name>
  12781. <description>I2C2 reset</description>
  12782. <bitOffset>22</bitOffset>
  12783. <bitWidth>1</bitWidth>
  12784. </field>
  12785. <field>
  12786. <name>I2C1RST</name>
  12787. <description>I2C1 reset</description>
  12788. <bitOffset>21</bitOffset>
  12789. <bitWidth>1</bitWidth>
  12790. </field>
  12791. <field>
  12792. <name>LPUART1RST</name>
  12793. <description>LPUART1 reset</description>
  12794. <bitOffset>18</bitOffset>
  12795. <bitWidth>1</bitWidth>
  12796. </field>
  12797. <field>
  12798. <name>LPUART12RST</name>
  12799. <description>UART2 reset</description>
  12800. <bitOffset>17</bitOffset>
  12801. <bitWidth>1</bitWidth>
  12802. </field>
  12803. <field>
  12804. <name>SPI2RST</name>
  12805. <description>SPI2 reset</description>
  12806. <bitOffset>14</bitOffset>
  12807. <bitWidth>1</bitWidth>
  12808. </field>
  12809. <field>
  12810. <name>WWDRST</name>
  12811. <description>Window watchdog reset</description>
  12812. <bitOffset>11</bitOffset>
  12813. <bitWidth>1</bitWidth>
  12814. </field>
  12815. <field>
  12816. <name>LCDRST</name>
  12817. <description>LCD reset</description>
  12818. <bitOffset>9</bitOffset>
  12819. <bitWidth>1</bitWidth>
  12820. </field>
  12821. <field>
  12822. <name>TIM6RST</name>
  12823. <description>Timer 6 reset</description>
  12824. <bitOffset>4</bitOffset>
  12825. <bitWidth>1</bitWidth>
  12826. </field>
  12827. <field>
  12828. <name>TIM2RST</name>
  12829. <description>Timer2 reset</description>
  12830. <bitOffset>0</bitOffset>
  12831. <bitWidth>1</bitWidth>
  12832. </field>
  12833. </fields>
  12834. </register>
  12835. <register>
  12836. <name>IOPENR</name>
  12837. <displayName>IOPENR</displayName>
  12838. <description>GPIO clock enable register</description>
  12839. <addressOffset>0x2C</addressOffset>
  12840. <size>0x20</size>
  12841. <access>read-write</access>
  12842. <resetValue>0x00000000</resetValue>
  12843. <fields>
  12844. <field>
  12845. <name>IOPHEN</name>
  12846. <description>I/O port H clock enable
  12847. bit</description>
  12848. <bitOffset>7</bitOffset>
  12849. <bitWidth>1</bitWidth>
  12850. </field>
  12851. <field>
  12852. <name>IOPDEN</name>
  12853. <description>I/O port D clock enable
  12854. bit</description>
  12855. <bitOffset>3</bitOffset>
  12856. <bitWidth>1</bitWidth>
  12857. </field>
  12858. <field>
  12859. <name>IOPCEN</name>
  12860. <description>IO port A clock enable bit</description>
  12861. <bitOffset>2</bitOffset>
  12862. <bitWidth>1</bitWidth>
  12863. </field>
  12864. <field>
  12865. <name>IOPBEN</name>
  12866. <description>IO port B clock enable bit</description>
  12867. <bitOffset>1</bitOffset>
  12868. <bitWidth>1</bitWidth>
  12869. </field>
  12870. <field>
  12871. <name>IOPAEN</name>
  12872. <description>IO port A clock enable bit</description>
  12873. <bitOffset>0</bitOffset>
  12874. <bitWidth>1</bitWidth>
  12875. </field>
  12876. </fields>
  12877. </register>
  12878. <register>
  12879. <name>AHBENR</name>
  12880. <displayName>AHBENR</displayName>
  12881. <description>AHB peripheral clock enable
  12882. register</description>
  12883. <addressOffset>0x30</addressOffset>
  12884. <size>0x20</size>
  12885. <access>read-write</access>
  12886. <resetValue>0x00000100</resetValue>
  12887. <fields>
  12888. <field>
  12889. <name>CRYPEN</name>
  12890. <description>Crypto clock enable bit</description>
  12891. <bitOffset>24</bitOffset>
  12892. <bitWidth>1</bitWidth>
  12893. </field>
  12894. <field>
  12895. <name>RNGEN</name>
  12896. <description>Random Number Generator clock enable
  12897. bit</description>
  12898. <bitOffset>20</bitOffset>
  12899. <bitWidth>1</bitWidth>
  12900. </field>
  12901. <field>
  12902. <name>TOUCHEN</name>
  12903. <description>Touch Sensing clock enable
  12904. bit</description>
  12905. <bitOffset>16</bitOffset>
  12906. <bitWidth>1</bitWidth>
  12907. </field>
  12908. <field>
  12909. <name>CRCEN</name>
  12910. <description>CRC clock enable bit</description>
  12911. <bitOffset>12</bitOffset>
  12912. <bitWidth>1</bitWidth>
  12913. </field>
  12914. <field>
  12915. <name>MIFEN</name>
  12916. <description>NVM interface clock enable
  12917. bit</description>
  12918. <bitOffset>8</bitOffset>
  12919. <bitWidth>1</bitWidth>
  12920. </field>
  12921. <field>
  12922. <name>DMAEN</name>
  12923. <description>DMA clock enable bit</description>
  12924. <bitOffset>0</bitOffset>
  12925. <bitWidth>1</bitWidth>
  12926. </field>
  12927. </fields>
  12928. </register>
  12929. <register>
  12930. <name>APB2ENR</name>
  12931. <displayName>APB2ENR</displayName>
  12932. <description>APB2 peripheral clock enable
  12933. register</description>
  12934. <addressOffset>0x34</addressOffset>
  12935. <size>0x20</size>
  12936. <access>read-write</access>
  12937. <resetValue>0x00000000</resetValue>
  12938. <fields>
  12939. <field>
  12940. <name>DBGEN</name>
  12941. <description>DBG clock enable bit</description>
  12942. <bitOffset>22</bitOffset>
  12943. <bitWidth>1</bitWidth>
  12944. </field>
  12945. <field>
  12946. <name>USART1EN</name>
  12947. <description>USART1 clock enable bit</description>
  12948. <bitOffset>14</bitOffset>
  12949. <bitWidth>1</bitWidth>
  12950. </field>
  12951. <field>
  12952. <name>SPI1EN</name>
  12953. <description>SPI1 clock enable bit</description>
  12954. <bitOffset>12</bitOffset>
  12955. <bitWidth>1</bitWidth>
  12956. </field>
  12957. <field>
  12958. <name>ADCEN</name>
  12959. <description>ADC clock enable bit</description>
  12960. <bitOffset>9</bitOffset>
  12961. <bitWidth>1</bitWidth>
  12962. </field>
  12963. <field>
  12964. <name>MIFIEN</name>
  12965. <description>MiFaRe Firewall clock enable
  12966. bit</description>
  12967. <bitOffset>7</bitOffset>
  12968. <bitWidth>1</bitWidth>
  12969. </field>
  12970. <field>
  12971. <name>TIM22EN</name>
  12972. <description>TIM22 timer clock enable
  12973. bit</description>
  12974. <bitOffset>5</bitOffset>
  12975. <bitWidth>1</bitWidth>
  12976. </field>
  12977. <field>
  12978. <name>TIM21EN</name>
  12979. <description>TIM21 timer clock enable
  12980. bit</description>
  12981. <bitOffset>2</bitOffset>
  12982. <bitWidth>1</bitWidth>
  12983. </field>
  12984. <field>
  12985. <name>SYSCFGEN</name>
  12986. <description>System configuration controller clock
  12987. enable bit</description>
  12988. <bitOffset>0</bitOffset>
  12989. <bitWidth>1</bitWidth>
  12990. </field>
  12991. </fields>
  12992. </register>
  12993. <register>
  12994. <name>APB1ENR</name>
  12995. <displayName>APB1ENR</displayName>
  12996. <description>APB1 peripheral clock enable
  12997. register</description>
  12998. <addressOffset>0x38</addressOffset>
  12999. <size>0x20</size>
  13000. <access>read-write</access>
  13001. <resetValue>0x00000000</resetValue>
  13002. <fields>
  13003. <field>
  13004. <name>LPTIM1EN</name>
  13005. <description>Low power timer clock enable
  13006. bit</description>
  13007. <bitOffset>31</bitOffset>
  13008. <bitWidth>1</bitWidth>
  13009. </field>
  13010. <field>
  13011. <name>DACEN</name>
  13012. <description>DAC interface clock enable
  13013. bit</description>
  13014. <bitOffset>29</bitOffset>
  13015. <bitWidth>1</bitWidth>
  13016. </field>
  13017. <field>
  13018. <name>PWREN</name>
  13019. <description>Power interface clock enable
  13020. bit</description>
  13021. <bitOffset>28</bitOffset>
  13022. <bitWidth>1</bitWidth>
  13023. </field>
  13024. <field>
  13025. <name>CRSEN</name>
  13026. <description>Clock recovery system clock enable
  13027. bit</description>
  13028. <bitOffset>27</bitOffset>
  13029. <bitWidth>1</bitWidth>
  13030. </field>
  13031. <field>
  13032. <name>USBEN</name>
  13033. <description>USB clock enable bit</description>
  13034. <bitOffset>23</bitOffset>
  13035. <bitWidth>1</bitWidth>
  13036. </field>
  13037. <field>
  13038. <name>I2C2EN</name>
  13039. <description>I2C2 clock enable bit</description>
  13040. <bitOffset>22</bitOffset>
  13041. <bitWidth>1</bitWidth>
  13042. </field>
  13043. <field>
  13044. <name>I2C1EN</name>
  13045. <description>I2C1 clock enable bit</description>
  13046. <bitOffset>21</bitOffset>
  13047. <bitWidth>1</bitWidth>
  13048. </field>
  13049. <field>
  13050. <name>LPUART1EN</name>
  13051. <description>LPUART1 clock enable bit</description>
  13052. <bitOffset>18</bitOffset>
  13053. <bitWidth>1</bitWidth>
  13054. </field>
  13055. <field>
  13056. <name>USART2EN</name>
  13057. <description>UART2 clock enable bit</description>
  13058. <bitOffset>17</bitOffset>
  13059. <bitWidth>1</bitWidth>
  13060. </field>
  13061. <field>
  13062. <name>SPI2EN</name>
  13063. <description>SPI2 clock enable bit</description>
  13064. <bitOffset>14</bitOffset>
  13065. <bitWidth>1</bitWidth>
  13066. </field>
  13067. <field>
  13068. <name>WWDGEN</name>
  13069. <description>Window watchdog clock enable
  13070. bit</description>
  13071. <bitOffset>11</bitOffset>
  13072. <bitWidth>1</bitWidth>
  13073. </field>
  13074. <field>
  13075. <name>LCDEN</name>
  13076. <description>LCD clock enable bit</description>
  13077. <bitOffset>9</bitOffset>
  13078. <bitWidth>1</bitWidth>
  13079. </field>
  13080. <field>
  13081. <name>TIM6EN</name>
  13082. <description>Timer 6 clock enable bit</description>
  13083. <bitOffset>4</bitOffset>
  13084. <bitWidth>1</bitWidth>
  13085. </field>
  13086. <field>
  13087. <name>TIM2EN</name>
  13088. <description>Timer2 clock enable bit</description>
  13089. <bitOffset>0</bitOffset>
  13090. <bitWidth>1</bitWidth>
  13091. </field>
  13092. </fields>
  13093. </register>
  13094. <register>
  13095. <name>IOPSMEN</name>
  13096. <displayName>IOPSMEN</displayName>
  13097. <description>GPIO clock enable in sleep mode
  13098. register</description>
  13099. <addressOffset>0x3C</addressOffset>
  13100. <size>0x20</size>
  13101. <access>read-write</access>
  13102. <resetValue>0x0000008F</resetValue>
  13103. <fields>
  13104. <field>
  13105. <name>IOPHSMEN</name>
  13106. <description>IOPHSMEN</description>
  13107. <bitOffset>7</bitOffset>
  13108. <bitWidth>1</bitWidth>
  13109. </field>
  13110. <field>
  13111. <name>IOPDSMEN</name>
  13112. <description>IOPDSMEN</description>
  13113. <bitOffset>3</bitOffset>
  13114. <bitWidth>1</bitWidth>
  13115. </field>
  13116. <field>
  13117. <name>IOPCSMEN</name>
  13118. <description>IOPCSMEN</description>
  13119. <bitOffset>2</bitOffset>
  13120. <bitWidth>1</bitWidth>
  13121. </field>
  13122. <field>
  13123. <name>IOPBSMEN</name>
  13124. <description>IOPBSMEN</description>
  13125. <bitOffset>1</bitOffset>
  13126. <bitWidth>1</bitWidth>
  13127. </field>
  13128. <field>
  13129. <name>IOPASMEN</name>
  13130. <description>IOPASMEN</description>
  13131. <bitOffset>0</bitOffset>
  13132. <bitWidth>1</bitWidth>
  13133. </field>
  13134. </fields>
  13135. </register>
  13136. <register>
  13137. <name>AHBSMENR</name>
  13138. <displayName>AHBSMENR</displayName>
  13139. <description>AHB peripheral clock enable in sleep mode
  13140. register</description>
  13141. <addressOffset>0x40</addressOffset>
  13142. <size>0x20</size>
  13143. <access>read-write</access>
  13144. <resetValue>0x01111301</resetValue>
  13145. <fields>
  13146. <field>
  13147. <name>CRYPSMEN</name>
  13148. <description>Crypto clock enable during sleep mode
  13149. bit</description>
  13150. <bitOffset>24</bitOffset>
  13151. <bitWidth>1</bitWidth>
  13152. </field>
  13153. <field>
  13154. <name>RNGSMEN</name>
  13155. <description>Random Number Generator clock enable
  13156. during sleep mode bit</description>
  13157. <bitOffset>20</bitOffset>
  13158. <bitWidth>1</bitWidth>
  13159. </field>
  13160. <field>
  13161. <name>TOUCHSMEN</name>
  13162. <description>Touch Sensing clock enable during sleep
  13163. mode bit</description>
  13164. <bitOffset>16</bitOffset>
  13165. <bitWidth>1</bitWidth>
  13166. </field>
  13167. <field>
  13168. <name>CRCSMEN</name>
  13169. <description>CRC clock enable during sleep mode
  13170. bit</description>
  13171. <bitOffset>12</bitOffset>
  13172. <bitWidth>1</bitWidth>
  13173. </field>
  13174. <field>
  13175. <name>SRAMSMEN</name>
  13176. <description>SRAM interface clock enable during sleep
  13177. mode bit</description>
  13178. <bitOffset>9</bitOffset>
  13179. <bitWidth>1</bitWidth>
  13180. </field>
  13181. <field>
  13182. <name>MIFSMEN</name>
  13183. <description>NVM interface clock enable during sleep
  13184. mode bit</description>
  13185. <bitOffset>8</bitOffset>
  13186. <bitWidth>1</bitWidth>
  13187. </field>
  13188. <field>
  13189. <name>DMASMEN</name>
  13190. <description>DMA clock enable during sleep mode
  13191. bit</description>
  13192. <bitOffset>0</bitOffset>
  13193. <bitWidth>1</bitWidth>
  13194. </field>
  13195. </fields>
  13196. </register>
  13197. <register>
  13198. <name>APB2SMENR</name>
  13199. <displayName>APB2SMENR</displayName>
  13200. <description>APB2 peripheral clock enable in sleep mode
  13201. register</description>
  13202. <addressOffset>0x44</addressOffset>
  13203. <size>0x20</size>
  13204. <access>read-write</access>
  13205. <resetValue>0x00405225</resetValue>
  13206. <fields>
  13207. <field>
  13208. <name>DBGSMEN</name>
  13209. <description>DBG clock enable during sleep mode
  13210. bit</description>
  13211. <bitOffset>22</bitOffset>
  13212. <bitWidth>1</bitWidth>
  13213. </field>
  13214. <field>
  13215. <name>USART1SMEN</name>
  13216. <description>USART1 clock enable during sleep mode
  13217. bit</description>
  13218. <bitOffset>14</bitOffset>
  13219. <bitWidth>1</bitWidth>
  13220. </field>
  13221. <field>
  13222. <name>SPI1SMEN</name>
  13223. <description>SPI1 clock enable during sleep mode
  13224. bit</description>
  13225. <bitOffset>12</bitOffset>
  13226. <bitWidth>1</bitWidth>
  13227. </field>
  13228. <field>
  13229. <name>ADCSMEN</name>
  13230. <description>ADC clock enable during sleep mode
  13231. bit</description>
  13232. <bitOffset>9</bitOffset>
  13233. <bitWidth>1</bitWidth>
  13234. </field>
  13235. <field>
  13236. <name>TIM22SMEN</name>
  13237. <description>TIM22 timer clock enable during sleep
  13238. mode bit</description>
  13239. <bitOffset>5</bitOffset>
  13240. <bitWidth>1</bitWidth>
  13241. </field>
  13242. <field>
  13243. <name>TIM21SMEN</name>
  13244. <description>TIM21 timer clock enable during sleep
  13245. mode bit</description>
  13246. <bitOffset>2</bitOffset>
  13247. <bitWidth>1</bitWidth>
  13248. </field>
  13249. <field>
  13250. <name>SYSCFGSMEN</name>
  13251. <description>System configuration controller clock
  13252. enable during sleep mode bit</description>
  13253. <bitOffset>0</bitOffset>
  13254. <bitWidth>1</bitWidth>
  13255. </field>
  13256. </fields>
  13257. </register>
  13258. <register>
  13259. <name>APB1SMENR</name>
  13260. <displayName>APB1SMENR</displayName>
  13261. <description>APB1 peripheral clock enable in sleep mode
  13262. register</description>
  13263. <addressOffset>0x48</addressOffset>
  13264. <size>0x20</size>
  13265. <access>read-write</access>
  13266. <resetValue>0xB8E64A11</resetValue>
  13267. <fields>
  13268. <field>
  13269. <name>LPTIM1SMEN</name>
  13270. <description>Low power timer clock enable during
  13271. sleep mode bit</description>
  13272. <bitOffset>31</bitOffset>
  13273. <bitWidth>1</bitWidth>
  13274. </field>
  13275. <field>
  13276. <name>DACSMEN</name>
  13277. <description>DAC interface clock enable during sleep
  13278. mode bit</description>
  13279. <bitOffset>29</bitOffset>
  13280. <bitWidth>1</bitWidth>
  13281. </field>
  13282. <field>
  13283. <name>PWRSMEN</name>
  13284. <description>Power interface clock enable during
  13285. sleep mode bit</description>
  13286. <bitOffset>28</bitOffset>
  13287. <bitWidth>1</bitWidth>
  13288. </field>
  13289. <field>
  13290. <name>CRSSMEN</name>
  13291. <description>Clock recovery system clock enable
  13292. during sleep mode bit</description>
  13293. <bitOffset>27</bitOffset>
  13294. <bitWidth>1</bitWidth>
  13295. </field>
  13296. <field>
  13297. <name>USBSMEN</name>
  13298. <description>USB clock enable during sleep mode
  13299. bit</description>
  13300. <bitOffset>23</bitOffset>
  13301. <bitWidth>1</bitWidth>
  13302. </field>
  13303. <field>
  13304. <name>I2C2SMEN</name>
  13305. <description>I2C2 clock enable during sleep mode
  13306. bit</description>
  13307. <bitOffset>22</bitOffset>
  13308. <bitWidth>1</bitWidth>
  13309. </field>
  13310. <field>
  13311. <name>I2C1SMEN</name>
  13312. <description>I2C1 clock enable during sleep mode
  13313. bit</description>
  13314. <bitOffset>21</bitOffset>
  13315. <bitWidth>1</bitWidth>
  13316. </field>
  13317. <field>
  13318. <name>LPUART1SMEN</name>
  13319. <description>LPUART1 clock enable during sleep mode
  13320. bit</description>
  13321. <bitOffset>18</bitOffset>
  13322. <bitWidth>1</bitWidth>
  13323. </field>
  13324. <field>
  13325. <name>USART2SMEN</name>
  13326. <description>UART2 clock enable during sleep mode
  13327. bit</description>
  13328. <bitOffset>17</bitOffset>
  13329. <bitWidth>1</bitWidth>
  13330. </field>
  13331. <field>
  13332. <name>SPI2SMEN</name>
  13333. <description>SPI2 clock enable during sleep mode
  13334. bit</description>
  13335. <bitOffset>14</bitOffset>
  13336. <bitWidth>1</bitWidth>
  13337. </field>
  13338. <field>
  13339. <name>WWDGSMEN</name>
  13340. <description>Window watchdog clock enable during
  13341. sleep mode bit</description>
  13342. <bitOffset>11</bitOffset>
  13343. <bitWidth>1</bitWidth>
  13344. </field>
  13345. <field>
  13346. <name>LCDSMEN</name>
  13347. <description>LCD clock enable during sleep mode
  13348. bit</description>
  13349. <bitOffset>9</bitOffset>
  13350. <bitWidth>1</bitWidth>
  13351. </field>
  13352. <field>
  13353. <name>TIM6SMEN</name>
  13354. <description>Timer 6 clock enable during sleep mode
  13355. bit</description>
  13356. <bitOffset>4</bitOffset>
  13357. <bitWidth>1</bitWidth>
  13358. </field>
  13359. <field>
  13360. <name>TIM2SMEN</name>
  13361. <description>Timer2 clock enable during sleep mode
  13362. bit</description>
  13363. <bitOffset>0</bitOffset>
  13364. <bitWidth>1</bitWidth>
  13365. </field>
  13366. </fields>
  13367. </register>
  13368. <register>
  13369. <name>CCIPR</name>
  13370. <displayName>CCIPR</displayName>
  13371. <description>Clock configuration register</description>
  13372. <addressOffset>0x4C</addressOffset>
  13373. <size>0x20</size>
  13374. <access>read-write</access>
  13375. <resetValue>0x00000000</resetValue>
  13376. <fields>
  13377. <field>
  13378. <name>HSI48MSEL</name>
  13379. <description>48 MHz HSI48 clock source selection
  13380. bit</description>
  13381. <bitOffset>26</bitOffset>
  13382. <bitWidth>1</bitWidth>
  13383. </field>
  13384. <field>
  13385. <name>LPTIM1SEL1</name>
  13386. <description>Low Power Timer clock source selection
  13387. bits</description>
  13388. <bitOffset>19</bitOffset>
  13389. <bitWidth>1</bitWidth>
  13390. </field>
  13391. <field>
  13392. <name>LPTIM1SEL0</name>
  13393. <description>LPTIM1SEL0</description>
  13394. <bitOffset>18</bitOffset>
  13395. <bitWidth>1</bitWidth>
  13396. </field>
  13397. <field>
  13398. <name>I2C1SEL1</name>
  13399. <description>I2C1 clock source selection
  13400. bits</description>
  13401. <bitOffset>13</bitOffset>
  13402. <bitWidth>1</bitWidth>
  13403. </field>
  13404. <field>
  13405. <name>I2C1SEL0</name>
  13406. <description>I2C1SEL0</description>
  13407. <bitOffset>12</bitOffset>
  13408. <bitWidth>1</bitWidth>
  13409. </field>
  13410. <field>
  13411. <name>LPUART1SEL1</name>
  13412. <description>LPUART1 clock source selection
  13413. bits</description>
  13414. <bitOffset>11</bitOffset>
  13415. <bitWidth>1</bitWidth>
  13416. </field>
  13417. <field>
  13418. <name>LPUART1SEL0</name>
  13419. <description>LPUART1SEL0</description>
  13420. <bitOffset>10</bitOffset>
  13421. <bitWidth>1</bitWidth>
  13422. </field>
  13423. <field>
  13424. <name>USART2SEL1</name>
  13425. <description>USART2 clock source selection
  13426. bits</description>
  13427. <bitOffset>3</bitOffset>
  13428. <bitWidth>1</bitWidth>
  13429. </field>
  13430. <field>
  13431. <name>USART2SEL0</name>
  13432. <description>USART2SEL0</description>
  13433. <bitOffset>2</bitOffset>
  13434. <bitWidth>1</bitWidth>
  13435. </field>
  13436. <field>
  13437. <name>USART1SEL1</name>
  13438. <description>USART1 clock source selection
  13439. bits</description>
  13440. <bitOffset>1</bitOffset>
  13441. <bitWidth>1</bitWidth>
  13442. </field>
  13443. <field>
  13444. <name>USART1SEL0</name>
  13445. <description>USART1SEL0</description>
  13446. <bitOffset>0</bitOffset>
  13447. <bitWidth>1</bitWidth>
  13448. </field>
  13449. </fields>
  13450. </register>
  13451. <register>
  13452. <name>CSR</name>
  13453. <displayName>CSR</displayName>
  13454. <description>Control and status register</description>
  13455. <addressOffset>0x50</addressOffset>
  13456. <size>0x20</size>
  13457. <resetValue>0x0C000000</resetValue>
  13458. <fields>
  13459. <field>
  13460. <name>LPWRSTF</name>
  13461. <description>Low-power reset flag</description>
  13462. <bitOffset>31</bitOffset>
  13463. <bitWidth>1</bitWidth>
  13464. <access>read-write</access>
  13465. </field>
  13466. <field>
  13467. <name>WWDGRSTF</name>
  13468. <description>Window watchdog reset flag</description>
  13469. <bitOffset>30</bitOffset>
  13470. <bitWidth>1</bitWidth>
  13471. <access>read-write</access>
  13472. </field>
  13473. <field>
  13474. <name>IWDGRSTF</name>
  13475. <description>Independent watchdog reset
  13476. flag</description>
  13477. <bitOffset>29</bitOffset>
  13478. <bitWidth>1</bitWidth>
  13479. <access>read-write</access>
  13480. </field>
  13481. <field>
  13482. <name>SFTRSTF</name>
  13483. <description>Software reset flag</description>
  13484. <bitOffset>28</bitOffset>
  13485. <bitWidth>1</bitWidth>
  13486. <access>read-write</access>
  13487. </field>
  13488. <field>
  13489. <name>PORRSTF</name>
  13490. <description>POR/PDR reset flag</description>
  13491. <bitOffset>27</bitOffset>
  13492. <bitWidth>1</bitWidth>
  13493. <access>read-write</access>
  13494. </field>
  13495. <field>
  13496. <name>PINRSTF</name>
  13497. <description>PIN reset flag</description>
  13498. <bitOffset>26</bitOffset>
  13499. <bitWidth>1</bitWidth>
  13500. <access>read-write</access>
  13501. </field>
  13502. <field>
  13503. <name>OBLRSTF</name>
  13504. <description>OBLRSTF</description>
  13505. <bitOffset>25</bitOffset>
  13506. <bitWidth>1</bitWidth>
  13507. <access>read-write</access>
  13508. </field>
  13509. <field>
  13510. <name>RMVF</name>
  13511. <description>Remove reset flag</description>
  13512. <bitOffset>24</bitOffset>
  13513. <bitWidth>1</bitWidth>
  13514. <access>read-write</access>
  13515. </field>
  13516. <field>
  13517. <name>RTCRST</name>
  13518. <description>RTC software reset bit</description>
  13519. <bitOffset>19</bitOffset>
  13520. <bitWidth>1</bitWidth>
  13521. <access>read-write</access>
  13522. </field>
  13523. <field>
  13524. <name>RTCEN</name>
  13525. <description>RTC clock enable bit</description>
  13526. <bitOffset>18</bitOffset>
  13527. <bitWidth>1</bitWidth>
  13528. <access>read-write</access>
  13529. </field>
  13530. <field>
  13531. <name>RTCSEL</name>
  13532. <description>RTC and LCD clock source selection
  13533. bits</description>
  13534. <bitOffset>16</bitOffset>
  13535. <bitWidth>2</bitWidth>
  13536. <access>read-write</access>
  13537. </field>
  13538. <field>
  13539. <name>CSSLSED</name>
  13540. <description>CSS on LSE failure detection
  13541. flag</description>
  13542. <bitOffset>14</bitOffset>
  13543. <bitWidth>1</bitWidth>
  13544. <access>read-write</access>
  13545. </field>
  13546. <field>
  13547. <name>CSSLSEON</name>
  13548. <description>CSSLSEON</description>
  13549. <bitOffset>13</bitOffset>
  13550. <bitWidth>1</bitWidth>
  13551. <access>read-write</access>
  13552. </field>
  13553. <field>
  13554. <name>LSEDRV</name>
  13555. <description>LSEDRV</description>
  13556. <bitOffset>11</bitOffset>
  13557. <bitWidth>2</bitWidth>
  13558. <access>read-write</access>
  13559. </field>
  13560. <field>
  13561. <name>LSEBYP</name>
  13562. <description>External low-speed oscillator bypass
  13563. bit</description>
  13564. <bitOffset>10</bitOffset>
  13565. <bitWidth>1</bitWidth>
  13566. <access>read-write</access>
  13567. </field>
  13568. <field>
  13569. <name>LSERDY</name>
  13570. <description>External low-speed oscillator ready
  13571. bit</description>
  13572. <bitOffset>9</bitOffset>
  13573. <bitWidth>1</bitWidth>
  13574. <access>read-only</access>
  13575. </field>
  13576. <field>
  13577. <name>LSEON</name>
  13578. <description>External low-speed oscillator enable
  13579. bit</description>
  13580. <bitOffset>8</bitOffset>
  13581. <bitWidth>1</bitWidth>
  13582. <access>read-write</access>
  13583. </field>
  13584. <field>
  13585. <name>LSIRDY</name>
  13586. <description>Internal low-speed oscillator ready
  13587. bit</description>
  13588. <bitOffset>1</bitOffset>
  13589. <bitWidth>1</bitWidth>
  13590. <access>read-write</access>
  13591. </field>
  13592. <field>
  13593. <name>LSION</name>
  13594. <description>Internal low-speed oscillator
  13595. enable</description>
  13596. <bitOffset>0</bitOffset>
  13597. <bitWidth>1</bitWidth>
  13598. <access>read-write</access>
  13599. </field>
  13600. </fields>
  13601. </register>
  13602. </registers>
  13603. </peripheral>
  13604. <peripheral>
  13605. <name>SYSCFG</name>
  13606. <description>System configuration controller</description>
  13607. <groupName>SYSCFG</groupName>
  13608. <baseAddress>0x40010000</baseAddress>
  13609. <addressBlock>
  13610. <offset>0x0</offset>
  13611. <size>0x400</size>
  13612. <usage>registers</usage>
  13613. </addressBlock>
  13614. <registers>
  13615. <register>
  13616. <name>CFGR1</name>
  13617. <displayName>CFGR1</displayName>
  13618. <description>SYSCFG configuration register
  13619. 1</description>
  13620. <addressOffset>0x0</addressOffset>
  13621. <size>0x20</size>
  13622. <resetValue>0x00000000</resetValue>
  13623. <fields>
  13624. <field>
  13625. <name>BOOT_MODE</name>
  13626. <description>Boot mode selected by the boot pins
  13627. status bits</description>
  13628. <bitOffset>8</bitOffset>
  13629. <bitWidth>2</bitWidth>
  13630. <access>read-only</access>
  13631. </field>
  13632. <field>
  13633. <name>MEM_MODE</name>
  13634. <description>Memory mapping selection
  13635. bits</description>
  13636. <bitOffset>0</bitOffset>
  13637. <bitWidth>2</bitWidth>
  13638. <access>read-write</access>
  13639. </field>
  13640. </fields>
  13641. </register>
  13642. <register>
  13643. <name>CFGR2</name>
  13644. <displayName>CFGR2</displayName>
  13645. <description>SYSCFG configuration register
  13646. 2</description>
  13647. <addressOffset>0x4</addressOffset>
  13648. <size>0x20</size>
  13649. <access>read-write</access>
  13650. <resetValue>0x00000000</resetValue>
  13651. <fields>
  13652. <field>
  13653. <name>I2C2_FMP</name>
  13654. <description>I2C2 Fm+ drive capability enable
  13655. bit</description>
  13656. <bitOffset>13</bitOffset>
  13657. <bitWidth>1</bitWidth>
  13658. </field>
  13659. <field>
  13660. <name>I2C1_FMP</name>
  13661. <description>I2C1 Fm+ drive capability enable
  13662. bit</description>
  13663. <bitOffset>12</bitOffset>
  13664. <bitWidth>1</bitWidth>
  13665. </field>
  13666. <field>
  13667. <name>I2C_PB9_FMP</name>
  13668. <description>Fm+ drive capability on PB9 enable
  13669. bit</description>
  13670. <bitOffset>11</bitOffset>
  13671. <bitWidth>1</bitWidth>
  13672. </field>
  13673. <field>
  13674. <name>I2C_PB8_FMP</name>
  13675. <description>Fm+ drive capability on PB8 enable
  13676. bit</description>
  13677. <bitOffset>10</bitOffset>
  13678. <bitWidth>1</bitWidth>
  13679. </field>
  13680. <field>
  13681. <name>I2C_PB7_FMP</name>
  13682. <description>Fm+ drive capability on PB7 enable
  13683. bit</description>
  13684. <bitOffset>9</bitOffset>
  13685. <bitWidth>1</bitWidth>
  13686. </field>
  13687. <field>
  13688. <name>I2C_PB6_FMP</name>
  13689. <description>Fm+ drive capability on PB6 enable
  13690. bit</description>
  13691. <bitOffset>8</bitOffset>
  13692. <bitWidth>1</bitWidth>
  13693. </field>
  13694. <field>
  13695. <name>CAPA</name>
  13696. <description>Configuration of internal VLCD rail
  13697. connection to optional external
  13698. capacitor</description>
  13699. <bitOffset>1</bitOffset>
  13700. <bitWidth>3</bitWidth>
  13701. </field>
  13702. <field>
  13703. <name>FWDISEN</name>
  13704. <description>Firewall disable bit</description>
  13705. <bitOffset>0</bitOffset>
  13706. <bitWidth>1</bitWidth>
  13707. </field>
  13708. </fields>
  13709. </register>
  13710. <register>
  13711. <name>EXTICR1</name>
  13712. <displayName>EXTICR1</displayName>
  13713. <description>external interrupt configuration register
  13714. 1</description>
  13715. <addressOffset>0x8</addressOffset>
  13716. <size>0x20</size>
  13717. <access>read-write</access>
  13718. <resetValue>0x0000</resetValue>
  13719. <fields>
  13720. <field>
  13721. <name>EXTI3</name>
  13722. <description>EXTI x configuration (x = 0 to
  13723. 3)</description>
  13724. <bitOffset>12</bitOffset>
  13725. <bitWidth>4</bitWidth>
  13726. </field>
  13727. <field>
  13728. <name>EXTI2</name>
  13729. <description>EXTI x configuration (x = 0 to
  13730. 3)</description>
  13731. <bitOffset>8</bitOffset>
  13732. <bitWidth>4</bitWidth>
  13733. </field>
  13734. <field>
  13735. <name>EXTI1</name>
  13736. <description>EXTI x configuration (x = 0 to
  13737. 3)</description>
  13738. <bitOffset>4</bitOffset>
  13739. <bitWidth>4</bitWidth>
  13740. </field>
  13741. <field>
  13742. <name>EXTI0</name>
  13743. <description>EXTI x configuration (x = 0 to
  13744. 3)</description>
  13745. <bitOffset>0</bitOffset>
  13746. <bitWidth>4</bitWidth>
  13747. </field>
  13748. </fields>
  13749. </register>
  13750. <register>
  13751. <name>EXTICR2</name>
  13752. <displayName>EXTICR2</displayName>
  13753. <description>external interrupt configuration register
  13754. 2</description>
  13755. <addressOffset>0xC</addressOffset>
  13756. <size>0x20</size>
  13757. <access>read-write</access>
  13758. <resetValue>0x0000</resetValue>
  13759. <fields>
  13760. <field>
  13761. <name>EXTI7</name>
  13762. <description>EXTI x configuration (x = 4 to
  13763. 7)</description>
  13764. <bitOffset>12</bitOffset>
  13765. <bitWidth>4</bitWidth>
  13766. </field>
  13767. <field>
  13768. <name>EXTI6</name>
  13769. <description>EXTI x configuration (x = 4 to
  13770. 7)</description>
  13771. <bitOffset>8</bitOffset>
  13772. <bitWidth>4</bitWidth>
  13773. </field>
  13774. <field>
  13775. <name>EXTI5</name>
  13776. <description>EXTI x configuration (x = 4 to
  13777. 7)</description>
  13778. <bitOffset>4</bitOffset>
  13779. <bitWidth>4</bitWidth>
  13780. </field>
  13781. <field>
  13782. <name>EXTI4</name>
  13783. <description>EXTI x configuration (x = 4 to
  13784. 7)</description>
  13785. <bitOffset>0</bitOffset>
  13786. <bitWidth>4</bitWidth>
  13787. </field>
  13788. </fields>
  13789. </register>
  13790. <register>
  13791. <name>EXTICR3</name>
  13792. <displayName>EXTICR3</displayName>
  13793. <description>external interrupt configuration register
  13794. 3</description>
  13795. <addressOffset>0x10</addressOffset>
  13796. <size>0x20</size>
  13797. <access>read-write</access>
  13798. <resetValue>0x0000</resetValue>
  13799. <fields>
  13800. <field>
  13801. <name>EXTI11</name>
  13802. <description>EXTI x configuration (x = 8 to
  13803. 11)</description>
  13804. <bitOffset>12</bitOffset>
  13805. <bitWidth>4</bitWidth>
  13806. </field>
  13807. <field>
  13808. <name>EXTI10</name>
  13809. <description>EXTI10</description>
  13810. <bitOffset>8</bitOffset>
  13811. <bitWidth>4</bitWidth>
  13812. </field>
  13813. <field>
  13814. <name>EXTI9</name>
  13815. <description>EXTI x configuration (x = 8 to
  13816. 11)</description>
  13817. <bitOffset>4</bitOffset>
  13818. <bitWidth>4</bitWidth>
  13819. </field>
  13820. <field>
  13821. <name>EXTI8</name>
  13822. <description>EXTI x configuration (x = 8 to
  13823. 11)</description>
  13824. <bitOffset>0</bitOffset>
  13825. <bitWidth>4</bitWidth>
  13826. </field>
  13827. </fields>
  13828. </register>
  13829. <register>
  13830. <name>EXTICR4</name>
  13831. <displayName>EXTICR4</displayName>
  13832. <description>external interrupt configuration register
  13833. 4</description>
  13834. <addressOffset>0x14</addressOffset>
  13835. <size>0x20</size>
  13836. <access>read-write</access>
  13837. <resetValue>0x0000</resetValue>
  13838. <fields>
  13839. <field>
  13840. <name>EXTI15</name>
  13841. <description>EXTI x configuration (x = 12 to
  13842. 15)</description>
  13843. <bitOffset>12</bitOffset>
  13844. <bitWidth>4</bitWidth>
  13845. </field>
  13846. <field>
  13847. <name>EXTI14</name>
  13848. <description>EXTI14</description>
  13849. <bitOffset>8</bitOffset>
  13850. <bitWidth>4</bitWidth>
  13851. </field>
  13852. <field>
  13853. <name>EXTI13</name>
  13854. <description>EXTI13</description>
  13855. <bitOffset>4</bitOffset>
  13856. <bitWidth>4</bitWidth>
  13857. </field>
  13858. <field>
  13859. <name>EXTI12</name>
  13860. <description>EXTI12</description>
  13861. <bitOffset>0</bitOffset>
  13862. <bitWidth>4</bitWidth>
  13863. </field>
  13864. </fields>
  13865. </register>
  13866. <register>
  13867. <name>CFGR3</name>
  13868. <displayName>CFGR3</displayName>
  13869. <description>SYSCFG configuration register
  13870. 3</description>
  13871. <addressOffset>0x20</addressOffset>
  13872. <size>0x20</size>
  13873. <resetValue>0x00000000</resetValue>
  13874. <fields>
  13875. <field>
  13876. <name>REF_LOCK</name>
  13877. <description>REF_CTRL lock bit</description>
  13878. <bitOffset>31</bitOffset>
  13879. <bitWidth>1</bitWidth>
  13880. <access>write-only</access>
  13881. </field>
  13882. <field>
  13883. <name>VREFINT_RDYF</name>
  13884. <description>VREFINT ready flag</description>
  13885. <bitOffset>30</bitOffset>
  13886. <bitWidth>1</bitWidth>
  13887. <access>read-only</access>
  13888. </field>
  13889. <field>
  13890. <name>VREFINT_COMP_RDYF</name>
  13891. <description>VREFINT for comparator ready
  13892. flag</description>
  13893. <bitOffset>29</bitOffset>
  13894. <bitWidth>1</bitWidth>
  13895. <access>read-only</access>
  13896. </field>
  13897. <field>
  13898. <name>VREFINT_ADC_RDYF</name>
  13899. <description>VREFINT for ADC ready flag</description>
  13900. <bitOffset>28</bitOffset>
  13901. <bitWidth>1</bitWidth>
  13902. <access>read-only</access>
  13903. </field>
  13904. <field>
  13905. <name>SENSOR_ADC_RDYF</name>
  13906. <description>Sensor for ADC ready flag</description>
  13907. <bitOffset>27</bitOffset>
  13908. <bitWidth>1</bitWidth>
  13909. <access>read-only</access>
  13910. </field>
  13911. <field>
  13912. <name>REF_RC48MHz_RDYF</name>
  13913. <description>VREFINT for 48 MHz RC oscillator ready
  13914. flag</description>
  13915. <bitOffset>26</bitOffset>
  13916. <bitWidth>1</bitWidth>
  13917. <access>read-only</access>
  13918. </field>
  13919. <field>
  13920. <name>ENREF_RC48MHz</name>
  13921. <description>VREFINT reference for 48 MHz RC
  13922. oscillator enable bit</description>
  13923. <bitOffset>13</bitOffset>
  13924. <bitWidth>1</bitWidth>
  13925. <access>read-write</access>
  13926. </field>
  13927. <field>
  13928. <name>ENBUF_VREFINT_COMP</name>
  13929. <description>VREFINT reference for comparator 2
  13930. enable bit</description>
  13931. <bitOffset>12</bitOffset>
  13932. <bitWidth>1</bitWidth>
  13933. <access>read-write</access>
  13934. </field>
  13935. <field>
  13936. <name>ENBUF_SENSOR_ADC</name>
  13937. <description>Sensor reference for ADC enable
  13938. bit</description>
  13939. <bitOffset>9</bitOffset>
  13940. <bitWidth>1</bitWidth>
  13941. <access>read-write</access>
  13942. </field>
  13943. <field>
  13944. <name>ENBUF_BGAP_ADC</name>
  13945. <description>VREFINT reference for ADC enable
  13946. bit</description>
  13947. <bitOffset>8</bitOffset>
  13948. <bitWidth>1</bitWidth>
  13949. <access>read-write</access>
  13950. </field>
  13951. <field>
  13952. <name>SEL_VREF_OUT</name>
  13953. <description>BGAP_ADC connection bit</description>
  13954. <bitOffset>4</bitOffset>
  13955. <bitWidth>2</bitWidth>
  13956. <access>read-write</access>
  13957. </field>
  13958. <field>
  13959. <name>EN_BGAP</name>
  13960. <description>Vref Enable bit</description>
  13961. <bitOffset>0</bitOffset>
  13962. <bitWidth>1</bitWidth>
  13963. <access>read-write</access>
  13964. </field>
  13965. </fields>
  13966. </register>
  13967. </registers>
  13968. </peripheral>
  13969. <peripheral>
  13970. <name>SPI1</name>
  13971. <description>Serial peripheral interface</description>
  13972. <groupName>SPI</groupName>
  13973. <baseAddress>0x40013000</baseAddress>
  13974. <addressBlock>
  13975. <offset>0x0</offset>
  13976. <size>0x400</size>
  13977. <usage>registers</usage>
  13978. </addressBlock>
  13979. <interrupt>
  13980. <name>SPI1</name>
  13981. <description>SPI1_global_interrupt</description>
  13982. <value>25</value>
  13983. </interrupt>
  13984. <registers>
  13985. <register>
  13986. <name>CR1</name>
  13987. <displayName>CR1</displayName>
  13988. <description>control register 1</description>
  13989. <addressOffset>0x0</addressOffset>
  13990. <size>0x20</size>
  13991. <access>read-write</access>
  13992. <resetValue>0x0000</resetValue>
  13993. <fields>
  13994. <field>
  13995. <name>BIDIMODE</name>
  13996. <description>Bidirectional data mode
  13997. enable</description>
  13998. <bitOffset>15</bitOffset>
  13999. <bitWidth>1</bitWidth>
  14000. </field>
  14001. <field>
  14002. <name>BIDIOE</name>
  14003. <description>Output enable in bidirectional
  14004. mode</description>
  14005. <bitOffset>14</bitOffset>
  14006. <bitWidth>1</bitWidth>
  14007. </field>
  14008. <field>
  14009. <name>CRCEN</name>
  14010. <description>Hardware CRC calculation
  14011. enable</description>
  14012. <bitOffset>13</bitOffset>
  14013. <bitWidth>1</bitWidth>
  14014. </field>
  14015. <field>
  14016. <name>CRCNEXT</name>
  14017. <description>CRC transfer next</description>
  14018. <bitOffset>12</bitOffset>
  14019. <bitWidth>1</bitWidth>
  14020. </field>
  14021. <field>
  14022. <name>DFF</name>
  14023. <description>Data frame format</description>
  14024. <bitOffset>11</bitOffset>
  14025. <bitWidth>1</bitWidth>
  14026. </field>
  14027. <field>
  14028. <name>RXONLY</name>
  14029. <description>Receive only</description>
  14030. <bitOffset>10</bitOffset>
  14031. <bitWidth>1</bitWidth>
  14032. </field>
  14033. <field>
  14034. <name>SSM</name>
  14035. <description>Software slave management</description>
  14036. <bitOffset>9</bitOffset>
  14037. <bitWidth>1</bitWidth>
  14038. </field>
  14039. <field>
  14040. <name>SSI</name>
  14041. <description>Internal slave select</description>
  14042. <bitOffset>8</bitOffset>
  14043. <bitWidth>1</bitWidth>
  14044. </field>
  14045. <field>
  14046. <name>LSBFIRST</name>
  14047. <description>Frame format</description>
  14048. <bitOffset>7</bitOffset>
  14049. <bitWidth>1</bitWidth>
  14050. </field>
  14051. <field>
  14052. <name>SPE</name>
  14053. <description>SPI enable</description>
  14054. <bitOffset>6</bitOffset>
  14055. <bitWidth>1</bitWidth>
  14056. </field>
  14057. <field>
  14058. <name>BR</name>
  14059. <description>Baud rate control</description>
  14060. <bitOffset>3</bitOffset>
  14061. <bitWidth>3</bitWidth>
  14062. </field>
  14063. <field>
  14064. <name>MSTR</name>
  14065. <description>Master selection</description>
  14066. <bitOffset>2</bitOffset>
  14067. <bitWidth>1</bitWidth>
  14068. </field>
  14069. <field>
  14070. <name>CPOL</name>
  14071. <description>Clock polarity</description>
  14072. <bitOffset>1</bitOffset>
  14073. <bitWidth>1</bitWidth>
  14074. </field>
  14075. <field>
  14076. <name>CPHA</name>
  14077. <description>Clock phase</description>
  14078. <bitOffset>0</bitOffset>
  14079. <bitWidth>1</bitWidth>
  14080. </field>
  14081. </fields>
  14082. </register>
  14083. <register>
  14084. <name>CR2</name>
  14085. <displayName>CR2</displayName>
  14086. <description>control register 2</description>
  14087. <addressOffset>0x4</addressOffset>
  14088. <size>0x20</size>
  14089. <access>read-write</access>
  14090. <resetValue>0x0000</resetValue>
  14091. <fields>
  14092. <field>
  14093. <name>RXDMAEN</name>
  14094. <description>Rx buffer DMA enable</description>
  14095. <bitOffset>0</bitOffset>
  14096. <bitWidth>1</bitWidth>
  14097. </field>
  14098. <field>
  14099. <name>TXDMAEN</name>
  14100. <description>Tx buffer DMA enable</description>
  14101. <bitOffset>1</bitOffset>
  14102. <bitWidth>1</bitWidth>
  14103. </field>
  14104. <field>
  14105. <name>SSOE</name>
  14106. <description>SS output enable</description>
  14107. <bitOffset>2</bitOffset>
  14108. <bitWidth>1</bitWidth>
  14109. </field>
  14110. <field>
  14111. <name>FRF</name>
  14112. <description>Frame format</description>
  14113. <bitOffset>4</bitOffset>
  14114. <bitWidth>1</bitWidth>
  14115. </field>
  14116. <field>
  14117. <name>ERRIE</name>
  14118. <description>Error interrupt enable</description>
  14119. <bitOffset>5</bitOffset>
  14120. <bitWidth>1</bitWidth>
  14121. </field>
  14122. <field>
  14123. <name>RXNEIE</name>
  14124. <description>RX buffer not empty interrupt
  14125. enable</description>
  14126. <bitOffset>6</bitOffset>
  14127. <bitWidth>1</bitWidth>
  14128. </field>
  14129. <field>
  14130. <name>TXEIE</name>
  14131. <description>Tx buffer empty interrupt
  14132. enable</description>
  14133. <bitOffset>7</bitOffset>
  14134. <bitWidth>1</bitWidth>
  14135. </field>
  14136. </fields>
  14137. </register>
  14138. <register>
  14139. <name>SR</name>
  14140. <displayName>SR</displayName>
  14141. <description>status register</description>
  14142. <addressOffset>0x8</addressOffset>
  14143. <size>0x20</size>
  14144. <resetValue>0x0002</resetValue>
  14145. <fields>
  14146. <field>
  14147. <name>RXNE</name>
  14148. <description>Receive buffer not empty</description>
  14149. <bitOffset>0</bitOffset>
  14150. <bitWidth>1</bitWidth>
  14151. <access>read-only</access>
  14152. </field>
  14153. <field>
  14154. <name>TXE</name>
  14155. <description>Transmit buffer empty</description>
  14156. <bitOffset>1</bitOffset>
  14157. <bitWidth>1</bitWidth>
  14158. <access>read-only</access>
  14159. </field>
  14160. <field>
  14161. <name>CHSIDE</name>
  14162. <description>Channel side</description>
  14163. <bitOffset>2</bitOffset>
  14164. <bitWidth>1</bitWidth>
  14165. <access>read-only</access>
  14166. </field>
  14167. <field>
  14168. <name>UDR</name>
  14169. <description>Underrun flag</description>
  14170. <bitOffset>3</bitOffset>
  14171. <bitWidth>1</bitWidth>
  14172. <access>read-only</access>
  14173. </field>
  14174. <field>
  14175. <name>CRCERR</name>
  14176. <description>CRC error flag</description>
  14177. <bitOffset>4</bitOffset>
  14178. <bitWidth>1</bitWidth>
  14179. <access>read-write</access>
  14180. </field>
  14181. <field>
  14182. <name>MODF</name>
  14183. <description>Mode fault</description>
  14184. <bitOffset>5</bitOffset>
  14185. <bitWidth>1</bitWidth>
  14186. <access>read-only</access>
  14187. </field>
  14188. <field>
  14189. <name>OVR</name>
  14190. <description>Overrun flag</description>
  14191. <bitOffset>6</bitOffset>
  14192. <bitWidth>1</bitWidth>
  14193. <access>read-only</access>
  14194. </field>
  14195. <field>
  14196. <name>BSY</name>
  14197. <description>Busy flag</description>
  14198. <bitOffset>7</bitOffset>
  14199. <bitWidth>1</bitWidth>
  14200. <access>read-only</access>
  14201. </field>
  14202. <field>
  14203. <name>TIFRFE</name>
  14204. <description>TI frame format error</description>
  14205. <bitOffset>8</bitOffset>
  14206. <bitWidth>1</bitWidth>
  14207. <access>read-only</access>
  14208. </field>
  14209. </fields>
  14210. </register>
  14211. <register>
  14212. <name>DR</name>
  14213. <displayName>DR</displayName>
  14214. <description>data register</description>
  14215. <addressOffset>0xC</addressOffset>
  14216. <size>0x20</size>
  14217. <access>read-write</access>
  14218. <resetValue>0x0000</resetValue>
  14219. <fields>
  14220. <field>
  14221. <name>DR</name>
  14222. <description>Data register</description>
  14223. <bitOffset>0</bitOffset>
  14224. <bitWidth>16</bitWidth>
  14225. </field>
  14226. </fields>
  14227. </register>
  14228. <register>
  14229. <name>CRCPR</name>
  14230. <displayName>CRCPR</displayName>
  14231. <description>CRC polynomial register</description>
  14232. <addressOffset>0x10</addressOffset>
  14233. <size>0x20</size>
  14234. <access>read-write</access>
  14235. <resetValue>0x0007</resetValue>
  14236. <fields>
  14237. <field>
  14238. <name>CRCPOLY</name>
  14239. <description>CRC polynomial register</description>
  14240. <bitOffset>0</bitOffset>
  14241. <bitWidth>16</bitWidth>
  14242. </field>
  14243. </fields>
  14244. </register>
  14245. <register>
  14246. <name>RXCRCR</name>
  14247. <displayName>RXCRCR</displayName>
  14248. <description>RX CRC register</description>
  14249. <addressOffset>0x14</addressOffset>
  14250. <size>0x20</size>
  14251. <access>read-only</access>
  14252. <resetValue>0x0000</resetValue>
  14253. <fields>
  14254. <field>
  14255. <name>RxCRC</name>
  14256. <description>Rx CRC register</description>
  14257. <bitOffset>0</bitOffset>
  14258. <bitWidth>16</bitWidth>
  14259. </field>
  14260. </fields>
  14261. </register>
  14262. <register>
  14263. <name>TXCRCR</name>
  14264. <displayName>TXCRCR</displayName>
  14265. <description>TX CRC register</description>
  14266. <addressOffset>0x18</addressOffset>
  14267. <size>0x20</size>
  14268. <access>read-only</access>
  14269. <resetValue>0x0000</resetValue>
  14270. <fields>
  14271. <field>
  14272. <name>TxCRC</name>
  14273. <description>Tx CRC register</description>
  14274. <bitOffset>0</bitOffset>
  14275. <bitWidth>16</bitWidth>
  14276. </field>
  14277. </fields>
  14278. </register>
  14279. <register>
  14280. <name>I2SCFGR</name>
  14281. <displayName>I2SCFGR</displayName>
  14282. <description>I2S configuration register</description>
  14283. <addressOffset>0x1C</addressOffset>
  14284. <size>0x20</size>
  14285. <access>read-write</access>
  14286. <resetValue>0x0000</resetValue>
  14287. <fields>
  14288. <field>
  14289. <name>I2SMOD</name>
  14290. <description>I2S mode selection</description>
  14291. <bitOffset>11</bitOffset>
  14292. <bitWidth>1</bitWidth>
  14293. </field>
  14294. <field>
  14295. <name>I2SE</name>
  14296. <description>I2S Enable</description>
  14297. <bitOffset>10</bitOffset>
  14298. <bitWidth>1</bitWidth>
  14299. </field>
  14300. <field>
  14301. <name>I2SCFG</name>
  14302. <description>I2S configuration mode</description>
  14303. <bitOffset>8</bitOffset>
  14304. <bitWidth>2</bitWidth>
  14305. </field>
  14306. <field>
  14307. <name>PCMSYNC</name>
  14308. <description>PCM frame synchronization</description>
  14309. <bitOffset>7</bitOffset>
  14310. <bitWidth>1</bitWidth>
  14311. </field>
  14312. <field>
  14313. <name>I2SSTD</name>
  14314. <description>I2S standard selection</description>
  14315. <bitOffset>4</bitOffset>
  14316. <bitWidth>2</bitWidth>
  14317. </field>
  14318. <field>
  14319. <name>CKPOL</name>
  14320. <description>Steady state clock
  14321. polarity</description>
  14322. <bitOffset>3</bitOffset>
  14323. <bitWidth>1</bitWidth>
  14324. </field>
  14325. <field>
  14326. <name>DATLEN</name>
  14327. <description>Data length to be
  14328. transferred</description>
  14329. <bitOffset>1</bitOffset>
  14330. <bitWidth>2</bitWidth>
  14331. </field>
  14332. <field>
  14333. <name>CHLEN</name>
  14334. <description>Channel length (number of bits per audio
  14335. channel)</description>
  14336. <bitOffset>0</bitOffset>
  14337. <bitWidth>1</bitWidth>
  14338. </field>
  14339. </fields>
  14340. </register>
  14341. <register>
  14342. <name>I2SPR</name>
  14343. <displayName>I2SPR</displayName>
  14344. <description>I2S prescaler register</description>
  14345. <addressOffset>0x20</addressOffset>
  14346. <size>0x20</size>
  14347. <access>read-write</access>
  14348. <resetValue>0x00000010</resetValue>
  14349. <fields>
  14350. <field>
  14351. <name>MCKOE</name>
  14352. <description>Master clock output enable</description>
  14353. <bitOffset>9</bitOffset>
  14354. <bitWidth>1</bitWidth>
  14355. </field>
  14356. <field>
  14357. <name>ODD</name>
  14358. <description>Odd factor for the
  14359. prescaler</description>
  14360. <bitOffset>8</bitOffset>
  14361. <bitWidth>1</bitWidth>
  14362. </field>
  14363. <field>
  14364. <name>I2SDIV</name>
  14365. <description>I2S Linear prescaler</description>
  14366. <bitOffset>0</bitOffset>
  14367. <bitWidth>8</bitWidth>
  14368. </field>
  14369. </fields>
  14370. </register>
  14371. </registers>
  14372. </peripheral>
  14373. <peripheral derivedFrom="SPI1">
  14374. <name>SPI2</name>
  14375. <baseAddress>0x40003800</baseAddress>
  14376. <interrupt>
  14377. <name>SPI2</name>
  14378. <description>SPI2 global interrupt</description>
  14379. <value>26</value>
  14380. </interrupt>
  14381. </peripheral>
  14382. <peripheral>
  14383. <name>I2C1</name>
  14384. <description>Inter-integrated circuit</description>
  14385. <groupName>I2C</groupName>
  14386. <baseAddress>0x40005400</baseAddress>
  14387. <addressBlock>
  14388. <offset>0x0</offset>
  14389. <size>0x400</size>
  14390. <usage>registers</usage>
  14391. </addressBlock>
  14392. <interrupt>
  14393. <name>I2C1</name>
  14394. <description>I2C1 global interrupt</description>
  14395. <value>23</value>
  14396. </interrupt>
  14397. <registers>
  14398. <register>
  14399. <name>CR1</name>
  14400. <displayName>CR1</displayName>
  14401. <description>Control register 1</description>
  14402. <addressOffset>0x0</addressOffset>
  14403. <size>0x20</size>
  14404. <access>read-write</access>
  14405. <resetValue>0x00000000</resetValue>
  14406. <fields>
  14407. <field>
  14408. <name>PE</name>
  14409. <description>Peripheral enable</description>
  14410. <bitOffset>0</bitOffset>
  14411. <bitWidth>1</bitWidth>
  14412. </field>
  14413. <field>
  14414. <name>TXIE</name>
  14415. <description>TX Interrupt enable</description>
  14416. <bitOffset>1</bitOffset>
  14417. <bitWidth>1</bitWidth>
  14418. </field>
  14419. <field>
  14420. <name>RXIE</name>
  14421. <description>RX Interrupt enable</description>
  14422. <bitOffset>2</bitOffset>
  14423. <bitWidth>1</bitWidth>
  14424. </field>
  14425. <field>
  14426. <name>ADDRIE</name>
  14427. <description>Address match interrupt enable (slave
  14428. only)</description>
  14429. <bitOffset>3</bitOffset>
  14430. <bitWidth>1</bitWidth>
  14431. </field>
  14432. <field>
  14433. <name>NACKIE</name>
  14434. <description>Not acknowledge received interrupt
  14435. enable</description>
  14436. <bitOffset>4</bitOffset>
  14437. <bitWidth>1</bitWidth>
  14438. </field>
  14439. <field>
  14440. <name>STOPIE</name>
  14441. <description>STOP detection Interrupt
  14442. enable</description>
  14443. <bitOffset>5</bitOffset>
  14444. <bitWidth>1</bitWidth>
  14445. </field>
  14446. <field>
  14447. <name>TCIE</name>
  14448. <description>Transfer Complete interrupt
  14449. enable</description>
  14450. <bitOffset>6</bitOffset>
  14451. <bitWidth>1</bitWidth>
  14452. </field>
  14453. <field>
  14454. <name>ERRIE</name>
  14455. <description>Error interrupts enable</description>
  14456. <bitOffset>7</bitOffset>
  14457. <bitWidth>1</bitWidth>
  14458. </field>
  14459. <field>
  14460. <name>DNF</name>
  14461. <description>Digital noise filter</description>
  14462. <bitOffset>8</bitOffset>
  14463. <bitWidth>4</bitWidth>
  14464. </field>
  14465. <field>
  14466. <name>ANFOFF</name>
  14467. <description>Analog noise filter OFF</description>
  14468. <bitOffset>12</bitOffset>
  14469. <bitWidth>1</bitWidth>
  14470. </field>
  14471. <field>
  14472. <name>TXDMAEN</name>
  14473. <description>DMA transmission requests
  14474. enable</description>
  14475. <bitOffset>14</bitOffset>
  14476. <bitWidth>1</bitWidth>
  14477. </field>
  14478. <field>
  14479. <name>RXDMAEN</name>
  14480. <description>DMA reception requests
  14481. enable</description>
  14482. <bitOffset>15</bitOffset>
  14483. <bitWidth>1</bitWidth>
  14484. </field>
  14485. <field>
  14486. <name>SBC</name>
  14487. <description>Slave byte control</description>
  14488. <bitOffset>16</bitOffset>
  14489. <bitWidth>1</bitWidth>
  14490. </field>
  14491. <field>
  14492. <name>NOSTRETCH</name>
  14493. <description>Clock stretching disable</description>
  14494. <bitOffset>17</bitOffset>
  14495. <bitWidth>1</bitWidth>
  14496. </field>
  14497. <field>
  14498. <name>WUPEN</name>
  14499. <description>Wakeup from STOP enable</description>
  14500. <bitOffset>18</bitOffset>
  14501. <bitWidth>1</bitWidth>
  14502. </field>
  14503. <field>
  14504. <name>GCEN</name>
  14505. <description>General call enable</description>
  14506. <bitOffset>19</bitOffset>
  14507. <bitWidth>1</bitWidth>
  14508. </field>
  14509. <field>
  14510. <name>SMBHEN</name>
  14511. <description>SMBus Host address enable</description>
  14512. <bitOffset>20</bitOffset>
  14513. <bitWidth>1</bitWidth>
  14514. </field>
  14515. <field>
  14516. <name>SMBDEN</name>
  14517. <description>SMBus Device Default address
  14518. enable</description>
  14519. <bitOffset>21</bitOffset>
  14520. <bitWidth>1</bitWidth>
  14521. </field>
  14522. <field>
  14523. <name>ALERTEN</name>
  14524. <description>SMBUS alert enable</description>
  14525. <bitOffset>22</bitOffset>
  14526. <bitWidth>1</bitWidth>
  14527. </field>
  14528. <field>
  14529. <name>PECEN</name>
  14530. <description>PEC enable</description>
  14531. <bitOffset>23</bitOffset>
  14532. <bitWidth>1</bitWidth>
  14533. </field>
  14534. </fields>
  14535. </register>
  14536. <register>
  14537. <name>CR2</name>
  14538. <displayName>CR2</displayName>
  14539. <description>Control register 2</description>
  14540. <addressOffset>0x4</addressOffset>
  14541. <size>0x20</size>
  14542. <access>read-write</access>
  14543. <resetValue>0x00000000</resetValue>
  14544. <fields>
  14545. <field>
  14546. <name>PECBYTE</name>
  14547. <description>Packet error checking byte</description>
  14548. <bitOffset>26</bitOffset>
  14549. <bitWidth>1</bitWidth>
  14550. </field>
  14551. <field>
  14552. <name>AUTOEND</name>
  14553. <description>Automatic end mode (master
  14554. mode)</description>
  14555. <bitOffset>25</bitOffset>
  14556. <bitWidth>1</bitWidth>
  14557. </field>
  14558. <field>
  14559. <name>RELOAD</name>
  14560. <description>NBYTES reload mode</description>
  14561. <bitOffset>24</bitOffset>
  14562. <bitWidth>1</bitWidth>
  14563. </field>
  14564. <field>
  14565. <name>NBYTES</name>
  14566. <description>Number of bytes</description>
  14567. <bitOffset>16</bitOffset>
  14568. <bitWidth>8</bitWidth>
  14569. </field>
  14570. <field>
  14571. <name>NACK</name>
  14572. <description>NACK generation (slave
  14573. mode)</description>
  14574. <bitOffset>15</bitOffset>
  14575. <bitWidth>1</bitWidth>
  14576. </field>
  14577. <field>
  14578. <name>STOP</name>
  14579. <description>Stop generation (master
  14580. mode)</description>
  14581. <bitOffset>14</bitOffset>
  14582. <bitWidth>1</bitWidth>
  14583. </field>
  14584. <field>
  14585. <name>START</name>
  14586. <description>Start generation</description>
  14587. <bitOffset>13</bitOffset>
  14588. <bitWidth>1</bitWidth>
  14589. </field>
  14590. <field>
  14591. <name>HEAD10R</name>
  14592. <description>10-bit address header only read
  14593. direction (master receiver mode)</description>
  14594. <bitOffset>12</bitOffset>
  14595. <bitWidth>1</bitWidth>
  14596. </field>
  14597. <field>
  14598. <name>ADD10</name>
  14599. <description>10-bit addressing mode (master
  14600. mode)</description>
  14601. <bitOffset>11</bitOffset>
  14602. <bitWidth>1</bitWidth>
  14603. </field>
  14604. <field>
  14605. <name>RD_WRN</name>
  14606. <description>Transfer direction (master
  14607. mode)</description>
  14608. <bitOffset>10</bitOffset>
  14609. <bitWidth>1</bitWidth>
  14610. </field>
  14611. <field>
  14612. <name>SADD</name>
  14613. <description>Slave address bit (master
  14614. mode)</description>
  14615. <bitOffset>0</bitOffset>
  14616. <bitWidth>10</bitWidth>
  14617. </field>
  14618. </fields>
  14619. </register>
  14620. <register>
  14621. <name>OAR1</name>
  14622. <displayName>OAR1</displayName>
  14623. <description>Own address register 1</description>
  14624. <addressOffset>0x8</addressOffset>
  14625. <size>0x20</size>
  14626. <access>read-write</access>
  14627. <resetValue>0x00000000</resetValue>
  14628. <fields>
  14629. <field>
  14630. <name>OA1</name>
  14631. <description>Interface address</description>
  14632. <bitOffset>0</bitOffset>
  14633. <bitWidth>10</bitWidth>
  14634. </field>
  14635. <field>
  14636. <name>OA1MODE</name>
  14637. <description>Own Address 1 10-bit mode</description>
  14638. <bitOffset>10</bitOffset>
  14639. <bitWidth>1</bitWidth>
  14640. </field>
  14641. <field>
  14642. <name>OA1EN</name>
  14643. <description>Own Address 1 enable</description>
  14644. <bitOffset>15</bitOffset>
  14645. <bitWidth>1</bitWidth>
  14646. </field>
  14647. </fields>
  14648. </register>
  14649. <register>
  14650. <name>OAR2</name>
  14651. <displayName>OAR2</displayName>
  14652. <description>Own address register 2</description>
  14653. <addressOffset>0xC</addressOffset>
  14654. <size>0x20</size>
  14655. <access>read-write</access>
  14656. <resetValue>0x00000000</resetValue>
  14657. <fields>
  14658. <field>
  14659. <name>OA2</name>
  14660. <description>Interface address</description>
  14661. <bitOffset>1</bitOffset>
  14662. <bitWidth>7</bitWidth>
  14663. </field>
  14664. <field>
  14665. <name>OA2MSK</name>
  14666. <description>Own Address 2 masks</description>
  14667. <bitOffset>8</bitOffset>
  14668. <bitWidth>3</bitWidth>
  14669. </field>
  14670. <field>
  14671. <name>OA2EN</name>
  14672. <description>Own Address 2 enable</description>
  14673. <bitOffset>15</bitOffset>
  14674. <bitWidth>1</bitWidth>
  14675. </field>
  14676. </fields>
  14677. </register>
  14678. <register>
  14679. <name>TIMINGR</name>
  14680. <displayName>TIMINGR</displayName>
  14681. <description>Timing register</description>
  14682. <addressOffset>0x10</addressOffset>
  14683. <size>0x20</size>
  14684. <access>read-write</access>
  14685. <resetValue>0x00000000</resetValue>
  14686. <fields>
  14687. <field>
  14688. <name>SCLL</name>
  14689. <description>SCL low period (master
  14690. mode)</description>
  14691. <bitOffset>0</bitOffset>
  14692. <bitWidth>8</bitWidth>
  14693. </field>
  14694. <field>
  14695. <name>SCLH</name>
  14696. <description>SCL high period (master
  14697. mode)</description>
  14698. <bitOffset>8</bitOffset>
  14699. <bitWidth>8</bitWidth>
  14700. </field>
  14701. <field>
  14702. <name>SDADEL</name>
  14703. <description>Data hold time</description>
  14704. <bitOffset>16</bitOffset>
  14705. <bitWidth>4</bitWidth>
  14706. </field>
  14707. <field>
  14708. <name>SCLDEL</name>
  14709. <description>Data setup time</description>
  14710. <bitOffset>20</bitOffset>
  14711. <bitWidth>4</bitWidth>
  14712. </field>
  14713. <field>
  14714. <name>PRESC</name>
  14715. <description>Timing prescaler</description>
  14716. <bitOffset>28</bitOffset>
  14717. <bitWidth>4</bitWidth>
  14718. </field>
  14719. </fields>
  14720. </register>
  14721. <register>
  14722. <name>TIMEOUTR</name>
  14723. <displayName>TIMEOUTR</displayName>
  14724. <description>Status register 1</description>
  14725. <addressOffset>0x14</addressOffset>
  14726. <size>0x20</size>
  14727. <access>read-write</access>
  14728. <resetValue>0x00000000</resetValue>
  14729. <fields>
  14730. <field>
  14731. <name>TIMEOUTA</name>
  14732. <description>Bus timeout A</description>
  14733. <bitOffset>0</bitOffset>
  14734. <bitWidth>12</bitWidth>
  14735. </field>
  14736. <field>
  14737. <name>TIDLE</name>
  14738. <description>Idle clock timeout
  14739. detection</description>
  14740. <bitOffset>12</bitOffset>
  14741. <bitWidth>1</bitWidth>
  14742. </field>
  14743. <field>
  14744. <name>TIMOUTEN</name>
  14745. <description>Clock timeout enable</description>
  14746. <bitOffset>15</bitOffset>
  14747. <bitWidth>1</bitWidth>
  14748. </field>
  14749. <field>
  14750. <name>TIMEOUTB</name>
  14751. <description>Bus timeout B</description>
  14752. <bitOffset>16</bitOffset>
  14753. <bitWidth>12</bitWidth>
  14754. </field>
  14755. <field>
  14756. <name>TEXTEN</name>
  14757. <description>Extended clock timeout
  14758. enable</description>
  14759. <bitOffset>31</bitOffset>
  14760. <bitWidth>1</bitWidth>
  14761. </field>
  14762. </fields>
  14763. </register>
  14764. <register>
  14765. <name>ISR</name>
  14766. <displayName>ISR</displayName>
  14767. <description>Interrupt and Status register</description>
  14768. <addressOffset>0x18</addressOffset>
  14769. <size>0x20</size>
  14770. <resetValue>0x00000001</resetValue>
  14771. <fields>
  14772. <field>
  14773. <name>ADDCODE</name>
  14774. <description>Address match code (Slave
  14775. mode)</description>
  14776. <bitOffset>17</bitOffset>
  14777. <bitWidth>7</bitWidth>
  14778. <access>read-only</access>
  14779. </field>
  14780. <field>
  14781. <name>DIR</name>
  14782. <description>Transfer direction (Slave
  14783. mode)</description>
  14784. <bitOffset>16</bitOffset>
  14785. <bitWidth>1</bitWidth>
  14786. <access>read-only</access>
  14787. </field>
  14788. <field>
  14789. <name>BUSY</name>
  14790. <description>Bus busy</description>
  14791. <bitOffset>15</bitOffset>
  14792. <bitWidth>1</bitWidth>
  14793. <access>read-only</access>
  14794. </field>
  14795. <field>
  14796. <name>ALERT</name>
  14797. <description>SMBus alert</description>
  14798. <bitOffset>13</bitOffset>
  14799. <bitWidth>1</bitWidth>
  14800. <access>read-only</access>
  14801. </field>
  14802. <field>
  14803. <name>TIMEOUT</name>
  14804. <description>Timeout or t_low detection
  14805. flag</description>
  14806. <bitOffset>12</bitOffset>
  14807. <bitWidth>1</bitWidth>
  14808. <access>read-only</access>
  14809. </field>
  14810. <field>
  14811. <name>PECERR</name>
  14812. <description>PEC Error in reception</description>
  14813. <bitOffset>11</bitOffset>
  14814. <bitWidth>1</bitWidth>
  14815. <access>read-only</access>
  14816. </field>
  14817. <field>
  14818. <name>OVR</name>
  14819. <description>Overrun/Underrun (slave
  14820. mode)</description>
  14821. <bitOffset>10</bitOffset>
  14822. <bitWidth>1</bitWidth>
  14823. <access>read-only</access>
  14824. </field>
  14825. <field>
  14826. <name>ARLO</name>
  14827. <description>Arbitration lost</description>
  14828. <bitOffset>9</bitOffset>
  14829. <bitWidth>1</bitWidth>
  14830. <access>read-only</access>
  14831. </field>
  14832. <field>
  14833. <name>BERR</name>
  14834. <description>Bus error</description>
  14835. <bitOffset>8</bitOffset>
  14836. <bitWidth>1</bitWidth>
  14837. <access>read-only</access>
  14838. </field>
  14839. <field>
  14840. <name>TCR</name>
  14841. <description>Transfer Complete Reload</description>
  14842. <bitOffset>7</bitOffset>
  14843. <bitWidth>1</bitWidth>
  14844. <access>read-only</access>
  14845. </field>
  14846. <field>
  14847. <name>TC</name>
  14848. <description>Transfer Complete (master
  14849. mode)</description>
  14850. <bitOffset>6</bitOffset>
  14851. <bitWidth>1</bitWidth>
  14852. <access>read-only</access>
  14853. </field>
  14854. <field>
  14855. <name>STOPF</name>
  14856. <description>Stop detection flag</description>
  14857. <bitOffset>5</bitOffset>
  14858. <bitWidth>1</bitWidth>
  14859. <access>read-only</access>
  14860. </field>
  14861. <field>
  14862. <name>NACKF</name>
  14863. <description>Not acknowledge received
  14864. flag</description>
  14865. <bitOffset>4</bitOffset>
  14866. <bitWidth>1</bitWidth>
  14867. <access>read-only</access>
  14868. </field>
  14869. <field>
  14870. <name>ADDR</name>
  14871. <description>Address matched (slave
  14872. mode)</description>
  14873. <bitOffset>3</bitOffset>
  14874. <bitWidth>1</bitWidth>
  14875. <access>read-only</access>
  14876. </field>
  14877. <field>
  14878. <name>RXNE</name>
  14879. <description>Receive data register not empty
  14880. (receivers)</description>
  14881. <bitOffset>2</bitOffset>
  14882. <bitWidth>1</bitWidth>
  14883. <access>read-only</access>
  14884. </field>
  14885. <field>
  14886. <name>TXIS</name>
  14887. <description>Transmit interrupt status
  14888. (transmitters)</description>
  14889. <bitOffset>1</bitOffset>
  14890. <bitWidth>1</bitWidth>
  14891. <access>read-write</access>
  14892. </field>
  14893. <field>
  14894. <name>TXE</name>
  14895. <description>Transmit data register empty
  14896. (transmitters)</description>
  14897. <bitOffset>0</bitOffset>
  14898. <bitWidth>1</bitWidth>
  14899. <access>read-write</access>
  14900. </field>
  14901. </fields>
  14902. </register>
  14903. <register>
  14904. <name>ICR</name>
  14905. <displayName>ICR</displayName>
  14906. <description>Interrupt clear register</description>
  14907. <addressOffset>0x1C</addressOffset>
  14908. <size>0x20</size>
  14909. <access>write-only</access>
  14910. <resetValue>0x00000000</resetValue>
  14911. <fields>
  14912. <field>
  14913. <name>ALERTCF</name>
  14914. <description>Alert flag clear</description>
  14915. <bitOffset>13</bitOffset>
  14916. <bitWidth>1</bitWidth>
  14917. </field>
  14918. <field>
  14919. <name>TIMOUTCF</name>
  14920. <description>Timeout detection flag
  14921. clear</description>
  14922. <bitOffset>12</bitOffset>
  14923. <bitWidth>1</bitWidth>
  14924. </field>
  14925. <field>
  14926. <name>PECCF</name>
  14927. <description>PEC Error flag clear</description>
  14928. <bitOffset>11</bitOffset>
  14929. <bitWidth>1</bitWidth>
  14930. </field>
  14931. <field>
  14932. <name>OVRCF</name>
  14933. <description>Overrun/Underrun flag
  14934. clear</description>
  14935. <bitOffset>10</bitOffset>
  14936. <bitWidth>1</bitWidth>
  14937. </field>
  14938. <field>
  14939. <name>ARLOCF</name>
  14940. <description>Arbitration lost flag
  14941. clear</description>
  14942. <bitOffset>9</bitOffset>
  14943. <bitWidth>1</bitWidth>
  14944. </field>
  14945. <field>
  14946. <name>BERRCF</name>
  14947. <description>Bus error flag clear</description>
  14948. <bitOffset>8</bitOffset>
  14949. <bitWidth>1</bitWidth>
  14950. </field>
  14951. <field>
  14952. <name>STOPCF</name>
  14953. <description>Stop detection flag clear</description>
  14954. <bitOffset>5</bitOffset>
  14955. <bitWidth>1</bitWidth>
  14956. </field>
  14957. <field>
  14958. <name>NACKCF</name>
  14959. <description>Not Acknowledge flag clear</description>
  14960. <bitOffset>4</bitOffset>
  14961. <bitWidth>1</bitWidth>
  14962. </field>
  14963. <field>
  14964. <name>ADDRCF</name>
  14965. <description>Address Matched flag clear</description>
  14966. <bitOffset>3</bitOffset>
  14967. <bitWidth>1</bitWidth>
  14968. </field>
  14969. </fields>
  14970. </register>
  14971. <register>
  14972. <name>PECR</name>
  14973. <displayName>PECR</displayName>
  14974. <description>PEC register</description>
  14975. <addressOffset>0x20</addressOffset>
  14976. <size>0x20</size>
  14977. <access>read-only</access>
  14978. <resetValue>0x00000000</resetValue>
  14979. <fields>
  14980. <field>
  14981. <name>PEC</name>
  14982. <description>Packet error checking
  14983. register</description>
  14984. <bitOffset>0</bitOffset>
  14985. <bitWidth>8</bitWidth>
  14986. </field>
  14987. </fields>
  14988. </register>
  14989. <register>
  14990. <name>RXDR</name>
  14991. <displayName>RXDR</displayName>
  14992. <description>Receive data register</description>
  14993. <addressOffset>0x24</addressOffset>
  14994. <size>0x20</size>
  14995. <access>read-only</access>
  14996. <resetValue>0x00000000</resetValue>
  14997. <fields>
  14998. <field>
  14999. <name>RXDATA</name>
  15000. <description>8-bit receive data</description>
  15001. <bitOffset>0</bitOffset>
  15002. <bitWidth>8</bitWidth>
  15003. </field>
  15004. </fields>
  15005. </register>
  15006. <register>
  15007. <name>TXDR</name>
  15008. <displayName>TXDR</displayName>
  15009. <description>Transmit data register</description>
  15010. <addressOffset>0x28</addressOffset>
  15011. <size>0x20</size>
  15012. <access>read-write</access>
  15013. <resetValue>0x00000000</resetValue>
  15014. <fields>
  15015. <field>
  15016. <name>TXDATA</name>
  15017. <description>8-bit transmit data</description>
  15018. <bitOffset>0</bitOffset>
  15019. <bitWidth>8</bitWidth>
  15020. </field>
  15021. </fields>
  15022. </register>
  15023. </registers>
  15024. </peripheral>
  15025. <peripheral derivedFrom="I2C1">
  15026. <name>I2C2</name>
  15027. <baseAddress>0x40005800</baseAddress>
  15028. <interrupt>
  15029. <name>I2C2</name>
  15030. <description>I2C2 global interrupt</description>
  15031. <value>24</value>
  15032. </interrupt>
  15033. </peripheral>
  15034. <peripheral>
  15035. <name>PWR</name>
  15036. <description>Power control</description>
  15037. <groupName>PWR</groupName>
  15038. <baseAddress>0x40007000</baseAddress>
  15039. <addressBlock>
  15040. <offset>0x0</offset>
  15041. <size>0x400</size>
  15042. <usage>registers</usage>
  15043. </addressBlock>
  15044. <registers>
  15045. <register>
  15046. <name>CR</name>
  15047. <displayName>CR</displayName>
  15048. <description>power control register</description>
  15049. <addressOffset>0x0</addressOffset>
  15050. <size>0x20</size>
  15051. <access>read-write</access>
  15052. <resetValue>0x00001000</resetValue>
  15053. <fields>
  15054. <field>
  15055. <name>LPDS</name>
  15056. <description>Low-power deep sleep</description>
  15057. <bitOffset>0</bitOffset>
  15058. <bitWidth>1</bitWidth>
  15059. </field>
  15060. <field>
  15061. <name>PDDS</name>
  15062. <description>Power down deepsleep</description>
  15063. <bitOffset>1</bitOffset>
  15064. <bitWidth>1</bitWidth>
  15065. </field>
  15066. <field>
  15067. <name>CWUF</name>
  15068. <description>Clear wakeup flag</description>
  15069. <bitOffset>2</bitOffset>
  15070. <bitWidth>1</bitWidth>
  15071. </field>
  15072. <field>
  15073. <name>CSBF</name>
  15074. <description>Clear standby flag</description>
  15075. <bitOffset>3</bitOffset>
  15076. <bitWidth>1</bitWidth>
  15077. </field>
  15078. <field>
  15079. <name>PVDE</name>
  15080. <description>Power voltage detector
  15081. enable</description>
  15082. <bitOffset>4</bitOffset>
  15083. <bitWidth>1</bitWidth>
  15084. </field>
  15085. <field>
  15086. <name>PLS</name>
  15087. <description>PVD level selection</description>
  15088. <bitOffset>5</bitOffset>
  15089. <bitWidth>3</bitWidth>
  15090. </field>
  15091. <field>
  15092. <name>DBP</name>
  15093. <description>Disable backup domain write
  15094. protection</description>
  15095. <bitOffset>8</bitOffset>
  15096. <bitWidth>1</bitWidth>
  15097. </field>
  15098. <field>
  15099. <name>ULP</name>
  15100. <description>Ultra-low-power mode</description>
  15101. <bitOffset>9</bitOffset>
  15102. <bitWidth>1</bitWidth>
  15103. </field>
  15104. <field>
  15105. <name>FWU</name>
  15106. <description>Fast wakeup</description>
  15107. <bitOffset>10</bitOffset>
  15108. <bitWidth>1</bitWidth>
  15109. </field>
  15110. <field>
  15111. <name>VOS</name>
  15112. <description>Voltage scaling range
  15113. selection</description>
  15114. <bitOffset>11</bitOffset>
  15115. <bitWidth>2</bitWidth>
  15116. </field>
  15117. <field>
  15118. <name>DS_EE_KOFF</name>
  15119. <description>Deep sleep mode with Flash memory kept
  15120. off</description>
  15121. <bitOffset>13</bitOffset>
  15122. <bitWidth>1</bitWidth>
  15123. </field>
  15124. <field>
  15125. <name>LPRUN</name>
  15126. <description>Low power run mode</description>
  15127. <bitOffset>14</bitOffset>
  15128. <bitWidth>1</bitWidth>
  15129. </field>
  15130. </fields>
  15131. </register>
  15132. <register>
  15133. <name>CSR</name>
  15134. <displayName>CSR</displayName>
  15135. <description>power control/status register</description>
  15136. <addressOffset>0x4</addressOffset>
  15137. <size>0x20</size>
  15138. <resetValue>0x00000000</resetValue>
  15139. <fields>
  15140. <field>
  15141. <name>BRE</name>
  15142. <description>Backup regulator enable</description>
  15143. <bitOffset>9</bitOffset>
  15144. <bitWidth>1</bitWidth>
  15145. <access>read-write</access>
  15146. </field>
  15147. <field>
  15148. <name>EWUP</name>
  15149. <description>Enable WKUP pin</description>
  15150. <bitOffset>8</bitOffset>
  15151. <bitWidth>1</bitWidth>
  15152. <access>read-write</access>
  15153. </field>
  15154. <field>
  15155. <name>BRR</name>
  15156. <description>Backup regulator ready</description>
  15157. <bitOffset>3</bitOffset>
  15158. <bitWidth>1</bitWidth>
  15159. <access>read-only</access>
  15160. </field>
  15161. <field>
  15162. <name>PVDO</name>
  15163. <description>PVD output</description>
  15164. <bitOffset>2</bitOffset>
  15165. <bitWidth>1</bitWidth>
  15166. <access>read-only</access>
  15167. </field>
  15168. <field>
  15169. <name>SBF</name>
  15170. <description>Standby flag</description>
  15171. <bitOffset>1</bitOffset>
  15172. <bitWidth>1</bitWidth>
  15173. <access>read-only</access>
  15174. </field>
  15175. <field>
  15176. <name>WUF</name>
  15177. <description>Wakeup flag</description>
  15178. <bitOffset>0</bitOffset>
  15179. <bitWidth>1</bitWidth>
  15180. <access>read-only</access>
  15181. </field>
  15182. <field>
  15183. <name>VOSF</name>
  15184. <description>Voltage Scaling select
  15185. flag</description>
  15186. <bitOffset>4</bitOffset>
  15187. <bitWidth>1</bitWidth>
  15188. <access>read-only</access>
  15189. </field>
  15190. <field>
  15191. <name>REGLPF</name>
  15192. <description>Regulator LP flag</description>
  15193. <bitOffset>5</bitOffset>
  15194. <bitWidth>1</bitWidth>
  15195. <access>read-only</access>
  15196. </field>
  15197. </fields>
  15198. </register>
  15199. </registers>
  15200. </peripheral>
  15201. <peripheral>
  15202. <name>Flash</name>
  15203. <description>Flash</description>
  15204. <groupName>Flash</groupName>
  15205. <baseAddress>0x40022000</baseAddress>
  15206. <addressBlock>
  15207. <offset>0x0</offset>
  15208. <size>0x400</size>
  15209. <usage>registers</usage>
  15210. </addressBlock>
  15211. <interrupt>
  15212. <name>FLASH</name>
  15213. <description>Flash global interrupt</description>
  15214. <value>3</value>
  15215. </interrupt>
  15216. <registers>
  15217. <register>
  15218. <name>ACR</name>
  15219. <displayName>ACR</displayName>
  15220. <description>Access control register</description>
  15221. <addressOffset>0x0</addressOffset>
  15222. <size>0x20</size>
  15223. <access>read-write</access>
  15224. <resetValue>0x00000000</resetValue>
  15225. <fields>
  15226. <field>
  15227. <name>LATENCY</name>
  15228. <description>Latency</description>
  15229. <bitOffset>0</bitOffset>
  15230. <bitWidth>1</bitWidth>
  15231. </field>
  15232. <field>
  15233. <name>PRFTEN</name>
  15234. <description>Prefetch enable</description>
  15235. <bitOffset>1</bitOffset>
  15236. <bitWidth>1</bitWidth>
  15237. </field>
  15238. <field>
  15239. <name>SLEEP_PD</name>
  15240. <description>Flash mode during Sleep</description>
  15241. <bitOffset>3</bitOffset>
  15242. <bitWidth>1</bitWidth>
  15243. </field>
  15244. <field>
  15245. <name>RUN_PD</name>
  15246. <description>Flash mode during Run</description>
  15247. <bitOffset>4</bitOffset>
  15248. <bitWidth>1</bitWidth>
  15249. </field>
  15250. <field>
  15251. <name>DESAB_BUF</name>
  15252. <description>Disable Buffer</description>
  15253. <bitOffset>5</bitOffset>
  15254. <bitWidth>1</bitWidth>
  15255. </field>
  15256. <field>
  15257. <name>PRE_READ</name>
  15258. <description>Pre-read data address</description>
  15259. <bitOffset>6</bitOffset>
  15260. <bitWidth>1</bitWidth>
  15261. </field>
  15262. </fields>
  15263. </register>
  15264. <register>
  15265. <name>PECR</name>
  15266. <displayName>PECR</displayName>
  15267. <description>Program/erase control register</description>
  15268. <addressOffset>0x4</addressOffset>
  15269. <size>0x20</size>
  15270. <access>read-write</access>
  15271. <resetValue>0x00000007</resetValue>
  15272. <fields>
  15273. <field>
  15274. <name>PELOCK</name>
  15275. <description>FLASH_PECR and data EEPROM
  15276. lock</description>
  15277. <bitOffset>0</bitOffset>
  15278. <bitWidth>1</bitWidth>
  15279. </field>
  15280. <field>
  15281. <name>PRGLOCK</name>
  15282. <description>Program memory lock</description>
  15283. <bitOffset>1</bitOffset>
  15284. <bitWidth>1</bitWidth>
  15285. </field>
  15286. <field>
  15287. <name>OPTLOCK</name>
  15288. <description>Option bytes block lock</description>
  15289. <bitOffset>2</bitOffset>
  15290. <bitWidth>1</bitWidth>
  15291. </field>
  15292. <field>
  15293. <name>PROG</name>
  15294. <description>Program memory selection</description>
  15295. <bitOffset>3</bitOffset>
  15296. <bitWidth>1</bitWidth>
  15297. </field>
  15298. <field>
  15299. <name>DATA</name>
  15300. <description>Data EEPROM selection</description>
  15301. <bitOffset>4</bitOffset>
  15302. <bitWidth>1</bitWidth>
  15303. </field>
  15304. <field>
  15305. <name>FTDW</name>
  15306. <description>Fixed time data write for Byte, Half
  15307. Word and Word programming</description>
  15308. <bitOffset>8</bitOffset>
  15309. <bitWidth>1</bitWidth>
  15310. </field>
  15311. <field>
  15312. <name>ERASE</name>
  15313. <description>Page or Double Word erase
  15314. mode</description>
  15315. <bitOffset>9</bitOffset>
  15316. <bitWidth>1</bitWidth>
  15317. </field>
  15318. <field>
  15319. <name>FPRG</name>
  15320. <description>Half Page/Double Word programming
  15321. mode</description>
  15322. <bitOffset>10</bitOffset>
  15323. <bitWidth>1</bitWidth>
  15324. </field>
  15325. <field>
  15326. <name>PARALLELBANK</name>
  15327. <description>Parallel bank mode</description>
  15328. <bitOffset>15</bitOffset>
  15329. <bitWidth>1</bitWidth>
  15330. </field>
  15331. <field>
  15332. <name>EOPIE</name>
  15333. <description>End of programming interrupt
  15334. enable</description>
  15335. <bitOffset>16</bitOffset>
  15336. <bitWidth>1</bitWidth>
  15337. </field>
  15338. <field>
  15339. <name>ERRIE</name>
  15340. <description>Error interrupt enable</description>
  15341. <bitOffset>17</bitOffset>
  15342. <bitWidth>1</bitWidth>
  15343. </field>
  15344. <field>
  15345. <name>OBL_LAUNCH</name>
  15346. <description>Launch the option byte
  15347. loading</description>
  15348. <bitOffset>18</bitOffset>
  15349. <bitWidth>1</bitWidth>
  15350. </field>
  15351. </fields>
  15352. </register>
  15353. <register>
  15354. <name>PDKEYR</name>
  15355. <displayName>PDKEYR</displayName>
  15356. <description>Power down key register</description>
  15357. <addressOffset>0x8</addressOffset>
  15358. <size>0x20</size>
  15359. <access>write-only</access>
  15360. <resetValue>0x00000000</resetValue>
  15361. <fields>
  15362. <field>
  15363. <name>PDKEYR</name>
  15364. <description>RUN_PD in FLASH_ACR key</description>
  15365. <bitOffset>0</bitOffset>
  15366. <bitWidth>32</bitWidth>
  15367. </field>
  15368. </fields>
  15369. </register>
  15370. <register>
  15371. <name>PEKEYR</name>
  15372. <displayName>PEKEYR</displayName>
  15373. <description>Program/erase key register</description>
  15374. <addressOffset>0xC</addressOffset>
  15375. <size>0x20</size>
  15376. <access>write-only</access>
  15377. <resetValue>0x00000000</resetValue>
  15378. <fields>
  15379. <field>
  15380. <name>PEKEYR</name>
  15381. <description>FLASH_PEC and data EEPROM
  15382. key</description>
  15383. <bitOffset>0</bitOffset>
  15384. <bitWidth>32</bitWidth>
  15385. </field>
  15386. </fields>
  15387. </register>
  15388. <register>
  15389. <name>PRGKEYR</name>
  15390. <displayName>PRGKEYR</displayName>
  15391. <description>Program memory key register</description>
  15392. <addressOffset>0x10</addressOffset>
  15393. <size>0x20</size>
  15394. <access>write-only</access>
  15395. <resetValue>0x00000000</resetValue>
  15396. <fields>
  15397. <field>
  15398. <name>PRGKEYR</name>
  15399. <description>Program memory key</description>
  15400. <bitOffset>0</bitOffset>
  15401. <bitWidth>32</bitWidth>
  15402. </field>
  15403. </fields>
  15404. </register>
  15405. <register>
  15406. <name>OPTKEYR</name>
  15407. <displayName>OPTKEYR</displayName>
  15408. <description>Option byte key register</description>
  15409. <addressOffset>0x14</addressOffset>
  15410. <size>0x20</size>
  15411. <access>write-only</access>
  15412. <resetValue>0x00000000</resetValue>
  15413. <fields>
  15414. <field>
  15415. <name>OPTKEYR</name>
  15416. <description>Option byte key</description>
  15417. <bitOffset>0</bitOffset>
  15418. <bitWidth>32</bitWidth>
  15419. </field>
  15420. </fields>
  15421. </register>
  15422. <register>
  15423. <name>SR</name>
  15424. <displayName>SR</displayName>
  15425. <description>Status register</description>
  15426. <addressOffset>0x18</addressOffset>
  15427. <size>0x20</size>
  15428. <resetValue>0x00000004</resetValue>
  15429. <fields>
  15430. <field>
  15431. <name>BSY</name>
  15432. <description>Write/erase operations in
  15433. progress</description>
  15434. <bitOffset>0</bitOffset>
  15435. <bitWidth>1</bitWidth>
  15436. <access>read-only</access>
  15437. </field>
  15438. <field>
  15439. <name>EOP</name>
  15440. <description>End of operation</description>
  15441. <bitOffset>1</bitOffset>
  15442. <bitWidth>1</bitWidth>
  15443. <access>read-only</access>
  15444. </field>
  15445. <field>
  15446. <name>ENDHV</name>
  15447. <description>End of high voltage</description>
  15448. <bitOffset>2</bitOffset>
  15449. <bitWidth>1</bitWidth>
  15450. <access>read-only</access>
  15451. </field>
  15452. <field>
  15453. <name>READY</name>
  15454. <description>Flash memory module ready after low
  15455. power mode</description>
  15456. <bitOffset>3</bitOffset>
  15457. <bitWidth>1</bitWidth>
  15458. <access>read-only</access>
  15459. </field>
  15460. <field>
  15461. <name>WRPERR</name>
  15462. <description>Write protected error</description>
  15463. <bitOffset>8</bitOffset>
  15464. <bitWidth>1</bitWidth>
  15465. <access>read-write</access>
  15466. </field>
  15467. <field>
  15468. <name>PGAERR</name>
  15469. <description>Programming alignment
  15470. error</description>
  15471. <bitOffset>9</bitOffset>
  15472. <bitWidth>1</bitWidth>
  15473. <access>read-write</access>
  15474. </field>
  15475. <field>
  15476. <name>SIZERR</name>
  15477. <description>Size error</description>
  15478. <bitOffset>10</bitOffset>
  15479. <bitWidth>1</bitWidth>
  15480. <access>read-write</access>
  15481. </field>
  15482. <field>
  15483. <name>OPTVERR</name>
  15484. <description>Option validity error</description>
  15485. <bitOffset>11</bitOffset>
  15486. <bitWidth>1</bitWidth>
  15487. <access>read-write</access>
  15488. </field>
  15489. <field>
  15490. <name>RDERR</name>
  15491. <description>RDERR</description>
  15492. <bitOffset>14</bitOffset>
  15493. <bitWidth>1</bitWidth>
  15494. <access>read-write</access>
  15495. </field>
  15496. <field>
  15497. <name>NOTZEROERR</name>
  15498. <description>NOTZEROERR</description>
  15499. <bitOffset>16</bitOffset>
  15500. <bitWidth>1</bitWidth>
  15501. <access>read-write</access>
  15502. </field>
  15503. <field>
  15504. <name>FWWERR</name>
  15505. <description>FWWERR</description>
  15506. <bitOffset>17</bitOffset>
  15507. <bitWidth>1</bitWidth>
  15508. <access>read-write</access>
  15509. </field>
  15510. </fields>
  15511. </register>
  15512. <register>
  15513. <name>OBR</name>
  15514. <displayName>OBR</displayName>
  15515. <description>Option byte register</description>
  15516. <addressOffset>0x1C</addressOffset>
  15517. <size>0x20</size>
  15518. <access>read-only</access>
  15519. <resetValue>0x00F80000</resetValue>
  15520. <fields>
  15521. <field>
  15522. <name>RDPRT</name>
  15523. <description>Read protection</description>
  15524. <bitOffset>0</bitOffset>
  15525. <bitWidth>8</bitWidth>
  15526. </field>
  15527. <field>
  15528. <name>BOR_LEV</name>
  15529. <description>BOR_LEV</description>
  15530. <bitOffset>16</bitOffset>
  15531. <bitWidth>4</bitWidth>
  15532. </field>
  15533. <field>
  15534. <name>SPRMOD</name>
  15535. <description>Selection of protection mode of WPR
  15536. bits</description>
  15537. <bitOffset>8</bitOffset>
  15538. <bitWidth>1</bitWidth>
  15539. </field>
  15540. </fields>
  15541. </register>
  15542. <register>
  15543. <name>WRPR</name>
  15544. <displayName>WRPR</displayName>
  15545. <description>Write protection register</description>
  15546. <addressOffset>0x20</addressOffset>
  15547. <size>0x20</size>
  15548. <access>read-write</access>
  15549. <resetValue>0x00000000</resetValue>
  15550. <fields>
  15551. <field>
  15552. <name>WRP</name>
  15553. <description>Write protection</description>
  15554. <bitOffset>0</bitOffset>
  15555. <bitWidth>16</bitWidth>
  15556. </field>
  15557. </fields>
  15558. </register>
  15559. </registers>
  15560. </peripheral>
  15561. <peripheral>
  15562. <name>EXTI</name>
  15563. <description>External interrupt/event
  15564. controller</description>
  15565. <groupName>EXTI</groupName>
  15566. <baseAddress>0x40010400</baseAddress>
  15567. <addressBlock>
  15568. <offset>0x0</offset>
  15569. <size>0x400</size>
  15570. <usage>registers</usage>
  15571. </addressBlock>
  15572. <interrupt>
  15573. <name>PVD</name>
  15574. <description>PVD through EXTI line detection</description>
  15575. <value>1</value>
  15576. </interrupt>
  15577. <interrupt>
  15578. <name>EXTI0_1</name>
  15579. <description>EXTI Line[1:0] interrupts</description>
  15580. <value>5</value>
  15581. </interrupt>
  15582. <interrupt>
  15583. <name>EXTI2_3</name>
  15584. <description>EXTI Line[3:2] interrupts</description>
  15585. <value>6</value>
  15586. </interrupt>
  15587. <interrupt>
  15588. <name>EXTI4_15</name>
  15589. <description>EXTI Line15 and EXTI4 interrupts</description>
  15590. <value>7</value>
  15591. </interrupt>
  15592. <registers>
  15593. <register>
  15594. <name>IMR</name>
  15595. <displayName>IMR</displayName>
  15596. <description>Interrupt mask register
  15597. (EXTI_IMR)</description>
  15598. <addressOffset>0x0</addressOffset>
  15599. <size>0x20</size>
  15600. <access>read-write</access>
  15601. <resetValue>0xFF840000</resetValue>
  15602. <fields>
  15603. <field>
  15604. <name>MR0</name>
  15605. <description>Interrupt Mask on line 0</description>
  15606. <bitOffset>0</bitOffset>
  15607. <bitWidth>1</bitWidth>
  15608. </field>
  15609. <field>
  15610. <name>MR1</name>
  15611. <description>Interrupt Mask on line 1</description>
  15612. <bitOffset>1</bitOffset>
  15613. <bitWidth>1</bitWidth>
  15614. </field>
  15615. <field>
  15616. <name>MR2</name>
  15617. <description>Interrupt Mask on line 2</description>
  15618. <bitOffset>2</bitOffset>
  15619. <bitWidth>1</bitWidth>
  15620. </field>
  15621. <field>
  15622. <name>MR3</name>
  15623. <description>Interrupt Mask on line 3</description>
  15624. <bitOffset>3</bitOffset>
  15625. <bitWidth>1</bitWidth>
  15626. </field>
  15627. <field>
  15628. <name>MR4</name>
  15629. <description>Interrupt Mask on line 4</description>
  15630. <bitOffset>4</bitOffset>
  15631. <bitWidth>1</bitWidth>
  15632. </field>
  15633. <field>
  15634. <name>MR5</name>
  15635. <description>Interrupt Mask on line 5</description>
  15636. <bitOffset>5</bitOffset>
  15637. <bitWidth>1</bitWidth>
  15638. </field>
  15639. <field>
  15640. <name>MR6</name>
  15641. <description>Interrupt Mask on line 6</description>
  15642. <bitOffset>6</bitOffset>
  15643. <bitWidth>1</bitWidth>
  15644. </field>
  15645. <field>
  15646. <name>MR7</name>
  15647. <description>Interrupt Mask on line 7</description>
  15648. <bitOffset>7</bitOffset>
  15649. <bitWidth>1</bitWidth>
  15650. </field>
  15651. <field>
  15652. <name>MR8</name>
  15653. <description>Interrupt Mask on line 8</description>
  15654. <bitOffset>8</bitOffset>
  15655. <bitWidth>1</bitWidth>
  15656. </field>
  15657. <field>
  15658. <name>MR9</name>
  15659. <description>Interrupt Mask on line 9</description>
  15660. <bitOffset>9</bitOffset>
  15661. <bitWidth>1</bitWidth>
  15662. </field>
  15663. <field>
  15664. <name>MR10</name>
  15665. <description>Interrupt Mask on line 10</description>
  15666. <bitOffset>10</bitOffset>
  15667. <bitWidth>1</bitWidth>
  15668. </field>
  15669. <field>
  15670. <name>MR11</name>
  15671. <description>Interrupt Mask on line 11</description>
  15672. <bitOffset>11</bitOffset>
  15673. <bitWidth>1</bitWidth>
  15674. </field>
  15675. <field>
  15676. <name>MR12</name>
  15677. <description>Interrupt Mask on line 12</description>
  15678. <bitOffset>12</bitOffset>
  15679. <bitWidth>1</bitWidth>
  15680. </field>
  15681. <field>
  15682. <name>MR13</name>
  15683. <description>Interrupt Mask on line 13</description>
  15684. <bitOffset>13</bitOffset>
  15685. <bitWidth>1</bitWidth>
  15686. </field>
  15687. <field>
  15688. <name>MR14</name>
  15689. <description>Interrupt Mask on line 14</description>
  15690. <bitOffset>14</bitOffset>
  15691. <bitWidth>1</bitWidth>
  15692. </field>
  15693. <field>
  15694. <name>MR15</name>
  15695. <description>Interrupt Mask on line 15</description>
  15696. <bitOffset>15</bitOffset>
  15697. <bitWidth>1</bitWidth>
  15698. </field>
  15699. <field>
  15700. <name>MR16</name>
  15701. <description>Interrupt Mask on line 16</description>
  15702. <bitOffset>16</bitOffset>
  15703. <bitWidth>1</bitWidth>
  15704. </field>
  15705. <field>
  15706. <name>MR17</name>
  15707. <description>Interrupt Mask on line 17</description>
  15708. <bitOffset>17</bitOffset>
  15709. <bitWidth>1</bitWidth>
  15710. </field>
  15711. <field>
  15712. <name>MR19</name>
  15713. <description>Interrupt Mask on line 19</description>
  15714. <bitOffset>19</bitOffset>
  15715. <bitWidth>1</bitWidth>
  15716. </field>
  15717. <field>
  15718. <name>MR21</name>
  15719. <description>Interrupt Mask on line 21</description>
  15720. <bitOffset>21</bitOffset>
  15721. <bitWidth>1</bitWidth>
  15722. </field>
  15723. <field>
  15724. <name>MR22</name>
  15725. <description>Interrupt Mask on line 22</description>
  15726. <bitOffset>22</bitOffset>
  15727. <bitWidth>1</bitWidth>
  15728. </field>
  15729. <field>
  15730. <name>MR23</name>
  15731. <description>Interrupt Mask on line 23</description>
  15732. <bitOffset>23</bitOffset>
  15733. <bitWidth>1</bitWidth>
  15734. </field>
  15735. <field>
  15736. <name>MR25</name>
  15737. <description>Interrupt Mask on line 25</description>
  15738. <bitOffset>25</bitOffset>
  15739. <bitWidth>1</bitWidth>
  15740. </field>
  15741. <field>
  15742. <name>MR27</name>
  15743. <description>Interrupt Mask on line 27</description>
  15744. <bitOffset>27</bitOffset>
  15745. <bitWidth>1</bitWidth>
  15746. </field>
  15747. </fields>
  15748. </register>
  15749. <register>
  15750. <name>EMR</name>
  15751. <displayName>EMR</displayName>
  15752. <description>Event mask register (EXTI_EMR)</description>
  15753. <addressOffset>0x4</addressOffset>
  15754. <size>0x20</size>
  15755. <access>read-write</access>
  15756. <resetValue>0x00000000</resetValue>
  15757. <fields>
  15758. <field>
  15759. <name>MR0</name>
  15760. <description>Event Mask on line 0</description>
  15761. <bitOffset>0</bitOffset>
  15762. <bitWidth>1</bitWidth>
  15763. </field>
  15764. <field>
  15765. <name>MR1</name>
  15766. <description>Event Mask on line 1</description>
  15767. <bitOffset>1</bitOffset>
  15768. <bitWidth>1</bitWidth>
  15769. </field>
  15770. <field>
  15771. <name>MR2</name>
  15772. <description>Event Mask on line 2</description>
  15773. <bitOffset>2</bitOffset>
  15774. <bitWidth>1</bitWidth>
  15775. </field>
  15776. <field>
  15777. <name>MR3</name>
  15778. <description>Event Mask on line 3</description>
  15779. <bitOffset>3</bitOffset>
  15780. <bitWidth>1</bitWidth>
  15781. </field>
  15782. <field>
  15783. <name>MR4</name>
  15784. <description>Event Mask on line 4</description>
  15785. <bitOffset>4</bitOffset>
  15786. <bitWidth>1</bitWidth>
  15787. </field>
  15788. <field>
  15789. <name>MR5</name>
  15790. <description>Event Mask on line 5</description>
  15791. <bitOffset>5</bitOffset>
  15792. <bitWidth>1</bitWidth>
  15793. </field>
  15794. <field>
  15795. <name>MR6</name>
  15796. <description>Event Mask on line 6</description>
  15797. <bitOffset>6</bitOffset>
  15798. <bitWidth>1</bitWidth>
  15799. </field>
  15800. <field>
  15801. <name>MR7</name>
  15802. <description>Event Mask on line 7</description>
  15803. <bitOffset>7</bitOffset>
  15804. <bitWidth>1</bitWidth>
  15805. </field>
  15806. <field>
  15807. <name>MR8</name>
  15808. <description>Event Mask on line 8</description>
  15809. <bitOffset>8</bitOffset>
  15810. <bitWidth>1</bitWidth>
  15811. </field>
  15812. <field>
  15813. <name>MR9</name>
  15814. <description>Event Mask on line 9</description>
  15815. <bitOffset>9</bitOffset>
  15816. <bitWidth>1</bitWidth>
  15817. </field>
  15818. <field>
  15819. <name>MR10</name>
  15820. <description>Event Mask on line 10</description>
  15821. <bitOffset>10</bitOffset>
  15822. <bitWidth>1</bitWidth>
  15823. </field>
  15824. <field>
  15825. <name>MR11</name>
  15826. <description>Event Mask on line 11</description>
  15827. <bitOffset>11</bitOffset>
  15828. <bitWidth>1</bitWidth>
  15829. </field>
  15830. <field>
  15831. <name>MR12</name>
  15832. <description>Event Mask on line 12</description>
  15833. <bitOffset>12</bitOffset>
  15834. <bitWidth>1</bitWidth>
  15835. </field>
  15836. <field>
  15837. <name>MR13</name>
  15838. <description>Event Mask on line 13</description>
  15839. <bitOffset>13</bitOffset>
  15840. <bitWidth>1</bitWidth>
  15841. </field>
  15842. <field>
  15843. <name>MR14</name>
  15844. <description>Event Mask on line 14</description>
  15845. <bitOffset>14</bitOffset>
  15846. <bitWidth>1</bitWidth>
  15847. </field>
  15848. <field>
  15849. <name>MR15</name>
  15850. <description>Event Mask on line 15</description>
  15851. <bitOffset>15</bitOffset>
  15852. <bitWidth>1</bitWidth>
  15853. </field>
  15854. <field>
  15855. <name>MR16</name>
  15856. <description>Event Mask on line 16</description>
  15857. <bitOffset>16</bitOffset>
  15858. <bitWidth>1</bitWidth>
  15859. </field>
  15860. <field>
  15861. <name>MR17</name>
  15862. <description>Event Mask on line 17</description>
  15863. <bitOffset>17</bitOffset>
  15864. <bitWidth>1</bitWidth>
  15865. </field>
  15866. <field>
  15867. <name>MR19</name>
  15868. <description>Event Mask on line 19</description>
  15869. <bitOffset>19</bitOffset>
  15870. <bitWidth>1</bitWidth>
  15871. </field>
  15872. <field>
  15873. <name>MR21</name>
  15874. <description>Event Mask on line 21</description>
  15875. <bitOffset>21</bitOffset>
  15876. <bitWidth>1</bitWidth>
  15877. </field>
  15878. <field>
  15879. <name>MR22</name>
  15880. <description>Event Mask on line 22</description>
  15881. <bitOffset>22</bitOffset>
  15882. <bitWidth>1</bitWidth>
  15883. </field>
  15884. <field>
  15885. <name>MR23</name>
  15886. <description>Event Mask on line 23</description>
  15887. <bitOffset>23</bitOffset>
  15888. <bitWidth>1</bitWidth>
  15889. </field>
  15890. <field>
  15891. <name>MR25</name>
  15892. <description>Event Mask on line 25</description>
  15893. <bitOffset>25</bitOffset>
  15894. <bitWidth>1</bitWidth>
  15895. </field>
  15896. <field>
  15897. <name>MR27</name>
  15898. <description>Event Mask on line 27</description>
  15899. <bitOffset>27</bitOffset>
  15900. <bitWidth>1</bitWidth>
  15901. </field>
  15902. </fields>
  15903. </register>
  15904. <register>
  15905. <name>RTSR</name>
  15906. <displayName>RTSR</displayName>
  15907. <description>Rising Trigger selection register
  15908. (EXTI_RTSR)</description>
  15909. <addressOffset>0x8</addressOffset>
  15910. <size>0x20</size>
  15911. <access>read-write</access>
  15912. <resetValue>0x00000000</resetValue>
  15913. <fields>
  15914. <field>
  15915. <name>TR0</name>
  15916. <description>Rising trigger event configuration of
  15917. line 0</description>
  15918. <bitOffset>0</bitOffset>
  15919. <bitWidth>1</bitWidth>
  15920. </field>
  15921. <field>
  15922. <name>TR1</name>
  15923. <description>Rising trigger event configuration of
  15924. line 1</description>
  15925. <bitOffset>1</bitOffset>
  15926. <bitWidth>1</bitWidth>
  15927. </field>
  15928. <field>
  15929. <name>TR2</name>
  15930. <description>Rising trigger event configuration of
  15931. line 2</description>
  15932. <bitOffset>2</bitOffset>
  15933. <bitWidth>1</bitWidth>
  15934. </field>
  15935. <field>
  15936. <name>TR3</name>
  15937. <description>Rising trigger event configuration of
  15938. line 3</description>
  15939. <bitOffset>3</bitOffset>
  15940. <bitWidth>1</bitWidth>
  15941. </field>
  15942. <field>
  15943. <name>TR4</name>
  15944. <description>Rising trigger event configuration of
  15945. line 4</description>
  15946. <bitOffset>4</bitOffset>
  15947. <bitWidth>1</bitWidth>
  15948. </field>
  15949. <field>
  15950. <name>TR5</name>
  15951. <description>Rising trigger event configuration of
  15952. line 5</description>
  15953. <bitOffset>5</bitOffset>
  15954. <bitWidth>1</bitWidth>
  15955. </field>
  15956. <field>
  15957. <name>TR6</name>
  15958. <description>Rising trigger event configuration of
  15959. line 6</description>
  15960. <bitOffset>6</bitOffset>
  15961. <bitWidth>1</bitWidth>
  15962. </field>
  15963. <field>
  15964. <name>TR7</name>
  15965. <description>Rising trigger event configuration of
  15966. line 7</description>
  15967. <bitOffset>7</bitOffset>
  15968. <bitWidth>1</bitWidth>
  15969. </field>
  15970. <field>
  15971. <name>TR8</name>
  15972. <description>Rising trigger event configuration of
  15973. line 8</description>
  15974. <bitOffset>8</bitOffset>
  15975. <bitWidth>1</bitWidth>
  15976. </field>
  15977. <field>
  15978. <name>TR9</name>
  15979. <description>Rising trigger event configuration of
  15980. line 9</description>
  15981. <bitOffset>9</bitOffset>
  15982. <bitWidth>1</bitWidth>
  15983. </field>
  15984. <field>
  15985. <name>TR10</name>
  15986. <description>Rising trigger event configuration of
  15987. line 10</description>
  15988. <bitOffset>10</bitOffset>
  15989. <bitWidth>1</bitWidth>
  15990. </field>
  15991. <field>
  15992. <name>TR11</name>
  15993. <description>Rising trigger event configuration of
  15994. line 11</description>
  15995. <bitOffset>11</bitOffset>
  15996. <bitWidth>1</bitWidth>
  15997. </field>
  15998. <field>
  15999. <name>TR12</name>
  16000. <description>Rising trigger event configuration of
  16001. line 12</description>
  16002. <bitOffset>12</bitOffset>
  16003. <bitWidth>1</bitWidth>
  16004. </field>
  16005. <field>
  16006. <name>TR13</name>
  16007. <description>Rising trigger event configuration of
  16008. line 13</description>
  16009. <bitOffset>13</bitOffset>
  16010. <bitWidth>1</bitWidth>
  16011. </field>
  16012. <field>
  16013. <name>TR14</name>
  16014. <description>Rising trigger event configuration of
  16015. line 14</description>
  16016. <bitOffset>14</bitOffset>
  16017. <bitWidth>1</bitWidth>
  16018. </field>
  16019. <field>
  16020. <name>TR15</name>
  16021. <description>Rising trigger event configuration of
  16022. line 15</description>
  16023. <bitOffset>15</bitOffset>
  16024. <bitWidth>1</bitWidth>
  16025. </field>
  16026. <field>
  16027. <name>TR16</name>
  16028. <description>Rising trigger event configuration of
  16029. line 16</description>
  16030. <bitOffset>16</bitOffset>
  16031. <bitWidth>1</bitWidth>
  16032. </field>
  16033. <field>
  16034. <name>TR17</name>
  16035. <description>Rising trigger event configuration of
  16036. line 17</description>
  16037. <bitOffset>17</bitOffset>
  16038. <bitWidth>1</bitWidth>
  16039. </field>
  16040. <field>
  16041. <name>TR19</name>
  16042. <description>Rising trigger event configuration of
  16043. line 19</description>
  16044. <bitOffset>19</bitOffset>
  16045. <bitWidth>1</bitWidth>
  16046. </field>
  16047. </fields>
  16048. </register>
  16049. <register>
  16050. <name>FTSR</name>
  16051. <displayName>FTSR</displayName>
  16052. <description>Falling Trigger selection register
  16053. (EXTI_FTSR)</description>
  16054. <addressOffset>0xC</addressOffset>
  16055. <size>0x20</size>
  16056. <access>read-write</access>
  16057. <resetValue>0x00000000</resetValue>
  16058. <fields>
  16059. <field>
  16060. <name>TR0</name>
  16061. <description>Falling trigger event configuration of
  16062. line 0</description>
  16063. <bitOffset>0</bitOffset>
  16064. <bitWidth>1</bitWidth>
  16065. </field>
  16066. <field>
  16067. <name>TR1</name>
  16068. <description>Falling trigger event configuration of
  16069. line 1</description>
  16070. <bitOffset>1</bitOffset>
  16071. <bitWidth>1</bitWidth>
  16072. </field>
  16073. <field>
  16074. <name>TR2</name>
  16075. <description>Falling trigger event configuration of
  16076. line 2</description>
  16077. <bitOffset>2</bitOffset>
  16078. <bitWidth>1</bitWidth>
  16079. </field>
  16080. <field>
  16081. <name>TR3</name>
  16082. <description>Falling trigger event configuration of
  16083. line 3</description>
  16084. <bitOffset>3</bitOffset>
  16085. <bitWidth>1</bitWidth>
  16086. </field>
  16087. <field>
  16088. <name>TR4</name>
  16089. <description>Falling trigger event configuration of
  16090. line 4</description>
  16091. <bitOffset>4</bitOffset>
  16092. <bitWidth>1</bitWidth>
  16093. </field>
  16094. <field>
  16095. <name>TR5</name>
  16096. <description>Falling trigger event configuration of
  16097. line 5</description>
  16098. <bitOffset>5</bitOffset>
  16099. <bitWidth>1</bitWidth>
  16100. </field>
  16101. <field>
  16102. <name>TR6</name>
  16103. <description>Falling trigger event configuration of
  16104. line 6</description>
  16105. <bitOffset>6</bitOffset>
  16106. <bitWidth>1</bitWidth>
  16107. </field>
  16108. <field>
  16109. <name>TR7</name>
  16110. <description>Falling trigger event configuration of
  16111. line 7</description>
  16112. <bitOffset>7</bitOffset>
  16113. <bitWidth>1</bitWidth>
  16114. </field>
  16115. <field>
  16116. <name>TR8</name>
  16117. <description>Falling trigger event configuration of
  16118. line 8</description>
  16119. <bitOffset>8</bitOffset>
  16120. <bitWidth>1</bitWidth>
  16121. </field>
  16122. <field>
  16123. <name>TR9</name>
  16124. <description>Falling trigger event configuration of
  16125. line 9</description>
  16126. <bitOffset>9</bitOffset>
  16127. <bitWidth>1</bitWidth>
  16128. </field>
  16129. <field>
  16130. <name>TR10</name>
  16131. <description>Falling trigger event configuration of
  16132. line 10</description>
  16133. <bitOffset>10</bitOffset>
  16134. <bitWidth>1</bitWidth>
  16135. </field>
  16136. <field>
  16137. <name>TR11</name>
  16138. <description>Falling trigger event configuration of
  16139. line 11</description>
  16140. <bitOffset>11</bitOffset>
  16141. <bitWidth>1</bitWidth>
  16142. </field>
  16143. <field>
  16144. <name>TR12</name>
  16145. <description>Falling trigger event configuration of
  16146. line 12</description>
  16147. <bitOffset>12</bitOffset>
  16148. <bitWidth>1</bitWidth>
  16149. </field>
  16150. <field>
  16151. <name>TR13</name>
  16152. <description>Falling trigger event configuration of
  16153. line 13</description>
  16154. <bitOffset>13</bitOffset>
  16155. <bitWidth>1</bitWidth>
  16156. </field>
  16157. <field>
  16158. <name>TR14</name>
  16159. <description>Falling trigger event configuration of
  16160. line 14</description>
  16161. <bitOffset>14</bitOffset>
  16162. <bitWidth>1</bitWidth>
  16163. </field>
  16164. <field>
  16165. <name>TR15</name>
  16166. <description>Falling trigger event configuration of
  16167. line 15</description>
  16168. <bitOffset>15</bitOffset>
  16169. <bitWidth>1</bitWidth>
  16170. </field>
  16171. <field>
  16172. <name>TR16</name>
  16173. <description>Falling trigger event configuration of
  16174. line 16</description>
  16175. <bitOffset>16</bitOffset>
  16176. <bitWidth>1</bitWidth>
  16177. </field>
  16178. <field>
  16179. <name>TR17</name>
  16180. <description>Falling trigger event configuration of
  16181. line 17</description>
  16182. <bitOffset>17</bitOffset>
  16183. <bitWidth>1</bitWidth>
  16184. </field>
  16185. <field>
  16186. <name>TR19</name>
  16187. <description>Falling trigger event configuration of
  16188. line 19</description>
  16189. <bitOffset>19</bitOffset>
  16190. <bitWidth>1</bitWidth>
  16191. </field>
  16192. </fields>
  16193. </register>
  16194. <register>
  16195. <name>SWIER</name>
  16196. <displayName>SWIER</displayName>
  16197. <description>Software interrupt event register
  16198. (EXTI_SWIER)</description>
  16199. <addressOffset>0x10</addressOffset>
  16200. <size>0x20</size>
  16201. <access>read-write</access>
  16202. <resetValue>0x00000000</resetValue>
  16203. <fields>
  16204. <field>
  16205. <name>SWIER0</name>
  16206. <description>Software Interrupt on line
  16207. 0</description>
  16208. <bitOffset>0</bitOffset>
  16209. <bitWidth>1</bitWidth>
  16210. </field>
  16211. <field>
  16212. <name>SWIER1</name>
  16213. <description>Software Interrupt on line
  16214. 1</description>
  16215. <bitOffset>1</bitOffset>
  16216. <bitWidth>1</bitWidth>
  16217. </field>
  16218. <field>
  16219. <name>SWIER2</name>
  16220. <description>Software Interrupt on line
  16221. 2</description>
  16222. <bitOffset>2</bitOffset>
  16223. <bitWidth>1</bitWidth>
  16224. </field>
  16225. <field>
  16226. <name>SWIER3</name>
  16227. <description>Software Interrupt on line
  16228. 3</description>
  16229. <bitOffset>3</bitOffset>
  16230. <bitWidth>1</bitWidth>
  16231. </field>
  16232. <field>
  16233. <name>SWIER4</name>
  16234. <description>Software Interrupt on line
  16235. 4</description>
  16236. <bitOffset>4</bitOffset>
  16237. <bitWidth>1</bitWidth>
  16238. </field>
  16239. <field>
  16240. <name>SWIER5</name>
  16241. <description>Software Interrupt on line
  16242. 5</description>
  16243. <bitOffset>5</bitOffset>
  16244. <bitWidth>1</bitWidth>
  16245. </field>
  16246. <field>
  16247. <name>SWIER6</name>
  16248. <description>Software Interrupt on line
  16249. 6</description>
  16250. <bitOffset>6</bitOffset>
  16251. <bitWidth>1</bitWidth>
  16252. </field>
  16253. <field>
  16254. <name>SWIER7</name>
  16255. <description>Software Interrupt on line
  16256. 7</description>
  16257. <bitOffset>7</bitOffset>
  16258. <bitWidth>1</bitWidth>
  16259. </field>
  16260. <field>
  16261. <name>SWIER8</name>
  16262. <description>Software Interrupt on line
  16263. 8</description>
  16264. <bitOffset>8</bitOffset>
  16265. <bitWidth>1</bitWidth>
  16266. </field>
  16267. <field>
  16268. <name>SWIER9</name>
  16269. <description>Software Interrupt on line
  16270. 9</description>
  16271. <bitOffset>9</bitOffset>
  16272. <bitWidth>1</bitWidth>
  16273. </field>
  16274. <field>
  16275. <name>SWIER10</name>
  16276. <description>Software Interrupt on line
  16277. 10</description>
  16278. <bitOffset>10</bitOffset>
  16279. <bitWidth>1</bitWidth>
  16280. </field>
  16281. <field>
  16282. <name>SWIER11</name>
  16283. <description>Software Interrupt on line
  16284. 11</description>
  16285. <bitOffset>11</bitOffset>
  16286. <bitWidth>1</bitWidth>
  16287. </field>
  16288. <field>
  16289. <name>SWIER12</name>
  16290. <description>Software Interrupt on line
  16291. 12</description>
  16292. <bitOffset>12</bitOffset>
  16293. <bitWidth>1</bitWidth>
  16294. </field>
  16295. <field>
  16296. <name>SWIER13</name>
  16297. <description>Software Interrupt on line
  16298. 13</description>
  16299. <bitOffset>13</bitOffset>
  16300. <bitWidth>1</bitWidth>
  16301. </field>
  16302. <field>
  16303. <name>SWIER14</name>
  16304. <description>Software Interrupt on line
  16305. 14</description>
  16306. <bitOffset>14</bitOffset>
  16307. <bitWidth>1</bitWidth>
  16308. </field>
  16309. <field>
  16310. <name>SWIER15</name>
  16311. <description>Software Interrupt on line
  16312. 15</description>
  16313. <bitOffset>15</bitOffset>
  16314. <bitWidth>1</bitWidth>
  16315. </field>
  16316. <field>
  16317. <name>SWIER16</name>
  16318. <description>Software Interrupt on line
  16319. 16</description>
  16320. <bitOffset>16</bitOffset>
  16321. <bitWidth>1</bitWidth>
  16322. </field>
  16323. <field>
  16324. <name>SWIER17</name>
  16325. <description>Software Interrupt on line
  16326. 17</description>
  16327. <bitOffset>17</bitOffset>
  16328. <bitWidth>1</bitWidth>
  16329. </field>
  16330. <field>
  16331. <name>SWIER19</name>
  16332. <description>Software Interrupt on line
  16333. 19</description>
  16334. <bitOffset>19</bitOffset>
  16335. <bitWidth>1</bitWidth>
  16336. </field>
  16337. </fields>
  16338. </register>
  16339. <register>
  16340. <name>PR</name>
  16341. <displayName>PR</displayName>
  16342. <description>Pending register (EXTI_PR)</description>
  16343. <addressOffset>0x14</addressOffset>
  16344. <size>0x20</size>
  16345. <access>read-write</access>
  16346. <resetValue>0x00000000</resetValue>
  16347. <fields>
  16348. <field>
  16349. <name>PR0</name>
  16350. <description>Pending bit 0</description>
  16351. <bitOffset>0</bitOffset>
  16352. <bitWidth>1</bitWidth>
  16353. </field>
  16354. <field>
  16355. <name>PR1</name>
  16356. <description>Pending bit 1</description>
  16357. <bitOffset>1</bitOffset>
  16358. <bitWidth>1</bitWidth>
  16359. </field>
  16360. <field>
  16361. <name>PR2</name>
  16362. <description>Pending bit 2</description>
  16363. <bitOffset>2</bitOffset>
  16364. <bitWidth>1</bitWidth>
  16365. </field>
  16366. <field>
  16367. <name>PR3</name>
  16368. <description>Pending bit 3</description>
  16369. <bitOffset>3</bitOffset>
  16370. <bitWidth>1</bitWidth>
  16371. </field>
  16372. <field>
  16373. <name>PR4</name>
  16374. <description>Pending bit 4</description>
  16375. <bitOffset>4</bitOffset>
  16376. <bitWidth>1</bitWidth>
  16377. </field>
  16378. <field>
  16379. <name>PR5</name>
  16380. <description>Pending bit 5</description>
  16381. <bitOffset>5</bitOffset>
  16382. <bitWidth>1</bitWidth>
  16383. </field>
  16384. <field>
  16385. <name>PR6</name>
  16386. <description>Pending bit 6</description>
  16387. <bitOffset>6</bitOffset>
  16388. <bitWidth>1</bitWidth>
  16389. </field>
  16390. <field>
  16391. <name>PR7</name>
  16392. <description>Pending bit 7</description>
  16393. <bitOffset>7</bitOffset>
  16394. <bitWidth>1</bitWidth>
  16395. </field>
  16396. <field>
  16397. <name>PR8</name>
  16398. <description>Pending bit 8</description>
  16399. <bitOffset>8</bitOffset>
  16400. <bitWidth>1</bitWidth>
  16401. </field>
  16402. <field>
  16403. <name>PR9</name>
  16404. <description>Pending bit 9</description>
  16405. <bitOffset>9</bitOffset>
  16406. <bitWidth>1</bitWidth>
  16407. </field>
  16408. <field>
  16409. <name>PR10</name>
  16410. <description>Pending bit 10</description>
  16411. <bitOffset>10</bitOffset>
  16412. <bitWidth>1</bitWidth>
  16413. </field>
  16414. <field>
  16415. <name>PR11</name>
  16416. <description>Pending bit 11</description>
  16417. <bitOffset>11</bitOffset>
  16418. <bitWidth>1</bitWidth>
  16419. </field>
  16420. <field>
  16421. <name>PR12</name>
  16422. <description>Pending bit 12</description>
  16423. <bitOffset>12</bitOffset>
  16424. <bitWidth>1</bitWidth>
  16425. </field>
  16426. <field>
  16427. <name>PR13</name>
  16428. <description>Pending bit 13</description>
  16429. <bitOffset>13</bitOffset>
  16430. <bitWidth>1</bitWidth>
  16431. </field>
  16432. <field>
  16433. <name>PR14</name>
  16434. <description>Pending bit 14</description>
  16435. <bitOffset>14</bitOffset>
  16436. <bitWidth>1</bitWidth>
  16437. </field>
  16438. <field>
  16439. <name>PR15</name>
  16440. <description>Pending bit 15</description>
  16441. <bitOffset>15</bitOffset>
  16442. <bitWidth>1</bitWidth>
  16443. </field>
  16444. <field>
  16445. <name>PR16</name>
  16446. <description>Pending bit 16</description>
  16447. <bitOffset>16</bitOffset>
  16448. <bitWidth>1</bitWidth>
  16449. </field>
  16450. <field>
  16451. <name>PR17</name>
  16452. <description>Pending bit 17</description>
  16453. <bitOffset>17</bitOffset>
  16454. <bitWidth>1</bitWidth>
  16455. </field>
  16456. <field>
  16457. <name>PR19</name>
  16458. <description>Pending bit 19</description>
  16459. <bitOffset>19</bitOffset>
  16460. <bitWidth>1</bitWidth>
  16461. </field>
  16462. </fields>
  16463. </register>
  16464. </registers>
  16465. </peripheral>
  16466. <peripheral>
  16467. <name>ADC</name>
  16468. <description>Analog-to-digital converter</description>
  16469. <groupName>ADC</groupName>
  16470. <baseAddress>0x40012400</baseAddress>
  16471. <addressBlock>
  16472. <offset>0x0</offset>
  16473. <size>0x400</size>
  16474. <usage>registers</usage>
  16475. </addressBlock>
  16476. <interrupt>
  16477. <name>ADC_COMP</name>
  16478. <description>ADC and comparator 1 and 2</description>
  16479. <value>12</value>
  16480. </interrupt>
  16481. <registers>
  16482. <register>
  16483. <name>ISR</name>
  16484. <displayName>ISR</displayName>
  16485. <description>interrupt and status register</description>
  16486. <addressOffset>0x0</addressOffset>
  16487. <size>0x20</size>
  16488. <access>read-write</access>
  16489. <resetValue>0x00000000</resetValue>
  16490. <fields>
  16491. <field>
  16492. <name>ADRDY</name>
  16493. <description>ADC ready</description>
  16494. <bitOffset>0</bitOffset>
  16495. <bitWidth>1</bitWidth>
  16496. </field>
  16497. <field>
  16498. <name>EOSMP</name>
  16499. <description>End of sampling flag</description>
  16500. <bitOffset>1</bitOffset>
  16501. <bitWidth>1</bitWidth>
  16502. </field>
  16503. <field>
  16504. <name>EOC</name>
  16505. <description>End of conversion flag</description>
  16506. <bitOffset>2</bitOffset>
  16507. <bitWidth>1</bitWidth>
  16508. </field>
  16509. <field>
  16510. <name>EOS</name>
  16511. <description>End of sequence flag</description>
  16512. <bitOffset>3</bitOffset>
  16513. <bitWidth>1</bitWidth>
  16514. </field>
  16515. <field>
  16516. <name>OVR</name>
  16517. <description>ADC overrun</description>
  16518. <bitOffset>4</bitOffset>
  16519. <bitWidth>1</bitWidth>
  16520. </field>
  16521. <field>
  16522. <name>AWD</name>
  16523. <description>Analog watchdog flag</description>
  16524. <bitOffset>7</bitOffset>
  16525. <bitWidth>1</bitWidth>
  16526. </field>
  16527. <field>
  16528. <name>EOCAL</name>
  16529. <description>End Of Calibration flag</description>
  16530. <bitOffset>11</bitOffset>
  16531. <bitWidth>1</bitWidth>
  16532. </field>
  16533. </fields>
  16534. </register>
  16535. <register>
  16536. <name>IER</name>
  16537. <displayName>IER</displayName>
  16538. <description>interrupt enable register</description>
  16539. <addressOffset>0x4</addressOffset>
  16540. <size>0x20</size>
  16541. <access>read-write</access>
  16542. <resetValue>0x00000000</resetValue>
  16543. <fields>
  16544. <field>
  16545. <name>ADRDYIE</name>
  16546. <description>ADC ready interrupt enable</description>
  16547. <bitOffset>0</bitOffset>
  16548. <bitWidth>1</bitWidth>
  16549. </field>
  16550. <field>
  16551. <name>EOSMPIE</name>
  16552. <description>End of sampling flag interrupt
  16553. enable</description>
  16554. <bitOffset>1</bitOffset>
  16555. <bitWidth>1</bitWidth>
  16556. </field>
  16557. <field>
  16558. <name>EOCIE</name>
  16559. <description>End of conversion interrupt
  16560. enable</description>
  16561. <bitOffset>2</bitOffset>
  16562. <bitWidth>1</bitWidth>
  16563. </field>
  16564. <field>
  16565. <name>EOSIE</name>
  16566. <description>End of conversion sequence interrupt
  16567. enable</description>
  16568. <bitOffset>3</bitOffset>
  16569. <bitWidth>1</bitWidth>
  16570. </field>
  16571. <field>
  16572. <name>OVRIE</name>
  16573. <description>Overrun interrupt enable</description>
  16574. <bitOffset>4</bitOffset>
  16575. <bitWidth>1</bitWidth>
  16576. </field>
  16577. <field>
  16578. <name>AWDIE</name>
  16579. <description>Analog watchdog interrupt
  16580. enable</description>
  16581. <bitOffset>7</bitOffset>
  16582. <bitWidth>1</bitWidth>
  16583. </field>
  16584. <field>
  16585. <name>EOCALIE</name>
  16586. <description>End of calibration interrupt
  16587. enable</description>
  16588. <bitOffset>11</bitOffset>
  16589. <bitWidth>1</bitWidth>
  16590. </field>
  16591. </fields>
  16592. </register>
  16593. <register>
  16594. <name>CR</name>
  16595. <displayName>CR</displayName>
  16596. <description>control register</description>
  16597. <addressOffset>0x8</addressOffset>
  16598. <size>0x20</size>
  16599. <access>read-write</access>
  16600. <resetValue>0x00000000</resetValue>
  16601. <fields>
  16602. <field>
  16603. <name>ADEN</name>
  16604. <description>ADC enable command</description>
  16605. <bitOffset>0</bitOffset>
  16606. <bitWidth>1</bitWidth>
  16607. </field>
  16608. <field>
  16609. <name>ADDIS</name>
  16610. <description>ADC disable command</description>
  16611. <bitOffset>1</bitOffset>
  16612. <bitWidth>1</bitWidth>
  16613. </field>
  16614. <field>
  16615. <name>ADSTART</name>
  16616. <description>ADC start conversion
  16617. command</description>
  16618. <bitOffset>2</bitOffset>
  16619. <bitWidth>1</bitWidth>
  16620. </field>
  16621. <field>
  16622. <name>ADSTP</name>
  16623. <description>ADC stop conversion
  16624. command</description>
  16625. <bitOffset>4</bitOffset>
  16626. <bitWidth>1</bitWidth>
  16627. </field>
  16628. <field>
  16629. <name>ADVREGEN</name>
  16630. <description>ADC Voltage Regulator
  16631. Enable</description>
  16632. <bitOffset>28</bitOffset>
  16633. <bitWidth>1</bitWidth>
  16634. </field>
  16635. <field>
  16636. <name>ADCAL</name>
  16637. <description>ADC calibration</description>
  16638. <bitOffset>31</bitOffset>
  16639. <bitWidth>1</bitWidth>
  16640. </field>
  16641. </fields>
  16642. </register>
  16643. <register>
  16644. <name>CFGR1</name>
  16645. <displayName>CFGR1</displayName>
  16646. <description>configuration register 1</description>
  16647. <addressOffset>0xC</addressOffset>
  16648. <size>0x20</size>
  16649. <access>read-write</access>
  16650. <resetValue>0x00000000</resetValue>
  16651. <fields>
  16652. <field>
  16653. <name>AWDCH</name>
  16654. <description>Analog watchdog channel
  16655. selection</description>
  16656. <bitOffset>26</bitOffset>
  16657. <bitWidth>5</bitWidth>
  16658. </field>
  16659. <field>
  16660. <name>AWDEN</name>
  16661. <description>Analog watchdog enable</description>
  16662. <bitOffset>23</bitOffset>
  16663. <bitWidth>1</bitWidth>
  16664. </field>
  16665. <field>
  16666. <name>AWDSGL</name>
  16667. <description>Enable the watchdog on a single channel
  16668. or on all channels</description>
  16669. <bitOffset>22</bitOffset>
  16670. <bitWidth>1</bitWidth>
  16671. </field>
  16672. <field>
  16673. <name>DISCEN</name>
  16674. <description>Discontinuous mode</description>
  16675. <bitOffset>16</bitOffset>
  16676. <bitWidth>1</bitWidth>
  16677. </field>
  16678. <field>
  16679. <name>AUTOFF</name>
  16680. <description>Auto-off mode</description>
  16681. <bitOffset>15</bitOffset>
  16682. <bitWidth>1</bitWidth>
  16683. </field>
  16684. <field>
  16685. <name>AUTDLY</name>
  16686. <description>Auto-delayed conversion
  16687. mode</description>
  16688. <bitOffset>14</bitOffset>
  16689. <bitWidth>1</bitWidth>
  16690. </field>
  16691. <field>
  16692. <name>CONT</name>
  16693. <description>Single / continuous conversion
  16694. mode</description>
  16695. <bitOffset>13</bitOffset>
  16696. <bitWidth>1</bitWidth>
  16697. </field>
  16698. <field>
  16699. <name>OVRMOD</name>
  16700. <description>Overrun management mode</description>
  16701. <bitOffset>12</bitOffset>
  16702. <bitWidth>1</bitWidth>
  16703. </field>
  16704. <field>
  16705. <name>EXTEN</name>
  16706. <description>External trigger enable and polarity
  16707. selection</description>
  16708. <bitOffset>10</bitOffset>
  16709. <bitWidth>2</bitWidth>
  16710. </field>
  16711. <field>
  16712. <name>EXTSEL</name>
  16713. <description>External trigger selection</description>
  16714. <bitOffset>6</bitOffset>
  16715. <bitWidth>3</bitWidth>
  16716. </field>
  16717. <field>
  16718. <name>ALIGN</name>
  16719. <description>Data alignment</description>
  16720. <bitOffset>5</bitOffset>
  16721. <bitWidth>1</bitWidth>
  16722. </field>
  16723. <field>
  16724. <name>RES</name>
  16725. <description>Data resolution</description>
  16726. <bitOffset>3</bitOffset>
  16727. <bitWidth>2</bitWidth>
  16728. </field>
  16729. <field>
  16730. <name>SCANDIR</name>
  16731. <description>Scan sequence direction</description>
  16732. <bitOffset>2</bitOffset>
  16733. <bitWidth>1</bitWidth>
  16734. </field>
  16735. <field>
  16736. <name>DMACFG</name>
  16737. <description>Direct memery access
  16738. configuration</description>
  16739. <bitOffset>1</bitOffset>
  16740. <bitWidth>1</bitWidth>
  16741. </field>
  16742. <field>
  16743. <name>DMAEN</name>
  16744. <description>Direct memory access
  16745. enable</description>
  16746. <bitOffset>0</bitOffset>
  16747. <bitWidth>1</bitWidth>
  16748. </field>
  16749. </fields>
  16750. </register>
  16751. <register>
  16752. <name>CFGR2</name>
  16753. <displayName>CFGR2</displayName>
  16754. <description>configuration register 2</description>
  16755. <addressOffset>0x10</addressOffset>
  16756. <size>0x20</size>
  16757. <access>read-write</access>
  16758. <resetValue>0x00000000</resetValue>
  16759. <fields>
  16760. <field>
  16761. <name>OVSE</name>
  16762. <description>Oversampler Enable</description>
  16763. <bitOffset>0</bitOffset>
  16764. <bitWidth>1</bitWidth>
  16765. </field>
  16766. <field>
  16767. <name>OVSR</name>
  16768. <description>Oversampling ratio</description>
  16769. <bitOffset>2</bitOffset>
  16770. <bitWidth>3</bitWidth>
  16771. </field>
  16772. <field>
  16773. <name>OVSS</name>
  16774. <description>Oversampling shift</description>
  16775. <bitOffset>5</bitOffset>
  16776. <bitWidth>4</bitWidth>
  16777. </field>
  16778. <field>
  16779. <name>TOVS</name>
  16780. <description>Triggered Oversampling</description>
  16781. <bitOffset>9</bitOffset>
  16782. <bitWidth>1</bitWidth>
  16783. </field>
  16784. <field>
  16785. <name>CKMODE</name>
  16786. <description>ADC clock mode</description>
  16787. <bitOffset>30</bitOffset>
  16788. <bitWidth>2</bitWidth>
  16789. </field>
  16790. </fields>
  16791. </register>
  16792. <register>
  16793. <name>SMPR</name>
  16794. <displayName>SMPR</displayName>
  16795. <description>sampling time register</description>
  16796. <addressOffset>0x14</addressOffset>
  16797. <size>0x20</size>
  16798. <access>read-write</access>
  16799. <resetValue>0x00000000</resetValue>
  16800. <fields>
  16801. <field>
  16802. <name>SMPR</name>
  16803. <description>Sampling time selection</description>
  16804. <bitOffset>0</bitOffset>
  16805. <bitWidth>3</bitWidth>
  16806. </field>
  16807. </fields>
  16808. </register>
  16809. <register>
  16810. <name>TR</name>
  16811. <displayName>TR</displayName>
  16812. <description>watchdog threshold register</description>
  16813. <addressOffset>0x20</addressOffset>
  16814. <size>0x20</size>
  16815. <access>read-write</access>
  16816. <resetValue>0x0FFF0000</resetValue>
  16817. <fields>
  16818. <field>
  16819. <name>HT</name>
  16820. <description>Analog watchdog higher
  16821. threshold</description>
  16822. <bitOffset>16</bitOffset>
  16823. <bitWidth>12</bitWidth>
  16824. </field>
  16825. <field>
  16826. <name>LT</name>
  16827. <description>Analog watchdog lower
  16828. threshold</description>
  16829. <bitOffset>0</bitOffset>
  16830. <bitWidth>12</bitWidth>
  16831. </field>
  16832. </fields>
  16833. </register>
  16834. <register>
  16835. <name>CHSELR</name>
  16836. <displayName>CHSELR</displayName>
  16837. <description>channel selection register</description>
  16838. <addressOffset>0x28</addressOffset>
  16839. <size>0x20</size>
  16840. <access>read-write</access>
  16841. <resetValue>0x00000000</resetValue>
  16842. <fields>
  16843. <field>
  16844. <name>CHSEL18</name>
  16845. <description>Channel-x selection</description>
  16846. <bitOffset>18</bitOffset>
  16847. <bitWidth>1</bitWidth>
  16848. </field>
  16849. <field>
  16850. <name>CHSEL17</name>
  16851. <description>Channel-x selection</description>
  16852. <bitOffset>17</bitOffset>
  16853. <bitWidth>1</bitWidth>
  16854. </field>
  16855. <field>
  16856. <name>CHSEL16</name>
  16857. <description>Channel-x selection</description>
  16858. <bitOffset>16</bitOffset>
  16859. <bitWidth>1</bitWidth>
  16860. </field>
  16861. <field>
  16862. <name>CHSEL15</name>
  16863. <description>Channel-x selection</description>
  16864. <bitOffset>15</bitOffset>
  16865. <bitWidth>1</bitWidth>
  16866. </field>
  16867. <field>
  16868. <name>CHSEL14</name>
  16869. <description>Channel-x selection</description>
  16870. <bitOffset>14</bitOffset>
  16871. <bitWidth>1</bitWidth>
  16872. </field>
  16873. <field>
  16874. <name>CHSEL13</name>
  16875. <description>Channel-x selection</description>
  16876. <bitOffset>13</bitOffset>
  16877. <bitWidth>1</bitWidth>
  16878. </field>
  16879. <field>
  16880. <name>CHSEL12</name>
  16881. <description>Channel-x selection</description>
  16882. <bitOffset>12</bitOffset>
  16883. <bitWidth>1</bitWidth>
  16884. </field>
  16885. <field>
  16886. <name>CHSEL11</name>
  16887. <description>Channel-x selection</description>
  16888. <bitOffset>11</bitOffset>
  16889. <bitWidth>1</bitWidth>
  16890. </field>
  16891. <field>
  16892. <name>CHSEL10</name>
  16893. <description>Channel-x selection</description>
  16894. <bitOffset>10</bitOffset>
  16895. <bitWidth>1</bitWidth>
  16896. </field>
  16897. <field>
  16898. <name>CHSEL9</name>
  16899. <description>Channel-x selection</description>
  16900. <bitOffset>9</bitOffset>
  16901. <bitWidth>1</bitWidth>
  16902. </field>
  16903. <field>
  16904. <name>CHSEL8</name>
  16905. <description>Channel-x selection</description>
  16906. <bitOffset>8</bitOffset>
  16907. <bitWidth>1</bitWidth>
  16908. </field>
  16909. <field>
  16910. <name>CHSEL7</name>
  16911. <description>Channel-x selection</description>
  16912. <bitOffset>7</bitOffset>
  16913. <bitWidth>1</bitWidth>
  16914. </field>
  16915. <field>
  16916. <name>CHSEL6</name>
  16917. <description>Channel-x selection</description>
  16918. <bitOffset>6</bitOffset>
  16919. <bitWidth>1</bitWidth>
  16920. </field>
  16921. <field>
  16922. <name>CHSEL5</name>
  16923. <description>Channel-x selection</description>
  16924. <bitOffset>5</bitOffset>
  16925. <bitWidth>1</bitWidth>
  16926. </field>
  16927. <field>
  16928. <name>CHSEL4</name>
  16929. <description>Channel-x selection</description>
  16930. <bitOffset>4</bitOffset>
  16931. <bitWidth>1</bitWidth>
  16932. </field>
  16933. <field>
  16934. <name>CHSEL3</name>
  16935. <description>Channel-x selection</description>
  16936. <bitOffset>3</bitOffset>
  16937. <bitWidth>1</bitWidth>
  16938. </field>
  16939. <field>
  16940. <name>CHSEL2</name>
  16941. <description>Channel-x selection</description>
  16942. <bitOffset>2</bitOffset>
  16943. <bitWidth>1</bitWidth>
  16944. </field>
  16945. <field>
  16946. <name>CHSEL1</name>
  16947. <description>Channel-x selection</description>
  16948. <bitOffset>1</bitOffset>
  16949. <bitWidth>1</bitWidth>
  16950. </field>
  16951. <field>
  16952. <name>CHSEL0</name>
  16953. <description>Channel-x selection</description>
  16954. <bitOffset>0</bitOffset>
  16955. <bitWidth>1</bitWidth>
  16956. </field>
  16957. </fields>
  16958. </register>
  16959. <register>
  16960. <name>DR</name>
  16961. <displayName>DR</displayName>
  16962. <description>data register</description>
  16963. <addressOffset>0x40</addressOffset>
  16964. <size>0x20</size>
  16965. <access>read-only</access>
  16966. <resetValue>0x00000000</resetValue>
  16967. <fields>
  16968. <field>
  16969. <name>DATA</name>
  16970. <description>Converted data</description>
  16971. <bitOffset>0</bitOffset>
  16972. <bitWidth>16</bitWidth>
  16973. </field>
  16974. </fields>
  16975. </register>
  16976. <register>
  16977. <name>CALFACT</name>
  16978. <displayName>CALFACT</displayName>
  16979. <description>ADC Calibration factor</description>
  16980. <addressOffset>0xB4</addressOffset>
  16981. <size>0x20</size>
  16982. <access>read-write</access>
  16983. <resetValue>0x00000000</resetValue>
  16984. <fields>
  16985. <field>
  16986. <name>CALFACT</name>
  16987. <description>Calibration factor</description>
  16988. <bitOffset>0</bitOffset>
  16989. <bitWidth>7</bitWidth>
  16990. </field>
  16991. </fields>
  16992. </register>
  16993. <register>
  16994. <name>CCR</name>
  16995. <displayName>CCR</displayName>
  16996. <description>ADC common configuration
  16997. register</description>
  16998. <addressOffset>0x308</addressOffset>
  16999. <size>0x20</size>
  17000. <access>read-write</access>
  17001. <resetValue>0x00000000</resetValue>
  17002. <fields>
  17003. <field>
  17004. <name>PRESC</name>
  17005. <description>ADC prescaler</description>
  17006. <bitOffset>18</bitOffset>
  17007. <bitWidth>4</bitWidth>
  17008. </field>
  17009. <field>
  17010. <name>VREFEN</name>
  17011. <description>VREFINT enable</description>
  17012. <bitOffset>22</bitOffset>
  17013. <bitWidth>1</bitWidth>
  17014. </field>
  17015. <field>
  17016. <name>TSEN</name>
  17017. <description>Temperature sensor enable</description>
  17018. <bitOffset>23</bitOffset>
  17019. <bitWidth>1</bitWidth>
  17020. </field>
  17021. <field>
  17022. <name>VLCDEN</name>
  17023. <description>VLCD enable</description>
  17024. <bitOffset>24</bitOffset>
  17025. <bitWidth>1</bitWidth>
  17026. </field>
  17027. <field>
  17028. <name>LFMEN</name>
  17029. <description>Low Frequency Mode enable</description>
  17030. <bitOffset>25</bitOffset>
  17031. <bitWidth>1</bitWidth>
  17032. </field>
  17033. </fields>
  17034. </register>
  17035. </registers>
  17036. </peripheral>
  17037. <peripheral>
  17038. <name>DBGMCU</name>
  17039. <description>Debug support</description>
  17040. <groupName>DBGMCU</groupName>
  17041. <baseAddress>0x40015800</baseAddress>
  17042. <addressBlock>
  17043. <offset>0x0</offset>
  17044. <size>0x400</size>
  17045. <usage>registers</usage>
  17046. </addressBlock>
  17047. <registers>
  17048. <register>
  17049. <name>IDCODE</name>
  17050. <displayName>IDCODE</displayName>
  17051. <description>MCU Device ID Code Register</description>
  17052. <addressOffset>0x0</addressOffset>
  17053. <size>0x20</size>
  17054. <access>read-only</access>
  17055. <resetValue>0x0</resetValue>
  17056. <fields>
  17057. <field>
  17058. <name>DEV_ID</name>
  17059. <description>Device Identifier</description>
  17060. <bitOffset>0</bitOffset>
  17061. <bitWidth>12</bitWidth>
  17062. </field>
  17063. <field>
  17064. <name>REV_ID</name>
  17065. <description>Revision Identifier</description>
  17066. <bitOffset>16</bitOffset>
  17067. <bitWidth>16</bitWidth>
  17068. </field>
  17069. </fields>
  17070. </register>
  17071. <register>
  17072. <name>CR</name>
  17073. <displayName>CR</displayName>
  17074. <description>Debug MCU Configuration
  17075. Register</description>
  17076. <addressOffset>0x4</addressOffset>
  17077. <size>0x20</size>
  17078. <access>read-write</access>
  17079. <resetValue>0x0</resetValue>
  17080. <fields>
  17081. <field>
  17082. <name>DBG_STOP</name>
  17083. <description>Debug Stop Mode</description>
  17084. <bitOffset>1</bitOffset>
  17085. <bitWidth>1</bitWidth>
  17086. </field>
  17087. <field>
  17088. <name>DBG_STANDBY</name>
  17089. <description>Debug Standby Mode</description>
  17090. <bitOffset>2</bitOffset>
  17091. <bitWidth>1</bitWidth>
  17092. </field>
  17093. <field>
  17094. <name>DBG_SLEEP</name>
  17095. <description>Debug Sleep Mode</description>
  17096. <bitOffset>0</bitOffset>
  17097. <bitWidth>1</bitWidth>
  17098. </field>
  17099. </fields>
  17100. </register>
  17101. <register>
  17102. <name>APB1_FZ</name>
  17103. <displayName>APB1_FZ</displayName>
  17104. <description>APB Low Freeze Register</description>
  17105. <addressOffset>0x8</addressOffset>
  17106. <size>0x20</size>
  17107. <access>read-write</access>
  17108. <resetValue>0x0</resetValue>
  17109. <fields>
  17110. <field>
  17111. <name>DBG_TIMER2_STOP</name>
  17112. <description>Debug Timer 2 stopped when Core is
  17113. halted</description>
  17114. <bitOffset>0</bitOffset>
  17115. <bitWidth>1</bitWidth>
  17116. </field>
  17117. <field>
  17118. <name>DBG_TIMER6_STOP</name>
  17119. <description>Debug Timer 6 stopped when Core is
  17120. halted</description>
  17121. <bitOffset>4</bitOffset>
  17122. <bitWidth>1</bitWidth>
  17123. </field>
  17124. <field>
  17125. <name>DBG_RTC_STOP</name>
  17126. <description>Debug RTC stopped when Core is
  17127. halted</description>
  17128. <bitOffset>10</bitOffset>
  17129. <bitWidth>1</bitWidth>
  17130. </field>
  17131. <field>
  17132. <name>DBG_WWDG_STOP</name>
  17133. <description>Debug Window Wachdog stopped when Core
  17134. is halted</description>
  17135. <bitOffset>11</bitOffset>
  17136. <bitWidth>1</bitWidth>
  17137. </field>
  17138. <field>
  17139. <name>DBG_IWDG_STOP</name>
  17140. <description>Debug Independent Wachdog stopped when
  17141. Core is halted</description>
  17142. <bitOffset>12</bitOffset>
  17143. <bitWidth>1</bitWidth>
  17144. </field>
  17145. <field>
  17146. <name>DBG_I2C1_STOP</name>
  17147. <description>I2C1 SMBUS timeout mode stopped when
  17148. core is halted</description>
  17149. <bitOffset>21</bitOffset>
  17150. <bitWidth>1</bitWidth>
  17151. </field>
  17152. <field>
  17153. <name>DBG_I2C2_STOP</name>
  17154. <description>I2C2 SMBUS timeout mode stopped when
  17155. core is halted</description>
  17156. <bitOffset>22</bitOffset>
  17157. <bitWidth>1</bitWidth>
  17158. </field>
  17159. <field>
  17160. <name>DBG_I2C3_STOP</name>
  17161. <description>I2C3 SMBUS timeout mode stopped when
  17162. core is halted</description>
  17163. <bitOffset>30</bitOffset>
  17164. <bitWidth>1</bitWidth>
  17165. </field>
  17166. <field>
  17167. <name>DBG_LPTIMER_STOP</name>
  17168. <description>LPTIM1 counter stopped when core is
  17169. halted</description>
  17170. <bitOffset>31</bitOffset>
  17171. <bitWidth>1</bitWidth>
  17172. </field>
  17173. </fields>
  17174. </register>
  17175. <register>
  17176. <name>APB2_FZ</name>
  17177. <displayName>APB2_FZ</displayName>
  17178. <description>APB High Freeze Register</description>
  17179. <addressOffset>0xC</addressOffset>
  17180. <size>0x20</size>
  17181. <access>read-write</access>
  17182. <resetValue>0x0</resetValue>
  17183. <fields>
  17184. <field>
  17185. <name>DBG_TIMER21_STOP</name>
  17186. <description>Debug Timer 21 stopped when Core is
  17187. halted</description>
  17188. <bitOffset>2</bitOffset>
  17189. <bitWidth>1</bitWidth>
  17190. </field>
  17191. <field>
  17192. <name>DBG_TIMER22_STOP</name>
  17193. <description>Debug Timer 22 stopped when Core is
  17194. halted</description>
  17195. <bitOffset>5</bitOffset>
  17196. <bitWidth>1</bitWidth>
  17197. </field>
  17198. </fields>
  17199. </register>
  17200. </registers>
  17201. </peripheral>
  17202. <peripheral>
  17203. <name>TIM2</name>
  17204. <description>General-purpose-timers</description>
  17205. <groupName>TIM</groupName>
  17206. <baseAddress>0x40000000</baseAddress>
  17207. <addressBlock>
  17208. <offset>0x0</offset>
  17209. <size>0x400</size>
  17210. <usage>registers</usage>
  17211. </addressBlock>
  17212. <interrupt>
  17213. <name>TIM2</name>
  17214. <description>TIM2 global interrupt</description>
  17215. <value>15</value>
  17216. </interrupt>
  17217. <registers>
  17218. <register>
  17219. <name>CR1</name>
  17220. <displayName>CR1</displayName>
  17221. <description>control register 1</description>
  17222. <addressOffset>0x0</addressOffset>
  17223. <size>0x20</size>
  17224. <access>read-write</access>
  17225. <resetValue>0x0000</resetValue>
  17226. <fields>
  17227. <field>
  17228. <name>CKD</name>
  17229. <description>Clock division</description>
  17230. <bitOffset>8</bitOffset>
  17231. <bitWidth>2</bitWidth>
  17232. </field>
  17233. <field>
  17234. <name>ARPE</name>
  17235. <description>Auto-reload preload enable</description>
  17236. <bitOffset>7</bitOffset>
  17237. <bitWidth>1</bitWidth>
  17238. </field>
  17239. <field>
  17240. <name>CMS</name>
  17241. <description>Center-aligned mode
  17242. selection</description>
  17243. <bitOffset>5</bitOffset>
  17244. <bitWidth>2</bitWidth>
  17245. </field>
  17246. <field>
  17247. <name>DIR</name>
  17248. <description>Direction</description>
  17249. <bitOffset>4</bitOffset>
  17250. <bitWidth>1</bitWidth>
  17251. </field>
  17252. <field>
  17253. <name>OPM</name>
  17254. <description>One-pulse mode</description>
  17255. <bitOffset>3</bitOffset>
  17256. <bitWidth>1</bitWidth>
  17257. </field>
  17258. <field>
  17259. <name>URS</name>
  17260. <description>Update request source</description>
  17261. <bitOffset>2</bitOffset>
  17262. <bitWidth>1</bitWidth>
  17263. </field>
  17264. <field>
  17265. <name>UDIS</name>
  17266. <description>Update disable</description>
  17267. <bitOffset>1</bitOffset>
  17268. <bitWidth>1</bitWidth>
  17269. </field>
  17270. <field>
  17271. <name>CEN</name>
  17272. <description>Counter enable</description>
  17273. <bitOffset>0</bitOffset>
  17274. <bitWidth>1</bitWidth>
  17275. </field>
  17276. </fields>
  17277. </register>
  17278. <register>
  17279. <name>CR2</name>
  17280. <displayName>CR2</displayName>
  17281. <description>control register 2</description>
  17282. <addressOffset>0x4</addressOffset>
  17283. <size>0x20</size>
  17284. <access>read-write</access>
  17285. <resetValue>0x0000</resetValue>
  17286. <fields>
  17287. <field>
  17288. <name>TI1S</name>
  17289. <description>TI1 selection</description>
  17290. <bitOffset>7</bitOffset>
  17291. <bitWidth>1</bitWidth>
  17292. </field>
  17293. <field>
  17294. <name>MMS</name>
  17295. <description>Master mode selection</description>
  17296. <bitOffset>4</bitOffset>
  17297. <bitWidth>3</bitWidth>
  17298. </field>
  17299. <field>
  17300. <name>CCDS</name>
  17301. <description>Capture/compare DMA
  17302. selection</description>
  17303. <bitOffset>3</bitOffset>
  17304. <bitWidth>1</bitWidth>
  17305. </field>
  17306. </fields>
  17307. </register>
  17308. <register>
  17309. <name>SMCR</name>
  17310. <displayName>SMCR</displayName>
  17311. <description>slave mode control register</description>
  17312. <addressOffset>0x8</addressOffset>
  17313. <size>0x20</size>
  17314. <access>read-write</access>
  17315. <resetValue>0x0000</resetValue>
  17316. <fields>
  17317. <field>
  17318. <name>ETP</name>
  17319. <description>External trigger polarity</description>
  17320. <bitOffset>15</bitOffset>
  17321. <bitWidth>1</bitWidth>
  17322. </field>
  17323. <field>
  17324. <name>ECE</name>
  17325. <description>External clock enable</description>
  17326. <bitOffset>14</bitOffset>
  17327. <bitWidth>1</bitWidth>
  17328. </field>
  17329. <field>
  17330. <name>ETPS</name>
  17331. <description>External trigger prescaler</description>
  17332. <bitOffset>12</bitOffset>
  17333. <bitWidth>2</bitWidth>
  17334. </field>
  17335. <field>
  17336. <name>ETF</name>
  17337. <description>External trigger filter</description>
  17338. <bitOffset>8</bitOffset>
  17339. <bitWidth>4</bitWidth>
  17340. </field>
  17341. <field>
  17342. <name>MSM</name>
  17343. <description>Master/Slave mode</description>
  17344. <bitOffset>7</bitOffset>
  17345. <bitWidth>1</bitWidth>
  17346. </field>
  17347. <field>
  17348. <name>TS</name>
  17349. <description>Trigger selection</description>
  17350. <bitOffset>4</bitOffset>
  17351. <bitWidth>3</bitWidth>
  17352. </field>
  17353. <field>
  17354. <name>SMS</name>
  17355. <description>Slave mode selection</description>
  17356. <bitOffset>0</bitOffset>
  17357. <bitWidth>3</bitWidth>
  17358. </field>
  17359. </fields>
  17360. </register>
  17361. <register>
  17362. <name>DIER</name>
  17363. <displayName>DIER</displayName>
  17364. <description>DMA/Interrupt enable register</description>
  17365. <addressOffset>0xC</addressOffset>
  17366. <size>0x20</size>
  17367. <access>read-write</access>
  17368. <resetValue>0x0000</resetValue>
  17369. <fields>
  17370. <field>
  17371. <name>TDE</name>
  17372. <description>Trigger DMA request enable</description>
  17373. <bitOffset>14</bitOffset>
  17374. <bitWidth>1</bitWidth>
  17375. </field>
  17376. <field>
  17377. <name>COMDE</name>
  17378. <description>Reserved</description>
  17379. <bitOffset>13</bitOffset>
  17380. <bitWidth>1</bitWidth>
  17381. </field>
  17382. <field>
  17383. <name>CC4DE</name>
  17384. <description>Capture/Compare 4 DMA request
  17385. enable</description>
  17386. <bitOffset>12</bitOffset>
  17387. <bitWidth>1</bitWidth>
  17388. </field>
  17389. <field>
  17390. <name>CC3DE</name>
  17391. <description>Capture/Compare 3 DMA request
  17392. enable</description>
  17393. <bitOffset>11</bitOffset>
  17394. <bitWidth>1</bitWidth>
  17395. </field>
  17396. <field>
  17397. <name>CC2DE</name>
  17398. <description>Capture/Compare 2 DMA request
  17399. enable</description>
  17400. <bitOffset>10</bitOffset>
  17401. <bitWidth>1</bitWidth>
  17402. </field>
  17403. <field>
  17404. <name>CC1DE</name>
  17405. <description>Capture/Compare 1 DMA request
  17406. enable</description>
  17407. <bitOffset>9</bitOffset>
  17408. <bitWidth>1</bitWidth>
  17409. </field>
  17410. <field>
  17411. <name>UDE</name>
  17412. <description>Update DMA request enable</description>
  17413. <bitOffset>8</bitOffset>
  17414. <bitWidth>1</bitWidth>
  17415. </field>
  17416. <field>
  17417. <name>TIE</name>
  17418. <description>Trigger interrupt enable</description>
  17419. <bitOffset>6</bitOffset>
  17420. <bitWidth>1</bitWidth>
  17421. </field>
  17422. <field>
  17423. <name>CC4IE</name>
  17424. <description>Capture/Compare 4 interrupt
  17425. enable</description>
  17426. <bitOffset>4</bitOffset>
  17427. <bitWidth>1</bitWidth>
  17428. </field>
  17429. <field>
  17430. <name>CC3IE</name>
  17431. <description>Capture/Compare 3 interrupt
  17432. enable</description>
  17433. <bitOffset>3</bitOffset>
  17434. <bitWidth>1</bitWidth>
  17435. </field>
  17436. <field>
  17437. <name>CC2IE</name>
  17438. <description>Capture/Compare 2 interrupt
  17439. enable</description>
  17440. <bitOffset>2</bitOffset>
  17441. <bitWidth>1</bitWidth>
  17442. </field>
  17443. <field>
  17444. <name>CC1IE</name>
  17445. <description>Capture/Compare 1 interrupt
  17446. enable</description>
  17447. <bitOffset>1</bitOffset>
  17448. <bitWidth>1</bitWidth>
  17449. </field>
  17450. <field>
  17451. <name>UIE</name>
  17452. <description>Update interrupt enable</description>
  17453. <bitOffset>0</bitOffset>
  17454. <bitWidth>1</bitWidth>
  17455. </field>
  17456. </fields>
  17457. </register>
  17458. <register>
  17459. <name>SR</name>
  17460. <displayName>SR</displayName>
  17461. <description>status register</description>
  17462. <addressOffset>0x10</addressOffset>
  17463. <size>0x20</size>
  17464. <access>read-write</access>
  17465. <resetValue>0x0000</resetValue>
  17466. <fields>
  17467. <field>
  17468. <name>CC4OF</name>
  17469. <description>Capture/Compare 4 overcapture
  17470. flag</description>
  17471. <bitOffset>12</bitOffset>
  17472. <bitWidth>1</bitWidth>
  17473. </field>
  17474. <field>
  17475. <name>CC3OF</name>
  17476. <description>Capture/Compare 3 overcapture
  17477. flag</description>
  17478. <bitOffset>11</bitOffset>
  17479. <bitWidth>1</bitWidth>
  17480. </field>
  17481. <field>
  17482. <name>CC2OF</name>
  17483. <description>Capture/compare 2 overcapture
  17484. flag</description>
  17485. <bitOffset>10</bitOffset>
  17486. <bitWidth>1</bitWidth>
  17487. </field>
  17488. <field>
  17489. <name>CC1OF</name>
  17490. <description>Capture/Compare 1 overcapture
  17491. flag</description>
  17492. <bitOffset>9</bitOffset>
  17493. <bitWidth>1</bitWidth>
  17494. </field>
  17495. <field>
  17496. <name>TIF</name>
  17497. <description>Trigger interrupt flag</description>
  17498. <bitOffset>6</bitOffset>
  17499. <bitWidth>1</bitWidth>
  17500. </field>
  17501. <field>
  17502. <name>CC4IF</name>
  17503. <description>Capture/Compare 4 interrupt
  17504. flag</description>
  17505. <bitOffset>4</bitOffset>
  17506. <bitWidth>1</bitWidth>
  17507. </field>
  17508. <field>
  17509. <name>CC3IF</name>
  17510. <description>Capture/Compare 3 interrupt
  17511. flag</description>
  17512. <bitOffset>3</bitOffset>
  17513. <bitWidth>1</bitWidth>
  17514. </field>
  17515. <field>
  17516. <name>CC2IF</name>
  17517. <description>Capture/Compare 2 interrupt
  17518. flag</description>
  17519. <bitOffset>2</bitOffset>
  17520. <bitWidth>1</bitWidth>
  17521. </field>
  17522. <field>
  17523. <name>CC1IF</name>
  17524. <description>Capture/compare 1 interrupt
  17525. flag</description>
  17526. <bitOffset>1</bitOffset>
  17527. <bitWidth>1</bitWidth>
  17528. </field>
  17529. <field>
  17530. <name>UIF</name>
  17531. <description>Update interrupt flag</description>
  17532. <bitOffset>0</bitOffset>
  17533. <bitWidth>1</bitWidth>
  17534. </field>
  17535. </fields>
  17536. </register>
  17537. <register>
  17538. <name>EGR</name>
  17539. <displayName>EGR</displayName>
  17540. <description>event generation register</description>
  17541. <addressOffset>0x14</addressOffset>
  17542. <size>0x20</size>
  17543. <access>write-only</access>
  17544. <resetValue>0x0000</resetValue>
  17545. <fields>
  17546. <field>
  17547. <name>TG</name>
  17548. <description>Trigger generation</description>
  17549. <bitOffset>6</bitOffset>
  17550. <bitWidth>1</bitWidth>
  17551. </field>
  17552. <field>
  17553. <name>CC4G</name>
  17554. <description>Capture/compare 4
  17555. generation</description>
  17556. <bitOffset>4</bitOffset>
  17557. <bitWidth>1</bitWidth>
  17558. </field>
  17559. <field>
  17560. <name>CC3G</name>
  17561. <description>Capture/compare 3
  17562. generation</description>
  17563. <bitOffset>3</bitOffset>
  17564. <bitWidth>1</bitWidth>
  17565. </field>
  17566. <field>
  17567. <name>CC2G</name>
  17568. <description>Capture/compare 2
  17569. generation</description>
  17570. <bitOffset>2</bitOffset>
  17571. <bitWidth>1</bitWidth>
  17572. </field>
  17573. <field>
  17574. <name>CC1G</name>
  17575. <description>Capture/compare 1
  17576. generation</description>
  17577. <bitOffset>1</bitOffset>
  17578. <bitWidth>1</bitWidth>
  17579. </field>
  17580. <field>
  17581. <name>UG</name>
  17582. <description>Update generation</description>
  17583. <bitOffset>0</bitOffset>
  17584. <bitWidth>1</bitWidth>
  17585. </field>
  17586. </fields>
  17587. </register>
  17588. <register>
  17589. <name>CCMR1_Output</name>
  17590. <displayName>CCMR1_Output</displayName>
  17591. <description>capture/compare mode register 1 (output
  17592. mode)</description>
  17593. <addressOffset>0x18</addressOffset>
  17594. <size>0x20</size>
  17595. <access>read-write</access>
  17596. <resetValue>0x00000000</resetValue>
  17597. <fields>
  17598. <field>
  17599. <name>OC2CE</name>
  17600. <description>Output compare 2 clear
  17601. enable</description>
  17602. <bitOffset>15</bitOffset>
  17603. <bitWidth>1</bitWidth>
  17604. </field>
  17605. <field>
  17606. <name>OC2M</name>
  17607. <description>Output compare 2 mode</description>
  17608. <bitOffset>12</bitOffset>
  17609. <bitWidth>3</bitWidth>
  17610. </field>
  17611. <field>
  17612. <name>OC2PE</name>
  17613. <description>Output compare 2 preload
  17614. enable</description>
  17615. <bitOffset>11</bitOffset>
  17616. <bitWidth>1</bitWidth>
  17617. </field>
  17618. <field>
  17619. <name>OC2FE</name>
  17620. <description>Output compare 2 fast
  17621. enable</description>
  17622. <bitOffset>10</bitOffset>
  17623. <bitWidth>1</bitWidth>
  17624. </field>
  17625. <field>
  17626. <name>CC2S</name>
  17627. <description>Capture/Compare 2
  17628. selection</description>
  17629. <bitOffset>8</bitOffset>
  17630. <bitWidth>2</bitWidth>
  17631. </field>
  17632. <field>
  17633. <name>OC1CE</name>
  17634. <description>Output compare 1 clear
  17635. enable</description>
  17636. <bitOffset>7</bitOffset>
  17637. <bitWidth>1</bitWidth>
  17638. </field>
  17639. <field>
  17640. <name>OC1M</name>
  17641. <description>Output compare 1 mode</description>
  17642. <bitOffset>4</bitOffset>
  17643. <bitWidth>3</bitWidth>
  17644. </field>
  17645. <field>
  17646. <name>OC1PE</name>
  17647. <description>Output compare 1 preload
  17648. enable</description>
  17649. <bitOffset>3</bitOffset>
  17650. <bitWidth>1</bitWidth>
  17651. </field>
  17652. <field>
  17653. <name>OC1FE</name>
  17654. <description>Output compare 1 fast
  17655. enable</description>
  17656. <bitOffset>2</bitOffset>
  17657. <bitWidth>1</bitWidth>
  17658. </field>
  17659. <field>
  17660. <name>CC1S</name>
  17661. <description>Capture/Compare 1
  17662. selection</description>
  17663. <bitOffset>0</bitOffset>
  17664. <bitWidth>2</bitWidth>
  17665. </field>
  17666. </fields>
  17667. </register>
  17668. <register>
  17669. <name>CCMR1_Input</name>
  17670. <displayName>CCMR1_Input</displayName>
  17671. <description>capture/compare mode register 1 (input
  17672. mode)</description>
  17673. <alternateRegister>CCMR1_Output</alternateRegister>
  17674. <addressOffset>0x18</addressOffset>
  17675. <size>0x20</size>
  17676. <access>read-write</access>
  17677. <resetValue>0x00000000</resetValue>
  17678. <fields>
  17679. <field>
  17680. <name>IC2F</name>
  17681. <description>Input capture 2 filter</description>
  17682. <bitOffset>12</bitOffset>
  17683. <bitWidth>4</bitWidth>
  17684. </field>
  17685. <field>
  17686. <name>IC2PSC</name>
  17687. <description>Input capture 2 prescaler</description>
  17688. <bitOffset>10</bitOffset>
  17689. <bitWidth>2</bitWidth>
  17690. </field>
  17691. <field>
  17692. <name>CC2S</name>
  17693. <description>Capture/compare 2
  17694. selection</description>
  17695. <bitOffset>8</bitOffset>
  17696. <bitWidth>2</bitWidth>
  17697. </field>
  17698. <field>
  17699. <name>IC1F</name>
  17700. <description>Input capture 1 filter</description>
  17701. <bitOffset>4</bitOffset>
  17702. <bitWidth>4</bitWidth>
  17703. </field>
  17704. <field>
  17705. <name>IC1PSC</name>
  17706. <description>Input capture 1 prescaler</description>
  17707. <bitOffset>2</bitOffset>
  17708. <bitWidth>2</bitWidth>
  17709. </field>
  17710. <field>
  17711. <name>CC1S</name>
  17712. <description>Capture/Compare 1
  17713. selection</description>
  17714. <bitOffset>0</bitOffset>
  17715. <bitWidth>2</bitWidth>
  17716. </field>
  17717. </fields>
  17718. </register>
  17719. <register>
  17720. <name>CCMR2_Output</name>
  17721. <displayName>CCMR2_Output</displayName>
  17722. <description>capture/compare mode register 2 (output
  17723. mode)</description>
  17724. <addressOffset>0x1C</addressOffset>
  17725. <size>0x20</size>
  17726. <access>read-write</access>
  17727. <resetValue>0x00000000</resetValue>
  17728. <fields>
  17729. <field>
  17730. <name>OC4CE</name>
  17731. <description>Output compare 4 clear
  17732. enable</description>
  17733. <bitOffset>15</bitOffset>
  17734. <bitWidth>1</bitWidth>
  17735. </field>
  17736. <field>
  17737. <name>OC4M</name>
  17738. <description>Output compare 4 mode</description>
  17739. <bitOffset>12</bitOffset>
  17740. <bitWidth>3</bitWidth>
  17741. </field>
  17742. <field>
  17743. <name>OC4PE</name>
  17744. <description>Output compare 4 preload
  17745. enable</description>
  17746. <bitOffset>11</bitOffset>
  17747. <bitWidth>1</bitWidth>
  17748. </field>
  17749. <field>
  17750. <name>OC4FE</name>
  17751. <description>Output compare 4 fast
  17752. enable</description>
  17753. <bitOffset>10</bitOffset>
  17754. <bitWidth>1</bitWidth>
  17755. </field>
  17756. <field>
  17757. <name>CC4S</name>
  17758. <description>Capture/Compare 4
  17759. selection</description>
  17760. <bitOffset>8</bitOffset>
  17761. <bitWidth>2</bitWidth>
  17762. </field>
  17763. <field>
  17764. <name>OC3CE</name>
  17765. <description>Output compare 3 clear
  17766. enable</description>
  17767. <bitOffset>7</bitOffset>
  17768. <bitWidth>1</bitWidth>
  17769. </field>
  17770. <field>
  17771. <name>OC3M</name>
  17772. <description>Output compare 3 mode</description>
  17773. <bitOffset>4</bitOffset>
  17774. <bitWidth>3</bitWidth>
  17775. </field>
  17776. <field>
  17777. <name>OC3PE</name>
  17778. <description>Output compare 3 preload
  17779. enable</description>
  17780. <bitOffset>3</bitOffset>
  17781. <bitWidth>1</bitWidth>
  17782. </field>
  17783. <field>
  17784. <name>OC3FE</name>
  17785. <description>Output compare 3 fast
  17786. enable</description>
  17787. <bitOffset>2</bitOffset>
  17788. <bitWidth>1</bitWidth>
  17789. </field>
  17790. <field>
  17791. <name>CC3S</name>
  17792. <description>Capture/Compare 3
  17793. selection</description>
  17794. <bitOffset>0</bitOffset>
  17795. <bitWidth>2</bitWidth>
  17796. </field>
  17797. </fields>
  17798. </register>
  17799. <register>
  17800. <name>CCMR2_Input</name>
  17801. <displayName>CCMR2_Input</displayName>
  17802. <description>capture/compare mode register 2 (input
  17803. mode)</description>
  17804. <alternateRegister>CCMR2_Output</alternateRegister>
  17805. <addressOffset>0x1C</addressOffset>
  17806. <size>0x20</size>
  17807. <access>read-write</access>
  17808. <resetValue>0x00000000</resetValue>
  17809. <fields>
  17810. <field>
  17811. <name>IC4F</name>
  17812. <description>Input capture 4 filter</description>
  17813. <bitOffset>12</bitOffset>
  17814. <bitWidth>4</bitWidth>
  17815. </field>
  17816. <field>
  17817. <name>IC4PSC</name>
  17818. <description>Input capture 4 prescaler</description>
  17819. <bitOffset>10</bitOffset>
  17820. <bitWidth>2</bitWidth>
  17821. </field>
  17822. <field>
  17823. <name>CC4S</name>
  17824. <description>Capture/Compare 4
  17825. selection</description>
  17826. <bitOffset>8</bitOffset>
  17827. <bitWidth>2</bitWidth>
  17828. </field>
  17829. <field>
  17830. <name>IC3F</name>
  17831. <description>Input capture 3 filter</description>
  17832. <bitOffset>4</bitOffset>
  17833. <bitWidth>4</bitWidth>
  17834. </field>
  17835. <field>
  17836. <name>IC3PSC</name>
  17837. <description>Input capture 3 prescaler</description>
  17838. <bitOffset>2</bitOffset>
  17839. <bitWidth>2</bitWidth>
  17840. </field>
  17841. <field>
  17842. <name>CC3S</name>
  17843. <description>Capture/Compare 3
  17844. selection</description>
  17845. <bitOffset>0</bitOffset>
  17846. <bitWidth>2</bitWidth>
  17847. </field>
  17848. </fields>
  17849. </register>
  17850. <register>
  17851. <name>CCER</name>
  17852. <displayName>CCER</displayName>
  17853. <description>capture/compare enable
  17854. register</description>
  17855. <addressOffset>0x20</addressOffset>
  17856. <size>0x20</size>
  17857. <access>read-write</access>
  17858. <resetValue>0x0000</resetValue>
  17859. <fields>
  17860. <field>
  17861. <name>CC4NP</name>
  17862. <description>Capture/Compare 4 output
  17863. Polarity</description>
  17864. <bitOffset>15</bitOffset>
  17865. <bitWidth>1</bitWidth>
  17866. </field>
  17867. <field>
  17868. <name>CC4P</name>
  17869. <description>Capture/Compare 3 output
  17870. Polarity</description>
  17871. <bitOffset>13</bitOffset>
  17872. <bitWidth>1</bitWidth>
  17873. </field>
  17874. <field>
  17875. <name>CC4E</name>
  17876. <description>Capture/Compare 4 output
  17877. enable</description>
  17878. <bitOffset>12</bitOffset>
  17879. <bitWidth>1</bitWidth>
  17880. </field>
  17881. <field>
  17882. <name>CC3NP</name>
  17883. <description>Capture/Compare 3 output
  17884. Polarity</description>
  17885. <bitOffset>11</bitOffset>
  17886. <bitWidth>1</bitWidth>
  17887. </field>
  17888. <field>
  17889. <name>CC3P</name>
  17890. <description>Capture/Compare 3 output
  17891. Polarity</description>
  17892. <bitOffset>9</bitOffset>
  17893. <bitWidth>1</bitWidth>
  17894. </field>
  17895. <field>
  17896. <name>CC3E</name>
  17897. <description>Capture/Compare 3 output
  17898. enable</description>
  17899. <bitOffset>8</bitOffset>
  17900. <bitWidth>1</bitWidth>
  17901. </field>
  17902. <field>
  17903. <name>CC2NP</name>
  17904. <description>Capture/Compare 2 output
  17905. Polarity</description>
  17906. <bitOffset>7</bitOffset>
  17907. <bitWidth>1</bitWidth>
  17908. </field>
  17909. <field>
  17910. <name>CC2P</name>
  17911. <description>Capture/Compare 2 output
  17912. Polarity</description>
  17913. <bitOffset>5</bitOffset>
  17914. <bitWidth>1</bitWidth>
  17915. </field>
  17916. <field>
  17917. <name>CC2E</name>
  17918. <description>Capture/Compare 2 output
  17919. enable</description>
  17920. <bitOffset>4</bitOffset>
  17921. <bitWidth>1</bitWidth>
  17922. </field>
  17923. <field>
  17924. <name>CC1NP</name>
  17925. <description>Capture/Compare 1 output
  17926. Polarity</description>
  17927. <bitOffset>3</bitOffset>
  17928. <bitWidth>1</bitWidth>
  17929. </field>
  17930. <field>
  17931. <name>CC1P</name>
  17932. <description>Capture/Compare 1 output
  17933. Polarity</description>
  17934. <bitOffset>1</bitOffset>
  17935. <bitWidth>1</bitWidth>
  17936. </field>
  17937. <field>
  17938. <name>CC1E</name>
  17939. <description>Capture/Compare 1 output
  17940. enable</description>
  17941. <bitOffset>0</bitOffset>
  17942. <bitWidth>1</bitWidth>
  17943. </field>
  17944. </fields>
  17945. </register>
  17946. <register>
  17947. <name>CNT</name>
  17948. <displayName>CNT</displayName>
  17949. <description>counter</description>
  17950. <addressOffset>0x24</addressOffset>
  17951. <size>0x20</size>
  17952. <access>read-write</access>
  17953. <resetValue>0x00000000</resetValue>
  17954. <fields>
  17955. <field>
  17956. <name>CNT_H</name>
  17957. <description>High counter value (TIM2
  17958. only)</description>
  17959. <bitOffset>16</bitOffset>
  17960. <bitWidth>16</bitWidth>
  17961. </field>
  17962. <field>
  17963. <name>CNT_L</name>
  17964. <description>Low counter value</description>
  17965. <bitOffset>0</bitOffset>
  17966. <bitWidth>16</bitWidth>
  17967. </field>
  17968. </fields>
  17969. </register>
  17970. <register>
  17971. <name>PSC</name>
  17972. <displayName>PSC</displayName>
  17973. <description>prescaler</description>
  17974. <addressOffset>0x28</addressOffset>
  17975. <size>0x20</size>
  17976. <access>read-write</access>
  17977. <resetValue>0x0000</resetValue>
  17978. <fields>
  17979. <field>
  17980. <name>PSC</name>
  17981. <description>Prescaler value</description>
  17982. <bitOffset>0</bitOffset>
  17983. <bitWidth>16</bitWidth>
  17984. </field>
  17985. </fields>
  17986. </register>
  17987. <register>
  17988. <name>ARR</name>
  17989. <displayName>ARR</displayName>
  17990. <description>auto-reload register</description>
  17991. <addressOffset>0x2C</addressOffset>
  17992. <size>0x20</size>
  17993. <access>read-write</access>
  17994. <resetValue>0x00000000</resetValue>
  17995. <fields>
  17996. <field>
  17997. <name>ARR_H</name>
  17998. <description>High Auto-reload value (TIM2
  17999. only)</description>
  18000. <bitOffset>16</bitOffset>
  18001. <bitWidth>16</bitWidth>
  18002. </field>
  18003. <field>
  18004. <name>ARR_L</name>
  18005. <description>Low Auto-reload value</description>
  18006. <bitOffset>0</bitOffset>
  18007. <bitWidth>16</bitWidth>
  18008. </field>
  18009. </fields>
  18010. </register>
  18011. <register>
  18012. <name>CCR1</name>
  18013. <displayName>CCR1</displayName>
  18014. <description>capture/compare register 1</description>
  18015. <addressOffset>0x34</addressOffset>
  18016. <size>0x20</size>
  18017. <access>read-write</access>
  18018. <resetValue>0x00000000</resetValue>
  18019. <fields>
  18020. <field>
  18021. <name>CCR1_H</name>
  18022. <description>High Capture/Compare 1 value (TIM2
  18023. only)</description>
  18024. <bitOffset>16</bitOffset>
  18025. <bitWidth>16</bitWidth>
  18026. </field>
  18027. <field>
  18028. <name>CCR1_L</name>
  18029. <description>Low Capture/Compare 1
  18030. value</description>
  18031. <bitOffset>0</bitOffset>
  18032. <bitWidth>16</bitWidth>
  18033. </field>
  18034. </fields>
  18035. </register>
  18036. <register>
  18037. <name>CCR2</name>
  18038. <displayName>CCR2</displayName>
  18039. <description>capture/compare register 2</description>
  18040. <addressOffset>0x38</addressOffset>
  18041. <size>0x20</size>
  18042. <access>read-write</access>
  18043. <resetValue>0x00000000</resetValue>
  18044. <fields>
  18045. <field>
  18046. <name>CCR2_H</name>
  18047. <description>High Capture/Compare 2 value (TIM2
  18048. only)</description>
  18049. <bitOffset>16</bitOffset>
  18050. <bitWidth>16</bitWidth>
  18051. </field>
  18052. <field>
  18053. <name>CCR2_L</name>
  18054. <description>Low Capture/Compare 2
  18055. value</description>
  18056. <bitOffset>0</bitOffset>
  18057. <bitWidth>16</bitWidth>
  18058. </field>
  18059. </fields>
  18060. </register>
  18061. <register>
  18062. <name>CCR3</name>
  18063. <displayName>CCR3</displayName>
  18064. <description>capture/compare register 3</description>
  18065. <addressOffset>0x3C</addressOffset>
  18066. <size>0x20</size>
  18067. <access>read-write</access>
  18068. <resetValue>0x00000000</resetValue>
  18069. <fields>
  18070. <field>
  18071. <name>CCR3_H</name>
  18072. <description>High Capture/Compare value (TIM2
  18073. only)</description>
  18074. <bitOffset>16</bitOffset>
  18075. <bitWidth>16</bitWidth>
  18076. </field>
  18077. <field>
  18078. <name>CCR3_L</name>
  18079. <description>Low Capture/Compare value</description>
  18080. <bitOffset>0</bitOffset>
  18081. <bitWidth>16</bitWidth>
  18082. </field>
  18083. </fields>
  18084. </register>
  18085. <register>
  18086. <name>CCR4</name>
  18087. <displayName>CCR4</displayName>
  18088. <description>capture/compare register 4</description>
  18089. <addressOffset>0x40</addressOffset>
  18090. <size>0x20</size>
  18091. <access>read-write</access>
  18092. <resetValue>0x00000000</resetValue>
  18093. <fields>
  18094. <field>
  18095. <name>CCR4_H</name>
  18096. <description>High Capture/Compare value (TIM2
  18097. only)</description>
  18098. <bitOffset>16</bitOffset>
  18099. <bitWidth>16</bitWidth>
  18100. </field>
  18101. <field>
  18102. <name>CCR4_L</name>
  18103. <description>Low Capture/Compare value</description>
  18104. <bitOffset>0</bitOffset>
  18105. <bitWidth>16</bitWidth>
  18106. </field>
  18107. </fields>
  18108. </register>
  18109. <register>
  18110. <name>DCR</name>
  18111. <displayName>DCR</displayName>
  18112. <description>DMA control register</description>
  18113. <addressOffset>0x48</addressOffset>
  18114. <size>0x20</size>
  18115. <access>read-write</access>
  18116. <resetValue>0x0000</resetValue>
  18117. <fields>
  18118. <field>
  18119. <name>DBL</name>
  18120. <description>DMA burst length</description>
  18121. <bitOffset>8</bitOffset>
  18122. <bitWidth>5</bitWidth>
  18123. </field>
  18124. <field>
  18125. <name>DBA</name>
  18126. <description>DMA base address</description>
  18127. <bitOffset>0</bitOffset>
  18128. <bitWidth>5</bitWidth>
  18129. </field>
  18130. </fields>
  18131. </register>
  18132. <register>
  18133. <name>DMAR</name>
  18134. <displayName>DMAR</displayName>
  18135. <description>DMA address for full transfer</description>
  18136. <addressOffset>0x4C</addressOffset>
  18137. <size>0x20</size>
  18138. <access>read-write</access>
  18139. <resetValue>0x0000</resetValue>
  18140. <fields>
  18141. <field>
  18142. <name>DMAB</name>
  18143. <description>DMA register for burst
  18144. accesses</description>
  18145. <bitOffset>0</bitOffset>
  18146. <bitWidth>16</bitWidth>
  18147. </field>
  18148. </fields>
  18149. </register>
  18150. <register>
  18151. <name>OR</name>
  18152. <displayName>OR</displayName>
  18153. <description>TIM2 option register</description>
  18154. <addressOffset>0x50</addressOffset>
  18155. <size>0x20</size>
  18156. <access>read-write</access>
  18157. <resetValue>0x0000</resetValue>
  18158. <fields>
  18159. <field>
  18160. <name>ETR_RMP</name>
  18161. <description>Timer2 ETR remap</description>
  18162. <bitOffset>0</bitOffset>
  18163. <bitWidth>3</bitWidth>
  18164. </field>
  18165. <field>
  18166. <name>TI4_RMP</name>
  18167. <description>Internal trigger</description>
  18168. <bitOffset>3</bitOffset>
  18169. <bitWidth>2</bitWidth>
  18170. </field>
  18171. </fields>
  18172. </register>
  18173. </registers>
  18174. </peripheral>
  18175. <peripheral>
  18176. <name>TIM6</name>
  18177. <description>Basic-timers</description>
  18178. <groupName>TIM</groupName>
  18179. <baseAddress>0x40001000</baseAddress>
  18180. <addressBlock>
  18181. <offset>0x0</offset>
  18182. <size>0x400</size>
  18183. <usage>registers</usage>
  18184. </addressBlock>
  18185. <interrupt>
  18186. <name>TIM6_DAC</name>
  18187. <description>TIM6 global interrupt and DAC</description>
  18188. <value>17</value>
  18189. </interrupt>
  18190. <registers>
  18191. <register>
  18192. <name>CR1</name>
  18193. <displayName>CR1</displayName>
  18194. <description>control register 1</description>
  18195. <addressOffset>0x0</addressOffset>
  18196. <size>0x20</size>
  18197. <access>read-write</access>
  18198. <resetValue>0x0000</resetValue>
  18199. <fields>
  18200. <field>
  18201. <name>ARPE</name>
  18202. <description>Auto-reload preload enable</description>
  18203. <bitOffset>7</bitOffset>
  18204. <bitWidth>1</bitWidth>
  18205. </field>
  18206. <field>
  18207. <name>OPM</name>
  18208. <description>One-pulse mode</description>
  18209. <bitOffset>3</bitOffset>
  18210. <bitWidth>1</bitWidth>
  18211. </field>
  18212. <field>
  18213. <name>URS</name>
  18214. <description>Update request source</description>
  18215. <bitOffset>2</bitOffset>
  18216. <bitWidth>1</bitWidth>
  18217. </field>
  18218. <field>
  18219. <name>UDIS</name>
  18220. <description>Update disable</description>
  18221. <bitOffset>1</bitOffset>
  18222. <bitWidth>1</bitWidth>
  18223. </field>
  18224. <field>
  18225. <name>CEN</name>
  18226. <description>Counter enable</description>
  18227. <bitOffset>0</bitOffset>
  18228. <bitWidth>1</bitWidth>
  18229. </field>
  18230. </fields>
  18231. </register>
  18232. <register>
  18233. <name>CR2</name>
  18234. <displayName>CR2</displayName>
  18235. <description>control register 2</description>
  18236. <addressOffset>0x4</addressOffset>
  18237. <size>0x20</size>
  18238. <access>read-write</access>
  18239. <resetValue>0x0000</resetValue>
  18240. <fields>
  18241. <field>
  18242. <name>MMS</name>
  18243. <description>Master mode selection</description>
  18244. <bitOffset>4</bitOffset>
  18245. <bitWidth>3</bitWidth>
  18246. </field>
  18247. </fields>
  18248. </register>
  18249. <register>
  18250. <name>DIER</name>
  18251. <displayName>DIER</displayName>
  18252. <description>DMA/Interrupt enable register</description>
  18253. <addressOffset>0xC</addressOffset>
  18254. <size>0x20</size>
  18255. <access>read-write</access>
  18256. <resetValue>0x0000</resetValue>
  18257. <fields>
  18258. <field>
  18259. <name>UDE</name>
  18260. <description>Update DMA request enable</description>
  18261. <bitOffset>8</bitOffset>
  18262. <bitWidth>1</bitWidth>
  18263. </field>
  18264. <field>
  18265. <name>UIE</name>
  18266. <description>Update interrupt enable</description>
  18267. <bitOffset>0</bitOffset>
  18268. <bitWidth>1</bitWidth>
  18269. </field>
  18270. </fields>
  18271. </register>
  18272. <register>
  18273. <name>SR</name>
  18274. <displayName>SR</displayName>
  18275. <description>status register</description>
  18276. <addressOffset>0x10</addressOffset>
  18277. <size>0x20</size>
  18278. <access>read-write</access>
  18279. <resetValue>0x0000</resetValue>
  18280. <fields>
  18281. <field>
  18282. <name>UIF</name>
  18283. <description>Update interrupt flag</description>
  18284. <bitOffset>0</bitOffset>
  18285. <bitWidth>1</bitWidth>
  18286. </field>
  18287. </fields>
  18288. </register>
  18289. <register>
  18290. <name>EGR</name>
  18291. <displayName>EGR</displayName>
  18292. <description>event generation register</description>
  18293. <addressOffset>0x14</addressOffset>
  18294. <size>0x20</size>
  18295. <access>write-only</access>
  18296. <resetValue>0x0000</resetValue>
  18297. <fields>
  18298. <field>
  18299. <name>UG</name>
  18300. <description>Update generation</description>
  18301. <bitOffset>0</bitOffset>
  18302. <bitWidth>1</bitWidth>
  18303. </field>
  18304. </fields>
  18305. </register>
  18306. <register>
  18307. <name>CNT</name>
  18308. <displayName>CNT</displayName>
  18309. <description>counter</description>
  18310. <addressOffset>0x24</addressOffset>
  18311. <size>0x20</size>
  18312. <access>read-write</access>
  18313. <resetValue>0x00000000</resetValue>
  18314. <fields>
  18315. <field>
  18316. <name>CNT</name>
  18317. <description>Low counter value</description>
  18318. <bitOffset>0</bitOffset>
  18319. <bitWidth>16</bitWidth>
  18320. </field>
  18321. </fields>
  18322. </register>
  18323. <register>
  18324. <name>PSC</name>
  18325. <displayName>PSC</displayName>
  18326. <description>prescaler</description>
  18327. <addressOffset>0x28</addressOffset>
  18328. <size>0x20</size>
  18329. <access>read-write</access>
  18330. <resetValue>0x0000</resetValue>
  18331. <fields>
  18332. <field>
  18333. <name>PSC</name>
  18334. <description>Prescaler value</description>
  18335. <bitOffset>0</bitOffset>
  18336. <bitWidth>16</bitWidth>
  18337. </field>
  18338. </fields>
  18339. </register>
  18340. <register>
  18341. <name>ARR</name>
  18342. <displayName>ARR</displayName>
  18343. <description>auto-reload register</description>
  18344. <addressOffset>0x2C</addressOffset>
  18345. <size>0x20</size>
  18346. <access>read-write</access>
  18347. <resetValue>0x00000000</resetValue>
  18348. <fields>
  18349. <field>
  18350. <name>ARR</name>
  18351. <description>Low Auto-reload value</description>
  18352. <bitOffset>0</bitOffset>
  18353. <bitWidth>16</bitWidth>
  18354. </field>
  18355. </fields>
  18356. </register>
  18357. </registers>
  18358. </peripheral>
  18359. <peripheral>
  18360. <name>TIM21</name>
  18361. <description>General-purpose-timers</description>
  18362. <groupName>TIM</groupName>
  18363. <baseAddress>0x40010800</baseAddress>
  18364. <addressBlock>
  18365. <offset>0x0</offset>
  18366. <size>0x400</size>
  18367. <usage>registers</usage>
  18368. </addressBlock>
  18369. <interrupt>
  18370. <name>TIM21</name>
  18371. <description>TIMER21 global interrupt</description>
  18372. <value>20</value>
  18373. </interrupt>
  18374. <registers>
  18375. <register>
  18376. <name>CR1</name>
  18377. <displayName>CR1</displayName>
  18378. <description>control register 1</description>
  18379. <addressOffset>0x0</addressOffset>
  18380. <size>0x20</size>
  18381. <access>read-write</access>
  18382. <resetValue>0x0000</resetValue>
  18383. <fields>
  18384. <field>
  18385. <name>CEN</name>
  18386. <description>Counter enable</description>
  18387. <bitOffset>0</bitOffset>
  18388. <bitWidth>1</bitWidth>
  18389. </field>
  18390. <field>
  18391. <name>UDIS</name>
  18392. <description>Update disable</description>
  18393. <bitOffset>1</bitOffset>
  18394. <bitWidth>1</bitWidth>
  18395. </field>
  18396. <field>
  18397. <name>URS</name>
  18398. <description>Update request source</description>
  18399. <bitOffset>2</bitOffset>
  18400. <bitWidth>1</bitWidth>
  18401. </field>
  18402. <field>
  18403. <name>OPM</name>
  18404. <description>One-pulse mode</description>
  18405. <bitOffset>3</bitOffset>
  18406. <bitWidth>1</bitWidth>
  18407. </field>
  18408. <field>
  18409. <name>DIR</name>
  18410. <description>Direction</description>
  18411. <bitOffset>4</bitOffset>
  18412. <bitWidth>1</bitWidth>
  18413. </field>
  18414. <field>
  18415. <name>CMS</name>
  18416. <description>Center-aligned mode
  18417. selection</description>
  18418. <bitOffset>5</bitOffset>
  18419. <bitWidth>2</bitWidth>
  18420. </field>
  18421. <field>
  18422. <name>ARPE</name>
  18423. <description>Auto-reload preload enable</description>
  18424. <bitOffset>7</bitOffset>
  18425. <bitWidth>1</bitWidth>
  18426. </field>
  18427. <field>
  18428. <name>CKD</name>
  18429. <description>Clock division</description>
  18430. <bitOffset>8</bitOffset>
  18431. <bitWidth>2</bitWidth>
  18432. </field>
  18433. </fields>
  18434. </register>
  18435. <register>
  18436. <name>CR2</name>
  18437. <displayName>CR2</displayName>
  18438. <description>control register 2</description>
  18439. <addressOffset>0x4</addressOffset>
  18440. <size>0x20</size>
  18441. <access>read-write</access>
  18442. <resetValue>0x0000</resetValue>
  18443. <fields>
  18444. <field>
  18445. <name>MMS</name>
  18446. <description>Master mode selection</description>
  18447. <bitOffset>4</bitOffset>
  18448. <bitWidth>3</bitWidth>
  18449. </field>
  18450. </fields>
  18451. </register>
  18452. <register>
  18453. <name>SMCR</name>
  18454. <displayName>SMCR</displayName>
  18455. <description>slave mode control register</description>
  18456. <addressOffset>0x8</addressOffset>
  18457. <size>0x20</size>
  18458. <access>read-write</access>
  18459. <resetValue>0x0000</resetValue>
  18460. <fields>
  18461. <field>
  18462. <name>SMS</name>
  18463. <description>Slave mode selection</description>
  18464. <bitOffset>0</bitOffset>
  18465. <bitWidth>3</bitWidth>
  18466. </field>
  18467. <field>
  18468. <name>TS</name>
  18469. <description>Trigger selection</description>
  18470. <bitOffset>4</bitOffset>
  18471. <bitWidth>3</bitWidth>
  18472. </field>
  18473. <field>
  18474. <name>MSM</name>
  18475. <description>Master/Slave mode</description>
  18476. <bitOffset>7</bitOffset>
  18477. <bitWidth>1</bitWidth>
  18478. </field>
  18479. <field>
  18480. <name>ETF</name>
  18481. <description>External trigger filter</description>
  18482. <bitOffset>8</bitOffset>
  18483. <bitWidth>4</bitWidth>
  18484. </field>
  18485. <field>
  18486. <name>ETPS</name>
  18487. <description>External trigger prescaler</description>
  18488. <bitOffset>12</bitOffset>
  18489. <bitWidth>2</bitWidth>
  18490. </field>
  18491. <field>
  18492. <name>ECE</name>
  18493. <description>External clock enable</description>
  18494. <bitOffset>14</bitOffset>
  18495. <bitWidth>1</bitWidth>
  18496. </field>
  18497. <field>
  18498. <name>ETP</name>
  18499. <description>External trigger polarity</description>
  18500. <bitOffset>15</bitOffset>
  18501. <bitWidth>1</bitWidth>
  18502. </field>
  18503. </fields>
  18504. </register>
  18505. <register>
  18506. <name>DIER</name>
  18507. <displayName>DIER</displayName>
  18508. <description>DMA/Interrupt enable register</description>
  18509. <addressOffset>0xC</addressOffset>
  18510. <size>0x20</size>
  18511. <access>read-write</access>
  18512. <resetValue>0x0000</resetValue>
  18513. <fields>
  18514. <field>
  18515. <name>TIE</name>
  18516. <description>Trigger interrupt enable</description>
  18517. <bitOffset>6</bitOffset>
  18518. <bitWidth>1</bitWidth>
  18519. </field>
  18520. <field>
  18521. <name>CC2IE</name>
  18522. <description>Capture/Compare 2 interrupt
  18523. enable</description>
  18524. <bitOffset>2</bitOffset>
  18525. <bitWidth>1</bitWidth>
  18526. </field>
  18527. <field>
  18528. <name>CC1IE</name>
  18529. <description>Capture/Compare 1 interrupt
  18530. enable</description>
  18531. <bitOffset>1</bitOffset>
  18532. <bitWidth>1</bitWidth>
  18533. </field>
  18534. <field>
  18535. <name>UIE</name>
  18536. <description>Update interrupt enable</description>
  18537. <bitOffset>0</bitOffset>
  18538. <bitWidth>1</bitWidth>
  18539. </field>
  18540. </fields>
  18541. </register>
  18542. <register>
  18543. <name>SR</name>
  18544. <displayName>SR</displayName>
  18545. <description>status register</description>
  18546. <addressOffset>0x10</addressOffset>
  18547. <size>0x20</size>
  18548. <access>read-write</access>
  18549. <resetValue>0x0000</resetValue>
  18550. <fields>
  18551. <field>
  18552. <name>CC2OF</name>
  18553. <description>Capture/compare 2 overcapture
  18554. flag</description>
  18555. <bitOffset>10</bitOffset>
  18556. <bitWidth>1</bitWidth>
  18557. </field>
  18558. <field>
  18559. <name>CC1OF</name>
  18560. <description>Capture/Compare 1 overcapture
  18561. flag</description>
  18562. <bitOffset>9</bitOffset>
  18563. <bitWidth>1</bitWidth>
  18564. </field>
  18565. <field>
  18566. <name>TIF</name>
  18567. <description>Trigger interrupt flag</description>
  18568. <bitOffset>6</bitOffset>
  18569. <bitWidth>1</bitWidth>
  18570. </field>
  18571. <field>
  18572. <name>CC2IF</name>
  18573. <description>Capture/Compare 2 interrupt
  18574. flag</description>
  18575. <bitOffset>2</bitOffset>
  18576. <bitWidth>1</bitWidth>
  18577. </field>
  18578. <field>
  18579. <name>CC1IF</name>
  18580. <description>Capture/compare 1 interrupt
  18581. flag</description>
  18582. <bitOffset>1</bitOffset>
  18583. <bitWidth>1</bitWidth>
  18584. </field>
  18585. <field>
  18586. <name>UIF</name>
  18587. <description>Update interrupt flag</description>
  18588. <bitOffset>0</bitOffset>
  18589. <bitWidth>1</bitWidth>
  18590. </field>
  18591. </fields>
  18592. </register>
  18593. <register>
  18594. <name>EGR</name>
  18595. <displayName>EGR</displayName>
  18596. <description>event generation register</description>
  18597. <addressOffset>0x14</addressOffset>
  18598. <size>0x20</size>
  18599. <access>write-only</access>
  18600. <resetValue>0x0000</resetValue>
  18601. <fields>
  18602. <field>
  18603. <name>TG</name>
  18604. <description>Trigger generation</description>
  18605. <bitOffset>6</bitOffset>
  18606. <bitWidth>1</bitWidth>
  18607. </field>
  18608. <field>
  18609. <name>CC2G</name>
  18610. <description>Capture/compare 2
  18611. generation</description>
  18612. <bitOffset>2</bitOffset>
  18613. <bitWidth>1</bitWidth>
  18614. </field>
  18615. <field>
  18616. <name>CC1G</name>
  18617. <description>Capture/compare 1
  18618. generation</description>
  18619. <bitOffset>1</bitOffset>
  18620. <bitWidth>1</bitWidth>
  18621. </field>
  18622. <field>
  18623. <name>UG</name>
  18624. <description>Update generation</description>
  18625. <bitOffset>0</bitOffset>
  18626. <bitWidth>1</bitWidth>
  18627. </field>
  18628. </fields>
  18629. </register>
  18630. <register>
  18631. <name>CCMR1_Output</name>
  18632. <displayName>CCMR1_Output</displayName>
  18633. <description>capture/compare mode register (output
  18634. mode)</description>
  18635. <addressOffset>0x18</addressOffset>
  18636. <size>0x20</size>
  18637. <access>read-write</access>
  18638. <resetValue>0x00000000</resetValue>
  18639. <fields>
  18640. <field>
  18641. <name>OC2M</name>
  18642. <description>Output Compare 2 mode</description>
  18643. <bitOffset>12</bitOffset>
  18644. <bitWidth>3</bitWidth>
  18645. </field>
  18646. <field>
  18647. <name>OC2PE</name>
  18648. <description>Output Compare 2 preload
  18649. enable</description>
  18650. <bitOffset>11</bitOffset>
  18651. <bitWidth>1</bitWidth>
  18652. </field>
  18653. <field>
  18654. <name>OC2FE</name>
  18655. <description>Output Compare 2 fast
  18656. enable</description>
  18657. <bitOffset>10</bitOffset>
  18658. <bitWidth>1</bitWidth>
  18659. </field>
  18660. <field>
  18661. <name>CC2S</name>
  18662. <description>Capture/Compare 2
  18663. selection</description>
  18664. <bitOffset>8</bitOffset>
  18665. <bitWidth>2</bitWidth>
  18666. </field>
  18667. <field>
  18668. <name>OC1M</name>
  18669. <description>Output Compare 1 mode</description>
  18670. <bitOffset>4</bitOffset>
  18671. <bitWidth>3</bitWidth>
  18672. </field>
  18673. <field>
  18674. <name>OC1PE</name>
  18675. <description>Output Compare 1 preload
  18676. enable</description>
  18677. <bitOffset>3</bitOffset>
  18678. <bitWidth>1</bitWidth>
  18679. </field>
  18680. <field>
  18681. <name>OC1FE</name>
  18682. <description>Output Compare 1 fast
  18683. enable</description>
  18684. <bitOffset>2</bitOffset>
  18685. <bitWidth>1</bitWidth>
  18686. </field>
  18687. <field>
  18688. <name>CC1S</name>
  18689. <description>Capture/Compare 1
  18690. selection</description>
  18691. <bitOffset>0</bitOffset>
  18692. <bitWidth>2</bitWidth>
  18693. </field>
  18694. </fields>
  18695. </register>
  18696. <register>
  18697. <name>CCMR1_Input</name>
  18698. <displayName>CCMR1_Input</displayName>
  18699. <description>capture/compare mode register 1 (input
  18700. mode)</description>
  18701. <alternateRegister>CCMR1_Output</alternateRegister>
  18702. <addressOffset>0x18</addressOffset>
  18703. <size>0x20</size>
  18704. <access>read-write</access>
  18705. <resetValue>0x00000000</resetValue>
  18706. <fields>
  18707. <field>
  18708. <name>IC2F</name>
  18709. <description>Input capture 2 filter</description>
  18710. <bitOffset>12</bitOffset>
  18711. <bitWidth>4</bitWidth>
  18712. </field>
  18713. <field>
  18714. <name>IC2PSC</name>
  18715. <description>Input capture 2 prescaler</description>
  18716. <bitOffset>10</bitOffset>
  18717. <bitWidth>2</bitWidth>
  18718. </field>
  18719. <field>
  18720. <name>CC2S</name>
  18721. <description>Capture/Compare 2
  18722. selection</description>
  18723. <bitOffset>8</bitOffset>
  18724. <bitWidth>2</bitWidth>
  18725. </field>
  18726. <field>
  18727. <name>IC1F</name>
  18728. <description>Input capture 1 filter</description>
  18729. <bitOffset>4</bitOffset>
  18730. <bitWidth>4</bitWidth>
  18731. </field>
  18732. <field>
  18733. <name>IC1PSC</name>
  18734. <description>Input capture 1 prescaler</description>
  18735. <bitOffset>2</bitOffset>
  18736. <bitWidth>2</bitWidth>
  18737. </field>
  18738. <field>
  18739. <name>CC1S</name>
  18740. <description>Capture/Compare 1
  18741. selection</description>
  18742. <bitOffset>0</bitOffset>
  18743. <bitWidth>2</bitWidth>
  18744. </field>
  18745. </fields>
  18746. </register>
  18747. <register>
  18748. <name>CCER</name>
  18749. <displayName>CCER</displayName>
  18750. <description>capture/compare enable
  18751. register</description>
  18752. <addressOffset>0x20</addressOffset>
  18753. <size>0x20</size>
  18754. <access>read-write</access>
  18755. <resetValue>0x0000</resetValue>
  18756. <fields>
  18757. <field>
  18758. <name>CC2NP</name>
  18759. <description>Capture/Compare 2 output
  18760. Polarity</description>
  18761. <bitOffset>7</bitOffset>
  18762. <bitWidth>1</bitWidth>
  18763. </field>
  18764. <field>
  18765. <name>CC2P</name>
  18766. <description>Capture/Compare 2 output
  18767. Polarity</description>
  18768. <bitOffset>5</bitOffset>
  18769. <bitWidth>1</bitWidth>
  18770. </field>
  18771. <field>
  18772. <name>CC2E</name>
  18773. <description>Capture/Compare 2 output
  18774. enable</description>
  18775. <bitOffset>4</bitOffset>
  18776. <bitWidth>1</bitWidth>
  18777. </field>
  18778. <field>
  18779. <name>CC1NP</name>
  18780. <description>Capture/Compare 1 output
  18781. Polarity</description>
  18782. <bitOffset>3</bitOffset>
  18783. <bitWidth>1</bitWidth>
  18784. </field>
  18785. <field>
  18786. <name>CC1P</name>
  18787. <description>Capture/Compare 1 output
  18788. Polarity</description>
  18789. <bitOffset>1</bitOffset>
  18790. <bitWidth>1</bitWidth>
  18791. </field>
  18792. <field>
  18793. <name>CC1E</name>
  18794. <description>Capture/Compare 1 output
  18795. enable</description>
  18796. <bitOffset>0</bitOffset>
  18797. <bitWidth>1</bitWidth>
  18798. </field>
  18799. </fields>
  18800. </register>
  18801. <register>
  18802. <name>CNT</name>
  18803. <displayName>CNT</displayName>
  18804. <description>counter</description>
  18805. <addressOffset>0x24</addressOffset>
  18806. <size>0x20</size>
  18807. <access>read-write</access>
  18808. <resetValue>0x00000000</resetValue>
  18809. <fields>
  18810. <field>
  18811. <name>CNT</name>
  18812. <description>counter value</description>
  18813. <bitOffset>0</bitOffset>
  18814. <bitWidth>16</bitWidth>
  18815. </field>
  18816. </fields>
  18817. </register>
  18818. <register>
  18819. <name>PSC</name>
  18820. <displayName>PSC</displayName>
  18821. <description>prescaler</description>
  18822. <addressOffset>0x28</addressOffset>
  18823. <size>0x20</size>
  18824. <access>read-write</access>
  18825. <resetValue>0x0000</resetValue>
  18826. <fields>
  18827. <field>
  18828. <name>PSC</name>
  18829. <description>Prescaler value</description>
  18830. <bitOffset>0</bitOffset>
  18831. <bitWidth>16</bitWidth>
  18832. </field>
  18833. </fields>
  18834. </register>
  18835. <register>
  18836. <name>ARR</name>
  18837. <displayName>ARR</displayName>
  18838. <description>auto-reload register</description>
  18839. <addressOffset>0x2C</addressOffset>
  18840. <size>0x20</size>
  18841. <access>read-write</access>
  18842. <resetValue>0x00000000</resetValue>
  18843. <fields>
  18844. <field>
  18845. <name>ARR</name>
  18846. <description>Auto-reload value</description>
  18847. <bitOffset>0</bitOffset>
  18848. <bitWidth>16</bitWidth>
  18849. </field>
  18850. </fields>
  18851. </register>
  18852. <register>
  18853. <name>CCR1</name>
  18854. <displayName>CCR1</displayName>
  18855. <description>capture/compare register 1</description>
  18856. <addressOffset>0x34</addressOffset>
  18857. <size>0x20</size>
  18858. <access>read-write</access>
  18859. <resetValue>0x00000000</resetValue>
  18860. <fields>
  18861. <field>
  18862. <name>CCR1</name>
  18863. <description>Capture/Compare 1 value</description>
  18864. <bitOffset>0</bitOffset>
  18865. <bitWidth>16</bitWidth>
  18866. </field>
  18867. </fields>
  18868. </register>
  18869. <register>
  18870. <name>CCR2</name>
  18871. <displayName>CCR2</displayName>
  18872. <description>capture/compare register 2</description>
  18873. <addressOffset>0x38</addressOffset>
  18874. <size>0x20</size>
  18875. <access>read-write</access>
  18876. <resetValue>0x00000000</resetValue>
  18877. <fields>
  18878. <field>
  18879. <name>CCR2</name>
  18880. <description>Capture/Compare 2 value</description>
  18881. <bitOffset>0</bitOffset>
  18882. <bitWidth>16</bitWidth>
  18883. </field>
  18884. </fields>
  18885. </register>
  18886. <register>
  18887. <name>OR</name>
  18888. <displayName>OR</displayName>
  18889. <description>TIM21 option register</description>
  18890. <addressOffset>0x50</addressOffset>
  18891. <size>0x20</size>
  18892. <access>read-write</access>
  18893. <resetValue>0x00000000</resetValue>
  18894. <fields>
  18895. <field>
  18896. <name>ETR_RMP</name>
  18897. <description>Timer21 ETR remap</description>
  18898. <bitOffset>0</bitOffset>
  18899. <bitWidth>2</bitWidth>
  18900. </field>
  18901. <field>
  18902. <name>TI1_RMP</name>
  18903. <description>Timer21 TI1</description>
  18904. <bitOffset>2</bitOffset>
  18905. <bitWidth>3</bitWidth>
  18906. </field>
  18907. <field>
  18908. <name>TI2_RMP</name>
  18909. <description>Timer21 TI2</description>
  18910. <bitOffset>5</bitOffset>
  18911. <bitWidth>1</bitWidth>
  18912. </field>
  18913. </fields>
  18914. </register>
  18915. </registers>
  18916. </peripheral>
  18917. <peripheral>
  18918. <name>TIM22</name>
  18919. <description>General-purpose-timers</description>
  18920. <groupName>TIM</groupName>
  18921. <baseAddress>0x40011400</baseAddress>
  18922. <addressBlock>
  18923. <offset>0x0</offset>
  18924. <size>0x400</size>
  18925. <usage>registers</usage>
  18926. </addressBlock>
  18927. <interrupt>
  18928. <name>TIM22</name>
  18929. <description>TIMER22 global interrupt</description>
  18930. <value>22</value>
  18931. </interrupt>
  18932. <registers>
  18933. <register>
  18934. <name>CR1</name>
  18935. <displayName>CR1</displayName>
  18936. <description>control register 1</description>
  18937. <addressOffset>0x0</addressOffset>
  18938. <size>0x20</size>
  18939. <access>read-write</access>
  18940. <resetValue>0x0000</resetValue>
  18941. <fields>
  18942. <field>
  18943. <name>CEN</name>
  18944. <description>Counter enable</description>
  18945. <bitOffset>0</bitOffset>
  18946. <bitWidth>1</bitWidth>
  18947. </field>
  18948. <field>
  18949. <name>UDIS</name>
  18950. <description>Update disable</description>
  18951. <bitOffset>1</bitOffset>
  18952. <bitWidth>1</bitWidth>
  18953. </field>
  18954. <field>
  18955. <name>URS</name>
  18956. <description>Update request source</description>
  18957. <bitOffset>2</bitOffset>
  18958. <bitWidth>1</bitWidth>
  18959. </field>
  18960. <field>
  18961. <name>OPM</name>
  18962. <description>One-pulse mode</description>
  18963. <bitOffset>3</bitOffset>
  18964. <bitWidth>1</bitWidth>
  18965. </field>
  18966. <field>
  18967. <name>DIR</name>
  18968. <description>Direction</description>
  18969. <bitOffset>4</bitOffset>
  18970. <bitWidth>1</bitWidth>
  18971. </field>
  18972. <field>
  18973. <name>CMS</name>
  18974. <description>Center-aligned mode
  18975. selection</description>
  18976. <bitOffset>5</bitOffset>
  18977. <bitWidth>2</bitWidth>
  18978. </field>
  18979. <field>
  18980. <name>ARPE</name>
  18981. <description>Auto-reload preload enable</description>
  18982. <bitOffset>7</bitOffset>
  18983. <bitWidth>1</bitWidth>
  18984. </field>
  18985. <field>
  18986. <name>CKD</name>
  18987. <description>Clock division</description>
  18988. <bitOffset>8</bitOffset>
  18989. <bitWidth>2</bitWidth>
  18990. </field>
  18991. </fields>
  18992. </register>
  18993. <register>
  18994. <name>CR2</name>
  18995. <displayName>CR2</displayName>
  18996. <description>control register 2</description>
  18997. <addressOffset>0x4</addressOffset>
  18998. <size>0x20</size>
  18999. <access>read-write</access>
  19000. <resetValue>0x0000</resetValue>
  19001. <fields>
  19002. <field>
  19003. <name>MMS</name>
  19004. <description>Master mode selection</description>
  19005. <bitOffset>4</bitOffset>
  19006. <bitWidth>3</bitWidth>
  19007. </field>
  19008. </fields>
  19009. </register>
  19010. <register>
  19011. <name>SMCR</name>
  19012. <displayName>SMCR</displayName>
  19013. <description>slave mode control register</description>
  19014. <addressOffset>0x8</addressOffset>
  19015. <size>0x20</size>
  19016. <access>read-write</access>
  19017. <resetValue>0x0000</resetValue>
  19018. <fields>
  19019. <field>
  19020. <name>SMS</name>
  19021. <description>Slave mode selection</description>
  19022. <bitOffset>0</bitOffset>
  19023. <bitWidth>3</bitWidth>
  19024. </field>
  19025. <field>
  19026. <name>TS</name>
  19027. <description>Trigger selection</description>
  19028. <bitOffset>4</bitOffset>
  19029. <bitWidth>3</bitWidth>
  19030. </field>
  19031. <field>
  19032. <name>MSM</name>
  19033. <description>Master/Slave mode</description>
  19034. <bitOffset>7</bitOffset>
  19035. <bitWidth>1</bitWidth>
  19036. </field>
  19037. <field>
  19038. <name>ETF</name>
  19039. <description>External trigger filter</description>
  19040. <bitOffset>8</bitOffset>
  19041. <bitWidth>4</bitWidth>
  19042. </field>
  19043. <field>
  19044. <name>ETPS</name>
  19045. <description>External trigger prescaler</description>
  19046. <bitOffset>12</bitOffset>
  19047. <bitWidth>2</bitWidth>
  19048. </field>
  19049. <field>
  19050. <name>ECE</name>
  19051. <description>External clock enable</description>
  19052. <bitOffset>14</bitOffset>
  19053. <bitWidth>1</bitWidth>
  19054. </field>
  19055. <field>
  19056. <name>ETP</name>
  19057. <description>External trigger polarity</description>
  19058. <bitOffset>15</bitOffset>
  19059. <bitWidth>1</bitWidth>
  19060. </field>
  19061. </fields>
  19062. </register>
  19063. <register>
  19064. <name>DIER</name>
  19065. <displayName>DIER</displayName>
  19066. <description>DMA/Interrupt enable register</description>
  19067. <addressOffset>0xC</addressOffset>
  19068. <size>0x20</size>
  19069. <access>read-write</access>
  19070. <resetValue>0x0000</resetValue>
  19071. <fields>
  19072. <field>
  19073. <name>TIE</name>
  19074. <description>Trigger interrupt enable</description>
  19075. <bitOffset>6</bitOffset>
  19076. <bitWidth>1</bitWidth>
  19077. </field>
  19078. <field>
  19079. <name>CC2IE</name>
  19080. <description>Capture/Compare 2 interrupt
  19081. enable</description>
  19082. <bitOffset>2</bitOffset>
  19083. <bitWidth>1</bitWidth>
  19084. </field>
  19085. <field>
  19086. <name>CC1IE</name>
  19087. <description>Capture/Compare 1 interrupt
  19088. enable</description>
  19089. <bitOffset>1</bitOffset>
  19090. <bitWidth>1</bitWidth>
  19091. </field>
  19092. <field>
  19093. <name>UIE</name>
  19094. <description>Update interrupt enable</description>
  19095. <bitOffset>0</bitOffset>
  19096. <bitWidth>1</bitWidth>
  19097. </field>
  19098. </fields>
  19099. </register>
  19100. <register>
  19101. <name>SR</name>
  19102. <displayName>SR</displayName>
  19103. <description>status register</description>
  19104. <addressOffset>0x10</addressOffset>
  19105. <size>0x20</size>
  19106. <access>read-write</access>
  19107. <resetValue>0x0000</resetValue>
  19108. <fields>
  19109. <field>
  19110. <name>CC2OF</name>
  19111. <description>Capture/compare 2 overcapture
  19112. flag</description>
  19113. <bitOffset>10</bitOffset>
  19114. <bitWidth>1</bitWidth>
  19115. </field>
  19116. <field>
  19117. <name>CC1OF</name>
  19118. <description>Capture/Compare 1 overcapture
  19119. flag</description>
  19120. <bitOffset>9</bitOffset>
  19121. <bitWidth>1</bitWidth>
  19122. </field>
  19123. <field>
  19124. <name>TIF</name>
  19125. <description>Trigger interrupt flag</description>
  19126. <bitOffset>6</bitOffset>
  19127. <bitWidth>1</bitWidth>
  19128. </field>
  19129. <field>
  19130. <name>CC2IF</name>
  19131. <description>Capture/Compare 2 interrupt
  19132. flag</description>
  19133. <bitOffset>2</bitOffset>
  19134. <bitWidth>1</bitWidth>
  19135. </field>
  19136. <field>
  19137. <name>CC1IF</name>
  19138. <description>Capture/compare 1 interrupt
  19139. flag</description>
  19140. <bitOffset>1</bitOffset>
  19141. <bitWidth>1</bitWidth>
  19142. </field>
  19143. <field>
  19144. <name>UIF</name>
  19145. <description>Update interrupt flag</description>
  19146. <bitOffset>0</bitOffset>
  19147. <bitWidth>1</bitWidth>
  19148. </field>
  19149. </fields>
  19150. </register>
  19151. <register>
  19152. <name>EGR</name>
  19153. <displayName>EGR</displayName>
  19154. <description>event generation register</description>
  19155. <addressOffset>0x14</addressOffset>
  19156. <size>0x20</size>
  19157. <access>write-only</access>
  19158. <resetValue>0x0000</resetValue>
  19159. <fields>
  19160. <field>
  19161. <name>TG</name>
  19162. <description>Trigger generation</description>
  19163. <bitOffset>6</bitOffset>
  19164. <bitWidth>1</bitWidth>
  19165. </field>
  19166. <field>
  19167. <name>CC2G</name>
  19168. <description>Capture/compare 2
  19169. generation</description>
  19170. <bitOffset>2</bitOffset>
  19171. <bitWidth>1</bitWidth>
  19172. </field>
  19173. <field>
  19174. <name>CC1G</name>
  19175. <description>Capture/compare 1
  19176. generation</description>
  19177. <bitOffset>1</bitOffset>
  19178. <bitWidth>1</bitWidth>
  19179. </field>
  19180. <field>
  19181. <name>UG</name>
  19182. <description>Update generation</description>
  19183. <bitOffset>0</bitOffset>
  19184. <bitWidth>1</bitWidth>
  19185. </field>
  19186. </fields>
  19187. </register>
  19188. <register>
  19189. <name>CCMR1_Output</name>
  19190. <displayName>CCMR1_Output</displayName>
  19191. <description>capture/compare mode register (output
  19192. mode)</description>
  19193. <addressOffset>0x18</addressOffset>
  19194. <size>0x20</size>
  19195. <access>read-write</access>
  19196. <resetValue>0x00000000</resetValue>
  19197. <fields>
  19198. <field>
  19199. <name>OC2M</name>
  19200. <description>Output Compare 2 mode</description>
  19201. <bitOffset>12</bitOffset>
  19202. <bitWidth>3</bitWidth>
  19203. </field>
  19204. <field>
  19205. <name>OC2PE</name>
  19206. <description>Output Compare 2 preload
  19207. enable</description>
  19208. <bitOffset>11</bitOffset>
  19209. <bitWidth>1</bitWidth>
  19210. </field>
  19211. <field>
  19212. <name>OC2FE</name>
  19213. <description>Output Compare 2 fast
  19214. enable</description>
  19215. <bitOffset>10</bitOffset>
  19216. <bitWidth>1</bitWidth>
  19217. </field>
  19218. <field>
  19219. <name>CC2S</name>
  19220. <description>Capture/Compare 2
  19221. selection</description>
  19222. <bitOffset>8</bitOffset>
  19223. <bitWidth>2</bitWidth>
  19224. </field>
  19225. <field>
  19226. <name>OC1M</name>
  19227. <description>Output Compare 1 mode</description>
  19228. <bitOffset>4</bitOffset>
  19229. <bitWidth>3</bitWidth>
  19230. </field>
  19231. <field>
  19232. <name>OC1PE</name>
  19233. <description>Output Compare 1 preload
  19234. enable</description>
  19235. <bitOffset>3</bitOffset>
  19236. <bitWidth>1</bitWidth>
  19237. </field>
  19238. <field>
  19239. <name>OC1FE</name>
  19240. <description>Output Compare 1 fast
  19241. enable</description>
  19242. <bitOffset>2</bitOffset>
  19243. <bitWidth>1</bitWidth>
  19244. </field>
  19245. <field>
  19246. <name>CC1S</name>
  19247. <description>Capture/Compare 1
  19248. selection</description>
  19249. <bitOffset>0</bitOffset>
  19250. <bitWidth>2</bitWidth>
  19251. </field>
  19252. </fields>
  19253. </register>
  19254. <register>
  19255. <name>CCMR1_Input</name>
  19256. <displayName>CCMR1_Input</displayName>
  19257. <description>capture/compare mode register 1 (input
  19258. mode)</description>
  19259. <alternateRegister>CCMR1_Output</alternateRegister>
  19260. <addressOffset>0x18</addressOffset>
  19261. <size>0x20</size>
  19262. <access>read-write</access>
  19263. <resetValue>0x00000000</resetValue>
  19264. <fields>
  19265. <field>
  19266. <name>IC2F</name>
  19267. <description>Input capture 2 filter</description>
  19268. <bitOffset>12</bitOffset>
  19269. <bitWidth>4</bitWidth>
  19270. </field>
  19271. <field>
  19272. <name>IC2PSC</name>
  19273. <description>Input capture 2 prescaler</description>
  19274. <bitOffset>10</bitOffset>
  19275. <bitWidth>2</bitWidth>
  19276. </field>
  19277. <field>
  19278. <name>CC2S</name>
  19279. <description>Capture/Compare 2
  19280. selection</description>
  19281. <bitOffset>8</bitOffset>
  19282. <bitWidth>2</bitWidth>
  19283. </field>
  19284. <field>
  19285. <name>IC1F</name>
  19286. <description>Input capture 1 filter</description>
  19287. <bitOffset>4</bitOffset>
  19288. <bitWidth>4</bitWidth>
  19289. </field>
  19290. <field>
  19291. <name>IC1PSC</name>
  19292. <description>Input capture 1 prescaler</description>
  19293. <bitOffset>2</bitOffset>
  19294. <bitWidth>2</bitWidth>
  19295. </field>
  19296. <field>
  19297. <name>CC1S</name>
  19298. <description>Capture/Compare 1
  19299. selection</description>
  19300. <bitOffset>0</bitOffset>
  19301. <bitWidth>2</bitWidth>
  19302. </field>
  19303. </fields>
  19304. </register>
  19305. <register>
  19306. <name>CCER</name>
  19307. <displayName>CCER</displayName>
  19308. <description>capture/compare enable
  19309. register</description>
  19310. <addressOffset>0x20</addressOffset>
  19311. <size>0x20</size>
  19312. <access>read-write</access>
  19313. <resetValue>0x0000</resetValue>
  19314. <fields>
  19315. <field>
  19316. <name>CC2NP</name>
  19317. <description>Capture/Compare 2 output
  19318. Polarity</description>
  19319. <bitOffset>7</bitOffset>
  19320. <bitWidth>1</bitWidth>
  19321. </field>
  19322. <field>
  19323. <name>CC2P</name>
  19324. <description>Capture/Compare 2 output
  19325. Polarity</description>
  19326. <bitOffset>5</bitOffset>
  19327. <bitWidth>1</bitWidth>
  19328. </field>
  19329. <field>
  19330. <name>CC2E</name>
  19331. <description>Capture/Compare 2 output
  19332. enable</description>
  19333. <bitOffset>4</bitOffset>
  19334. <bitWidth>1</bitWidth>
  19335. </field>
  19336. <field>
  19337. <name>CC1NP</name>
  19338. <description>Capture/Compare 1 output
  19339. Polarity</description>
  19340. <bitOffset>3</bitOffset>
  19341. <bitWidth>1</bitWidth>
  19342. </field>
  19343. <field>
  19344. <name>CC1P</name>
  19345. <description>Capture/Compare 1 output
  19346. Polarity</description>
  19347. <bitOffset>1</bitOffset>
  19348. <bitWidth>1</bitWidth>
  19349. </field>
  19350. <field>
  19351. <name>CC1E</name>
  19352. <description>Capture/Compare 1 output
  19353. enable</description>
  19354. <bitOffset>0</bitOffset>
  19355. <bitWidth>1</bitWidth>
  19356. </field>
  19357. </fields>
  19358. </register>
  19359. <register>
  19360. <name>CNT</name>
  19361. <displayName>CNT</displayName>
  19362. <description>counter</description>
  19363. <addressOffset>0x24</addressOffset>
  19364. <size>0x20</size>
  19365. <access>read-write</access>
  19366. <resetValue>0x00000000</resetValue>
  19367. <fields>
  19368. <field>
  19369. <name>CNT</name>
  19370. <description>counter value</description>
  19371. <bitOffset>0</bitOffset>
  19372. <bitWidth>16</bitWidth>
  19373. </field>
  19374. </fields>
  19375. </register>
  19376. <register>
  19377. <name>PSC</name>
  19378. <displayName>PSC</displayName>
  19379. <description>prescaler</description>
  19380. <addressOffset>0x28</addressOffset>
  19381. <size>0x20</size>
  19382. <access>read-write</access>
  19383. <resetValue>0x0000</resetValue>
  19384. <fields>
  19385. <field>
  19386. <name>PSC</name>
  19387. <description>Prescaler value</description>
  19388. <bitOffset>0</bitOffset>
  19389. <bitWidth>16</bitWidth>
  19390. </field>
  19391. </fields>
  19392. </register>
  19393. <register>
  19394. <name>ARR</name>
  19395. <displayName>ARR</displayName>
  19396. <description>auto-reload register</description>
  19397. <addressOffset>0x2C</addressOffset>
  19398. <size>0x20</size>
  19399. <access>read-write</access>
  19400. <resetValue>0x00000000</resetValue>
  19401. <fields>
  19402. <field>
  19403. <name>ARR</name>
  19404. <description>Auto-reload value</description>
  19405. <bitOffset>0</bitOffset>
  19406. <bitWidth>16</bitWidth>
  19407. </field>
  19408. </fields>
  19409. </register>
  19410. <register>
  19411. <name>CCR1</name>
  19412. <displayName>CCR1</displayName>
  19413. <description>capture/compare register 1</description>
  19414. <addressOffset>0x34</addressOffset>
  19415. <size>0x20</size>
  19416. <access>read-write</access>
  19417. <resetValue>0x00000000</resetValue>
  19418. <fields>
  19419. <field>
  19420. <name>CCR1</name>
  19421. <description>Capture/Compare 1 value</description>
  19422. <bitOffset>0</bitOffset>
  19423. <bitWidth>16</bitWidth>
  19424. </field>
  19425. </fields>
  19426. </register>
  19427. <register>
  19428. <name>CCR2</name>
  19429. <displayName>CCR2</displayName>
  19430. <description>capture/compare register 2</description>
  19431. <addressOffset>0x38</addressOffset>
  19432. <size>0x20</size>
  19433. <access>read-write</access>
  19434. <resetValue>0x00000000</resetValue>
  19435. <fields>
  19436. <field>
  19437. <name>CCR2</name>
  19438. <description>Capture/Compare 2 value</description>
  19439. <bitOffset>0</bitOffset>
  19440. <bitWidth>16</bitWidth>
  19441. </field>
  19442. </fields>
  19443. </register>
  19444. <register>
  19445. <name>OR</name>
  19446. <displayName>OR</displayName>
  19447. <description>TIM22 option register</description>
  19448. <addressOffset>0x50</addressOffset>
  19449. <size>0x20</size>
  19450. <access>read-write</access>
  19451. <resetValue>0x00000000</resetValue>
  19452. <fields>
  19453. <field>
  19454. <name>ETR_RMP</name>
  19455. <description>Timer22 ETR remap</description>
  19456. <bitOffset>0</bitOffset>
  19457. <bitWidth>2</bitWidth>
  19458. </field>
  19459. <field>
  19460. <name>TI1_RMP</name>
  19461. <description>Timer22 TI1</description>
  19462. <bitOffset>2</bitOffset>
  19463. <bitWidth>2</bitWidth>
  19464. </field>
  19465. </fields>
  19466. </register>
  19467. </registers>
  19468. </peripheral>
  19469. <peripheral>
  19470. <name>LPUSART1</name>
  19471. <description>Universal synchronous asynchronous receiver
  19472. transmitter</description>
  19473. <groupName>USART</groupName>
  19474. <baseAddress>0x40004800</baseAddress>
  19475. <addressBlock>
  19476. <offset>0x0</offset>
  19477. <size>0x400</size>
  19478. <usage>registers</usage>
  19479. </addressBlock>
  19480. <registers>
  19481. <register>
  19482. <name>CR1</name>
  19483. <displayName>CR1</displayName>
  19484. <description>Control register 1</description>
  19485. <addressOffset>0x0</addressOffset>
  19486. <size>0x20</size>
  19487. <access>read-write</access>
  19488. <resetValue>0x0000</resetValue>
  19489. <fields>
  19490. <field>
  19491. <name>M1</name>
  19492. <description>Word length</description>
  19493. <bitOffset>28</bitOffset>
  19494. <bitWidth>1</bitWidth>
  19495. </field>
  19496. <field>
  19497. <name>DEAT4</name>
  19498. <description>Driver Enable assertion
  19499. time</description>
  19500. <bitOffset>25</bitOffset>
  19501. <bitWidth>1</bitWidth>
  19502. </field>
  19503. <field>
  19504. <name>DEAT3</name>
  19505. <description>DEAT3</description>
  19506. <bitOffset>24</bitOffset>
  19507. <bitWidth>1</bitWidth>
  19508. </field>
  19509. <field>
  19510. <name>DEAT2</name>
  19511. <description>DEAT2</description>
  19512. <bitOffset>23</bitOffset>
  19513. <bitWidth>1</bitWidth>
  19514. </field>
  19515. <field>
  19516. <name>DEAT1</name>
  19517. <description>DEAT1</description>
  19518. <bitOffset>22</bitOffset>
  19519. <bitWidth>1</bitWidth>
  19520. </field>
  19521. <field>
  19522. <name>DEAT0</name>
  19523. <description>DEAT0</description>
  19524. <bitOffset>21</bitOffset>
  19525. <bitWidth>1</bitWidth>
  19526. </field>
  19527. <field>
  19528. <name>DEDT4</name>
  19529. <description>Driver Enable de-assertion
  19530. time</description>
  19531. <bitOffset>20</bitOffset>
  19532. <bitWidth>1</bitWidth>
  19533. </field>
  19534. <field>
  19535. <name>DEDT3</name>
  19536. <description>DEDT3</description>
  19537. <bitOffset>19</bitOffset>
  19538. <bitWidth>1</bitWidth>
  19539. </field>
  19540. <field>
  19541. <name>DEDT2</name>
  19542. <description>DEDT2</description>
  19543. <bitOffset>18</bitOffset>
  19544. <bitWidth>1</bitWidth>
  19545. </field>
  19546. <field>
  19547. <name>DEDT1</name>
  19548. <description>DEDT1</description>
  19549. <bitOffset>17</bitOffset>
  19550. <bitWidth>1</bitWidth>
  19551. </field>
  19552. <field>
  19553. <name>DEDT0</name>
  19554. <description>DEDT0</description>
  19555. <bitOffset>16</bitOffset>
  19556. <bitWidth>1</bitWidth>
  19557. </field>
  19558. <field>
  19559. <name>CMIE</name>
  19560. <description>Character match interrupt
  19561. enable</description>
  19562. <bitOffset>14</bitOffset>
  19563. <bitWidth>1</bitWidth>
  19564. </field>
  19565. <field>
  19566. <name>MME</name>
  19567. <description>Mute mode enable</description>
  19568. <bitOffset>13</bitOffset>
  19569. <bitWidth>1</bitWidth>
  19570. </field>
  19571. <field>
  19572. <name>M0</name>
  19573. <description>Word length</description>
  19574. <bitOffset>12</bitOffset>
  19575. <bitWidth>1</bitWidth>
  19576. </field>
  19577. <field>
  19578. <name>WAKE</name>
  19579. <description>Receiver wakeup method</description>
  19580. <bitOffset>11</bitOffset>
  19581. <bitWidth>1</bitWidth>
  19582. </field>
  19583. <field>
  19584. <name>PCE</name>
  19585. <description>Parity control enable</description>
  19586. <bitOffset>10</bitOffset>
  19587. <bitWidth>1</bitWidth>
  19588. </field>
  19589. <field>
  19590. <name>PS</name>
  19591. <description>Parity selection</description>
  19592. <bitOffset>9</bitOffset>
  19593. <bitWidth>1</bitWidth>
  19594. </field>
  19595. <field>
  19596. <name>PEIE</name>
  19597. <description>PE interrupt enable</description>
  19598. <bitOffset>8</bitOffset>
  19599. <bitWidth>1</bitWidth>
  19600. </field>
  19601. <field>
  19602. <name>TXEIE</name>
  19603. <description>interrupt enable</description>
  19604. <bitOffset>7</bitOffset>
  19605. <bitWidth>1</bitWidth>
  19606. </field>
  19607. <field>
  19608. <name>TCIE</name>
  19609. <description>Transmission complete interrupt
  19610. enable</description>
  19611. <bitOffset>6</bitOffset>
  19612. <bitWidth>1</bitWidth>
  19613. </field>
  19614. <field>
  19615. <name>RXNEIE</name>
  19616. <description>RXNE interrupt enable</description>
  19617. <bitOffset>5</bitOffset>
  19618. <bitWidth>1</bitWidth>
  19619. </field>
  19620. <field>
  19621. <name>IDLEIE</name>
  19622. <description>IDLE interrupt enable</description>
  19623. <bitOffset>4</bitOffset>
  19624. <bitWidth>1</bitWidth>
  19625. </field>
  19626. <field>
  19627. <name>TE</name>
  19628. <description>Transmitter enable</description>
  19629. <bitOffset>3</bitOffset>
  19630. <bitWidth>1</bitWidth>
  19631. </field>
  19632. <field>
  19633. <name>RE</name>
  19634. <description>Receiver enable</description>
  19635. <bitOffset>2</bitOffset>
  19636. <bitWidth>1</bitWidth>
  19637. </field>
  19638. <field>
  19639. <name>UESM</name>
  19640. <description>USART enable in Stop mode</description>
  19641. <bitOffset>1</bitOffset>
  19642. <bitWidth>1</bitWidth>
  19643. </field>
  19644. <field>
  19645. <name>UE</name>
  19646. <description>USART enable</description>
  19647. <bitOffset>0</bitOffset>
  19648. <bitWidth>1</bitWidth>
  19649. </field>
  19650. </fields>
  19651. </register>
  19652. <register>
  19653. <name>CR2</name>
  19654. <displayName>CR2</displayName>
  19655. <description>Control register 2</description>
  19656. <addressOffset>0x4</addressOffset>
  19657. <size>0x20</size>
  19658. <access>read-write</access>
  19659. <resetValue>0x0000</resetValue>
  19660. <fields>
  19661. <field>
  19662. <name>ADD4_7</name>
  19663. <description>Address of the USART node</description>
  19664. <bitOffset>28</bitOffset>
  19665. <bitWidth>4</bitWidth>
  19666. </field>
  19667. <field>
  19668. <name>ADD0_3</name>
  19669. <description>Address of the USART node</description>
  19670. <bitOffset>24</bitOffset>
  19671. <bitWidth>4</bitWidth>
  19672. </field>
  19673. <field>
  19674. <name>MSBFIRST</name>
  19675. <description>Most significant bit first</description>
  19676. <bitOffset>19</bitOffset>
  19677. <bitWidth>1</bitWidth>
  19678. </field>
  19679. <field>
  19680. <name>TAINV</name>
  19681. <description>Binary data inversion</description>
  19682. <bitOffset>18</bitOffset>
  19683. <bitWidth>1</bitWidth>
  19684. </field>
  19685. <field>
  19686. <name>TXINV</name>
  19687. <description>TX pin active level
  19688. inversion</description>
  19689. <bitOffset>17</bitOffset>
  19690. <bitWidth>1</bitWidth>
  19691. </field>
  19692. <field>
  19693. <name>RXINV</name>
  19694. <description>RX pin active level
  19695. inversion</description>
  19696. <bitOffset>16</bitOffset>
  19697. <bitWidth>1</bitWidth>
  19698. </field>
  19699. <field>
  19700. <name>SWAP</name>
  19701. <description>Swap TX/RX pins</description>
  19702. <bitOffset>15</bitOffset>
  19703. <bitWidth>1</bitWidth>
  19704. </field>
  19705. <field>
  19706. <name>STOP</name>
  19707. <description>STOP bits</description>
  19708. <bitOffset>12</bitOffset>
  19709. <bitWidth>2</bitWidth>
  19710. </field>
  19711. <field>
  19712. <name>CLKEN</name>
  19713. <description>Clock enable</description>
  19714. <bitOffset>11</bitOffset>
  19715. <bitWidth>1</bitWidth>
  19716. </field>
  19717. <field>
  19718. <name>ADDM7</name>
  19719. <description>7-bit Address Detection/4-bit Address
  19720. Detection</description>
  19721. <bitOffset>4</bitOffset>
  19722. <bitWidth>1</bitWidth>
  19723. </field>
  19724. </fields>
  19725. </register>
  19726. <register>
  19727. <name>CR3</name>
  19728. <displayName>CR3</displayName>
  19729. <description>Control register 3</description>
  19730. <addressOffset>0x8</addressOffset>
  19731. <size>0x20</size>
  19732. <access>read-write</access>
  19733. <resetValue>0x0000</resetValue>
  19734. <fields>
  19735. <field>
  19736. <name>WUFIE</name>
  19737. <description>Wakeup from Stop mode interrupt
  19738. enable</description>
  19739. <bitOffset>22</bitOffset>
  19740. <bitWidth>1</bitWidth>
  19741. </field>
  19742. <field>
  19743. <name>WUS</name>
  19744. <description>Wakeup from Stop mode interrupt flag
  19745. selection</description>
  19746. <bitOffset>20</bitOffset>
  19747. <bitWidth>2</bitWidth>
  19748. </field>
  19749. <field>
  19750. <name>DEP</name>
  19751. <description>Driver enable polarity
  19752. selection</description>
  19753. <bitOffset>15</bitOffset>
  19754. <bitWidth>1</bitWidth>
  19755. </field>
  19756. <field>
  19757. <name>DEM</name>
  19758. <description>Driver enable mode</description>
  19759. <bitOffset>14</bitOffset>
  19760. <bitWidth>1</bitWidth>
  19761. </field>
  19762. <field>
  19763. <name>DDRE</name>
  19764. <description>DMA Disable on Reception
  19765. Error</description>
  19766. <bitOffset>13</bitOffset>
  19767. <bitWidth>1</bitWidth>
  19768. </field>
  19769. <field>
  19770. <name>OVRDIS</name>
  19771. <description>Overrun Disable</description>
  19772. <bitOffset>12</bitOffset>
  19773. <bitWidth>1</bitWidth>
  19774. </field>
  19775. <field>
  19776. <name>CTSIE</name>
  19777. <description>CTS interrupt enable</description>
  19778. <bitOffset>10</bitOffset>
  19779. <bitWidth>1</bitWidth>
  19780. </field>
  19781. <field>
  19782. <name>CTSE</name>
  19783. <description>CTS enable</description>
  19784. <bitOffset>9</bitOffset>
  19785. <bitWidth>1</bitWidth>
  19786. </field>
  19787. <field>
  19788. <name>RTSE</name>
  19789. <description>RTS enable</description>
  19790. <bitOffset>8</bitOffset>
  19791. <bitWidth>1</bitWidth>
  19792. </field>
  19793. <field>
  19794. <name>DMAT</name>
  19795. <description>DMA enable transmitter</description>
  19796. <bitOffset>7</bitOffset>
  19797. <bitWidth>1</bitWidth>
  19798. </field>
  19799. <field>
  19800. <name>DMAR</name>
  19801. <description>DMA enable receiver</description>
  19802. <bitOffset>6</bitOffset>
  19803. <bitWidth>1</bitWidth>
  19804. </field>
  19805. <field>
  19806. <name>HDSEL</name>
  19807. <description>Half-duplex selection</description>
  19808. <bitOffset>3</bitOffset>
  19809. <bitWidth>1</bitWidth>
  19810. </field>
  19811. <field>
  19812. <name>EIE</name>
  19813. <description>Error interrupt enable</description>
  19814. <bitOffset>0</bitOffset>
  19815. <bitWidth>1</bitWidth>
  19816. </field>
  19817. </fields>
  19818. </register>
  19819. <register>
  19820. <name>BRR</name>
  19821. <displayName>BRR</displayName>
  19822. <description>Baud rate register</description>
  19823. <addressOffset>0xC</addressOffset>
  19824. <size>0x20</size>
  19825. <access>read-write</access>
  19826. <resetValue>0x0000</resetValue>
  19827. <fields>
  19828. <field>
  19829. <name>BRR</name>
  19830. <description>BRR</description>
  19831. <bitOffset>0</bitOffset>
  19832. <bitWidth>20</bitWidth>
  19833. </field>
  19834. </fields>
  19835. </register>
  19836. <register>
  19837. <name>RQR</name>
  19838. <displayName>RQR</displayName>
  19839. <description>Request register</description>
  19840. <addressOffset>0x18</addressOffset>
  19841. <size>0x20</size>
  19842. <access>write-only</access>
  19843. <resetValue>0x0000</resetValue>
  19844. <fields>
  19845. <field>
  19846. <name>RXFRQ</name>
  19847. <description>Receive data flush request</description>
  19848. <bitOffset>3</bitOffset>
  19849. <bitWidth>1</bitWidth>
  19850. </field>
  19851. <field>
  19852. <name>MMRQ</name>
  19853. <description>Mute mode request</description>
  19854. <bitOffset>2</bitOffset>
  19855. <bitWidth>1</bitWidth>
  19856. </field>
  19857. <field>
  19858. <name>SBKRQ</name>
  19859. <description>Send break request</description>
  19860. <bitOffset>1</bitOffset>
  19861. <bitWidth>1</bitWidth>
  19862. </field>
  19863. </fields>
  19864. </register>
  19865. <register>
  19866. <name>ISR</name>
  19867. <displayName>ISR</displayName>
  19868. <description>Interrupt &amp; status
  19869. register</description>
  19870. <addressOffset>0x1C</addressOffset>
  19871. <size>0x20</size>
  19872. <access>read-only</access>
  19873. <resetValue>0x00C0</resetValue>
  19874. <fields>
  19875. <field>
  19876. <name>REACK</name>
  19877. <description>REACK</description>
  19878. <bitOffset>22</bitOffset>
  19879. <bitWidth>1</bitWidth>
  19880. </field>
  19881. <field>
  19882. <name>TEACK</name>
  19883. <description>TEACK</description>
  19884. <bitOffset>21</bitOffset>
  19885. <bitWidth>1</bitWidth>
  19886. </field>
  19887. <field>
  19888. <name>WUF</name>
  19889. <description>WUF</description>
  19890. <bitOffset>20</bitOffset>
  19891. <bitWidth>1</bitWidth>
  19892. </field>
  19893. <field>
  19894. <name>RWU</name>
  19895. <description>RWU</description>
  19896. <bitOffset>19</bitOffset>
  19897. <bitWidth>1</bitWidth>
  19898. </field>
  19899. <field>
  19900. <name>SBKF</name>
  19901. <description>SBKF</description>
  19902. <bitOffset>18</bitOffset>
  19903. <bitWidth>1</bitWidth>
  19904. </field>
  19905. <field>
  19906. <name>CMF</name>
  19907. <description>CMF</description>
  19908. <bitOffset>17</bitOffset>
  19909. <bitWidth>1</bitWidth>
  19910. </field>
  19911. <field>
  19912. <name>BUSY</name>
  19913. <description>BUSY</description>
  19914. <bitOffset>16</bitOffset>
  19915. <bitWidth>1</bitWidth>
  19916. </field>
  19917. <field>
  19918. <name>CTS</name>
  19919. <description>CTS</description>
  19920. <bitOffset>10</bitOffset>
  19921. <bitWidth>1</bitWidth>
  19922. </field>
  19923. <field>
  19924. <name>CTSIF</name>
  19925. <description>CTSIF</description>
  19926. <bitOffset>9</bitOffset>
  19927. <bitWidth>1</bitWidth>
  19928. </field>
  19929. <field>
  19930. <name>TXE</name>
  19931. <description>TXE</description>
  19932. <bitOffset>7</bitOffset>
  19933. <bitWidth>1</bitWidth>
  19934. </field>
  19935. <field>
  19936. <name>TC</name>
  19937. <description>TC</description>
  19938. <bitOffset>6</bitOffset>
  19939. <bitWidth>1</bitWidth>
  19940. </field>
  19941. <field>
  19942. <name>RXNE</name>
  19943. <description>RXNE</description>
  19944. <bitOffset>5</bitOffset>
  19945. <bitWidth>1</bitWidth>
  19946. </field>
  19947. <field>
  19948. <name>IDLE</name>
  19949. <description>IDLE</description>
  19950. <bitOffset>4</bitOffset>
  19951. <bitWidth>1</bitWidth>
  19952. </field>
  19953. <field>
  19954. <name>ORE</name>
  19955. <description>ORE</description>
  19956. <bitOffset>3</bitOffset>
  19957. <bitWidth>1</bitWidth>
  19958. </field>
  19959. <field>
  19960. <name>NF</name>
  19961. <description>NF</description>
  19962. <bitOffset>2</bitOffset>
  19963. <bitWidth>1</bitWidth>
  19964. </field>
  19965. <field>
  19966. <name>FE</name>
  19967. <description>FE</description>
  19968. <bitOffset>1</bitOffset>
  19969. <bitWidth>1</bitWidth>
  19970. </field>
  19971. <field>
  19972. <name>PE</name>
  19973. <description>PE</description>
  19974. <bitOffset>0</bitOffset>
  19975. <bitWidth>1</bitWidth>
  19976. </field>
  19977. </fields>
  19978. </register>
  19979. <register>
  19980. <name>ICR</name>
  19981. <displayName>ICR</displayName>
  19982. <description>Interrupt flag clear register</description>
  19983. <addressOffset>0x20</addressOffset>
  19984. <size>0x20</size>
  19985. <access>write-only</access>
  19986. <resetValue>0x0000</resetValue>
  19987. <fields>
  19988. <field>
  19989. <name>WUCF</name>
  19990. <description>Wakeup from Stop mode clear
  19991. flag</description>
  19992. <bitOffset>20</bitOffset>
  19993. <bitWidth>1</bitWidth>
  19994. </field>
  19995. <field>
  19996. <name>CMCF</name>
  19997. <description>Character match clear flag</description>
  19998. <bitOffset>17</bitOffset>
  19999. <bitWidth>1</bitWidth>
  20000. </field>
  20001. <field>
  20002. <name>CTSCF</name>
  20003. <description>CTS clear flag</description>
  20004. <bitOffset>9</bitOffset>
  20005. <bitWidth>1</bitWidth>
  20006. </field>
  20007. <field>
  20008. <name>TCCF</name>
  20009. <description>Transmission complete clear
  20010. flag</description>
  20011. <bitOffset>6</bitOffset>
  20012. <bitWidth>1</bitWidth>
  20013. </field>
  20014. <field>
  20015. <name>IDLECF</name>
  20016. <description>Idle line detected clear
  20017. flag</description>
  20018. <bitOffset>4</bitOffset>
  20019. <bitWidth>1</bitWidth>
  20020. </field>
  20021. <field>
  20022. <name>ORECF</name>
  20023. <description>Overrun error clear flag</description>
  20024. <bitOffset>3</bitOffset>
  20025. <bitWidth>1</bitWidth>
  20026. </field>
  20027. <field>
  20028. <name>NCF</name>
  20029. <description>Noise detected clear flag</description>
  20030. <bitOffset>2</bitOffset>
  20031. <bitWidth>1</bitWidth>
  20032. </field>
  20033. <field>
  20034. <name>FECF</name>
  20035. <description>Framing error clear flag</description>
  20036. <bitOffset>1</bitOffset>
  20037. <bitWidth>1</bitWidth>
  20038. </field>
  20039. <field>
  20040. <name>PECF</name>
  20041. <description>Parity error clear flag</description>
  20042. <bitOffset>0</bitOffset>
  20043. <bitWidth>1</bitWidth>
  20044. </field>
  20045. </fields>
  20046. </register>
  20047. <register>
  20048. <name>RDR</name>
  20049. <displayName>RDR</displayName>
  20050. <description>Receive data register</description>
  20051. <addressOffset>0x24</addressOffset>
  20052. <size>0x20</size>
  20053. <access>read-only</access>
  20054. <resetValue>0x0000</resetValue>
  20055. <fields>
  20056. <field>
  20057. <name>RDR</name>
  20058. <description>Receive data value</description>
  20059. <bitOffset>0</bitOffset>
  20060. <bitWidth>9</bitWidth>
  20061. </field>
  20062. </fields>
  20063. </register>
  20064. <register>
  20065. <name>TDR</name>
  20066. <displayName>TDR</displayName>
  20067. <description>Transmit data register</description>
  20068. <addressOffset>0x28</addressOffset>
  20069. <size>0x20</size>
  20070. <access>read-write</access>
  20071. <resetValue>0x0000</resetValue>
  20072. <fields>
  20073. <field>
  20074. <name>TDR</name>
  20075. <description>Transmit data value</description>
  20076. <bitOffset>0</bitOffset>
  20077. <bitWidth>9</bitWidth>
  20078. </field>
  20079. </fields>
  20080. </register>
  20081. </registers>
  20082. </peripheral>
  20083. <peripheral>
  20084. <name>NVIC</name>
  20085. <description>Nested Vectored Interrupt
  20086. Controller</description>
  20087. <groupName>NVIC</groupName>
  20088. <baseAddress>0xE000E100</baseAddress>
  20089. <addressBlock>
  20090. <offset>0x0</offset>
  20091. <size>0x33D</size>
  20092. <usage>registers</usage>
  20093. </addressBlock>
  20094. <registers>
  20095. <register>
  20096. <name>ISER</name>
  20097. <displayName>ISER</displayName>
  20098. <description>Interrupt Set Enable Register</description>
  20099. <addressOffset>0x0</addressOffset>
  20100. <size>0x20</size>
  20101. <access>read-write</access>
  20102. <resetValue>0x00000000</resetValue>
  20103. <fields>
  20104. <field>
  20105. <name>SETENA</name>
  20106. <description>SETENA</description>
  20107. <bitOffset>0</bitOffset>
  20108. <bitWidth>32</bitWidth>
  20109. </field>
  20110. </fields>
  20111. </register>
  20112. <register>
  20113. <name>ICER</name>
  20114. <displayName>ICER</displayName>
  20115. <description>Interrupt Clear Enable
  20116. Register</description>
  20117. <addressOffset>0x80</addressOffset>
  20118. <size>0x20</size>
  20119. <access>read-write</access>
  20120. <resetValue>0x00000000</resetValue>
  20121. <fields>
  20122. <field>
  20123. <name>CLRENA</name>
  20124. <description>CLRENA</description>
  20125. <bitOffset>0</bitOffset>
  20126. <bitWidth>32</bitWidth>
  20127. </field>
  20128. </fields>
  20129. </register>
  20130. <register>
  20131. <name>ISPR</name>
  20132. <displayName>ISPR</displayName>
  20133. <description>Interrupt Set-Pending Register</description>
  20134. <addressOffset>0x100</addressOffset>
  20135. <size>0x20</size>
  20136. <access>read-write</access>
  20137. <resetValue>0x00000000</resetValue>
  20138. <fields>
  20139. <field>
  20140. <name>SETPEND</name>
  20141. <description>SETPEND</description>
  20142. <bitOffset>0</bitOffset>
  20143. <bitWidth>32</bitWidth>
  20144. </field>
  20145. </fields>
  20146. </register>
  20147. <register>
  20148. <name>ICPR</name>
  20149. <displayName>ICPR</displayName>
  20150. <description>Interrupt Clear-Pending
  20151. Register</description>
  20152. <addressOffset>0x180</addressOffset>
  20153. <size>0x20</size>
  20154. <access>read-write</access>
  20155. <resetValue>0x00000000</resetValue>
  20156. <fields>
  20157. <field>
  20158. <name>CLRPEND</name>
  20159. <description>CLRPEND</description>
  20160. <bitOffset>0</bitOffset>
  20161. <bitWidth>32</bitWidth>
  20162. </field>
  20163. </fields>
  20164. </register>
  20165. <register>
  20166. <name>IPR0</name>
  20167. <displayName>IPR0</displayName>
  20168. <description>Interrupt Priority Register 0</description>
  20169. <addressOffset>0x300</addressOffset>
  20170. <size>0x20</size>
  20171. <access>read-write</access>
  20172. <resetValue>0x00000000</resetValue>
  20173. <fields>
  20174. <field>
  20175. <name>PRI_0</name>
  20176. <description>priority for interrupt 0</description>
  20177. <bitOffset>0</bitOffset>
  20178. <bitWidth>8</bitWidth>
  20179. </field>
  20180. <field>
  20181. <name>PRI_1</name>
  20182. <description>priority for interrupt 1</description>
  20183. <bitOffset>8</bitOffset>
  20184. <bitWidth>8</bitWidth>
  20185. </field>
  20186. <field>
  20187. <name>PRI_2</name>
  20188. <description>priority for interrupt 2</description>
  20189. <bitOffset>16</bitOffset>
  20190. <bitWidth>8</bitWidth>
  20191. </field>
  20192. <field>
  20193. <name>PRI_3</name>
  20194. <description>priority for interrupt 3</description>
  20195. <bitOffset>24</bitOffset>
  20196. <bitWidth>8</bitWidth>
  20197. </field>
  20198. </fields>
  20199. </register>
  20200. <register>
  20201. <name>IPR1</name>
  20202. <displayName>IPR1</displayName>
  20203. <description>Interrupt Priority Register 1</description>
  20204. <addressOffset>0x304</addressOffset>
  20205. <size>0x20</size>
  20206. <access>read-write</access>
  20207. <resetValue>0x00000000</resetValue>
  20208. <fields>
  20209. <field>
  20210. <name>PRI_4</name>
  20211. <description>priority for interrupt n</description>
  20212. <bitOffset>0</bitOffset>
  20213. <bitWidth>8</bitWidth>
  20214. </field>
  20215. <field>
  20216. <name>PRI_5</name>
  20217. <description>priority for interrupt n</description>
  20218. <bitOffset>8</bitOffset>
  20219. <bitWidth>8</bitWidth>
  20220. </field>
  20221. <field>
  20222. <name>PRI_6</name>
  20223. <description>priority for interrupt n</description>
  20224. <bitOffset>16</bitOffset>
  20225. <bitWidth>8</bitWidth>
  20226. </field>
  20227. <field>
  20228. <name>PRI_7</name>
  20229. <description>priority for interrupt n</description>
  20230. <bitOffset>24</bitOffset>
  20231. <bitWidth>8</bitWidth>
  20232. </field>
  20233. </fields>
  20234. </register>
  20235. <register>
  20236. <name>IPR2</name>
  20237. <displayName>IPR2</displayName>
  20238. <description>Interrupt Priority Register 2</description>
  20239. <addressOffset>0x308</addressOffset>
  20240. <size>0x20</size>
  20241. <access>read-write</access>
  20242. <resetValue>0x00000000</resetValue>
  20243. <fields>
  20244. <field>
  20245. <name>PRI_8</name>
  20246. <description>priority for interrupt n</description>
  20247. <bitOffset>0</bitOffset>
  20248. <bitWidth>8</bitWidth>
  20249. </field>
  20250. <field>
  20251. <name>PRI_9</name>
  20252. <description>priority for interrupt n</description>
  20253. <bitOffset>8</bitOffset>
  20254. <bitWidth>8</bitWidth>
  20255. </field>
  20256. <field>
  20257. <name>PRI_10</name>
  20258. <description>priority for interrupt n</description>
  20259. <bitOffset>16</bitOffset>
  20260. <bitWidth>8</bitWidth>
  20261. </field>
  20262. <field>
  20263. <name>PRI_11</name>
  20264. <description>priority for interrupt n</description>
  20265. <bitOffset>24</bitOffset>
  20266. <bitWidth>8</bitWidth>
  20267. </field>
  20268. </fields>
  20269. </register>
  20270. <register>
  20271. <name>IPR3</name>
  20272. <displayName>IPR3</displayName>
  20273. <description>Interrupt Priority Register 3</description>
  20274. <addressOffset>0x30C</addressOffset>
  20275. <size>0x20</size>
  20276. <access>read-write</access>
  20277. <resetValue>0x00000000</resetValue>
  20278. <fields>
  20279. <field>
  20280. <name>PRI_12</name>
  20281. <description>priority for interrupt n</description>
  20282. <bitOffset>0</bitOffset>
  20283. <bitWidth>8</bitWidth>
  20284. </field>
  20285. <field>
  20286. <name>PRI_13</name>
  20287. <description>priority for interrupt n</description>
  20288. <bitOffset>8</bitOffset>
  20289. <bitWidth>8</bitWidth>
  20290. </field>
  20291. <field>
  20292. <name>PRI_14</name>
  20293. <description>priority for interrupt n</description>
  20294. <bitOffset>16</bitOffset>
  20295. <bitWidth>8</bitWidth>
  20296. </field>
  20297. <field>
  20298. <name>PRI_15</name>
  20299. <description>priority for interrupt n</description>
  20300. <bitOffset>24</bitOffset>
  20301. <bitWidth>8</bitWidth>
  20302. </field>
  20303. </fields>
  20304. </register>
  20305. <register>
  20306. <name>IPR4</name>
  20307. <displayName>IPR4</displayName>
  20308. <description>Interrupt Priority Register 4</description>
  20309. <addressOffset>0x310</addressOffset>
  20310. <size>0x20</size>
  20311. <access>read-write</access>
  20312. <resetValue>0x00000000</resetValue>
  20313. <fields>
  20314. <field>
  20315. <name>PRI_16</name>
  20316. <description>priority for interrupt n</description>
  20317. <bitOffset>0</bitOffset>
  20318. <bitWidth>8</bitWidth>
  20319. </field>
  20320. <field>
  20321. <name>PRI_17</name>
  20322. <description>priority for interrupt n</description>
  20323. <bitOffset>8</bitOffset>
  20324. <bitWidth>8</bitWidth>
  20325. </field>
  20326. <field>
  20327. <name>PRI_18</name>
  20328. <description>priority for interrupt n</description>
  20329. <bitOffset>16</bitOffset>
  20330. <bitWidth>8</bitWidth>
  20331. </field>
  20332. <field>
  20333. <name>PRI_19</name>
  20334. <description>priority for interrupt n</description>
  20335. <bitOffset>24</bitOffset>
  20336. <bitWidth>8</bitWidth>
  20337. </field>
  20338. </fields>
  20339. </register>
  20340. <register>
  20341. <name>IPR5</name>
  20342. <displayName>IPR5</displayName>
  20343. <description>Interrupt Priority Register 5</description>
  20344. <addressOffset>0x314</addressOffset>
  20345. <size>0x20</size>
  20346. <access>read-write</access>
  20347. <resetValue>0x00000000</resetValue>
  20348. <fields>
  20349. <field>
  20350. <name>PRI_20</name>
  20351. <description>priority for interrupt n</description>
  20352. <bitOffset>0</bitOffset>
  20353. <bitWidth>8</bitWidth>
  20354. </field>
  20355. <field>
  20356. <name>PRI_21</name>
  20357. <description>priority for interrupt n</description>
  20358. <bitOffset>8</bitOffset>
  20359. <bitWidth>8</bitWidth>
  20360. </field>
  20361. <field>
  20362. <name>PRI_22</name>
  20363. <description>priority for interrupt n</description>
  20364. <bitOffset>16</bitOffset>
  20365. <bitWidth>8</bitWidth>
  20366. </field>
  20367. <field>
  20368. <name>PRI_23</name>
  20369. <description>priority for interrupt n</description>
  20370. <bitOffset>24</bitOffset>
  20371. <bitWidth>8</bitWidth>
  20372. </field>
  20373. </fields>
  20374. </register>
  20375. <register>
  20376. <name>IPR6</name>
  20377. <displayName>IPR6</displayName>
  20378. <description>Interrupt Priority Register 6</description>
  20379. <addressOffset>0x318</addressOffset>
  20380. <size>0x20</size>
  20381. <access>read-write</access>
  20382. <resetValue>0x00000000</resetValue>
  20383. <fields>
  20384. <field>
  20385. <name>PRI_24</name>
  20386. <description>priority for interrupt n</description>
  20387. <bitOffset>0</bitOffset>
  20388. <bitWidth>8</bitWidth>
  20389. </field>
  20390. <field>
  20391. <name>PRI_25</name>
  20392. <description>priority for interrupt n</description>
  20393. <bitOffset>8</bitOffset>
  20394. <bitWidth>8</bitWidth>
  20395. </field>
  20396. <field>
  20397. <name>PRI_26</name>
  20398. <description>priority for interrupt n</description>
  20399. <bitOffset>16</bitOffset>
  20400. <bitWidth>8</bitWidth>
  20401. </field>
  20402. <field>
  20403. <name>PRI_27</name>
  20404. <description>priority for interrupt n</description>
  20405. <bitOffset>24</bitOffset>
  20406. <bitWidth>8</bitWidth>
  20407. </field>
  20408. </fields>
  20409. </register>
  20410. <register>
  20411. <name>IPR7</name>
  20412. <displayName>IPR7</displayName>
  20413. <description>Interrupt Priority Register 7</description>
  20414. <addressOffset>0x31C</addressOffset>
  20415. <size>0x20</size>
  20416. <access>read-write</access>
  20417. <resetValue>0x00000000</resetValue>
  20418. <fields>
  20419. <field>
  20420. <name>PRI_28</name>
  20421. <description>priority for interrupt n</description>
  20422. <bitOffset>0</bitOffset>
  20423. <bitWidth>8</bitWidth>
  20424. </field>
  20425. <field>
  20426. <name>PRI_29</name>
  20427. <description>priority for interrupt n</description>
  20428. <bitOffset>8</bitOffset>
  20429. <bitWidth>8</bitWidth>
  20430. </field>
  20431. <field>
  20432. <name>PRI_30</name>
  20433. <description>priority for interrupt n</description>
  20434. <bitOffset>16</bitOffset>
  20435. <bitWidth>8</bitWidth>
  20436. </field>
  20437. <field>
  20438. <name>PRI_31</name>
  20439. <description>priority for interrupt n</description>
  20440. <bitOffset>24</bitOffset>
  20441. <bitWidth>8</bitWidth>
  20442. </field>
  20443. </fields>
  20444. </register>
  20445. </registers>
  20446. </peripheral>
  20447. </peripherals>
  20448. </device>