STM32L0x0.svd 625 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  3. <name>STM32L0x0</name>
  4. <version>1.0</version>
  5. <description>STM32L0x0</description>
  6. <cpu>
  7. <name>CM0+</name>
  8. <revision>r0p0</revision>
  9. <endian>little</endian>
  10. <mpuPresent>true</mpuPresent>
  11. <fpuPresent>false</fpuPresent>
  12. <nvicPrioBits>4</nvicPrioBits>
  13. <vendorSystickConfig>false</vendorSystickConfig>
  14. </cpu>
  15. <!--Bus Interface Properties-->
  16. <!--Cortex-M3 is byte addressable-->
  17. <addressUnitBits>8</addressUnitBits>
  18. <!--the maximum data bit width accessible within a single transfer-->
  19. <width>32</width>
  20. <!--Register Default Properties-->
  21. <size>0x20</size>
  22. <resetValue>0x0</resetValue>
  23. <resetMask>0xFFFFFFFF</resetMask>
  24. <peripherals>
  25. <peripheral>
  26. <name>DMA1</name>
  27. <description>Direct memory access controller</description>
  28. <groupName>DMA</groupName>
  29. <baseAddress>0x40020000</baseAddress>
  30. <addressBlock>
  31. <offset>0x0</offset>
  32. <size>0x400</size>
  33. <usage>registers</usage>
  34. </addressBlock>
  35. <interrupt>
  36. <name>DMA1_Channel1</name>
  37. <description>DMA1 Channel1 global interrupt</description>
  38. <value>9</value>
  39. </interrupt>
  40. <interrupt>
  41. <name>DMA1_Channel2_3</name>
  42. <description>DMA1 Channel2 and 3 interrupts</description>
  43. <value>10</value>
  44. </interrupt>
  45. <interrupt>
  46. <name>DMA1_Channel4_7</name>
  47. <description>DMA1 Channel4 to 7 interrupts</description>
  48. <value>11</value>
  49. </interrupt>
  50. <registers>
  51. <register>
  52. <name>ISR</name>
  53. <displayName>ISR</displayName>
  54. <description>interrupt status register</description>
  55. <addressOffset>0x0</addressOffset>
  56. <size>0x20</size>
  57. <access>read-only</access>
  58. <resetValue>0x00000000</resetValue>
  59. <fields>
  60. <field>
  61. <name>TEIF7</name>
  62. <description>Channel x transfer error flag (x = 1 ..7)</description>
  63. <bitOffset>27</bitOffset>
  64. <bitWidth>1</bitWidth>
  65. </field>
  66. <field>
  67. <name>HTIF7</name>
  68. <description>Channel x half transfer flag (x = 1 ..7)</description>
  69. <bitOffset>26</bitOffset>
  70. <bitWidth>1</bitWidth>
  71. </field>
  72. <field>
  73. <name>TCIF7</name>
  74. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  75. <bitOffset>25</bitOffset>
  76. <bitWidth>1</bitWidth>
  77. </field>
  78. <field>
  79. <name>GIF7</name>
  80. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  81. <bitOffset>24</bitOffset>
  82. <bitWidth>1</bitWidth>
  83. </field>
  84. <field>
  85. <name>TEIF6</name>
  86. <description>Channel x transfer error flag (x = 1 ..7)</description>
  87. <bitOffset>23</bitOffset>
  88. <bitWidth>1</bitWidth>
  89. </field>
  90. <field>
  91. <name>HTIF6</name>
  92. <description>Channel x half transfer flag (x = 1 ..7)</description>
  93. <bitOffset>22</bitOffset>
  94. <bitWidth>1</bitWidth>
  95. </field>
  96. <field>
  97. <name>TCIF6</name>
  98. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  99. <bitOffset>21</bitOffset>
  100. <bitWidth>1</bitWidth>
  101. </field>
  102. <field>
  103. <name>GIF6</name>
  104. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  105. <bitOffset>20</bitOffset>
  106. <bitWidth>1</bitWidth>
  107. </field>
  108. <field>
  109. <name>TEIF5</name>
  110. <description>Channel x transfer error flag (x = 1 ..7)</description>
  111. <bitOffset>19</bitOffset>
  112. <bitWidth>1</bitWidth>
  113. </field>
  114. <field>
  115. <name>HTIF5</name>
  116. <description>Channel x half transfer flag (x = 1 ..7)</description>
  117. <bitOffset>18</bitOffset>
  118. <bitWidth>1</bitWidth>
  119. </field>
  120. <field>
  121. <name>TCIF5</name>
  122. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  123. <bitOffset>17</bitOffset>
  124. <bitWidth>1</bitWidth>
  125. </field>
  126. <field>
  127. <name>GIF5</name>
  128. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  129. <bitOffset>16</bitOffset>
  130. <bitWidth>1</bitWidth>
  131. </field>
  132. <field>
  133. <name>TEIF4</name>
  134. <description>Channel x transfer error flag (x = 1 ..7)</description>
  135. <bitOffset>15</bitOffset>
  136. <bitWidth>1</bitWidth>
  137. </field>
  138. <field>
  139. <name>HTIF4</name>
  140. <description>Channel x half transfer flag (x = 1 ..7)</description>
  141. <bitOffset>14</bitOffset>
  142. <bitWidth>1</bitWidth>
  143. </field>
  144. <field>
  145. <name>TCIF4</name>
  146. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  147. <bitOffset>13</bitOffset>
  148. <bitWidth>1</bitWidth>
  149. </field>
  150. <field>
  151. <name>GIF4</name>
  152. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  153. <bitOffset>12</bitOffset>
  154. <bitWidth>1</bitWidth>
  155. </field>
  156. <field>
  157. <name>TEIF3</name>
  158. <description>Channel x transfer error flag (x = 1 ..7)</description>
  159. <bitOffset>11</bitOffset>
  160. <bitWidth>1</bitWidth>
  161. </field>
  162. <field>
  163. <name>HTIF3</name>
  164. <description>Channel x half transfer flag (x = 1 ..7)</description>
  165. <bitOffset>10</bitOffset>
  166. <bitWidth>1</bitWidth>
  167. </field>
  168. <field>
  169. <name>TCIF3</name>
  170. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  171. <bitOffset>9</bitOffset>
  172. <bitWidth>1</bitWidth>
  173. </field>
  174. <field>
  175. <name>GIF3</name>
  176. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  177. <bitOffset>8</bitOffset>
  178. <bitWidth>1</bitWidth>
  179. </field>
  180. <field>
  181. <name>TEIF2</name>
  182. <description>Channel x transfer error flag (x = 1 ..7)</description>
  183. <bitOffset>7</bitOffset>
  184. <bitWidth>1</bitWidth>
  185. </field>
  186. <field>
  187. <name>HTIF2</name>
  188. <description>Channel x half transfer flag (x = 1 ..7)</description>
  189. <bitOffset>6</bitOffset>
  190. <bitWidth>1</bitWidth>
  191. </field>
  192. <field>
  193. <name>TCIF2</name>
  194. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  195. <bitOffset>5</bitOffset>
  196. <bitWidth>1</bitWidth>
  197. </field>
  198. <field>
  199. <name>GIF2</name>
  200. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  201. <bitOffset>4</bitOffset>
  202. <bitWidth>1</bitWidth>
  203. </field>
  204. <field>
  205. <name>TEIF1</name>
  206. <description>Channel x transfer error flag (x = 1 ..7)</description>
  207. <bitOffset>3</bitOffset>
  208. <bitWidth>1</bitWidth>
  209. </field>
  210. <field>
  211. <name>HTIF1</name>
  212. <description>Channel x half transfer flag (x = 1 ..7)</description>
  213. <bitOffset>2</bitOffset>
  214. <bitWidth>1</bitWidth>
  215. </field>
  216. <field>
  217. <name>TCIF1</name>
  218. <description>Channel x transfer complete flag (x = 1 ..7)</description>
  219. <bitOffset>1</bitOffset>
  220. <bitWidth>1</bitWidth>
  221. </field>
  222. <field>
  223. <name>GIF1</name>
  224. <description>Channel x global interrupt flag (x = 1 ..7)</description>
  225. <bitOffset>0</bitOffset>
  226. <bitWidth>1</bitWidth>
  227. </field>
  228. </fields>
  229. </register>
  230. <register>
  231. <name>IFCR</name>
  232. <displayName>IFCR</displayName>
  233. <description>interrupt flag clear register</description>
  234. <addressOffset>0x4</addressOffset>
  235. <size>0x20</size>
  236. <access>write-only</access>
  237. <resetValue>0x00000000</resetValue>
  238. <fields>
  239. <field>
  240. <name>CTEIF7</name>
  241. <description>Channel x transfer error clear (x = 1 ..7)</description>
  242. <bitOffset>27</bitOffset>
  243. <bitWidth>1</bitWidth>
  244. </field>
  245. <field>
  246. <name>CHTIF7</name>
  247. <description>Channel x half transfer clear (x = 1 ..7)</description>
  248. <bitOffset>26</bitOffset>
  249. <bitWidth>1</bitWidth>
  250. </field>
  251. <field>
  252. <name>CTCIF7</name>
  253. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  254. <bitOffset>25</bitOffset>
  255. <bitWidth>1</bitWidth>
  256. </field>
  257. <field>
  258. <name>CGIF7</name>
  259. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  260. <bitOffset>24</bitOffset>
  261. <bitWidth>1</bitWidth>
  262. </field>
  263. <field>
  264. <name>CTEIF6</name>
  265. <description>Channel x transfer error clear (x = 1 ..7)</description>
  266. <bitOffset>23</bitOffset>
  267. <bitWidth>1</bitWidth>
  268. </field>
  269. <field>
  270. <name>CHTIF6</name>
  271. <description>Channel x half transfer clear (x = 1 ..7)</description>
  272. <bitOffset>22</bitOffset>
  273. <bitWidth>1</bitWidth>
  274. </field>
  275. <field>
  276. <name>CTCIF6</name>
  277. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  278. <bitOffset>21</bitOffset>
  279. <bitWidth>1</bitWidth>
  280. </field>
  281. <field>
  282. <name>CGIF6</name>
  283. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  284. <bitOffset>20</bitOffset>
  285. <bitWidth>1</bitWidth>
  286. </field>
  287. <field>
  288. <name>CTEIF5</name>
  289. <description>Channel x transfer error clear (x = 1 ..7)</description>
  290. <bitOffset>19</bitOffset>
  291. <bitWidth>1</bitWidth>
  292. </field>
  293. <field>
  294. <name>CHTIF5</name>
  295. <description>Channel x half transfer clear (x = 1 ..7)</description>
  296. <bitOffset>18</bitOffset>
  297. <bitWidth>1</bitWidth>
  298. </field>
  299. <field>
  300. <name>CTCIF5</name>
  301. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  302. <bitOffset>17</bitOffset>
  303. <bitWidth>1</bitWidth>
  304. </field>
  305. <field>
  306. <name>CGIF5</name>
  307. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  308. <bitOffset>16</bitOffset>
  309. <bitWidth>1</bitWidth>
  310. </field>
  311. <field>
  312. <name>CTEIF4</name>
  313. <description>Channel x transfer error clear (x = 1 ..7)</description>
  314. <bitOffset>15</bitOffset>
  315. <bitWidth>1</bitWidth>
  316. </field>
  317. <field>
  318. <name>CHTIF4</name>
  319. <description>Channel x half transfer clear (x = 1 ..7)</description>
  320. <bitOffset>14</bitOffset>
  321. <bitWidth>1</bitWidth>
  322. </field>
  323. <field>
  324. <name>CTCIF4</name>
  325. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  326. <bitOffset>13</bitOffset>
  327. <bitWidth>1</bitWidth>
  328. </field>
  329. <field>
  330. <name>CGIF4</name>
  331. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  332. <bitOffset>12</bitOffset>
  333. <bitWidth>1</bitWidth>
  334. </field>
  335. <field>
  336. <name>CTEIF3</name>
  337. <description>Channel x transfer error clear (x = 1 ..7)</description>
  338. <bitOffset>11</bitOffset>
  339. <bitWidth>1</bitWidth>
  340. </field>
  341. <field>
  342. <name>CHTIF3</name>
  343. <description>Channel x half transfer clear (x = 1 ..7)</description>
  344. <bitOffset>10</bitOffset>
  345. <bitWidth>1</bitWidth>
  346. </field>
  347. <field>
  348. <name>CTCIF3</name>
  349. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  350. <bitOffset>9</bitOffset>
  351. <bitWidth>1</bitWidth>
  352. </field>
  353. <field>
  354. <name>CGIF3</name>
  355. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  356. <bitOffset>8</bitOffset>
  357. <bitWidth>1</bitWidth>
  358. </field>
  359. <field>
  360. <name>CTEIF2</name>
  361. <description>Channel x transfer error clear (x = 1 ..7)</description>
  362. <bitOffset>7</bitOffset>
  363. <bitWidth>1</bitWidth>
  364. </field>
  365. <field>
  366. <name>CHTIF2</name>
  367. <description>Channel x half transfer clear (x = 1 ..7)</description>
  368. <bitOffset>6</bitOffset>
  369. <bitWidth>1</bitWidth>
  370. </field>
  371. <field>
  372. <name>CTCIF2</name>
  373. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  374. <bitOffset>5</bitOffset>
  375. <bitWidth>1</bitWidth>
  376. </field>
  377. <field>
  378. <name>CGIF2</name>
  379. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  380. <bitOffset>4</bitOffset>
  381. <bitWidth>1</bitWidth>
  382. </field>
  383. <field>
  384. <name>CTEIF1</name>
  385. <description>Channel x transfer error clear (x = 1 ..7)</description>
  386. <bitOffset>3</bitOffset>
  387. <bitWidth>1</bitWidth>
  388. </field>
  389. <field>
  390. <name>CHTIF1</name>
  391. <description>Channel x half transfer clear (x = 1 ..7)</description>
  392. <bitOffset>2</bitOffset>
  393. <bitWidth>1</bitWidth>
  394. </field>
  395. <field>
  396. <name>CTCIF1</name>
  397. <description>Channel x transfer complete clear (x = 1 ..7)</description>
  398. <bitOffset>1</bitOffset>
  399. <bitWidth>1</bitWidth>
  400. </field>
  401. <field>
  402. <name>CGIF1</name>
  403. <description>Channel x global interrupt clear (x = 1 ..7)</description>
  404. <bitOffset>0</bitOffset>
  405. <bitWidth>1</bitWidth>
  406. </field>
  407. </fields>
  408. </register>
  409. <register>
  410. <name>CCR1</name>
  411. <displayName>CCR1</displayName>
  412. <description>channel x configuration register</description>
  413. <addressOffset>0x8</addressOffset>
  414. <size>0x20</size>
  415. <access>read-write</access>
  416. <resetValue>0x00000000</resetValue>
  417. <fields>
  418. <field>
  419. <name>MEM2MEM</name>
  420. <description>Memory to memory mode</description>
  421. <bitOffset>14</bitOffset>
  422. <bitWidth>1</bitWidth>
  423. </field>
  424. <field>
  425. <name>PL</name>
  426. <description>Channel priority level</description>
  427. <bitOffset>12</bitOffset>
  428. <bitWidth>2</bitWidth>
  429. </field>
  430. <field>
  431. <name>MSIZE</name>
  432. <description>Memory size</description>
  433. <bitOffset>10</bitOffset>
  434. <bitWidth>2</bitWidth>
  435. </field>
  436. <field>
  437. <name>PSIZE</name>
  438. <description>Peripheral size</description>
  439. <bitOffset>8</bitOffset>
  440. <bitWidth>2</bitWidth>
  441. </field>
  442. <field>
  443. <name>MINC</name>
  444. <description>Memory increment mode</description>
  445. <bitOffset>7</bitOffset>
  446. <bitWidth>1</bitWidth>
  447. </field>
  448. <field>
  449. <name>PINC</name>
  450. <description>Peripheral increment mode</description>
  451. <bitOffset>6</bitOffset>
  452. <bitWidth>1</bitWidth>
  453. </field>
  454. <field>
  455. <name>CIRC</name>
  456. <description>Circular mode</description>
  457. <bitOffset>5</bitOffset>
  458. <bitWidth>1</bitWidth>
  459. </field>
  460. <field>
  461. <name>DIR</name>
  462. <description>Data transfer direction</description>
  463. <bitOffset>4</bitOffset>
  464. <bitWidth>1</bitWidth>
  465. </field>
  466. <field>
  467. <name>TEIE</name>
  468. <description>Transfer error interrupt enable</description>
  469. <bitOffset>3</bitOffset>
  470. <bitWidth>1</bitWidth>
  471. </field>
  472. <field>
  473. <name>HTIE</name>
  474. <description>Half transfer interrupt enable</description>
  475. <bitOffset>2</bitOffset>
  476. <bitWidth>1</bitWidth>
  477. </field>
  478. <field>
  479. <name>TCIE</name>
  480. <description>Transfer complete interrupt enable</description>
  481. <bitOffset>1</bitOffset>
  482. <bitWidth>1</bitWidth>
  483. </field>
  484. <field>
  485. <name>EN</name>
  486. <description>Channel enable</description>
  487. <bitOffset>0</bitOffset>
  488. <bitWidth>1</bitWidth>
  489. </field>
  490. </fields>
  491. </register>
  492. <register>
  493. <name>CNDTR1</name>
  494. <displayName>CNDTR1</displayName>
  495. <description>channel x number of data register</description>
  496. <addressOffset>0xC</addressOffset>
  497. <size>0x20</size>
  498. <access>read-write</access>
  499. <resetValue>0x00000000</resetValue>
  500. <fields>
  501. <field>
  502. <name>NDT</name>
  503. <description>Number of data to transfer</description>
  504. <bitOffset>0</bitOffset>
  505. <bitWidth>16</bitWidth>
  506. </field>
  507. </fields>
  508. </register>
  509. <register>
  510. <name>CPAR1</name>
  511. <displayName>CPAR1</displayName>
  512. <description>channel x peripheral address register</description>
  513. <addressOffset>0x10</addressOffset>
  514. <size>0x20</size>
  515. <access>read-write</access>
  516. <resetValue>0x00000000</resetValue>
  517. <fields>
  518. <field>
  519. <name>PA</name>
  520. <description>Peripheral address</description>
  521. <bitOffset>0</bitOffset>
  522. <bitWidth>32</bitWidth>
  523. </field>
  524. </fields>
  525. </register>
  526. <register>
  527. <name>CMAR1</name>
  528. <displayName>CMAR1</displayName>
  529. <description>channel x memory address register</description>
  530. <addressOffset>0x14</addressOffset>
  531. <size>0x20</size>
  532. <access>read-write</access>
  533. <resetValue>0x00000000</resetValue>
  534. <fields>
  535. <field>
  536. <name>MA</name>
  537. <description>Memory address</description>
  538. <bitOffset>0</bitOffset>
  539. <bitWidth>32</bitWidth>
  540. </field>
  541. </fields>
  542. </register>
  543. <register>
  544. <name>CCR2</name>
  545. <displayName>CCR2</displayName>
  546. <description>channel x configuration register</description>
  547. <addressOffset>0x1C</addressOffset>
  548. <size>0x20</size>
  549. <access>read-write</access>
  550. <resetValue>0x00000000</resetValue>
  551. <fields>
  552. <field>
  553. <name>MEM2MEM</name>
  554. <description>Memory to memory mode</description>
  555. <bitOffset>14</bitOffset>
  556. <bitWidth>1</bitWidth>
  557. </field>
  558. <field>
  559. <name>PL</name>
  560. <description>Channel priority level</description>
  561. <bitOffset>12</bitOffset>
  562. <bitWidth>2</bitWidth>
  563. </field>
  564. <field>
  565. <name>MSIZE</name>
  566. <description>Memory size</description>
  567. <bitOffset>10</bitOffset>
  568. <bitWidth>2</bitWidth>
  569. </field>
  570. <field>
  571. <name>PSIZE</name>
  572. <description>Peripheral size</description>
  573. <bitOffset>8</bitOffset>
  574. <bitWidth>2</bitWidth>
  575. </field>
  576. <field>
  577. <name>MINC</name>
  578. <description>Memory increment mode</description>
  579. <bitOffset>7</bitOffset>
  580. <bitWidth>1</bitWidth>
  581. </field>
  582. <field>
  583. <name>PINC</name>
  584. <description>Peripheral increment mode</description>
  585. <bitOffset>6</bitOffset>
  586. <bitWidth>1</bitWidth>
  587. </field>
  588. <field>
  589. <name>CIRC</name>
  590. <description>Circular mode</description>
  591. <bitOffset>5</bitOffset>
  592. <bitWidth>1</bitWidth>
  593. </field>
  594. <field>
  595. <name>DIR</name>
  596. <description>Data transfer direction</description>
  597. <bitOffset>4</bitOffset>
  598. <bitWidth>1</bitWidth>
  599. </field>
  600. <field>
  601. <name>TEIE</name>
  602. <description>Transfer error interrupt enable</description>
  603. <bitOffset>3</bitOffset>
  604. <bitWidth>1</bitWidth>
  605. </field>
  606. <field>
  607. <name>HTIE</name>
  608. <description>Half transfer interrupt enable</description>
  609. <bitOffset>2</bitOffset>
  610. <bitWidth>1</bitWidth>
  611. </field>
  612. <field>
  613. <name>TCIE</name>
  614. <description>Transfer complete interrupt enable</description>
  615. <bitOffset>1</bitOffset>
  616. <bitWidth>1</bitWidth>
  617. </field>
  618. <field>
  619. <name>EN</name>
  620. <description>Channel enable</description>
  621. <bitOffset>0</bitOffset>
  622. <bitWidth>1</bitWidth>
  623. </field>
  624. </fields>
  625. </register>
  626. <register>
  627. <name>CNDTR2</name>
  628. <displayName>CNDTR2</displayName>
  629. <description>channel x number of data register</description>
  630. <addressOffset>0x20</addressOffset>
  631. <size>0x20</size>
  632. <access>read-write</access>
  633. <resetValue>0x00000000</resetValue>
  634. <fields>
  635. <field>
  636. <name>NDT</name>
  637. <description>Number of data to transfer</description>
  638. <bitOffset>0</bitOffset>
  639. <bitWidth>16</bitWidth>
  640. </field>
  641. </fields>
  642. </register>
  643. <register>
  644. <name>CPAR2</name>
  645. <displayName>CPAR2</displayName>
  646. <description>channel x peripheral address register</description>
  647. <addressOffset>0x24</addressOffset>
  648. <size>0x20</size>
  649. <access>read-write</access>
  650. <resetValue>0x00000000</resetValue>
  651. <fields>
  652. <field>
  653. <name>PA</name>
  654. <description>Peripheral address</description>
  655. <bitOffset>0</bitOffset>
  656. <bitWidth>32</bitWidth>
  657. </field>
  658. </fields>
  659. </register>
  660. <register>
  661. <name>CMAR2</name>
  662. <displayName>CMAR2</displayName>
  663. <description>channel x memory address register</description>
  664. <addressOffset>0x28</addressOffset>
  665. <size>0x20</size>
  666. <access>read-write</access>
  667. <resetValue>0x00000000</resetValue>
  668. <fields>
  669. <field>
  670. <name>MA</name>
  671. <description>Memory address</description>
  672. <bitOffset>0</bitOffset>
  673. <bitWidth>32</bitWidth>
  674. </field>
  675. </fields>
  676. </register>
  677. <register>
  678. <name>CCR3</name>
  679. <displayName>CCR3</displayName>
  680. <description>channel x configuration register</description>
  681. <addressOffset>0x30</addressOffset>
  682. <size>0x20</size>
  683. <access>read-write</access>
  684. <resetValue>0x00000000</resetValue>
  685. <fields>
  686. <field>
  687. <name>MEM2MEM</name>
  688. <description>Memory to memory mode</description>
  689. <bitOffset>14</bitOffset>
  690. <bitWidth>1</bitWidth>
  691. </field>
  692. <field>
  693. <name>PL</name>
  694. <description>Channel priority level</description>
  695. <bitOffset>12</bitOffset>
  696. <bitWidth>2</bitWidth>
  697. </field>
  698. <field>
  699. <name>MSIZE</name>
  700. <description>Memory size</description>
  701. <bitOffset>10</bitOffset>
  702. <bitWidth>2</bitWidth>
  703. </field>
  704. <field>
  705. <name>PSIZE</name>
  706. <description>Peripheral size</description>
  707. <bitOffset>8</bitOffset>
  708. <bitWidth>2</bitWidth>
  709. </field>
  710. <field>
  711. <name>MINC</name>
  712. <description>Memory increment mode</description>
  713. <bitOffset>7</bitOffset>
  714. <bitWidth>1</bitWidth>
  715. </field>
  716. <field>
  717. <name>PINC</name>
  718. <description>Peripheral increment mode</description>
  719. <bitOffset>6</bitOffset>
  720. <bitWidth>1</bitWidth>
  721. </field>
  722. <field>
  723. <name>CIRC</name>
  724. <description>Circular mode</description>
  725. <bitOffset>5</bitOffset>
  726. <bitWidth>1</bitWidth>
  727. </field>
  728. <field>
  729. <name>DIR</name>
  730. <description>Data transfer direction</description>
  731. <bitOffset>4</bitOffset>
  732. <bitWidth>1</bitWidth>
  733. </field>
  734. <field>
  735. <name>TEIE</name>
  736. <description>Transfer error interrupt enable</description>
  737. <bitOffset>3</bitOffset>
  738. <bitWidth>1</bitWidth>
  739. </field>
  740. <field>
  741. <name>HTIE</name>
  742. <description>Half transfer interrupt enable</description>
  743. <bitOffset>2</bitOffset>
  744. <bitWidth>1</bitWidth>
  745. </field>
  746. <field>
  747. <name>TCIE</name>
  748. <description>Transfer complete interrupt enable</description>
  749. <bitOffset>1</bitOffset>
  750. <bitWidth>1</bitWidth>
  751. </field>
  752. <field>
  753. <name>EN</name>
  754. <description>Channel enable</description>
  755. <bitOffset>0</bitOffset>
  756. <bitWidth>1</bitWidth>
  757. </field>
  758. </fields>
  759. </register>
  760. <register>
  761. <name>CNDTR3</name>
  762. <displayName>CNDTR3</displayName>
  763. <description>channel x number of data register</description>
  764. <addressOffset>0x34</addressOffset>
  765. <size>0x20</size>
  766. <access>read-write</access>
  767. <resetValue>0x00000000</resetValue>
  768. <fields>
  769. <field>
  770. <name>NDT</name>
  771. <description>Number of data to transfer</description>
  772. <bitOffset>0</bitOffset>
  773. <bitWidth>16</bitWidth>
  774. </field>
  775. </fields>
  776. </register>
  777. <register>
  778. <name>CPAR3</name>
  779. <displayName>CPAR3</displayName>
  780. <description>channel x peripheral address register</description>
  781. <addressOffset>0x38</addressOffset>
  782. <size>0x20</size>
  783. <access>read-write</access>
  784. <resetValue>0x00000000</resetValue>
  785. <fields>
  786. <field>
  787. <name>PA</name>
  788. <description>Peripheral address</description>
  789. <bitOffset>0</bitOffset>
  790. <bitWidth>32</bitWidth>
  791. </field>
  792. </fields>
  793. </register>
  794. <register>
  795. <name>CMAR3</name>
  796. <displayName>CMAR3</displayName>
  797. <description>channel x memory address register</description>
  798. <addressOffset>0x3C</addressOffset>
  799. <size>0x20</size>
  800. <access>read-write</access>
  801. <resetValue>0x00000000</resetValue>
  802. <fields>
  803. <field>
  804. <name>MA</name>
  805. <description>Memory address</description>
  806. <bitOffset>0</bitOffset>
  807. <bitWidth>32</bitWidth>
  808. </field>
  809. </fields>
  810. </register>
  811. <register>
  812. <name>CCR4</name>
  813. <displayName>CCR4</displayName>
  814. <description>channel x configuration register</description>
  815. <addressOffset>0x44</addressOffset>
  816. <size>0x20</size>
  817. <access>read-write</access>
  818. <resetValue>0x00000000</resetValue>
  819. <fields>
  820. <field>
  821. <name>MEM2MEM</name>
  822. <description>Memory to memory mode</description>
  823. <bitOffset>14</bitOffset>
  824. <bitWidth>1</bitWidth>
  825. </field>
  826. <field>
  827. <name>PL</name>
  828. <description>Channel priority level</description>
  829. <bitOffset>12</bitOffset>
  830. <bitWidth>2</bitWidth>
  831. </field>
  832. <field>
  833. <name>MSIZE</name>
  834. <description>Memory size</description>
  835. <bitOffset>10</bitOffset>
  836. <bitWidth>2</bitWidth>
  837. </field>
  838. <field>
  839. <name>PSIZE</name>
  840. <description>Peripheral size</description>
  841. <bitOffset>8</bitOffset>
  842. <bitWidth>2</bitWidth>
  843. </field>
  844. <field>
  845. <name>MINC</name>
  846. <description>Memory increment mode</description>
  847. <bitOffset>7</bitOffset>
  848. <bitWidth>1</bitWidth>
  849. </field>
  850. <field>
  851. <name>PINC</name>
  852. <description>Peripheral increment mode</description>
  853. <bitOffset>6</bitOffset>
  854. <bitWidth>1</bitWidth>
  855. </field>
  856. <field>
  857. <name>CIRC</name>
  858. <description>Circular mode</description>
  859. <bitOffset>5</bitOffset>
  860. <bitWidth>1</bitWidth>
  861. </field>
  862. <field>
  863. <name>DIR</name>
  864. <description>Data transfer direction</description>
  865. <bitOffset>4</bitOffset>
  866. <bitWidth>1</bitWidth>
  867. </field>
  868. <field>
  869. <name>TEIE</name>
  870. <description>Transfer error interrupt enable</description>
  871. <bitOffset>3</bitOffset>
  872. <bitWidth>1</bitWidth>
  873. </field>
  874. <field>
  875. <name>HTIE</name>
  876. <description>Half transfer interrupt enable</description>
  877. <bitOffset>2</bitOffset>
  878. <bitWidth>1</bitWidth>
  879. </field>
  880. <field>
  881. <name>TCIE</name>
  882. <description>Transfer complete interrupt enable</description>
  883. <bitOffset>1</bitOffset>
  884. <bitWidth>1</bitWidth>
  885. </field>
  886. <field>
  887. <name>EN</name>
  888. <description>Channel enable</description>
  889. <bitOffset>0</bitOffset>
  890. <bitWidth>1</bitWidth>
  891. </field>
  892. </fields>
  893. </register>
  894. <register>
  895. <name>CNDTR4</name>
  896. <displayName>CNDTR4</displayName>
  897. <description>channel x number of data register</description>
  898. <addressOffset>0x48</addressOffset>
  899. <size>0x20</size>
  900. <access>read-write</access>
  901. <resetValue>0x00000000</resetValue>
  902. <fields>
  903. <field>
  904. <name>NDT</name>
  905. <description>Number of data to transfer</description>
  906. <bitOffset>0</bitOffset>
  907. <bitWidth>16</bitWidth>
  908. </field>
  909. </fields>
  910. </register>
  911. <register>
  912. <name>CPAR4</name>
  913. <displayName>CPAR4</displayName>
  914. <description>channel x peripheral address register</description>
  915. <addressOffset>0x4C</addressOffset>
  916. <size>0x20</size>
  917. <access>read-write</access>
  918. <resetValue>0x00000000</resetValue>
  919. <fields>
  920. <field>
  921. <name>PA</name>
  922. <description>Peripheral address</description>
  923. <bitOffset>0</bitOffset>
  924. <bitWidth>32</bitWidth>
  925. </field>
  926. </fields>
  927. </register>
  928. <register>
  929. <name>CMAR4</name>
  930. <displayName>CMAR4</displayName>
  931. <description>channel x memory address register</description>
  932. <addressOffset>0x50</addressOffset>
  933. <size>0x20</size>
  934. <access>read-write</access>
  935. <resetValue>0x00000000</resetValue>
  936. <fields>
  937. <field>
  938. <name>MA</name>
  939. <description>Memory address</description>
  940. <bitOffset>0</bitOffset>
  941. <bitWidth>32</bitWidth>
  942. </field>
  943. </fields>
  944. </register>
  945. <register>
  946. <name>CCR5</name>
  947. <displayName>CCR5</displayName>
  948. <description>channel x configuration register</description>
  949. <addressOffset>0x58</addressOffset>
  950. <size>0x20</size>
  951. <access>read-write</access>
  952. <resetValue>0x00000000</resetValue>
  953. <fields>
  954. <field>
  955. <name>MEM2MEM</name>
  956. <description>Memory to memory mode</description>
  957. <bitOffset>14</bitOffset>
  958. <bitWidth>1</bitWidth>
  959. </field>
  960. <field>
  961. <name>PL</name>
  962. <description>Channel priority level</description>
  963. <bitOffset>12</bitOffset>
  964. <bitWidth>2</bitWidth>
  965. </field>
  966. <field>
  967. <name>MSIZE</name>
  968. <description>Memory size</description>
  969. <bitOffset>10</bitOffset>
  970. <bitWidth>2</bitWidth>
  971. </field>
  972. <field>
  973. <name>PSIZE</name>
  974. <description>Peripheral size</description>
  975. <bitOffset>8</bitOffset>
  976. <bitWidth>2</bitWidth>
  977. </field>
  978. <field>
  979. <name>MINC</name>
  980. <description>Memory increment mode</description>
  981. <bitOffset>7</bitOffset>
  982. <bitWidth>1</bitWidth>
  983. </field>
  984. <field>
  985. <name>PINC</name>
  986. <description>Peripheral increment mode</description>
  987. <bitOffset>6</bitOffset>
  988. <bitWidth>1</bitWidth>
  989. </field>
  990. <field>
  991. <name>CIRC</name>
  992. <description>Circular mode</description>
  993. <bitOffset>5</bitOffset>
  994. <bitWidth>1</bitWidth>
  995. </field>
  996. <field>
  997. <name>DIR</name>
  998. <description>Data transfer direction</description>
  999. <bitOffset>4</bitOffset>
  1000. <bitWidth>1</bitWidth>
  1001. </field>
  1002. <field>
  1003. <name>TEIE</name>
  1004. <description>Transfer error interrupt enable</description>
  1005. <bitOffset>3</bitOffset>
  1006. <bitWidth>1</bitWidth>
  1007. </field>
  1008. <field>
  1009. <name>HTIE</name>
  1010. <description>Half transfer interrupt enable</description>
  1011. <bitOffset>2</bitOffset>
  1012. <bitWidth>1</bitWidth>
  1013. </field>
  1014. <field>
  1015. <name>TCIE</name>
  1016. <description>Transfer complete interrupt enable</description>
  1017. <bitOffset>1</bitOffset>
  1018. <bitWidth>1</bitWidth>
  1019. </field>
  1020. <field>
  1021. <name>EN</name>
  1022. <description>Channel enable</description>
  1023. <bitOffset>0</bitOffset>
  1024. <bitWidth>1</bitWidth>
  1025. </field>
  1026. </fields>
  1027. </register>
  1028. <register>
  1029. <name>CNDTR5</name>
  1030. <displayName>CNDTR5</displayName>
  1031. <description>channel x number of data register</description>
  1032. <addressOffset>0x5C</addressOffset>
  1033. <size>0x20</size>
  1034. <access>read-write</access>
  1035. <resetValue>0x00000000</resetValue>
  1036. <fields>
  1037. <field>
  1038. <name>NDT</name>
  1039. <description>Number of data to transfer</description>
  1040. <bitOffset>0</bitOffset>
  1041. <bitWidth>16</bitWidth>
  1042. </field>
  1043. </fields>
  1044. </register>
  1045. <register>
  1046. <name>CPAR5</name>
  1047. <displayName>CPAR5</displayName>
  1048. <description>channel x peripheral address register</description>
  1049. <addressOffset>0x60</addressOffset>
  1050. <size>0x20</size>
  1051. <access>read-write</access>
  1052. <resetValue>0x00000000</resetValue>
  1053. <fields>
  1054. <field>
  1055. <name>PA</name>
  1056. <description>Peripheral address</description>
  1057. <bitOffset>0</bitOffset>
  1058. <bitWidth>32</bitWidth>
  1059. </field>
  1060. </fields>
  1061. </register>
  1062. <register>
  1063. <name>CMAR5</name>
  1064. <displayName>CMAR5</displayName>
  1065. <description>channel x memory address register</description>
  1066. <addressOffset>0x64</addressOffset>
  1067. <size>0x20</size>
  1068. <access>read-write</access>
  1069. <resetValue>0x00000000</resetValue>
  1070. <fields>
  1071. <field>
  1072. <name>MA</name>
  1073. <description>Memory address</description>
  1074. <bitOffset>0</bitOffset>
  1075. <bitWidth>32</bitWidth>
  1076. </field>
  1077. </fields>
  1078. </register>
  1079. <register>
  1080. <name>CCR6</name>
  1081. <displayName>CCR6</displayName>
  1082. <description>channel x configuration register</description>
  1083. <addressOffset>0x6C</addressOffset>
  1084. <size>0x20</size>
  1085. <access>read-write</access>
  1086. <resetValue>0x00000000</resetValue>
  1087. <fields>
  1088. <field>
  1089. <name>MEM2MEM</name>
  1090. <description>Memory to memory mode</description>
  1091. <bitOffset>14</bitOffset>
  1092. <bitWidth>1</bitWidth>
  1093. </field>
  1094. <field>
  1095. <name>PL</name>
  1096. <description>Channel priority level</description>
  1097. <bitOffset>12</bitOffset>
  1098. <bitWidth>2</bitWidth>
  1099. </field>
  1100. <field>
  1101. <name>MSIZE</name>
  1102. <description>Memory size</description>
  1103. <bitOffset>10</bitOffset>
  1104. <bitWidth>2</bitWidth>
  1105. </field>
  1106. <field>
  1107. <name>PSIZE</name>
  1108. <description>Peripheral size</description>
  1109. <bitOffset>8</bitOffset>
  1110. <bitWidth>2</bitWidth>
  1111. </field>
  1112. <field>
  1113. <name>MINC</name>
  1114. <description>Memory increment mode</description>
  1115. <bitOffset>7</bitOffset>
  1116. <bitWidth>1</bitWidth>
  1117. </field>
  1118. <field>
  1119. <name>PINC</name>
  1120. <description>Peripheral increment mode</description>
  1121. <bitOffset>6</bitOffset>
  1122. <bitWidth>1</bitWidth>
  1123. </field>
  1124. <field>
  1125. <name>CIRC</name>
  1126. <description>Circular mode</description>
  1127. <bitOffset>5</bitOffset>
  1128. <bitWidth>1</bitWidth>
  1129. </field>
  1130. <field>
  1131. <name>DIR</name>
  1132. <description>Data transfer direction</description>
  1133. <bitOffset>4</bitOffset>
  1134. <bitWidth>1</bitWidth>
  1135. </field>
  1136. <field>
  1137. <name>TEIE</name>
  1138. <description>Transfer error interrupt enable</description>
  1139. <bitOffset>3</bitOffset>
  1140. <bitWidth>1</bitWidth>
  1141. </field>
  1142. <field>
  1143. <name>HTIE</name>
  1144. <description>Half transfer interrupt enable</description>
  1145. <bitOffset>2</bitOffset>
  1146. <bitWidth>1</bitWidth>
  1147. </field>
  1148. <field>
  1149. <name>TCIE</name>
  1150. <description>Transfer complete interrupt enable</description>
  1151. <bitOffset>1</bitOffset>
  1152. <bitWidth>1</bitWidth>
  1153. </field>
  1154. <field>
  1155. <name>EN</name>
  1156. <description>Channel enable</description>
  1157. <bitOffset>0</bitOffset>
  1158. <bitWidth>1</bitWidth>
  1159. </field>
  1160. </fields>
  1161. </register>
  1162. <register>
  1163. <name>CNDTR6</name>
  1164. <displayName>CNDTR6</displayName>
  1165. <description>channel x number of data register</description>
  1166. <addressOffset>0x70</addressOffset>
  1167. <size>0x20</size>
  1168. <access>read-write</access>
  1169. <resetValue>0x00000000</resetValue>
  1170. <fields>
  1171. <field>
  1172. <name>NDT</name>
  1173. <description>Number of data to transfer</description>
  1174. <bitOffset>0</bitOffset>
  1175. <bitWidth>16</bitWidth>
  1176. </field>
  1177. </fields>
  1178. </register>
  1179. <register>
  1180. <name>CPAR6</name>
  1181. <displayName>CPAR6</displayName>
  1182. <description>channel x peripheral address register</description>
  1183. <addressOffset>0x74</addressOffset>
  1184. <size>0x20</size>
  1185. <access>read-write</access>
  1186. <resetValue>0x00000000</resetValue>
  1187. <fields>
  1188. <field>
  1189. <name>PA</name>
  1190. <description>Peripheral address</description>
  1191. <bitOffset>0</bitOffset>
  1192. <bitWidth>32</bitWidth>
  1193. </field>
  1194. </fields>
  1195. </register>
  1196. <register>
  1197. <name>CMAR6</name>
  1198. <displayName>CMAR6</displayName>
  1199. <description>channel x memory address register</description>
  1200. <addressOffset>0x78</addressOffset>
  1201. <size>0x20</size>
  1202. <access>read-write</access>
  1203. <resetValue>0x00000000</resetValue>
  1204. <fields>
  1205. <field>
  1206. <name>MA</name>
  1207. <description>Memory address</description>
  1208. <bitOffset>0</bitOffset>
  1209. <bitWidth>32</bitWidth>
  1210. </field>
  1211. </fields>
  1212. </register>
  1213. <register>
  1214. <name>CCR7</name>
  1215. <displayName>CCR7</displayName>
  1216. <description>channel x configuration register</description>
  1217. <addressOffset>0x80</addressOffset>
  1218. <size>0x20</size>
  1219. <access>read-write</access>
  1220. <resetValue>0x00000000</resetValue>
  1221. <fields>
  1222. <field>
  1223. <name>MEM2MEM</name>
  1224. <description>Memory to memory mode</description>
  1225. <bitOffset>14</bitOffset>
  1226. <bitWidth>1</bitWidth>
  1227. </field>
  1228. <field>
  1229. <name>PL</name>
  1230. <description>Channel priority level</description>
  1231. <bitOffset>12</bitOffset>
  1232. <bitWidth>2</bitWidth>
  1233. </field>
  1234. <field>
  1235. <name>MSIZE</name>
  1236. <description>Memory size</description>
  1237. <bitOffset>10</bitOffset>
  1238. <bitWidth>2</bitWidth>
  1239. </field>
  1240. <field>
  1241. <name>PSIZE</name>
  1242. <description>Peripheral size</description>
  1243. <bitOffset>8</bitOffset>
  1244. <bitWidth>2</bitWidth>
  1245. </field>
  1246. <field>
  1247. <name>MINC</name>
  1248. <description>Memory increment mode</description>
  1249. <bitOffset>7</bitOffset>
  1250. <bitWidth>1</bitWidth>
  1251. </field>
  1252. <field>
  1253. <name>PINC</name>
  1254. <description>Peripheral increment mode</description>
  1255. <bitOffset>6</bitOffset>
  1256. <bitWidth>1</bitWidth>
  1257. </field>
  1258. <field>
  1259. <name>CIRC</name>
  1260. <description>Circular mode</description>
  1261. <bitOffset>5</bitOffset>
  1262. <bitWidth>1</bitWidth>
  1263. </field>
  1264. <field>
  1265. <name>DIR</name>
  1266. <description>Data transfer direction</description>
  1267. <bitOffset>4</bitOffset>
  1268. <bitWidth>1</bitWidth>
  1269. </field>
  1270. <field>
  1271. <name>TEIE</name>
  1272. <description>Transfer error interrupt enable</description>
  1273. <bitOffset>3</bitOffset>
  1274. <bitWidth>1</bitWidth>
  1275. </field>
  1276. <field>
  1277. <name>HTIE</name>
  1278. <description>Half transfer interrupt enable</description>
  1279. <bitOffset>2</bitOffset>
  1280. <bitWidth>1</bitWidth>
  1281. </field>
  1282. <field>
  1283. <name>TCIE</name>
  1284. <description>Transfer complete interrupt enable</description>
  1285. <bitOffset>1</bitOffset>
  1286. <bitWidth>1</bitWidth>
  1287. </field>
  1288. <field>
  1289. <name>EN</name>
  1290. <description>Channel enable</description>
  1291. <bitOffset>0</bitOffset>
  1292. <bitWidth>1</bitWidth>
  1293. </field>
  1294. </fields>
  1295. </register>
  1296. <register>
  1297. <name>CNDTR7</name>
  1298. <displayName>CNDTR7</displayName>
  1299. <description>channel x number of data register</description>
  1300. <addressOffset>0x84</addressOffset>
  1301. <size>0x20</size>
  1302. <access>read-write</access>
  1303. <resetValue>0x00000000</resetValue>
  1304. <fields>
  1305. <field>
  1306. <name>NDT</name>
  1307. <description>Number of data to transfer</description>
  1308. <bitOffset>0</bitOffset>
  1309. <bitWidth>16</bitWidth>
  1310. </field>
  1311. </fields>
  1312. </register>
  1313. <register>
  1314. <name>CPAR7</name>
  1315. <displayName>CPAR7</displayName>
  1316. <description>channel x peripheral address register</description>
  1317. <addressOffset>0x88</addressOffset>
  1318. <size>0x20</size>
  1319. <access>read-write</access>
  1320. <resetValue>0x00000000</resetValue>
  1321. <fields>
  1322. <field>
  1323. <name>PA</name>
  1324. <description>Peripheral address</description>
  1325. <bitOffset>0</bitOffset>
  1326. <bitWidth>32</bitWidth>
  1327. </field>
  1328. </fields>
  1329. </register>
  1330. <register>
  1331. <name>CMAR7</name>
  1332. <displayName>CMAR7</displayName>
  1333. <description>channel x memory address register</description>
  1334. <addressOffset>0x8C</addressOffset>
  1335. <size>0x20</size>
  1336. <access>read-write</access>
  1337. <resetValue>0x00000000</resetValue>
  1338. <fields>
  1339. <field>
  1340. <name>MA</name>
  1341. <description>Memory address</description>
  1342. <bitOffset>0</bitOffset>
  1343. <bitWidth>32</bitWidth>
  1344. </field>
  1345. </fields>
  1346. </register>
  1347. <register>
  1348. <name>CSELR</name>
  1349. <displayName>CSELR</displayName>
  1350. <description>channel selection register</description>
  1351. <addressOffset>0xA8</addressOffset>
  1352. <size>0x20</size>
  1353. <access>read-write</access>
  1354. <resetValue>0x00000000</resetValue>
  1355. <fields>
  1356. <field>
  1357. <name>C7S</name>
  1358. <description>DMA channel 7 selection</description>
  1359. <bitOffset>24</bitOffset>
  1360. <bitWidth>4</bitWidth>
  1361. </field>
  1362. <field>
  1363. <name>C6S</name>
  1364. <description>DMA channel 6 selection</description>
  1365. <bitOffset>20</bitOffset>
  1366. <bitWidth>4</bitWidth>
  1367. </field>
  1368. <field>
  1369. <name>C5S</name>
  1370. <description>DMA channel 5 selection</description>
  1371. <bitOffset>16</bitOffset>
  1372. <bitWidth>4</bitWidth>
  1373. </field>
  1374. <field>
  1375. <name>C4S</name>
  1376. <description>DMA channel 4 selection</description>
  1377. <bitOffset>12</bitOffset>
  1378. <bitWidth>4</bitWidth>
  1379. </field>
  1380. <field>
  1381. <name>C3S</name>
  1382. <description>DMA channel 3 selection</description>
  1383. <bitOffset>8</bitOffset>
  1384. <bitWidth>4</bitWidth>
  1385. </field>
  1386. <field>
  1387. <name>C2S</name>
  1388. <description>DMA channel 2 selection</description>
  1389. <bitOffset>4</bitOffset>
  1390. <bitWidth>4</bitWidth>
  1391. </field>
  1392. <field>
  1393. <name>C1S</name>
  1394. <description>DMA channel 1 selection</description>
  1395. <bitOffset>0</bitOffset>
  1396. <bitWidth>4</bitWidth>
  1397. </field>
  1398. </fields>
  1399. </register>
  1400. </registers>
  1401. </peripheral>
  1402. <peripheral>
  1403. <name>CRC</name>
  1404. <description>Cyclic redundancy check calculation unit</description>
  1405. <groupName>CRC</groupName>
  1406. <baseAddress>0x40023000</baseAddress>
  1407. <addressBlock>
  1408. <offset>0x0</offset>
  1409. <size>0x400</size>
  1410. <usage>registers</usage>
  1411. </addressBlock>
  1412. <registers>
  1413. <register>
  1414. <name>DR</name>
  1415. <displayName>DR</displayName>
  1416. <description>Data register</description>
  1417. <addressOffset>0x0</addressOffset>
  1418. <size>0x20</size>
  1419. <access>read-write</access>
  1420. <resetValue>0xFFFFFFFF</resetValue>
  1421. <fields>
  1422. <field>
  1423. <name>DR</name>
  1424. <description>Data register bits</description>
  1425. <bitOffset>0</bitOffset>
  1426. <bitWidth>32</bitWidth>
  1427. </field>
  1428. </fields>
  1429. </register>
  1430. <register>
  1431. <name>IDR</name>
  1432. <displayName>IDR</displayName>
  1433. <description>Independent data register</description>
  1434. <addressOffset>0x4</addressOffset>
  1435. <size>0x20</size>
  1436. <access>read-write</access>
  1437. <resetValue>0x00000000</resetValue>
  1438. <fields>
  1439. <field>
  1440. <name>IDR</name>
  1441. <description>General-purpose 8-bit data register bits</description>
  1442. <bitOffset>0</bitOffset>
  1443. <bitWidth>8</bitWidth>
  1444. </field>
  1445. </fields>
  1446. </register>
  1447. <register>
  1448. <name>CR</name>
  1449. <displayName>CR</displayName>
  1450. <description>Control register</description>
  1451. <addressOffset>0x8</addressOffset>
  1452. <size>0x20</size>
  1453. <resetValue>0x00000000</resetValue>
  1454. <fields>
  1455. <field>
  1456. <name>REV_OUT</name>
  1457. <description>Reverse output data</description>
  1458. <bitOffset>7</bitOffset>
  1459. <bitWidth>1</bitWidth>
  1460. <access>read-write</access>
  1461. </field>
  1462. <field>
  1463. <name>REV_IN</name>
  1464. <description>Reverse input data</description>
  1465. <bitOffset>5</bitOffset>
  1466. <bitWidth>2</bitWidth>
  1467. <access>read-write</access>
  1468. </field>
  1469. <field>
  1470. <name>POLYSIZE</name>
  1471. <description>Polynomial size</description>
  1472. <bitOffset>3</bitOffset>
  1473. <bitWidth>2</bitWidth>
  1474. <access>read-write</access>
  1475. </field>
  1476. <field>
  1477. <name>RESET</name>
  1478. <description>RESET bit</description>
  1479. <bitOffset>0</bitOffset>
  1480. <bitWidth>1</bitWidth>
  1481. <access>write-only</access>
  1482. </field>
  1483. </fields>
  1484. </register>
  1485. <register>
  1486. <name>INIT</name>
  1487. <displayName>INIT</displayName>
  1488. <description>Initial CRC value</description>
  1489. <addressOffset>0x10</addressOffset>
  1490. <size>0x20</size>
  1491. <access>read-write</access>
  1492. <resetValue>0xFFFFFFFF</resetValue>
  1493. <fields>
  1494. <field>
  1495. <name>CRC_INIT</name>
  1496. <description>Programmable initial CRC value</description>
  1497. <bitOffset>0</bitOffset>
  1498. <bitWidth>32</bitWidth>
  1499. </field>
  1500. </fields>
  1501. </register>
  1502. <register>
  1503. <name>POL</name>
  1504. <displayName>POL</displayName>
  1505. <description>polynomial</description>
  1506. <addressOffset>0x14</addressOffset>
  1507. <size>0x20</size>
  1508. <access>read-write</access>
  1509. <resetValue>0x04C11DB7</resetValue>
  1510. <fields>
  1511. <field>
  1512. <name>Polynomialcoefficients</name>
  1513. <description>Programmable polynomial</description>
  1514. <bitOffset>0</bitOffset>
  1515. <bitWidth>32</bitWidth>
  1516. </field>
  1517. </fields>
  1518. </register>
  1519. </registers>
  1520. </peripheral>
  1521. <peripheral>
  1522. <name>GPIOA</name>
  1523. <description>General-purpose I/Os</description>
  1524. <groupName>GPIO</groupName>
  1525. <baseAddress>0x50000000</baseAddress>
  1526. <addressBlock>
  1527. <offset>0x0</offset>
  1528. <size>0x400</size>
  1529. <usage>registers</usage>
  1530. </addressBlock>
  1531. <registers>
  1532. <register>
  1533. <name>MODER</name>
  1534. <displayName>MODER</displayName>
  1535. <description>GPIO port mode register</description>
  1536. <addressOffset>0x0</addressOffset>
  1537. <size>0x20</size>
  1538. <access>read-write</access>
  1539. <resetValue>0xEBFFFCFF</resetValue>
  1540. <fields>
  1541. <field>
  1542. <name>MODE0</name>
  1543. <description>Port x configuration bits (y = 0..15)</description>
  1544. <bitOffset>0</bitOffset>
  1545. <bitWidth>2</bitWidth>
  1546. </field>
  1547. <field>
  1548. <name>MODE1</name>
  1549. <description>Port x configuration bits (y = 0..15)</description>
  1550. <bitOffset>2</bitOffset>
  1551. <bitWidth>2</bitWidth>
  1552. </field>
  1553. <field>
  1554. <name>MODE2</name>
  1555. <description>Port x configuration bits (y = 0..15)</description>
  1556. <bitOffset>4</bitOffset>
  1557. <bitWidth>2</bitWidth>
  1558. </field>
  1559. <field>
  1560. <name>MODE3</name>
  1561. <description>Port x configuration bits (y = 0..15)</description>
  1562. <bitOffset>6</bitOffset>
  1563. <bitWidth>2</bitWidth>
  1564. </field>
  1565. <field>
  1566. <name>MODE4</name>
  1567. <description>Port x configuration bits (y = 0..15)</description>
  1568. <bitOffset>8</bitOffset>
  1569. <bitWidth>2</bitWidth>
  1570. </field>
  1571. <field>
  1572. <name>MODE5</name>
  1573. <description>Port x configuration bits (y = 0..15)</description>
  1574. <bitOffset>10</bitOffset>
  1575. <bitWidth>2</bitWidth>
  1576. </field>
  1577. <field>
  1578. <name>MODE6</name>
  1579. <description>Port x configuration bits (y = 0..15)</description>
  1580. <bitOffset>12</bitOffset>
  1581. <bitWidth>2</bitWidth>
  1582. </field>
  1583. <field>
  1584. <name>MODE7</name>
  1585. <description>Port x configuration bits (y = 0..15)</description>
  1586. <bitOffset>14</bitOffset>
  1587. <bitWidth>2</bitWidth>
  1588. </field>
  1589. <field>
  1590. <name>MODE8</name>
  1591. <description>Port x configuration bits (y = 0..15)</description>
  1592. <bitOffset>16</bitOffset>
  1593. <bitWidth>2</bitWidth>
  1594. </field>
  1595. <field>
  1596. <name>MODE9</name>
  1597. <description>Port x configuration bits (y = 0..15)</description>
  1598. <bitOffset>18</bitOffset>
  1599. <bitWidth>2</bitWidth>
  1600. </field>
  1601. <field>
  1602. <name>MODE10</name>
  1603. <description>Port x configuration bits (y = 0..15)</description>
  1604. <bitOffset>20</bitOffset>
  1605. <bitWidth>2</bitWidth>
  1606. </field>
  1607. <field>
  1608. <name>MODE11</name>
  1609. <description>Port x configuration bits (y = 0..15)</description>
  1610. <bitOffset>22</bitOffset>
  1611. <bitWidth>2</bitWidth>
  1612. </field>
  1613. <field>
  1614. <name>MODE12</name>
  1615. <description>Port x configuration bits (y = 0..15)</description>
  1616. <bitOffset>24</bitOffset>
  1617. <bitWidth>2</bitWidth>
  1618. </field>
  1619. <field>
  1620. <name>MODE13</name>
  1621. <description>Port x configuration bits (y = 0..15)</description>
  1622. <bitOffset>26</bitOffset>
  1623. <bitWidth>2</bitWidth>
  1624. </field>
  1625. <field>
  1626. <name>MODE14</name>
  1627. <description>Port x configuration bits (y = 0..15)</description>
  1628. <bitOffset>28</bitOffset>
  1629. <bitWidth>2</bitWidth>
  1630. </field>
  1631. <field>
  1632. <name>MODE15</name>
  1633. <description>Port x configuration bits (y = 0..15)</description>
  1634. <bitOffset>30</bitOffset>
  1635. <bitWidth>2</bitWidth>
  1636. </field>
  1637. </fields>
  1638. </register>
  1639. <register>
  1640. <name>OTYPER</name>
  1641. <displayName>OTYPER</displayName>
  1642. <description>GPIO port output type register</description>
  1643. <addressOffset>0x4</addressOffset>
  1644. <size>0x20</size>
  1645. <access>read-write</access>
  1646. <resetValue>0x00000000</resetValue>
  1647. <fields>
  1648. <field>
  1649. <name>OT15</name>
  1650. <description>Port x configuration bits (y = 0..15)</description>
  1651. <bitOffset>15</bitOffset>
  1652. <bitWidth>1</bitWidth>
  1653. </field>
  1654. <field>
  1655. <name>OT14</name>
  1656. <description>Port x configuration bits (y = 0..15)</description>
  1657. <bitOffset>14</bitOffset>
  1658. <bitWidth>1</bitWidth>
  1659. </field>
  1660. <field>
  1661. <name>OT13</name>
  1662. <description>Port x configuration bits (y = 0..15)</description>
  1663. <bitOffset>13</bitOffset>
  1664. <bitWidth>1</bitWidth>
  1665. </field>
  1666. <field>
  1667. <name>OT12</name>
  1668. <description>Port x configuration bits (y = 0..15)</description>
  1669. <bitOffset>12</bitOffset>
  1670. <bitWidth>1</bitWidth>
  1671. </field>
  1672. <field>
  1673. <name>OT11</name>
  1674. <description>Port x configuration bits (y = 0..15)</description>
  1675. <bitOffset>11</bitOffset>
  1676. <bitWidth>1</bitWidth>
  1677. </field>
  1678. <field>
  1679. <name>OT10</name>
  1680. <description>Port x configuration bits (y = 0..15)</description>
  1681. <bitOffset>10</bitOffset>
  1682. <bitWidth>1</bitWidth>
  1683. </field>
  1684. <field>
  1685. <name>OT9</name>
  1686. <description>Port x configuration bits (y = 0..15)</description>
  1687. <bitOffset>9</bitOffset>
  1688. <bitWidth>1</bitWidth>
  1689. </field>
  1690. <field>
  1691. <name>OT8</name>
  1692. <description>Port x configuration bits (y = 0..15)</description>
  1693. <bitOffset>8</bitOffset>
  1694. <bitWidth>1</bitWidth>
  1695. </field>
  1696. <field>
  1697. <name>OT7</name>
  1698. <description>Port x configuration bits (y = 0..15)</description>
  1699. <bitOffset>7</bitOffset>
  1700. <bitWidth>1</bitWidth>
  1701. </field>
  1702. <field>
  1703. <name>OT6</name>
  1704. <description>Port x configuration bits (y = 0..15)</description>
  1705. <bitOffset>6</bitOffset>
  1706. <bitWidth>1</bitWidth>
  1707. </field>
  1708. <field>
  1709. <name>OT5</name>
  1710. <description>Port x configuration bits (y = 0..15)</description>
  1711. <bitOffset>5</bitOffset>
  1712. <bitWidth>1</bitWidth>
  1713. </field>
  1714. <field>
  1715. <name>OT4</name>
  1716. <description>Port x configuration bits (y = 0..15)</description>
  1717. <bitOffset>4</bitOffset>
  1718. <bitWidth>1</bitWidth>
  1719. </field>
  1720. <field>
  1721. <name>OT3</name>
  1722. <description>Port x configuration bits (y = 0..15)</description>
  1723. <bitOffset>3</bitOffset>
  1724. <bitWidth>1</bitWidth>
  1725. </field>
  1726. <field>
  1727. <name>OT2</name>
  1728. <description>Port x configuration bits (y = 0..15)</description>
  1729. <bitOffset>2</bitOffset>
  1730. <bitWidth>1</bitWidth>
  1731. </field>
  1732. <field>
  1733. <name>OT1</name>
  1734. <description>Port x configuration bits (y = 0..15)</description>
  1735. <bitOffset>1</bitOffset>
  1736. <bitWidth>1</bitWidth>
  1737. </field>
  1738. <field>
  1739. <name>OT0</name>
  1740. <description>Port x configuration bits (y = 0..15)</description>
  1741. <bitOffset>0</bitOffset>
  1742. <bitWidth>1</bitWidth>
  1743. </field>
  1744. </fields>
  1745. </register>
  1746. <register>
  1747. <name>OSPEEDR</name>
  1748. <displayName>OSPEEDR</displayName>
  1749. <description>GPIO port output speed register</description>
  1750. <addressOffset>0x8</addressOffset>
  1751. <size>0x20</size>
  1752. <access>read-write</access>
  1753. <resetValue>0x00000000</resetValue>
  1754. <fields>
  1755. <field>
  1756. <name>OSPEED15</name>
  1757. <description>Port x configuration bits (y = 0..15)</description>
  1758. <bitOffset>30</bitOffset>
  1759. <bitWidth>2</bitWidth>
  1760. </field>
  1761. <field>
  1762. <name>OSPEED14</name>
  1763. <description>Port x configuration bits (y = 0..15)</description>
  1764. <bitOffset>28</bitOffset>
  1765. <bitWidth>2</bitWidth>
  1766. </field>
  1767. <field>
  1768. <name>OSPEED13</name>
  1769. <description>Port x configuration bits (y = 0..15)</description>
  1770. <bitOffset>26</bitOffset>
  1771. <bitWidth>2</bitWidth>
  1772. </field>
  1773. <field>
  1774. <name>OSPEED12</name>
  1775. <description>Port x configuration bits (y = 0..15)</description>
  1776. <bitOffset>24</bitOffset>
  1777. <bitWidth>2</bitWidth>
  1778. </field>
  1779. <field>
  1780. <name>OSPEED11</name>
  1781. <description>Port x configuration bits (y = 0..15)</description>
  1782. <bitOffset>22</bitOffset>
  1783. <bitWidth>2</bitWidth>
  1784. </field>
  1785. <field>
  1786. <name>OSPEED10</name>
  1787. <description>Port x configuration bits (y = 0..15)</description>
  1788. <bitOffset>20</bitOffset>
  1789. <bitWidth>2</bitWidth>
  1790. </field>
  1791. <field>
  1792. <name>OSPEED9</name>
  1793. <description>Port x configuration bits (y = 0..15)</description>
  1794. <bitOffset>18</bitOffset>
  1795. <bitWidth>2</bitWidth>
  1796. </field>
  1797. <field>
  1798. <name>OSPEED8</name>
  1799. <description>Port x configuration bits (y = 0..15)</description>
  1800. <bitOffset>16</bitOffset>
  1801. <bitWidth>2</bitWidth>
  1802. </field>
  1803. <field>
  1804. <name>OSPEED7</name>
  1805. <description>Port x configuration bits (y = 0..15)</description>
  1806. <bitOffset>14</bitOffset>
  1807. <bitWidth>2</bitWidth>
  1808. </field>
  1809. <field>
  1810. <name>OSPEED6</name>
  1811. <description>Port x configuration bits (y = 0..15)</description>
  1812. <bitOffset>12</bitOffset>
  1813. <bitWidth>2</bitWidth>
  1814. </field>
  1815. <field>
  1816. <name>OSPEED5</name>
  1817. <description>Port x configuration bits (y = 0..15)</description>
  1818. <bitOffset>10</bitOffset>
  1819. <bitWidth>2</bitWidth>
  1820. </field>
  1821. <field>
  1822. <name>OSPEED4</name>
  1823. <description>Port x configuration bits (y = 0..15)</description>
  1824. <bitOffset>8</bitOffset>
  1825. <bitWidth>2</bitWidth>
  1826. </field>
  1827. <field>
  1828. <name>OSPEED3</name>
  1829. <description>Port x configuration bits (y = 0..15)</description>
  1830. <bitOffset>6</bitOffset>
  1831. <bitWidth>2</bitWidth>
  1832. </field>
  1833. <field>
  1834. <name>OSPEED2</name>
  1835. <description>Port x configuration bits (y = 0..15)</description>
  1836. <bitOffset>4</bitOffset>
  1837. <bitWidth>2</bitWidth>
  1838. </field>
  1839. <field>
  1840. <name>OSPEED1</name>
  1841. <description>Port x configuration bits (y = 0..15)</description>
  1842. <bitOffset>2</bitOffset>
  1843. <bitWidth>2</bitWidth>
  1844. </field>
  1845. <field>
  1846. <name>OSPEED0</name>
  1847. <description>Port x configuration bits (y = 0..15)</description>
  1848. <bitOffset>0</bitOffset>
  1849. <bitWidth>2</bitWidth>
  1850. </field>
  1851. </fields>
  1852. </register>
  1853. <register>
  1854. <name>PUPDR</name>
  1855. <displayName>PUPDR</displayName>
  1856. <description>GPIO port pull-up/pull-down register</description>
  1857. <addressOffset>0xC</addressOffset>
  1858. <size>0x20</size>
  1859. <access>read-write</access>
  1860. <resetValue>0x24000000</resetValue>
  1861. <fields>
  1862. <field>
  1863. <name>PUPD15</name>
  1864. <description>Port x configuration bits (y = 0..15)</description>
  1865. <bitOffset>30</bitOffset>
  1866. <bitWidth>2</bitWidth>
  1867. </field>
  1868. <field>
  1869. <name>PUPD14</name>
  1870. <description>Port x configuration bits (y = 0..15)</description>
  1871. <bitOffset>28</bitOffset>
  1872. <bitWidth>2</bitWidth>
  1873. </field>
  1874. <field>
  1875. <name>PUPD13</name>
  1876. <description>Port x configuration bits (y = 0..15)</description>
  1877. <bitOffset>26</bitOffset>
  1878. <bitWidth>2</bitWidth>
  1879. </field>
  1880. <field>
  1881. <name>PUPD12</name>
  1882. <description>Port x configuration bits (y = 0..15)</description>
  1883. <bitOffset>24</bitOffset>
  1884. <bitWidth>2</bitWidth>
  1885. </field>
  1886. <field>
  1887. <name>PUPD11</name>
  1888. <description>Port x configuration bits (y = 0..15)</description>
  1889. <bitOffset>22</bitOffset>
  1890. <bitWidth>2</bitWidth>
  1891. </field>
  1892. <field>
  1893. <name>PUPD10</name>
  1894. <description>Port x configuration bits (y = 0..15)</description>
  1895. <bitOffset>20</bitOffset>
  1896. <bitWidth>2</bitWidth>
  1897. </field>
  1898. <field>
  1899. <name>PUPD9</name>
  1900. <description>Port x configuration bits (y = 0..15)</description>
  1901. <bitOffset>18</bitOffset>
  1902. <bitWidth>2</bitWidth>
  1903. </field>
  1904. <field>
  1905. <name>PUPD8</name>
  1906. <description>Port x configuration bits (y = 0..15)</description>
  1907. <bitOffset>16</bitOffset>
  1908. <bitWidth>2</bitWidth>
  1909. </field>
  1910. <field>
  1911. <name>PUPD7</name>
  1912. <description>Port x configuration bits (y = 0..15)</description>
  1913. <bitOffset>14</bitOffset>
  1914. <bitWidth>2</bitWidth>
  1915. </field>
  1916. <field>
  1917. <name>PUPD6</name>
  1918. <description>Port x configuration bits (y = 0..15)</description>
  1919. <bitOffset>12</bitOffset>
  1920. <bitWidth>2</bitWidth>
  1921. </field>
  1922. <field>
  1923. <name>PUPD5</name>
  1924. <description>Port x configuration bits (y = 0..15)</description>
  1925. <bitOffset>10</bitOffset>
  1926. <bitWidth>2</bitWidth>
  1927. </field>
  1928. <field>
  1929. <name>PUPD4</name>
  1930. <description>Port x configuration bits (y = 0..15)</description>
  1931. <bitOffset>8</bitOffset>
  1932. <bitWidth>2</bitWidth>
  1933. </field>
  1934. <field>
  1935. <name>PUPD3</name>
  1936. <description>Port x configuration bits (y = 0..15)</description>
  1937. <bitOffset>6</bitOffset>
  1938. <bitWidth>2</bitWidth>
  1939. </field>
  1940. <field>
  1941. <name>PUPD2</name>
  1942. <description>Port x configuration bits (y = 0..15)</description>
  1943. <bitOffset>4</bitOffset>
  1944. <bitWidth>2</bitWidth>
  1945. </field>
  1946. <field>
  1947. <name>PUPD1</name>
  1948. <description>Port x configuration bits (y = 0..15)</description>
  1949. <bitOffset>2</bitOffset>
  1950. <bitWidth>2</bitWidth>
  1951. </field>
  1952. <field>
  1953. <name>PUPD0</name>
  1954. <description>Port x configuration bits (y = 0..15)</description>
  1955. <bitOffset>0</bitOffset>
  1956. <bitWidth>2</bitWidth>
  1957. </field>
  1958. </fields>
  1959. </register>
  1960. <register>
  1961. <name>IDR</name>
  1962. <displayName>IDR</displayName>
  1963. <description>GPIO port input data register</description>
  1964. <addressOffset>0x10</addressOffset>
  1965. <size>0x20</size>
  1966. <access>read-only</access>
  1967. <resetValue>0x00000000</resetValue>
  1968. <fields>
  1969. <field>
  1970. <name>ID15</name>
  1971. <description>Port input data bit (y = 0..15)</description>
  1972. <bitOffset>15</bitOffset>
  1973. <bitWidth>1</bitWidth>
  1974. </field>
  1975. <field>
  1976. <name>ID14</name>
  1977. <description>Port input data bit (y = 0..15)</description>
  1978. <bitOffset>14</bitOffset>
  1979. <bitWidth>1</bitWidth>
  1980. </field>
  1981. <field>
  1982. <name>ID13</name>
  1983. <description>Port input data bit (y = 0..15)</description>
  1984. <bitOffset>13</bitOffset>
  1985. <bitWidth>1</bitWidth>
  1986. </field>
  1987. <field>
  1988. <name>ID12</name>
  1989. <description>Port input data bit (y = 0..15)</description>
  1990. <bitOffset>12</bitOffset>
  1991. <bitWidth>1</bitWidth>
  1992. </field>
  1993. <field>
  1994. <name>ID11</name>
  1995. <description>Port input data bit (y = 0..15)</description>
  1996. <bitOffset>11</bitOffset>
  1997. <bitWidth>1</bitWidth>
  1998. </field>
  1999. <field>
  2000. <name>ID10</name>
  2001. <description>Port input data bit (y = 0..15)</description>
  2002. <bitOffset>10</bitOffset>
  2003. <bitWidth>1</bitWidth>
  2004. </field>
  2005. <field>
  2006. <name>ID9</name>
  2007. <description>Port input data bit (y = 0..15)</description>
  2008. <bitOffset>9</bitOffset>
  2009. <bitWidth>1</bitWidth>
  2010. </field>
  2011. <field>
  2012. <name>ID8</name>
  2013. <description>Port input data bit (y = 0..15)</description>
  2014. <bitOffset>8</bitOffset>
  2015. <bitWidth>1</bitWidth>
  2016. </field>
  2017. <field>
  2018. <name>ID7</name>
  2019. <description>Port input data bit (y = 0..15)</description>
  2020. <bitOffset>7</bitOffset>
  2021. <bitWidth>1</bitWidth>
  2022. </field>
  2023. <field>
  2024. <name>ID6</name>
  2025. <description>Port input data bit (y = 0..15)</description>
  2026. <bitOffset>6</bitOffset>
  2027. <bitWidth>1</bitWidth>
  2028. </field>
  2029. <field>
  2030. <name>ID5</name>
  2031. <description>Port input data bit (y = 0..15)</description>
  2032. <bitOffset>5</bitOffset>
  2033. <bitWidth>1</bitWidth>
  2034. </field>
  2035. <field>
  2036. <name>ID4</name>
  2037. <description>Port input data bit (y = 0..15)</description>
  2038. <bitOffset>4</bitOffset>
  2039. <bitWidth>1</bitWidth>
  2040. </field>
  2041. <field>
  2042. <name>ID3</name>
  2043. <description>Port input data bit (y = 0..15)</description>
  2044. <bitOffset>3</bitOffset>
  2045. <bitWidth>1</bitWidth>
  2046. </field>
  2047. <field>
  2048. <name>ID2</name>
  2049. <description>Port input data bit (y = 0..15)</description>
  2050. <bitOffset>2</bitOffset>
  2051. <bitWidth>1</bitWidth>
  2052. </field>
  2053. <field>
  2054. <name>ID1</name>
  2055. <description>Port input data bit (y = 0..15)</description>
  2056. <bitOffset>1</bitOffset>
  2057. <bitWidth>1</bitWidth>
  2058. </field>
  2059. <field>
  2060. <name>ID0</name>
  2061. <description>Port input data bit (y = 0..15)</description>
  2062. <bitOffset>0</bitOffset>
  2063. <bitWidth>1</bitWidth>
  2064. </field>
  2065. </fields>
  2066. </register>
  2067. <register>
  2068. <name>ODR</name>
  2069. <displayName>ODR</displayName>
  2070. <description>GPIO port output data register</description>
  2071. <addressOffset>0x14</addressOffset>
  2072. <size>0x20</size>
  2073. <access>read-write</access>
  2074. <resetValue>0x00000000</resetValue>
  2075. <fields>
  2076. <field>
  2077. <name>OD15</name>
  2078. <description>Port output data bit (y = 0..15)</description>
  2079. <bitOffset>15</bitOffset>
  2080. <bitWidth>1</bitWidth>
  2081. </field>
  2082. <field>
  2083. <name>OD14</name>
  2084. <description>Port output data bit (y = 0..15)</description>
  2085. <bitOffset>14</bitOffset>
  2086. <bitWidth>1</bitWidth>
  2087. </field>
  2088. <field>
  2089. <name>OD13</name>
  2090. <description>Port output data bit (y = 0..15)</description>
  2091. <bitOffset>13</bitOffset>
  2092. <bitWidth>1</bitWidth>
  2093. </field>
  2094. <field>
  2095. <name>OD12</name>
  2096. <description>Port output data bit (y = 0..15)</description>
  2097. <bitOffset>12</bitOffset>
  2098. <bitWidth>1</bitWidth>
  2099. </field>
  2100. <field>
  2101. <name>OD11</name>
  2102. <description>Port output data bit (y = 0..15)</description>
  2103. <bitOffset>11</bitOffset>
  2104. <bitWidth>1</bitWidth>
  2105. </field>
  2106. <field>
  2107. <name>OD10</name>
  2108. <description>Port output data bit (y = 0..15)</description>
  2109. <bitOffset>10</bitOffset>
  2110. <bitWidth>1</bitWidth>
  2111. </field>
  2112. <field>
  2113. <name>OD9</name>
  2114. <description>Port output data bit (y = 0..15)</description>
  2115. <bitOffset>9</bitOffset>
  2116. <bitWidth>1</bitWidth>
  2117. </field>
  2118. <field>
  2119. <name>OD8</name>
  2120. <description>Port output data bit (y = 0..15)</description>
  2121. <bitOffset>8</bitOffset>
  2122. <bitWidth>1</bitWidth>
  2123. </field>
  2124. <field>
  2125. <name>OD7</name>
  2126. <description>Port output data bit (y = 0..15)</description>
  2127. <bitOffset>7</bitOffset>
  2128. <bitWidth>1</bitWidth>
  2129. </field>
  2130. <field>
  2131. <name>OD6</name>
  2132. <description>Port output data bit (y = 0..15)</description>
  2133. <bitOffset>6</bitOffset>
  2134. <bitWidth>1</bitWidth>
  2135. </field>
  2136. <field>
  2137. <name>OD5</name>
  2138. <description>Port output data bit (y = 0..15)</description>
  2139. <bitOffset>5</bitOffset>
  2140. <bitWidth>1</bitWidth>
  2141. </field>
  2142. <field>
  2143. <name>OD4</name>
  2144. <description>Port output data bit (y = 0..15)</description>
  2145. <bitOffset>4</bitOffset>
  2146. <bitWidth>1</bitWidth>
  2147. </field>
  2148. <field>
  2149. <name>OD3</name>
  2150. <description>Port output data bit (y = 0..15)</description>
  2151. <bitOffset>3</bitOffset>
  2152. <bitWidth>1</bitWidth>
  2153. </field>
  2154. <field>
  2155. <name>OD2</name>
  2156. <description>Port output data bit (y = 0..15)</description>
  2157. <bitOffset>2</bitOffset>
  2158. <bitWidth>1</bitWidth>
  2159. </field>
  2160. <field>
  2161. <name>OD1</name>
  2162. <description>Port output data bit (y = 0..15)</description>
  2163. <bitOffset>1</bitOffset>
  2164. <bitWidth>1</bitWidth>
  2165. </field>
  2166. <field>
  2167. <name>OD0</name>
  2168. <description>Port output data bit (y = 0..15)</description>
  2169. <bitOffset>0</bitOffset>
  2170. <bitWidth>1</bitWidth>
  2171. </field>
  2172. </fields>
  2173. </register>
  2174. <register>
  2175. <name>BSRR</name>
  2176. <displayName>BSRR</displayName>
  2177. <description>GPIO port bit set/reset register</description>
  2178. <addressOffset>0x18</addressOffset>
  2179. <size>0x20</size>
  2180. <access>write-only</access>
  2181. <resetValue>0x00000000</resetValue>
  2182. <fields>
  2183. <field>
  2184. <name>BR15</name>
  2185. <description>Port x reset bit y (y = 0..15)</description>
  2186. <bitOffset>31</bitOffset>
  2187. <bitWidth>1</bitWidth>
  2188. </field>
  2189. <field>
  2190. <name>BR14</name>
  2191. <description>Port x reset bit y (y = 0..15)</description>
  2192. <bitOffset>30</bitOffset>
  2193. <bitWidth>1</bitWidth>
  2194. </field>
  2195. <field>
  2196. <name>BR13</name>
  2197. <description>Port x reset bit y (y = 0..15)</description>
  2198. <bitOffset>29</bitOffset>
  2199. <bitWidth>1</bitWidth>
  2200. </field>
  2201. <field>
  2202. <name>BR12</name>
  2203. <description>Port x reset bit y (y = 0..15)</description>
  2204. <bitOffset>28</bitOffset>
  2205. <bitWidth>1</bitWidth>
  2206. </field>
  2207. <field>
  2208. <name>BR11</name>
  2209. <description>Port x reset bit y (y = 0..15)</description>
  2210. <bitOffset>27</bitOffset>
  2211. <bitWidth>1</bitWidth>
  2212. </field>
  2213. <field>
  2214. <name>BR10</name>
  2215. <description>Port x reset bit y (y = 0..15)</description>
  2216. <bitOffset>26</bitOffset>
  2217. <bitWidth>1</bitWidth>
  2218. </field>
  2219. <field>
  2220. <name>BR9</name>
  2221. <description>Port x reset bit y (y = 0..15)</description>
  2222. <bitOffset>25</bitOffset>
  2223. <bitWidth>1</bitWidth>
  2224. </field>
  2225. <field>
  2226. <name>BR8</name>
  2227. <description>Port x reset bit y (y = 0..15)</description>
  2228. <bitOffset>24</bitOffset>
  2229. <bitWidth>1</bitWidth>
  2230. </field>
  2231. <field>
  2232. <name>BR7</name>
  2233. <description>Port x reset bit y (y = 0..15)</description>
  2234. <bitOffset>23</bitOffset>
  2235. <bitWidth>1</bitWidth>
  2236. </field>
  2237. <field>
  2238. <name>BR6</name>
  2239. <description>Port x reset bit y (y = 0..15)</description>
  2240. <bitOffset>22</bitOffset>
  2241. <bitWidth>1</bitWidth>
  2242. </field>
  2243. <field>
  2244. <name>BR5</name>
  2245. <description>Port x reset bit y (y = 0..15)</description>
  2246. <bitOffset>21</bitOffset>
  2247. <bitWidth>1</bitWidth>
  2248. </field>
  2249. <field>
  2250. <name>BR4</name>
  2251. <description>Port x reset bit y (y = 0..15)</description>
  2252. <bitOffset>20</bitOffset>
  2253. <bitWidth>1</bitWidth>
  2254. </field>
  2255. <field>
  2256. <name>BR3</name>
  2257. <description>Port x reset bit y (y = 0..15)</description>
  2258. <bitOffset>19</bitOffset>
  2259. <bitWidth>1</bitWidth>
  2260. </field>
  2261. <field>
  2262. <name>BR2</name>
  2263. <description>Port x reset bit y (y = 0..15)</description>
  2264. <bitOffset>18</bitOffset>
  2265. <bitWidth>1</bitWidth>
  2266. </field>
  2267. <field>
  2268. <name>BR1</name>
  2269. <description>Port x reset bit y (y = 0..15)</description>
  2270. <bitOffset>17</bitOffset>
  2271. <bitWidth>1</bitWidth>
  2272. </field>
  2273. <field>
  2274. <name>BR0</name>
  2275. <description>Port x reset bit y (y = 0..15)</description>
  2276. <bitOffset>16</bitOffset>
  2277. <bitWidth>1</bitWidth>
  2278. </field>
  2279. <field>
  2280. <name>BS15</name>
  2281. <description>Port x set bit y (y= 0..15)</description>
  2282. <bitOffset>15</bitOffset>
  2283. <bitWidth>1</bitWidth>
  2284. </field>
  2285. <field>
  2286. <name>BS14</name>
  2287. <description>Port x set bit y (y= 0..15)</description>
  2288. <bitOffset>14</bitOffset>
  2289. <bitWidth>1</bitWidth>
  2290. </field>
  2291. <field>
  2292. <name>BS13</name>
  2293. <description>Port x set bit y (y= 0..15)</description>
  2294. <bitOffset>13</bitOffset>
  2295. <bitWidth>1</bitWidth>
  2296. </field>
  2297. <field>
  2298. <name>BS12</name>
  2299. <description>Port x set bit y (y= 0..15)</description>
  2300. <bitOffset>12</bitOffset>
  2301. <bitWidth>1</bitWidth>
  2302. </field>
  2303. <field>
  2304. <name>BS11</name>
  2305. <description>Port x set bit y (y= 0..15)</description>
  2306. <bitOffset>11</bitOffset>
  2307. <bitWidth>1</bitWidth>
  2308. </field>
  2309. <field>
  2310. <name>BS10</name>
  2311. <description>Port x set bit y (y= 0..15)</description>
  2312. <bitOffset>10</bitOffset>
  2313. <bitWidth>1</bitWidth>
  2314. </field>
  2315. <field>
  2316. <name>BS9</name>
  2317. <description>Port x set bit y (y= 0..15)</description>
  2318. <bitOffset>9</bitOffset>
  2319. <bitWidth>1</bitWidth>
  2320. </field>
  2321. <field>
  2322. <name>BS8</name>
  2323. <description>Port x set bit y (y= 0..15)</description>
  2324. <bitOffset>8</bitOffset>
  2325. <bitWidth>1</bitWidth>
  2326. </field>
  2327. <field>
  2328. <name>BS7</name>
  2329. <description>Port x set bit y (y= 0..15)</description>
  2330. <bitOffset>7</bitOffset>
  2331. <bitWidth>1</bitWidth>
  2332. </field>
  2333. <field>
  2334. <name>BS6</name>
  2335. <description>Port x set bit y (y= 0..15)</description>
  2336. <bitOffset>6</bitOffset>
  2337. <bitWidth>1</bitWidth>
  2338. </field>
  2339. <field>
  2340. <name>BS5</name>
  2341. <description>Port x set bit y (y= 0..15)</description>
  2342. <bitOffset>5</bitOffset>
  2343. <bitWidth>1</bitWidth>
  2344. </field>
  2345. <field>
  2346. <name>BS4</name>
  2347. <description>Port x set bit y (y= 0..15)</description>
  2348. <bitOffset>4</bitOffset>
  2349. <bitWidth>1</bitWidth>
  2350. </field>
  2351. <field>
  2352. <name>BS3</name>
  2353. <description>Port x set bit y (y= 0..15)</description>
  2354. <bitOffset>3</bitOffset>
  2355. <bitWidth>1</bitWidth>
  2356. </field>
  2357. <field>
  2358. <name>BS2</name>
  2359. <description>Port x set bit y (y= 0..15)</description>
  2360. <bitOffset>2</bitOffset>
  2361. <bitWidth>1</bitWidth>
  2362. </field>
  2363. <field>
  2364. <name>BS1</name>
  2365. <description>Port x set bit y (y= 0..15)</description>
  2366. <bitOffset>1</bitOffset>
  2367. <bitWidth>1</bitWidth>
  2368. </field>
  2369. <field>
  2370. <name>BS0</name>
  2371. <description>Port x set bit y (y= 0..15)</description>
  2372. <bitOffset>0</bitOffset>
  2373. <bitWidth>1</bitWidth>
  2374. </field>
  2375. </fields>
  2376. </register>
  2377. <register>
  2378. <name>LCKR</name>
  2379. <displayName>LCKR</displayName>
  2380. <description>GPIO port configuration lock register</description>
  2381. <addressOffset>0x1C</addressOffset>
  2382. <size>0x20</size>
  2383. <access>read-write</access>
  2384. <resetValue>0x00000000</resetValue>
  2385. <fields>
  2386. <field>
  2387. <name>LCKK</name>
  2388. <description>Port x lock bit y (y= 0..15)</description>
  2389. <bitOffset>16</bitOffset>
  2390. <bitWidth>1</bitWidth>
  2391. </field>
  2392. <field>
  2393. <name>LCK15</name>
  2394. <description>Port x lock bit y (y= 0..15)</description>
  2395. <bitOffset>15</bitOffset>
  2396. <bitWidth>1</bitWidth>
  2397. </field>
  2398. <field>
  2399. <name>LCK14</name>
  2400. <description>Port x lock bit y (y= 0..15)</description>
  2401. <bitOffset>14</bitOffset>
  2402. <bitWidth>1</bitWidth>
  2403. </field>
  2404. <field>
  2405. <name>LCK13</name>
  2406. <description>Port x lock bit y (y= 0..15)</description>
  2407. <bitOffset>13</bitOffset>
  2408. <bitWidth>1</bitWidth>
  2409. </field>
  2410. <field>
  2411. <name>LCK12</name>
  2412. <description>Port x lock bit y (y= 0..15)</description>
  2413. <bitOffset>12</bitOffset>
  2414. <bitWidth>1</bitWidth>
  2415. </field>
  2416. <field>
  2417. <name>LCK11</name>
  2418. <description>Port x lock bit y (y= 0..15)</description>
  2419. <bitOffset>11</bitOffset>
  2420. <bitWidth>1</bitWidth>
  2421. </field>
  2422. <field>
  2423. <name>LCK10</name>
  2424. <description>Port x lock bit y (y= 0..15)</description>
  2425. <bitOffset>10</bitOffset>
  2426. <bitWidth>1</bitWidth>
  2427. </field>
  2428. <field>
  2429. <name>LCK9</name>
  2430. <description>Port x lock bit y (y= 0..15)</description>
  2431. <bitOffset>9</bitOffset>
  2432. <bitWidth>1</bitWidth>
  2433. </field>
  2434. <field>
  2435. <name>LCK8</name>
  2436. <description>Port x lock bit y (y= 0..15)</description>
  2437. <bitOffset>8</bitOffset>
  2438. <bitWidth>1</bitWidth>
  2439. </field>
  2440. <field>
  2441. <name>LCK7</name>
  2442. <description>Port x lock bit y (y= 0..15)</description>
  2443. <bitOffset>7</bitOffset>
  2444. <bitWidth>1</bitWidth>
  2445. </field>
  2446. <field>
  2447. <name>LCK6</name>
  2448. <description>Port x lock bit y (y= 0..15)</description>
  2449. <bitOffset>6</bitOffset>
  2450. <bitWidth>1</bitWidth>
  2451. </field>
  2452. <field>
  2453. <name>LCK5</name>
  2454. <description>Port x lock bit y (y= 0..15)</description>
  2455. <bitOffset>5</bitOffset>
  2456. <bitWidth>1</bitWidth>
  2457. </field>
  2458. <field>
  2459. <name>LCK4</name>
  2460. <description>Port x lock bit y (y= 0..15)</description>
  2461. <bitOffset>4</bitOffset>
  2462. <bitWidth>1</bitWidth>
  2463. </field>
  2464. <field>
  2465. <name>LCK3</name>
  2466. <description>Port x lock bit y (y= 0..15)</description>
  2467. <bitOffset>3</bitOffset>
  2468. <bitWidth>1</bitWidth>
  2469. </field>
  2470. <field>
  2471. <name>LCK2</name>
  2472. <description>Port x lock bit y (y= 0..15)</description>
  2473. <bitOffset>2</bitOffset>
  2474. <bitWidth>1</bitWidth>
  2475. </field>
  2476. <field>
  2477. <name>LCK1</name>
  2478. <description>Port x lock bit y (y= 0..15)</description>
  2479. <bitOffset>1</bitOffset>
  2480. <bitWidth>1</bitWidth>
  2481. </field>
  2482. <field>
  2483. <name>LCK0</name>
  2484. <description>Port x lock bit y (y= 0..15)</description>
  2485. <bitOffset>0</bitOffset>
  2486. <bitWidth>1</bitWidth>
  2487. </field>
  2488. </fields>
  2489. </register>
  2490. <register>
  2491. <name>AFRL</name>
  2492. <displayName>AFRL</displayName>
  2493. <description>GPIO alternate function low register</description>
  2494. <addressOffset>0x20</addressOffset>
  2495. <size>0x20</size>
  2496. <access>read-write</access>
  2497. <resetValue>0x00000000</resetValue>
  2498. <fields>
  2499. <field>
  2500. <name>AFSEL7</name>
  2501. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2502. <bitOffset>28</bitOffset>
  2503. <bitWidth>4</bitWidth>
  2504. </field>
  2505. <field>
  2506. <name>AFSEL6</name>
  2507. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2508. <bitOffset>24</bitOffset>
  2509. <bitWidth>4</bitWidth>
  2510. </field>
  2511. <field>
  2512. <name>AFSEL5</name>
  2513. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2514. <bitOffset>20</bitOffset>
  2515. <bitWidth>4</bitWidth>
  2516. </field>
  2517. <field>
  2518. <name>AFSEL4</name>
  2519. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2520. <bitOffset>16</bitOffset>
  2521. <bitWidth>4</bitWidth>
  2522. </field>
  2523. <field>
  2524. <name>AFSEL3</name>
  2525. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2526. <bitOffset>12</bitOffset>
  2527. <bitWidth>4</bitWidth>
  2528. </field>
  2529. <field>
  2530. <name>AFSEL2</name>
  2531. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2532. <bitOffset>8</bitOffset>
  2533. <bitWidth>4</bitWidth>
  2534. </field>
  2535. <field>
  2536. <name>AFSEL1</name>
  2537. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2538. <bitOffset>4</bitOffset>
  2539. <bitWidth>4</bitWidth>
  2540. </field>
  2541. <field>
  2542. <name>AFSEL0</name>
  2543. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  2544. <bitOffset>0</bitOffset>
  2545. <bitWidth>4</bitWidth>
  2546. </field>
  2547. </fields>
  2548. </register>
  2549. <register>
  2550. <name>AFRH</name>
  2551. <displayName>AFRH</displayName>
  2552. <description>GPIO alternate function high register</description>
  2553. <addressOffset>0x24</addressOffset>
  2554. <size>0x20</size>
  2555. <access>read-write</access>
  2556. <resetValue>0x00000000</resetValue>
  2557. <fields>
  2558. <field>
  2559. <name>AFSEL15</name>
  2560. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2561. <bitOffset>28</bitOffset>
  2562. <bitWidth>4</bitWidth>
  2563. </field>
  2564. <field>
  2565. <name>AFSEL14</name>
  2566. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2567. <bitOffset>24</bitOffset>
  2568. <bitWidth>4</bitWidth>
  2569. </field>
  2570. <field>
  2571. <name>AFSEL13</name>
  2572. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2573. <bitOffset>20</bitOffset>
  2574. <bitWidth>4</bitWidth>
  2575. </field>
  2576. <field>
  2577. <name>AFSEL12</name>
  2578. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2579. <bitOffset>16</bitOffset>
  2580. <bitWidth>4</bitWidth>
  2581. </field>
  2582. <field>
  2583. <name>AFSEL11</name>
  2584. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2585. <bitOffset>12</bitOffset>
  2586. <bitWidth>4</bitWidth>
  2587. </field>
  2588. <field>
  2589. <name>AFSEL10</name>
  2590. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2591. <bitOffset>8</bitOffset>
  2592. <bitWidth>4</bitWidth>
  2593. </field>
  2594. <field>
  2595. <name>AFSEL9</name>
  2596. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2597. <bitOffset>4</bitOffset>
  2598. <bitWidth>4</bitWidth>
  2599. </field>
  2600. <field>
  2601. <name>AFSEL8</name>
  2602. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  2603. <bitOffset>0</bitOffset>
  2604. <bitWidth>4</bitWidth>
  2605. </field>
  2606. </fields>
  2607. </register>
  2608. <register>
  2609. <name>BRR</name>
  2610. <displayName>BRR</displayName>
  2611. <description>GPIO port bit reset register</description>
  2612. <addressOffset>0x28</addressOffset>
  2613. <size>0x20</size>
  2614. <access>write-only</access>
  2615. <resetValue>0x00000000</resetValue>
  2616. <fields>
  2617. <field>
  2618. <name>BR15</name>
  2619. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2620. <bitOffset>15</bitOffset>
  2621. <bitWidth>1</bitWidth>
  2622. </field>
  2623. <field>
  2624. <name>BR14</name>
  2625. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2626. <bitOffset>14</bitOffset>
  2627. <bitWidth>1</bitWidth>
  2628. </field>
  2629. <field>
  2630. <name>BR13</name>
  2631. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2632. <bitOffset>13</bitOffset>
  2633. <bitWidth>1</bitWidth>
  2634. </field>
  2635. <field>
  2636. <name>BR12</name>
  2637. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2638. <bitOffset>12</bitOffset>
  2639. <bitWidth>1</bitWidth>
  2640. </field>
  2641. <field>
  2642. <name>BR11</name>
  2643. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2644. <bitOffset>11</bitOffset>
  2645. <bitWidth>1</bitWidth>
  2646. </field>
  2647. <field>
  2648. <name>BR10</name>
  2649. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2650. <bitOffset>10</bitOffset>
  2651. <bitWidth>1</bitWidth>
  2652. </field>
  2653. <field>
  2654. <name>BR9</name>
  2655. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2656. <bitOffset>9</bitOffset>
  2657. <bitWidth>1</bitWidth>
  2658. </field>
  2659. <field>
  2660. <name>BR8</name>
  2661. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2662. <bitOffset>8</bitOffset>
  2663. <bitWidth>1</bitWidth>
  2664. </field>
  2665. <field>
  2666. <name>BR7</name>
  2667. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2668. <bitOffset>7</bitOffset>
  2669. <bitWidth>1</bitWidth>
  2670. </field>
  2671. <field>
  2672. <name>BR6</name>
  2673. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2674. <bitOffset>6</bitOffset>
  2675. <bitWidth>1</bitWidth>
  2676. </field>
  2677. <field>
  2678. <name>BR5</name>
  2679. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2680. <bitOffset>5</bitOffset>
  2681. <bitWidth>1</bitWidth>
  2682. </field>
  2683. <field>
  2684. <name>BR4</name>
  2685. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2686. <bitOffset>4</bitOffset>
  2687. <bitWidth>1</bitWidth>
  2688. </field>
  2689. <field>
  2690. <name>BR3</name>
  2691. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2692. <bitOffset>3</bitOffset>
  2693. <bitWidth>1</bitWidth>
  2694. </field>
  2695. <field>
  2696. <name>BR2</name>
  2697. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2698. <bitOffset>2</bitOffset>
  2699. <bitWidth>1</bitWidth>
  2700. </field>
  2701. <field>
  2702. <name>BR1</name>
  2703. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2704. <bitOffset>1</bitOffset>
  2705. <bitWidth>1</bitWidth>
  2706. </field>
  2707. <field>
  2708. <name>BR0</name>
  2709. <description>Port x Reset bit y (y= 0 .. 15)</description>
  2710. <bitOffset>0</bitOffset>
  2711. <bitWidth>1</bitWidth>
  2712. </field>
  2713. </fields>
  2714. </register>
  2715. </registers>
  2716. </peripheral>
  2717. <peripheral>
  2718. <name>GPIOB</name>
  2719. <description>General-purpose I/Os</description>
  2720. <groupName>GPIO</groupName>
  2721. <baseAddress>0x50000400</baseAddress>
  2722. <addressBlock>
  2723. <offset>0x0</offset>
  2724. <size>0x400</size>
  2725. <usage>registers</usage>
  2726. </addressBlock>
  2727. <registers>
  2728. <register>
  2729. <name>MODER</name>
  2730. <displayName>MODER</displayName>
  2731. <description>GPIO port mode register</description>
  2732. <addressOffset>0x0</addressOffset>
  2733. <size>0x20</size>
  2734. <access>read-write</access>
  2735. <resetValue>0xFFFFFFFF</resetValue>
  2736. <fields>
  2737. <field>
  2738. <name>MODE15</name>
  2739. <description>Port x configuration bits (y = 0..15)</description>
  2740. <bitOffset>30</bitOffset>
  2741. <bitWidth>2</bitWidth>
  2742. </field>
  2743. <field>
  2744. <name>MODE14</name>
  2745. <description>Port x configuration bits (y = 0..15)</description>
  2746. <bitOffset>28</bitOffset>
  2747. <bitWidth>2</bitWidth>
  2748. </field>
  2749. <field>
  2750. <name>MODE13</name>
  2751. <description>Port x configuration bits (y = 0..15)</description>
  2752. <bitOffset>26</bitOffset>
  2753. <bitWidth>2</bitWidth>
  2754. </field>
  2755. <field>
  2756. <name>MODE12</name>
  2757. <description>Port x configuration bits (y = 0..15)</description>
  2758. <bitOffset>24</bitOffset>
  2759. <bitWidth>2</bitWidth>
  2760. </field>
  2761. <field>
  2762. <name>MODE11</name>
  2763. <description>Port x configuration bits (y = 0..15)</description>
  2764. <bitOffset>22</bitOffset>
  2765. <bitWidth>2</bitWidth>
  2766. </field>
  2767. <field>
  2768. <name>MODE10</name>
  2769. <description>Port x configuration bits (y = 0..15)</description>
  2770. <bitOffset>20</bitOffset>
  2771. <bitWidth>2</bitWidth>
  2772. </field>
  2773. <field>
  2774. <name>MODE9</name>
  2775. <description>Port x configuration bits (y = 0..15)</description>
  2776. <bitOffset>18</bitOffset>
  2777. <bitWidth>2</bitWidth>
  2778. </field>
  2779. <field>
  2780. <name>MODE8</name>
  2781. <description>Port x configuration bits (y = 0..15)</description>
  2782. <bitOffset>16</bitOffset>
  2783. <bitWidth>2</bitWidth>
  2784. </field>
  2785. <field>
  2786. <name>MODE7</name>
  2787. <description>Port x configuration bits (y = 0..15)</description>
  2788. <bitOffset>14</bitOffset>
  2789. <bitWidth>2</bitWidth>
  2790. </field>
  2791. <field>
  2792. <name>MODE6</name>
  2793. <description>Port x configuration bits (y = 0..15)</description>
  2794. <bitOffset>12</bitOffset>
  2795. <bitWidth>2</bitWidth>
  2796. </field>
  2797. <field>
  2798. <name>MODE5</name>
  2799. <description>Port x configuration bits (y = 0..15)</description>
  2800. <bitOffset>10</bitOffset>
  2801. <bitWidth>2</bitWidth>
  2802. </field>
  2803. <field>
  2804. <name>MODE4</name>
  2805. <description>Port x configuration bits (y = 0..15)</description>
  2806. <bitOffset>8</bitOffset>
  2807. <bitWidth>2</bitWidth>
  2808. </field>
  2809. <field>
  2810. <name>MODE3</name>
  2811. <description>Port x configuration bits (y = 0..15)</description>
  2812. <bitOffset>6</bitOffset>
  2813. <bitWidth>2</bitWidth>
  2814. </field>
  2815. <field>
  2816. <name>MODE2</name>
  2817. <description>Port x configuration bits (y = 0..15)</description>
  2818. <bitOffset>4</bitOffset>
  2819. <bitWidth>2</bitWidth>
  2820. </field>
  2821. <field>
  2822. <name>MODE1</name>
  2823. <description>Port x configuration bits (y = 0..15)</description>
  2824. <bitOffset>2</bitOffset>
  2825. <bitWidth>2</bitWidth>
  2826. </field>
  2827. <field>
  2828. <name>MODE0</name>
  2829. <description>Port x configuration bits (y = 0..15)</description>
  2830. <bitOffset>0</bitOffset>
  2831. <bitWidth>2</bitWidth>
  2832. </field>
  2833. </fields>
  2834. </register>
  2835. <register>
  2836. <name>OTYPER</name>
  2837. <displayName>OTYPER</displayName>
  2838. <description>GPIO port output type register</description>
  2839. <addressOffset>0x4</addressOffset>
  2840. <size>0x20</size>
  2841. <access>read-write</access>
  2842. <resetValue>0x00000000</resetValue>
  2843. <fields>
  2844. <field>
  2845. <name>OT15</name>
  2846. <description>Port x configuration bits (y = 0..15)</description>
  2847. <bitOffset>15</bitOffset>
  2848. <bitWidth>1</bitWidth>
  2849. </field>
  2850. <field>
  2851. <name>OT14</name>
  2852. <description>Port x configuration bits (y = 0..15)</description>
  2853. <bitOffset>14</bitOffset>
  2854. <bitWidth>1</bitWidth>
  2855. </field>
  2856. <field>
  2857. <name>OT13</name>
  2858. <description>Port x configuration bits (y = 0..15)</description>
  2859. <bitOffset>13</bitOffset>
  2860. <bitWidth>1</bitWidth>
  2861. </field>
  2862. <field>
  2863. <name>OT12</name>
  2864. <description>Port x configuration bits (y = 0..15)</description>
  2865. <bitOffset>12</bitOffset>
  2866. <bitWidth>1</bitWidth>
  2867. </field>
  2868. <field>
  2869. <name>OT11</name>
  2870. <description>Port x configuration bits (y = 0..15)</description>
  2871. <bitOffset>11</bitOffset>
  2872. <bitWidth>1</bitWidth>
  2873. </field>
  2874. <field>
  2875. <name>OT10</name>
  2876. <description>Port x configuration bits (y = 0..15)</description>
  2877. <bitOffset>10</bitOffset>
  2878. <bitWidth>1</bitWidth>
  2879. </field>
  2880. <field>
  2881. <name>OT9</name>
  2882. <description>Port x configuration bits (y = 0..15)</description>
  2883. <bitOffset>9</bitOffset>
  2884. <bitWidth>1</bitWidth>
  2885. </field>
  2886. <field>
  2887. <name>OT8</name>
  2888. <description>Port x configuration bits (y = 0..15)</description>
  2889. <bitOffset>8</bitOffset>
  2890. <bitWidth>1</bitWidth>
  2891. </field>
  2892. <field>
  2893. <name>OT7</name>
  2894. <description>Port x configuration bits (y = 0..15)</description>
  2895. <bitOffset>7</bitOffset>
  2896. <bitWidth>1</bitWidth>
  2897. </field>
  2898. <field>
  2899. <name>OT6</name>
  2900. <description>Port x configuration bits (y = 0..15)</description>
  2901. <bitOffset>6</bitOffset>
  2902. <bitWidth>1</bitWidth>
  2903. </field>
  2904. <field>
  2905. <name>OT5</name>
  2906. <description>Port x configuration bits (y = 0..15)</description>
  2907. <bitOffset>5</bitOffset>
  2908. <bitWidth>1</bitWidth>
  2909. </field>
  2910. <field>
  2911. <name>OT4</name>
  2912. <description>Port x configuration bits (y = 0..15)</description>
  2913. <bitOffset>4</bitOffset>
  2914. <bitWidth>1</bitWidth>
  2915. </field>
  2916. <field>
  2917. <name>OT3</name>
  2918. <description>Port x configuration bits (y = 0..15)</description>
  2919. <bitOffset>3</bitOffset>
  2920. <bitWidth>1</bitWidth>
  2921. </field>
  2922. <field>
  2923. <name>OT2</name>
  2924. <description>Port x configuration bits (y = 0..15)</description>
  2925. <bitOffset>2</bitOffset>
  2926. <bitWidth>1</bitWidth>
  2927. </field>
  2928. <field>
  2929. <name>OT1</name>
  2930. <description>Port x configuration bits (y = 0..15)</description>
  2931. <bitOffset>1</bitOffset>
  2932. <bitWidth>1</bitWidth>
  2933. </field>
  2934. <field>
  2935. <name>OT0</name>
  2936. <description>Port x configuration bits (y = 0..15)</description>
  2937. <bitOffset>0</bitOffset>
  2938. <bitWidth>1</bitWidth>
  2939. </field>
  2940. </fields>
  2941. </register>
  2942. <register>
  2943. <name>OSPEEDR</name>
  2944. <displayName>OSPEEDR</displayName>
  2945. <description>GPIO port output speed register</description>
  2946. <addressOffset>0x8</addressOffset>
  2947. <size>0x20</size>
  2948. <access>read-write</access>
  2949. <resetValue>0x00000000</resetValue>
  2950. <fields>
  2951. <field>
  2952. <name>OSPEED15</name>
  2953. <description>Port x configuration bits (y = 0..15)</description>
  2954. <bitOffset>30</bitOffset>
  2955. <bitWidth>2</bitWidth>
  2956. </field>
  2957. <field>
  2958. <name>OSPEED14</name>
  2959. <description>Port x configuration bits (y = 0..15)</description>
  2960. <bitOffset>28</bitOffset>
  2961. <bitWidth>2</bitWidth>
  2962. </field>
  2963. <field>
  2964. <name>OSPEED13</name>
  2965. <description>Port x configuration bits (y = 0..15)</description>
  2966. <bitOffset>26</bitOffset>
  2967. <bitWidth>2</bitWidth>
  2968. </field>
  2969. <field>
  2970. <name>OSPEED12</name>
  2971. <description>Port x configuration bits (y = 0..15)</description>
  2972. <bitOffset>24</bitOffset>
  2973. <bitWidth>2</bitWidth>
  2974. </field>
  2975. <field>
  2976. <name>OSPEED11</name>
  2977. <description>Port x configuration bits (y = 0..15)</description>
  2978. <bitOffset>22</bitOffset>
  2979. <bitWidth>2</bitWidth>
  2980. </field>
  2981. <field>
  2982. <name>OSPEED10</name>
  2983. <description>Port x configuration bits (y = 0..15)</description>
  2984. <bitOffset>20</bitOffset>
  2985. <bitWidth>2</bitWidth>
  2986. </field>
  2987. <field>
  2988. <name>OSPEED9</name>
  2989. <description>Port x configuration bits (y = 0..15)</description>
  2990. <bitOffset>18</bitOffset>
  2991. <bitWidth>2</bitWidth>
  2992. </field>
  2993. <field>
  2994. <name>OSPEED8</name>
  2995. <description>Port x configuration bits (y = 0..15)</description>
  2996. <bitOffset>16</bitOffset>
  2997. <bitWidth>2</bitWidth>
  2998. </field>
  2999. <field>
  3000. <name>OSPEED7</name>
  3001. <description>Port x configuration bits (y = 0..15)</description>
  3002. <bitOffset>14</bitOffset>
  3003. <bitWidth>2</bitWidth>
  3004. </field>
  3005. <field>
  3006. <name>OSPEED6</name>
  3007. <description>Port x configuration bits (y = 0..15)</description>
  3008. <bitOffset>12</bitOffset>
  3009. <bitWidth>2</bitWidth>
  3010. </field>
  3011. <field>
  3012. <name>OSPEED5</name>
  3013. <description>Port x configuration bits (y = 0..15)</description>
  3014. <bitOffset>10</bitOffset>
  3015. <bitWidth>2</bitWidth>
  3016. </field>
  3017. <field>
  3018. <name>OSPEED4</name>
  3019. <description>Port x configuration bits (y = 0..15)</description>
  3020. <bitOffset>8</bitOffset>
  3021. <bitWidth>2</bitWidth>
  3022. </field>
  3023. <field>
  3024. <name>OSPEED3</name>
  3025. <description>Port x configuration bits (y = 0..15)</description>
  3026. <bitOffset>6</bitOffset>
  3027. <bitWidth>2</bitWidth>
  3028. </field>
  3029. <field>
  3030. <name>OSPEED2</name>
  3031. <description>Port x configuration bits (y = 0..15)</description>
  3032. <bitOffset>4</bitOffset>
  3033. <bitWidth>2</bitWidth>
  3034. </field>
  3035. <field>
  3036. <name>OSPEED1</name>
  3037. <description>Port x configuration bits (y = 0..15)</description>
  3038. <bitOffset>2</bitOffset>
  3039. <bitWidth>2</bitWidth>
  3040. </field>
  3041. <field>
  3042. <name>OSPEED0</name>
  3043. <description>Port x configuration bits (y = 0..15)</description>
  3044. <bitOffset>0</bitOffset>
  3045. <bitWidth>2</bitWidth>
  3046. </field>
  3047. </fields>
  3048. </register>
  3049. <register>
  3050. <name>PUPDR</name>
  3051. <displayName>PUPDR</displayName>
  3052. <description>GPIO port pull-up/pull-down register</description>
  3053. <addressOffset>0xC</addressOffset>
  3054. <size>0x20</size>
  3055. <access>read-write</access>
  3056. <resetValue>0x00000000</resetValue>
  3057. <fields>
  3058. <field>
  3059. <name>PUPD15</name>
  3060. <description>Port x configuration bits (y = 0..15)</description>
  3061. <bitOffset>30</bitOffset>
  3062. <bitWidth>2</bitWidth>
  3063. </field>
  3064. <field>
  3065. <name>PUPD14</name>
  3066. <description>Port x configuration bits (y = 0..15)</description>
  3067. <bitOffset>28</bitOffset>
  3068. <bitWidth>2</bitWidth>
  3069. </field>
  3070. <field>
  3071. <name>PUPD13</name>
  3072. <description>Port x configuration bits (y = 0..15)</description>
  3073. <bitOffset>26</bitOffset>
  3074. <bitWidth>2</bitWidth>
  3075. </field>
  3076. <field>
  3077. <name>PUPD12</name>
  3078. <description>Port x configuration bits (y = 0..15)</description>
  3079. <bitOffset>24</bitOffset>
  3080. <bitWidth>2</bitWidth>
  3081. </field>
  3082. <field>
  3083. <name>PUPD11</name>
  3084. <description>Port x configuration bits (y = 0..15)</description>
  3085. <bitOffset>22</bitOffset>
  3086. <bitWidth>2</bitWidth>
  3087. </field>
  3088. <field>
  3089. <name>PUPD10</name>
  3090. <description>Port x configuration bits (y = 0..15)</description>
  3091. <bitOffset>20</bitOffset>
  3092. <bitWidth>2</bitWidth>
  3093. </field>
  3094. <field>
  3095. <name>PUPD9</name>
  3096. <description>Port x configuration bits (y = 0..15)</description>
  3097. <bitOffset>18</bitOffset>
  3098. <bitWidth>2</bitWidth>
  3099. </field>
  3100. <field>
  3101. <name>PUPD8</name>
  3102. <description>Port x configuration bits (y = 0..15)</description>
  3103. <bitOffset>16</bitOffset>
  3104. <bitWidth>2</bitWidth>
  3105. </field>
  3106. <field>
  3107. <name>PUPD7</name>
  3108. <description>Port x configuration bits (y = 0..15)</description>
  3109. <bitOffset>14</bitOffset>
  3110. <bitWidth>2</bitWidth>
  3111. </field>
  3112. <field>
  3113. <name>PUPD6</name>
  3114. <description>Port x configuration bits (y = 0..15)</description>
  3115. <bitOffset>12</bitOffset>
  3116. <bitWidth>2</bitWidth>
  3117. </field>
  3118. <field>
  3119. <name>PUPD5</name>
  3120. <description>Port x configuration bits (y = 0..15)</description>
  3121. <bitOffset>10</bitOffset>
  3122. <bitWidth>2</bitWidth>
  3123. </field>
  3124. <field>
  3125. <name>PUPD4</name>
  3126. <description>Port x configuration bits (y = 0..15)</description>
  3127. <bitOffset>8</bitOffset>
  3128. <bitWidth>2</bitWidth>
  3129. </field>
  3130. <field>
  3131. <name>PUPD3</name>
  3132. <description>Port x configuration bits (y = 0..15)</description>
  3133. <bitOffset>6</bitOffset>
  3134. <bitWidth>2</bitWidth>
  3135. </field>
  3136. <field>
  3137. <name>PUPD2</name>
  3138. <description>Port x configuration bits (y = 0..15)</description>
  3139. <bitOffset>4</bitOffset>
  3140. <bitWidth>2</bitWidth>
  3141. </field>
  3142. <field>
  3143. <name>PUPD1</name>
  3144. <description>Port x configuration bits (y = 0..15)</description>
  3145. <bitOffset>2</bitOffset>
  3146. <bitWidth>2</bitWidth>
  3147. </field>
  3148. <field>
  3149. <name>PUPD0</name>
  3150. <description>Port x configuration bits (y = 0..15)</description>
  3151. <bitOffset>0</bitOffset>
  3152. <bitWidth>2</bitWidth>
  3153. </field>
  3154. </fields>
  3155. </register>
  3156. <register>
  3157. <name>IDR</name>
  3158. <displayName>IDR</displayName>
  3159. <description>GPIO port input data register</description>
  3160. <addressOffset>0x10</addressOffset>
  3161. <size>0x20</size>
  3162. <access>read-only</access>
  3163. <resetValue>0x00000000</resetValue>
  3164. <fields>
  3165. <field>
  3166. <name>ID15</name>
  3167. <description>Port input data bit (y = 0..15)</description>
  3168. <bitOffset>15</bitOffset>
  3169. <bitWidth>1</bitWidth>
  3170. </field>
  3171. <field>
  3172. <name>ID14</name>
  3173. <description>Port input data bit (y = 0..15)</description>
  3174. <bitOffset>14</bitOffset>
  3175. <bitWidth>1</bitWidth>
  3176. </field>
  3177. <field>
  3178. <name>ID13</name>
  3179. <description>Port input data bit (y = 0..15)</description>
  3180. <bitOffset>13</bitOffset>
  3181. <bitWidth>1</bitWidth>
  3182. </field>
  3183. <field>
  3184. <name>ID12</name>
  3185. <description>Port input data bit (y = 0..15)</description>
  3186. <bitOffset>12</bitOffset>
  3187. <bitWidth>1</bitWidth>
  3188. </field>
  3189. <field>
  3190. <name>ID11</name>
  3191. <description>Port input data bit (y = 0..15)</description>
  3192. <bitOffset>11</bitOffset>
  3193. <bitWidth>1</bitWidth>
  3194. </field>
  3195. <field>
  3196. <name>ID10</name>
  3197. <description>Port input data bit (y = 0..15)</description>
  3198. <bitOffset>10</bitOffset>
  3199. <bitWidth>1</bitWidth>
  3200. </field>
  3201. <field>
  3202. <name>ID9</name>
  3203. <description>Port input data bit (y = 0..15)</description>
  3204. <bitOffset>9</bitOffset>
  3205. <bitWidth>1</bitWidth>
  3206. </field>
  3207. <field>
  3208. <name>ID8</name>
  3209. <description>Port input data bit (y = 0..15)</description>
  3210. <bitOffset>8</bitOffset>
  3211. <bitWidth>1</bitWidth>
  3212. </field>
  3213. <field>
  3214. <name>ID7</name>
  3215. <description>Port input data bit (y = 0..15)</description>
  3216. <bitOffset>7</bitOffset>
  3217. <bitWidth>1</bitWidth>
  3218. </field>
  3219. <field>
  3220. <name>ID6</name>
  3221. <description>Port input data bit (y = 0..15)</description>
  3222. <bitOffset>6</bitOffset>
  3223. <bitWidth>1</bitWidth>
  3224. </field>
  3225. <field>
  3226. <name>ID5</name>
  3227. <description>Port input data bit (y = 0..15)</description>
  3228. <bitOffset>5</bitOffset>
  3229. <bitWidth>1</bitWidth>
  3230. </field>
  3231. <field>
  3232. <name>ID4</name>
  3233. <description>Port input data bit (y = 0..15)</description>
  3234. <bitOffset>4</bitOffset>
  3235. <bitWidth>1</bitWidth>
  3236. </field>
  3237. <field>
  3238. <name>ID3</name>
  3239. <description>Port input data bit (y = 0..15)</description>
  3240. <bitOffset>3</bitOffset>
  3241. <bitWidth>1</bitWidth>
  3242. </field>
  3243. <field>
  3244. <name>ID2</name>
  3245. <description>Port input data bit (y = 0..15)</description>
  3246. <bitOffset>2</bitOffset>
  3247. <bitWidth>1</bitWidth>
  3248. </field>
  3249. <field>
  3250. <name>ID1</name>
  3251. <description>Port input data bit (y = 0..15)</description>
  3252. <bitOffset>1</bitOffset>
  3253. <bitWidth>1</bitWidth>
  3254. </field>
  3255. <field>
  3256. <name>ID0</name>
  3257. <description>Port input data bit (y = 0..15)</description>
  3258. <bitOffset>0</bitOffset>
  3259. <bitWidth>1</bitWidth>
  3260. </field>
  3261. </fields>
  3262. </register>
  3263. <register>
  3264. <name>ODR</name>
  3265. <displayName>ODR</displayName>
  3266. <description>GPIO port output data register</description>
  3267. <addressOffset>0x14</addressOffset>
  3268. <size>0x20</size>
  3269. <access>read-write</access>
  3270. <resetValue>0x00000000</resetValue>
  3271. <fields>
  3272. <field>
  3273. <name>OD15</name>
  3274. <description>Port output data bit (y = 0..15)</description>
  3275. <bitOffset>15</bitOffset>
  3276. <bitWidth>1</bitWidth>
  3277. </field>
  3278. <field>
  3279. <name>OD14</name>
  3280. <description>Port output data bit (y = 0..15)</description>
  3281. <bitOffset>14</bitOffset>
  3282. <bitWidth>1</bitWidth>
  3283. </field>
  3284. <field>
  3285. <name>OD13</name>
  3286. <description>Port output data bit (y = 0..15)</description>
  3287. <bitOffset>13</bitOffset>
  3288. <bitWidth>1</bitWidth>
  3289. </field>
  3290. <field>
  3291. <name>OD12</name>
  3292. <description>Port output data bit (y = 0..15)</description>
  3293. <bitOffset>12</bitOffset>
  3294. <bitWidth>1</bitWidth>
  3295. </field>
  3296. <field>
  3297. <name>OD11</name>
  3298. <description>Port output data bit (y = 0..15)</description>
  3299. <bitOffset>11</bitOffset>
  3300. <bitWidth>1</bitWidth>
  3301. </field>
  3302. <field>
  3303. <name>OD10</name>
  3304. <description>Port output data bit (y = 0..15)</description>
  3305. <bitOffset>10</bitOffset>
  3306. <bitWidth>1</bitWidth>
  3307. </field>
  3308. <field>
  3309. <name>OD9</name>
  3310. <description>Port output data bit (y = 0..15)</description>
  3311. <bitOffset>9</bitOffset>
  3312. <bitWidth>1</bitWidth>
  3313. </field>
  3314. <field>
  3315. <name>OD8</name>
  3316. <description>Port output data bit (y = 0..15)</description>
  3317. <bitOffset>8</bitOffset>
  3318. <bitWidth>1</bitWidth>
  3319. </field>
  3320. <field>
  3321. <name>OD7</name>
  3322. <description>Port output data bit (y = 0..15)</description>
  3323. <bitOffset>7</bitOffset>
  3324. <bitWidth>1</bitWidth>
  3325. </field>
  3326. <field>
  3327. <name>OD6</name>
  3328. <description>Port output data bit (y = 0..15)</description>
  3329. <bitOffset>6</bitOffset>
  3330. <bitWidth>1</bitWidth>
  3331. </field>
  3332. <field>
  3333. <name>OD5</name>
  3334. <description>Port output data bit (y = 0..15)</description>
  3335. <bitOffset>5</bitOffset>
  3336. <bitWidth>1</bitWidth>
  3337. </field>
  3338. <field>
  3339. <name>OD4</name>
  3340. <description>Port output data bit (y = 0..15)</description>
  3341. <bitOffset>4</bitOffset>
  3342. <bitWidth>1</bitWidth>
  3343. </field>
  3344. <field>
  3345. <name>OD3</name>
  3346. <description>Port output data bit (y = 0..15)</description>
  3347. <bitOffset>3</bitOffset>
  3348. <bitWidth>1</bitWidth>
  3349. </field>
  3350. <field>
  3351. <name>OD2</name>
  3352. <description>Port output data bit (y = 0..15)</description>
  3353. <bitOffset>2</bitOffset>
  3354. <bitWidth>1</bitWidth>
  3355. </field>
  3356. <field>
  3357. <name>OD1</name>
  3358. <description>Port output data bit (y = 0..15)</description>
  3359. <bitOffset>1</bitOffset>
  3360. <bitWidth>1</bitWidth>
  3361. </field>
  3362. <field>
  3363. <name>OD0</name>
  3364. <description>Port output data bit (y = 0..15)</description>
  3365. <bitOffset>0</bitOffset>
  3366. <bitWidth>1</bitWidth>
  3367. </field>
  3368. </fields>
  3369. </register>
  3370. <register>
  3371. <name>BSRR</name>
  3372. <displayName>BSRR</displayName>
  3373. <description>GPIO port bit set/reset register</description>
  3374. <addressOffset>0x18</addressOffset>
  3375. <size>0x20</size>
  3376. <access>write-only</access>
  3377. <resetValue>0x00000000</resetValue>
  3378. <fields>
  3379. <field>
  3380. <name>BR15</name>
  3381. <description>Port x reset bit y (y = 0..15)</description>
  3382. <bitOffset>31</bitOffset>
  3383. <bitWidth>1</bitWidth>
  3384. </field>
  3385. <field>
  3386. <name>BR14</name>
  3387. <description>Port x reset bit y (y = 0..15)</description>
  3388. <bitOffset>30</bitOffset>
  3389. <bitWidth>1</bitWidth>
  3390. </field>
  3391. <field>
  3392. <name>BR13</name>
  3393. <description>Port x reset bit y (y = 0..15)</description>
  3394. <bitOffset>29</bitOffset>
  3395. <bitWidth>1</bitWidth>
  3396. </field>
  3397. <field>
  3398. <name>BR12</name>
  3399. <description>Port x reset bit y (y = 0..15)</description>
  3400. <bitOffset>28</bitOffset>
  3401. <bitWidth>1</bitWidth>
  3402. </field>
  3403. <field>
  3404. <name>BR11</name>
  3405. <description>Port x reset bit y (y = 0..15)</description>
  3406. <bitOffset>27</bitOffset>
  3407. <bitWidth>1</bitWidth>
  3408. </field>
  3409. <field>
  3410. <name>BR10</name>
  3411. <description>Port x reset bit y (y = 0..15)</description>
  3412. <bitOffset>26</bitOffset>
  3413. <bitWidth>1</bitWidth>
  3414. </field>
  3415. <field>
  3416. <name>BR9</name>
  3417. <description>Port x reset bit y (y = 0..15)</description>
  3418. <bitOffset>25</bitOffset>
  3419. <bitWidth>1</bitWidth>
  3420. </field>
  3421. <field>
  3422. <name>BR8</name>
  3423. <description>Port x reset bit y (y = 0..15)</description>
  3424. <bitOffset>24</bitOffset>
  3425. <bitWidth>1</bitWidth>
  3426. </field>
  3427. <field>
  3428. <name>BR7</name>
  3429. <description>Port x reset bit y (y = 0..15)</description>
  3430. <bitOffset>23</bitOffset>
  3431. <bitWidth>1</bitWidth>
  3432. </field>
  3433. <field>
  3434. <name>BR6</name>
  3435. <description>Port x reset bit y (y = 0..15)</description>
  3436. <bitOffset>22</bitOffset>
  3437. <bitWidth>1</bitWidth>
  3438. </field>
  3439. <field>
  3440. <name>BR5</name>
  3441. <description>Port x reset bit y (y = 0..15)</description>
  3442. <bitOffset>21</bitOffset>
  3443. <bitWidth>1</bitWidth>
  3444. </field>
  3445. <field>
  3446. <name>BR4</name>
  3447. <description>Port x reset bit y (y = 0..15)</description>
  3448. <bitOffset>20</bitOffset>
  3449. <bitWidth>1</bitWidth>
  3450. </field>
  3451. <field>
  3452. <name>BR3</name>
  3453. <description>Port x reset bit y (y = 0..15)</description>
  3454. <bitOffset>19</bitOffset>
  3455. <bitWidth>1</bitWidth>
  3456. </field>
  3457. <field>
  3458. <name>BR2</name>
  3459. <description>Port x reset bit y (y = 0..15)</description>
  3460. <bitOffset>18</bitOffset>
  3461. <bitWidth>1</bitWidth>
  3462. </field>
  3463. <field>
  3464. <name>BR1</name>
  3465. <description>Port x reset bit y (y = 0..15)</description>
  3466. <bitOffset>17</bitOffset>
  3467. <bitWidth>1</bitWidth>
  3468. </field>
  3469. <field>
  3470. <name>BR0</name>
  3471. <description>Port x reset bit y (y = 0..15)</description>
  3472. <bitOffset>16</bitOffset>
  3473. <bitWidth>1</bitWidth>
  3474. </field>
  3475. <field>
  3476. <name>BS15</name>
  3477. <description>Port x set bit y (y= 0..15)</description>
  3478. <bitOffset>15</bitOffset>
  3479. <bitWidth>1</bitWidth>
  3480. </field>
  3481. <field>
  3482. <name>BS14</name>
  3483. <description>Port x set bit y (y= 0..15)</description>
  3484. <bitOffset>14</bitOffset>
  3485. <bitWidth>1</bitWidth>
  3486. </field>
  3487. <field>
  3488. <name>BS13</name>
  3489. <description>Port x set bit y (y= 0..15)</description>
  3490. <bitOffset>13</bitOffset>
  3491. <bitWidth>1</bitWidth>
  3492. </field>
  3493. <field>
  3494. <name>BS12</name>
  3495. <description>Port x set bit y (y= 0..15)</description>
  3496. <bitOffset>12</bitOffset>
  3497. <bitWidth>1</bitWidth>
  3498. </field>
  3499. <field>
  3500. <name>BS11</name>
  3501. <description>Port x set bit y (y= 0..15)</description>
  3502. <bitOffset>11</bitOffset>
  3503. <bitWidth>1</bitWidth>
  3504. </field>
  3505. <field>
  3506. <name>BS10</name>
  3507. <description>Port x set bit y (y= 0..15)</description>
  3508. <bitOffset>10</bitOffset>
  3509. <bitWidth>1</bitWidth>
  3510. </field>
  3511. <field>
  3512. <name>BS9</name>
  3513. <description>Port x set bit y (y= 0..15)</description>
  3514. <bitOffset>9</bitOffset>
  3515. <bitWidth>1</bitWidth>
  3516. </field>
  3517. <field>
  3518. <name>BS8</name>
  3519. <description>Port x set bit y (y= 0..15)</description>
  3520. <bitOffset>8</bitOffset>
  3521. <bitWidth>1</bitWidth>
  3522. </field>
  3523. <field>
  3524. <name>BS7</name>
  3525. <description>Port x set bit y (y= 0..15)</description>
  3526. <bitOffset>7</bitOffset>
  3527. <bitWidth>1</bitWidth>
  3528. </field>
  3529. <field>
  3530. <name>BS6</name>
  3531. <description>Port x set bit y (y= 0..15)</description>
  3532. <bitOffset>6</bitOffset>
  3533. <bitWidth>1</bitWidth>
  3534. </field>
  3535. <field>
  3536. <name>BS5</name>
  3537. <description>Port x set bit y (y= 0..15)</description>
  3538. <bitOffset>5</bitOffset>
  3539. <bitWidth>1</bitWidth>
  3540. </field>
  3541. <field>
  3542. <name>BS4</name>
  3543. <description>Port x set bit y (y= 0..15)</description>
  3544. <bitOffset>4</bitOffset>
  3545. <bitWidth>1</bitWidth>
  3546. </field>
  3547. <field>
  3548. <name>BS3</name>
  3549. <description>Port x set bit y (y= 0..15)</description>
  3550. <bitOffset>3</bitOffset>
  3551. <bitWidth>1</bitWidth>
  3552. </field>
  3553. <field>
  3554. <name>BS2</name>
  3555. <description>Port x set bit y (y= 0..15)</description>
  3556. <bitOffset>2</bitOffset>
  3557. <bitWidth>1</bitWidth>
  3558. </field>
  3559. <field>
  3560. <name>BS1</name>
  3561. <description>Port x set bit y (y= 0..15)</description>
  3562. <bitOffset>1</bitOffset>
  3563. <bitWidth>1</bitWidth>
  3564. </field>
  3565. <field>
  3566. <name>BS0</name>
  3567. <description>Port x set bit y (y= 0..15)</description>
  3568. <bitOffset>0</bitOffset>
  3569. <bitWidth>1</bitWidth>
  3570. </field>
  3571. </fields>
  3572. </register>
  3573. <register>
  3574. <name>LCKR</name>
  3575. <displayName>LCKR</displayName>
  3576. <description>GPIO port configuration lock register</description>
  3577. <addressOffset>0x1C</addressOffset>
  3578. <size>0x20</size>
  3579. <access>read-write</access>
  3580. <resetValue>0x00000000</resetValue>
  3581. <fields>
  3582. <field>
  3583. <name>LCKK</name>
  3584. <description>Port x lock bit y (y= 0..15)</description>
  3585. <bitOffset>16</bitOffset>
  3586. <bitWidth>1</bitWidth>
  3587. </field>
  3588. <field>
  3589. <name>LCK15</name>
  3590. <description>Port x lock bit y (y= 0..15)</description>
  3591. <bitOffset>15</bitOffset>
  3592. <bitWidth>1</bitWidth>
  3593. </field>
  3594. <field>
  3595. <name>LCK14</name>
  3596. <description>Port x lock bit y (y= 0..15)</description>
  3597. <bitOffset>14</bitOffset>
  3598. <bitWidth>1</bitWidth>
  3599. </field>
  3600. <field>
  3601. <name>LCK13</name>
  3602. <description>Port x lock bit y (y= 0..15)</description>
  3603. <bitOffset>13</bitOffset>
  3604. <bitWidth>1</bitWidth>
  3605. </field>
  3606. <field>
  3607. <name>LCK12</name>
  3608. <description>Port x lock bit y (y= 0..15)</description>
  3609. <bitOffset>12</bitOffset>
  3610. <bitWidth>1</bitWidth>
  3611. </field>
  3612. <field>
  3613. <name>LCK11</name>
  3614. <description>Port x lock bit y (y= 0..15)</description>
  3615. <bitOffset>11</bitOffset>
  3616. <bitWidth>1</bitWidth>
  3617. </field>
  3618. <field>
  3619. <name>LCK10</name>
  3620. <description>Port x lock bit y (y= 0..15)</description>
  3621. <bitOffset>10</bitOffset>
  3622. <bitWidth>1</bitWidth>
  3623. </field>
  3624. <field>
  3625. <name>LCK9</name>
  3626. <description>Port x lock bit y (y= 0..15)</description>
  3627. <bitOffset>9</bitOffset>
  3628. <bitWidth>1</bitWidth>
  3629. </field>
  3630. <field>
  3631. <name>LCK8</name>
  3632. <description>Port x lock bit y (y= 0..15)</description>
  3633. <bitOffset>8</bitOffset>
  3634. <bitWidth>1</bitWidth>
  3635. </field>
  3636. <field>
  3637. <name>LCK7</name>
  3638. <description>Port x lock bit y (y= 0..15)</description>
  3639. <bitOffset>7</bitOffset>
  3640. <bitWidth>1</bitWidth>
  3641. </field>
  3642. <field>
  3643. <name>LCK6</name>
  3644. <description>Port x lock bit y (y= 0..15)</description>
  3645. <bitOffset>6</bitOffset>
  3646. <bitWidth>1</bitWidth>
  3647. </field>
  3648. <field>
  3649. <name>LCK5</name>
  3650. <description>Port x lock bit y (y= 0..15)</description>
  3651. <bitOffset>5</bitOffset>
  3652. <bitWidth>1</bitWidth>
  3653. </field>
  3654. <field>
  3655. <name>LCK4</name>
  3656. <description>Port x lock bit y (y= 0..15)</description>
  3657. <bitOffset>4</bitOffset>
  3658. <bitWidth>1</bitWidth>
  3659. </field>
  3660. <field>
  3661. <name>LCK3</name>
  3662. <description>Port x lock bit y (y= 0..15)</description>
  3663. <bitOffset>3</bitOffset>
  3664. <bitWidth>1</bitWidth>
  3665. </field>
  3666. <field>
  3667. <name>LCK2</name>
  3668. <description>Port x lock bit y (y= 0..15)</description>
  3669. <bitOffset>2</bitOffset>
  3670. <bitWidth>1</bitWidth>
  3671. </field>
  3672. <field>
  3673. <name>LCK1</name>
  3674. <description>Port x lock bit y (y= 0..15)</description>
  3675. <bitOffset>1</bitOffset>
  3676. <bitWidth>1</bitWidth>
  3677. </field>
  3678. <field>
  3679. <name>LCK0</name>
  3680. <description>Port x lock bit y (y= 0..15)</description>
  3681. <bitOffset>0</bitOffset>
  3682. <bitWidth>1</bitWidth>
  3683. </field>
  3684. </fields>
  3685. </register>
  3686. <register>
  3687. <name>AFRL</name>
  3688. <displayName>AFRL</displayName>
  3689. <description>GPIO alternate function low register</description>
  3690. <addressOffset>0x20</addressOffset>
  3691. <size>0x20</size>
  3692. <access>read-write</access>
  3693. <resetValue>0x00000000</resetValue>
  3694. <fields>
  3695. <field>
  3696. <name>AFSEL7</name>
  3697. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3698. <bitOffset>28</bitOffset>
  3699. <bitWidth>4</bitWidth>
  3700. </field>
  3701. <field>
  3702. <name>AFSEL6</name>
  3703. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3704. <bitOffset>24</bitOffset>
  3705. <bitWidth>4</bitWidth>
  3706. </field>
  3707. <field>
  3708. <name>AFSEL5</name>
  3709. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3710. <bitOffset>20</bitOffset>
  3711. <bitWidth>4</bitWidth>
  3712. </field>
  3713. <field>
  3714. <name>AFSEL4</name>
  3715. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3716. <bitOffset>16</bitOffset>
  3717. <bitWidth>4</bitWidth>
  3718. </field>
  3719. <field>
  3720. <name>AFSEL3</name>
  3721. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3722. <bitOffset>12</bitOffset>
  3723. <bitWidth>4</bitWidth>
  3724. </field>
  3725. <field>
  3726. <name>AFSEL2</name>
  3727. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3728. <bitOffset>8</bitOffset>
  3729. <bitWidth>4</bitWidth>
  3730. </field>
  3731. <field>
  3732. <name>AFSEL1</name>
  3733. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3734. <bitOffset>4</bitOffset>
  3735. <bitWidth>4</bitWidth>
  3736. </field>
  3737. <field>
  3738. <name>AFSEL0</name>
  3739. <description>Alternate function selection for port x pin y (y = 0..7)</description>
  3740. <bitOffset>0</bitOffset>
  3741. <bitWidth>4</bitWidth>
  3742. </field>
  3743. </fields>
  3744. </register>
  3745. <register>
  3746. <name>AFRH</name>
  3747. <displayName>AFRH</displayName>
  3748. <description>GPIO alternate function high register</description>
  3749. <addressOffset>0x24</addressOffset>
  3750. <size>0x20</size>
  3751. <access>read-write</access>
  3752. <resetValue>0x00000000</resetValue>
  3753. <fields>
  3754. <field>
  3755. <name>AFSEL15</name>
  3756. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3757. <bitOffset>28</bitOffset>
  3758. <bitWidth>4</bitWidth>
  3759. </field>
  3760. <field>
  3761. <name>AFSEL14</name>
  3762. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3763. <bitOffset>24</bitOffset>
  3764. <bitWidth>4</bitWidth>
  3765. </field>
  3766. <field>
  3767. <name>AFSEL13</name>
  3768. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3769. <bitOffset>20</bitOffset>
  3770. <bitWidth>4</bitWidth>
  3771. </field>
  3772. <field>
  3773. <name>AFSEL12</name>
  3774. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3775. <bitOffset>16</bitOffset>
  3776. <bitWidth>4</bitWidth>
  3777. </field>
  3778. <field>
  3779. <name>AFSEL11</name>
  3780. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3781. <bitOffset>12</bitOffset>
  3782. <bitWidth>4</bitWidth>
  3783. </field>
  3784. <field>
  3785. <name>AFSEL10</name>
  3786. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3787. <bitOffset>8</bitOffset>
  3788. <bitWidth>4</bitWidth>
  3789. </field>
  3790. <field>
  3791. <name>AFSEL9</name>
  3792. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3793. <bitOffset>4</bitOffset>
  3794. <bitWidth>4</bitWidth>
  3795. </field>
  3796. <field>
  3797. <name>AFSEL8</name>
  3798. <description>Alternate function selection for port x pin y (y = 8..15)</description>
  3799. <bitOffset>0</bitOffset>
  3800. <bitWidth>4</bitWidth>
  3801. </field>
  3802. </fields>
  3803. </register>
  3804. <register>
  3805. <name>BRR</name>
  3806. <displayName>BRR</displayName>
  3807. <description>GPIO port bit reset register</description>
  3808. <addressOffset>0x28</addressOffset>
  3809. <size>0x20</size>
  3810. <access>write-only</access>
  3811. <resetValue>0x00000000</resetValue>
  3812. <fields>
  3813. <field>
  3814. <name>BR15</name>
  3815. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3816. <bitOffset>15</bitOffset>
  3817. <bitWidth>1</bitWidth>
  3818. </field>
  3819. <field>
  3820. <name>BR14</name>
  3821. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3822. <bitOffset>14</bitOffset>
  3823. <bitWidth>1</bitWidth>
  3824. </field>
  3825. <field>
  3826. <name>BR13</name>
  3827. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3828. <bitOffset>13</bitOffset>
  3829. <bitWidth>1</bitWidth>
  3830. </field>
  3831. <field>
  3832. <name>BR12</name>
  3833. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3834. <bitOffset>12</bitOffset>
  3835. <bitWidth>1</bitWidth>
  3836. </field>
  3837. <field>
  3838. <name>BR11</name>
  3839. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3840. <bitOffset>11</bitOffset>
  3841. <bitWidth>1</bitWidth>
  3842. </field>
  3843. <field>
  3844. <name>BR10</name>
  3845. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3846. <bitOffset>10</bitOffset>
  3847. <bitWidth>1</bitWidth>
  3848. </field>
  3849. <field>
  3850. <name>BR9</name>
  3851. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3852. <bitOffset>9</bitOffset>
  3853. <bitWidth>1</bitWidth>
  3854. </field>
  3855. <field>
  3856. <name>BR8</name>
  3857. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3858. <bitOffset>8</bitOffset>
  3859. <bitWidth>1</bitWidth>
  3860. </field>
  3861. <field>
  3862. <name>BR7</name>
  3863. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3864. <bitOffset>7</bitOffset>
  3865. <bitWidth>1</bitWidth>
  3866. </field>
  3867. <field>
  3868. <name>BR6</name>
  3869. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3870. <bitOffset>6</bitOffset>
  3871. <bitWidth>1</bitWidth>
  3872. </field>
  3873. <field>
  3874. <name>BR5</name>
  3875. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3876. <bitOffset>5</bitOffset>
  3877. <bitWidth>1</bitWidth>
  3878. </field>
  3879. <field>
  3880. <name>BR4</name>
  3881. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3882. <bitOffset>4</bitOffset>
  3883. <bitWidth>1</bitWidth>
  3884. </field>
  3885. <field>
  3886. <name>BR3</name>
  3887. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3888. <bitOffset>3</bitOffset>
  3889. <bitWidth>1</bitWidth>
  3890. </field>
  3891. <field>
  3892. <name>BR2</name>
  3893. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3894. <bitOffset>2</bitOffset>
  3895. <bitWidth>1</bitWidth>
  3896. </field>
  3897. <field>
  3898. <name>BR1</name>
  3899. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3900. <bitOffset>1</bitOffset>
  3901. <bitWidth>1</bitWidth>
  3902. </field>
  3903. <field>
  3904. <name>BR0</name>
  3905. <description>Port x Reset bit y (y= 0 .. 15)</description>
  3906. <bitOffset>0</bitOffset>
  3907. <bitWidth>1</bitWidth>
  3908. </field>
  3909. </fields>
  3910. </register>
  3911. </registers>
  3912. </peripheral>
  3913. <peripheral derivedFrom="GPIOB">
  3914. <name>GPIOC</name>
  3915. <baseAddress>0x50000800</baseAddress>
  3916. </peripheral>
  3917. <peripheral derivedFrom="GPIOB">
  3918. <name>GPIOD</name>
  3919. <baseAddress>0x50000C00</baseAddress>
  3920. </peripheral>
  3921. <peripheral derivedFrom="GPIOB">
  3922. <name>GPIOH</name>
  3923. <baseAddress>0x50001C00</baseAddress>
  3924. </peripheral>
  3925. <peripheral derivedFrom="GPIOB">
  3926. <name>GPIOE</name>
  3927. <baseAddress>0x50001000</baseAddress>
  3928. </peripheral>
  3929. <peripheral>
  3930. <name>LPTIM</name>
  3931. <description>Low power timer</description>
  3932. <groupName>LPTIM</groupName>
  3933. <baseAddress>0x40007C00</baseAddress>
  3934. <addressBlock>
  3935. <offset>0x0</offset>
  3936. <size>0x400</size>
  3937. <usage>registers</usage>
  3938. </addressBlock>
  3939. <interrupt>
  3940. <name>LPTIM1</name>
  3941. <description>LPTIMER1 interrupt through
  3942. EXTI29</description>
  3943. <value>13</value>
  3944. </interrupt>
  3945. <registers>
  3946. <register>
  3947. <name>ISR</name>
  3948. <displayName>ISR</displayName>
  3949. <description>Interrupt and Status Register</description>
  3950. <addressOffset>0x0</addressOffset>
  3951. <size>0x20</size>
  3952. <access>read-only</access>
  3953. <resetValue>0x00000000</resetValue>
  3954. <fields>
  3955. <field>
  3956. <name>DOWN</name>
  3957. <description>Counter direction change up to down</description>
  3958. <bitOffset>6</bitOffset>
  3959. <bitWidth>1</bitWidth>
  3960. </field>
  3961. <field>
  3962. <name>UP</name>
  3963. <description>Counter direction change down to up</description>
  3964. <bitOffset>5</bitOffset>
  3965. <bitWidth>1</bitWidth>
  3966. </field>
  3967. <field>
  3968. <name>ARROK</name>
  3969. <description>Autoreload register update OK</description>
  3970. <bitOffset>4</bitOffset>
  3971. <bitWidth>1</bitWidth>
  3972. </field>
  3973. <field>
  3974. <name>CMPOK</name>
  3975. <description>Compare register update OK</description>
  3976. <bitOffset>3</bitOffset>
  3977. <bitWidth>1</bitWidth>
  3978. </field>
  3979. <field>
  3980. <name>EXTTRIG</name>
  3981. <description>External trigger edge event</description>
  3982. <bitOffset>2</bitOffset>
  3983. <bitWidth>1</bitWidth>
  3984. </field>
  3985. <field>
  3986. <name>ARRM</name>
  3987. <description>Autoreload match</description>
  3988. <bitOffset>1</bitOffset>
  3989. <bitWidth>1</bitWidth>
  3990. </field>
  3991. <field>
  3992. <name>CMPM</name>
  3993. <description>Compare match</description>
  3994. <bitOffset>0</bitOffset>
  3995. <bitWidth>1</bitWidth>
  3996. </field>
  3997. </fields>
  3998. </register>
  3999. <register>
  4000. <name>ICR</name>
  4001. <displayName>ICR</displayName>
  4002. <description>Interrupt Clear Register</description>
  4003. <addressOffset>0x4</addressOffset>
  4004. <size>0x20</size>
  4005. <access>write-only</access>
  4006. <resetValue>0x00000000</resetValue>
  4007. <fields>
  4008. <field>
  4009. <name>DOWNCF</name>
  4010. <description>Direction change to down Clear Flag</description>
  4011. <bitOffset>6</bitOffset>
  4012. <bitWidth>1</bitWidth>
  4013. </field>
  4014. <field>
  4015. <name>UPCF</name>
  4016. <description>Direction change to UP Clear Flag</description>
  4017. <bitOffset>5</bitOffset>
  4018. <bitWidth>1</bitWidth>
  4019. </field>
  4020. <field>
  4021. <name>ARROKCF</name>
  4022. <description>Autoreload register update OK Clear Flag</description>
  4023. <bitOffset>4</bitOffset>
  4024. <bitWidth>1</bitWidth>
  4025. </field>
  4026. <field>
  4027. <name>CMPOKCF</name>
  4028. <description>Compare register update OK Clear Flag</description>
  4029. <bitOffset>3</bitOffset>
  4030. <bitWidth>1</bitWidth>
  4031. </field>
  4032. <field>
  4033. <name>EXTTRIGCF</name>
  4034. <description>External trigger valid edge Clear Flag</description>
  4035. <bitOffset>2</bitOffset>
  4036. <bitWidth>1</bitWidth>
  4037. </field>
  4038. <field>
  4039. <name>ARRMCF</name>
  4040. <description>Autoreload match Clear Flag</description>
  4041. <bitOffset>1</bitOffset>
  4042. <bitWidth>1</bitWidth>
  4043. </field>
  4044. <field>
  4045. <name>CMPMCF</name>
  4046. <description>compare match Clear Flag</description>
  4047. <bitOffset>0</bitOffset>
  4048. <bitWidth>1</bitWidth>
  4049. </field>
  4050. </fields>
  4051. </register>
  4052. <register>
  4053. <name>IER</name>
  4054. <displayName>IER</displayName>
  4055. <description>Interrupt Enable Register</description>
  4056. <addressOffset>0x8</addressOffset>
  4057. <size>0x20</size>
  4058. <access>read-write</access>
  4059. <resetValue>0x00000000</resetValue>
  4060. <fields>
  4061. <field>
  4062. <name>DOWNIE</name>
  4063. <description>Direction change to down Interrupt Enable</description>
  4064. <bitOffset>6</bitOffset>
  4065. <bitWidth>1</bitWidth>
  4066. </field>
  4067. <field>
  4068. <name>UPIE</name>
  4069. <description>Direction change to UP Interrupt Enable</description>
  4070. <bitOffset>5</bitOffset>
  4071. <bitWidth>1</bitWidth>
  4072. </field>
  4073. <field>
  4074. <name>ARROKIE</name>
  4075. <description>Autoreload register update OK Interrupt Enable</description>
  4076. <bitOffset>4</bitOffset>
  4077. <bitWidth>1</bitWidth>
  4078. </field>
  4079. <field>
  4080. <name>CMPOKIE</name>
  4081. <description>Compare register update OK Interrupt Enable</description>
  4082. <bitOffset>3</bitOffset>
  4083. <bitWidth>1</bitWidth>
  4084. </field>
  4085. <field>
  4086. <name>EXTTRIGIE</name>
  4087. <description>External trigger valid edge Interrupt Enable</description>
  4088. <bitOffset>2</bitOffset>
  4089. <bitWidth>1</bitWidth>
  4090. </field>
  4091. <field>
  4092. <name>ARRMIE</name>
  4093. <description>Autoreload match Interrupt Enable</description>
  4094. <bitOffset>1</bitOffset>
  4095. <bitWidth>1</bitWidth>
  4096. </field>
  4097. <field>
  4098. <name>CMPMIE</name>
  4099. <description>Compare match Interrupt Enable</description>
  4100. <bitOffset>0</bitOffset>
  4101. <bitWidth>1</bitWidth>
  4102. </field>
  4103. </fields>
  4104. </register>
  4105. <register>
  4106. <name>CFGR</name>
  4107. <displayName>CFGR</displayName>
  4108. <description>Configuration Register</description>
  4109. <addressOffset>0xC</addressOffset>
  4110. <size>0x20</size>
  4111. <access>read-write</access>
  4112. <resetValue>0x00000000</resetValue>
  4113. <fields>
  4114. <field>
  4115. <name>ENC</name>
  4116. <description>Encoder mode enable</description>
  4117. <bitOffset>24</bitOffset>
  4118. <bitWidth>1</bitWidth>
  4119. </field>
  4120. <field>
  4121. <name>COUNTMODE</name>
  4122. <description>counter mode enabled</description>
  4123. <bitOffset>23</bitOffset>
  4124. <bitWidth>1</bitWidth>
  4125. </field>
  4126. <field>
  4127. <name>PRELOAD</name>
  4128. <description>Registers update mode</description>
  4129. <bitOffset>22</bitOffset>
  4130. <bitWidth>1</bitWidth>
  4131. </field>
  4132. <field>
  4133. <name>WAVPOL</name>
  4134. <description>Waveform shape polarity</description>
  4135. <bitOffset>21</bitOffset>
  4136. <bitWidth>1</bitWidth>
  4137. </field>
  4138. <field>
  4139. <name>WAVE</name>
  4140. <description>Waveform shape</description>
  4141. <bitOffset>20</bitOffset>
  4142. <bitWidth>1</bitWidth>
  4143. </field>
  4144. <field>
  4145. <name>TIMOUT</name>
  4146. <description>Timeout enable</description>
  4147. <bitOffset>19</bitOffset>
  4148. <bitWidth>1</bitWidth>
  4149. </field>
  4150. <field>
  4151. <name>TRIGEN</name>
  4152. <description>Trigger enable and polarity</description>
  4153. <bitOffset>17</bitOffset>
  4154. <bitWidth>2</bitWidth>
  4155. </field>
  4156. <field>
  4157. <name>TRIGSEL</name>
  4158. <description>Trigger selector</description>
  4159. <bitOffset>13</bitOffset>
  4160. <bitWidth>3</bitWidth>
  4161. </field>
  4162. <field>
  4163. <name>PRESC</name>
  4164. <description>Clock prescaler</description>
  4165. <bitOffset>9</bitOffset>
  4166. <bitWidth>3</bitWidth>
  4167. </field>
  4168. <field>
  4169. <name>TRGFLT</name>
  4170. <description>Configurable digital filter for trigger</description>
  4171. <bitOffset>6</bitOffset>
  4172. <bitWidth>2</bitWidth>
  4173. </field>
  4174. <field>
  4175. <name>CKFLT</name>
  4176. <description>Configurable digital filter for external clock</description>
  4177. <bitOffset>3</bitOffset>
  4178. <bitWidth>2</bitWidth>
  4179. </field>
  4180. <field>
  4181. <name>CKPOL</name>
  4182. <description>Clock Polarity</description>
  4183. <bitOffset>1</bitOffset>
  4184. <bitWidth>2</bitWidth>
  4185. </field>
  4186. <field>
  4187. <name>CKSEL</name>
  4188. <description>Clock selector</description>
  4189. <bitOffset>0</bitOffset>
  4190. <bitWidth>1</bitWidth>
  4191. </field>
  4192. </fields>
  4193. </register>
  4194. <register>
  4195. <name>CR</name>
  4196. <displayName>CR</displayName>
  4197. <description>Control Register</description>
  4198. <addressOffset>0x10</addressOffset>
  4199. <size>0x20</size>
  4200. <access>read-write</access>
  4201. <resetValue>0x00000000</resetValue>
  4202. <fields>
  4203. <field>
  4204. <name>CNTSTRT</name>
  4205. <description>Timer start in continuous mode</description>
  4206. <bitOffset>2</bitOffset>
  4207. <bitWidth>1</bitWidth>
  4208. </field>
  4209. <field>
  4210. <name>SNGSTRT</name>
  4211. <description>LPTIM start in single mode</description>
  4212. <bitOffset>1</bitOffset>
  4213. <bitWidth>1</bitWidth>
  4214. </field>
  4215. <field>
  4216. <name>ENABLE</name>
  4217. <description>LPTIM Enable</description>
  4218. <bitOffset>0</bitOffset>
  4219. <bitWidth>1</bitWidth>
  4220. </field>
  4221. </fields>
  4222. </register>
  4223. <register>
  4224. <name>CMP</name>
  4225. <displayName>CMP</displayName>
  4226. <description>Compare Register</description>
  4227. <addressOffset>0x14</addressOffset>
  4228. <size>0x20</size>
  4229. <access>read-write</access>
  4230. <resetValue>0x00000000</resetValue>
  4231. <fields>
  4232. <field>
  4233. <name>CMP</name>
  4234. <description>Compare value.</description>
  4235. <bitOffset>0</bitOffset>
  4236. <bitWidth>16</bitWidth>
  4237. </field>
  4238. </fields>
  4239. </register>
  4240. <register>
  4241. <name>ARR</name>
  4242. <displayName>ARR</displayName>
  4243. <description>Autoreload Register</description>
  4244. <addressOffset>0x18</addressOffset>
  4245. <size>0x20</size>
  4246. <access>read-write</access>
  4247. <resetValue>0x00000001</resetValue>
  4248. <fields>
  4249. <field>
  4250. <name>ARR</name>
  4251. <description>Auto reload value.</description>
  4252. <bitOffset>0</bitOffset>
  4253. <bitWidth>16</bitWidth>
  4254. </field>
  4255. </fields>
  4256. </register>
  4257. <register>
  4258. <name>CNT</name>
  4259. <displayName>CNT</displayName>
  4260. <description>Counter Register</description>
  4261. <addressOffset>0x1C</addressOffset>
  4262. <size>0x20</size>
  4263. <access>read-only</access>
  4264. <resetValue>0x00000000</resetValue>
  4265. <fields>
  4266. <field>
  4267. <name>CNT</name>
  4268. <description>Counter value.</description>
  4269. <bitOffset>0</bitOffset>
  4270. <bitWidth>16</bitWidth>
  4271. </field>
  4272. </fields>
  4273. </register>
  4274. </registers>
  4275. </peripheral>
  4276. <peripheral>
  4277. <name>RTC</name>
  4278. <description>Real-time clock</description>
  4279. <groupName>RTC</groupName>
  4280. <baseAddress>0x40002800</baseAddress>
  4281. <addressBlock>
  4282. <offset>0x0</offset>
  4283. <size>0x400</size>
  4284. <usage>registers</usage>
  4285. </addressBlock>
  4286. <interrupt>
  4287. <name>RTC</name>
  4288. <description>RTC global interrupt</description>
  4289. <value>2</value>
  4290. </interrupt>
  4291. <registers>
  4292. <register>
  4293. <name>TR</name>
  4294. <displayName>TR</displayName>
  4295. <description>RTC time register</description>
  4296. <addressOffset>0x0</addressOffset>
  4297. <size>0x20</size>
  4298. <access>read-write</access>
  4299. <resetValue>0x00000000</resetValue>
  4300. <fields>
  4301. <field>
  4302. <name>PM</name>
  4303. <description>AM/PM notation</description>
  4304. <bitOffset>22</bitOffset>
  4305. <bitWidth>1</bitWidth>
  4306. </field>
  4307. <field>
  4308. <name>HT</name>
  4309. <description>Hour tens in BCD format</description>
  4310. <bitOffset>20</bitOffset>
  4311. <bitWidth>2</bitWidth>
  4312. </field>
  4313. <field>
  4314. <name>HU</name>
  4315. <description>Hour units in BCD format</description>
  4316. <bitOffset>16</bitOffset>
  4317. <bitWidth>4</bitWidth>
  4318. </field>
  4319. <field>
  4320. <name>MNT</name>
  4321. <description>Minute tens in BCD format</description>
  4322. <bitOffset>12</bitOffset>
  4323. <bitWidth>3</bitWidth>
  4324. </field>
  4325. <field>
  4326. <name>MNU</name>
  4327. <description>Minute units in BCD format</description>
  4328. <bitOffset>8</bitOffset>
  4329. <bitWidth>4</bitWidth>
  4330. </field>
  4331. <field>
  4332. <name>ST</name>
  4333. <description>Second tens in BCD format</description>
  4334. <bitOffset>4</bitOffset>
  4335. <bitWidth>3</bitWidth>
  4336. </field>
  4337. <field>
  4338. <name>SU</name>
  4339. <description>Second units in BCD format</description>
  4340. <bitOffset>0</bitOffset>
  4341. <bitWidth>4</bitWidth>
  4342. </field>
  4343. </fields>
  4344. </register>
  4345. <register>
  4346. <name>DR</name>
  4347. <displayName>DR</displayName>
  4348. <description>RTC date register</description>
  4349. <addressOffset>0x4</addressOffset>
  4350. <size>0x20</size>
  4351. <access>read-write</access>
  4352. <resetValue>0x00000000</resetValue>
  4353. <fields>
  4354. <field>
  4355. <name>YT</name>
  4356. <description>Year tens in BCD format</description>
  4357. <bitOffset>20</bitOffset>
  4358. <bitWidth>4</bitWidth>
  4359. </field>
  4360. <field>
  4361. <name>YU</name>
  4362. <description>Year units in BCD format</description>
  4363. <bitOffset>16</bitOffset>
  4364. <bitWidth>4</bitWidth>
  4365. </field>
  4366. <field>
  4367. <name>WDU</name>
  4368. <description>Week day units</description>
  4369. <bitOffset>13</bitOffset>
  4370. <bitWidth>3</bitWidth>
  4371. </field>
  4372. <field>
  4373. <name>MT</name>
  4374. <description>Month tens in BCD format</description>
  4375. <bitOffset>12</bitOffset>
  4376. <bitWidth>1</bitWidth>
  4377. </field>
  4378. <field>
  4379. <name>MU</name>
  4380. <description>Month units in BCD format</description>
  4381. <bitOffset>8</bitOffset>
  4382. <bitWidth>4</bitWidth>
  4383. </field>
  4384. <field>
  4385. <name>DT</name>
  4386. <description>Date tens in BCD format</description>
  4387. <bitOffset>4</bitOffset>
  4388. <bitWidth>2</bitWidth>
  4389. </field>
  4390. <field>
  4391. <name>DU</name>
  4392. <description>Date units in BCD format</description>
  4393. <bitOffset>0</bitOffset>
  4394. <bitWidth>4</bitWidth>
  4395. </field>
  4396. </fields>
  4397. </register>
  4398. <register>
  4399. <name>CR</name>
  4400. <displayName>CR</displayName>
  4401. <description>RTC control register</description>
  4402. <addressOffset>0x8</addressOffset>
  4403. <size>0x20</size>
  4404. <resetValue>0x00000000</resetValue>
  4405. <fields>
  4406. <field>
  4407. <name>COE</name>
  4408. <description>Calibration output enable</description>
  4409. <bitOffset>23</bitOffset>
  4410. <bitWidth>1</bitWidth>
  4411. <access>read-write</access>
  4412. </field>
  4413. <field>
  4414. <name>OSEL</name>
  4415. <description>Output selection</description>
  4416. <bitOffset>21</bitOffset>
  4417. <bitWidth>2</bitWidth>
  4418. <access>read-write</access>
  4419. </field>
  4420. <field>
  4421. <name>POL</name>
  4422. <description>Output polarity</description>
  4423. <bitOffset>20</bitOffset>
  4424. <bitWidth>1</bitWidth>
  4425. <access>read-write</access>
  4426. </field>
  4427. <field>
  4428. <name>COSEL</name>
  4429. <description>Calibration output selection</description>
  4430. <bitOffset>19</bitOffset>
  4431. <bitWidth>1</bitWidth>
  4432. <access>read-write</access>
  4433. </field>
  4434. <field>
  4435. <name>BKP</name>
  4436. <description>Backup</description>
  4437. <bitOffset>18</bitOffset>
  4438. <bitWidth>1</bitWidth>
  4439. <access>read-write</access>
  4440. </field>
  4441. <field>
  4442. <name>SUB1H</name>
  4443. <description>Subtract 1 hour (winter time change)</description>
  4444. <bitOffset>17</bitOffset>
  4445. <bitWidth>1</bitWidth>
  4446. <access>write-only</access>
  4447. </field>
  4448. <field>
  4449. <name>ADD1H</name>
  4450. <description>Add 1 hour (summer time change)</description>
  4451. <bitOffset>16</bitOffset>
  4452. <bitWidth>1</bitWidth>
  4453. <access>write-only</access>
  4454. </field>
  4455. <field>
  4456. <name>TSIE</name>
  4457. <description>Time-stamp interrupt enable</description>
  4458. <bitOffset>15</bitOffset>
  4459. <bitWidth>1</bitWidth>
  4460. <access>read-write</access>
  4461. </field>
  4462. <field>
  4463. <name>WUTIE</name>
  4464. <description>Wakeup timer interrupt enable</description>
  4465. <bitOffset>14</bitOffset>
  4466. <bitWidth>1</bitWidth>
  4467. <access>read-write</access>
  4468. </field>
  4469. <field>
  4470. <name>ALRBIE</name>
  4471. <description>Alarm B interrupt enable</description>
  4472. <bitOffset>13</bitOffset>
  4473. <bitWidth>1</bitWidth>
  4474. <access>read-write</access>
  4475. </field>
  4476. <field>
  4477. <name>ALRAIE</name>
  4478. <description>Alarm A interrupt enable</description>
  4479. <bitOffset>12</bitOffset>
  4480. <bitWidth>1</bitWidth>
  4481. <access>read-write</access>
  4482. </field>
  4483. <field>
  4484. <name>TSE</name>
  4485. <description>timestamp enable</description>
  4486. <bitOffset>11</bitOffset>
  4487. <bitWidth>1</bitWidth>
  4488. <access>read-write</access>
  4489. </field>
  4490. <field>
  4491. <name>WUTE</name>
  4492. <description>Wakeup timer enable</description>
  4493. <bitOffset>10</bitOffset>
  4494. <bitWidth>1</bitWidth>
  4495. <access>read-write</access>
  4496. </field>
  4497. <field>
  4498. <name>ALRBE</name>
  4499. <description>Alarm B enable</description>
  4500. <bitOffset>9</bitOffset>
  4501. <bitWidth>1</bitWidth>
  4502. <access>read-write</access>
  4503. </field>
  4504. <field>
  4505. <name>ALRAE</name>
  4506. <description>Alarm A enable</description>
  4507. <bitOffset>8</bitOffset>
  4508. <bitWidth>1</bitWidth>
  4509. <access>read-write</access>
  4510. </field>
  4511. <field>
  4512. <name>FMT</name>
  4513. <description>Hour format</description>
  4514. <bitOffset>6</bitOffset>
  4515. <bitWidth>1</bitWidth>
  4516. <access>read-write</access>
  4517. </field>
  4518. <field>
  4519. <name>BYPSHAD</name>
  4520. <description>Bypass the shadow registers</description>
  4521. <bitOffset>5</bitOffset>
  4522. <bitWidth>1</bitWidth>
  4523. <access>read-write</access>
  4524. </field>
  4525. <field>
  4526. <name>REFCKON</name>
  4527. <description>RTC_REFIN reference clock detection enable (50 or 60 Hz)</description>
  4528. <bitOffset>4</bitOffset>
  4529. <bitWidth>1</bitWidth>
  4530. <access>read-write</access>
  4531. </field>
  4532. <field>
  4533. <name>TSEDGE</name>
  4534. <description>Time-stamp event active edge</description>
  4535. <bitOffset>3</bitOffset>
  4536. <bitWidth>1</bitWidth>
  4537. <access>read-write</access>
  4538. </field>
  4539. <field>
  4540. <name>WUCKSEL</name>
  4541. <description>Wakeup clock selection</description>
  4542. <bitOffset>0</bitOffset>
  4543. <bitWidth>3</bitWidth>
  4544. <access>read-write</access>
  4545. </field>
  4546. </fields>
  4547. </register>
  4548. <register>
  4549. <name>ISR</name>
  4550. <displayName>ISR</displayName>
  4551. <description>RTC initialization and status register</description>
  4552. <addressOffset>0xC</addressOffset>
  4553. <size>0x20</size>
  4554. <resetValue>0x00000000</resetValue>
  4555. <fields>
  4556. <field>
  4557. <name>TAMP2F</name>
  4558. <description>RTC_TAMP2 detection flag</description>
  4559. <bitOffset>14</bitOffset>
  4560. <bitWidth>1</bitWidth>
  4561. <access>read-write</access>
  4562. </field>
  4563. <field>
  4564. <name>TAMP1F</name>
  4565. <description>RTC_TAMP1 detection flag</description>
  4566. <bitOffset>13</bitOffset>
  4567. <bitWidth>1</bitWidth>
  4568. <access>read-write</access>
  4569. </field>
  4570. <field>
  4571. <name>TSOVF</name>
  4572. <description>Time-stamp overflow flag</description>
  4573. <bitOffset>12</bitOffset>
  4574. <bitWidth>1</bitWidth>
  4575. <access>read-write</access>
  4576. </field>
  4577. <field>
  4578. <name>TSF</name>
  4579. <description>Time-stamp flag</description>
  4580. <bitOffset>11</bitOffset>
  4581. <bitWidth>1</bitWidth>
  4582. <access>read-write</access>
  4583. </field>
  4584. <field>
  4585. <name>WUTF</name>
  4586. <description>Wakeup timer flag</description>
  4587. <bitOffset>10</bitOffset>
  4588. <bitWidth>1</bitWidth>
  4589. <access>read-write</access>
  4590. </field>
  4591. <field>
  4592. <name>ALRBF</name>
  4593. <description>Alarm B flag</description>
  4594. <bitOffset>9</bitOffset>
  4595. <bitWidth>1</bitWidth>
  4596. <access>read-write</access>
  4597. </field>
  4598. <field>
  4599. <name>ALRAF</name>
  4600. <description>Alarm A flag</description>
  4601. <bitOffset>8</bitOffset>
  4602. <bitWidth>1</bitWidth>
  4603. <access>read-write</access>
  4604. </field>
  4605. <field>
  4606. <name>INIT</name>
  4607. <description>Initialization mode</description>
  4608. <bitOffset>7</bitOffset>
  4609. <bitWidth>1</bitWidth>
  4610. <access>read-write</access>
  4611. </field>
  4612. <field>
  4613. <name>INITF</name>
  4614. <description>Initialization flag</description>
  4615. <bitOffset>6</bitOffset>
  4616. <bitWidth>1</bitWidth>
  4617. <access>read-only</access>
  4618. </field>
  4619. <field>
  4620. <name>RSF</name>
  4621. <description>Registers synchronization flag</description>
  4622. <bitOffset>5</bitOffset>
  4623. <bitWidth>1</bitWidth>
  4624. <access>read-write</access>
  4625. </field>
  4626. <field>
  4627. <name>INITS</name>
  4628. <description>Initialization status flag</description>
  4629. <bitOffset>4</bitOffset>
  4630. <bitWidth>1</bitWidth>
  4631. <access>read-only</access>
  4632. </field>
  4633. <field>
  4634. <name>SHPF</name>
  4635. <description>Shift operation pending</description>
  4636. <bitOffset>3</bitOffset>
  4637. <bitWidth>1</bitWidth>
  4638. <access>read-only</access>
  4639. </field>
  4640. <field>
  4641. <name>WUTWF</name>
  4642. <description>Wakeup timer write flag</description>
  4643. <bitOffset>2</bitOffset>
  4644. <bitWidth>1</bitWidth>
  4645. <access>read-only</access>
  4646. </field>
  4647. <field>
  4648. <name>ALRBWF</name>
  4649. <description>Alarm B write flag</description>
  4650. <bitOffset>1</bitOffset>
  4651. <bitWidth>1</bitWidth>
  4652. <access>read-only</access>
  4653. </field>
  4654. <field>
  4655. <name>ALRAWF</name>
  4656. <description>Alarm A write flag</description>
  4657. <bitOffset>0</bitOffset>
  4658. <bitWidth>1</bitWidth>
  4659. <access>read-only</access>
  4660. </field>
  4661. </fields>
  4662. </register>
  4663. <register>
  4664. <name>PRER</name>
  4665. <displayName>PRER</displayName>
  4666. <description>RTC prescaler register</description>
  4667. <addressOffset>0x10</addressOffset>
  4668. <size>0x20</size>
  4669. <access>read-write</access>
  4670. <resetValue>0x00000000</resetValue>
  4671. <fields>
  4672. <field>
  4673. <name>PREDIV_A</name>
  4674. <description>Asynchronous prescaler factor</description>
  4675. <bitOffset>16</bitOffset>
  4676. <bitWidth>7</bitWidth>
  4677. </field>
  4678. <field>
  4679. <name>PREDIV_S</name>
  4680. <description>Synchronous prescaler factor</description>
  4681. <bitOffset>0</bitOffset>
  4682. <bitWidth>16</bitWidth>
  4683. </field>
  4684. </fields>
  4685. </register>
  4686. <register>
  4687. <name>WUTR</name>
  4688. <displayName>WUTR</displayName>
  4689. <description>RTC wakeup timer register</description>
  4690. <addressOffset>0x14</addressOffset>
  4691. <size>0x20</size>
  4692. <access>read-write</access>
  4693. <resetValue>0x00000000</resetValue>
  4694. <fields>
  4695. <field>
  4696. <name>WUT</name>
  4697. <description>Wakeup auto-reload value bits</description>
  4698. <bitOffset>0</bitOffset>
  4699. <bitWidth>16</bitWidth>
  4700. </field>
  4701. </fields>
  4702. </register>
  4703. <register>
  4704. <name>ALRMAR</name>
  4705. <displayName>ALRMAR</displayName>
  4706. <description>RTC alarm A register</description>
  4707. <addressOffset>0x1C</addressOffset>
  4708. <size>0x20</size>
  4709. <access>read-write</access>
  4710. <resetValue>0x00000000</resetValue>
  4711. <fields>
  4712. <field>
  4713. <name>MSK4</name>
  4714. <description>Alarm A date mask</description>
  4715. <bitOffset>31</bitOffset>
  4716. <bitWidth>1</bitWidth>
  4717. </field>
  4718. <field>
  4719. <name>WDSEL</name>
  4720. <description>Week day selection</description>
  4721. <bitOffset>30</bitOffset>
  4722. <bitWidth>1</bitWidth>
  4723. </field>
  4724. <field>
  4725. <name>DT</name>
  4726. <description>Date tens in BCD format.</description>
  4727. <bitOffset>28</bitOffset>
  4728. <bitWidth>2</bitWidth>
  4729. </field>
  4730. <field>
  4731. <name>DU</name>
  4732. <description>Date units or day in BCD format.</description>
  4733. <bitOffset>24</bitOffset>
  4734. <bitWidth>4</bitWidth>
  4735. </field>
  4736. <field>
  4737. <name>MSK3</name>
  4738. <description>Alarm A hours mask</description>
  4739. <bitOffset>23</bitOffset>
  4740. <bitWidth>1</bitWidth>
  4741. </field>
  4742. <field>
  4743. <name>PM</name>
  4744. <description>AM/PM notation</description>
  4745. <bitOffset>22</bitOffset>
  4746. <bitWidth>1</bitWidth>
  4747. </field>
  4748. <field>
  4749. <name>HT</name>
  4750. <description>Hour tens in BCD format.</description>
  4751. <bitOffset>20</bitOffset>
  4752. <bitWidth>2</bitWidth>
  4753. </field>
  4754. <field>
  4755. <name>HU</name>
  4756. <description>Hour units in BCD format.</description>
  4757. <bitOffset>16</bitOffset>
  4758. <bitWidth>4</bitWidth>
  4759. </field>
  4760. <field>
  4761. <name>MSK2</name>
  4762. <description>Alarm A minutes mask</description>
  4763. <bitOffset>15</bitOffset>
  4764. <bitWidth>1</bitWidth>
  4765. </field>
  4766. <field>
  4767. <name>MNT</name>
  4768. <description>Minute tens in BCD format.</description>
  4769. <bitOffset>12</bitOffset>
  4770. <bitWidth>3</bitWidth>
  4771. </field>
  4772. <field>
  4773. <name>MNU</name>
  4774. <description>Minute units in BCD format.</description>
  4775. <bitOffset>8</bitOffset>
  4776. <bitWidth>4</bitWidth>
  4777. </field>
  4778. <field>
  4779. <name>MSK1</name>
  4780. <description>Alarm A seconds mask</description>
  4781. <bitOffset>7</bitOffset>
  4782. <bitWidth>1</bitWidth>
  4783. </field>
  4784. <field>
  4785. <name>ST</name>
  4786. <description>Second tens in BCD format.</description>
  4787. <bitOffset>4</bitOffset>
  4788. <bitWidth>3</bitWidth>
  4789. </field>
  4790. <field>
  4791. <name>SU</name>
  4792. <description>Second units in BCD format.</description>
  4793. <bitOffset>0</bitOffset>
  4794. <bitWidth>4</bitWidth>
  4795. </field>
  4796. </fields>
  4797. </register>
  4798. <register>
  4799. <name>ALRMBR</name>
  4800. <displayName>ALRMBR</displayName>
  4801. <description>RTC alarm B register</description>
  4802. <addressOffset>0x20</addressOffset>
  4803. <size>0x20</size>
  4804. <access>read-write</access>
  4805. <resetValue>0x00000000</resetValue>
  4806. <fields>
  4807. <field>
  4808. <name>MSK4</name>
  4809. <description>Alarm B date mask</description>
  4810. <bitOffset>31</bitOffset>
  4811. <bitWidth>1</bitWidth>
  4812. </field>
  4813. <field>
  4814. <name>WDSEL</name>
  4815. <description>Week day selection</description>
  4816. <bitOffset>30</bitOffset>
  4817. <bitWidth>1</bitWidth>
  4818. </field>
  4819. <field>
  4820. <name>DT</name>
  4821. <description>Date tens in BCD format</description>
  4822. <bitOffset>28</bitOffset>
  4823. <bitWidth>2</bitWidth>
  4824. </field>
  4825. <field>
  4826. <name>DU</name>
  4827. <description>Date units or day in BCD format</description>
  4828. <bitOffset>24</bitOffset>
  4829. <bitWidth>4</bitWidth>
  4830. </field>
  4831. <field>
  4832. <name>MSK3</name>
  4833. <description>Alarm B hours mask</description>
  4834. <bitOffset>23</bitOffset>
  4835. <bitWidth>1</bitWidth>
  4836. </field>
  4837. <field>
  4838. <name>PM</name>
  4839. <description>AM/PM notation</description>
  4840. <bitOffset>22</bitOffset>
  4841. <bitWidth>1</bitWidth>
  4842. </field>
  4843. <field>
  4844. <name>HT</name>
  4845. <description>Hour tens in BCD format</description>
  4846. <bitOffset>20</bitOffset>
  4847. <bitWidth>2</bitWidth>
  4848. </field>
  4849. <field>
  4850. <name>HU</name>
  4851. <description>Hour units in BCD format</description>
  4852. <bitOffset>16</bitOffset>
  4853. <bitWidth>4</bitWidth>
  4854. </field>
  4855. <field>
  4856. <name>MSK2</name>
  4857. <description>Alarm B minutes mask</description>
  4858. <bitOffset>15</bitOffset>
  4859. <bitWidth>1</bitWidth>
  4860. </field>
  4861. <field>
  4862. <name>MNT</name>
  4863. <description>Minute tens in BCD format</description>
  4864. <bitOffset>12</bitOffset>
  4865. <bitWidth>3</bitWidth>
  4866. </field>
  4867. <field>
  4868. <name>MNU</name>
  4869. <description>Minute units in BCD format</description>
  4870. <bitOffset>8</bitOffset>
  4871. <bitWidth>4</bitWidth>
  4872. </field>
  4873. <field>
  4874. <name>MSK1</name>
  4875. <description>Alarm B seconds mask</description>
  4876. <bitOffset>7</bitOffset>
  4877. <bitWidth>1</bitWidth>
  4878. </field>
  4879. <field>
  4880. <name>ST</name>
  4881. <description>Second tens in BCD format</description>
  4882. <bitOffset>4</bitOffset>
  4883. <bitWidth>3</bitWidth>
  4884. </field>
  4885. <field>
  4886. <name>SU</name>
  4887. <description>Second units in BCD format</description>
  4888. <bitOffset>0</bitOffset>
  4889. <bitWidth>4</bitWidth>
  4890. </field>
  4891. </fields>
  4892. </register>
  4893. <register>
  4894. <name>WPR</name>
  4895. <displayName>WPR</displayName>
  4896. <description>write protection register</description>
  4897. <addressOffset>0x24</addressOffset>
  4898. <size>0x20</size>
  4899. <access>write-only</access>
  4900. <resetValue>0x00000000</resetValue>
  4901. <fields>
  4902. <field>
  4903. <name>KEY</name>
  4904. <description>Write protection key</description>
  4905. <bitOffset>0</bitOffset>
  4906. <bitWidth>8</bitWidth>
  4907. </field>
  4908. </fields>
  4909. </register>
  4910. <register>
  4911. <name>SSR</name>
  4912. <displayName>SSR</displayName>
  4913. <description>RTC sub second register</description>
  4914. <addressOffset>0x28</addressOffset>
  4915. <size>0x20</size>
  4916. <access>read-only</access>
  4917. <resetValue>0x00000000</resetValue>
  4918. <fields>
  4919. <field>
  4920. <name>SS</name>
  4921. <description>Sub second value</description>
  4922. <bitOffset>0</bitOffset>
  4923. <bitWidth>16</bitWidth>
  4924. </field>
  4925. </fields>
  4926. </register>
  4927. <register>
  4928. <name>SHIFTR</name>
  4929. <displayName>SHIFTR</displayName>
  4930. <description>RTC shift control register</description>
  4931. <addressOffset>0x2C</addressOffset>
  4932. <size>0x20</size>
  4933. <access>write-only</access>
  4934. <resetValue>0x00000000</resetValue>
  4935. <fields>
  4936. <field>
  4937. <name>ADD1S</name>
  4938. <description>Add one second</description>
  4939. <bitOffset>31</bitOffset>
  4940. <bitWidth>1</bitWidth>
  4941. </field>
  4942. <field>
  4943. <name>SUBFS</name>
  4944. <description>Subtract a fraction of a second</description>
  4945. <bitOffset>0</bitOffset>
  4946. <bitWidth>15</bitWidth>
  4947. </field>
  4948. </fields>
  4949. </register>
  4950. <register>
  4951. <name>TSTR</name>
  4952. <displayName>TSTR</displayName>
  4953. <description>RTC timestamp time register</description>
  4954. <addressOffset>0x30</addressOffset>
  4955. <size>0x20</size>
  4956. <access>read-only</access>
  4957. <resetValue>0x00000000</resetValue>
  4958. <fields>
  4959. <field>
  4960. <name>PM</name>
  4961. <description>AM/PM notation</description>
  4962. <bitOffset>22</bitOffset>
  4963. <bitWidth>1</bitWidth>
  4964. </field>
  4965. <field>
  4966. <name>HT</name>
  4967. <description>Hour tens in BCD format.</description>
  4968. <bitOffset>20</bitOffset>
  4969. <bitWidth>2</bitWidth>
  4970. </field>
  4971. <field>
  4972. <name>HU</name>
  4973. <description>Hour units in BCD format.</description>
  4974. <bitOffset>16</bitOffset>
  4975. <bitWidth>4</bitWidth>
  4976. </field>
  4977. <field>
  4978. <name>MNT</name>
  4979. <description>Minute tens in BCD format.</description>
  4980. <bitOffset>12</bitOffset>
  4981. <bitWidth>3</bitWidth>
  4982. </field>
  4983. <field>
  4984. <name>MNU</name>
  4985. <description>Minute units in BCD format.</description>
  4986. <bitOffset>8</bitOffset>
  4987. <bitWidth>4</bitWidth>
  4988. </field>
  4989. <field>
  4990. <name>ST</name>
  4991. <description>Second tens in BCD format.</description>
  4992. <bitOffset>4</bitOffset>
  4993. <bitWidth>3</bitWidth>
  4994. </field>
  4995. <field>
  4996. <name>SU</name>
  4997. <description>Second units in BCD format.</description>
  4998. <bitOffset>0</bitOffset>
  4999. <bitWidth>4</bitWidth>
  5000. </field>
  5001. </fields>
  5002. </register>
  5003. <register>
  5004. <name>TSDR</name>
  5005. <displayName>TSDR</displayName>
  5006. <description>RTC timestamp date register</description>
  5007. <addressOffset>0x34</addressOffset>
  5008. <size>0x20</size>
  5009. <access>read-only</access>
  5010. <resetValue>0x00000000</resetValue>
  5011. <fields>
  5012. <field>
  5013. <name>WDU</name>
  5014. <description>Week day units</description>
  5015. <bitOffset>13</bitOffset>
  5016. <bitWidth>3</bitWidth>
  5017. </field>
  5018. <field>
  5019. <name>MT</name>
  5020. <description>Month tens in BCD format</description>
  5021. <bitOffset>12</bitOffset>
  5022. <bitWidth>1</bitWidth>
  5023. </field>
  5024. <field>
  5025. <name>MU</name>
  5026. <description>Month units in BCD format</description>
  5027. <bitOffset>8</bitOffset>
  5028. <bitWidth>4</bitWidth>
  5029. </field>
  5030. <field>
  5031. <name>DT</name>
  5032. <description>Date tens in BCD format</description>
  5033. <bitOffset>4</bitOffset>
  5034. <bitWidth>2</bitWidth>
  5035. </field>
  5036. <field>
  5037. <name>DU</name>
  5038. <description>Date units in BCD format</description>
  5039. <bitOffset>0</bitOffset>
  5040. <bitWidth>4</bitWidth>
  5041. </field>
  5042. </fields>
  5043. </register>
  5044. <register>
  5045. <name>TSSSR</name>
  5046. <displayName>TSSSR</displayName>
  5047. <description>RTC time-stamp sub second register</description>
  5048. <addressOffset>0x38</addressOffset>
  5049. <size>0x20</size>
  5050. <access>read-only</access>
  5051. <resetValue>0x00000000</resetValue>
  5052. <fields>
  5053. <field>
  5054. <name>SS</name>
  5055. <description>Sub second value</description>
  5056. <bitOffset>0</bitOffset>
  5057. <bitWidth>16</bitWidth>
  5058. </field>
  5059. </fields>
  5060. </register>
  5061. <register>
  5062. <name>CALR</name>
  5063. <displayName>CALR</displayName>
  5064. <description>RTC calibration register</description>
  5065. <addressOffset>0x3C</addressOffset>
  5066. <size>0x20</size>
  5067. <access>read-write</access>
  5068. <resetValue>0x00000000</resetValue>
  5069. <fields>
  5070. <field>
  5071. <name>CALP</name>
  5072. <description>Increase frequency of RTC by 488.5 ppm</description>
  5073. <bitOffset>15</bitOffset>
  5074. <bitWidth>1</bitWidth>
  5075. </field>
  5076. <field>
  5077. <name>CALW8</name>
  5078. <description>Use an 8-second calibration cycle period</description>
  5079. <bitOffset>14</bitOffset>
  5080. <bitWidth>1</bitWidth>
  5081. </field>
  5082. <field>
  5083. <name>CALW16</name>
  5084. <description>Use a 16-second calibration cycle period</description>
  5085. <bitOffset>13</bitOffset>
  5086. <bitWidth>1</bitWidth>
  5087. </field>
  5088. <field>
  5089. <name>CALM</name>
  5090. <description>Calibration minus</description>
  5091. <bitOffset>0</bitOffset>
  5092. <bitWidth>9</bitWidth>
  5093. </field>
  5094. </fields>
  5095. </register>
  5096. <register>
  5097. <name>TAMPCR</name>
  5098. <displayName>TAMPCR</displayName>
  5099. <description>RTC tamper configuration register</description>
  5100. <addressOffset>0x40</addressOffset>
  5101. <size>0x20</size>
  5102. <access>read-write</access>
  5103. <resetValue>0x00000000</resetValue>
  5104. <fields>
  5105. <field>
  5106. <name>TAMP2MF</name>
  5107. <description>Tamper 2 mask flag</description>
  5108. <bitOffset>21</bitOffset>
  5109. <bitWidth>1</bitWidth>
  5110. </field>
  5111. <field>
  5112. <name>TAMP2NOERASE</name>
  5113. <description>Tamper 2 no erase</description>
  5114. <bitOffset>20</bitOffset>
  5115. <bitWidth>1</bitWidth>
  5116. </field>
  5117. <field>
  5118. <name>TAMP2IE</name>
  5119. <description>Tamper 2 interrupt enable</description>
  5120. <bitOffset>19</bitOffset>
  5121. <bitWidth>1</bitWidth>
  5122. </field>
  5123. <field>
  5124. <name>TAMP1MF</name>
  5125. <description>Tamper 1 mask flag</description>
  5126. <bitOffset>18</bitOffset>
  5127. <bitWidth>1</bitWidth>
  5128. </field>
  5129. <field>
  5130. <name>TAMP1NOERASE</name>
  5131. <description>Tamper 1 no erase</description>
  5132. <bitOffset>17</bitOffset>
  5133. <bitWidth>1</bitWidth>
  5134. </field>
  5135. <field>
  5136. <name>TAMP1IE</name>
  5137. <description>Tamper 1 interrupt enable</description>
  5138. <bitOffset>16</bitOffset>
  5139. <bitWidth>1</bitWidth>
  5140. </field>
  5141. <field>
  5142. <name>TAMPPUDIS</name>
  5143. <description>RTC_TAMPx pull-up disable</description>
  5144. <bitOffset>15</bitOffset>
  5145. <bitWidth>1</bitWidth>
  5146. </field>
  5147. <field>
  5148. <name>TAMPPRCH</name>
  5149. <description>RTC_TAMPx precharge duration</description>
  5150. <bitOffset>13</bitOffset>
  5151. <bitWidth>2</bitWidth>
  5152. </field>
  5153. <field>
  5154. <name>TAMPFLT</name>
  5155. <description>RTC_TAMPx filter count</description>
  5156. <bitOffset>11</bitOffset>
  5157. <bitWidth>2</bitWidth>
  5158. </field>
  5159. <field>
  5160. <name>TAMPFREQ</name>
  5161. <description>Tamper sampling frequency</description>
  5162. <bitOffset>8</bitOffset>
  5163. <bitWidth>3</bitWidth>
  5164. </field>
  5165. <field>
  5166. <name>TAMPTS</name>
  5167. <description>Activate timestamp on tamper detection event</description>
  5168. <bitOffset>7</bitOffset>
  5169. <bitWidth>1</bitWidth>
  5170. </field>
  5171. <field>
  5172. <name>TAMP2_TRG</name>
  5173. <description>Active level for RTC_TAMP2 input</description>
  5174. <bitOffset>4</bitOffset>
  5175. <bitWidth>1</bitWidth>
  5176. </field>
  5177. <field>
  5178. <name>TAMP2E</name>
  5179. <description>RTC_TAMP2 input detection enable</description>
  5180. <bitOffset>3</bitOffset>
  5181. <bitWidth>1</bitWidth>
  5182. </field>
  5183. <field>
  5184. <name>TAMPIE</name>
  5185. <description>Tamper interrupt enable</description>
  5186. <bitOffset>2</bitOffset>
  5187. <bitWidth>1</bitWidth>
  5188. </field>
  5189. <field>
  5190. <name>TAMP1TRG</name>
  5191. <description>Active level for RTC_TAMP1 input</description>
  5192. <bitOffset>1</bitOffset>
  5193. <bitWidth>1</bitWidth>
  5194. </field>
  5195. <field>
  5196. <name>TAMP1E</name>
  5197. <description>RTC_TAMP1 input detection enable</description>
  5198. <bitOffset>0</bitOffset>
  5199. <bitWidth>1</bitWidth>
  5200. </field>
  5201. </fields>
  5202. </register>
  5203. <register>
  5204. <name>ALRMASSR</name>
  5205. <displayName>ALRMASSR</displayName>
  5206. <description>RTC alarm A sub second register</description>
  5207. <addressOffset>0x44</addressOffset>
  5208. <size>0x20</size>
  5209. <access>read-write</access>
  5210. <resetValue>0x00000000</resetValue>
  5211. <fields>
  5212. <field>
  5213. <name>MASKSS</name>
  5214. <description>Mask the most-significant bits starting at this bit</description>
  5215. <bitOffset>24</bitOffset>
  5216. <bitWidth>4</bitWidth>
  5217. </field>
  5218. <field>
  5219. <name>SS</name>
  5220. <description>Sub seconds value</description>
  5221. <bitOffset>0</bitOffset>
  5222. <bitWidth>15</bitWidth>
  5223. </field>
  5224. </fields>
  5225. </register>
  5226. <register>
  5227. <name>ALRMBSSR</name>
  5228. <displayName>ALRMBSSR</displayName>
  5229. <description>RTC alarm B sub second register</description>
  5230. <addressOffset>0x48</addressOffset>
  5231. <size>0x20</size>
  5232. <access>read-write</access>
  5233. <resetValue>0x00000000</resetValue>
  5234. <fields>
  5235. <field>
  5236. <name>MASKSS</name>
  5237. <description>Mask the most-significant bits starting at this bit</description>
  5238. <bitOffset>24</bitOffset>
  5239. <bitWidth>4</bitWidth>
  5240. </field>
  5241. <field>
  5242. <name>SS</name>
  5243. <description>Sub seconds value</description>
  5244. <bitOffset>0</bitOffset>
  5245. <bitWidth>15</bitWidth>
  5246. </field>
  5247. </fields>
  5248. </register>
  5249. <register>
  5250. <name>OR</name>
  5251. <displayName>OR</displayName>
  5252. <description>option register</description>
  5253. <addressOffset>0x4C</addressOffset>
  5254. <size>0x20</size>
  5255. <access>read-write</access>
  5256. <resetValue>0x00000000</resetValue>
  5257. <fields>
  5258. <field>
  5259. <name>RTC_OUT_RMP</name>
  5260. <description>RTC_ALARM on PC13 output type</description>
  5261. <bitOffset>1</bitOffset>
  5262. <bitWidth>1</bitWidth>
  5263. </field>
  5264. <field>
  5265. <name>RTC_ALARM_TYPE</name>
  5266. <description>RTC_ALARM on PC13 output type</description>
  5267. <bitOffset>0</bitOffset>
  5268. <bitWidth>1</bitWidth>
  5269. </field>
  5270. </fields>
  5271. </register>
  5272. <register>
  5273. <name>BKP0R</name>
  5274. <displayName>BKP0R</displayName>
  5275. <description>RTC backup registers</description>
  5276. <addressOffset>0x50</addressOffset>
  5277. <size>0x20</size>
  5278. <access>read-write</access>
  5279. <resetValue>0x00000000</resetValue>
  5280. <fields>
  5281. <field>
  5282. <name>BKP</name>
  5283. <description>BKP</description>
  5284. <bitOffset>0</bitOffset>
  5285. <bitWidth>32</bitWidth>
  5286. </field>
  5287. </fields>
  5288. </register>
  5289. <register>
  5290. <name>BKP1R</name>
  5291. <displayName>BKP1R</displayName>
  5292. <description>RTC backup registers</description>
  5293. <addressOffset>0x54</addressOffset>
  5294. <size>0x20</size>
  5295. <access>read-write</access>
  5296. <resetValue>0x00000000</resetValue>
  5297. <fields>
  5298. <field>
  5299. <name>BKP</name>
  5300. <description>BKP</description>
  5301. <bitOffset>0</bitOffset>
  5302. <bitWidth>32</bitWidth>
  5303. </field>
  5304. </fields>
  5305. </register>
  5306. <register>
  5307. <name>BKP2R</name>
  5308. <displayName>BKP2R</displayName>
  5309. <description>RTC backup registers</description>
  5310. <addressOffset>0x58</addressOffset>
  5311. <size>0x20</size>
  5312. <access>read-write</access>
  5313. <resetValue>0x00000000</resetValue>
  5314. <fields>
  5315. <field>
  5316. <name>BKP</name>
  5317. <description>BKP</description>
  5318. <bitOffset>0</bitOffset>
  5319. <bitWidth>32</bitWidth>
  5320. </field>
  5321. </fields>
  5322. </register>
  5323. <register>
  5324. <name>BKP3R</name>
  5325. <displayName>BKP3R</displayName>
  5326. <description>RTC backup registers</description>
  5327. <addressOffset>0x5C</addressOffset>
  5328. <size>0x20</size>
  5329. <access>read-write</access>
  5330. <resetValue>0x00000000</resetValue>
  5331. <fields>
  5332. <field>
  5333. <name>BKP</name>
  5334. <description>BKP</description>
  5335. <bitOffset>0</bitOffset>
  5336. <bitWidth>32</bitWidth>
  5337. </field>
  5338. </fields>
  5339. </register>
  5340. <register>
  5341. <name>BKP4R</name>
  5342. <displayName>BKP4R</displayName>
  5343. <description>RTC backup registers</description>
  5344. <addressOffset>0x60</addressOffset>
  5345. <size>0x20</size>
  5346. <access>read-write</access>
  5347. <resetValue>0x00000000</resetValue>
  5348. <fields>
  5349. <field>
  5350. <name>BKP</name>
  5351. <description>BKP</description>
  5352. <bitOffset>0</bitOffset>
  5353. <bitWidth>32</bitWidth>
  5354. </field>
  5355. </fields>
  5356. </register>
  5357. </registers>
  5358. </peripheral>
  5359. <peripheral>
  5360. <name>USART2</name>
  5361. <description>Universal synchronous asynchronous receiver transmitter</description>
  5362. <groupName>USART</groupName>
  5363. <baseAddress>0x40004400</baseAddress>
  5364. <addressBlock>
  5365. <offset>0x0</offset>
  5366. <size>0x400</size>
  5367. <usage>registers</usage>
  5368. </addressBlock>
  5369. <registers>
  5370. <register>
  5371. <name>CR1</name>
  5372. <displayName>CR1</displayName>
  5373. <description>Control register 1</description>
  5374. <addressOffset>0x0</addressOffset>
  5375. <size>0x20</size>
  5376. <access>read-write</access>
  5377. <resetValue>0x0000</resetValue>
  5378. <fields>
  5379. <field>
  5380. <name>M1</name>
  5381. <description>Word length</description>
  5382. <bitOffset>28</bitOffset>
  5383. <bitWidth>1</bitWidth>
  5384. </field>
  5385. <field>
  5386. <name>EOBIE</name>
  5387. <description>End of Block interrupt enable</description>
  5388. <bitOffset>27</bitOffset>
  5389. <bitWidth>1</bitWidth>
  5390. </field>
  5391. <field>
  5392. <name>RTOIE</name>
  5393. <description>Receiver timeout interrupt enable</description>
  5394. <bitOffset>26</bitOffset>
  5395. <bitWidth>1</bitWidth>
  5396. </field>
  5397. <field>
  5398. <name>DEAT4</name>
  5399. <description>Driver Enable assertion time</description>
  5400. <bitOffset>25</bitOffset>
  5401. <bitWidth>1</bitWidth>
  5402. </field>
  5403. <field>
  5404. <name>DEAT3</name>
  5405. <description>DEAT3</description>
  5406. <bitOffset>24</bitOffset>
  5407. <bitWidth>1</bitWidth>
  5408. </field>
  5409. <field>
  5410. <name>DEAT2</name>
  5411. <description>DEAT2</description>
  5412. <bitOffset>23</bitOffset>
  5413. <bitWidth>1</bitWidth>
  5414. </field>
  5415. <field>
  5416. <name>DEAT1</name>
  5417. <description>DEAT1</description>
  5418. <bitOffset>22</bitOffset>
  5419. <bitWidth>1</bitWidth>
  5420. </field>
  5421. <field>
  5422. <name>DEAT0</name>
  5423. <description>DEAT0</description>
  5424. <bitOffset>21</bitOffset>
  5425. <bitWidth>1</bitWidth>
  5426. </field>
  5427. <field>
  5428. <name>DEDT4</name>
  5429. <description>Driver Enable de-assertion time</description>
  5430. <bitOffset>20</bitOffset>
  5431. <bitWidth>1</bitWidth>
  5432. </field>
  5433. <field>
  5434. <name>DEDT3</name>
  5435. <description>DEDT3</description>
  5436. <bitOffset>19</bitOffset>
  5437. <bitWidth>1</bitWidth>
  5438. </field>
  5439. <field>
  5440. <name>DEDT2</name>
  5441. <description>DEDT2</description>
  5442. <bitOffset>18</bitOffset>
  5443. <bitWidth>1</bitWidth>
  5444. </field>
  5445. <field>
  5446. <name>DEDT1</name>
  5447. <description>DEDT1</description>
  5448. <bitOffset>17</bitOffset>
  5449. <bitWidth>1</bitWidth>
  5450. </field>
  5451. <field>
  5452. <name>DEDT0</name>
  5453. <description>DEDT0</description>
  5454. <bitOffset>16</bitOffset>
  5455. <bitWidth>1</bitWidth>
  5456. </field>
  5457. <field>
  5458. <name>OVER8</name>
  5459. <description>Oversampling mode</description>
  5460. <bitOffset>15</bitOffset>
  5461. <bitWidth>1</bitWidth>
  5462. </field>
  5463. <field>
  5464. <name>CMIE</name>
  5465. <description>Character match interrupt enable</description>
  5466. <bitOffset>14</bitOffset>
  5467. <bitWidth>1</bitWidth>
  5468. </field>
  5469. <field>
  5470. <name>MME</name>
  5471. <description>Mute mode enable</description>
  5472. <bitOffset>13</bitOffset>
  5473. <bitWidth>1</bitWidth>
  5474. </field>
  5475. <field>
  5476. <name>M0</name>
  5477. <description>Word length</description>
  5478. <bitOffset>12</bitOffset>
  5479. <bitWidth>1</bitWidth>
  5480. </field>
  5481. <field>
  5482. <name>WAKE</name>
  5483. <description>Receiver wakeup method</description>
  5484. <bitOffset>11</bitOffset>
  5485. <bitWidth>1</bitWidth>
  5486. </field>
  5487. <field>
  5488. <name>PCE</name>
  5489. <description>Parity control enable</description>
  5490. <bitOffset>10</bitOffset>
  5491. <bitWidth>1</bitWidth>
  5492. </field>
  5493. <field>
  5494. <name>PS</name>
  5495. <description>Parity selection</description>
  5496. <bitOffset>9</bitOffset>
  5497. <bitWidth>1</bitWidth>
  5498. </field>
  5499. <field>
  5500. <name>PEIE</name>
  5501. <description>PE interrupt enable</description>
  5502. <bitOffset>8</bitOffset>
  5503. <bitWidth>1</bitWidth>
  5504. </field>
  5505. <field>
  5506. <name>TXEIE</name>
  5507. <description>interrupt enable</description>
  5508. <bitOffset>7</bitOffset>
  5509. <bitWidth>1</bitWidth>
  5510. </field>
  5511. <field>
  5512. <name>TCIE</name>
  5513. <description>Transmission complete interrupt enable</description>
  5514. <bitOffset>6</bitOffset>
  5515. <bitWidth>1</bitWidth>
  5516. </field>
  5517. <field>
  5518. <name>RXNEIE</name>
  5519. <description>RXNE interrupt enable</description>
  5520. <bitOffset>5</bitOffset>
  5521. <bitWidth>1</bitWidth>
  5522. </field>
  5523. <field>
  5524. <name>IDLEIE</name>
  5525. <description>IDLE interrupt enable</description>
  5526. <bitOffset>4</bitOffset>
  5527. <bitWidth>1</bitWidth>
  5528. </field>
  5529. <field>
  5530. <name>TE</name>
  5531. <description>Transmitter enable</description>
  5532. <bitOffset>3</bitOffset>
  5533. <bitWidth>1</bitWidth>
  5534. </field>
  5535. <field>
  5536. <name>RE</name>
  5537. <description>Receiver enable</description>
  5538. <bitOffset>2</bitOffset>
  5539. <bitWidth>1</bitWidth>
  5540. </field>
  5541. <field>
  5542. <name>UESM</name>
  5543. <description>USART enable in Stop mode</description>
  5544. <bitOffset>1</bitOffset>
  5545. <bitWidth>1</bitWidth>
  5546. </field>
  5547. <field>
  5548. <name>UE</name>
  5549. <description>USART enable</description>
  5550. <bitOffset>0</bitOffset>
  5551. <bitWidth>1</bitWidth>
  5552. </field>
  5553. </fields>
  5554. </register>
  5555. <register>
  5556. <name>CR2</name>
  5557. <displayName>CR2</displayName>
  5558. <description>Control register 2</description>
  5559. <addressOffset>0x4</addressOffset>
  5560. <size>0x20</size>
  5561. <access>read-write</access>
  5562. <resetValue>0x0000</resetValue>
  5563. <fields>
  5564. <field>
  5565. <name>ADD4_7</name>
  5566. <description>Address of the USART node</description>
  5567. <bitOffset>28</bitOffset>
  5568. <bitWidth>4</bitWidth>
  5569. </field>
  5570. <field>
  5571. <name>ADD0_3</name>
  5572. <description>Address of the USART node</description>
  5573. <bitOffset>24</bitOffset>
  5574. <bitWidth>4</bitWidth>
  5575. </field>
  5576. <field>
  5577. <name>RTOEN</name>
  5578. <description>Receiver timeout enable</description>
  5579. <bitOffset>23</bitOffset>
  5580. <bitWidth>1</bitWidth>
  5581. </field>
  5582. <field>
  5583. <name>ABRMOD1</name>
  5584. <description>Auto baud rate mode</description>
  5585. <bitOffset>22</bitOffset>
  5586. <bitWidth>1</bitWidth>
  5587. </field>
  5588. <field>
  5589. <name>ABRMOD0</name>
  5590. <description>ABRMOD0</description>
  5591. <bitOffset>21</bitOffset>
  5592. <bitWidth>1</bitWidth>
  5593. </field>
  5594. <field>
  5595. <name>ABREN</name>
  5596. <description>Auto baud rate enable</description>
  5597. <bitOffset>20</bitOffset>
  5598. <bitWidth>1</bitWidth>
  5599. </field>
  5600. <field>
  5601. <name>MSBFIRST</name>
  5602. <description>Most significant bit first</description>
  5603. <bitOffset>19</bitOffset>
  5604. <bitWidth>1</bitWidth>
  5605. </field>
  5606. <field>
  5607. <name>TAINV</name>
  5608. <description>Binary data inversion</description>
  5609. <bitOffset>18</bitOffset>
  5610. <bitWidth>1</bitWidth>
  5611. </field>
  5612. <field>
  5613. <name>TXINV</name>
  5614. <description>TX pin active level inversion</description>
  5615. <bitOffset>17</bitOffset>
  5616. <bitWidth>1</bitWidth>
  5617. </field>
  5618. <field>
  5619. <name>RXINV</name>
  5620. <description>RX pin active level inversion</description>
  5621. <bitOffset>16</bitOffset>
  5622. <bitWidth>1</bitWidth>
  5623. </field>
  5624. <field>
  5625. <name>SWAP</name>
  5626. <description>Swap TX/RX pins</description>
  5627. <bitOffset>15</bitOffset>
  5628. <bitWidth>1</bitWidth>
  5629. </field>
  5630. <field>
  5631. <name>LINEN</name>
  5632. <description>LIN mode enable</description>
  5633. <bitOffset>14</bitOffset>
  5634. <bitWidth>1</bitWidth>
  5635. </field>
  5636. <field>
  5637. <name>STOP</name>
  5638. <description>STOP bits</description>
  5639. <bitOffset>12</bitOffset>
  5640. <bitWidth>2</bitWidth>
  5641. </field>
  5642. <field>
  5643. <name>CLKEN</name>
  5644. <description>Clock enable</description>
  5645. <bitOffset>11</bitOffset>
  5646. <bitWidth>1</bitWidth>
  5647. </field>
  5648. <field>
  5649. <name>CPOL</name>
  5650. <description>Clock polarity</description>
  5651. <bitOffset>10</bitOffset>
  5652. <bitWidth>1</bitWidth>
  5653. </field>
  5654. <field>
  5655. <name>CPHA</name>
  5656. <description>Clock phase</description>
  5657. <bitOffset>9</bitOffset>
  5658. <bitWidth>1</bitWidth>
  5659. </field>
  5660. <field>
  5661. <name>LBCL</name>
  5662. <description>Last bit clock pulse</description>
  5663. <bitOffset>8</bitOffset>
  5664. <bitWidth>1</bitWidth>
  5665. </field>
  5666. <field>
  5667. <name>LBDIE</name>
  5668. <description>LIN break detection interrupt enable</description>
  5669. <bitOffset>6</bitOffset>
  5670. <bitWidth>1</bitWidth>
  5671. </field>
  5672. <field>
  5673. <name>LBDL</name>
  5674. <description>LIN break detection length</description>
  5675. <bitOffset>5</bitOffset>
  5676. <bitWidth>1</bitWidth>
  5677. </field>
  5678. <field>
  5679. <name>ADDM7</name>
  5680. <description>7-bit Address Detection/4-bit Address Detection</description>
  5681. <bitOffset>4</bitOffset>
  5682. <bitWidth>1</bitWidth>
  5683. </field>
  5684. </fields>
  5685. </register>
  5686. <register>
  5687. <name>CR3</name>
  5688. <displayName>CR3</displayName>
  5689. <description>Control register 3</description>
  5690. <addressOffset>0x8</addressOffset>
  5691. <size>0x20</size>
  5692. <access>read-write</access>
  5693. <resetValue>0x0000</resetValue>
  5694. <fields>
  5695. <field>
  5696. <name>WUFIE</name>
  5697. <description>Wakeup from Stop mode interrupt enable</description>
  5698. <bitOffset>22</bitOffset>
  5699. <bitWidth>1</bitWidth>
  5700. </field>
  5701. <field>
  5702. <name>WUS</name>
  5703. <description>Wakeup from Stop mode interrupt flag selection</description>
  5704. <bitOffset>20</bitOffset>
  5705. <bitWidth>2</bitWidth>
  5706. </field>
  5707. <field>
  5708. <name>SCARCNT</name>
  5709. <description>Smartcard auto-retry count</description>
  5710. <bitOffset>17</bitOffset>
  5711. <bitWidth>3</bitWidth>
  5712. </field>
  5713. <field>
  5714. <name>DEP</name>
  5715. <description>Driver enable polarity selection</description>
  5716. <bitOffset>15</bitOffset>
  5717. <bitWidth>1</bitWidth>
  5718. </field>
  5719. <field>
  5720. <name>DEM</name>
  5721. <description>Driver enable mode</description>
  5722. <bitOffset>14</bitOffset>
  5723. <bitWidth>1</bitWidth>
  5724. </field>
  5725. <field>
  5726. <name>DDRE</name>
  5727. <description>DMA Disable on Reception Error</description>
  5728. <bitOffset>13</bitOffset>
  5729. <bitWidth>1</bitWidth>
  5730. </field>
  5731. <field>
  5732. <name>OVRDIS</name>
  5733. <description>Overrun Disable</description>
  5734. <bitOffset>12</bitOffset>
  5735. <bitWidth>1</bitWidth>
  5736. </field>
  5737. <field>
  5738. <name>ONEBIT</name>
  5739. <description>One sample bit method enable</description>
  5740. <bitOffset>11</bitOffset>
  5741. <bitWidth>1</bitWidth>
  5742. </field>
  5743. <field>
  5744. <name>CTSIE</name>
  5745. <description>CTS interrupt enable</description>
  5746. <bitOffset>10</bitOffset>
  5747. <bitWidth>1</bitWidth>
  5748. </field>
  5749. <field>
  5750. <name>CTSE</name>
  5751. <description>CTS enable</description>
  5752. <bitOffset>9</bitOffset>
  5753. <bitWidth>1</bitWidth>
  5754. </field>
  5755. <field>
  5756. <name>RTSE</name>
  5757. <description>RTS enable</description>
  5758. <bitOffset>8</bitOffset>
  5759. <bitWidth>1</bitWidth>
  5760. </field>
  5761. <field>
  5762. <name>DMAT</name>
  5763. <description>DMA enable transmitter</description>
  5764. <bitOffset>7</bitOffset>
  5765. <bitWidth>1</bitWidth>
  5766. </field>
  5767. <field>
  5768. <name>DMAR</name>
  5769. <description>DMA enable receiver</description>
  5770. <bitOffset>6</bitOffset>
  5771. <bitWidth>1</bitWidth>
  5772. </field>
  5773. <field>
  5774. <name>SCEN</name>
  5775. <description>Smartcard mode enable</description>
  5776. <bitOffset>5</bitOffset>
  5777. <bitWidth>1</bitWidth>
  5778. </field>
  5779. <field>
  5780. <name>NACK</name>
  5781. <description>Smartcard NACK enable</description>
  5782. <bitOffset>4</bitOffset>
  5783. <bitWidth>1</bitWidth>
  5784. </field>
  5785. <field>
  5786. <name>HDSEL</name>
  5787. <description>Half-duplex selection</description>
  5788. <bitOffset>3</bitOffset>
  5789. <bitWidth>1</bitWidth>
  5790. </field>
  5791. <field>
  5792. <name>IRLP</name>
  5793. <description>Ir low-power</description>
  5794. <bitOffset>2</bitOffset>
  5795. <bitWidth>1</bitWidth>
  5796. </field>
  5797. <field>
  5798. <name>IREN</name>
  5799. <description>Ir mode enable</description>
  5800. <bitOffset>1</bitOffset>
  5801. <bitWidth>1</bitWidth>
  5802. </field>
  5803. <field>
  5804. <name>EIE</name>
  5805. <description>Error interrupt enable</description>
  5806. <bitOffset>0</bitOffset>
  5807. <bitWidth>1</bitWidth>
  5808. </field>
  5809. </fields>
  5810. </register>
  5811. <register>
  5812. <name>BRR</name>
  5813. <displayName>BRR</displayName>
  5814. <description>Baud rate register</description>
  5815. <addressOffset>0xC</addressOffset>
  5816. <size>0x20</size>
  5817. <access>read-write</access>
  5818. <resetValue>0x0000</resetValue>
  5819. <fields>
  5820. <field>
  5821. <name>DIV_Mantissa</name>
  5822. <description>DIV_Mantissa</description>
  5823. <bitOffset>4</bitOffset>
  5824. <bitWidth>12</bitWidth>
  5825. </field>
  5826. <field>
  5827. <name>DIV_Fraction</name>
  5828. <description>DIV_Fraction</description>
  5829. <bitOffset>0</bitOffset>
  5830. <bitWidth>4</bitWidth>
  5831. </field>
  5832. </fields>
  5833. </register>
  5834. <register>
  5835. <name>GTPR</name>
  5836. <displayName>GTPR</displayName>
  5837. <description>Guard time and prescaler register</description>
  5838. <addressOffset>0x10</addressOffset>
  5839. <size>0x20</size>
  5840. <access>read-write</access>
  5841. <resetValue>0x0000</resetValue>
  5842. <fields>
  5843. <field>
  5844. <name>GT</name>
  5845. <description>Guard time value</description>
  5846. <bitOffset>8</bitOffset>
  5847. <bitWidth>8</bitWidth>
  5848. </field>
  5849. <field>
  5850. <name>PSC</name>
  5851. <description>Prescaler value</description>
  5852. <bitOffset>0</bitOffset>
  5853. <bitWidth>8</bitWidth>
  5854. </field>
  5855. </fields>
  5856. </register>
  5857. <register>
  5858. <name>RTOR</name>
  5859. <displayName>RTOR</displayName>
  5860. <description>Receiver timeout register</description>
  5861. <addressOffset>0x14</addressOffset>
  5862. <size>0x20</size>
  5863. <access>read-write</access>
  5864. <resetValue>0x0000</resetValue>
  5865. <fields>
  5866. <field>
  5867. <name>BLEN</name>
  5868. <description>Block Length</description>
  5869. <bitOffset>24</bitOffset>
  5870. <bitWidth>8</bitWidth>
  5871. </field>
  5872. <field>
  5873. <name>RTO</name>
  5874. <description>Receiver timeout value</description>
  5875. <bitOffset>0</bitOffset>
  5876. <bitWidth>24</bitWidth>
  5877. </field>
  5878. </fields>
  5879. </register>
  5880. <register>
  5881. <name>RQR</name>
  5882. <displayName>RQR</displayName>
  5883. <description>Request register</description>
  5884. <addressOffset>0x18</addressOffset>
  5885. <size>0x20</size>
  5886. <access>write-only</access>
  5887. <resetValue>0x0000</resetValue>
  5888. <fields>
  5889. <field>
  5890. <name>TXFRQ</name>
  5891. <description>Transmit data flush request</description>
  5892. <bitOffset>4</bitOffset>
  5893. <bitWidth>1</bitWidth>
  5894. </field>
  5895. <field>
  5896. <name>RXFRQ</name>
  5897. <description>Receive data flush request</description>
  5898. <bitOffset>3</bitOffset>
  5899. <bitWidth>1</bitWidth>
  5900. </field>
  5901. <field>
  5902. <name>MMRQ</name>
  5903. <description>Mute mode request</description>
  5904. <bitOffset>2</bitOffset>
  5905. <bitWidth>1</bitWidth>
  5906. </field>
  5907. <field>
  5908. <name>SBKRQ</name>
  5909. <description>Send break request</description>
  5910. <bitOffset>1</bitOffset>
  5911. <bitWidth>1</bitWidth>
  5912. </field>
  5913. <field>
  5914. <name>ABRRQ</name>
  5915. <description>Auto baud rate request</description>
  5916. <bitOffset>0</bitOffset>
  5917. <bitWidth>1</bitWidth>
  5918. </field>
  5919. </fields>
  5920. </register>
  5921. <register>
  5922. <name>ISR</name>
  5923. <displayName>ISR</displayName>
  5924. <description>Interrupt &amp; status register</description>
  5925. <addressOffset>0x1C</addressOffset>
  5926. <size>0x20</size>
  5927. <access>read-only</access>
  5928. <resetValue>0x00C0</resetValue>
  5929. <fields>
  5930. <field>
  5931. <name>REACK</name>
  5932. <description>REACK</description>
  5933. <bitOffset>22</bitOffset>
  5934. <bitWidth>1</bitWidth>
  5935. </field>
  5936. <field>
  5937. <name>TEACK</name>
  5938. <description>TEACK</description>
  5939. <bitOffset>21</bitOffset>
  5940. <bitWidth>1</bitWidth>
  5941. </field>
  5942. <field>
  5943. <name>WUF</name>
  5944. <description>WUF</description>
  5945. <bitOffset>20</bitOffset>
  5946. <bitWidth>1</bitWidth>
  5947. </field>
  5948. <field>
  5949. <name>RWU</name>
  5950. <description>RWU</description>
  5951. <bitOffset>19</bitOffset>
  5952. <bitWidth>1</bitWidth>
  5953. </field>
  5954. <field>
  5955. <name>SBKF</name>
  5956. <description>SBKF</description>
  5957. <bitOffset>18</bitOffset>
  5958. <bitWidth>1</bitWidth>
  5959. </field>
  5960. <field>
  5961. <name>CMF</name>
  5962. <description>CMF</description>
  5963. <bitOffset>17</bitOffset>
  5964. <bitWidth>1</bitWidth>
  5965. </field>
  5966. <field>
  5967. <name>BUSY</name>
  5968. <description>BUSY</description>
  5969. <bitOffset>16</bitOffset>
  5970. <bitWidth>1</bitWidth>
  5971. </field>
  5972. <field>
  5973. <name>ABRF</name>
  5974. <description>ABRF</description>
  5975. <bitOffset>15</bitOffset>
  5976. <bitWidth>1</bitWidth>
  5977. </field>
  5978. <field>
  5979. <name>ABRE</name>
  5980. <description>ABRE</description>
  5981. <bitOffset>14</bitOffset>
  5982. <bitWidth>1</bitWidth>
  5983. </field>
  5984. <field>
  5985. <name>EOBF</name>
  5986. <description>EOBF</description>
  5987. <bitOffset>12</bitOffset>
  5988. <bitWidth>1</bitWidth>
  5989. </field>
  5990. <field>
  5991. <name>RTOF</name>
  5992. <description>RTOF</description>
  5993. <bitOffset>11</bitOffset>
  5994. <bitWidth>1</bitWidth>
  5995. </field>
  5996. <field>
  5997. <name>CTS</name>
  5998. <description>CTS</description>
  5999. <bitOffset>10</bitOffset>
  6000. <bitWidth>1</bitWidth>
  6001. </field>
  6002. <field>
  6003. <name>CTSIF</name>
  6004. <description>CTSIF</description>
  6005. <bitOffset>9</bitOffset>
  6006. <bitWidth>1</bitWidth>
  6007. </field>
  6008. <field>
  6009. <name>LBDF</name>
  6010. <description>LBDF</description>
  6011. <bitOffset>8</bitOffset>
  6012. <bitWidth>1</bitWidth>
  6013. </field>
  6014. <field>
  6015. <name>TXE</name>
  6016. <description>TXE</description>
  6017. <bitOffset>7</bitOffset>
  6018. <bitWidth>1</bitWidth>
  6019. </field>
  6020. <field>
  6021. <name>TC</name>
  6022. <description>TC</description>
  6023. <bitOffset>6</bitOffset>
  6024. <bitWidth>1</bitWidth>
  6025. </field>
  6026. <field>
  6027. <name>RXNE</name>
  6028. <description>RXNE</description>
  6029. <bitOffset>5</bitOffset>
  6030. <bitWidth>1</bitWidth>
  6031. </field>
  6032. <field>
  6033. <name>IDLE</name>
  6034. <description>IDLE</description>
  6035. <bitOffset>4</bitOffset>
  6036. <bitWidth>1</bitWidth>
  6037. </field>
  6038. <field>
  6039. <name>ORE</name>
  6040. <description>ORE</description>
  6041. <bitOffset>3</bitOffset>
  6042. <bitWidth>1</bitWidth>
  6043. </field>
  6044. <field>
  6045. <name>NF</name>
  6046. <description>NF</description>
  6047. <bitOffset>2</bitOffset>
  6048. <bitWidth>1</bitWidth>
  6049. </field>
  6050. <field>
  6051. <name>FE</name>
  6052. <description>FE</description>
  6053. <bitOffset>1</bitOffset>
  6054. <bitWidth>1</bitWidth>
  6055. </field>
  6056. <field>
  6057. <name>PE</name>
  6058. <description>PE</description>
  6059. <bitOffset>0</bitOffset>
  6060. <bitWidth>1</bitWidth>
  6061. </field>
  6062. </fields>
  6063. </register>
  6064. <register>
  6065. <name>ICR</name>
  6066. <displayName>ICR</displayName>
  6067. <description>Interrupt flag clear register</description>
  6068. <addressOffset>0x20</addressOffset>
  6069. <size>0x20</size>
  6070. <access>write-only</access>
  6071. <resetValue>0x0000</resetValue>
  6072. <fields>
  6073. <field>
  6074. <name>WUCF</name>
  6075. <description>Wakeup from Stop mode clear flag</description>
  6076. <bitOffset>20</bitOffset>
  6077. <bitWidth>1</bitWidth>
  6078. </field>
  6079. <field>
  6080. <name>CMCF</name>
  6081. <description>Character match clear flag</description>
  6082. <bitOffset>17</bitOffset>
  6083. <bitWidth>1</bitWidth>
  6084. </field>
  6085. <field>
  6086. <name>EOBCF</name>
  6087. <description>End of block clear flag</description>
  6088. <bitOffset>12</bitOffset>
  6089. <bitWidth>1</bitWidth>
  6090. </field>
  6091. <field>
  6092. <name>RTOCF</name>
  6093. <description>Receiver timeout clear flag</description>
  6094. <bitOffset>11</bitOffset>
  6095. <bitWidth>1</bitWidth>
  6096. </field>
  6097. <field>
  6098. <name>CTSCF</name>
  6099. <description>CTS clear flag</description>
  6100. <bitOffset>9</bitOffset>
  6101. <bitWidth>1</bitWidth>
  6102. </field>
  6103. <field>
  6104. <name>LBDCF</name>
  6105. <description>LIN break detection clear flag</description>
  6106. <bitOffset>8</bitOffset>
  6107. <bitWidth>1</bitWidth>
  6108. </field>
  6109. <field>
  6110. <name>TCCF</name>
  6111. <description>Transmission complete clear flag</description>
  6112. <bitOffset>6</bitOffset>
  6113. <bitWidth>1</bitWidth>
  6114. </field>
  6115. <field>
  6116. <name>IDLECF</name>
  6117. <description>Idle line detected clear flag</description>
  6118. <bitOffset>4</bitOffset>
  6119. <bitWidth>1</bitWidth>
  6120. </field>
  6121. <field>
  6122. <name>ORECF</name>
  6123. <description>Overrun error clear flag</description>
  6124. <bitOffset>3</bitOffset>
  6125. <bitWidth>1</bitWidth>
  6126. </field>
  6127. <field>
  6128. <name>NCF</name>
  6129. <description>Noise detected clear flag</description>
  6130. <bitOffset>2</bitOffset>
  6131. <bitWidth>1</bitWidth>
  6132. </field>
  6133. <field>
  6134. <name>FECF</name>
  6135. <description>Framing error clear flag</description>
  6136. <bitOffset>1</bitOffset>
  6137. <bitWidth>1</bitWidth>
  6138. </field>
  6139. <field>
  6140. <name>PECF</name>
  6141. <description>Parity error clear flag</description>
  6142. <bitOffset>0</bitOffset>
  6143. <bitWidth>1</bitWidth>
  6144. </field>
  6145. </fields>
  6146. </register>
  6147. <register>
  6148. <name>RDR</name>
  6149. <displayName>RDR</displayName>
  6150. <description>Receive data register</description>
  6151. <addressOffset>0x24</addressOffset>
  6152. <size>0x20</size>
  6153. <access>read-only</access>
  6154. <resetValue>0x0000</resetValue>
  6155. <fields>
  6156. <field>
  6157. <name>RDR</name>
  6158. <description>Receive data value</description>
  6159. <bitOffset>0</bitOffset>
  6160. <bitWidth>9</bitWidth>
  6161. </field>
  6162. </fields>
  6163. </register>
  6164. <register>
  6165. <name>TDR</name>
  6166. <displayName>TDR</displayName>
  6167. <description>Transmit data register</description>
  6168. <addressOffset>0x28</addressOffset>
  6169. <size>0x20</size>
  6170. <access>read-write</access>
  6171. <resetValue>0x0000</resetValue>
  6172. <fields>
  6173. <field>
  6174. <name>TDR</name>
  6175. <description>Transmit data value</description>
  6176. <bitOffset>0</bitOffset>
  6177. <bitWidth>9</bitWidth>
  6178. </field>
  6179. </fields>
  6180. </register>
  6181. </registers>
  6182. </peripheral>
  6183. <peripheral>
  6184. <name>IWDG</name>
  6185. <description>Independent watchdog</description>
  6186. <groupName>IWDG</groupName>
  6187. <baseAddress>0x40003000</baseAddress>
  6188. <addressBlock>
  6189. <offset>0x0</offset>
  6190. <size>0x400</size>
  6191. <usage>registers</usage>
  6192. </addressBlock>
  6193. <interrupt>
  6194. <name>USART2</name>
  6195. <description>USART2 global interrupt</description>
  6196. <value>28</value>
  6197. </interrupt>
  6198. <registers>
  6199. <register>
  6200. <name>KR</name>
  6201. <displayName>KR</displayName>
  6202. <description>Key register</description>
  6203. <addressOffset>0x0</addressOffset>
  6204. <size>0x20</size>
  6205. <access>write-only</access>
  6206. <resetValue>0x00000000</resetValue>
  6207. <fields>
  6208. <field>
  6209. <name>KEY</name>
  6210. <description>Key value (write only, read 0x0000)</description>
  6211. <bitOffset>0</bitOffset>
  6212. <bitWidth>16</bitWidth>
  6213. </field>
  6214. </fields>
  6215. </register>
  6216. <register>
  6217. <name>PR</name>
  6218. <displayName>PR</displayName>
  6219. <description>Prescaler register</description>
  6220. <addressOffset>0x4</addressOffset>
  6221. <size>0x20</size>
  6222. <access>read-write</access>
  6223. <resetValue>0x00000000</resetValue>
  6224. <fields>
  6225. <field>
  6226. <name>PR</name>
  6227. <description>Prescaler divider</description>
  6228. <bitOffset>0</bitOffset>
  6229. <bitWidth>3</bitWidth>
  6230. </field>
  6231. </fields>
  6232. </register>
  6233. <register>
  6234. <name>RLR</name>
  6235. <displayName>RLR</displayName>
  6236. <description>Reload register</description>
  6237. <addressOffset>0x8</addressOffset>
  6238. <size>0x20</size>
  6239. <access>read-write</access>
  6240. <resetValue>0x00000FFF</resetValue>
  6241. <fields>
  6242. <field>
  6243. <name>RL</name>
  6244. <description>Watchdog counter reload value</description>
  6245. <bitOffset>0</bitOffset>
  6246. <bitWidth>12</bitWidth>
  6247. </field>
  6248. </fields>
  6249. </register>
  6250. <register>
  6251. <name>SR</name>
  6252. <displayName>SR</displayName>
  6253. <description>Status register</description>
  6254. <addressOffset>0xC</addressOffset>
  6255. <size>0x20</size>
  6256. <access>read-only</access>
  6257. <resetValue>0x00000000</resetValue>
  6258. <fields>
  6259. <field>
  6260. <name>WVU</name>
  6261. <description>Watchdog counter window value update</description>
  6262. <bitOffset>2</bitOffset>
  6263. <bitWidth>1</bitWidth>
  6264. </field>
  6265. <field>
  6266. <name>RVU</name>
  6267. <description>Watchdog counter reload value update</description>
  6268. <bitOffset>1</bitOffset>
  6269. <bitWidth>1</bitWidth>
  6270. </field>
  6271. <field>
  6272. <name>PVU</name>
  6273. <description>Watchdog prescaler value update</description>
  6274. <bitOffset>0</bitOffset>
  6275. <bitWidth>1</bitWidth>
  6276. </field>
  6277. </fields>
  6278. </register>
  6279. <register>
  6280. <name>WINR</name>
  6281. <displayName>WINR</displayName>
  6282. <description>Window register</description>
  6283. <addressOffset>0x10</addressOffset>
  6284. <size>0x20</size>
  6285. <access>read-write</access>
  6286. <resetValue>0x00000FFF</resetValue>
  6287. <fields>
  6288. <field>
  6289. <name>WIN</name>
  6290. <description>Watchdog counter window value</description>
  6291. <bitOffset>0</bitOffset>
  6292. <bitWidth>12</bitWidth>
  6293. </field>
  6294. </fields>
  6295. </register>
  6296. </registers>
  6297. </peripheral>
  6298. <peripheral>
  6299. <name>WWDG</name>
  6300. <description>System window watchdog</description>
  6301. <groupName>WWDG</groupName>
  6302. <baseAddress>0x40002C00</baseAddress>
  6303. <addressBlock>
  6304. <offset>0x0</offset>
  6305. <size>0x400</size>
  6306. <usage>registers</usage>
  6307. </addressBlock>
  6308. <registers>
  6309. <register>
  6310. <name>CR</name>
  6311. <displayName>CR</displayName>
  6312. <description>Control register</description>
  6313. <addressOffset>0x0</addressOffset>
  6314. <size>0x20</size>
  6315. <access>read-write</access>
  6316. <resetValue>0x0000007F</resetValue>
  6317. <fields>
  6318. <field>
  6319. <name>WDGA</name>
  6320. <description>Activation bit</description>
  6321. <bitOffset>7</bitOffset>
  6322. <bitWidth>1</bitWidth>
  6323. </field>
  6324. <field>
  6325. <name>T</name>
  6326. <description>7-bit counter (MSB to LSB)</description>
  6327. <bitOffset>0</bitOffset>
  6328. <bitWidth>7</bitWidth>
  6329. </field>
  6330. </fields>
  6331. </register>
  6332. <register>
  6333. <name>CFR</name>
  6334. <displayName>CFR</displayName>
  6335. <description>Configuration register</description>
  6336. <addressOffset>0x4</addressOffset>
  6337. <size>0x20</size>
  6338. <access>read-write</access>
  6339. <resetValue>0x0000007F</resetValue>
  6340. <fields>
  6341. <field>
  6342. <name>EWI</name>
  6343. <description>Early wakeup interrupt</description>
  6344. <bitOffset>9</bitOffset>
  6345. <bitWidth>1</bitWidth>
  6346. </field>
  6347. <field>
  6348. <name>WDGTB1</name>
  6349. <description>Timer base</description>
  6350. <bitOffset>8</bitOffset>
  6351. <bitWidth>1</bitWidth>
  6352. </field>
  6353. <field>
  6354. <name>WDGTB0</name>
  6355. <description>WDGTB0</description>
  6356. <bitOffset>7</bitOffset>
  6357. <bitWidth>1</bitWidth>
  6358. </field>
  6359. <field>
  6360. <name>W</name>
  6361. <description>7-bit window value</description>
  6362. <bitOffset>0</bitOffset>
  6363. <bitWidth>7</bitWidth>
  6364. </field>
  6365. </fields>
  6366. </register>
  6367. <register>
  6368. <name>SR</name>
  6369. <displayName>SR</displayName>
  6370. <description>Status register</description>
  6371. <addressOffset>0x8</addressOffset>
  6372. <size>0x20</size>
  6373. <access>read-write</access>
  6374. <resetValue>0x00000000</resetValue>
  6375. <fields>
  6376. <field>
  6377. <name>EWIF</name>
  6378. <description>Early wakeup interrupt flag</description>
  6379. <bitOffset>0</bitOffset>
  6380. <bitWidth>1</bitWidth>
  6381. </field>
  6382. </fields>
  6383. </register>
  6384. </registers>
  6385. </peripheral>
  6386. <peripheral>
  6387. <name>Firewall</name>
  6388. <description>Firewall</description>
  6389. <groupName>Firewall</groupName>
  6390. <baseAddress>0x40011C00</baseAddress>
  6391. <addressBlock>
  6392. <offset>0x0</offset>
  6393. <size>0x400</size>
  6394. <usage>registers</usage>
  6395. </addressBlock>
  6396. <interrupt>
  6397. <name>WWDG</name>
  6398. <description>Window Watchdog interrupt</description>
  6399. <value>0</value>
  6400. </interrupt>
  6401. <registers>
  6402. <register>
  6403. <name>FIREWALL_CSSA</name>
  6404. <displayName>FIREWALL_CSSA</displayName>
  6405. <description>Code segment start address</description>
  6406. <addressOffset>0x0</addressOffset>
  6407. <size>0x20</size>
  6408. <access>read-write</access>
  6409. <resetValue>0x00000000</resetValue>
  6410. <fields>
  6411. <field>
  6412. <name>ADD</name>
  6413. <description>code segment start address</description>
  6414. <bitOffset>8</bitOffset>
  6415. <bitWidth>16</bitWidth>
  6416. </field>
  6417. </fields>
  6418. </register>
  6419. <register>
  6420. <name>FIREWALL_CSL</name>
  6421. <displayName>FIREWALL_CSL</displayName>
  6422. <description>Code segment length</description>
  6423. <addressOffset>0x4</addressOffset>
  6424. <size>0x20</size>
  6425. <access>read-write</access>
  6426. <resetValue>0x00000000</resetValue>
  6427. <fields>
  6428. <field>
  6429. <name>LENG</name>
  6430. <description>code segment length</description>
  6431. <bitOffset>8</bitOffset>
  6432. <bitWidth>14</bitWidth>
  6433. </field>
  6434. </fields>
  6435. </register>
  6436. <register>
  6437. <name>FIREWALL_NVDSSA</name>
  6438. <displayName>FIREWALL_NVDSSA</displayName>
  6439. <description>Non-volatile data segment start address</description>
  6440. <addressOffset>0x8</addressOffset>
  6441. <size>0x20</size>
  6442. <access>read-write</access>
  6443. <resetValue>0x00000000</resetValue>
  6444. <fields>
  6445. <field>
  6446. <name>ADD</name>
  6447. <description>Non-volatile data segment start address</description>
  6448. <bitOffset>8</bitOffset>
  6449. <bitWidth>16</bitWidth>
  6450. </field>
  6451. </fields>
  6452. </register>
  6453. <register>
  6454. <name>FIREWALL_NVDSL</name>
  6455. <displayName>FIREWALL_NVDSL</displayName>
  6456. <description>Non-volatile data segment length</description>
  6457. <addressOffset>0xC</addressOffset>
  6458. <size>0x20</size>
  6459. <access>read-write</access>
  6460. <resetValue>0x00000000</resetValue>
  6461. <fields>
  6462. <field>
  6463. <name>LENG</name>
  6464. <description>Non-volatile data segment length</description>
  6465. <bitOffset>8</bitOffset>
  6466. <bitWidth>14</bitWidth>
  6467. </field>
  6468. </fields>
  6469. </register>
  6470. <register>
  6471. <name>FIREWALL_VDSSA</name>
  6472. <displayName>FIREWALL_VDSSA</displayName>
  6473. <description>Volatile data segment start address</description>
  6474. <addressOffset>0x10</addressOffset>
  6475. <size>0x20</size>
  6476. <access>read-write</access>
  6477. <resetValue>0x00000000</resetValue>
  6478. <fields>
  6479. <field>
  6480. <name>ADD</name>
  6481. <description>Volatile data segment start address</description>
  6482. <bitOffset>6</bitOffset>
  6483. <bitWidth>10</bitWidth>
  6484. </field>
  6485. </fields>
  6486. </register>
  6487. <register>
  6488. <name>FIREWALL_VDSL</name>
  6489. <displayName>FIREWALL_VDSL</displayName>
  6490. <description>Volatile data segment length</description>
  6491. <addressOffset>0x14</addressOffset>
  6492. <size>0x20</size>
  6493. <access>read-write</access>
  6494. <resetValue>0x00000000</resetValue>
  6495. <fields>
  6496. <field>
  6497. <name>LENG</name>
  6498. <description>Non-volatile data segment length</description>
  6499. <bitOffset>6</bitOffset>
  6500. <bitWidth>10</bitWidth>
  6501. </field>
  6502. </fields>
  6503. </register>
  6504. <register>
  6505. <name>FIREWALL_CR</name>
  6506. <displayName>FIREWALL_CR</displayName>
  6507. <description>Configuration register</description>
  6508. <addressOffset>0x20</addressOffset>
  6509. <size>0x20</size>
  6510. <access>read-write</access>
  6511. <resetValue>0x00000000</resetValue>
  6512. <fields>
  6513. <field>
  6514. <name>VDE</name>
  6515. <description>Volatile data execution</description>
  6516. <bitOffset>2</bitOffset>
  6517. <bitWidth>1</bitWidth>
  6518. </field>
  6519. <field>
  6520. <name>VDS</name>
  6521. <description>Volatile data shared</description>
  6522. <bitOffset>1</bitOffset>
  6523. <bitWidth>1</bitWidth>
  6524. </field>
  6525. <field>
  6526. <name>FPA</name>
  6527. <description>Firewall pre alarm</description>
  6528. <bitOffset>0</bitOffset>
  6529. <bitWidth>1</bitWidth>
  6530. </field>
  6531. </fields>
  6532. </register>
  6533. </registers>
  6534. </peripheral>
  6535. <peripheral>
  6536. <name>RCC</name>
  6537. <description>Reset and clock control</description>
  6538. <groupName>RCC</groupName>
  6539. <baseAddress>0x40021000</baseAddress>
  6540. <addressBlock>
  6541. <offset>0x0</offset>
  6542. <size>0x400</size>
  6543. <usage>registers</usage>
  6544. </addressBlock>
  6545. <registers>
  6546. <register>
  6547. <name>CR</name>
  6548. <displayName>CR</displayName>
  6549. <description>Clock control register</description>
  6550. <addressOffset>0x0</addressOffset>
  6551. <size>0x20</size>
  6552. <resetValue>0x00000300</resetValue>
  6553. <fields>
  6554. <field>
  6555. <name>PLLRDY</name>
  6556. <description>PLL clock ready flag</description>
  6557. <bitOffset>25</bitOffset>
  6558. <bitWidth>1</bitWidth>
  6559. <access>read-only</access>
  6560. </field>
  6561. <field>
  6562. <name>PLLON</name>
  6563. <description>PLL enable bit</description>
  6564. <bitOffset>24</bitOffset>
  6565. <bitWidth>1</bitWidth>
  6566. <access>read-write</access>
  6567. </field>
  6568. <field>
  6569. <name>RTCPRE</name>
  6570. <description>TC/LCD prescaler</description>
  6571. <bitOffset>20</bitOffset>
  6572. <bitWidth>2</bitWidth>
  6573. <access>read-write</access>
  6574. </field>
  6575. <field>
  6576. <name>CSSLSEON</name>
  6577. <description>Clock security system on HSE enable bit</description>
  6578. <bitOffset>19</bitOffset>
  6579. <bitWidth>1</bitWidth>
  6580. <access>read-write</access>
  6581. </field>
  6582. <field>
  6583. <name>HSEBYP</name>
  6584. <description>HSE clock bypass bit</description>
  6585. <bitOffset>18</bitOffset>
  6586. <bitWidth>1</bitWidth>
  6587. <access>read-write</access>
  6588. </field>
  6589. <field>
  6590. <name>HSERDY</name>
  6591. <description>HSE clock ready flag</description>
  6592. <bitOffset>17</bitOffset>
  6593. <bitWidth>1</bitWidth>
  6594. <access>read-only</access>
  6595. </field>
  6596. <field>
  6597. <name>HSEON</name>
  6598. <description>HSE clock enable bit</description>
  6599. <bitOffset>16</bitOffset>
  6600. <bitWidth>1</bitWidth>
  6601. <access>read-write</access>
  6602. </field>
  6603. <field>
  6604. <name>MSIRDY</name>
  6605. <description>MSI clock ready flag</description>
  6606. <bitOffset>9</bitOffset>
  6607. <bitWidth>1</bitWidth>
  6608. <access>read-only</access>
  6609. </field>
  6610. <field>
  6611. <name>MSION</name>
  6612. <description>MSI clock enable bit</description>
  6613. <bitOffset>8</bitOffset>
  6614. <bitWidth>1</bitWidth>
  6615. <access>read-write</access>
  6616. </field>
  6617. <field>
  6618. <name>HSI16DIVF</name>
  6619. <description>HSI16DIVF</description>
  6620. <bitOffset>4</bitOffset>
  6621. <bitWidth>1</bitWidth>
  6622. <access>read-only</access>
  6623. </field>
  6624. <field>
  6625. <name>HSI16DIVEN</name>
  6626. <description>HSI16DIVEN</description>
  6627. <bitOffset>3</bitOffset>
  6628. <bitWidth>1</bitWidth>
  6629. <access>read-write</access>
  6630. </field>
  6631. <field>
  6632. <name>HSI16RDYF</name>
  6633. <description>Internal high-speed clock ready flag</description>
  6634. <bitOffset>2</bitOffset>
  6635. <bitWidth>1</bitWidth>
  6636. <access>read-write</access>
  6637. </field>
  6638. <field>
  6639. <name>HSI16KERON</name>
  6640. <description>High-speed internal clock enable bit for some IP kernels</description>
  6641. <bitOffset>1</bitOffset>
  6642. <bitWidth>1</bitWidth>
  6643. <access>read-only</access>
  6644. </field>
  6645. <field>
  6646. <name>HSI16ON</name>
  6647. <description>16 MHz high-speed internal clock enable</description>
  6648. <bitOffset>0</bitOffset>
  6649. <bitWidth>1</bitWidth>
  6650. <access>read-write</access>
  6651. </field>
  6652. <field>
  6653. <name>HSI16OUTEN</name>
  6654. <description>16 MHz high-speed internal clock output enable</description>
  6655. <bitOffset>5</bitOffset>
  6656. <bitWidth>1</bitWidth>
  6657. <access>read-write</access>
  6658. </field>
  6659. </fields>
  6660. </register>
  6661. <register>
  6662. <name>ICSCR</name>
  6663. <displayName>ICSCR</displayName>
  6664. <description>Internal clock sources calibration register</description>
  6665. <addressOffset>0x4</addressOffset>
  6666. <size>0x20</size>
  6667. <resetValue>0x0000B000</resetValue>
  6668. <fields>
  6669. <field>
  6670. <name>MSITRIM</name>
  6671. <description>MSI clock trimming</description>
  6672. <bitOffset>24</bitOffset>
  6673. <bitWidth>8</bitWidth>
  6674. <access>read-write</access>
  6675. </field>
  6676. <field>
  6677. <name>MSICAL</name>
  6678. <description>MSI clock calibration</description>
  6679. <bitOffset>16</bitOffset>
  6680. <bitWidth>8</bitWidth>
  6681. <access>read-only</access>
  6682. </field>
  6683. <field>
  6684. <name>MSIRANGE</name>
  6685. <description>MSI clock ranges</description>
  6686. <bitOffset>13</bitOffset>
  6687. <bitWidth>3</bitWidth>
  6688. <access>read-write</access>
  6689. </field>
  6690. <field>
  6691. <name>HSI16TRIM</name>
  6692. <description>High speed internal clock trimming</description>
  6693. <bitOffset>8</bitOffset>
  6694. <bitWidth>5</bitWidth>
  6695. <access>read-write</access>
  6696. </field>
  6697. <field>
  6698. <name>HSI16CAL</name>
  6699. <description>nternal high speed clock calibration</description>
  6700. <bitOffset>0</bitOffset>
  6701. <bitWidth>8</bitWidth>
  6702. <access>read-only</access>
  6703. </field>
  6704. </fields>
  6705. </register>
  6706. <register>
  6707. <name>CFGR</name>
  6708. <displayName>CFGR</displayName>
  6709. <description>Clock configuration register</description>
  6710. <addressOffset>0xC</addressOffset>
  6711. <size>0x20</size>
  6712. <resetValue>0x00000000</resetValue>
  6713. <fields>
  6714. <field>
  6715. <name>MCOPRE</name>
  6716. <description>Microcontroller clock output prescaler</description>
  6717. <bitOffset>28</bitOffset>
  6718. <bitWidth>3</bitWidth>
  6719. <access>read-write</access>
  6720. </field>
  6721. <field>
  6722. <name>MCOSEL</name>
  6723. <description>Microcontroller clock output selection</description>
  6724. <bitOffset>24</bitOffset>
  6725. <bitWidth>3</bitWidth>
  6726. <access>read-write</access>
  6727. </field>
  6728. <field>
  6729. <name>PLLDIV</name>
  6730. <description>PLL output division</description>
  6731. <bitOffset>22</bitOffset>
  6732. <bitWidth>2</bitWidth>
  6733. <access>read-write</access>
  6734. </field>
  6735. <field>
  6736. <name>PLLMUL</name>
  6737. <description>PLL multiplication factor</description>
  6738. <bitOffset>18</bitOffset>
  6739. <bitWidth>4</bitWidth>
  6740. <access>read-write</access>
  6741. </field>
  6742. <field>
  6743. <name>PLLSRC</name>
  6744. <description>PLL entry clock source</description>
  6745. <bitOffset>16</bitOffset>
  6746. <bitWidth>1</bitWidth>
  6747. <access>read-write</access>
  6748. </field>
  6749. <field>
  6750. <name>STOPWUCK</name>
  6751. <description>Wake-up from stop clock selection</description>
  6752. <bitOffset>15</bitOffset>
  6753. <bitWidth>1</bitWidth>
  6754. <access>read-write</access>
  6755. </field>
  6756. <field>
  6757. <name>PPRE2</name>
  6758. <description>APB high-speed prescaler (APB2)</description>
  6759. <bitOffset>11</bitOffset>
  6760. <bitWidth>3</bitWidth>
  6761. <access>read-write</access>
  6762. </field>
  6763. <field>
  6764. <name>PPRE1</name>
  6765. <description>APB low-speed prescaler (APB1)</description>
  6766. <bitOffset>8</bitOffset>
  6767. <bitWidth>3</bitWidth>
  6768. <access>read-write</access>
  6769. </field>
  6770. <field>
  6771. <name>HPRE</name>
  6772. <description>AHB prescaler</description>
  6773. <bitOffset>4</bitOffset>
  6774. <bitWidth>4</bitWidth>
  6775. <access>read-write</access>
  6776. </field>
  6777. <field>
  6778. <name>SWS</name>
  6779. <description>System clock switch status</description>
  6780. <bitOffset>2</bitOffset>
  6781. <bitWidth>2</bitWidth>
  6782. <access>read-only</access>
  6783. </field>
  6784. <field>
  6785. <name>SW</name>
  6786. <description>System clock switch</description>
  6787. <bitOffset>0</bitOffset>
  6788. <bitWidth>2</bitWidth>
  6789. <access>read-write</access>
  6790. </field>
  6791. </fields>
  6792. </register>
  6793. <register>
  6794. <name>CIER</name>
  6795. <displayName>CIER</displayName>
  6796. <description>Clock interrupt enable register</description>
  6797. <addressOffset>0x10</addressOffset>
  6798. <size>0x20</size>
  6799. <access>read-only</access>
  6800. <resetValue>0x00000000</resetValue>
  6801. <fields>
  6802. <field>
  6803. <name>CSSLSE</name>
  6804. <description>LSE CSS interrupt flag</description>
  6805. <bitOffset>7</bitOffset>
  6806. <bitWidth>1</bitWidth>
  6807. </field>
  6808. <field>
  6809. <name>MSIRDYIE</name>
  6810. <description>MSI ready interrupt flag</description>
  6811. <bitOffset>5</bitOffset>
  6812. <bitWidth>1</bitWidth>
  6813. </field>
  6814. <field>
  6815. <name>PLLRDYIE</name>
  6816. <description>PLL ready interrupt flag</description>
  6817. <bitOffset>4</bitOffset>
  6818. <bitWidth>1</bitWidth>
  6819. </field>
  6820. <field>
  6821. <name>HSERDYIE</name>
  6822. <description>HSE ready interrupt flag</description>
  6823. <bitOffset>3</bitOffset>
  6824. <bitWidth>1</bitWidth>
  6825. </field>
  6826. <field>
  6827. <name>HSI16RDYIE</name>
  6828. <description>HSI16 ready interrupt flag</description>
  6829. <bitOffset>2</bitOffset>
  6830. <bitWidth>1</bitWidth>
  6831. </field>
  6832. <field>
  6833. <name>LSERDYIE</name>
  6834. <description>LSE ready interrupt flag</description>
  6835. <bitOffset>1</bitOffset>
  6836. <bitWidth>1</bitWidth>
  6837. </field>
  6838. <field>
  6839. <name>LSIRDYIE</name>
  6840. <description>LSI ready interrupt flag</description>
  6841. <bitOffset>0</bitOffset>
  6842. <bitWidth>1</bitWidth>
  6843. </field>
  6844. </fields>
  6845. </register>
  6846. <register>
  6847. <name>CIFR</name>
  6848. <displayName>CIFR</displayName>
  6849. <description>Clock interrupt flag register</description>
  6850. <addressOffset>0x14</addressOffset>
  6851. <size>0x20</size>
  6852. <access>read-only</access>
  6853. <resetValue>0x00000000</resetValue>
  6854. <fields>
  6855. <field>
  6856. <name>CSSHSEF</name>
  6857. <description>Clock Security System Interrupt flag</description>
  6858. <bitOffset>8</bitOffset>
  6859. <bitWidth>1</bitWidth>
  6860. </field>
  6861. <field>
  6862. <name>CSSLSEF</name>
  6863. <description>LSE Clock Security System Interrupt flag</description>
  6864. <bitOffset>7</bitOffset>
  6865. <bitWidth>1</bitWidth>
  6866. </field>
  6867. <field>
  6868. <name>MSIRDYF</name>
  6869. <description>MSI ready interrupt flag</description>
  6870. <bitOffset>5</bitOffset>
  6871. <bitWidth>1</bitWidth>
  6872. </field>
  6873. <field>
  6874. <name>PLLRDYF</name>
  6875. <description>PLL ready interrupt flag</description>
  6876. <bitOffset>4</bitOffset>
  6877. <bitWidth>1</bitWidth>
  6878. </field>
  6879. <field>
  6880. <name>HSERDYF</name>
  6881. <description>HSE ready interrupt flag</description>
  6882. <bitOffset>3</bitOffset>
  6883. <bitWidth>1</bitWidth>
  6884. </field>
  6885. <field>
  6886. <name>HSI16RDYF</name>
  6887. <description>HSI16 ready interrupt flag</description>
  6888. <bitOffset>2</bitOffset>
  6889. <bitWidth>1</bitWidth>
  6890. </field>
  6891. <field>
  6892. <name>LSERDYF</name>
  6893. <description>LSE ready interrupt flag</description>
  6894. <bitOffset>1</bitOffset>
  6895. <bitWidth>1</bitWidth>
  6896. </field>
  6897. <field>
  6898. <name>LSIRDYF</name>
  6899. <description>LSI ready interrupt flag</description>
  6900. <bitOffset>0</bitOffset>
  6901. <bitWidth>1</bitWidth>
  6902. </field>
  6903. </fields>
  6904. </register>
  6905. <register>
  6906. <name>CICR</name>
  6907. <displayName>CICR</displayName>
  6908. <description>Clock interrupt clear register</description>
  6909. <addressOffset>0x18</addressOffset>
  6910. <size>0x20</size>
  6911. <access>read-only</access>
  6912. <resetValue>0x00000000</resetValue>
  6913. <fields>
  6914. <field>
  6915. <name>CSSHSEC</name>
  6916. <description>Clock Security System Interrupt clear</description>
  6917. <bitOffset>8</bitOffset>
  6918. <bitWidth>1</bitWidth>
  6919. </field>
  6920. <field>
  6921. <name>CSSLSEC</name>
  6922. <description>LSE Clock Security System Interrupt clear</description>
  6923. <bitOffset>7</bitOffset>
  6924. <bitWidth>1</bitWidth>
  6925. </field>
  6926. <field>
  6927. <name>MSIRDYC</name>
  6928. <description>MSI ready Interrupt clear</description>
  6929. <bitOffset>5</bitOffset>
  6930. <bitWidth>1</bitWidth>
  6931. </field>
  6932. <field>
  6933. <name>PLLRDYC</name>
  6934. <description>PLL ready Interrupt clear</description>
  6935. <bitOffset>4</bitOffset>
  6936. <bitWidth>1</bitWidth>
  6937. </field>
  6938. <field>
  6939. <name>HSERDYC</name>
  6940. <description>HSE ready Interrupt clear</description>
  6941. <bitOffset>3</bitOffset>
  6942. <bitWidth>1</bitWidth>
  6943. </field>
  6944. <field>
  6945. <name>HSI16RDYC</name>
  6946. <description>HSI16 ready Interrupt clear</description>
  6947. <bitOffset>2</bitOffset>
  6948. <bitWidth>1</bitWidth>
  6949. </field>
  6950. <field>
  6951. <name>LSERDYC</name>
  6952. <description>LSE ready Interrupt clear</description>
  6953. <bitOffset>1</bitOffset>
  6954. <bitWidth>1</bitWidth>
  6955. </field>
  6956. <field>
  6957. <name>LSIRDYC</name>
  6958. <description>LSI ready Interrupt clear</description>
  6959. <bitOffset>0</bitOffset>
  6960. <bitWidth>1</bitWidth>
  6961. </field>
  6962. </fields>
  6963. </register>
  6964. <register>
  6965. <name>IOPRSTR</name>
  6966. <displayName>IOPRSTR</displayName>
  6967. <description>GPIO reset register</description>
  6968. <addressOffset>0x1C</addressOffset>
  6969. <size>0x20</size>
  6970. <access>read-write</access>
  6971. <resetValue>0x00000000</resetValue>
  6972. <fields>
  6973. <field>
  6974. <name>IOPHRST</name>
  6975. <description>I/O port H reset</description>
  6976. <bitOffset>7</bitOffset>
  6977. <bitWidth>1</bitWidth>
  6978. </field>
  6979. <field>
  6980. <name>IOPDRST</name>
  6981. <description>I/O port D reset</description>
  6982. <bitOffset>3</bitOffset>
  6983. <bitWidth>1</bitWidth>
  6984. </field>
  6985. <field>
  6986. <name>IOPCRST</name>
  6987. <description>I/O port A reset</description>
  6988. <bitOffset>2</bitOffset>
  6989. <bitWidth>1</bitWidth>
  6990. </field>
  6991. <field>
  6992. <name>IOPBRST</name>
  6993. <description>I/O port B reset</description>
  6994. <bitOffset>1</bitOffset>
  6995. <bitWidth>1</bitWidth>
  6996. </field>
  6997. <field>
  6998. <name>IOPARST</name>
  6999. <description>I/O port A reset</description>
  7000. <bitOffset>0</bitOffset>
  7001. <bitWidth>1</bitWidth>
  7002. </field>
  7003. <field>
  7004. <name>IOPERST</name>
  7005. <description>I/O port E reset</description>
  7006. <bitOffset>4</bitOffset>
  7007. <bitWidth>1</bitWidth>
  7008. </field>
  7009. </fields>
  7010. </register>
  7011. <register>
  7012. <name>AHBRSTR</name>
  7013. <displayName>AHBRSTR</displayName>
  7014. <description>AHB peripheral reset register</description>
  7015. <addressOffset>0x20</addressOffset>
  7016. <size>0x20</size>
  7017. <access>read-write</access>
  7018. <resetValue>0x00000000</resetValue>
  7019. <fields>
  7020. <field>
  7021. <name>CRYPRST</name>
  7022. <description>Crypto module reset</description>
  7023. <bitOffset>24</bitOffset>
  7024. <bitWidth>1</bitWidth>
  7025. </field>
  7026. <field>
  7027. <name>CRCRST</name>
  7028. <description>Test integration module reset</description>
  7029. <bitOffset>12</bitOffset>
  7030. <bitWidth>1</bitWidth>
  7031. </field>
  7032. <field>
  7033. <name>MIFRST</name>
  7034. <description>Memory interface reset</description>
  7035. <bitOffset>8</bitOffset>
  7036. <bitWidth>1</bitWidth>
  7037. </field>
  7038. <field>
  7039. <name>DMARST</name>
  7040. <description>DMA reset</description>
  7041. <bitOffset>0</bitOffset>
  7042. <bitWidth>1</bitWidth>
  7043. </field>
  7044. </fields>
  7045. </register>
  7046. <register>
  7047. <name>APB2RSTR</name>
  7048. <displayName>APB2RSTR</displayName>
  7049. <description>APB2 peripheral reset register</description>
  7050. <addressOffset>0x24</addressOffset>
  7051. <size>0x20</size>
  7052. <access>read-write</access>
  7053. <resetValue>0x000000000</resetValue>
  7054. <fields>
  7055. <field>
  7056. <name>DBGRST</name>
  7057. <description>DBG reset</description>
  7058. <bitOffset>22</bitOffset>
  7059. <bitWidth>1</bitWidth>
  7060. </field>
  7061. <field>
  7062. <name>USART1RST</name>
  7063. <description>USART1 reset</description>
  7064. <bitOffset>14</bitOffset>
  7065. <bitWidth>1</bitWidth>
  7066. </field>
  7067. <field>
  7068. <name>SPI1RST</name>
  7069. <description>SPI 1 reset</description>
  7070. <bitOffset>12</bitOffset>
  7071. <bitWidth>1</bitWidth>
  7072. </field>
  7073. <field>
  7074. <name>ADCRST</name>
  7075. <description>ADC interface reset</description>
  7076. <bitOffset>9</bitOffset>
  7077. <bitWidth>1</bitWidth>
  7078. </field>
  7079. <field>
  7080. <name>TIM22RST</name>
  7081. <description>TIM22 timer reset</description>
  7082. <bitOffset>5</bitOffset>
  7083. <bitWidth>1</bitWidth>
  7084. </field>
  7085. <field>
  7086. <name>TIM21RST</name>
  7087. <description>TIM21 timer reset</description>
  7088. <bitOffset>2</bitOffset>
  7089. <bitWidth>1</bitWidth>
  7090. </field>
  7091. <field>
  7092. <name>SYSCFGRST</name>
  7093. <description>System configuration controller reset</description>
  7094. <bitOffset>0</bitOffset>
  7095. <bitWidth>1</bitWidth>
  7096. </field>
  7097. </fields>
  7098. </register>
  7099. <register>
  7100. <name>APB1RSTR</name>
  7101. <displayName>APB1RSTR</displayName>
  7102. <description>APB1 peripheral reset register</description>
  7103. <addressOffset>0x28</addressOffset>
  7104. <size>0x20</size>
  7105. <access>read-write</access>
  7106. <resetValue>0x00000000</resetValue>
  7107. <fields>
  7108. <field>
  7109. <name>LPTIM1RST</name>
  7110. <description>Low power timer reset</description>
  7111. <bitOffset>31</bitOffset>
  7112. <bitWidth>1</bitWidth>
  7113. </field>
  7114. <field>
  7115. <name>PWRRST</name>
  7116. <description>Power interface reset</description>
  7117. <bitOffset>28</bitOffset>
  7118. <bitWidth>1</bitWidth>
  7119. </field>
  7120. <field>
  7121. <name>I2C2RST</name>
  7122. <description>I2C2 reset</description>
  7123. <bitOffset>22</bitOffset>
  7124. <bitWidth>1</bitWidth>
  7125. </field>
  7126. <field>
  7127. <name>I2C1RST</name>
  7128. <description>I2C1 reset</description>
  7129. <bitOffset>21</bitOffset>
  7130. <bitWidth>1</bitWidth>
  7131. </field>
  7132. <field>
  7133. <name>LPUART1RST</name>
  7134. <description>LPUART1 reset</description>
  7135. <bitOffset>18</bitOffset>
  7136. <bitWidth>1</bitWidth>
  7137. </field>
  7138. <field>
  7139. <name>USART2RST</name>
  7140. <description>USART2 reset</description>
  7141. <bitOffset>17</bitOffset>
  7142. <bitWidth>1</bitWidth>
  7143. </field>
  7144. <field>
  7145. <name>SPI2RST</name>
  7146. <description>SPI2 reset</description>
  7147. <bitOffset>14</bitOffset>
  7148. <bitWidth>1</bitWidth>
  7149. </field>
  7150. <field>
  7151. <name>WWDGRST</name>
  7152. <description>Window watchdog reset</description>
  7153. <bitOffset>11</bitOffset>
  7154. <bitWidth>1</bitWidth>
  7155. </field>
  7156. <field>
  7157. <name>TIM6RST</name>
  7158. <description>Timer 6 reset</description>
  7159. <bitOffset>4</bitOffset>
  7160. <bitWidth>1</bitWidth>
  7161. </field>
  7162. <field>
  7163. <name>TIM2RST</name>
  7164. <description>Timer 2 reset</description>
  7165. <bitOffset>0</bitOffset>
  7166. <bitWidth>1</bitWidth>
  7167. </field>
  7168. <field>
  7169. <name>TIM3RST</name>
  7170. <description>Timer 3 reset</description>
  7171. <bitOffset>1</bitOffset>
  7172. <bitWidth>1</bitWidth>
  7173. </field>
  7174. <field>
  7175. <name>TIM7RST</name>
  7176. <description>Timer 7 reset</description>
  7177. <bitOffset>5</bitOffset>
  7178. <bitWidth>1</bitWidth>
  7179. </field>
  7180. <field>
  7181. <name>USART4RST</name>
  7182. <description>USART4 reset</description>
  7183. <bitOffset>19</bitOffset>
  7184. <bitWidth>1</bitWidth>
  7185. </field>
  7186. <field>
  7187. <name>USART5RST</name>
  7188. <description>USART5 reset</description>
  7189. <bitOffset>20</bitOffset>
  7190. <bitWidth>1</bitWidth>
  7191. </field>
  7192. <field>
  7193. <name>CRCRST</name>
  7194. <description>CRC reset</description>
  7195. <bitOffset>27</bitOffset>
  7196. <bitWidth>1</bitWidth>
  7197. </field>
  7198. <field>
  7199. <name>I2C3</name>
  7200. <description>I2C3 reset</description>
  7201. <bitOffset>30</bitOffset>
  7202. <bitWidth>1</bitWidth>
  7203. </field>
  7204. </fields>
  7205. </register>
  7206. <register>
  7207. <name>IOPENR</name>
  7208. <displayName>IOPENR</displayName>
  7209. <description>GPIO clock enable register</description>
  7210. <addressOffset>0x2C</addressOffset>
  7211. <size>0x20</size>
  7212. <access>read-write</access>
  7213. <resetValue>0x00000000</resetValue>
  7214. <fields>
  7215. <field>
  7216. <name>IOPHEN</name>
  7217. <description>I/O port H clock enable bit</description>
  7218. <bitOffset>7</bitOffset>
  7219. <bitWidth>1</bitWidth>
  7220. </field>
  7221. <field>
  7222. <name>IOPDEN</name>
  7223. <description>I/O port D clock enable bit</description>
  7224. <bitOffset>3</bitOffset>
  7225. <bitWidth>1</bitWidth>
  7226. </field>
  7227. <field>
  7228. <name>IOPCEN</name>
  7229. <description>IO port A clock enable bit</description>
  7230. <bitOffset>2</bitOffset>
  7231. <bitWidth>1</bitWidth>
  7232. </field>
  7233. <field>
  7234. <name>IOPBEN</name>
  7235. <description>IO port B clock enable bit</description>
  7236. <bitOffset>1</bitOffset>
  7237. <bitWidth>1</bitWidth>
  7238. </field>
  7239. <field>
  7240. <name>IOPAEN</name>
  7241. <description>IO port A clock enable bit</description>
  7242. <bitOffset>0</bitOffset>
  7243. <bitWidth>1</bitWidth>
  7244. </field>
  7245. <field>
  7246. <name>IOPEEN</name>
  7247. <description>IO port E clock enable bit</description>
  7248. <bitOffset>4</bitOffset>
  7249. <bitWidth>1</bitWidth>
  7250. </field>
  7251. </fields>
  7252. </register>
  7253. <register>
  7254. <name>AHBENR</name>
  7255. <displayName>AHBENR</displayName>
  7256. <description>AHB peripheral clock enable register</description>
  7257. <addressOffset>0x30</addressOffset>
  7258. <size>0x20</size>
  7259. <access>read-write</access>
  7260. <resetValue>0x00000100</resetValue>
  7261. <fields>
  7262. <field>
  7263. <name>CRYPEN</name>
  7264. <description>Crypto clock enable bit</description>
  7265. <bitOffset>24</bitOffset>
  7266. <bitWidth>1</bitWidth>
  7267. </field>
  7268. <field>
  7269. <name>CRCEN</name>
  7270. <description>CRC clock enable bit</description>
  7271. <bitOffset>12</bitOffset>
  7272. <bitWidth>1</bitWidth>
  7273. </field>
  7274. <field>
  7275. <name>MIFEN</name>
  7276. <description>NVM interface clock enable bit</description>
  7277. <bitOffset>8</bitOffset>
  7278. <bitWidth>1</bitWidth>
  7279. </field>
  7280. <field>
  7281. <name>DMAEN</name>
  7282. <description>DMA clock enable bit</description>
  7283. <bitOffset>0</bitOffset>
  7284. <bitWidth>1</bitWidth>
  7285. </field>
  7286. </fields>
  7287. </register>
  7288. <register>
  7289. <name>APB2ENR</name>
  7290. <displayName>APB2ENR</displayName>
  7291. <description>APB2 peripheral clock enable register</description>
  7292. <addressOffset>0x34</addressOffset>
  7293. <size>0x20</size>
  7294. <access>read-write</access>
  7295. <resetValue>0x00000000</resetValue>
  7296. <fields>
  7297. <field>
  7298. <name>DBGEN</name>
  7299. <description>DBG clock enable bit</description>
  7300. <bitOffset>22</bitOffset>
  7301. <bitWidth>1</bitWidth>
  7302. </field>
  7303. <field>
  7304. <name>USART1EN</name>
  7305. <description>USART1 clock enable bit</description>
  7306. <bitOffset>14</bitOffset>
  7307. <bitWidth>1</bitWidth>
  7308. </field>
  7309. <field>
  7310. <name>SPI1EN</name>
  7311. <description>SPI1 clock enable bit</description>
  7312. <bitOffset>12</bitOffset>
  7313. <bitWidth>1</bitWidth>
  7314. </field>
  7315. <field>
  7316. <name>ADCEN</name>
  7317. <description>ADC clock enable bit</description>
  7318. <bitOffset>9</bitOffset>
  7319. <bitWidth>1</bitWidth>
  7320. </field>
  7321. <field>
  7322. <name>FWEN</name>
  7323. <description>Firewall clock enable bit</description>
  7324. <bitOffset>7</bitOffset>
  7325. <bitWidth>1</bitWidth>
  7326. </field>
  7327. <field>
  7328. <name>TIM22EN</name>
  7329. <description>TIM22 timer clock enable bit</description>
  7330. <bitOffset>5</bitOffset>
  7331. <bitWidth>1</bitWidth>
  7332. </field>
  7333. <field>
  7334. <name>TIM21EN</name>
  7335. <description>TIM21 timer clock enable bit</description>
  7336. <bitOffset>2</bitOffset>
  7337. <bitWidth>1</bitWidth>
  7338. </field>
  7339. <field>
  7340. <name>SYSCFGEN</name>
  7341. <description>System configuration controller clock enable bit</description>
  7342. <bitOffset>0</bitOffset>
  7343. <bitWidth>1</bitWidth>
  7344. </field>
  7345. </fields>
  7346. </register>
  7347. <register>
  7348. <name>APB1ENR</name>
  7349. <displayName>APB1ENR</displayName>
  7350. <description>APB1 peripheral clock enable register</description>
  7351. <addressOffset>0x38</addressOffset>
  7352. <size>0x20</size>
  7353. <access>read-write</access>
  7354. <resetValue>0x00000000</resetValue>
  7355. <fields>
  7356. <field>
  7357. <name>LPTIM1EN</name>
  7358. <description>Low power timer clock enable bit</description>
  7359. <bitOffset>31</bitOffset>
  7360. <bitWidth>1</bitWidth>
  7361. </field>
  7362. <field>
  7363. <name>PWREN</name>
  7364. <description>Power interface clock enable bit</description>
  7365. <bitOffset>28</bitOffset>
  7366. <bitWidth>1</bitWidth>
  7367. </field>
  7368. <field>
  7369. <name>I2C2EN</name>
  7370. <description>I2C2 clock enable bit</description>
  7371. <bitOffset>22</bitOffset>
  7372. <bitWidth>1</bitWidth>
  7373. </field>
  7374. <field>
  7375. <name>I2C1EN</name>
  7376. <description>I2C1 clock enable bit</description>
  7377. <bitOffset>21</bitOffset>
  7378. <bitWidth>1</bitWidth>
  7379. </field>
  7380. <field>
  7381. <name>LPUART1EN</name>
  7382. <description>LPUART1 clock enable bit</description>
  7383. <bitOffset>18</bitOffset>
  7384. <bitWidth>1</bitWidth>
  7385. </field>
  7386. <field>
  7387. <name>USART2EN</name>
  7388. <description>UART2 clock enable bit</description>
  7389. <bitOffset>17</bitOffset>
  7390. <bitWidth>1</bitWidth>
  7391. </field>
  7392. <field>
  7393. <name>SPI2EN</name>
  7394. <description>SPI2 clock enable bit</description>
  7395. <bitOffset>14</bitOffset>
  7396. <bitWidth>1</bitWidth>
  7397. </field>
  7398. <field>
  7399. <name>WWDGEN</name>
  7400. <description>Window watchdog clock enable bit</description>
  7401. <bitOffset>11</bitOffset>
  7402. <bitWidth>1</bitWidth>
  7403. </field>
  7404. <field>
  7405. <name>TIM6EN</name>
  7406. <description>Timer 6 clock enable bit</description>
  7407. <bitOffset>4</bitOffset>
  7408. <bitWidth>1</bitWidth>
  7409. </field>
  7410. <field>
  7411. <name>TIM2EN</name>
  7412. <description>Timer2 clock enable bit</description>
  7413. <bitOffset>0</bitOffset>
  7414. <bitWidth>1</bitWidth>
  7415. </field>
  7416. <field>
  7417. <name>TIM3EN</name>
  7418. <description>Timer 3 clock enbale bit</description>
  7419. <bitOffset>2</bitOffset>
  7420. <bitWidth>1</bitWidth>
  7421. </field>
  7422. <field>
  7423. <name>TIM7EN</name>
  7424. <description>Timer 7 clock enable bit</description>
  7425. <bitOffset>5</bitOffset>
  7426. <bitWidth>1</bitWidth>
  7427. </field>
  7428. <field>
  7429. <name>USART4EN</name>
  7430. <description>USART4 clock enable bit</description>
  7431. <bitOffset>19</bitOffset>
  7432. <bitWidth>1</bitWidth>
  7433. </field>
  7434. <field>
  7435. <name>USART5EN</name>
  7436. <description>USART5 clock enable bit</description>
  7437. <bitOffset>20</bitOffset>
  7438. <bitWidth>1</bitWidth>
  7439. </field>
  7440. <field>
  7441. <name>I2C3EN</name>
  7442. <description>I2C3 clock enable bit</description>
  7443. <bitOffset>30</bitOffset>
  7444. <bitWidth>1</bitWidth>
  7445. </field>
  7446. </fields>
  7447. </register>
  7448. <register>
  7449. <name>IOPSMEN</name>
  7450. <displayName>IOPSMEN</displayName>
  7451. <description>GPIO clock enable in sleep mode register</description>
  7452. <addressOffset>0x3C</addressOffset>
  7453. <size>0x20</size>
  7454. <access>read-write</access>
  7455. <resetValue>0x0000008F</resetValue>
  7456. <fields>
  7457. <field>
  7458. <name>IOPHSMEN</name>
  7459. <description>Port H clock enable during Sleep mode bit</description>
  7460. <bitOffset>7</bitOffset>
  7461. <bitWidth>1</bitWidth>
  7462. </field>
  7463. <field>
  7464. <name>IOPDSMEN</name>
  7465. <description>Port D clock enable during Sleep mode bit</description>
  7466. <bitOffset>3</bitOffset>
  7467. <bitWidth>1</bitWidth>
  7468. </field>
  7469. <field>
  7470. <name>IOPCSMEN</name>
  7471. <description>Port C clock enable during Sleep mode bit</description>
  7472. <bitOffset>2</bitOffset>
  7473. <bitWidth>1</bitWidth>
  7474. </field>
  7475. <field>
  7476. <name>IOPBSMEN</name>
  7477. <description>Port B clock enable during Sleep mode bit</description>
  7478. <bitOffset>1</bitOffset>
  7479. <bitWidth>1</bitWidth>
  7480. </field>
  7481. <field>
  7482. <name>IOPASMEN</name>
  7483. <description>Port A clock enable during Sleep mode bit</description>
  7484. <bitOffset>0</bitOffset>
  7485. <bitWidth>1</bitWidth>
  7486. </field>
  7487. <field>
  7488. <name>IOPESMEN</name>
  7489. <description>Port E clock enable during Sleep mode bit</description>
  7490. <bitOffset>4</bitOffset>
  7491. <bitWidth>1</bitWidth>
  7492. </field>
  7493. </fields>
  7494. </register>
  7495. <register>
  7496. <name>AHBSMENR</name>
  7497. <displayName>AHBSMENR</displayName>
  7498. <description>AHB peripheral clock enable in sleep mode register</description>
  7499. <addressOffset>0x40</addressOffset>
  7500. <size>0x20</size>
  7501. <access>read-write</access>
  7502. <resetValue>0x01111301</resetValue>
  7503. <fields>
  7504. <field>
  7505. <name>CRYPTSMEN</name>
  7506. <description>Crypto clock enable during sleep mode bit</description>
  7507. <bitOffset>24</bitOffset>
  7508. <bitWidth>1</bitWidth>
  7509. </field>
  7510. <field>
  7511. <name>CRCSMEN</name>
  7512. <description>CRC clock enable during sleep mode bit</description>
  7513. <bitOffset>12</bitOffset>
  7514. <bitWidth>1</bitWidth>
  7515. </field>
  7516. <field>
  7517. <name>SRAMSMEN</name>
  7518. <description>SRAM interface clock enable during sleep mode bit</description>
  7519. <bitOffset>9</bitOffset>
  7520. <bitWidth>1</bitWidth>
  7521. </field>
  7522. <field>
  7523. <name>MIFSMEN</name>
  7524. <description>NVM interface clock enable during sleep mode bit</description>
  7525. <bitOffset>8</bitOffset>
  7526. <bitWidth>1</bitWidth>
  7527. </field>
  7528. <field>
  7529. <name>DMASMEN</name>
  7530. <description>DMA clock enable during sleep mode bit</description>
  7531. <bitOffset>0</bitOffset>
  7532. <bitWidth>1</bitWidth>
  7533. </field>
  7534. </fields>
  7535. </register>
  7536. <register>
  7537. <name>APB2SMENR</name>
  7538. <displayName>APB2SMENR</displayName>
  7539. <description>APB2 peripheral clock enable in sleep mode register</description>
  7540. <addressOffset>0x44</addressOffset>
  7541. <size>0x20</size>
  7542. <access>read-write</access>
  7543. <resetValue>0x00405225</resetValue>
  7544. <fields>
  7545. <field>
  7546. <name>DBGSMEN</name>
  7547. <description>DBG clock enable during sleep mode bit</description>
  7548. <bitOffset>22</bitOffset>
  7549. <bitWidth>1</bitWidth>
  7550. </field>
  7551. <field>
  7552. <name>USART1SMEN</name>
  7553. <description>USART1 clock enable during sleep mode bit</description>
  7554. <bitOffset>14</bitOffset>
  7555. <bitWidth>1</bitWidth>
  7556. </field>
  7557. <field>
  7558. <name>SPI1SMEN</name>
  7559. <description>SPI1 clock enable during sleep mode bit</description>
  7560. <bitOffset>12</bitOffset>
  7561. <bitWidth>1</bitWidth>
  7562. </field>
  7563. <field>
  7564. <name>ADCSMEN</name>
  7565. <description>ADC clock enable during sleep mode bit</description>
  7566. <bitOffset>9</bitOffset>
  7567. <bitWidth>1</bitWidth>
  7568. </field>
  7569. <field>
  7570. <name>TIM22SMEN</name>
  7571. <description>TIM22 timer clock enable during sleep mode bit</description>
  7572. <bitOffset>5</bitOffset>
  7573. <bitWidth>1</bitWidth>
  7574. </field>
  7575. <field>
  7576. <name>TIM21SMEN</name>
  7577. <description>TIM21 timer clock enable during sleep mode bit</description>
  7578. <bitOffset>2</bitOffset>
  7579. <bitWidth>1</bitWidth>
  7580. </field>
  7581. <field>
  7582. <name>SYSCFGSMEN</name>
  7583. <description>System configuration controller clock enable during sleep mode bit</description>
  7584. <bitOffset>0</bitOffset>
  7585. <bitWidth>1</bitWidth>
  7586. </field>
  7587. </fields>
  7588. </register>
  7589. <register>
  7590. <name>APB1SMENR</name>
  7591. <displayName>APB1SMENR</displayName>
  7592. <description>APB1 peripheral clock enable in sleep mode register</description>
  7593. <addressOffset>0x48</addressOffset>
  7594. <size>0x20</size>
  7595. <access>read-write</access>
  7596. <resetValue>0xB8E64A11</resetValue>
  7597. <fields>
  7598. <field>
  7599. <name>LPTIM1SMEN</name>
  7600. <description>Low power timer clock enable during sleep mode bit</description>
  7601. <bitOffset>31</bitOffset>
  7602. <bitWidth>1</bitWidth>
  7603. </field>
  7604. <field>
  7605. <name>PWRSMEN</name>
  7606. <description>Power interface clock enable during sleep mode bit</description>
  7607. <bitOffset>28</bitOffset>
  7608. <bitWidth>1</bitWidth>
  7609. </field>
  7610. <field>
  7611. <name>CRSSMEN</name>
  7612. <description>Clock recovery system clock enable during sleep mode bit</description>
  7613. <bitOffset>27</bitOffset>
  7614. <bitWidth>1</bitWidth>
  7615. </field>
  7616. <field>
  7617. <name>I2C2SMEN</name>
  7618. <description>I2C2 clock enable during sleep mode bit</description>
  7619. <bitOffset>22</bitOffset>
  7620. <bitWidth>1</bitWidth>
  7621. </field>
  7622. <field>
  7623. <name>I2C1SMEN</name>
  7624. <description>I2C1 clock enable during sleep mode bit</description>
  7625. <bitOffset>21</bitOffset>
  7626. <bitWidth>1</bitWidth>
  7627. </field>
  7628. <field>
  7629. <name>LPUART1SMEN</name>
  7630. <description>LPUART1 clock enable during sleep mode bit</description>
  7631. <bitOffset>18</bitOffset>
  7632. <bitWidth>1</bitWidth>
  7633. </field>
  7634. <field>
  7635. <name>USART2SMEN</name>
  7636. <description>UART2 clock enable during sleep mode bit</description>
  7637. <bitOffset>17</bitOffset>
  7638. <bitWidth>1</bitWidth>
  7639. </field>
  7640. <field>
  7641. <name>SPI2SMEN</name>
  7642. <description>SPI2 clock enable during sleep mode bit</description>
  7643. <bitOffset>14</bitOffset>
  7644. <bitWidth>1</bitWidth>
  7645. </field>
  7646. <field>
  7647. <name>WWDGSMEN</name>
  7648. <description>Window watchdog clock enable during sleep mode bit</description>
  7649. <bitOffset>11</bitOffset>
  7650. <bitWidth>1</bitWidth>
  7651. </field>
  7652. <field>
  7653. <name>TIM6SMEN</name>
  7654. <description>Timer 6 clock enable during sleep mode bit</description>
  7655. <bitOffset>4</bitOffset>
  7656. <bitWidth>1</bitWidth>
  7657. </field>
  7658. <field>
  7659. <name>TIM2SMEN</name>
  7660. <description>Timer2 clock enable during sleep mode bit</description>
  7661. <bitOffset>0</bitOffset>
  7662. <bitWidth>1</bitWidth>
  7663. </field>
  7664. <field>
  7665. <name>TIM3SMEN</name>
  7666. <description>Timer 3 clock enable during sleep mode bit</description>
  7667. <bitOffset>1</bitOffset>
  7668. <bitWidth>1</bitWidth>
  7669. </field>
  7670. <field>
  7671. <name>TIM7SMEN</name>
  7672. <description>Timer 7 clock enable during sleep mode bit</description>
  7673. <bitOffset>5</bitOffset>
  7674. <bitWidth>1</bitWidth>
  7675. </field>
  7676. <field>
  7677. <name>USART4SMEN</name>
  7678. <description>USART4 clock enabe during sleep mode bit</description>
  7679. <bitOffset>19</bitOffset>
  7680. <bitWidth>1</bitWidth>
  7681. </field>
  7682. <field>
  7683. <name>USART5SMEN</name>
  7684. <description>USART5 clock enable during sleep mode bit</description>
  7685. <bitOffset>20</bitOffset>
  7686. <bitWidth>1</bitWidth>
  7687. </field>
  7688. <field>
  7689. <name>I2C3SMEN</name>
  7690. <description>I2C3 clock enable during sleep mode bit</description>
  7691. <bitOffset>30</bitOffset>
  7692. <bitWidth>1</bitWidth>
  7693. </field>
  7694. </fields>
  7695. </register>
  7696. <register>
  7697. <name>CCIPR</name>
  7698. <displayName>CCIPR</displayName>
  7699. <description>Clock configuration register</description>
  7700. <addressOffset>0x4C</addressOffset>
  7701. <size>0x20</size>
  7702. <access>read-write</access>
  7703. <resetValue>0x00000000</resetValue>
  7704. <fields>
  7705. <field>
  7706. <name>LPTIM1SEL1</name>
  7707. <description>Low Power Timer clock source selection bits</description>
  7708. <bitOffset>19</bitOffset>
  7709. <bitWidth>1</bitWidth>
  7710. </field>
  7711. <field>
  7712. <name>LPTIM1SEL0</name>
  7713. <description>LPTIM1SEL0</description>
  7714. <bitOffset>18</bitOffset>
  7715. <bitWidth>1</bitWidth>
  7716. </field>
  7717. <field>
  7718. <name>I2C1SEL1</name>
  7719. <description>I2C1 clock source selection bits</description>
  7720. <bitOffset>13</bitOffset>
  7721. <bitWidth>1</bitWidth>
  7722. </field>
  7723. <field>
  7724. <name>I2C1SEL0</name>
  7725. <description>I2C1SEL0</description>
  7726. <bitOffset>12</bitOffset>
  7727. <bitWidth>1</bitWidth>
  7728. </field>
  7729. <field>
  7730. <name>LPUART1SEL1</name>
  7731. <description>LPUART1 clock source selection bits</description>
  7732. <bitOffset>11</bitOffset>
  7733. <bitWidth>1</bitWidth>
  7734. </field>
  7735. <field>
  7736. <name>LPUART1SEL0</name>
  7737. <description>LPUART1SEL0</description>
  7738. <bitOffset>10</bitOffset>
  7739. <bitWidth>1</bitWidth>
  7740. </field>
  7741. <field>
  7742. <name>USART2SEL1</name>
  7743. <description>USART2 clock source selection bits</description>
  7744. <bitOffset>3</bitOffset>
  7745. <bitWidth>1</bitWidth>
  7746. </field>
  7747. <field>
  7748. <name>USART2SEL0</name>
  7749. <description>USART2SEL0</description>
  7750. <bitOffset>2</bitOffset>
  7751. <bitWidth>1</bitWidth>
  7752. </field>
  7753. <field>
  7754. <name>USART1SEL1</name>
  7755. <description>USART1 clock source selection bits</description>
  7756. <bitOffset>1</bitOffset>
  7757. <bitWidth>1</bitWidth>
  7758. </field>
  7759. <field>
  7760. <name>USART1SEL0</name>
  7761. <description>USART1SEL0</description>
  7762. <bitOffset>0</bitOffset>
  7763. <bitWidth>1</bitWidth>
  7764. </field>
  7765. <field>
  7766. <name>I2C3SEL0</name>
  7767. <description>I2C3 clock source selection bits</description>
  7768. <bitOffset>16</bitOffset>
  7769. <bitWidth>1</bitWidth>
  7770. </field>
  7771. <field>
  7772. <name>I2C3SEL1</name>
  7773. <description>I2C3 clock source selection bits</description>
  7774. <bitOffset>17</bitOffset>
  7775. <bitWidth>1</bitWidth>
  7776. </field>
  7777. </fields>
  7778. </register>
  7779. <register>
  7780. <name>CSR</name>
  7781. <displayName>CSR</displayName>
  7782. <description>Control and status register</description>
  7783. <addressOffset>0x50</addressOffset>
  7784. <size>0x20</size>
  7785. <resetValue>0x0C000000</resetValue>
  7786. <fields>
  7787. <field>
  7788. <name>LPWRSTF</name>
  7789. <description>Low-power reset flag</description>
  7790. <bitOffset>31</bitOffset>
  7791. <bitWidth>1</bitWidth>
  7792. <access>read-write</access>
  7793. </field>
  7794. <field>
  7795. <name>WWDGRSTF</name>
  7796. <description>Window watchdog reset flag</description>
  7797. <bitOffset>30</bitOffset>
  7798. <bitWidth>1</bitWidth>
  7799. <access>read-write</access>
  7800. </field>
  7801. <field>
  7802. <name>IWDGRSTF</name>
  7803. <description>Independent watchdog reset flag</description>
  7804. <bitOffset>29</bitOffset>
  7805. <bitWidth>1</bitWidth>
  7806. <access>read-write</access>
  7807. </field>
  7808. <field>
  7809. <name>SFTRSTF</name>
  7810. <description>Software reset flag</description>
  7811. <bitOffset>28</bitOffset>
  7812. <bitWidth>1</bitWidth>
  7813. <access>read-write</access>
  7814. </field>
  7815. <field>
  7816. <name>PORRSTF</name>
  7817. <description>POR/PDR reset flag</description>
  7818. <bitOffset>27</bitOffset>
  7819. <bitWidth>1</bitWidth>
  7820. <access>read-write</access>
  7821. </field>
  7822. <field>
  7823. <name>PINRSTF</name>
  7824. <description>PIN reset flag</description>
  7825. <bitOffset>26</bitOffset>
  7826. <bitWidth>1</bitWidth>
  7827. <access>read-write</access>
  7828. </field>
  7829. <field>
  7830. <name>OBLRSTF</name>
  7831. <description>OBLRSTF</description>
  7832. <bitOffset>25</bitOffset>
  7833. <bitWidth>1</bitWidth>
  7834. <access>read-write</access>
  7835. </field>
  7836. <field>
  7837. <name>FWRSTF</name>
  7838. <description>Firewall reset flag</description>
  7839. <bitOffset>24</bitOffset>
  7840. <bitWidth>1</bitWidth>
  7841. <access>read-write</access>
  7842. </field>
  7843. <field>
  7844. <name>RTCRST</name>
  7845. <description>RTC software reset bit</description>
  7846. <bitOffset>19</bitOffset>
  7847. <bitWidth>1</bitWidth>
  7848. <access>read-write</access>
  7849. </field>
  7850. <field>
  7851. <name>RTCEN</name>
  7852. <description>RTC clock enable bit</description>
  7853. <bitOffset>18</bitOffset>
  7854. <bitWidth>1</bitWidth>
  7855. <access>read-write</access>
  7856. </field>
  7857. <field>
  7858. <name>RTCSEL</name>
  7859. <description>RTC and LCD clock source selection bits</description>
  7860. <bitOffset>16</bitOffset>
  7861. <bitWidth>2</bitWidth>
  7862. <access>read-write</access>
  7863. </field>
  7864. <field>
  7865. <name>CSSLSED</name>
  7866. <description>CSS on LSE failure detection flag</description>
  7867. <bitOffset>14</bitOffset>
  7868. <bitWidth>1</bitWidth>
  7869. <access>read-write</access>
  7870. </field>
  7871. <field>
  7872. <name>CSSLSEON</name>
  7873. <description>CSSLSEON</description>
  7874. <bitOffset>13</bitOffset>
  7875. <bitWidth>1</bitWidth>
  7876. <access>read-write</access>
  7877. </field>
  7878. <field>
  7879. <name>LSEDRV</name>
  7880. <description>LSEDRV</description>
  7881. <bitOffset>11</bitOffset>
  7882. <bitWidth>2</bitWidth>
  7883. <access>read-write</access>
  7884. </field>
  7885. <field>
  7886. <name>LSEBYP</name>
  7887. <description>External low-speed oscillator bypass bit</description>
  7888. <bitOffset>10</bitOffset>
  7889. <bitWidth>1</bitWidth>
  7890. <access>read-write</access>
  7891. </field>
  7892. <field>
  7893. <name>LSERDY</name>
  7894. <description>External low-speed oscillator ready bit</description>
  7895. <bitOffset>9</bitOffset>
  7896. <bitWidth>1</bitWidth>
  7897. <access>read-only</access>
  7898. </field>
  7899. <field>
  7900. <name>LSEON</name>
  7901. <description>External low-speed oscillator enable bit</description>
  7902. <bitOffset>8</bitOffset>
  7903. <bitWidth>1</bitWidth>
  7904. <access>read-write</access>
  7905. </field>
  7906. <field>
  7907. <name>LSIRDY</name>
  7908. <description>Internal low-speed oscillator ready bit</description>
  7909. <bitOffset>1</bitOffset>
  7910. <bitWidth>1</bitWidth>
  7911. <access>read-only</access>
  7912. </field>
  7913. <field>
  7914. <name>LSION</name>
  7915. <description>Internal low-speed oscillator enable</description>
  7916. <bitOffset>0</bitOffset>
  7917. <bitWidth>1</bitWidth>
  7918. <access>read-write</access>
  7919. </field>
  7920. <field>
  7921. <name>LSIIWDGLP</name>
  7922. <description>LSI clock input to IWDG in Ultra-low-power mode (Stop and Standby) enable bit</description>
  7923. <bitOffset>2</bitOffset>
  7924. <bitWidth>1</bitWidth>
  7925. <access>read-write</access>
  7926. </field>
  7927. <field>
  7928. <name>RMVF</name>
  7929. <description>Remove reset flag</description>
  7930. <bitOffset>23</bitOffset>
  7931. <bitWidth>1</bitWidth>
  7932. <access>read-write</access>
  7933. </field>
  7934. </fields>
  7935. </register>
  7936. </registers>
  7937. </peripheral>
  7938. <peripheral>
  7939. <name>SYSCFG</name>
  7940. <description>System configuration controller register</description>
  7941. <groupName>SYSCFG</groupName>
  7942. <baseAddress>0x40010000</baseAddress>
  7943. <addressBlock>
  7944. <offset>0x0</offset>
  7945. <size>0x400</size>
  7946. <usage>registers</usage>
  7947. </addressBlock>
  7948. <interrupt>
  7949. <name>RCC</name>
  7950. <description>RCC global interrupt</description>
  7951. <value>4</value>
  7952. </interrupt>
  7953. <registers>
  7954. <register>
  7955. <name>CFGR1</name>
  7956. <displayName>CFGR1</displayName>
  7957. <description>SYSCFG configuration register 1</description>
  7958. <addressOffset>0x0</addressOffset>
  7959. <size>0x20</size>
  7960. <resetValue>0x00000000</resetValue>
  7961. <fields>
  7962. <field>
  7963. <name>BOOT_MODE</name>
  7964. <description>Boot mode selected by the boot pins status bits</description>
  7965. <bitOffset>8</bitOffset>
  7966. <bitWidth>2</bitWidth>
  7967. <access>read-only</access>
  7968. </field>
  7969. <field>
  7970. <name>MEM_MODE</name>
  7971. <description>Memory mapping selection bits</description>
  7972. <bitOffset>0</bitOffset>
  7973. <bitWidth>2</bitWidth>
  7974. <access>read-write</access>
  7975. </field>
  7976. </fields>
  7977. </register>
  7978. <register>
  7979. <name>CFGR2</name>
  7980. <displayName>CFGR2</displayName>
  7981. <description>SYSCFG configuration register 2</description>
  7982. <addressOffset>0x4</addressOffset>
  7983. <size>0x20</size>
  7984. <access>read-write</access>
  7985. <resetValue>0x00000000</resetValue>
  7986. <fields>
  7987. <field>
  7988. <name>I2C2_FMP</name>
  7989. <description>I2C2 Fm+ drive capability enable bit</description>
  7990. <bitOffset>13</bitOffset>
  7991. <bitWidth>1</bitWidth>
  7992. </field>
  7993. <field>
  7994. <name>I2C1_FMP</name>
  7995. <description>I2C1 Fm+ drive capability enable bit</description>
  7996. <bitOffset>12</bitOffset>
  7997. <bitWidth>1</bitWidth>
  7998. </field>
  7999. <field>
  8000. <name>I2C_PB9_FMP</name>
  8001. <description>Fm+ drive capability on PB9 enable bit</description>
  8002. <bitOffset>11</bitOffset>
  8003. <bitWidth>1</bitWidth>
  8004. </field>
  8005. <field>
  8006. <name>I2C_PB8_FMP</name>
  8007. <description>Fm+ drive capability on PB8 enable bit</description>
  8008. <bitOffset>10</bitOffset>
  8009. <bitWidth>1</bitWidth>
  8010. </field>
  8011. <field>
  8012. <name>I2C_PB7_FMP</name>
  8013. <description>Fm+ drive capability on PB7 enable bit</description>
  8014. <bitOffset>9</bitOffset>
  8015. <bitWidth>1</bitWidth>
  8016. </field>
  8017. <field>
  8018. <name>I2C_PB6_FMP</name>
  8019. <description>Fm+ drive capability on PB6 enable bit</description>
  8020. <bitOffset>8</bitOffset>
  8021. <bitWidth>1</bitWidth>
  8022. </field>
  8023. <field>
  8024. <name>CAPA</name>
  8025. <description>Configuration of internal VLCD rail connection to optional external capacitor</description>
  8026. <bitOffset>1</bitOffset>
  8027. <bitWidth>3</bitWidth>
  8028. </field>
  8029. <field>
  8030. <name>FWDISEN</name>
  8031. <description>Firewall disable bit</description>
  8032. <bitOffset>0</bitOffset>
  8033. <bitWidth>1</bitWidth>
  8034. </field>
  8035. </fields>
  8036. </register>
  8037. <register>
  8038. <name>EXTICR1</name>
  8039. <displayName>EXTICR1</displayName>
  8040. <description>external interrupt configuration register 1</description>
  8041. <addressOffset>0x8</addressOffset>
  8042. <size>0x20</size>
  8043. <access>read-write</access>
  8044. <resetValue>0x0000</resetValue>
  8045. <fields>
  8046. <field>
  8047. <name>EXTI3</name>
  8048. <description>EXTI x configuration (x = 0 to 3)</description>
  8049. <bitOffset>12</bitOffset>
  8050. <bitWidth>4</bitWidth>
  8051. </field>
  8052. <field>
  8053. <name>EXTI2</name>
  8054. <description>EXTI x configuration (x = 0 to 3)</description>
  8055. <bitOffset>8</bitOffset>
  8056. <bitWidth>4</bitWidth>
  8057. </field>
  8058. <field>
  8059. <name>EXTI1</name>
  8060. <description>EXTI x configuration (x = 0 to 3)</description>
  8061. <bitOffset>4</bitOffset>
  8062. <bitWidth>4</bitWidth>
  8063. </field>
  8064. <field>
  8065. <name>EXTI0</name>
  8066. <description>EXTI x configuration (x = 0 to 3)</description>
  8067. <bitOffset>0</bitOffset>
  8068. <bitWidth>4</bitWidth>
  8069. </field>
  8070. </fields>
  8071. </register>
  8072. <register>
  8073. <name>EXTICR2</name>
  8074. <displayName>EXTICR2</displayName>
  8075. <description>external interrupt configuration register 2</description>
  8076. <addressOffset>0xC</addressOffset>
  8077. <size>0x20</size>
  8078. <access>read-write</access>
  8079. <resetValue>0x0000</resetValue>
  8080. <fields>
  8081. <field>
  8082. <name>EXTI7</name>
  8083. <description>EXTI x configuration (x = 4 to 7)</description>
  8084. <bitOffset>12</bitOffset>
  8085. <bitWidth>4</bitWidth>
  8086. </field>
  8087. <field>
  8088. <name>EXTI6</name>
  8089. <description>EXTI x configuration (x = 4 to 7)</description>
  8090. <bitOffset>8</bitOffset>
  8091. <bitWidth>4</bitWidth>
  8092. </field>
  8093. <field>
  8094. <name>EXTI5</name>
  8095. <description>EXTI x configuration (x = 4 to 7)</description>
  8096. <bitOffset>4</bitOffset>
  8097. <bitWidth>4</bitWidth>
  8098. </field>
  8099. <field>
  8100. <name>EXTI4</name>
  8101. <description>EXTI x configuration (x = 4 to 7)</description>
  8102. <bitOffset>0</bitOffset>
  8103. <bitWidth>4</bitWidth>
  8104. </field>
  8105. </fields>
  8106. </register>
  8107. <register>
  8108. <name>EXTICR3</name>
  8109. <displayName>EXTICR3</displayName>
  8110. <description>external interrupt configuration register 3</description>
  8111. <addressOffset>0x10</addressOffset>
  8112. <size>0x20</size>
  8113. <access>read-write</access>
  8114. <resetValue>0x0000</resetValue>
  8115. <fields>
  8116. <field>
  8117. <name>EXTI11</name>
  8118. <description>EXTI x configuration (x = 8 to 11)</description>
  8119. <bitOffset>12</bitOffset>
  8120. <bitWidth>4</bitWidth>
  8121. </field>
  8122. <field>
  8123. <name>EXTI10</name>
  8124. <description>EXTI10</description>
  8125. <bitOffset>8</bitOffset>
  8126. <bitWidth>4</bitWidth>
  8127. </field>
  8128. <field>
  8129. <name>EXTI9</name>
  8130. <description>EXTI x configuration (x = 8 to 11)</description>
  8131. <bitOffset>4</bitOffset>
  8132. <bitWidth>4</bitWidth>
  8133. </field>
  8134. <field>
  8135. <name>EXTI8</name>
  8136. <description>EXTI x configuration (x = 8 to 11)</description>
  8137. <bitOffset>0</bitOffset>
  8138. <bitWidth>4</bitWidth>
  8139. </field>
  8140. </fields>
  8141. </register>
  8142. <register>
  8143. <name>EXTICR4</name>
  8144. <displayName>EXTICR4</displayName>
  8145. <description>external interrupt configuration register 4</description>
  8146. <addressOffset>0x14</addressOffset>
  8147. <size>0x20</size>
  8148. <access>read-write</access>
  8149. <resetValue>0x0000</resetValue>
  8150. <fields>
  8151. <field>
  8152. <name>EXTI15</name>
  8153. <description>EXTI x configuration (x = 12 to 15)</description>
  8154. <bitOffset>12</bitOffset>
  8155. <bitWidth>4</bitWidth>
  8156. </field>
  8157. <field>
  8158. <name>EXTI14</name>
  8159. <description>EXTI14</description>
  8160. <bitOffset>8</bitOffset>
  8161. <bitWidth>4</bitWidth>
  8162. </field>
  8163. <field>
  8164. <name>EXTI13</name>
  8165. <description>EXTI13</description>
  8166. <bitOffset>4</bitOffset>
  8167. <bitWidth>4</bitWidth>
  8168. </field>
  8169. <field>
  8170. <name>EXTI12</name>
  8171. <description>EXTI12</description>
  8172. <bitOffset>0</bitOffset>
  8173. <bitWidth>4</bitWidth>
  8174. </field>
  8175. </fields>
  8176. </register>
  8177. <register>
  8178. <name>CFGR3</name>
  8179. <displayName>CFGR3</displayName>
  8180. <description>SYSCFG configuration register 3</description>
  8181. <addressOffset>0x20</addressOffset>
  8182. <size>0x20</size>
  8183. <resetValue>0x00000000</resetValue>
  8184. <fields>
  8185. <field>
  8186. <name>REF_LOCK</name>
  8187. <description>REF_CTRL lock bit</description>
  8188. <bitOffset>31</bitOffset>
  8189. <bitWidth>1</bitWidth>
  8190. <access>write-only</access>
  8191. </field>
  8192. <field>
  8193. <name>VREFINT_RDYF</name>
  8194. <description>VREFINT ready flag</description>
  8195. <bitOffset>30</bitOffset>
  8196. <bitWidth>1</bitWidth>
  8197. <access>read-only</access>
  8198. </field>
  8199. <field>
  8200. <name>VREFINT_COMP_RDYF</name>
  8201. <description>VREFINT for comparator ready flag</description>
  8202. <bitOffset>29</bitOffset>
  8203. <bitWidth>1</bitWidth>
  8204. <access>read-only</access>
  8205. </field>
  8206. <field>
  8207. <name>VREFINT_ADC_RDYF</name>
  8208. <description>VREFINT for ADC ready flag</description>
  8209. <bitOffset>28</bitOffset>
  8210. <bitWidth>1</bitWidth>
  8211. <access>read-only</access>
  8212. </field>
  8213. <field>
  8214. <name>SENSOR_ADC_RDYF</name>
  8215. <description>Sensor for ADC ready flag</description>
  8216. <bitOffset>27</bitOffset>
  8217. <bitWidth>1</bitWidth>
  8218. <access>read-only</access>
  8219. </field>
  8220. <field>
  8221. <name>REF_RC48MHz_RDYF</name>
  8222. <description>VREFINT for 48 MHz RC oscillator ready flag</description>
  8223. <bitOffset>26</bitOffset>
  8224. <bitWidth>1</bitWidth>
  8225. <access>read-only</access>
  8226. </field>
  8227. <field>
  8228. <name>ENREF_RC48MHz</name>
  8229. <description>VREFINT reference for 48 MHz RC oscillator enable bit</description>
  8230. <bitOffset>13</bitOffset>
  8231. <bitWidth>1</bitWidth>
  8232. <access>read-write</access>
  8233. </field>
  8234. <field>
  8235. <name>ENBUF_VREFINT_COMP</name>
  8236. <description>VREFINT reference for comparator 2 enable bit</description>
  8237. <bitOffset>12</bitOffset>
  8238. <bitWidth>1</bitWidth>
  8239. <access>read-write</access>
  8240. </field>
  8241. <field>
  8242. <name>ENBUF_SENSOR_ADC</name>
  8243. <description>Sensor reference for ADC enable bit</description>
  8244. <bitOffset>9</bitOffset>
  8245. <bitWidth>1</bitWidth>
  8246. <access>read-write</access>
  8247. </field>
  8248. <field>
  8249. <name>ENBUF_BGAP_ADC</name>
  8250. <description>VREFINT reference for ADC enable bit</description>
  8251. <bitOffset>8</bitOffset>
  8252. <bitWidth>1</bitWidth>
  8253. <access>read-write</access>
  8254. </field>
  8255. <field>
  8256. <name>SEL_VREF_OUT</name>
  8257. <description>BGAP_ADC connection bit</description>
  8258. <bitOffset>4</bitOffset>
  8259. <bitWidth>2</bitWidth>
  8260. <access>read-write</access>
  8261. </field>
  8262. <field>
  8263. <name>EN_BGAP</name>
  8264. <description>Vref Enable bit</description>
  8265. <bitOffset>0</bitOffset>
  8266. <bitWidth>1</bitWidth>
  8267. <access>read-write</access>
  8268. </field>
  8269. </fields>
  8270. </register>
  8271. </registers>
  8272. </peripheral>
  8273. <peripheral>
  8274. <name>SPI1</name>
  8275. <description>Serial peripheral interface</description>
  8276. <groupName>SPI</groupName>
  8277. <baseAddress>0x40013000</baseAddress>
  8278. <addressBlock>
  8279. <offset>0x0</offset>
  8280. <size>0x400</size>
  8281. <usage>registers</usage>
  8282. </addressBlock>
  8283. <registers>
  8284. <register>
  8285. <name>CR1</name>
  8286. <displayName>CR1</displayName>
  8287. <description>control register 1</description>
  8288. <addressOffset>0x0</addressOffset>
  8289. <size>0x20</size>
  8290. <access>read-write</access>
  8291. <resetValue>0x0000</resetValue>
  8292. <fields>
  8293. <field>
  8294. <name>BIDIMODE</name>
  8295. <description>Bidirectional data mode enable</description>
  8296. <bitOffset>15</bitOffset>
  8297. <bitWidth>1</bitWidth>
  8298. </field>
  8299. <field>
  8300. <name>BIDIOE</name>
  8301. <description>Output enable in bidirectional mode</description>
  8302. <bitOffset>14</bitOffset>
  8303. <bitWidth>1</bitWidth>
  8304. </field>
  8305. <field>
  8306. <name>CRCEN</name>
  8307. <description>Hardware CRC calculation enable</description>
  8308. <bitOffset>13</bitOffset>
  8309. <bitWidth>1</bitWidth>
  8310. </field>
  8311. <field>
  8312. <name>CRCNEXT</name>
  8313. <description>CRC transfer next</description>
  8314. <bitOffset>12</bitOffset>
  8315. <bitWidth>1</bitWidth>
  8316. </field>
  8317. <field>
  8318. <name>DFF</name>
  8319. <description>Data frame format</description>
  8320. <bitOffset>11</bitOffset>
  8321. <bitWidth>1</bitWidth>
  8322. </field>
  8323. <field>
  8324. <name>RXONLY</name>
  8325. <description>Receive only</description>
  8326. <bitOffset>10</bitOffset>
  8327. <bitWidth>1</bitWidth>
  8328. </field>
  8329. <field>
  8330. <name>SSM</name>
  8331. <description>Software slave management</description>
  8332. <bitOffset>9</bitOffset>
  8333. <bitWidth>1</bitWidth>
  8334. </field>
  8335. <field>
  8336. <name>SSI</name>
  8337. <description>Internal slave select</description>
  8338. <bitOffset>8</bitOffset>
  8339. <bitWidth>1</bitWidth>
  8340. </field>
  8341. <field>
  8342. <name>LSBFIRST</name>
  8343. <description>Frame format</description>
  8344. <bitOffset>7</bitOffset>
  8345. <bitWidth>1</bitWidth>
  8346. </field>
  8347. <field>
  8348. <name>SPE</name>
  8349. <description>SPI enable</description>
  8350. <bitOffset>6</bitOffset>
  8351. <bitWidth>1</bitWidth>
  8352. </field>
  8353. <field>
  8354. <name>BR</name>
  8355. <description>Baud rate control</description>
  8356. <bitOffset>3</bitOffset>
  8357. <bitWidth>3</bitWidth>
  8358. </field>
  8359. <field>
  8360. <name>MSTR</name>
  8361. <description>Master selection</description>
  8362. <bitOffset>2</bitOffset>
  8363. <bitWidth>1</bitWidth>
  8364. </field>
  8365. <field>
  8366. <name>CPOL</name>
  8367. <description>Clock polarity</description>
  8368. <bitOffset>1</bitOffset>
  8369. <bitWidth>1</bitWidth>
  8370. </field>
  8371. <field>
  8372. <name>CPHA</name>
  8373. <description>Clock phase</description>
  8374. <bitOffset>0</bitOffset>
  8375. <bitWidth>1</bitWidth>
  8376. </field>
  8377. </fields>
  8378. </register>
  8379. <register>
  8380. <name>CR2</name>
  8381. <displayName>CR2</displayName>
  8382. <description>control register 2</description>
  8383. <addressOffset>0x4</addressOffset>
  8384. <size>0x20</size>
  8385. <access>read-write</access>
  8386. <resetValue>0x0000</resetValue>
  8387. <fields>
  8388. <field>
  8389. <name>RXDMAEN</name>
  8390. <description>Rx buffer DMA enable</description>
  8391. <bitOffset>0</bitOffset>
  8392. <bitWidth>1</bitWidth>
  8393. </field>
  8394. <field>
  8395. <name>TXDMAEN</name>
  8396. <description>Tx buffer DMA enable</description>
  8397. <bitOffset>1</bitOffset>
  8398. <bitWidth>1</bitWidth>
  8399. </field>
  8400. <field>
  8401. <name>SSOE</name>
  8402. <description>SS output enable</description>
  8403. <bitOffset>2</bitOffset>
  8404. <bitWidth>1</bitWidth>
  8405. </field>
  8406. <field>
  8407. <name>FRF</name>
  8408. <description>Frame format</description>
  8409. <bitOffset>4</bitOffset>
  8410. <bitWidth>1</bitWidth>
  8411. </field>
  8412. <field>
  8413. <name>ERRIE</name>
  8414. <description>Error interrupt enable</description>
  8415. <bitOffset>5</bitOffset>
  8416. <bitWidth>1</bitWidth>
  8417. </field>
  8418. <field>
  8419. <name>RXNEIE</name>
  8420. <description>RX buffer not empty interrupt enable</description>
  8421. <bitOffset>6</bitOffset>
  8422. <bitWidth>1</bitWidth>
  8423. </field>
  8424. <field>
  8425. <name>TXEIE</name>
  8426. <description>Tx buffer empty interrupt enable</description>
  8427. <bitOffset>7</bitOffset>
  8428. <bitWidth>1</bitWidth>
  8429. </field>
  8430. </fields>
  8431. </register>
  8432. <register>
  8433. <name>SR</name>
  8434. <displayName>SR</displayName>
  8435. <description>status register</description>
  8436. <addressOffset>0x8</addressOffset>
  8437. <size>0x20</size>
  8438. <resetValue>0x0002</resetValue>
  8439. <fields>
  8440. <field>
  8441. <name>RXNE</name>
  8442. <description>Receive buffer not empty</description>
  8443. <bitOffset>0</bitOffset>
  8444. <bitWidth>1</bitWidth>
  8445. <access>read-only</access>
  8446. </field>
  8447. <field>
  8448. <name>TXE</name>
  8449. <description>Transmit buffer empty</description>
  8450. <bitOffset>1</bitOffset>
  8451. <bitWidth>1</bitWidth>
  8452. <access>read-only</access>
  8453. </field>
  8454. <field>
  8455. <name>CHSIDE</name>
  8456. <description>Channel side</description>
  8457. <bitOffset>2</bitOffset>
  8458. <bitWidth>1</bitWidth>
  8459. <access>read-only</access>
  8460. </field>
  8461. <field>
  8462. <name>UDR</name>
  8463. <description>Underrun flag</description>
  8464. <bitOffset>3</bitOffset>
  8465. <bitWidth>1</bitWidth>
  8466. <access>read-only</access>
  8467. </field>
  8468. <field>
  8469. <name>CRCERR</name>
  8470. <description>CRC error flag</description>
  8471. <bitOffset>4</bitOffset>
  8472. <bitWidth>1</bitWidth>
  8473. <access>read-write</access>
  8474. </field>
  8475. <field>
  8476. <name>MODF</name>
  8477. <description>Mode fault</description>
  8478. <bitOffset>5</bitOffset>
  8479. <bitWidth>1</bitWidth>
  8480. <access>read-only</access>
  8481. </field>
  8482. <field>
  8483. <name>OVR</name>
  8484. <description>Overrun flag</description>
  8485. <bitOffset>6</bitOffset>
  8486. <bitWidth>1</bitWidth>
  8487. <access>read-only</access>
  8488. </field>
  8489. <field>
  8490. <name>BSY</name>
  8491. <description>Busy flag</description>
  8492. <bitOffset>7</bitOffset>
  8493. <bitWidth>1</bitWidth>
  8494. <access>read-only</access>
  8495. </field>
  8496. <field>
  8497. <name>TIFRFE</name>
  8498. <description>TI frame format error</description>
  8499. <bitOffset>8</bitOffset>
  8500. <bitWidth>1</bitWidth>
  8501. <access>read-only</access>
  8502. </field>
  8503. </fields>
  8504. </register>
  8505. <register>
  8506. <name>DR</name>
  8507. <displayName>DR</displayName>
  8508. <description>data register</description>
  8509. <addressOffset>0xC</addressOffset>
  8510. <size>0x20</size>
  8511. <access>read-write</access>
  8512. <resetValue>0x0000</resetValue>
  8513. <fields>
  8514. <field>
  8515. <name>DR</name>
  8516. <description>Data register</description>
  8517. <bitOffset>0</bitOffset>
  8518. <bitWidth>16</bitWidth>
  8519. </field>
  8520. </fields>
  8521. </register>
  8522. <register>
  8523. <name>CRCPR</name>
  8524. <displayName>CRCPR</displayName>
  8525. <description>CRC polynomial register</description>
  8526. <addressOffset>0x10</addressOffset>
  8527. <size>0x20</size>
  8528. <access>read-write</access>
  8529. <resetValue>0x0007</resetValue>
  8530. <fields>
  8531. <field>
  8532. <name>CRCPOLY</name>
  8533. <description>CRC polynomial register</description>
  8534. <bitOffset>0</bitOffset>
  8535. <bitWidth>16</bitWidth>
  8536. </field>
  8537. </fields>
  8538. </register>
  8539. <register>
  8540. <name>RXCRCR</name>
  8541. <displayName>RXCRCR</displayName>
  8542. <description>RX CRC register</description>
  8543. <addressOffset>0x14</addressOffset>
  8544. <size>0x20</size>
  8545. <access>read-only</access>
  8546. <resetValue>0x0000</resetValue>
  8547. <fields>
  8548. <field>
  8549. <name>RxCRC</name>
  8550. <description>Rx CRC register</description>
  8551. <bitOffset>0</bitOffset>
  8552. <bitWidth>16</bitWidth>
  8553. </field>
  8554. </fields>
  8555. </register>
  8556. <register>
  8557. <name>TXCRCR</name>
  8558. <displayName>TXCRCR</displayName>
  8559. <description>TX CRC register</description>
  8560. <addressOffset>0x18</addressOffset>
  8561. <size>0x20</size>
  8562. <access>read-only</access>
  8563. <resetValue>0x0000</resetValue>
  8564. <fields>
  8565. <field>
  8566. <name>TxCRC</name>
  8567. <description>Tx CRC register</description>
  8568. <bitOffset>0</bitOffset>
  8569. <bitWidth>16</bitWidth>
  8570. </field>
  8571. </fields>
  8572. </register>
  8573. <register>
  8574. <name>I2SCFGR</name>
  8575. <displayName>I2SCFGR</displayName>
  8576. <description>I2S configuration register</description>
  8577. <addressOffset>0x1C</addressOffset>
  8578. <size>0x20</size>
  8579. <access>read-write</access>
  8580. <resetValue>0x0000</resetValue>
  8581. <fields>
  8582. <field>
  8583. <name>I2SMOD</name>
  8584. <description>I2S mode selection</description>
  8585. <bitOffset>11</bitOffset>
  8586. <bitWidth>1</bitWidth>
  8587. </field>
  8588. <field>
  8589. <name>I2SE</name>
  8590. <description>I2S Enable</description>
  8591. <bitOffset>10</bitOffset>
  8592. <bitWidth>1</bitWidth>
  8593. </field>
  8594. <field>
  8595. <name>I2SCFG</name>
  8596. <description>I2S configuration mode</description>
  8597. <bitOffset>8</bitOffset>
  8598. <bitWidth>2</bitWidth>
  8599. </field>
  8600. <field>
  8601. <name>PCMSYNC</name>
  8602. <description>PCM frame synchronization</description>
  8603. <bitOffset>7</bitOffset>
  8604. <bitWidth>1</bitWidth>
  8605. </field>
  8606. <field>
  8607. <name>I2SSTD</name>
  8608. <description>I2S standard selection</description>
  8609. <bitOffset>4</bitOffset>
  8610. <bitWidth>2</bitWidth>
  8611. </field>
  8612. <field>
  8613. <name>CKPOL</name>
  8614. <description>Steady state clock polarity</description>
  8615. <bitOffset>3</bitOffset>
  8616. <bitWidth>1</bitWidth>
  8617. </field>
  8618. <field>
  8619. <name>DATLEN</name>
  8620. <description>Data length to be transferred</description>
  8621. <bitOffset>1</bitOffset>
  8622. <bitWidth>2</bitWidth>
  8623. </field>
  8624. <field>
  8625. <name>CHLEN</name>
  8626. <description>Channel length (number of bits per audio channel)</description>
  8627. <bitOffset>0</bitOffset>
  8628. <bitWidth>1</bitWidth>
  8629. </field>
  8630. </fields>
  8631. </register>
  8632. <register>
  8633. <name>I2SPR</name>
  8634. <displayName>I2SPR</displayName>
  8635. <description>I2S prescaler register</description>
  8636. <addressOffset>0x20</addressOffset>
  8637. <size>0x20</size>
  8638. <access>read-write</access>
  8639. <resetValue>0x00000010</resetValue>
  8640. <fields>
  8641. <field>
  8642. <name>MCKOE</name>
  8643. <description>Master clock output enable</description>
  8644. <bitOffset>9</bitOffset>
  8645. <bitWidth>1</bitWidth>
  8646. </field>
  8647. <field>
  8648. <name>ODD</name>
  8649. <description>Odd factor for the prescaler</description>
  8650. <bitOffset>8</bitOffset>
  8651. <bitWidth>1</bitWidth>
  8652. </field>
  8653. <field>
  8654. <name>I2SDIV</name>
  8655. <description>I2S Linear prescaler</description>
  8656. <bitOffset>0</bitOffset>
  8657. <bitWidth>8</bitWidth>
  8658. </field>
  8659. </fields>
  8660. </register>
  8661. </registers>
  8662. </peripheral>
  8663. <peripheral>
  8664. <name>I2C1</name>
  8665. <description>Inter-integrated circuit</description>
  8666. <groupName>I2C</groupName>
  8667. <baseAddress>0x40005400</baseAddress>
  8668. <addressBlock>
  8669. <offset>0x0</offset>
  8670. <size>0x400</size>
  8671. <usage>registers</usage>
  8672. </addressBlock>
  8673. <interrupt>
  8674. <name>SPI1</name>
  8675. <description>SPI1_global_interrupt</description>
  8676. <value>25</value>
  8677. </interrupt>
  8678. <registers>
  8679. <register>
  8680. <name>CR1</name>
  8681. <displayName>CR1</displayName>
  8682. <description>Control register 1</description>
  8683. <addressOffset>0x0</addressOffset>
  8684. <size>0x20</size>
  8685. <access>read-write</access>
  8686. <resetValue>0x00000000</resetValue>
  8687. <fields>
  8688. <field>
  8689. <name>PE</name>
  8690. <description>Peripheral enable</description>
  8691. <bitOffset>0</bitOffset>
  8692. <bitWidth>1</bitWidth>
  8693. </field>
  8694. <field>
  8695. <name>TXIE</name>
  8696. <description>TX Interrupt enable</description>
  8697. <bitOffset>1</bitOffset>
  8698. <bitWidth>1</bitWidth>
  8699. </field>
  8700. <field>
  8701. <name>RXIE</name>
  8702. <description>RX Interrupt enable</description>
  8703. <bitOffset>2</bitOffset>
  8704. <bitWidth>1</bitWidth>
  8705. </field>
  8706. <field>
  8707. <name>ADDRIE</name>
  8708. <description>Address match interrupt enable (slave only)</description>
  8709. <bitOffset>3</bitOffset>
  8710. <bitWidth>1</bitWidth>
  8711. </field>
  8712. <field>
  8713. <name>NACKIE</name>
  8714. <description>Not acknowledge received interrupt enable</description>
  8715. <bitOffset>4</bitOffset>
  8716. <bitWidth>1</bitWidth>
  8717. </field>
  8718. <field>
  8719. <name>STOPIE</name>
  8720. <description>STOP detection Interrupt enable</description>
  8721. <bitOffset>5</bitOffset>
  8722. <bitWidth>1</bitWidth>
  8723. </field>
  8724. <field>
  8725. <name>TCIE</name>
  8726. <description>Transfer Complete interrupt enable</description>
  8727. <bitOffset>6</bitOffset>
  8728. <bitWidth>1</bitWidth>
  8729. </field>
  8730. <field>
  8731. <name>ERRIE</name>
  8732. <description>Error interrupts enable</description>
  8733. <bitOffset>7</bitOffset>
  8734. <bitWidth>1</bitWidth>
  8735. </field>
  8736. <field>
  8737. <name>DNF</name>
  8738. <description>Digital noise filter</description>
  8739. <bitOffset>8</bitOffset>
  8740. <bitWidth>4</bitWidth>
  8741. </field>
  8742. <field>
  8743. <name>ANFOFF</name>
  8744. <description>Analog noise filter OFF</description>
  8745. <bitOffset>12</bitOffset>
  8746. <bitWidth>1</bitWidth>
  8747. </field>
  8748. <field>
  8749. <name>TXDMAEN</name>
  8750. <description>DMA transmission requests enable</description>
  8751. <bitOffset>14</bitOffset>
  8752. <bitWidth>1</bitWidth>
  8753. </field>
  8754. <field>
  8755. <name>RXDMAEN</name>
  8756. <description>DMA reception requests enable</description>
  8757. <bitOffset>15</bitOffset>
  8758. <bitWidth>1</bitWidth>
  8759. </field>
  8760. <field>
  8761. <name>SBC</name>
  8762. <description>Slave byte control</description>
  8763. <bitOffset>16</bitOffset>
  8764. <bitWidth>1</bitWidth>
  8765. </field>
  8766. <field>
  8767. <name>NOSTRETCH</name>
  8768. <description>Clock stretching disable</description>
  8769. <bitOffset>17</bitOffset>
  8770. <bitWidth>1</bitWidth>
  8771. </field>
  8772. <field>
  8773. <name>WUPEN</name>
  8774. <description>Wakeup from STOP enable</description>
  8775. <bitOffset>18</bitOffset>
  8776. <bitWidth>1</bitWidth>
  8777. </field>
  8778. <field>
  8779. <name>GCEN</name>
  8780. <description>General call enable</description>
  8781. <bitOffset>19</bitOffset>
  8782. <bitWidth>1</bitWidth>
  8783. </field>
  8784. <field>
  8785. <name>SMBHEN</name>
  8786. <description>SMBus Host address enable</description>
  8787. <bitOffset>20</bitOffset>
  8788. <bitWidth>1</bitWidth>
  8789. </field>
  8790. <field>
  8791. <name>SMBDEN</name>
  8792. <description>SMBus Device Default address enable</description>
  8793. <bitOffset>21</bitOffset>
  8794. <bitWidth>1</bitWidth>
  8795. </field>
  8796. <field>
  8797. <name>ALERTEN</name>
  8798. <description>SMBUS alert enable</description>
  8799. <bitOffset>22</bitOffset>
  8800. <bitWidth>1</bitWidth>
  8801. </field>
  8802. <field>
  8803. <name>PECEN</name>
  8804. <description>PEC enable</description>
  8805. <bitOffset>23</bitOffset>
  8806. <bitWidth>1</bitWidth>
  8807. </field>
  8808. </fields>
  8809. </register>
  8810. <register>
  8811. <name>CR2</name>
  8812. <displayName>CR2</displayName>
  8813. <description>Control register 2</description>
  8814. <addressOffset>0x4</addressOffset>
  8815. <size>0x20</size>
  8816. <access>read-write</access>
  8817. <resetValue>0x00000000</resetValue>
  8818. <fields>
  8819. <field>
  8820. <name>PECBYTE</name>
  8821. <description>Packet error checking byte</description>
  8822. <bitOffset>26</bitOffset>
  8823. <bitWidth>1</bitWidth>
  8824. </field>
  8825. <field>
  8826. <name>AUTOEND</name>
  8827. <description>Automatic end mode (master mode)</description>
  8828. <bitOffset>25</bitOffset>
  8829. <bitWidth>1</bitWidth>
  8830. </field>
  8831. <field>
  8832. <name>RELOAD</name>
  8833. <description>NBYTES reload mode</description>
  8834. <bitOffset>24</bitOffset>
  8835. <bitWidth>1</bitWidth>
  8836. </field>
  8837. <field>
  8838. <name>NBYTES</name>
  8839. <description>Number of bytes</description>
  8840. <bitOffset>16</bitOffset>
  8841. <bitWidth>8</bitWidth>
  8842. </field>
  8843. <field>
  8844. <name>NACK</name>
  8845. <description>NACK generation (slave mode)</description>
  8846. <bitOffset>15</bitOffset>
  8847. <bitWidth>1</bitWidth>
  8848. </field>
  8849. <field>
  8850. <name>STOP</name>
  8851. <description>Stop generation (master mode)</description>
  8852. <bitOffset>14</bitOffset>
  8853. <bitWidth>1</bitWidth>
  8854. </field>
  8855. <field>
  8856. <name>START</name>
  8857. <description>Start generation</description>
  8858. <bitOffset>13</bitOffset>
  8859. <bitWidth>1</bitWidth>
  8860. </field>
  8861. <field>
  8862. <name>HEAD10R</name>
  8863. <description>10-bit address header only read direction (master receiver mode)</description>
  8864. <bitOffset>12</bitOffset>
  8865. <bitWidth>1</bitWidth>
  8866. </field>
  8867. <field>
  8868. <name>ADD10</name>
  8869. <description>10-bit addressing mode (master mode)</description>
  8870. <bitOffset>11</bitOffset>
  8871. <bitWidth>1</bitWidth>
  8872. </field>
  8873. <field>
  8874. <name>RD_WRN</name>
  8875. <description>Transfer direction (master mode)</description>
  8876. <bitOffset>10</bitOffset>
  8877. <bitWidth>1</bitWidth>
  8878. </field>
  8879. <field>
  8880. <name>SADD</name>
  8881. <description>Slave address bit (master mode)</description>
  8882. <bitOffset>0</bitOffset>
  8883. <bitWidth>10</bitWidth>
  8884. </field>
  8885. </fields>
  8886. </register>
  8887. <register>
  8888. <name>OAR1</name>
  8889. <displayName>OAR1</displayName>
  8890. <description>Own address register 1</description>
  8891. <addressOffset>0x8</addressOffset>
  8892. <size>0x20</size>
  8893. <access>read-write</access>
  8894. <resetValue>0x00000000</resetValue>
  8895. <fields>
  8896. <field>
  8897. <name>OA1</name>
  8898. <description>Interface address</description>
  8899. <bitOffset>0</bitOffset>
  8900. <bitWidth>10</bitWidth>
  8901. </field>
  8902. <field>
  8903. <name>OA1MODE</name>
  8904. <description>Own Address 1 10-bit mode</description>
  8905. <bitOffset>10</bitOffset>
  8906. <bitWidth>1</bitWidth>
  8907. </field>
  8908. <field>
  8909. <name>OA1EN</name>
  8910. <description>Own Address 1 enable</description>
  8911. <bitOffset>15</bitOffset>
  8912. <bitWidth>1</bitWidth>
  8913. </field>
  8914. </fields>
  8915. </register>
  8916. <register>
  8917. <name>OAR2</name>
  8918. <displayName>OAR2</displayName>
  8919. <description>Own address register 2</description>
  8920. <addressOffset>0xC</addressOffset>
  8921. <size>0x20</size>
  8922. <access>read-write</access>
  8923. <resetValue>0x00000000</resetValue>
  8924. <fields>
  8925. <field>
  8926. <name>OA2</name>
  8927. <description>Interface address</description>
  8928. <bitOffset>1</bitOffset>
  8929. <bitWidth>7</bitWidth>
  8930. </field>
  8931. <field>
  8932. <name>OA2MSK</name>
  8933. <description>Own Address 2 masks</description>
  8934. <bitOffset>8</bitOffset>
  8935. <bitWidth>3</bitWidth>
  8936. </field>
  8937. <field>
  8938. <name>OA2EN</name>
  8939. <description>Own Address 2 enable</description>
  8940. <bitOffset>15</bitOffset>
  8941. <bitWidth>1</bitWidth>
  8942. </field>
  8943. </fields>
  8944. </register>
  8945. <register>
  8946. <name>TIMINGR</name>
  8947. <displayName>TIMINGR</displayName>
  8948. <description>Timing register</description>
  8949. <addressOffset>0x10</addressOffset>
  8950. <size>0x20</size>
  8951. <access>read-write</access>
  8952. <resetValue>0x00000000</resetValue>
  8953. <fields>
  8954. <field>
  8955. <name>SCLL</name>
  8956. <description>SCL low period (master mode)</description>
  8957. <bitOffset>0</bitOffset>
  8958. <bitWidth>8</bitWidth>
  8959. </field>
  8960. <field>
  8961. <name>SCLH</name>
  8962. <description>SCL high period (master mode)</description>
  8963. <bitOffset>8</bitOffset>
  8964. <bitWidth>8</bitWidth>
  8965. </field>
  8966. <field>
  8967. <name>SDADEL</name>
  8968. <description>Data hold time</description>
  8969. <bitOffset>16</bitOffset>
  8970. <bitWidth>4</bitWidth>
  8971. </field>
  8972. <field>
  8973. <name>SCLDEL</name>
  8974. <description>Data setup time</description>
  8975. <bitOffset>20</bitOffset>
  8976. <bitWidth>4</bitWidth>
  8977. </field>
  8978. <field>
  8979. <name>PRESC</name>
  8980. <description>Timing prescaler</description>
  8981. <bitOffset>28</bitOffset>
  8982. <bitWidth>4</bitWidth>
  8983. </field>
  8984. </fields>
  8985. </register>
  8986. <register>
  8987. <name>TIMEOUTR</name>
  8988. <displayName>TIMEOUTR</displayName>
  8989. <description>Status register 1</description>
  8990. <addressOffset>0x14</addressOffset>
  8991. <size>0x20</size>
  8992. <access>read-write</access>
  8993. <resetValue>0x00000000</resetValue>
  8994. <fields>
  8995. <field>
  8996. <name>TIMEOUTA</name>
  8997. <description>Bus timeout A</description>
  8998. <bitOffset>0</bitOffset>
  8999. <bitWidth>12</bitWidth>
  9000. </field>
  9001. <field>
  9002. <name>TIDLE</name>
  9003. <description>Idle clock timeout detection</description>
  9004. <bitOffset>12</bitOffset>
  9005. <bitWidth>1</bitWidth>
  9006. </field>
  9007. <field>
  9008. <name>TIMOUTEN</name>
  9009. <description>Clock timeout enable</description>
  9010. <bitOffset>15</bitOffset>
  9011. <bitWidth>1</bitWidth>
  9012. </field>
  9013. <field>
  9014. <name>TIMEOUTB</name>
  9015. <description>Bus timeout B</description>
  9016. <bitOffset>16</bitOffset>
  9017. <bitWidth>12</bitWidth>
  9018. </field>
  9019. <field>
  9020. <name>TEXTEN</name>
  9021. <description>Extended clock timeout enable</description>
  9022. <bitOffset>31</bitOffset>
  9023. <bitWidth>1</bitWidth>
  9024. </field>
  9025. </fields>
  9026. </register>
  9027. <register>
  9028. <name>ISR</name>
  9029. <displayName>ISR</displayName>
  9030. <description>Interrupt and Status register</description>
  9031. <addressOffset>0x18</addressOffset>
  9032. <size>0x20</size>
  9033. <resetValue>0x00000001</resetValue>
  9034. <fields>
  9035. <field>
  9036. <name>ADDCODE</name>
  9037. <description>Address match code (Slave mode)</description>
  9038. <bitOffset>17</bitOffset>
  9039. <bitWidth>7</bitWidth>
  9040. <access>read-only</access>
  9041. </field>
  9042. <field>
  9043. <name>DIR</name>
  9044. <description>Transfer direction (Slave mode)</description>
  9045. <bitOffset>16</bitOffset>
  9046. <bitWidth>1</bitWidth>
  9047. <access>read-only</access>
  9048. </field>
  9049. <field>
  9050. <name>BUSY</name>
  9051. <description>Bus busy</description>
  9052. <bitOffset>15</bitOffset>
  9053. <bitWidth>1</bitWidth>
  9054. <access>read-only</access>
  9055. </field>
  9056. <field>
  9057. <name>ALERT</name>
  9058. <description>SMBus alert</description>
  9059. <bitOffset>13</bitOffset>
  9060. <bitWidth>1</bitWidth>
  9061. <access>read-only</access>
  9062. </field>
  9063. <field>
  9064. <name>TIMEOUT</name>
  9065. <description>Timeout or t_low detection flag</description>
  9066. <bitOffset>12</bitOffset>
  9067. <bitWidth>1</bitWidth>
  9068. <access>read-only</access>
  9069. </field>
  9070. <field>
  9071. <name>PECERR</name>
  9072. <description>PEC Error in reception</description>
  9073. <bitOffset>11</bitOffset>
  9074. <bitWidth>1</bitWidth>
  9075. <access>read-only</access>
  9076. </field>
  9077. <field>
  9078. <name>OVR</name>
  9079. <description>Overrun/Underrun (slave mode)</description>
  9080. <bitOffset>10</bitOffset>
  9081. <bitWidth>1</bitWidth>
  9082. <access>read-only</access>
  9083. </field>
  9084. <field>
  9085. <name>ARLO</name>
  9086. <description>Arbitration lost</description>
  9087. <bitOffset>9</bitOffset>
  9088. <bitWidth>1</bitWidth>
  9089. <access>read-only</access>
  9090. </field>
  9091. <field>
  9092. <name>BERR</name>
  9093. <description>Bus error</description>
  9094. <bitOffset>8</bitOffset>
  9095. <bitWidth>1</bitWidth>
  9096. <access>read-only</access>
  9097. </field>
  9098. <field>
  9099. <name>TCR</name>
  9100. <description>Transfer Complete Reload</description>
  9101. <bitOffset>7</bitOffset>
  9102. <bitWidth>1</bitWidth>
  9103. <access>read-only</access>
  9104. </field>
  9105. <field>
  9106. <name>TC</name>
  9107. <description>Transfer Complete (master mode)</description>
  9108. <bitOffset>6</bitOffset>
  9109. <bitWidth>1</bitWidth>
  9110. <access>read-only</access>
  9111. </field>
  9112. <field>
  9113. <name>STOPF</name>
  9114. <description>Stop detection flag</description>
  9115. <bitOffset>5</bitOffset>
  9116. <bitWidth>1</bitWidth>
  9117. <access>read-only</access>
  9118. </field>
  9119. <field>
  9120. <name>NACKF</name>
  9121. <description>Not acknowledge received flag</description>
  9122. <bitOffset>4</bitOffset>
  9123. <bitWidth>1</bitWidth>
  9124. <access>read-only</access>
  9125. </field>
  9126. <field>
  9127. <name>ADDR</name>
  9128. <description>Address matched (slave mode)</description>
  9129. <bitOffset>3</bitOffset>
  9130. <bitWidth>1</bitWidth>
  9131. <access>read-only</access>
  9132. </field>
  9133. <field>
  9134. <name>RXNE</name>
  9135. <description>Receive data register not empty (receivers)</description>
  9136. <bitOffset>2</bitOffset>
  9137. <bitWidth>1</bitWidth>
  9138. <access>read-only</access>
  9139. </field>
  9140. <field>
  9141. <name>TXIS</name>
  9142. <description>Transmit interrupt status (transmitters)</description>
  9143. <bitOffset>1</bitOffset>
  9144. <bitWidth>1</bitWidth>
  9145. <access>read-write</access>
  9146. </field>
  9147. <field>
  9148. <name>TXE</name>
  9149. <description>Transmit data register empty (transmitters)</description>
  9150. <bitOffset>0</bitOffset>
  9151. <bitWidth>1</bitWidth>
  9152. <access>read-write</access>
  9153. </field>
  9154. </fields>
  9155. </register>
  9156. <register>
  9157. <name>ICR</name>
  9158. <displayName>ICR</displayName>
  9159. <description>Interrupt clear register</description>
  9160. <addressOffset>0x1C</addressOffset>
  9161. <size>0x20</size>
  9162. <access>write-only</access>
  9163. <resetValue>0x00000000</resetValue>
  9164. <fields>
  9165. <field>
  9166. <name>ALERTCF</name>
  9167. <description>Alert flag clear</description>
  9168. <bitOffset>13</bitOffset>
  9169. <bitWidth>1</bitWidth>
  9170. </field>
  9171. <field>
  9172. <name>TIMOUTCF</name>
  9173. <description>Timeout detection flag clear</description>
  9174. <bitOffset>12</bitOffset>
  9175. <bitWidth>1</bitWidth>
  9176. </field>
  9177. <field>
  9178. <name>PECCF</name>
  9179. <description>PEC Error flag clear</description>
  9180. <bitOffset>11</bitOffset>
  9181. <bitWidth>1</bitWidth>
  9182. </field>
  9183. <field>
  9184. <name>OVRCF</name>
  9185. <description>Overrun/Underrun flag clear</description>
  9186. <bitOffset>10</bitOffset>
  9187. <bitWidth>1</bitWidth>
  9188. </field>
  9189. <field>
  9190. <name>ARLOCF</name>
  9191. <description>Arbitration lost flag clear</description>
  9192. <bitOffset>9</bitOffset>
  9193. <bitWidth>1</bitWidth>
  9194. </field>
  9195. <field>
  9196. <name>BERRCF</name>
  9197. <description>Bus error flag clear</description>
  9198. <bitOffset>8</bitOffset>
  9199. <bitWidth>1</bitWidth>
  9200. </field>
  9201. <field>
  9202. <name>STOPCF</name>
  9203. <description>Stop detection flag clear</description>
  9204. <bitOffset>5</bitOffset>
  9205. <bitWidth>1</bitWidth>
  9206. </field>
  9207. <field>
  9208. <name>NACKCF</name>
  9209. <description>Not Acknowledge flag clear</description>
  9210. <bitOffset>4</bitOffset>
  9211. <bitWidth>1</bitWidth>
  9212. </field>
  9213. <field>
  9214. <name>ADDRCF</name>
  9215. <description>Address Matched flag clear</description>
  9216. <bitOffset>3</bitOffset>
  9217. <bitWidth>1</bitWidth>
  9218. </field>
  9219. </fields>
  9220. </register>
  9221. <register>
  9222. <name>PECR</name>
  9223. <displayName>PECR</displayName>
  9224. <description>PEC register</description>
  9225. <addressOffset>0x20</addressOffset>
  9226. <size>0x20</size>
  9227. <access>read-only</access>
  9228. <resetValue>0x00000000</resetValue>
  9229. <fields>
  9230. <field>
  9231. <name>PEC</name>
  9232. <description>Packet error checking register</description>
  9233. <bitOffset>0</bitOffset>
  9234. <bitWidth>8</bitWidth>
  9235. </field>
  9236. </fields>
  9237. </register>
  9238. <register>
  9239. <name>RXDR</name>
  9240. <displayName>RXDR</displayName>
  9241. <description>Receive data register</description>
  9242. <addressOffset>0x24</addressOffset>
  9243. <size>0x20</size>
  9244. <access>read-only</access>
  9245. <resetValue>0x00000000</resetValue>
  9246. <fields>
  9247. <field>
  9248. <name>RXDATA</name>
  9249. <description>8-bit receive data</description>
  9250. <bitOffset>0</bitOffset>
  9251. <bitWidth>8</bitWidth>
  9252. </field>
  9253. </fields>
  9254. </register>
  9255. <register>
  9256. <name>TXDR</name>
  9257. <displayName>TXDR</displayName>
  9258. <description>Transmit data register</description>
  9259. <addressOffset>0x28</addressOffset>
  9260. <size>0x20</size>
  9261. <access>read-write</access>
  9262. <resetValue>0x00000000</resetValue>
  9263. <fields>
  9264. <field>
  9265. <name>TXDATA</name>
  9266. <description>8-bit transmit data</description>
  9267. <bitOffset>0</bitOffset>
  9268. <bitWidth>8</bitWidth>
  9269. </field>
  9270. </fields>
  9271. </register>
  9272. </registers>
  9273. </peripheral>
  9274. <peripheral>
  9275. <name>PWR</name>
  9276. <description>Power control</description>
  9277. <groupName>PWR</groupName>
  9278. <baseAddress>0x40007000</baseAddress>
  9279. <addressBlock>
  9280. <offset>0x0</offset>
  9281. <size>0x400</size>
  9282. <usage>registers</usage>
  9283. </addressBlock>
  9284. <interrupt>
  9285. <name>I2C1</name>
  9286. <description>I2C1 global interrupt</description>
  9287. <value>23</value>
  9288. </interrupt>
  9289. <registers>
  9290. <register>
  9291. <name>CR</name>
  9292. <displayName>CR</displayName>
  9293. <description>power control register</description>
  9294. <addressOffset>0x0</addressOffset>
  9295. <size>0x20</size>
  9296. <access>read-write</access>
  9297. <resetValue>0x00001000</resetValue>
  9298. <fields>
  9299. <field>
  9300. <name>LPDS</name>
  9301. <description>Low-power deep sleep</description>
  9302. <bitOffset>0</bitOffset>
  9303. <bitWidth>1</bitWidth>
  9304. </field>
  9305. <field>
  9306. <name>PDDS</name>
  9307. <description>Power down deepsleep</description>
  9308. <bitOffset>1</bitOffset>
  9309. <bitWidth>1</bitWidth>
  9310. </field>
  9311. <field>
  9312. <name>CWUF</name>
  9313. <description>Clear wakeup flag</description>
  9314. <bitOffset>2</bitOffset>
  9315. <bitWidth>1</bitWidth>
  9316. </field>
  9317. <field>
  9318. <name>CSBF</name>
  9319. <description>Clear standby flag</description>
  9320. <bitOffset>3</bitOffset>
  9321. <bitWidth>1</bitWidth>
  9322. </field>
  9323. <field>
  9324. <name>PVDE</name>
  9325. <description>Power voltage detector enable</description>
  9326. <bitOffset>4</bitOffset>
  9327. <bitWidth>1</bitWidth>
  9328. </field>
  9329. <field>
  9330. <name>PLS</name>
  9331. <description>PVD level selection</description>
  9332. <bitOffset>5</bitOffset>
  9333. <bitWidth>3</bitWidth>
  9334. </field>
  9335. <field>
  9336. <name>DBP</name>
  9337. <description>Disable backup domain write protection</description>
  9338. <bitOffset>8</bitOffset>
  9339. <bitWidth>1</bitWidth>
  9340. </field>
  9341. <field>
  9342. <name>ULP</name>
  9343. <description>Ultra-low-power mode</description>
  9344. <bitOffset>9</bitOffset>
  9345. <bitWidth>1</bitWidth>
  9346. </field>
  9347. <field>
  9348. <name>FWU</name>
  9349. <description>Fast wakeup</description>
  9350. <bitOffset>10</bitOffset>
  9351. <bitWidth>1</bitWidth>
  9352. </field>
  9353. <field>
  9354. <name>VOS</name>
  9355. <description>Voltage scaling range selection</description>
  9356. <bitOffset>11</bitOffset>
  9357. <bitWidth>2</bitWidth>
  9358. </field>
  9359. <field>
  9360. <name>DS_EE_KOFF</name>
  9361. <description>Deep sleep mode with Flash memory kept off</description>
  9362. <bitOffset>13</bitOffset>
  9363. <bitWidth>1</bitWidth>
  9364. </field>
  9365. <field>
  9366. <name>LPRUN</name>
  9367. <description>Low power run mode</description>
  9368. <bitOffset>14</bitOffset>
  9369. <bitWidth>1</bitWidth>
  9370. </field>
  9371. </fields>
  9372. </register>
  9373. <register>
  9374. <name>CSR</name>
  9375. <displayName>CSR</displayName>
  9376. <description>power control/status register</description>
  9377. <addressOffset>0x4</addressOffset>
  9378. <size>0x20</size>
  9379. <resetValue>0x00000000</resetValue>
  9380. <fields>
  9381. <field>
  9382. <name>BRE</name>
  9383. <description>Backup regulator enable</description>
  9384. <bitOffset>9</bitOffset>
  9385. <bitWidth>1</bitWidth>
  9386. <access>read-write</access>
  9387. </field>
  9388. <field>
  9389. <name>EWUP</name>
  9390. <description>Enable WKUP pin</description>
  9391. <bitOffset>8</bitOffset>
  9392. <bitWidth>1</bitWidth>
  9393. <access>read-write</access>
  9394. </field>
  9395. <field>
  9396. <name>BRR</name>
  9397. <description>Backup regulator ready</description>
  9398. <bitOffset>3</bitOffset>
  9399. <bitWidth>1</bitWidth>
  9400. <access>read-only</access>
  9401. </field>
  9402. <field>
  9403. <name>PVDO</name>
  9404. <description>PVD output</description>
  9405. <bitOffset>2</bitOffset>
  9406. <bitWidth>1</bitWidth>
  9407. <access>read-only</access>
  9408. </field>
  9409. <field>
  9410. <name>SBF</name>
  9411. <description>Standby flag</description>
  9412. <bitOffset>1</bitOffset>
  9413. <bitWidth>1</bitWidth>
  9414. <access>read-only</access>
  9415. </field>
  9416. <field>
  9417. <name>WUF</name>
  9418. <description>Wakeup flag</description>
  9419. <bitOffset>0</bitOffset>
  9420. <bitWidth>1</bitWidth>
  9421. <access>read-only</access>
  9422. </field>
  9423. <field>
  9424. <name>VOSF</name>
  9425. <description>Voltage Scaling select flag</description>
  9426. <bitOffset>4</bitOffset>
  9427. <bitWidth>1</bitWidth>
  9428. <access>read-only</access>
  9429. </field>
  9430. <field>
  9431. <name>REGLPF</name>
  9432. <description>Regulator LP flag</description>
  9433. <bitOffset>5</bitOffset>
  9434. <bitWidth>1</bitWidth>
  9435. <access>read-only</access>
  9436. </field>
  9437. </fields>
  9438. </register>
  9439. </registers>
  9440. </peripheral>
  9441. <peripheral>
  9442. <name>Flash</name>
  9443. <description>Flash</description>
  9444. <groupName>Flash</groupName>
  9445. <baseAddress>0x40022000</baseAddress>
  9446. <addressBlock>
  9447. <offset>0x0</offset>
  9448. <size>0x400</size>
  9449. <usage>registers</usage>
  9450. </addressBlock>
  9451. <registers>
  9452. <register>
  9453. <name>ACR</name>
  9454. <displayName>ACR</displayName>
  9455. <description>Access control register</description>
  9456. <addressOffset>0x0</addressOffset>
  9457. <size>0x20</size>
  9458. <access>read-write</access>
  9459. <resetValue>0x00000000</resetValue>
  9460. <fields>
  9461. <field>
  9462. <name>LATENCY</name>
  9463. <description>Latency</description>
  9464. <bitOffset>0</bitOffset>
  9465. <bitWidth>1</bitWidth>
  9466. </field>
  9467. <field>
  9468. <name>PRFTEN</name>
  9469. <description>Prefetch enable</description>
  9470. <bitOffset>1</bitOffset>
  9471. <bitWidth>1</bitWidth>
  9472. </field>
  9473. <field>
  9474. <name>SLEEP_PD</name>
  9475. <description>Flash mode during Sleep</description>
  9476. <bitOffset>3</bitOffset>
  9477. <bitWidth>1</bitWidth>
  9478. </field>
  9479. <field>
  9480. <name>RUN_PD</name>
  9481. <description>Flash mode during Run</description>
  9482. <bitOffset>4</bitOffset>
  9483. <bitWidth>1</bitWidth>
  9484. </field>
  9485. <field>
  9486. <name>DESAB_BUF</name>
  9487. <description>Disable Buffer</description>
  9488. <bitOffset>5</bitOffset>
  9489. <bitWidth>1</bitWidth>
  9490. </field>
  9491. <field>
  9492. <name>PRE_READ</name>
  9493. <description>Pre-read data address</description>
  9494. <bitOffset>6</bitOffset>
  9495. <bitWidth>1</bitWidth>
  9496. </field>
  9497. </fields>
  9498. </register>
  9499. <register>
  9500. <name>PECR</name>
  9501. <displayName>PECR</displayName>
  9502. <description>Program/erase control register</description>
  9503. <addressOffset>0x4</addressOffset>
  9504. <size>0x20</size>
  9505. <access>read-write</access>
  9506. <resetValue>0x00000007</resetValue>
  9507. <fields>
  9508. <field>
  9509. <name>PELOCK</name>
  9510. <description>FLASH_PECR and data EEPROM lock</description>
  9511. <bitOffset>0</bitOffset>
  9512. <bitWidth>1</bitWidth>
  9513. </field>
  9514. <field>
  9515. <name>PRGLOCK</name>
  9516. <description>Program memory lock</description>
  9517. <bitOffset>1</bitOffset>
  9518. <bitWidth>1</bitWidth>
  9519. </field>
  9520. <field>
  9521. <name>OPTLOCK</name>
  9522. <description>Option bytes block lock</description>
  9523. <bitOffset>2</bitOffset>
  9524. <bitWidth>1</bitWidth>
  9525. </field>
  9526. <field>
  9527. <name>PROG</name>
  9528. <description>Program memory selection</description>
  9529. <bitOffset>3</bitOffset>
  9530. <bitWidth>1</bitWidth>
  9531. </field>
  9532. <field>
  9533. <name>DATA</name>
  9534. <description>Data EEPROM selection</description>
  9535. <bitOffset>4</bitOffset>
  9536. <bitWidth>1</bitWidth>
  9537. </field>
  9538. <field>
  9539. <name>FTDW</name>
  9540. <description>Fixed time data write for Byte, Half Word and Word programming</description>
  9541. <bitOffset>8</bitOffset>
  9542. <bitWidth>1</bitWidth>
  9543. </field>
  9544. <field>
  9545. <name>ERASE</name>
  9546. <description>Page or Double Word erase mode</description>
  9547. <bitOffset>9</bitOffset>
  9548. <bitWidth>1</bitWidth>
  9549. </field>
  9550. <field>
  9551. <name>FPRG</name>
  9552. <description>Half Page/Double Word programming mode</description>
  9553. <bitOffset>10</bitOffset>
  9554. <bitWidth>1</bitWidth>
  9555. </field>
  9556. <field>
  9557. <name>PARALLELBANK</name>
  9558. <description>Parallel bank mode</description>
  9559. <bitOffset>15</bitOffset>
  9560. <bitWidth>1</bitWidth>
  9561. </field>
  9562. <field>
  9563. <name>EOPIE</name>
  9564. <description>End of programming interrupt enable</description>
  9565. <bitOffset>16</bitOffset>
  9566. <bitWidth>1</bitWidth>
  9567. </field>
  9568. <field>
  9569. <name>ERRIE</name>
  9570. <description>Error interrupt enable</description>
  9571. <bitOffset>17</bitOffset>
  9572. <bitWidth>1</bitWidth>
  9573. </field>
  9574. <field>
  9575. <name>OBL_LAUNCH</name>
  9576. <description>Launch the option byte loading</description>
  9577. <bitOffset>18</bitOffset>
  9578. <bitWidth>1</bitWidth>
  9579. </field>
  9580. </fields>
  9581. </register>
  9582. <register>
  9583. <name>PDKEYR</name>
  9584. <displayName>PDKEYR</displayName>
  9585. <description>Power down key register</description>
  9586. <addressOffset>0x8</addressOffset>
  9587. <size>0x20</size>
  9588. <access>write-only</access>
  9589. <resetValue>0x00000000</resetValue>
  9590. <fields>
  9591. <field>
  9592. <name>PDKEYR</name>
  9593. <description>RUN_PD in FLASH_ACR key</description>
  9594. <bitOffset>0</bitOffset>
  9595. <bitWidth>32</bitWidth>
  9596. </field>
  9597. </fields>
  9598. </register>
  9599. <register>
  9600. <name>PEKEYR</name>
  9601. <displayName>PEKEYR</displayName>
  9602. <description>Program/erase key register</description>
  9603. <addressOffset>0xC</addressOffset>
  9604. <size>0x20</size>
  9605. <access>write-only</access>
  9606. <resetValue>0x00000000</resetValue>
  9607. <fields>
  9608. <field>
  9609. <name>PEKEYR</name>
  9610. <description>FLASH_PEC and data EEPROM key</description>
  9611. <bitOffset>0</bitOffset>
  9612. <bitWidth>32</bitWidth>
  9613. </field>
  9614. </fields>
  9615. </register>
  9616. <register>
  9617. <name>PRGKEYR</name>
  9618. <displayName>PRGKEYR</displayName>
  9619. <description>Program memory key register</description>
  9620. <addressOffset>0x10</addressOffset>
  9621. <size>0x20</size>
  9622. <access>write-only</access>
  9623. <resetValue>0x00000000</resetValue>
  9624. <fields>
  9625. <field>
  9626. <name>PRGKEYR</name>
  9627. <description>Program memory key</description>
  9628. <bitOffset>0</bitOffset>
  9629. <bitWidth>32</bitWidth>
  9630. </field>
  9631. </fields>
  9632. </register>
  9633. <register>
  9634. <name>OPTKEYR</name>
  9635. <displayName>OPTKEYR</displayName>
  9636. <description>Option byte key register</description>
  9637. <addressOffset>0x14</addressOffset>
  9638. <size>0x20</size>
  9639. <access>write-only</access>
  9640. <resetValue>0x00000000</resetValue>
  9641. <fields>
  9642. <field>
  9643. <name>OPTKEYR</name>
  9644. <description>Option byte key</description>
  9645. <bitOffset>0</bitOffset>
  9646. <bitWidth>32</bitWidth>
  9647. </field>
  9648. </fields>
  9649. </register>
  9650. <register>
  9651. <name>SR</name>
  9652. <displayName>SR</displayName>
  9653. <description>Status register</description>
  9654. <addressOffset>0x18</addressOffset>
  9655. <size>0x20</size>
  9656. <resetValue>0x00000004</resetValue>
  9657. <fields>
  9658. <field>
  9659. <name>BSY</name>
  9660. <description>Write/erase operations in progress</description>
  9661. <bitOffset>0</bitOffset>
  9662. <bitWidth>1</bitWidth>
  9663. <access>read-only</access>
  9664. </field>
  9665. <field>
  9666. <name>EOP</name>
  9667. <description>End of operation</description>
  9668. <bitOffset>1</bitOffset>
  9669. <bitWidth>1</bitWidth>
  9670. <access>read-only</access>
  9671. </field>
  9672. <field>
  9673. <name>ENDHV</name>
  9674. <description>End of high voltage</description>
  9675. <bitOffset>2</bitOffset>
  9676. <bitWidth>1</bitWidth>
  9677. <access>read-only</access>
  9678. </field>
  9679. <field>
  9680. <name>READY</name>
  9681. <description>Flash memory module ready after low power mode</description>
  9682. <bitOffset>3</bitOffset>
  9683. <bitWidth>1</bitWidth>
  9684. <access>read-only</access>
  9685. </field>
  9686. <field>
  9687. <name>WRPERR</name>
  9688. <description>Write protected error</description>
  9689. <bitOffset>8</bitOffset>
  9690. <bitWidth>1</bitWidth>
  9691. <access>read-write</access>
  9692. </field>
  9693. <field>
  9694. <name>PGAERR</name>
  9695. <description>Programming alignment error</description>
  9696. <bitOffset>9</bitOffset>
  9697. <bitWidth>1</bitWidth>
  9698. <access>read-write</access>
  9699. </field>
  9700. <field>
  9701. <name>SIZERR</name>
  9702. <description>Size error</description>
  9703. <bitOffset>10</bitOffset>
  9704. <bitWidth>1</bitWidth>
  9705. <access>read-write</access>
  9706. </field>
  9707. <field>
  9708. <name>OPTVERR</name>
  9709. <description>Option validity error</description>
  9710. <bitOffset>11</bitOffset>
  9711. <bitWidth>1</bitWidth>
  9712. <access>read-write</access>
  9713. </field>
  9714. <field>
  9715. <name>RDERR</name>
  9716. <description>RDERR</description>
  9717. <bitOffset>14</bitOffset>
  9718. <bitWidth>1</bitWidth>
  9719. <access>read-write</access>
  9720. </field>
  9721. <field>
  9722. <name>NOTZEROERR</name>
  9723. <description>NOTZEROERR</description>
  9724. <bitOffset>16</bitOffset>
  9725. <bitWidth>1</bitWidth>
  9726. <access>read-write</access>
  9727. </field>
  9728. <field>
  9729. <name>FWWERR</name>
  9730. <description>FWWERR</description>
  9731. <bitOffset>17</bitOffset>
  9732. <bitWidth>1</bitWidth>
  9733. <access>read-write</access>
  9734. </field>
  9735. </fields>
  9736. </register>
  9737. <register>
  9738. <name>OBR</name>
  9739. <displayName>OBR</displayName>
  9740. <description>Option byte register</description>
  9741. <addressOffset>0x1C</addressOffset>
  9742. <size>0x20</size>
  9743. <access>read-only</access>
  9744. <resetValue>0x00F80000</resetValue>
  9745. <fields>
  9746. <field>
  9747. <name>RDPRT</name>
  9748. <description>Read protection</description>
  9749. <bitOffset>0</bitOffset>
  9750. <bitWidth>8</bitWidth>
  9751. </field>
  9752. <field>
  9753. <name>BOR_LEV</name>
  9754. <description>BOR_LEV</description>
  9755. <bitOffset>16</bitOffset>
  9756. <bitWidth>4</bitWidth>
  9757. </field>
  9758. <field>
  9759. <name>SPRMOD</name>
  9760. <description>Selection of protection mode of WPR bits</description>
  9761. <bitOffset>8</bitOffset>
  9762. <bitWidth>1</bitWidth>
  9763. </field>
  9764. </fields>
  9765. </register>
  9766. <register>
  9767. <name>WRPR</name>
  9768. <displayName>WRPR</displayName>
  9769. <description>Write protection register</description>
  9770. <addressOffset>0x20</addressOffset>
  9771. <size>0x20</size>
  9772. <access>read-write</access>
  9773. <resetValue>0x00000000</resetValue>
  9774. <fields>
  9775. <field>
  9776. <name>WRP</name>
  9777. <description>Write protection</description>
  9778. <bitOffset>0</bitOffset>
  9779. <bitWidth>16</bitWidth>
  9780. </field>
  9781. </fields>
  9782. </register>
  9783. </registers>
  9784. </peripheral>
  9785. <peripheral>
  9786. <name>EXTI</name>
  9787. <description>External interrupt/event controller</description>
  9788. <groupName>EXTI</groupName>
  9789. <baseAddress>0x40010400</baseAddress>
  9790. <addressBlock>
  9791. <offset>0x0</offset>
  9792. <size>0x400</size>
  9793. <usage>registers</usage>
  9794. </addressBlock>
  9795. <interrupt>
  9796. <name>FLASH</name>
  9797. <description>Flash global interrupt</description>
  9798. <value>3</value>
  9799. </interrupt>
  9800. <registers>
  9801. <register>
  9802. <name>IMR</name>
  9803. <displayName>IMR</displayName>
  9804. <description>Interrupt mask register (EXTI_IMR)</description>
  9805. <addressOffset>0x0</addressOffset>
  9806. <size>0x20</size>
  9807. <access>read-write</access>
  9808. <resetValue>0xFF840000</resetValue>
  9809. <fields>
  9810. <field>
  9811. <name>IM0</name>
  9812. <description>Interrupt Mask on line 0</description>
  9813. <bitOffset>0</bitOffset>
  9814. <bitWidth>1</bitWidth>
  9815. </field>
  9816. <field>
  9817. <name>IM1</name>
  9818. <description>Interrupt Mask on line 1</description>
  9819. <bitOffset>1</bitOffset>
  9820. <bitWidth>1</bitWidth>
  9821. </field>
  9822. <field>
  9823. <name>IM2</name>
  9824. <description>Interrupt Mask on line 2</description>
  9825. <bitOffset>2</bitOffset>
  9826. <bitWidth>1</bitWidth>
  9827. </field>
  9828. <field>
  9829. <name>IM3</name>
  9830. <description>Interrupt Mask on line 3</description>
  9831. <bitOffset>3</bitOffset>
  9832. <bitWidth>1</bitWidth>
  9833. </field>
  9834. <field>
  9835. <name>IM4</name>
  9836. <description>Interrupt Mask on line 4</description>
  9837. <bitOffset>4</bitOffset>
  9838. <bitWidth>1</bitWidth>
  9839. </field>
  9840. <field>
  9841. <name>IM5</name>
  9842. <description>Interrupt Mask on line 5</description>
  9843. <bitOffset>5</bitOffset>
  9844. <bitWidth>1</bitWidth>
  9845. </field>
  9846. <field>
  9847. <name>IM6</name>
  9848. <description>Interrupt Mask on line 6</description>
  9849. <bitOffset>6</bitOffset>
  9850. <bitWidth>1</bitWidth>
  9851. </field>
  9852. <field>
  9853. <name>IM7</name>
  9854. <description>Interrupt Mask on line 7</description>
  9855. <bitOffset>7</bitOffset>
  9856. <bitWidth>1</bitWidth>
  9857. </field>
  9858. <field>
  9859. <name>IM8</name>
  9860. <description>Interrupt Mask on line 8</description>
  9861. <bitOffset>8</bitOffset>
  9862. <bitWidth>1</bitWidth>
  9863. </field>
  9864. <field>
  9865. <name>IM9</name>
  9866. <description>Interrupt Mask on line 9</description>
  9867. <bitOffset>9</bitOffset>
  9868. <bitWidth>1</bitWidth>
  9869. </field>
  9870. <field>
  9871. <name>IM10</name>
  9872. <description>Interrupt Mask on line 10</description>
  9873. <bitOffset>10</bitOffset>
  9874. <bitWidth>1</bitWidth>
  9875. </field>
  9876. <field>
  9877. <name>IM11</name>
  9878. <description>Interrupt Mask on line 11</description>
  9879. <bitOffset>11</bitOffset>
  9880. <bitWidth>1</bitWidth>
  9881. </field>
  9882. <field>
  9883. <name>IM12</name>
  9884. <description>Interrupt Mask on line 12</description>
  9885. <bitOffset>12</bitOffset>
  9886. <bitWidth>1</bitWidth>
  9887. </field>
  9888. <field>
  9889. <name>IM13</name>
  9890. <description>Interrupt Mask on line 13</description>
  9891. <bitOffset>13</bitOffset>
  9892. <bitWidth>1</bitWidth>
  9893. </field>
  9894. <field>
  9895. <name>IM14</name>
  9896. <description>Interrupt Mask on line 14</description>
  9897. <bitOffset>14</bitOffset>
  9898. <bitWidth>1</bitWidth>
  9899. </field>
  9900. <field>
  9901. <name>IM15</name>
  9902. <description>Interrupt Mask on line 15</description>
  9903. <bitOffset>15</bitOffset>
  9904. <bitWidth>1</bitWidth>
  9905. </field>
  9906. <field>
  9907. <name>IM16</name>
  9908. <description>Interrupt Mask on line 16</description>
  9909. <bitOffset>16</bitOffset>
  9910. <bitWidth>1</bitWidth>
  9911. </field>
  9912. <field>
  9913. <name>IM17</name>
  9914. <description>Interrupt Mask on line 17</description>
  9915. <bitOffset>17</bitOffset>
  9916. <bitWidth>1</bitWidth>
  9917. </field>
  9918. <field>
  9919. <name>IM18</name>
  9920. <description>Interrupt Mask on line 18</description>
  9921. <bitOffset>18</bitOffset>
  9922. <bitWidth>1</bitWidth>
  9923. </field>
  9924. <field>
  9925. <name>IM19</name>
  9926. <description>Interrupt Mask on line 19</description>
  9927. <bitOffset>19</bitOffset>
  9928. <bitWidth>1</bitWidth>
  9929. </field>
  9930. <field>
  9931. <name>IM20</name>
  9932. <description>Interrupt Mask on line 20</description>
  9933. <bitOffset>20</bitOffset>
  9934. <bitWidth>1</bitWidth>
  9935. </field>
  9936. <field>
  9937. <name>IM21</name>
  9938. <description>Interrupt Mask on line 21</description>
  9939. <bitOffset>21</bitOffset>
  9940. <bitWidth>1</bitWidth>
  9941. </field>
  9942. <field>
  9943. <name>IM22</name>
  9944. <description>Interrupt Mask on line 22</description>
  9945. <bitOffset>22</bitOffset>
  9946. <bitWidth>1</bitWidth>
  9947. </field>
  9948. <field>
  9949. <name>IM23</name>
  9950. <description>Interrupt Mask on line 23</description>
  9951. <bitOffset>23</bitOffset>
  9952. <bitWidth>1</bitWidth>
  9953. </field>
  9954. <field>
  9955. <name>IM24</name>
  9956. <description>Interrupt Mask on line 24</description>
  9957. <bitOffset>24</bitOffset>
  9958. <bitWidth>1</bitWidth>
  9959. </field>
  9960. <field>
  9961. <name>IM25</name>
  9962. <description>Interrupt Mask on line 25</description>
  9963. <bitOffset>25</bitOffset>
  9964. <bitWidth>1</bitWidth>
  9965. </field>
  9966. <field>
  9967. <name>IM26</name>
  9968. <description>Interrupt Mask on line 27</description>
  9969. <bitOffset>26</bitOffset>
  9970. <bitWidth>1</bitWidth>
  9971. </field>
  9972. <field>
  9973. <name>IM28</name>
  9974. <description>Interrupt Mask on line 27</description>
  9975. <bitOffset>28</bitOffset>
  9976. <bitWidth>1</bitWidth>
  9977. </field>
  9978. <field>
  9979. <name>IM29</name>
  9980. <description>Interrupt Mask on line 27</description>
  9981. <bitOffset>29</bitOffset>
  9982. <bitWidth>1</bitWidth>
  9983. </field>
  9984. </fields>
  9985. </register>
  9986. <register>
  9987. <name>EMR</name>
  9988. <displayName>EMR</displayName>
  9989. <description>Event mask register (EXTI_EMR)</description>
  9990. <addressOffset>0x4</addressOffset>
  9991. <size>0x20</size>
  9992. <access>read-write</access>
  9993. <resetValue>0x00000000</resetValue>
  9994. <fields>
  9995. <field>
  9996. <name>EM0</name>
  9997. <description>Event Mask on line 0</description>
  9998. <bitOffset>0</bitOffset>
  9999. <bitWidth>1</bitWidth>
  10000. </field>
  10001. <field>
  10002. <name>EM1</name>
  10003. <description>Event Mask on line 1</description>
  10004. <bitOffset>1</bitOffset>
  10005. <bitWidth>1</bitWidth>
  10006. </field>
  10007. <field>
  10008. <name>EM2</name>
  10009. <description>Event Mask on line 2</description>
  10010. <bitOffset>2</bitOffset>
  10011. <bitWidth>1</bitWidth>
  10012. </field>
  10013. <field>
  10014. <name>EM3</name>
  10015. <description>Event Mask on line 3</description>
  10016. <bitOffset>3</bitOffset>
  10017. <bitWidth>1</bitWidth>
  10018. </field>
  10019. <field>
  10020. <name>EM4</name>
  10021. <description>Event Mask on line 4</description>
  10022. <bitOffset>4</bitOffset>
  10023. <bitWidth>1</bitWidth>
  10024. </field>
  10025. <field>
  10026. <name>EM5</name>
  10027. <description>Event Mask on line 5</description>
  10028. <bitOffset>5</bitOffset>
  10029. <bitWidth>1</bitWidth>
  10030. </field>
  10031. <field>
  10032. <name>EM6</name>
  10033. <description>Event Mask on line 6</description>
  10034. <bitOffset>6</bitOffset>
  10035. <bitWidth>1</bitWidth>
  10036. </field>
  10037. <field>
  10038. <name>EM7</name>
  10039. <description>Event Mask on line 7</description>
  10040. <bitOffset>7</bitOffset>
  10041. <bitWidth>1</bitWidth>
  10042. </field>
  10043. <field>
  10044. <name>EM8</name>
  10045. <description>Event Mask on line 8</description>
  10046. <bitOffset>8</bitOffset>
  10047. <bitWidth>1</bitWidth>
  10048. </field>
  10049. <field>
  10050. <name>EM9</name>
  10051. <description>Event Mask on line 9</description>
  10052. <bitOffset>9</bitOffset>
  10053. <bitWidth>1</bitWidth>
  10054. </field>
  10055. <field>
  10056. <name>EM10</name>
  10057. <description>Event Mask on line 10</description>
  10058. <bitOffset>10</bitOffset>
  10059. <bitWidth>1</bitWidth>
  10060. </field>
  10061. <field>
  10062. <name>EM11</name>
  10063. <description>Event Mask on line 11</description>
  10064. <bitOffset>11</bitOffset>
  10065. <bitWidth>1</bitWidth>
  10066. </field>
  10067. <field>
  10068. <name>EM12</name>
  10069. <description>Event Mask on line 12</description>
  10070. <bitOffset>12</bitOffset>
  10071. <bitWidth>1</bitWidth>
  10072. </field>
  10073. <field>
  10074. <name>EM13</name>
  10075. <description>Event Mask on line 13</description>
  10076. <bitOffset>13</bitOffset>
  10077. <bitWidth>1</bitWidth>
  10078. </field>
  10079. <field>
  10080. <name>EM14</name>
  10081. <description>Event Mask on line 14</description>
  10082. <bitOffset>14</bitOffset>
  10083. <bitWidth>1</bitWidth>
  10084. </field>
  10085. <field>
  10086. <name>EM15</name>
  10087. <description>Event Mask on line 15</description>
  10088. <bitOffset>15</bitOffset>
  10089. <bitWidth>1</bitWidth>
  10090. </field>
  10091. <field>
  10092. <name>EM16</name>
  10093. <description>Event Mask on line 16</description>
  10094. <bitOffset>16</bitOffset>
  10095. <bitWidth>1</bitWidth>
  10096. </field>
  10097. <field>
  10098. <name>EM17</name>
  10099. <description>Event Mask on line 17</description>
  10100. <bitOffset>17</bitOffset>
  10101. <bitWidth>1</bitWidth>
  10102. </field>
  10103. <field>
  10104. <name>EM18</name>
  10105. <description>Event Mask on line 18</description>
  10106. <bitOffset>18</bitOffset>
  10107. <bitWidth>1</bitWidth>
  10108. </field>
  10109. <field>
  10110. <name>EM19</name>
  10111. <description>Event Mask on line 19</description>
  10112. <bitOffset>19</bitOffset>
  10113. <bitWidth>1</bitWidth>
  10114. </field>
  10115. <field>
  10116. <name>EM20</name>
  10117. <description>Event Mask on line 20</description>
  10118. <bitOffset>20</bitOffset>
  10119. <bitWidth>1</bitWidth>
  10120. </field>
  10121. <field>
  10122. <name>EM21</name>
  10123. <description>Event Mask on line 21</description>
  10124. <bitOffset>21</bitOffset>
  10125. <bitWidth>1</bitWidth>
  10126. </field>
  10127. <field>
  10128. <name>EM22</name>
  10129. <description>Event Mask on line 22</description>
  10130. <bitOffset>22</bitOffset>
  10131. <bitWidth>1</bitWidth>
  10132. </field>
  10133. <field>
  10134. <name>EM23</name>
  10135. <description>Event Mask on line 23</description>
  10136. <bitOffset>23</bitOffset>
  10137. <bitWidth>1</bitWidth>
  10138. </field>
  10139. <field>
  10140. <name>EM24</name>
  10141. <description>Event Mask on line 24</description>
  10142. <bitOffset>24</bitOffset>
  10143. <bitWidth>1</bitWidth>
  10144. </field>
  10145. <field>
  10146. <name>EM25</name>
  10147. <description>Event Mask on line 25</description>
  10148. <bitOffset>25</bitOffset>
  10149. <bitWidth>1</bitWidth>
  10150. </field>
  10151. <field>
  10152. <name>EM26</name>
  10153. <description>Event Mask on line 26</description>
  10154. <bitOffset>26</bitOffset>
  10155. <bitWidth>1</bitWidth>
  10156. </field>
  10157. <field>
  10158. <name>EM28</name>
  10159. <description>Event Mask on line 28</description>
  10160. <bitOffset>28</bitOffset>
  10161. <bitWidth>1</bitWidth>
  10162. </field>
  10163. <field>
  10164. <name>EM29</name>
  10165. <description>Event Mask on line 29</description>
  10166. <bitOffset>29</bitOffset>
  10167. <bitWidth>1</bitWidth>
  10168. </field>
  10169. </fields>
  10170. </register>
  10171. <register>
  10172. <name>RTSR</name>
  10173. <displayName>RTSR</displayName>
  10174. <description>Rising Trigger selection register (EXTI_RTSR)</description>
  10175. <addressOffset>0x8</addressOffset>
  10176. <size>0x20</size>
  10177. <access>read-write</access>
  10178. <resetValue>0x00000000</resetValue>
  10179. <fields>
  10180. <field>
  10181. <name>RT0</name>
  10182. <description>Rising trigger event configuration of line 0</description>
  10183. <bitOffset>0</bitOffset>
  10184. <bitWidth>1</bitWidth>
  10185. </field>
  10186. <field>
  10187. <name>RT1</name>
  10188. <description>Rising trigger event configuration of line 1</description>
  10189. <bitOffset>1</bitOffset>
  10190. <bitWidth>1</bitWidth>
  10191. </field>
  10192. <field>
  10193. <name>RT2</name>
  10194. <description>Rising trigger event configuration of line 2</description>
  10195. <bitOffset>2</bitOffset>
  10196. <bitWidth>1</bitWidth>
  10197. </field>
  10198. <field>
  10199. <name>RT3</name>
  10200. <description>Rising trigger event configuration of line 3</description>
  10201. <bitOffset>3</bitOffset>
  10202. <bitWidth>1</bitWidth>
  10203. </field>
  10204. <field>
  10205. <name>RT4</name>
  10206. <description>Rising trigger event configuration of line 4</description>
  10207. <bitOffset>4</bitOffset>
  10208. <bitWidth>1</bitWidth>
  10209. </field>
  10210. <field>
  10211. <name>RT5</name>
  10212. <description>Rising trigger event configuration of line 5</description>
  10213. <bitOffset>5</bitOffset>
  10214. <bitWidth>1</bitWidth>
  10215. </field>
  10216. <field>
  10217. <name>RT6</name>
  10218. <description>Rising trigger event configuration of line 6</description>
  10219. <bitOffset>6</bitOffset>
  10220. <bitWidth>1</bitWidth>
  10221. </field>
  10222. <field>
  10223. <name>RT7</name>
  10224. <description>Rising trigger event configuration of line 7</description>
  10225. <bitOffset>7</bitOffset>
  10226. <bitWidth>1</bitWidth>
  10227. </field>
  10228. <field>
  10229. <name>RT8</name>
  10230. <description>Rising trigger event configuration of line 8</description>
  10231. <bitOffset>8</bitOffset>
  10232. <bitWidth>1</bitWidth>
  10233. </field>
  10234. <field>
  10235. <name>RT9</name>
  10236. <description>Rising trigger event configuration of line 9</description>
  10237. <bitOffset>9</bitOffset>
  10238. <bitWidth>1</bitWidth>
  10239. </field>
  10240. <field>
  10241. <name>RT10</name>
  10242. <description>Rising trigger event configuration of line 10</description>
  10243. <bitOffset>10</bitOffset>
  10244. <bitWidth>1</bitWidth>
  10245. </field>
  10246. <field>
  10247. <name>RT11</name>
  10248. <description>Rising trigger event configuration of line 11</description>
  10249. <bitOffset>11</bitOffset>
  10250. <bitWidth>1</bitWidth>
  10251. </field>
  10252. <field>
  10253. <name>RT12</name>
  10254. <description>Rising trigger event configuration of line 12</description>
  10255. <bitOffset>12</bitOffset>
  10256. <bitWidth>1</bitWidth>
  10257. </field>
  10258. <field>
  10259. <name>RT13</name>
  10260. <description>Rising trigger event configuration of line 13</description>
  10261. <bitOffset>13</bitOffset>
  10262. <bitWidth>1</bitWidth>
  10263. </field>
  10264. <field>
  10265. <name>RT14</name>
  10266. <description>Rising trigger event configuration of line 14</description>
  10267. <bitOffset>14</bitOffset>
  10268. <bitWidth>1</bitWidth>
  10269. </field>
  10270. <field>
  10271. <name>RT15</name>
  10272. <description>Rising trigger event configuration of line 15</description>
  10273. <bitOffset>15</bitOffset>
  10274. <bitWidth>1</bitWidth>
  10275. </field>
  10276. <field>
  10277. <name>RT16</name>
  10278. <description>Rising trigger event configuration of line 16</description>
  10279. <bitOffset>16</bitOffset>
  10280. <bitWidth>1</bitWidth>
  10281. </field>
  10282. <field>
  10283. <name>RT17</name>
  10284. <description>Rising trigger event configuration of line 17</description>
  10285. <bitOffset>17</bitOffset>
  10286. <bitWidth>1</bitWidth>
  10287. </field>
  10288. <field>
  10289. <name>RT19</name>
  10290. <description>Rising trigger event configuration of line 19</description>
  10291. <bitOffset>19</bitOffset>
  10292. <bitWidth>1</bitWidth>
  10293. </field>
  10294. <field>
  10295. <name>RT20</name>
  10296. <description>Rising trigger event configuration of line 20</description>
  10297. <bitOffset>20</bitOffset>
  10298. <bitWidth>1</bitWidth>
  10299. </field>
  10300. <field>
  10301. <name>RT21</name>
  10302. <description>Rising trigger event configuration of line 21</description>
  10303. <bitOffset>21</bitOffset>
  10304. <bitWidth>1</bitWidth>
  10305. </field>
  10306. <field>
  10307. <name>RT22</name>
  10308. <description>Rising trigger event configuration of line 22</description>
  10309. <bitOffset>22</bitOffset>
  10310. <bitWidth>1</bitWidth>
  10311. </field>
  10312. </fields>
  10313. </register>
  10314. <register>
  10315. <name>FTSR</name>
  10316. <displayName>FTSR</displayName>
  10317. <description>Falling Trigger selection register (EXTI_FTSR)</description>
  10318. <addressOffset>0xC</addressOffset>
  10319. <size>0x20</size>
  10320. <access>read-write</access>
  10321. <resetValue>0x00000000</resetValue>
  10322. <fields>
  10323. <field>
  10324. <name>FT0</name>
  10325. <description>Falling trigger event configuration of line 0</description>
  10326. <bitOffset>0</bitOffset>
  10327. <bitWidth>1</bitWidth>
  10328. </field>
  10329. <field>
  10330. <name>FT1</name>
  10331. <description>Falling trigger event configuration of line 1</description>
  10332. <bitOffset>1</bitOffset>
  10333. <bitWidth>1</bitWidth>
  10334. </field>
  10335. <field>
  10336. <name>FT2</name>
  10337. <description>Falling trigger event configuration of line 2</description>
  10338. <bitOffset>2</bitOffset>
  10339. <bitWidth>1</bitWidth>
  10340. </field>
  10341. <field>
  10342. <name>FT3</name>
  10343. <description>Falling trigger event configuration of line 3</description>
  10344. <bitOffset>3</bitOffset>
  10345. <bitWidth>1</bitWidth>
  10346. </field>
  10347. <field>
  10348. <name>FT4</name>
  10349. <description>Falling trigger event configuration of line 4</description>
  10350. <bitOffset>4</bitOffset>
  10351. <bitWidth>1</bitWidth>
  10352. </field>
  10353. <field>
  10354. <name>FT5</name>
  10355. <description>Falling trigger event configuration of line 5</description>
  10356. <bitOffset>5</bitOffset>
  10357. <bitWidth>1</bitWidth>
  10358. </field>
  10359. <field>
  10360. <name>FT6</name>
  10361. <description>Falling trigger event configuration of line 6</description>
  10362. <bitOffset>6</bitOffset>
  10363. <bitWidth>1</bitWidth>
  10364. </field>
  10365. <field>
  10366. <name>FT7</name>
  10367. <description>Falling trigger event configuration of line 7</description>
  10368. <bitOffset>7</bitOffset>
  10369. <bitWidth>1</bitWidth>
  10370. </field>
  10371. <field>
  10372. <name>FT8</name>
  10373. <description>Falling trigger event configuration of line 8</description>
  10374. <bitOffset>8</bitOffset>
  10375. <bitWidth>1</bitWidth>
  10376. </field>
  10377. <field>
  10378. <name>FT9</name>
  10379. <description>Falling trigger event configuration of line 9</description>
  10380. <bitOffset>9</bitOffset>
  10381. <bitWidth>1</bitWidth>
  10382. </field>
  10383. <field>
  10384. <name>FT10</name>
  10385. <description>Falling trigger event configuration of line 10</description>
  10386. <bitOffset>10</bitOffset>
  10387. <bitWidth>1</bitWidth>
  10388. </field>
  10389. <field>
  10390. <name>FT11</name>
  10391. <description>Falling trigger event configuration of line 11</description>
  10392. <bitOffset>11</bitOffset>
  10393. <bitWidth>1</bitWidth>
  10394. </field>
  10395. <field>
  10396. <name>FT12</name>
  10397. <description>Falling trigger event configuration of line 12</description>
  10398. <bitOffset>12</bitOffset>
  10399. <bitWidth>1</bitWidth>
  10400. </field>
  10401. <field>
  10402. <name>FT13</name>
  10403. <description>Falling trigger event configuration of line 13</description>
  10404. <bitOffset>13</bitOffset>
  10405. <bitWidth>1</bitWidth>
  10406. </field>
  10407. <field>
  10408. <name>FT14</name>
  10409. <description>Falling trigger event configuration of line 14</description>
  10410. <bitOffset>14</bitOffset>
  10411. <bitWidth>1</bitWidth>
  10412. </field>
  10413. <field>
  10414. <name>FT15</name>
  10415. <description>Falling trigger event configuration of line 15</description>
  10416. <bitOffset>15</bitOffset>
  10417. <bitWidth>1</bitWidth>
  10418. </field>
  10419. <field>
  10420. <name>FT16</name>
  10421. <description>Falling trigger event configuration of line 16</description>
  10422. <bitOffset>16</bitOffset>
  10423. <bitWidth>1</bitWidth>
  10424. </field>
  10425. <field>
  10426. <name>FT17</name>
  10427. <description>Falling trigger event configuration of line 17</description>
  10428. <bitOffset>17</bitOffset>
  10429. <bitWidth>1</bitWidth>
  10430. </field>
  10431. <field>
  10432. <name>FT19</name>
  10433. <description>Falling trigger event configuration of line 19</description>
  10434. <bitOffset>19</bitOffset>
  10435. <bitWidth>1</bitWidth>
  10436. </field>
  10437. <field>
  10438. <name>FT20</name>
  10439. <description>Falling trigger event configuration of line 20</description>
  10440. <bitOffset>20</bitOffset>
  10441. <bitWidth>1</bitWidth>
  10442. </field>
  10443. <field>
  10444. <name>FT21</name>
  10445. <description>Falling trigger event configuration of line 21</description>
  10446. <bitOffset>21</bitOffset>
  10447. <bitWidth>1</bitWidth>
  10448. </field>
  10449. <field>
  10450. <name>FT22</name>
  10451. <description>Falling trigger event configuration of line 22</description>
  10452. <bitOffset>22</bitOffset>
  10453. <bitWidth>1</bitWidth>
  10454. </field>
  10455. </fields>
  10456. </register>
  10457. <register>
  10458. <name>SWIER</name>
  10459. <displayName>SWIER</displayName>
  10460. <description>Software interrupt event register (EXTI_SWIER)</description>
  10461. <addressOffset>0x10</addressOffset>
  10462. <size>0x20</size>
  10463. <access>read-write</access>
  10464. <resetValue>0x00000000</resetValue>
  10465. <fields>
  10466. <field>
  10467. <name>SWI0</name>
  10468. <description>Software Interrupt on line 0</description>
  10469. <bitOffset>0</bitOffset>
  10470. <bitWidth>1</bitWidth>
  10471. </field>
  10472. <field>
  10473. <name>SWI1</name>
  10474. <description>Software Interrupt on line 1</description>
  10475. <bitOffset>1</bitOffset>
  10476. <bitWidth>1</bitWidth>
  10477. </field>
  10478. <field>
  10479. <name>SWI2</name>
  10480. <description>Software Interrupt on line 2</description>
  10481. <bitOffset>2</bitOffset>
  10482. <bitWidth>1</bitWidth>
  10483. </field>
  10484. <field>
  10485. <name>SWI3</name>
  10486. <description>Software Interrupt on line 3</description>
  10487. <bitOffset>3</bitOffset>
  10488. <bitWidth>1</bitWidth>
  10489. </field>
  10490. <field>
  10491. <name>SWI4</name>
  10492. <description>Software Interrupt on line 4</description>
  10493. <bitOffset>4</bitOffset>
  10494. <bitWidth>1</bitWidth>
  10495. </field>
  10496. <field>
  10497. <name>SWI5</name>
  10498. <description>Software Interrupt on line 5</description>
  10499. <bitOffset>5</bitOffset>
  10500. <bitWidth>1</bitWidth>
  10501. </field>
  10502. <field>
  10503. <name>SWI6</name>
  10504. <description>Software Interrupt on line 6</description>
  10505. <bitOffset>6</bitOffset>
  10506. <bitWidth>1</bitWidth>
  10507. </field>
  10508. <field>
  10509. <name>SWI7</name>
  10510. <description>Software Interrupt on line 7</description>
  10511. <bitOffset>7</bitOffset>
  10512. <bitWidth>1</bitWidth>
  10513. </field>
  10514. <field>
  10515. <name>SWI8</name>
  10516. <description>Software Interrupt on line 8</description>
  10517. <bitOffset>8</bitOffset>
  10518. <bitWidth>1</bitWidth>
  10519. </field>
  10520. <field>
  10521. <name>SWI9</name>
  10522. <description>Software Interrupt on line 9</description>
  10523. <bitOffset>9</bitOffset>
  10524. <bitWidth>1</bitWidth>
  10525. </field>
  10526. <field>
  10527. <name>SWI10</name>
  10528. <description>Software Interrupt on line 10</description>
  10529. <bitOffset>10</bitOffset>
  10530. <bitWidth>1</bitWidth>
  10531. </field>
  10532. <field>
  10533. <name>SWI11</name>
  10534. <description>Software Interrupt on line 11</description>
  10535. <bitOffset>11</bitOffset>
  10536. <bitWidth>1</bitWidth>
  10537. </field>
  10538. <field>
  10539. <name>SWI12</name>
  10540. <description>Software Interrupt on line 12</description>
  10541. <bitOffset>12</bitOffset>
  10542. <bitWidth>1</bitWidth>
  10543. </field>
  10544. <field>
  10545. <name>SWI13</name>
  10546. <description>Software Interrupt on line 13</description>
  10547. <bitOffset>13</bitOffset>
  10548. <bitWidth>1</bitWidth>
  10549. </field>
  10550. <field>
  10551. <name>SWI14</name>
  10552. <description>Software Interrupt on line 14</description>
  10553. <bitOffset>14</bitOffset>
  10554. <bitWidth>1</bitWidth>
  10555. </field>
  10556. <field>
  10557. <name>SWI15</name>
  10558. <description>Software Interrupt on line 15</description>
  10559. <bitOffset>15</bitOffset>
  10560. <bitWidth>1</bitWidth>
  10561. </field>
  10562. <field>
  10563. <name>SWI16</name>
  10564. <description>Software Interrupt on line 16</description>
  10565. <bitOffset>16</bitOffset>
  10566. <bitWidth>1</bitWidth>
  10567. </field>
  10568. <field>
  10569. <name>SWI17</name>
  10570. <description>Software Interrupt on line 17</description>
  10571. <bitOffset>17</bitOffset>
  10572. <bitWidth>1</bitWidth>
  10573. </field>
  10574. <field>
  10575. <name>SWI19</name>
  10576. <description>Software Interrupt on line 19</description>
  10577. <bitOffset>19</bitOffset>
  10578. <bitWidth>1</bitWidth>
  10579. </field>
  10580. <field>
  10581. <name>SWI20</name>
  10582. <description>Software Interrupt on line 20</description>
  10583. <bitOffset>20</bitOffset>
  10584. <bitWidth>1</bitWidth>
  10585. </field>
  10586. <field>
  10587. <name>SWI21</name>
  10588. <description>Software Interrupt on line 21</description>
  10589. <bitOffset>21</bitOffset>
  10590. <bitWidth>1</bitWidth>
  10591. </field>
  10592. <field>
  10593. <name>SWI22</name>
  10594. <description>Software Interrupt on line 22</description>
  10595. <bitOffset>22</bitOffset>
  10596. <bitWidth>1</bitWidth>
  10597. </field>
  10598. </fields>
  10599. </register>
  10600. <register>
  10601. <name>PR</name>
  10602. <displayName>PR</displayName>
  10603. <description>Pending register (EXTI_PR)</description>
  10604. <addressOffset>0x14</addressOffset>
  10605. <size>0x20</size>
  10606. <access>read-write</access>
  10607. <resetValue>0x00000000</resetValue>
  10608. <fields>
  10609. <field>
  10610. <name>PIF0</name>
  10611. <description>Pending bit 0</description>
  10612. <bitOffset>0</bitOffset>
  10613. <bitWidth>1</bitWidth>
  10614. </field>
  10615. <field>
  10616. <name>PIF1</name>
  10617. <description>Pending bit 1</description>
  10618. <bitOffset>1</bitOffset>
  10619. <bitWidth>1</bitWidth>
  10620. </field>
  10621. <field>
  10622. <name>PIF2</name>
  10623. <description>Pending bit 2</description>
  10624. <bitOffset>2</bitOffset>
  10625. <bitWidth>1</bitWidth>
  10626. </field>
  10627. <field>
  10628. <name>PIF3</name>
  10629. <description>Pending bit 3</description>
  10630. <bitOffset>3</bitOffset>
  10631. <bitWidth>1</bitWidth>
  10632. </field>
  10633. <field>
  10634. <name>PIF4</name>
  10635. <description>Pending bit 4</description>
  10636. <bitOffset>4</bitOffset>
  10637. <bitWidth>1</bitWidth>
  10638. </field>
  10639. <field>
  10640. <name>PIF5</name>
  10641. <description>Pending bit 5</description>
  10642. <bitOffset>5</bitOffset>
  10643. <bitWidth>1</bitWidth>
  10644. </field>
  10645. <field>
  10646. <name>PIF6</name>
  10647. <description>Pending bit 6</description>
  10648. <bitOffset>6</bitOffset>
  10649. <bitWidth>1</bitWidth>
  10650. </field>
  10651. <field>
  10652. <name>PIF7</name>
  10653. <description>Pending bit 7</description>
  10654. <bitOffset>7</bitOffset>
  10655. <bitWidth>1</bitWidth>
  10656. </field>
  10657. <field>
  10658. <name>PIF8</name>
  10659. <description>Pending bit 8</description>
  10660. <bitOffset>8</bitOffset>
  10661. <bitWidth>1</bitWidth>
  10662. </field>
  10663. <field>
  10664. <name>PIF9</name>
  10665. <description>Pending bit 9</description>
  10666. <bitOffset>9</bitOffset>
  10667. <bitWidth>1</bitWidth>
  10668. </field>
  10669. <field>
  10670. <name>PIF10</name>
  10671. <description>Pending bit 10</description>
  10672. <bitOffset>10</bitOffset>
  10673. <bitWidth>1</bitWidth>
  10674. </field>
  10675. <field>
  10676. <name>PIF11</name>
  10677. <description>Pending bit 11</description>
  10678. <bitOffset>11</bitOffset>
  10679. <bitWidth>1</bitWidth>
  10680. </field>
  10681. <field>
  10682. <name>PIF12</name>
  10683. <description>Pending bit 12</description>
  10684. <bitOffset>12</bitOffset>
  10685. <bitWidth>1</bitWidth>
  10686. </field>
  10687. <field>
  10688. <name>PIF13</name>
  10689. <description>Pending bit 13</description>
  10690. <bitOffset>13</bitOffset>
  10691. <bitWidth>1</bitWidth>
  10692. </field>
  10693. <field>
  10694. <name>PIF14</name>
  10695. <description>Pending bit 14</description>
  10696. <bitOffset>14</bitOffset>
  10697. <bitWidth>1</bitWidth>
  10698. </field>
  10699. <field>
  10700. <name>PIF15</name>
  10701. <description>Pending bit 15</description>
  10702. <bitOffset>15</bitOffset>
  10703. <bitWidth>1</bitWidth>
  10704. </field>
  10705. <field>
  10706. <name>PIF16</name>
  10707. <description>Pending bit 16</description>
  10708. <bitOffset>16</bitOffset>
  10709. <bitWidth>1</bitWidth>
  10710. </field>
  10711. <field>
  10712. <name>PIF17</name>
  10713. <description>Pending bit 17</description>
  10714. <bitOffset>17</bitOffset>
  10715. <bitWidth>1</bitWidth>
  10716. </field>
  10717. <field>
  10718. <name>PIF19</name>
  10719. <description>Pending bit 19</description>
  10720. <bitOffset>19</bitOffset>
  10721. <bitWidth>1</bitWidth>
  10722. </field>
  10723. <field>
  10724. <name>PIF20</name>
  10725. <description>Pending bit 20</description>
  10726. <bitOffset>20</bitOffset>
  10727. <bitWidth>1</bitWidth>
  10728. </field>
  10729. <field>
  10730. <name>PIF21</name>
  10731. <description>Pending bit 21</description>
  10732. <bitOffset>21</bitOffset>
  10733. <bitWidth>1</bitWidth>
  10734. </field>
  10735. <field>
  10736. <name>PIF22</name>
  10737. <description>Pending bit 22</description>
  10738. <bitOffset>22</bitOffset>
  10739. <bitWidth>1</bitWidth>
  10740. </field>
  10741. </fields>
  10742. </register>
  10743. </registers>
  10744. </peripheral>
  10745. <peripheral>
  10746. <name>ADC</name>
  10747. <description>Analog-to-digital converter</description>
  10748. <groupName>ADC</groupName>
  10749. <baseAddress>0x40012400</baseAddress>
  10750. <addressBlock>
  10751. <offset>0x0</offset>
  10752. <size>0x400</size>
  10753. <usage>registers</usage>
  10754. </addressBlock>
  10755. <interrupt>
  10756. <name>EXTI0_1</name>
  10757. <description>EXTI Line[1:0] interrupts</description>
  10758. <value>5</value>
  10759. </interrupt>
  10760. <interrupt>
  10761. <name>EXTI2_3</name>
  10762. <description>EXTI Line[3:2] interrupts</description>
  10763. <value>6</value>
  10764. </interrupt>
  10765. <interrupt>
  10766. <name>EXTI4_15</name>
  10767. <description>EXTI Line15 and EXTI4 interrupts</description>
  10768. <value>7</value>
  10769. </interrupt>
  10770. <registers>
  10771. <register>
  10772. <name>ISR</name>
  10773. <displayName>ISR</displayName>
  10774. <description>interrupt and status register</description>
  10775. <addressOffset>0x0</addressOffset>
  10776. <size>0x20</size>
  10777. <access>read-write</access>
  10778. <resetValue>0x00000000</resetValue>
  10779. <fields>
  10780. <field>
  10781. <name>ADRDY</name>
  10782. <description>ADC ready</description>
  10783. <bitOffset>0</bitOffset>
  10784. <bitWidth>1</bitWidth>
  10785. </field>
  10786. <field>
  10787. <name>EOSMP</name>
  10788. <description>End of sampling flag</description>
  10789. <bitOffset>1</bitOffset>
  10790. <bitWidth>1</bitWidth>
  10791. </field>
  10792. <field>
  10793. <name>EOC</name>
  10794. <description>End of conversion flag</description>
  10795. <bitOffset>2</bitOffset>
  10796. <bitWidth>1</bitWidth>
  10797. </field>
  10798. <field>
  10799. <name>EOS</name>
  10800. <description>End of sequence flag</description>
  10801. <bitOffset>3</bitOffset>
  10802. <bitWidth>1</bitWidth>
  10803. </field>
  10804. <field>
  10805. <name>OVR</name>
  10806. <description>ADC overrun</description>
  10807. <bitOffset>4</bitOffset>
  10808. <bitWidth>1</bitWidth>
  10809. </field>
  10810. <field>
  10811. <name>AWD</name>
  10812. <description>Analog watchdog flag</description>
  10813. <bitOffset>7</bitOffset>
  10814. <bitWidth>1</bitWidth>
  10815. </field>
  10816. <field>
  10817. <name>EOCAL</name>
  10818. <description>End Of Calibration flag</description>
  10819. <bitOffset>11</bitOffset>
  10820. <bitWidth>1</bitWidth>
  10821. </field>
  10822. </fields>
  10823. </register>
  10824. <register>
  10825. <name>IER</name>
  10826. <displayName>IER</displayName>
  10827. <description>interrupt enable register</description>
  10828. <addressOffset>0x4</addressOffset>
  10829. <size>0x20</size>
  10830. <access>read-write</access>
  10831. <resetValue>0x00000000</resetValue>
  10832. <fields>
  10833. <field>
  10834. <name>ADRDYIE</name>
  10835. <description>ADC ready interrupt enable</description>
  10836. <bitOffset>0</bitOffset>
  10837. <bitWidth>1</bitWidth>
  10838. </field>
  10839. <field>
  10840. <name>EOSMPIE</name>
  10841. <description>End of sampling flag interrupt enable</description>
  10842. <bitOffset>1</bitOffset>
  10843. <bitWidth>1</bitWidth>
  10844. </field>
  10845. <field>
  10846. <name>EOCIE</name>
  10847. <description>End of conversion interrupt enable</description>
  10848. <bitOffset>2</bitOffset>
  10849. <bitWidth>1</bitWidth>
  10850. </field>
  10851. <field>
  10852. <name>EOSIE</name>
  10853. <description>End of conversion sequence interrupt enable</description>
  10854. <bitOffset>3</bitOffset>
  10855. <bitWidth>1</bitWidth>
  10856. </field>
  10857. <field>
  10858. <name>OVRIE</name>
  10859. <description>Overrun interrupt enable</description>
  10860. <bitOffset>4</bitOffset>
  10861. <bitWidth>1</bitWidth>
  10862. </field>
  10863. <field>
  10864. <name>AWDIE</name>
  10865. <description>Analog watchdog interrupt enable</description>
  10866. <bitOffset>7</bitOffset>
  10867. <bitWidth>1</bitWidth>
  10868. </field>
  10869. <field>
  10870. <name>EOCALIE</name>
  10871. <description>End of calibration interrupt enable</description>
  10872. <bitOffset>11</bitOffset>
  10873. <bitWidth>1</bitWidth>
  10874. </field>
  10875. </fields>
  10876. </register>
  10877. <register>
  10878. <name>CR</name>
  10879. <displayName>CR</displayName>
  10880. <description>control register</description>
  10881. <addressOffset>0x8</addressOffset>
  10882. <size>0x20</size>
  10883. <access>read-write</access>
  10884. <resetValue>0x00000000</resetValue>
  10885. <fields>
  10886. <field>
  10887. <name>ADEN</name>
  10888. <description>ADC enable command</description>
  10889. <bitOffset>0</bitOffset>
  10890. <bitWidth>1</bitWidth>
  10891. </field>
  10892. <field>
  10893. <name>ADDIS</name>
  10894. <description>ADC disable command</description>
  10895. <bitOffset>1</bitOffset>
  10896. <bitWidth>1</bitWidth>
  10897. </field>
  10898. <field>
  10899. <name>ADSTART</name>
  10900. <description>ADC start conversion command</description>
  10901. <bitOffset>2</bitOffset>
  10902. <bitWidth>1</bitWidth>
  10903. </field>
  10904. <field>
  10905. <name>ADSTP</name>
  10906. <description>ADC stop conversion command</description>
  10907. <bitOffset>4</bitOffset>
  10908. <bitWidth>1</bitWidth>
  10909. </field>
  10910. <field>
  10911. <name>ADVREGEN</name>
  10912. <description>ADC Voltage Regulator Enable</description>
  10913. <bitOffset>28</bitOffset>
  10914. <bitWidth>1</bitWidth>
  10915. </field>
  10916. <field>
  10917. <name>ADCAL</name>
  10918. <description>ADC calibration</description>
  10919. <bitOffset>31</bitOffset>
  10920. <bitWidth>1</bitWidth>
  10921. </field>
  10922. </fields>
  10923. </register>
  10924. <register>
  10925. <name>CFGR1</name>
  10926. <displayName>CFGR1</displayName>
  10927. <description>configuration register 1</description>
  10928. <addressOffset>0xC</addressOffset>
  10929. <size>0x20</size>
  10930. <access>read-write</access>
  10931. <resetValue>0x00000000</resetValue>
  10932. <fields>
  10933. <field>
  10934. <name>AWDCH</name>
  10935. <description>Analog watchdog channel selection</description>
  10936. <bitOffset>26</bitOffset>
  10937. <bitWidth>5</bitWidth>
  10938. </field>
  10939. <field>
  10940. <name>AWDEN</name>
  10941. <description>Analog watchdog enable</description>
  10942. <bitOffset>23</bitOffset>
  10943. <bitWidth>1</bitWidth>
  10944. </field>
  10945. <field>
  10946. <name>AWDSGL</name>
  10947. <description>Enable the watchdog on a single channel or on all channels</description>
  10948. <bitOffset>22</bitOffset>
  10949. <bitWidth>1</bitWidth>
  10950. </field>
  10951. <field>
  10952. <name>DISCEN</name>
  10953. <description>Discontinuous mode</description>
  10954. <bitOffset>16</bitOffset>
  10955. <bitWidth>1</bitWidth>
  10956. </field>
  10957. <field>
  10958. <name>AUTOFF</name>
  10959. <description>Auto-off mode</description>
  10960. <bitOffset>15</bitOffset>
  10961. <bitWidth>1</bitWidth>
  10962. </field>
  10963. <field>
  10964. <name>AUTDLY</name>
  10965. <description>Auto-delayed conversion mode</description>
  10966. <bitOffset>14</bitOffset>
  10967. <bitWidth>1</bitWidth>
  10968. </field>
  10969. <field>
  10970. <name>CONT</name>
  10971. <description>Single / continuous conversion mode</description>
  10972. <bitOffset>13</bitOffset>
  10973. <bitWidth>1</bitWidth>
  10974. </field>
  10975. <field>
  10976. <name>OVRMOD</name>
  10977. <description>Overrun management mode</description>
  10978. <bitOffset>12</bitOffset>
  10979. <bitWidth>1</bitWidth>
  10980. </field>
  10981. <field>
  10982. <name>EXTEN</name>
  10983. <description>External trigger enable and polarity selection</description>
  10984. <bitOffset>10</bitOffset>
  10985. <bitWidth>2</bitWidth>
  10986. </field>
  10987. <field>
  10988. <name>EXTSEL</name>
  10989. <description>External trigger selection</description>
  10990. <bitOffset>6</bitOffset>
  10991. <bitWidth>3</bitWidth>
  10992. </field>
  10993. <field>
  10994. <name>ALIGN</name>
  10995. <description>Data alignment</description>
  10996. <bitOffset>5</bitOffset>
  10997. <bitWidth>1</bitWidth>
  10998. </field>
  10999. <field>
  11000. <name>RES</name>
  11001. <description>Data resolution</description>
  11002. <bitOffset>3</bitOffset>
  11003. <bitWidth>2</bitWidth>
  11004. </field>
  11005. <field>
  11006. <name>SCANDIR</name>
  11007. <description>Scan sequence direction</description>
  11008. <bitOffset>2</bitOffset>
  11009. <bitWidth>1</bitWidth>
  11010. </field>
  11011. <field>
  11012. <name>DMACFG</name>
  11013. <description>Direct memery access configuration</description>
  11014. <bitOffset>1</bitOffset>
  11015. <bitWidth>1</bitWidth>
  11016. </field>
  11017. <field>
  11018. <name>DMAEN</name>
  11019. <description>Direct memory access enable</description>
  11020. <bitOffset>0</bitOffset>
  11021. <bitWidth>1</bitWidth>
  11022. </field>
  11023. </fields>
  11024. </register>
  11025. <register>
  11026. <name>CFGR2</name>
  11027. <displayName>CFGR2</displayName>
  11028. <description>configuration register 2</description>
  11029. <addressOffset>0x10</addressOffset>
  11030. <size>0x20</size>
  11031. <access>read-write</access>
  11032. <resetValue>0x00000000</resetValue>
  11033. <fields>
  11034. <field>
  11035. <name>OVSE</name>
  11036. <description>Oversampler Enable</description>
  11037. <bitOffset>0</bitOffset>
  11038. <bitWidth>1</bitWidth>
  11039. </field>
  11040. <field>
  11041. <name>OVSR</name>
  11042. <description>Oversampling ratio</description>
  11043. <bitOffset>2</bitOffset>
  11044. <bitWidth>3</bitWidth>
  11045. </field>
  11046. <field>
  11047. <name>OVSS</name>
  11048. <description>Oversampling shift</description>
  11049. <bitOffset>5</bitOffset>
  11050. <bitWidth>4</bitWidth>
  11051. </field>
  11052. <field>
  11053. <name>TOVS</name>
  11054. <description>Triggered Oversampling</description>
  11055. <bitOffset>9</bitOffset>
  11056. <bitWidth>1</bitWidth>
  11057. </field>
  11058. <field>
  11059. <name>CKMODE</name>
  11060. <description>ADC clock mode</description>
  11061. <bitOffset>30</bitOffset>
  11062. <bitWidth>2</bitWidth>
  11063. </field>
  11064. </fields>
  11065. </register>
  11066. <register>
  11067. <name>SMPR</name>
  11068. <displayName>SMPR</displayName>
  11069. <description>sampling time register</description>
  11070. <addressOffset>0x14</addressOffset>
  11071. <size>0x20</size>
  11072. <access>read-write</access>
  11073. <resetValue>0x00000000</resetValue>
  11074. <fields>
  11075. <field>
  11076. <name>SMPR</name>
  11077. <description>Sampling time selection</description>
  11078. <bitOffset>0</bitOffset>
  11079. <bitWidth>3</bitWidth>
  11080. </field>
  11081. </fields>
  11082. </register>
  11083. <register>
  11084. <name>TR</name>
  11085. <displayName>TR</displayName>
  11086. <description>watchdog threshold register</description>
  11087. <addressOffset>0x20</addressOffset>
  11088. <size>0x20</size>
  11089. <access>read-write</access>
  11090. <resetValue>0x0FFF0000</resetValue>
  11091. <fields>
  11092. <field>
  11093. <name>HT</name>
  11094. <description>Analog watchdog higher threshold</description>
  11095. <bitOffset>16</bitOffset>
  11096. <bitWidth>12</bitWidth>
  11097. </field>
  11098. <field>
  11099. <name>LT</name>
  11100. <description>Analog watchdog lower threshold</description>
  11101. <bitOffset>0</bitOffset>
  11102. <bitWidth>12</bitWidth>
  11103. </field>
  11104. </fields>
  11105. </register>
  11106. <register>
  11107. <name>CHSELR</name>
  11108. <displayName>CHSELR</displayName>
  11109. <description>channel selection register</description>
  11110. <addressOffset>0x28</addressOffset>
  11111. <size>0x20</size>
  11112. <access>read-write</access>
  11113. <resetValue>0x00000000</resetValue>
  11114. <fields>
  11115. <field>
  11116. <name>CHSEL18</name>
  11117. <description>Channel-x selection</description>
  11118. <bitOffset>18</bitOffset>
  11119. <bitWidth>1</bitWidth>
  11120. </field>
  11121. <field>
  11122. <name>CHSEL17</name>
  11123. <description>Channel-x selection</description>
  11124. <bitOffset>17</bitOffset>
  11125. <bitWidth>1</bitWidth>
  11126. </field>
  11127. <field>
  11128. <name>CHSEL16</name>
  11129. <description>Channel-x selection</description>
  11130. <bitOffset>16</bitOffset>
  11131. <bitWidth>1</bitWidth>
  11132. </field>
  11133. <field>
  11134. <name>CHSEL15</name>
  11135. <description>Channel-x selection</description>
  11136. <bitOffset>15</bitOffset>
  11137. <bitWidth>1</bitWidth>
  11138. </field>
  11139. <field>
  11140. <name>CHSEL14</name>
  11141. <description>Channel-x selection</description>
  11142. <bitOffset>14</bitOffset>
  11143. <bitWidth>1</bitWidth>
  11144. </field>
  11145. <field>
  11146. <name>CHSEL13</name>
  11147. <description>Channel-x selection</description>
  11148. <bitOffset>13</bitOffset>
  11149. <bitWidth>1</bitWidth>
  11150. </field>
  11151. <field>
  11152. <name>CHSEL12</name>
  11153. <description>Channel-x selection</description>
  11154. <bitOffset>12</bitOffset>
  11155. <bitWidth>1</bitWidth>
  11156. </field>
  11157. <field>
  11158. <name>CHSEL11</name>
  11159. <description>Channel-x selection</description>
  11160. <bitOffset>11</bitOffset>
  11161. <bitWidth>1</bitWidth>
  11162. </field>
  11163. <field>
  11164. <name>CHSEL10</name>
  11165. <description>Channel-x selection</description>
  11166. <bitOffset>10</bitOffset>
  11167. <bitWidth>1</bitWidth>
  11168. </field>
  11169. <field>
  11170. <name>CHSEL9</name>
  11171. <description>Channel-x selection</description>
  11172. <bitOffset>9</bitOffset>
  11173. <bitWidth>1</bitWidth>
  11174. </field>
  11175. <field>
  11176. <name>CHSEL8</name>
  11177. <description>Channel-x selection</description>
  11178. <bitOffset>8</bitOffset>
  11179. <bitWidth>1</bitWidth>
  11180. </field>
  11181. <field>
  11182. <name>CHSEL7</name>
  11183. <description>Channel-x selection</description>
  11184. <bitOffset>7</bitOffset>
  11185. <bitWidth>1</bitWidth>
  11186. </field>
  11187. <field>
  11188. <name>CHSEL6</name>
  11189. <description>Channel-x selection</description>
  11190. <bitOffset>6</bitOffset>
  11191. <bitWidth>1</bitWidth>
  11192. </field>
  11193. <field>
  11194. <name>CHSEL5</name>
  11195. <description>Channel-x selection</description>
  11196. <bitOffset>5</bitOffset>
  11197. <bitWidth>1</bitWidth>
  11198. </field>
  11199. <field>
  11200. <name>CHSEL4</name>
  11201. <description>Channel-x selection</description>
  11202. <bitOffset>4</bitOffset>
  11203. <bitWidth>1</bitWidth>
  11204. </field>
  11205. <field>
  11206. <name>CHSEL3</name>
  11207. <description>Channel-x selection</description>
  11208. <bitOffset>3</bitOffset>
  11209. <bitWidth>1</bitWidth>
  11210. </field>
  11211. <field>
  11212. <name>CHSEL2</name>
  11213. <description>Channel-x selection</description>
  11214. <bitOffset>2</bitOffset>
  11215. <bitWidth>1</bitWidth>
  11216. </field>
  11217. <field>
  11218. <name>CHSEL1</name>
  11219. <description>Channel-x selection</description>
  11220. <bitOffset>1</bitOffset>
  11221. <bitWidth>1</bitWidth>
  11222. </field>
  11223. <field>
  11224. <name>CHSEL0</name>
  11225. <description>Channel-x selection</description>
  11226. <bitOffset>0</bitOffset>
  11227. <bitWidth>1</bitWidth>
  11228. </field>
  11229. </fields>
  11230. </register>
  11231. <register>
  11232. <name>DR</name>
  11233. <displayName>DR</displayName>
  11234. <description>data register</description>
  11235. <addressOffset>0x40</addressOffset>
  11236. <size>0x20</size>
  11237. <access>read-only</access>
  11238. <resetValue>0x00000000</resetValue>
  11239. <fields>
  11240. <field>
  11241. <name>DATA</name>
  11242. <description>Converted data</description>
  11243. <bitOffset>0</bitOffset>
  11244. <bitWidth>16</bitWidth>
  11245. </field>
  11246. </fields>
  11247. </register>
  11248. <register>
  11249. <name>CALFACT</name>
  11250. <displayName>CALFACT</displayName>
  11251. <description>ADC Calibration factor</description>
  11252. <addressOffset>0xB4</addressOffset>
  11253. <size>0x20</size>
  11254. <access>read-write</access>
  11255. <resetValue>0x00000000</resetValue>
  11256. <fields>
  11257. <field>
  11258. <name>CALFACT</name>
  11259. <description>Calibration factor</description>
  11260. <bitOffset>0</bitOffset>
  11261. <bitWidth>7</bitWidth>
  11262. </field>
  11263. </fields>
  11264. </register>
  11265. <register>
  11266. <name>CCR</name>
  11267. <displayName>CCR</displayName>
  11268. <description>ADC common configuration register</description>
  11269. <addressOffset>0x308</addressOffset>
  11270. <size>0x20</size>
  11271. <access>read-write</access>
  11272. <resetValue>0x00000000</resetValue>
  11273. <fields>
  11274. <field>
  11275. <name>PRESC</name>
  11276. <description>ADC prescaler</description>
  11277. <bitOffset>18</bitOffset>
  11278. <bitWidth>4</bitWidth>
  11279. </field>
  11280. <field>
  11281. <name>VREFEN</name>
  11282. <description>VREFINT enable</description>
  11283. <bitOffset>22</bitOffset>
  11284. <bitWidth>1</bitWidth>
  11285. </field>
  11286. <field>
  11287. <name>TSEN</name>
  11288. <description>Temperature sensor enable</description>
  11289. <bitOffset>23</bitOffset>
  11290. <bitWidth>1</bitWidth>
  11291. </field>
  11292. <field>
  11293. <name>VLCDEN</name>
  11294. <description>VLCD enable</description>
  11295. <bitOffset>24</bitOffset>
  11296. <bitWidth>1</bitWidth>
  11297. </field>
  11298. <field>
  11299. <name>LFMEN</name>
  11300. <description>Low Frequency Mode enable</description>
  11301. <bitOffset>25</bitOffset>
  11302. <bitWidth>1</bitWidth>
  11303. </field>
  11304. </fields>
  11305. </register>
  11306. </registers>
  11307. </peripheral>
  11308. <peripheral>
  11309. <name>DBG</name>
  11310. <description>Debug support</description>
  11311. <groupName>DBGMCU</groupName>
  11312. <baseAddress>0x40015800</baseAddress>
  11313. <addressBlock>
  11314. <offset>0x0</offset>
  11315. <size>0x400</size>
  11316. <usage>registers</usage>
  11317. </addressBlock>
  11318. <interrupt>
  11319. <name>ADC</name>
  11320. <description>ADC</description>
  11321. <value>12</value>
  11322. </interrupt>
  11323. <registers>
  11324. <register>
  11325. <name>IDCODE</name>
  11326. <displayName>IDCODE</displayName>
  11327. <description>MCU Device ID Code Register</description>
  11328. <addressOffset>0x0</addressOffset>
  11329. <size>0x20</size>
  11330. <access>read-only</access>
  11331. <resetValue>0x0</resetValue>
  11332. <fields>
  11333. <field>
  11334. <name>DEV_ID</name>
  11335. <description>Device Identifier</description>
  11336. <bitOffset>0</bitOffset>
  11337. <bitWidth>12</bitWidth>
  11338. </field>
  11339. <field>
  11340. <name>REV_ID</name>
  11341. <description>Revision Identifier</description>
  11342. <bitOffset>16</bitOffset>
  11343. <bitWidth>16</bitWidth>
  11344. </field>
  11345. </fields>
  11346. </register>
  11347. <register>
  11348. <name>CR</name>
  11349. <displayName>CR</displayName>
  11350. <description>Debug MCU Configuration Register</description>
  11351. <addressOffset>0x4</addressOffset>
  11352. <size>0x20</size>
  11353. <access>read-write</access>
  11354. <resetValue>0x0</resetValue>
  11355. <fields>
  11356. <field>
  11357. <name>DBG_STOP</name>
  11358. <description>Debug Stop Mode</description>
  11359. <bitOffset>1</bitOffset>
  11360. <bitWidth>1</bitWidth>
  11361. </field>
  11362. <field>
  11363. <name>DBG_STANDBY</name>
  11364. <description>Debug Standby Mode</description>
  11365. <bitOffset>2</bitOffset>
  11366. <bitWidth>1</bitWidth>
  11367. </field>
  11368. <field>
  11369. <name>DBG_SLEEP</name>
  11370. <description>Debug Sleep Mode</description>
  11371. <bitOffset>0</bitOffset>
  11372. <bitWidth>1</bitWidth>
  11373. </field>
  11374. </fields>
  11375. </register>
  11376. <register>
  11377. <name>APB1_FZ</name>
  11378. <displayName>APB1_FZ</displayName>
  11379. <description>APB Low Freeze Register</description>
  11380. <addressOffset>0x8</addressOffset>
  11381. <size>0x20</size>
  11382. <access>read-write</access>
  11383. <resetValue>0x0</resetValue>
  11384. <fields>
  11385. <field>
  11386. <name>DBG_TIMER2_STOP</name>
  11387. <description>Debug Timer 2 stopped when Core is halted</description>
  11388. <bitOffset>0</bitOffset>
  11389. <bitWidth>1</bitWidth>
  11390. </field>
  11391. <field>
  11392. <name>DBG_TIMER6_STOP</name>
  11393. <description>Debug Timer 6 stopped when Core is halted</description>
  11394. <bitOffset>4</bitOffset>
  11395. <bitWidth>1</bitWidth>
  11396. </field>
  11397. <field>
  11398. <name>DBG_RTC_STOP</name>
  11399. <description>Debug RTC stopped when Core is halted</description>
  11400. <bitOffset>10</bitOffset>
  11401. <bitWidth>1</bitWidth>
  11402. </field>
  11403. <field>
  11404. <name>DBG_WWDG_STOP</name>
  11405. <description>Debug Window Wachdog stopped when Core is halted</description>
  11406. <bitOffset>11</bitOffset>
  11407. <bitWidth>1</bitWidth>
  11408. </field>
  11409. <field>
  11410. <name>DBG_IWDG_STOP</name>
  11411. <description>Debug Independent Wachdog stopped when Core is halted</description>
  11412. <bitOffset>12</bitOffset>
  11413. <bitWidth>1</bitWidth>
  11414. </field>
  11415. <field>
  11416. <name>DBG_I2C1_STOP</name>
  11417. <description>I2C1 SMBUS timeout mode stopped when core is halted</description>
  11418. <bitOffset>21</bitOffset>
  11419. <bitWidth>1</bitWidth>
  11420. </field>
  11421. <field>
  11422. <name>DBG_I2C2_STOP</name>
  11423. <description>I2C2 SMBUS timeout mode stopped when core is halted</description>
  11424. <bitOffset>22</bitOffset>
  11425. <bitWidth>1</bitWidth>
  11426. </field>
  11427. <field>
  11428. <name>DBG_LPTIMER_STOP</name>
  11429. <description>LPTIM1 counter stopped when core is halted</description>
  11430. <bitOffset>31</bitOffset>
  11431. <bitWidth>1</bitWidth>
  11432. </field>
  11433. </fields>
  11434. </register>
  11435. <register>
  11436. <name>APB2_FZ</name>
  11437. <displayName>APB2_FZ</displayName>
  11438. <description>APB High Freeze Register</description>
  11439. <addressOffset>0xC</addressOffset>
  11440. <size>0x20</size>
  11441. <access>read-write</access>
  11442. <resetValue>0x0</resetValue>
  11443. <fields>
  11444. <field>
  11445. <name>DBG_TIMER21_STOP</name>
  11446. <description>Debug Timer 21 stopped when Core is halted</description>
  11447. <bitOffset>2</bitOffset>
  11448. <bitWidth>1</bitWidth>
  11449. </field>
  11450. <field>
  11451. <name>DBG_TIMER22_STO</name>
  11452. <description>Debug Timer 22 stopped when Core is halted</description>
  11453. <bitOffset>6</bitOffset>
  11454. <bitWidth>1</bitWidth>
  11455. </field>
  11456. </fields>
  11457. </register>
  11458. </registers>
  11459. </peripheral>
  11460. <peripheral>
  11461. <name>TIM2</name>
  11462. <description>General-purpose-timers</description>
  11463. <groupName>TIM</groupName>
  11464. <baseAddress>0x40000000</baseAddress>
  11465. <addressBlock>
  11466. <offset>0x0</offset>
  11467. <size>0x400</size>
  11468. <usage>registers</usage>
  11469. </addressBlock>
  11470. <registers>
  11471. <register>
  11472. <name>CR1</name>
  11473. <displayName>CR1</displayName>
  11474. <description>control register 1</description>
  11475. <addressOffset>0x0</addressOffset>
  11476. <size>0x20</size>
  11477. <access>read-write</access>
  11478. <resetValue>0x0000</resetValue>
  11479. <fields>
  11480. <field>
  11481. <name>CKD</name>
  11482. <description>Clock division</description>
  11483. <bitOffset>8</bitOffset>
  11484. <bitWidth>2</bitWidth>
  11485. </field>
  11486. <field>
  11487. <name>ARPE</name>
  11488. <description>Auto-reload preload enable</description>
  11489. <bitOffset>7</bitOffset>
  11490. <bitWidth>1</bitWidth>
  11491. </field>
  11492. <field>
  11493. <name>CMS</name>
  11494. <description>Center-aligned mode selection</description>
  11495. <bitOffset>5</bitOffset>
  11496. <bitWidth>2</bitWidth>
  11497. </field>
  11498. <field>
  11499. <name>DIR</name>
  11500. <description>Direction</description>
  11501. <bitOffset>4</bitOffset>
  11502. <bitWidth>1</bitWidth>
  11503. </field>
  11504. <field>
  11505. <name>OPM</name>
  11506. <description>One-pulse mode</description>
  11507. <bitOffset>3</bitOffset>
  11508. <bitWidth>1</bitWidth>
  11509. </field>
  11510. <field>
  11511. <name>URS</name>
  11512. <description>Update request source</description>
  11513. <bitOffset>2</bitOffset>
  11514. <bitWidth>1</bitWidth>
  11515. </field>
  11516. <field>
  11517. <name>UDIS</name>
  11518. <description>Update disable</description>
  11519. <bitOffset>1</bitOffset>
  11520. <bitWidth>1</bitWidth>
  11521. </field>
  11522. <field>
  11523. <name>CEN</name>
  11524. <description>Counter enable</description>
  11525. <bitOffset>0</bitOffset>
  11526. <bitWidth>1</bitWidth>
  11527. </field>
  11528. </fields>
  11529. </register>
  11530. <register>
  11531. <name>CR2</name>
  11532. <displayName>CR2</displayName>
  11533. <description>control register 2</description>
  11534. <addressOffset>0x4</addressOffset>
  11535. <size>0x20</size>
  11536. <access>read-write</access>
  11537. <resetValue>0x0000</resetValue>
  11538. <fields>
  11539. <field>
  11540. <name>TI1S</name>
  11541. <description>TI1 selection</description>
  11542. <bitOffset>7</bitOffset>
  11543. <bitWidth>1</bitWidth>
  11544. </field>
  11545. <field>
  11546. <name>MMS</name>
  11547. <description>Master mode selection</description>
  11548. <bitOffset>4</bitOffset>
  11549. <bitWidth>3</bitWidth>
  11550. </field>
  11551. <field>
  11552. <name>CCDS</name>
  11553. <description>Capture/compare DMA selection</description>
  11554. <bitOffset>3</bitOffset>
  11555. <bitWidth>1</bitWidth>
  11556. </field>
  11557. </fields>
  11558. </register>
  11559. <register>
  11560. <name>SMCR</name>
  11561. <displayName>SMCR</displayName>
  11562. <description>slave mode control register</description>
  11563. <addressOffset>0x8</addressOffset>
  11564. <size>0x20</size>
  11565. <access>read-write</access>
  11566. <resetValue>0x0000</resetValue>
  11567. <fields>
  11568. <field>
  11569. <name>ETP</name>
  11570. <description>External trigger polarity</description>
  11571. <bitOffset>15</bitOffset>
  11572. <bitWidth>1</bitWidth>
  11573. </field>
  11574. <field>
  11575. <name>ECE</name>
  11576. <description>External clock enable</description>
  11577. <bitOffset>14</bitOffset>
  11578. <bitWidth>1</bitWidth>
  11579. </field>
  11580. <field>
  11581. <name>ETPS</name>
  11582. <description>External trigger prescaler</description>
  11583. <bitOffset>12</bitOffset>
  11584. <bitWidth>2</bitWidth>
  11585. </field>
  11586. <field>
  11587. <name>ETF</name>
  11588. <description>External trigger filter</description>
  11589. <bitOffset>8</bitOffset>
  11590. <bitWidth>4</bitWidth>
  11591. </field>
  11592. <field>
  11593. <name>MSM</name>
  11594. <description>Master/Slave mode</description>
  11595. <bitOffset>7</bitOffset>
  11596. <bitWidth>1</bitWidth>
  11597. </field>
  11598. <field>
  11599. <name>TS</name>
  11600. <description>Trigger selection</description>
  11601. <bitOffset>4</bitOffset>
  11602. <bitWidth>3</bitWidth>
  11603. </field>
  11604. <field>
  11605. <name>SMS</name>
  11606. <description>Slave mode selection</description>
  11607. <bitOffset>0</bitOffset>
  11608. <bitWidth>3</bitWidth>
  11609. </field>
  11610. </fields>
  11611. </register>
  11612. <register>
  11613. <name>DIER</name>
  11614. <displayName>DIER</displayName>
  11615. <description>DMA/Interrupt enable register</description>
  11616. <addressOffset>0xC</addressOffset>
  11617. <size>0x20</size>
  11618. <access>read-write</access>
  11619. <resetValue>0x0000</resetValue>
  11620. <fields>
  11621. <field>
  11622. <name>TDE</name>
  11623. <description>Trigger DMA request enable</description>
  11624. <bitOffset>14</bitOffset>
  11625. <bitWidth>1</bitWidth>
  11626. </field>
  11627. <field>
  11628. <name>CC4DE</name>
  11629. <description>Capture/Compare 4 DMA request enable</description>
  11630. <bitOffset>12</bitOffset>
  11631. <bitWidth>1</bitWidth>
  11632. </field>
  11633. <field>
  11634. <name>CC3DE</name>
  11635. <description>Capture/Compare 3 DMA request enable</description>
  11636. <bitOffset>11</bitOffset>
  11637. <bitWidth>1</bitWidth>
  11638. </field>
  11639. <field>
  11640. <name>CC2DE</name>
  11641. <description>Capture/Compare 2 DMA request enable</description>
  11642. <bitOffset>10</bitOffset>
  11643. <bitWidth>1</bitWidth>
  11644. </field>
  11645. <field>
  11646. <name>CC1DE</name>
  11647. <description>Capture/Compare 1 DMA request enable</description>
  11648. <bitOffset>9</bitOffset>
  11649. <bitWidth>1</bitWidth>
  11650. </field>
  11651. <field>
  11652. <name>UDE</name>
  11653. <description>Update DMA request enable</description>
  11654. <bitOffset>8</bitOffset>
  11655. <bitWidth>1</bitWidth>
  11656. </field>
  11657. <field>
  11658. <name>TIE</name>
  11659. <description>Trigger interrupt enable</description>
  11660. <bitOffset>6</bitOffset>
  11661. <bitWidth>1</bitWidth>
  11662. </field>
  11663. <field>
  11664. <name>CC4IE</name>
  11665. <description>Capture/Compare 4 interrupt enable</description>
  11666. <bitOffset>4</bitOffset>
  11667. <bitWidth>1</bitWidth>
  11668. </field>
  11669. <field>
  11670. <name>CC3IE</name>
  11671. <description>Capture/Compare 3 interrupt enable</description>
  11672. <bitOffset>3</bitOffset>
  11673. <bitWidth>1</bitWidth>
  11674. </field>
  11675. <field>
  11676. <name>CC2IE</name>
  11677. <description>Capture/Compare 2 interrupt enable</description>
  11678. <bitOffset>2</bitOffset>
  11679. <bitWidth>1</bitWidth>
  11680. </field>
  11681. <field>
  11682. <name>CC1IE</name>
  11683. <description>Capture/Compare 1 interrupt enable</description>
  11684. <bitOffset>1</bitOffset>
  11685. <bitWidth>1</bitWidth>
  11686. </field>
  11687. <field>
  11688. <name>UIE</name>
  11689. <description>Update interrupt enable</description>
  11690. <bitOffset>0</bitOffset>
  11691. <bitWidth>1</bitWidth>
  11692. </field>
  11693. </fields>
  11694. </register>
  11695. <register>
  11696. <name>SR</name>
  11697. <displayName>SR</displayName>
  11698. <description>status register</description>
  11699. <addressOffset>0x10</addressOffset>
  11700. <size>0x20</size>
  11701. <access>read-write</access>
  11702. <resetValue>0x0000</resetValue>
  11703. <fields>
  11704. <field>
  11705. <name>CC4OF</name>
  11706. <description>Capture/Compare 4 overcapture flag</description>
  11707. <bitOffset>12</bitOffset>
  11708. <bitWidth>1</bitWidth>
  11709. </field>
  11710. <field>
  11711. <name>CC3OF</name>
  11712. <description>Capture/Compare 3 overcapture flag</description>
  11713. <bitOffset>11</bitOffset>
  11714. <bitWidth>1</bitWidth>
  11715. </field>
  11716. <field>
  11717. <name>CC2OF</name>
  11718. <description>Capture/compare 2 overcapture flag</description>
  11719. <bitOffset>10</bitOffset>
  11720. <bitWidth>1</bitWidth>
  11721. </field>
  11722. <field>
  11723. <name>CC1OF</name>
  11724. <description>Capture/Compare 1 overcapture flag</description>
  11725. <bitOffset>9</bitOffset>
  11726. <bitWidth>1</bitWidth>
  11727. </field>
  11728. <field>
  11729. <name>TIF</name>
  11730. <description>Trigger interrupt flag</description>
  11731. <bitOffset>6</bitOffset>
  11732. <bitWidth>1</bitWidth>
  11733. </field>
  11734. <field>
  11735. <name>CC4IF</name>
  11736. <description>Capture/Compare 4 interrupt flag</description>
  11737. <bitOffset>4</bitOffset>
  11738. <bitWidth>1</bitWidth>
  11739. </field>
  11740. <field>
  11741. <name>CC3IF</name>
  11742. <description>Capture/Compare 3 interrupt flag</description>
  11743. <bitOffset>3</bitOffset>
  11744. <bitWidth>1</bitWidth>
  11745. </field>
  11746. <field>
  11747. <name>CC2IF</name>
  11748. <description>Capture/Compare 2 interrupt flag</description>
  11749. <bitOffset>2</bitOffset>
  11750. <bitWidth>1</bitWidth>
  11751. </field>
  11752. <field>
  11753. <name>CC1IF</name>
  11754. <description>Capture/compare 1 interrupt flag</description>
  11755. <bitOffset>1</bitOffset>
  11756. <bitWidth>1</bitWidth>
  11757. </field>
  11758. <field>
  11759. <name>UIF</name>
  11760. <description>Update interrupt flag</description>
  11761. <bitOffset>0</bitOffset>
  11762. <bitWidth>1</bitWidth>
  11763. </field>
  11764. </fields>
  11765. </register>
  11766. <register>
  11767. <name>EGR</name>
  11768. <displayName>EGR</displayName>
  11769. <description>event generation register</description>
  11770. <addressOffset>0x14</addressOffset>
  11771. <size>0x20</size>
  11772. <access>write-only</access>
  11773. <resetValue>0x0000</resetValue>
  11774. <fields>
  11775. <field>
  11776. <name>TG</name>
  11777. <description>Trigger generation</description>
  11778. <bitOffset>6</bitOffset>
  11779. <bitWidth>1</bitWidth>
  11780. </field>
  11781. <field>
  11782. <name>CC4G</name>
  11783. <description>Capture/compare 4 generation</description>
  11784. <bitOffset>4</bitOffset>
  11785. <bitWidth>1</bitWidth>
  11786. </field>
  11787. <field>
  11788. <name>CC3G</name>
  11789. <description>Capture/compare 3 generation</description>
  11790. <bitOffset>3</bitOffset>
  11791. <bitWidth>1</bitWidth>
  11792. </field>
  11793. <field>
  11794. <name>CC2G</name>
  11795. <description>Capture/compare 2 generation</description>
  11796. <bitOffset>2</bitOffset>
  11797. <bitWidth>1</bitWidth>
  11798. </field>
  11799. <field>
  11800. <name>CC1G</name>
  11801. <description>Capture/compare 1 generation</description>
  11802. <bitOffset>1</bitOffset>
  11803. <bitWidth>1</bitWidth>
  11804. </field>
  11805. <field>
  11806. <name>UG</name>
  11807. <description>Update generation</description>
  11808. <bitOffset>0</bitOffset>
  11809. <bitWidth>1</bitWidth>
  11810. </field>
  11811. </fields>
  11812. </register>
  11813. <register>
  11814. <name>CCMR1_Output</name>
  11815. <displayName>CCMR1_Output</displayName>
  11816. <description>capture/compare mode register 1 (output mode)</description>
  11817. <addressOffset>0x18</addressOffset>
  11818. <size>0x20</size>
  11819. <access>read-write</access>
  11820. <resetValue>0x00000000</resetValue>
  11821. <fields>
  11822. <field>
  11823. <name>OC2CE</name>
  11824. <description>Output compare 2 clear enable</description>
  11825. <bitOffset>15</bitOffset>
  11826. <bitWidth>1</bitWidth>
  11827. </field>
  11828. <field>
  11829. <name>OC2M</name>
  11830. <description>Output compare 2 mode</description>
  11831. <bitOffset>12</bitOffset>
  11832. <bitWidth>3</bitWidth>
  11833. </field>
  11834. <field>
  11835. <name>OC2PE</name>
  11836. <description>Output compare 2 preload enable</description>
  11837. <bitOffset>11</bitOffset>
  11838. <bitWidth>1</bitWidth>
  11839. </field>
  11840. <field>
  11841. <name>OC2FE</name>
  11842. <description>Output compare 2 fast enable</description>
  11843. <bitOffset>10</bitOffset>
  11844. <bitWidth>1</bitWidth>
  11845. </field>
  11846. <field>
  11847. <name>CC2S</name>
  11848. <description>Capture/Compare 2 selection</description>
  11849. <bitOffset>8</bitOffset>
  11850. <bitWidth>2</bitWidth>
  11851. </field>
  11852. <field>
  11853. <name>OC1CE</name>
  11854. <description>Output compare 1 clear enable</description>
  11855. <bitOffset>7</bitOffset>
  11856. <bitWidth>1</bitWidth>
  11857. </field>
  11858. <field>
  11859. <name>OC1M</name>
  11860. <description>Output compare 1 mode</description>
  11861. <bitOffset>4</bitOffset>
  11862. <bitWidth>3</bitWidth>
  11863. </field>
  11864. <field>
  11865. <name>OC1PE</name>
  11866. <description>Output compare 1 preload enable</description>
  11867. <bitOffset>3</bitOffset>
  11868. <bitWidth>1</bitWidth>
  11869. </field>
  11870. <field>
  11871. <name>OC1FE</name>
  11872. <description>Output compare 1 fast enable</description>
  11873. <bitOffset>2</bitOffset>
  11874. <bitWidth>1</bitWidth>
  11875. </field>
  11876. <field>
  11877. <name>CC1S</name>
  11878. <description>Capture/Compare 1 selection</description>
  11879. <bitOffset>0</bitOffset>
  11880. <bitWidth>2</bitWidth>
  11881. </field>
  11882. </fields>
  11883. </register>
  11884. <register>
  11885. <name>CCMR1_Input</name>
  11886. <displayName>CCMR1_Input</displayName>
  11887. <description>capture/compare mode register 1 (input mode)</description>
  11888. <alternateRegister>CCMR1_Output</alternateRegister>
  11889. <addressOffset>0x18</addressOffset>
  11890. <size>0x20</size>
  11891. <access>read-write</access>
  11892. <resetValue>0x00000000</resetValue>
  11893. <fields>
  11894. <field>
  11895. <name>IC2F</name>
  11896. <description>Input capture 2 filter</description>
  11897. <bitOffset>12</bitOffset>
  11898. <bitWidth>4</bitWidth>
  11899. </field>
  11900. <field>
  11901. <name>IC2PSC</name>
  11902. <description>Input capture 2 prescaler</description>
  11903. <bitOffset>10</bitOffset>
  11904. <bitWidth>2</bitWidth>
  11905. </field>
  11906. <field>
  11907. <name>CC2S</name>
  11908. <description>Capture/compare 2 selection</description>
  11909. <bitOffset>8</bitOffset>
  11910. <bitWidth>2</bitWidth>
  11911. </field>
  11912. <field>
  11913. <name>IC1F</name>
  11914. <description>Input capture 1 filter</description>
  11915. <bitOffset>4</bitOffset>
  11916. <bitWidth>4</bitWidth>
  11917. </field>
  11918. <field>
  11919. <name>IC1PSC</name>
  11920. <description>Input capture 1 prescaler</description>
  11921. <bitOffset>2</bitOffset>
  11922. <bitWidth>2</bitWidth>
  11923. </field>
  11924. <field>
  11925. <name>CC1S</name>
  11926. <description>Capture/Compare 1 selection</description>
  11927. <bitOffset>0</bitOffset>
  11928. <bitWidth>2</bitWidth>
  11929. </field>
  11930. </fields>
  11931. </register>
  11932. <register>
  11933. <name>CCMR2_Output</name>
  11934. <displayName>CCMR2_Output</displayName>
  11935. <description>capture/compare mode register 2 (output mode)</description>
  11936. <addressOffset>0x1C</addressOffset>
  11937. <size>0x20</size>
  11938. <access>read-write</access>
  11939. <resetValue>0x00000000</resetValue>
  11940. <fields>
  11941. <field>
  11942. <name>OC4CE</name>
  11943. <description>Output compare 4 clear enable</description>
  11944. <bitOffset>15</bitOffset>
  11945. <bitWidth>1</bitWidth>
  11946. </field>
  11947. <field>
  11948. <name>OC4M</name>
  11949. <description>Output compare 4 mode</description>
  11950. <bitOffset>12</bitOffset>
  11951. <bitWidth>3</bitWidth>
  11952. </field>
  11953. <field>
  11954. <name>OC4PE</name>
  11955. <description>Output compare 4 preload enable</description>
  11956. <bitOffset>11</bitOffset>
  11957. <bitWidth>1</bitWidth>
  11958. </field>
  11959. <field>
  11960. <name>OC4FE</name>
  11961. <description>Output compare 4 fast enable</description>
  11962. <bitOffset>10</bitOffset>
  11963. <bitWidth>1</bitWidth>
  11964. </field>
  11965. <field>
  11966. <name>CC4S</name>
  11967. <description>Capture/Compare 4 selection</description>
  11968. <bitOffset>8</bitOffset>
  11969. <bitWidth>2</bitWidth>
  11970. </field>
  11971. <field>
  11972. <name>OC3CE</name>
  11973. <description>Output compare 3 clear enable</description>
  11974. <bitOffset>7</bitOffset>
  11975. <bitWidth>1</bitWidth>
  11976. </field>
  11977. <field>
  11978. <name>OC3M</name>
  11979. <description>Output compare 3 mode</description>
  11980. <bitOffset>4</bitOffset>
  11981. <bitWidth>3</bitWidth>
  11982. </field>
  11983. <field>
  11984. <name>OC3PE</name>
  11985. <description>Output compare 3 preload enable</description>
  11986. <bitOffset>3</bitOffset>
  11987. <bitWidth>1</bitWidth>
  11988. </field>
  11989. <field>
  11990. <name>OC3FE</name>
  11991. <description>Output compare 3 fast enable</description>
  11992. <bitOffset>2</bitOffset>
  11993. <bitWidth>1</bitWidth>
  11994. </field>
  11995. <field>
  11996. <name>CC3S</name>
  11997. <description>Capture/Compare 3 selection</description>
  11998. <bitOffset>0</bitOffset>
  11999. <bitWidth>2</bitWidth>
  12000. </field>
  12001. </fields>
  12002. </register>
  12003. <register>
  12004. <name>CCMR2_Input</name>
  12005. <displayName>CCMR2_Input</displayName>
  12006. <description>capture/compare mode register 2 (input mode)</description>
  12007. <alternateRegister>CCMR2_Output</alternateRegister>
  12008. <addressOffset>0x1C</addressOffset>
  12009. <size>0x20</size>
  12010. <access>read-write</access>
  12011. <resetValue>0x00000000</resetValue>
  12012. <fields>
  12013. <field>
  12014. <name>IC4F</name>
  12015. <description>Input capture 4 filter</description>
  12016. <bitOffset>12</bitOffset>
  12017. <bitWidth>4</bitWidth>
  12018. </field>
  12019. <field>
  12020. <name>IC4PSC</name>
  12021. <description>Input capture 4 prescaler</description>
  12022. <bitOffset>10</bitOffset>
  12023. <bitWidth>2</bitWidth>
  12024. </field>
  12025. <field>
  12026. <name>CC4S</name>
  12027. <description>Capture/Compare 4 selection</description>
  12028. <bitOffset>8</bitOffset>
  12029. <bitWidth>2</bitWidth>
  12030. </field>
  12031. <field>
  12032. <name>IC3F</name>
  12033. <description>Input capture 3 filter</description>
  12034. <bitOffset>4</bitOffset>
  12035. <bitWidth>4</bitWidth>
  12036. </field>
  12037. <field>
  12038. <name>IC3PSC</name>
  12039. <description>Input capture 3 prescaler</description>
  12040. <bitOffset>2</bitOffset>
  12041. <bitWidth>2</bitWidth>
  12042. </field>
  12043. <field>
  12044. <name>CC3S</name>
  12045. <description>Capture/Compare 3 selection</description>
  12046. <bitOffset>0</bitOffset>
  12047. <bitWidth>2</bitWidth>
  12048. </field>
  12049. </fields>
  12050. </register>
  12051. <register>
  12052. <name>CCER</name>
  12053. <displayName>CCER</displayName>
  12054. <description>capture/compare enable register</description>
  12055. <addressOffset>0x20</addressOffset>
  12056. <size>0x20</size>
  12057. <access>read-write</access>
  12058. <resetValue>0x0000</resetValue>
  12059. <fields>
  12060. <field>
  12061. <name>CC4NP</name>
  12062. <description>Capture/Compare 4 output Polarity</description>
  12063. <bitOffset>15</bitOffset>
  12064. <bitWidth>1</bitWidth>
  12065. </field>
  12066. <field>
  12067. <name>CC4P</name>
  12068. <description>Capture/Compare 3 output Polarity</description>
  12069. <bitOffset>13</bitOffset>
  12070. <bitWidth>1</bitWidth>
  12071. </field>
  12072. <field>
  12073. <name>CC4E</name>
  12074. <description>Capture/Compare 4 output enable</description>
  12075. <bitOffset>12</bitOffset>
  12076. <bitWidth>1</bitWidth>
  12077. </field>
  12078. <field>
  12079. <name>CC3NP</name>
  12080. <description>Capture/Compare 3 output Polarity</description>
  12081. <bitOffset>11</bitOffset>
  12082. <bitWidth>1</bitWidth>
  12083. </field>
  12084. <field>
  12085. <name>CC3P</name>
  12086. <description>Capture/Compare 3 output Polarity</description>
  12087. <bitOffset>9</bitOffset>
  12088. <bitWidth>1</bitWidth>
  12089. </field>
  12090. <field>
  12091. <name>CC3E</name>
  12092. <description>Capture/Compare 3 output enable</description>
  12093. <bitOffset>8</bitOffset>
  12094. <bitWidth>1</bitWidth>
  12095. </field>
  12096. <field>
  12097. <name>CC2NP</name>
  12098. <description>Capture/Compare 2 output Polarity</description>
  12099. <bitOffset>7</bitOffset>
  12100. <bitWidth>1</bitWidth>
  12101. </field>
  12102. <field>
  12103. <name>CC2P</name>
  12104. <description>Capture/Compare 2 output Polarity</description>
  12105. <bitOffset>5</bitOffset>
  12106. <bitWidth>1</bitWidth>
  12107. </field>
  12108. <field>
  12109. <name>CC2E</name>
  12110. <description>Capture/Compare 2 output enable</description>
  12111. <bitOffset>4</bitOffset>
  12112. <bitWidth>1</bitWidth>
  12113. </field>
  12114. <field>
  12115. <name>CC1NP</name>
  12116. <description>Capture/Compare 1 output Polarity</description>
  12117. <bitOffset>3</bitOffset>
  12118. <bitWidth>1</bitWidth>
  12119. </field>
  12120. <field>
  12121. <name>CC1P</name>
  12122. <description>Capture/Compare 1 output Polarity</description>
  12123. <bitOffset>1</bitOffset>
  12124. <bitWidth>1</bitWidth>
  12125. </field>
  12126. <field>
  12127. <name>CC1E</name>
  12128. <description>Capture/Compare 1 output enable</description>
  12129. <bitOffset>0</bitOffset>
  12130. <bitWidth>1</bitWidth>
  12131. </field>
  12132. </fields>
  12133. </register>
  12134. <register>
  12135. <name>CNT</name>
  12136. <displayName>CNT</displayName>
  12137. <description>counter</description>
  12138. <addressOffset>0x24</addressOffset>
  12139. <size>0x20</size>
  12140. <access>read-write</access>
  12141. <resetValue>0x00000000</resetValue>
  12142. <fields>
  12143. <field>
  12144. <name>CNT_H</name>
  12145. <description>High counter value (TIM2 only)</description>
  12146. <bitOffset>16</bitOffset>
  12147. <bitWidth>16</bitWidth>
  12148. </field>
  12149. <field>
  12150. <name>CNT_L</name>
  12151. <description>Low counter value</description>
  12152. <bitOffset>0</bitOffset>
  12153. <bitWidth>16</bitWidth>
  12154. </field>
  12155. </fields>
  12156. </register>
  12157. <register>
  12158. <name>PSC</name>
  12159. <displayName>PSC</displayName>
  12160. <description>prescaler</description>
  12161. <addressOffset>0x28</addressOffset>
  12162. <size>0x20</size>
  12163. <access>read-write</access>
  12164. <resetValue>0x0000</resetValue>
  12165. <fields>
  12166. <field>
  12167. <name>PSC</name>
  12168. <description>Prescaler value</description>
  12169. <bitOffset>0</bitOffset>
  12170. <bitWidth>16</bitWidth>
  12171. </field>
  12172. </fields>
  12173. </register>
  12174. <register>
  12175. <name>ARR</name>
  12176. <displayName>ARR</displayName>
  12177. <description>auto-reload register</description>
  12178. <addressOffset>0x2C</addressOffset>
  12179. <size>0x20</size>
  12180. <access>read-write</access>
  12181. <resetValue>0x00000000</resetValue>
  12182. <fields>
  12183. <field>
  12184. <name>ARR_H</name>
  12185. <description>High Auto-reload value (TIM2 only)</description>
  12186. <bitOffset>16</bitOffset>
  12187. <bitWidth>16</bitWidth>
  12188. </field>
  12189. <field>
  12190. <name>ARR_L</name>
  12191. <description>Low Auto-reload value</description>
  12192. <bitOffset>0</bitOffset>
  12193. <bitWidth>16</bitWidth>
  12194. </field>
  12195. </fields>
  12196. </register>
  12197. <register>
  12198. <name>CCR1</name>
  12199. <displayName>CCR1</displayName>
  12200. <description>capture/compare register 1</description>
  12201. <addressOffset>0x34</addressOffset>
  12202. <size>0x20</size>
  12203. <access>read-write</access>
  12204. <resetValue>0x00000000</resetValue>
  12205. <fields>
  12206. <field>
  12207. <name>CCR1_H</name>
  12208. <description>High Capture/Compare 1 value (TIM2 only)</description>
  12209. <bitOffset>16</bitOffset>
  12210. <bitWidth>16</bitWidth>
  12211. </field>
  12212. <field>
  12213. <name>CCR1_L</name>
  12214. <description>Low Capture/Compare 1 value</description>
  12215. <bitOffset>0</bitOffset>
  12216. <bitWidth>16</bitWidth>
  12217. </field>
  12218. </fields>
  12219. </register>
  12220. <register>
  12221. <name>CCR2</name>
  12222. <displayName>CCR2</displayName>
  12223. <description>capture/compare register 2</description>
  12224. <addressOffset>0x38</addressOffset>
  12225. <size>0x20</size>
  12226. <access>read-write</access>
  12227. <resetValue>0x00000000</resetValue>
  12228. <fields>
  12229. <field>
  12230. <name>CCR2_H</name>
  12231. <description>High Capture/Compare 2 value (TIM2 only)</description>
  12232. <bitOffset>16</bitOffset>
  12233. <bitWidth>16</bitWidth>
  12234. </field>
  12235. <field>
  12236. <name>CCR2_L</name>
  12237. <description>Low Capture/Compare 2 value</description>
  12238. <bitOffset>0</bitOffset>
  12239. <bitWidth>16</bitWidth>
  12240. </field>
  12241. </fields>
  12242. </register>
  12243. <register>
  12244. <name>CCR3</name>
  12245. <displayName>CCR3</displayName>
  12246. <description>capture/compare register 3</description>
  12247. <addressOffset>0x3C</addressOffset>
  12248. <size>0x20</size>
  12249. <access>read-write</access>
  12250. <resetValue>0x00000000</resetValue>
  12251. <fields>
  12252. <field>
  12253. <name>CCR3_H</name>
  12254. <description>High Capture/Compare value (TIM2 only)</description>
  12255. <bitOffset>16</bitOffset>
  12256. <bitWidth>16</bitWidth>
  12257. </field>
  12258. <field>
  12259. <name>CCR3_L</name>
  12260. <description>Low Capture/Compare value</description>
  12261. <bitOffset>0</bitOffset>
  12262. <bitWidth>16</bitWidth>
  12263. </field>
  12264. </fields>
  12265. </register>
  12266. <register>
  12267. <name>CCR4</name>
  12268. <displayName>CCR4</displayName>
  12269. <description>capture/compare register 4</description>
  12270. <addressOffset>0x40</addressOffset>
  12271. <size>0x20</size>
  12272. <access>read-write</access>
  12273. <resetValue>0x00000000</resetValue>
  12274. <fields>
  12275. <field>
  12276. <name>CCR4_H</name>
  12277. <description>High Capture/Compare value (TIM2 only)</description>
  12278. <bitOffset>16</bitOffset>
  12279. <bitWidth>16</bitWidth>
  12280. </field>
  12281. <field>
  12282. <name>CCR4_L</name>
  12283. <description>Low Capture/Compare value</description>
  12284. <bitOffset>0</bitOffset>
  12285. <bitWidth>16</bitWidth>
  12286. </field>
  12287. </fields>
  12288. </register>
  12289. <register>
  12290. <name>DCR</name>
  12291. <displayName>DCR</displayName>
  12292. <description>DMA control register</description>
  12293. <addressOffset>0x48</addressOffset>
  12294. <size>0x20</size>
  12295. <access>read-write</access>
  12296. <resetValue>0x0000</resetValue>
  12297. <fields>
  12298. <field>
  12299. <name>DBL</name>
  12300. <description>DMA burst length</description>
  12301. <bitOffset>8</bitOffset>
  12302. <bitWidth>5</bitWidth>
  12303. </field>
  12304. <field>
  12305. <name>DBA</name>
  12306. <description>DMA base address</description>
  12307. <bitOffset>0</bitOffset>
  12308. <bitWidth>5</bitWidth>
  12309. </field>
  12310. </fields>
  12311. </register>
  12312. <register>
  12313. <name>DMAR</name>
  12314. <displayName>DMAR</displayName>
  12315. <description>DMA address for full transfer</description>
  12316. <addressOffset>0x4C</addressOffset>
  12317. <size>0x20</size>
  12318. <access>read-write</access>
  12319. <resetValue>0x0000</resetValue>
  12320. <fields>
  12321. <field>
  12322. <name>DMAB</name>
  12323. <description>DMA register for burst accesses</description>
  12324. <bitOffset>0</bitOffset>
  12325. <bitWidth>16</bitWidth>
  12326. </field>
  12327. </fields>
  12328. </register>
  12329. <register>
  12330. <name>OR</name>
  12331. <displayName>OR</displayName>
  12332. <description>TIM2 option register</description>
  12333. <addressOffset>0x50</addressOffset>
  12334. <size>0x20</size>
  12335. <access>read-write</access>
  12336. <resetValue>0x0000</resetValue>
  12337. <fields>
  12338. <field>
  12339. <name>ETR_RMP</name>
  12340. <description>Timer2 ETR remap</description>
  12341. <bitOffset>0</bitOffset>
  12342. <bitWidth>3</bitWidth>
  12343. </field>
  12344. <field>
  12345. <name>TI4_RMP</name>
  12346. <description>Internal trigger</description>
  12347. <bitOffset>3</bitOffset>
  12348. <bitWidth>2</bitWidth>
  12349. </field>
  12350. </fields>
  12351. </register>
  12352. </registers>
  12353. </peripheral>
  12354. <peripheral>
  12355. <name>TIM21</name>
  12356. <description>General-purpose-timers</description>
  12357. <groupName>TIM</groupName>
  12358. <baseAddress>0x40010800</baseAddress>
  12359. <addressBlock>
  12360. <offset>0x0</offset>
  12361. <size>0x400</size>
  12362. <usage>registers</usage>
  12363. </addressBlock>
  12364. <interrupt>
  12365. <name>TIM2</name>
  12366. <description>TIM2 global interrupt</description>
  12367. <value>15</value>
  12368. </interrupt>
  12369. <registers>
  12370. <register>
  12371. <name>CR1</name>
  12372. <displayName>CR1</displayName>
  12373. <description>control register 1</description>
  12374. <addressOffset>0x0</addressOffset>
  12375. <size>0x20</size>
  12376. <access>read-write</access>
  12377. <resetValue>0x0000</resetValue>
  12378. <fields>
  12379. <field>
  12380. <name>CEN</name>
  12381. <description>Counter enable</description>
  12382. <bitOffset>0</bitOffset>
  12383. <bitWidth>1</bitWidth>
  12384. </field>
  12385. <field>
  12386. <name>UDIS</name>
  12387. <description>Update disable</description>
  12388. <bitOffset>1</bitOffset>
  12389. <bitWidth>1</bitWidth>
  12390. </field>
  12391. <field>
  12392. <name>URS</name>
  12393. <description>Update request source</description>
  12394. <bitOffset>2</bitOffset>
  12395. <bitWidth>1</bitWidth>
  12396. </field>
  12397. <field>
  12398. <name>OPM</name>
  12399. <description>One-pulse mode</description>
  12400. <bitOffset>3</bitOffset>
  12401. <bitWidth>1</bitWidth>
  12402. </field>
  12403. <field>
  12404. <name>DIR</name>
  12405. <description>Direction</description>
  12406. <bitOffset>4</bitOffset>
  12407. <bitWidth>1</bitWidth>
  12408. </field>
  12409. <field>
  12410. <name>CMS</name>
  12411. <description>Center-aligned mode selection</description>
  12412. <bitOffset>5</bitOffset>
  12413. <bitWidth>2</bitWidth>
  12414. </field>
  12415. <field>
  12416. <name>ARPE</name>
  12417. <description>Auto-reload preload enable</description>
  12418. <bitOffset>7</bitOffset>
  12419. <bitWidth>1</bitWidth>
  12420. </field>
  12421. <field>
  12422. <name>CKD</name>
  12423. <description>Clock division</description>
  12424. <bitOffset>8</bitOffset>
  12425. <bitWidth>2</bitWidth>
  12426. </field>
  12427. </fields>
  12428. </register>
  12429. <register>
  12430. <name>CR2</name>
  12431. <displayName>CR2</displayName>
  12432. <description>control register 2</description>
  12433. <addressOffset>0x4</addressOffset>
  12434. <size>0x20</size>
  12435. <access>read-write</access>
  12436. <resetValue>0x0000</resetValue>
  12437. <fields>
  12438. <field>
  12439. <name>MMS</name>
  12440. <description>Master mode selection</description>
  12441. <bitOffset>4</bitOffset>
  12442. <bitWidth>3</bitWidth>
  12443. </field>
  12444. </fields>
  12445. </register>
  12446. <register>
  12447. <name>SMCR</name>
  12448. <displayName>SMCR</displayName>
  12449. <description>slave mode control register</description>
  12450. <addressOffset>0x8</addressOffset>
  12451. <size>0x20</size>
  12452. <access>read-write</access>
  12453. <resetValue>0x0000</resetValue>
  12454. <fields>
  12455. <field>
  12456. <name>SMS</name>
  12457. <description>Slave mode selection</description>
  12458. <bitOffset>0</bitOffset>
  12459. <bitWidth>3</bitWidth>
  12460. </field>
  12461. <field>
  12462. <name>TS</name>
  12463. <description>Trigger selection</description>
  12464. <bitOffset>4</bitOffset>
  12465. <bitWidth>3</bitWidth>
  12466. </field>
  12467. <field>
  12468. <name>MSM</name>
  12469. <description>Master/Slave mode</description>
  12470. <bitOffset>7</bitOffset>
  12471. <bitWidth>1</bitWidth>
  12472. </field>
  12473. <field>
  12474. <name>ETF</name>
  12475. <description>External trigger filter</description>
  12476. <bitOffset>8</bitOffset>
  12477. <bitWidth>4</bitWidth>
  12478. </field>
  12479. <field>
  12480. <name>ETPS</name>
  12481. <description>External trigger prescaler</description>
  12482. <bitOffset>12</bitOffset>
  12483. <bitWidth>2</bitWidth>
  12484. </field>
  12485. <field>
  12486. <name>ECE</name>
  12487. <description>External clock enable</description>
  12488. <bitOffset>14</bitOffset>
  12489. <bitWidth>1</bitWidth>
  12490. </field>
  12491. <field>
  12492. <name>ETP</name>
  12493. <description>External trigger polarity</description>
  12494. <bitOffset>15</bitOffset>
  12495. <bitWidth>1</bitWidth>
  12496. </field>
  12497. </fields>
  12498. </register>
  12499. <register>
  12500. <name>DIER</name>
  12501. <displayName>DIER</displayName>
  12502. <description>DMA/Interrupt enable register</description>
  12503. <addressOffset>0xC</addressOffset>
  12504. <size>0x20</size>
  12505. <access>read-write</access>
  12506. <resetValue>0x0000</resetValue>
  12507. <fields>
  12508. <field>
  12509. <name>TIE</name>
  12510. <description>Trigger interrupt enable</description>
  12511. <bitOffset>6</bitOffset>
  12512. <bitWidth>1</bitWidth>
  12513. </field>
  12514. <field>
  12515. <name>CC2IE</name>
  12516. <description>Capture/Compare 2 interrupt enable</description>
  12517. <bitOffset>2</bitOffset>
  12518. <bitWidth>1</bitWidth>
  12519. </field>
  12520. <field>
  12521. <name>CC1IE</name>
  12522. <description>Capture/Compare 1 interrupt enable</description>
  12523. <bitOffset>1</bitOffset>
  12524. <bitWidth>1</bitWidth>
  12525. </field>
  12526. <field>
  12527. <name>UIE</name>
  12528. <description>Update interrupt enable</description>
  12529. <bitOffset>0</bitOffset>
  12530. <bitWidth>1</bitWidth>
  12531. </field>
  12532. </fields>
  12533. </register>
  12534. <register>
  12535. <name>SR</name>
  12536. <displayName>SR</displayName>
  12537. <description>status register</description>
  12538. <addressOffset>0x10</addressOffset>
  12539. <size>0x20</size>
  12540. <access>read-write</access>
  12541. <resetValue>0x0000</resetValue>
  12542. <fields>
  12543. <field>
  12544. <name>CC2OF</name>
  12545. <description>Capture/compare 2 overcapture flag</description>
  12546. <bitOffset>10</bitOffset>
  12547. <bitWidth>1</bitWidth>
  12548. </field>
  12549. <field>
  12550. <name>CC1OF</name>
  12551. <description>Capture/Compare 1 overcapture flag</description>
  12552. <bitOffset>9</bitOffset>
  12553. <bitWidth>1</bitWidth>
  12554. </field>
  12555. <field>
  12556. <name>TIF</name>
  12557. <description>Trigger interrupt flag</description>
  12558. <bitOffset>6</bitOffset>
  12559. <bitWidth>1</bitWidth>
  12560. </field>
  12561. <field>
  12562. <name>CC2IF</name>
  12563. <description>Capture/Compare 2 interrupt flag</description>
  12564. <bitOffset>2</bitOffset>
  12565. <bitWidth>1</bitWidth>
  12566. </field>
  12567. <field>
  12568. <name>CC1IF</name>
  12569. <description>Capture/compare 1 interrupt flag</description>
  12570. <bitOffset>1</bitOffset>
  12571. <bitWidth>1</bitWidth>
  12572. </field>
  12573. <field>
  12574. <name>UIF</name>
  12575. <description>Update interrupt flag</description>
  12576. <bitOffset>0</bitOffset>
  12577. <bitWidth>1</bitWidth>
  12578. </field>
  12579. </fields>
  12580. </register>
  12581. <register>
  12582. <name>EGR</name>
  12583. <displayName>EGR</displayName>
  12584. <description>event generation register</description>
  12585. <addressOffset>0x14</addressOffset>
  12586. <size>0x20</size>
  12587. <access>write-only</access>
  12588. <resetValue>0x0000</resetValue>
  12589. <fields>
  12590. <field>
  12591. <name>TG</name>
  12592. <description>Trigger generation</description>
  12593. <bitOffset>6</bitOffset>
  12594. <bitWidth>1</bitWidth>
  12595. </field>
  12596. <field>
  12597. <name>CC2G</name>
  12598. <description>Capture/compare 2 generation</description>
  12599. <bitOffset>2</bitOffset>
  12600. <bitWidth>1</bitWidth>
  12601. </field>
  12602. <field>
  12603. <name>CC1G</name>
  12604. <description>Capture/compare 1 generation</description>
  12605. <bitOffset>1</bitOffset>
  12606. <bitWidth>1</bitWidth>
  12607. </field>
  12608. <field>
  12609. <name>UG</name>
  12610. <description>Update generation</description>
  12611. <bitOffset>0</bitOffset>
  12612. <bitWidth>1</bitWidth>
  12613. </field>
  12614. </fields>
  12615. </register>
  12616. <register>
  12617. <name>CCMR1_Output</name>
  12618. <displayName>CCMR1_Output</displayName>
  12619. <description>capture/compare mode register (output mode)</description>
  12620. <addressOffset>0x18</addressOffset>
  12621. <size>0x20</size>
  12622. <access>read-write</access>
  12623. <resetValue>0x00000000</resetValue>
  12624. <fields>
  12625. <field>
  12626. <name>OC2M</name>
  12627. <description>Output Compare 2 mode</description>
  12628. <bitOffset>12</bitOffset>
  12629. <bitWidth>3</bitWidth>
  12630. </field>
  12631. <field>
  12632. <name>OC2PE</name>
  12633. <description>Output Compare 2 preload enable</description>
  12634. <bitOffset>11</bitOffset>
  12635. <bitWidth>1</bitWidth>
  12636. </field>
  12637. <field>
  12638. <name>OC2FE</name>
  12639. <description>Output Compare 2 fast enable</description>
  12640. <bitOffset>10</bitOffset>
  12641. <bitWidth>1</bitWidth>
  12642. </field>
  12643. <field>
  12644. <name>CC2S</name>
  12645. <description>Capture/Compare 2 selection</description>
  12646. <bitOffset>8</bitOffset>
  12647. <bitWidth>2</bitWidth>
  12648. </field>
  12649. <field>
  12650. <name>OC1M</name>
  12651. <description>Output Compare 1 mode</description>
  12652. <bitOffset>4</bitOffset>
  12653. <bitWidth>3</bitWidth>
  12654. </field>
  12655. <field>
  12656. <name>OC1PE</name>
  12657. <description>Output Compare 1 preload enable</description>
  12658. <bitOffset>3</bitOffset>
  12659. <bitWidth>1</bitWidth>
  12660. </field>
  12661. <field>
  12662. <name>OC1FE</name>
  12663. <description>Output Compare 1 fast enable</description>
  12664. <bitOffset>2</bitOffset>
  12665. <bitWidth>1</bitWidth>
  12666. </field>
  12667. <field>
  12668. <name>CC1S</name>
  12669. <description>Capture/Compare 1 selection</description>
  12670. <bitOffset>0</bitOffset>
  12671. <bitWidth>2</bitWidth>
  12672. </field>
  12673. </fields>
  12674. </register>
  12675. <register>
  12676. <name>CCMR1_Input</name>
  12677. <displayName>CCMR1_Input</displayName>
  12678. <description>capture/compare mode register 1 (input mode)</description>
  12679. <alternateRegister>CCMR1_Output</alternateRegister>
  12680. <addressOffset>0x18</addressOffset>
  12681. <size>0x20</size>
  12682. <access>read-write</access>
  12683. <resetValue>0x00000000</resetValue>
  12684. <fields>
  12685. <field>
  12686. <name>IC2F</name>
  12687. <description>Input capture 2 filter</description>
  12688. <bitOffset>12</bitOffset>
  12689. <bitWidth>4</bitWidth>
  12690. </field>
  12691. <field>
  12692. <name>IC2PSC</name>
  12693. <description>Input capture 2 prescaler</description>
  12694. <bitOffset>10</bitOffset>
  12695. <bitWidth>2</bitWidth>
  12696. </field>
  12697. <field>
  12698. <name>CC2S</name>
  12699. <description>Capture/Compare 2 selection</description>
  12700. <bitOffset>8</bitOffset>
  12701. <bitWidth>2</bitWidth>
  12702. </field>
  12703. <field>
  12704. <name>IC1F</name>
  12705. <description>Input capture 1 filter</description>
  12706. <bitOffset>4</bitOffset>
  12707. <bitWidth>4</bitWidth>
  12708. </field>
  12709. <field>
  12710. <name>IC1PSC</name>
  12711. <description>Input capture 1 prescaler</description>
  12712. <bitOffset>2</bitOffset>
  12713. <bitWidth>2</bitWidth>
  12714. </field>
  12715. <field>
  12716. <name>CC1S</name>
  12717. <description>Capture/Compare 1 selection</description>
  12718. <bitOffset>0</bitOffset>
  12719. <bitWidth>2</bitWidth>
  12720. </field>
  12721. </fields>
  12722. </register>
  12723. <register>
  12724. <name>CCER</name>
  12725. <displayName>CCER</displayName>
  12726. <description>capture/compare enable register</description>
  12727. <addressOffset>0x20</addressOffset>
  12728. <size>0x20</size>
  12729. <access>read-write</access>
  12730. <resetValue>0x0000</resetValue>
  12731. <fields>
  12732. <field>
  12733. <name>CC2NP</name>
  12734. <description>Capture/Compare 2 output Polarity</description>
  12735. <bitOffset>7</bitOffset>
  12736. <bitWidth>1</bitWidth>
  12737. </field>
  12738. <field>
  12739. <name>CC2P</name>
  12740. <description>Capture/Compare 2 output Polarity</description>
  12741. <bitOffset>5</bitOffset>
  12742. <bitWidth>1</bitWidth>
  12743. </field>
  12744. <field>
  12745. <name>CC2E</name>
  12746. <description>Capture/Compare 2 output enable</description>
  12747. <bitOffset>4</bitOffset>
  12748. <bitWidth>1</bitWidth>
  12749. </field>
  12750. <field>
  12751. <name>CC1NP</name>
  12752. <description>Capture/Compare 1 output Polarity</description>
  12753. <bitOffset>3</bitOffset>
  12754. <bitWidth>1</bitWidth>
  12755. </field>
  12756. <field>
  12757. <name>CC1P</name>
  12758. <description>Capture/Compare 1 output Polarity</description>
  12759. <bitOffset>1</bitOffset>
  12760. <bitWidth>1</bitWidth>
  12761. </field>
  12762. <field>
  12763. <name>CC1E</name>
  12764. <description>Capture/Compare 1 output enable</description>
  12765. <bitOffset>0</bitOffset>
  12766. <bitWidth>1</bitWidth>
  12767. </field>
  12768. </fields>
  12769. </register>
  12770. <register>
  12771. <name>CNT</name>
  12772. <displayName>CNT</displayName>
  12773. <description>counter</description>
  12774. <addressOffset>0x24</addressOffset>
  12775. <size>0x20</size>
  12776. <access>read-write</access>
  12777. <resetValue>0x00000000</resetValue>
  12778. <fields>
  12779. <field>
  12780. <name>CNT</name>
  12781. <description>counter value</description>
  12782. <bitOffset>0</bitOffset>
  12783. <bitWidth>16</bitWidth>
  12784. </field>
  12785. </fields>
  12786. </register>
  12787. <register>
  12788. <name>PSC</name>
  12789. <displayName>PSC</displayName>
  12790. <description>prescaler</description>
  12791. <addressOffset>0x28</addressOffset>
  12792. <size>0x20</size>
  12793. <access>read-write</access>
  12794. <resetValue>0x0000</resetValue>
  12795. <fields>
  12796. <field>
  12797. <name>PSC</name>
  12798. <description>Prescaler value</description>
  12799. <bitOffset>0</bitOffset>
  12800. <bitWidth>16</bitWidth>
  12801. </field>
  12802. </fields>
  12803. </register>
  12804. <register>
  12805. <name>ARR</name>
  12806. <displayName>ARR</displayName>
  12807. <description>auto-reload register</description>
  12808. <addressOffset>0x2C</addressOffset>
  12809. <size>0x20</size>
  12810. <access>read-write</access>
  12811. <resetValue>0x00000000</resetValue>
  12812. <fields>
  12813. <field>
  12814. <name>ARR</name>
  12815. <description>Auto-reload value</description>
  12816. <bitOffset>0</bitOffset>
  12817. <bitWidth>16</bitWidth>
  12818. </field>
  12819. </fields>
  12820. </register>
  12821. <register>
  12822. <name>CCR1</name>
  12823. <displayName>CCR1</displayName>
  12824. <description>capture/compare register 1</description>
  12825. <addressOffset>0x34</addressOffset>
  12826. <size>0x20</size>
  12827. <access>read-write</access>
  12828. <resetValue>0x00000000</resetValue>
  12829. <fields>
  12830. <field>
  12831. <name>CCR1</name>
  12832. <description>Capture/Compare 1 value</description>
  12833. <bitOffset>0</bitOffset>
  12834. <bitWidth>16</bitWidth>
  12835. </field>
  12836. </fields>
  12837. </register>
  12838. <register>
  12839. <name>CCR2</name>
  12840. <displayName>CCR2</displayName>
  12841. <description>capture/compare register 2</description>
  12842. <addressOffset>0x38</addressOffset>
  12843. <size>0x20</size>
  12844. <access>read-write</access>
  12845. <resetValue>0x00000000</resetValue>
  12846. <fields>
  12847. <field>
  12848. <name>CCR2</name>
  12849. <description>Capture/Compare 2 value</description>
  12850. <bitOffset>0</bitOffset>
  12851. <bitWidth>16</bitWidth>
  12852. </field>
  12853. </fields>
  12854. </register>
  12855. <register>
  12856. <name>OR</name>
  12857. <displayName>OR</displayName>
  12858. <description>TIM21 option register</description>
  12859. <addressOffset>0x50</addressOffset>
  12860. <size>0x20</size>
  12861. <access>read-write</access>
  12862. <resetValue>0x00000000</resetValue>
  12863. <fields>
  12864. <field>
  12865. <name>ETR_RMP</name>
  12866. <description>Timer21 ETR remap</description>
  12867. <bitOffset>0</bitOffset>
  12868. <bitWidth>2</bitWidth>
  12869. </field>
  12870. <field>
  12871. <name>TI1_RMP</name>
  12872. <description>Timer21 TI1</description>
  12873. <bitOffset>2</bitOffset>
  12874. <bitWidth>3</bitWidth>
  12875. </field>
  12876. <field>
  12877. <name>TI2_RMP</name>
  12878. <description>Timer21 TI2</description>
  12879. <bitOffset>5</bitOffset>
  12880. <bitWidth>1</bitWidth>
  12881. </field>
  12882. </fields>
  12883. </register>
  12884. </registers>
  12885. </peripheral>
  12886. <peripheral>
  12887. <name>TIM22</name>
  12888. <description>General-purpose-timers</description>
  12889. <groupName>TIM</groupName>
  12890. <baseAddress>0x40011400</baseAddress>
  12891. <addressBlock>
  12892. <offset>0x0</offset>
  12893. <size>0x400</size>
  12894. <usage>registers</usage>
  12895. </addressBlock>
  12896. <interrupt>
  12897. <name>TIM21</name>
  12898. <description>TIMER21 global interrupt</description>
  12899. <value>20</value>
  12900. </interrupt>
  12901. <registers>
  12902. <register>
  12903. <name>CR1</name>
  12904. <displayName>CR1</displayName>
  12905. <description>control register 1</description>
  12906. <addressOffset>0x0</addressOffset>
  12907. <size>0x20</size>
  12908. <access>read-write</access>
  12909. <resetValue>0x0000</resetValue>
  12910. <fields>
  12911. <field>
  12912. <name>CEN</name>
  12913. <description>Counter enable</description>
  12914. <bitOffset>0</bitOffset>
  12915. <bitWidth>1</bitWidth>
  12916. </field>
  12917. <field>
  12918. <name>UDIS</name>
  12919. <description>Update disable</description>
  12920. <bitOffset>1</bitOffset>
  12921. <bitWidth>1</bitWidth>
  12922. </field>
  12923. <field>
  12924. <name>URS</name>
  12925. <description>Update request source</description>
  12926. <bitOffset>2</bitOffset>
  12927. <bitWidth>1</bitWidth>
  12928. </field>
  12929. <field>
  12930. <name>OPM</name>
  12931. <description>One-pulse mode</description>
  12932. <bitOffset>3</bitOffset>
  12933. <bitWidth>1</bitWidth>
  12934. </field>
  12935. <field>
  12936. <name>DIR</name>
  12937. <description>Direction</description>
  12938. <bitOffset>4</bitOffset>
  12939. <bitWidth>1</bitWidth>
  12940. </field>
  12941. <field>
  12942. <name>CMS</name>
  12943. <description>Center-aligned mode selection</description>
  12944. <bitOffset>5</bitOffset>
  12945. <bitWidth>2</bitWidth>
  12946. </field>
  12947. <field>
  12948. <name>ARPE</name>
  12949. <description>Auto-reload preload enable</description>
  12950. <bitOffset>7</bitOffset>
  12951. <bitWidth>1</bitWidth>
  12952. </field>
  12953. <field>
  12954. <name>CKD</name>
  12955. <description>Clock division</description>
  12956. <bitOffset>8</bitOffset>
  12957. <bitWidth>2</bitWidth>
  12958. </field>
  12959. </fields>
  12960. </register>
  12961. <register>
  12962. <name>CR2</name>
  12963. <displayName>CR2</displayName>
  12964. <description>control register 2</description>
  12965. <addressOffset>0x4</addressOffset>
  12966. <size>0x20</size>
  12967. <access>read-write</access>
  12968. <resetValue>0x0000</resetValue>
  12969. <fields>
  12970. <field>
  12971. <name>MMS</name>
  12972. <description>Master mode selection</description>
  12973. <bitOffset>4</bitOffset>
  12974. <bitWidth>3</bitWidth>
  12975. </field>
  12976. </fields>
  12977. </register>
  12978. <register>
  12979. <name>SMCR</name>
  12980. <displayName>SMCR</displayName>
  12981. <description>slave mode control register</description>
  12982. <addressOffset>0x8</addressOffset>
  12983. <size>0x20</size>
  12984. <access>read-write</access>
  12985. <resetValue>0x0000</resetValue>
  12986. <fields>
  12987. <field>
  12988. <name>SMS</name>
  12989. <description>Slave mode selection</description>
  12990. <bitOffset>0</bitOffset>
  12991. <bitWidth>3</bitWidth>
  12992. </field>
  12993. <field>
  12994. <name>TS</name>
  12995. <description>Trigger selection</description>
  12996. <bitOffset>4</bitOffset>
  12997. <bitWidth>3</bitWidth>
  12998. </field>
  12999. <field>
  13000. <name>MSM</name>
  13001. <description>Master/Slave mode</description>
  13002. <bitOffset>7</bitOffset>
  13003. <bitWidth>1</bitWidth>
  13004. </field>
  13005. <field>
  13006. <name>ETF</name>
  13007. <description>External trigger filter</description>
  13008. <bitOffset>8</bitOffset>
  13009. <bitWidth>4</bitWidth>
  13010. </field>
  13011. <field>
  13012. <name>ETPS</name>
  13013. <description>External trigger prescaler</description>
  13014. <bitOffset>12</bitOffset>
  13015. <bitWidth>2</bitWidth>
  13016. </field>
  13017. <field>
  13018. <name>ECE</name>
  13019. <description>External clock enable</description>
  13020. <bitOffset>14</bitOffset>
  13021. <bitWidth>1</bitWidth>
  13022. </field>
  13023. <field>
  13024. <name>ETP</name>
  13025. <description>External trigger polarity</description>
  13026. <bitOffset>15</bitOffset>
  13027. <bitWidth>1</bitWidth>
  13028. </field>
  13029. </fields>
  13030. </register>
  13031. <register>
  13032. <name>DIER</name>
  13033. <displayName>DIER</displayName>
  13034. <description>DMA/Interrupt enable register</description>
  13035. <addressOffset>0xC</addressOffset>
  13036. <size>0x20</size>
  13037. <access>read-write</access>
  13038. <resetValue>0x0000</resetValue>
  13039. <fields>
  13040. <field>
  13041. <name>TIE</name>
  13042. <description>Trigger interrupt enable</description>
  13043. <bitOffset>6</bitOffset>
  13044. <bitWidth>1</bitWidth>
  13045. </field>
  13046. <field>
  13047. <name>CC2IE</name>
  13048. <description>Capture/Compare 2 interrupt enable</description>
  13049. <bitOffset>2</bitOffset>
  13050. <bitWidth>1</bitWidth>
  13051. </field>
  13052. <field>
  13053. <name>CC1IE</name>
  13054. <description>Capture/Compare 1 interrupt enable</description>
  13055. <bitOffset>1</bitOffset>
  13056. <bitWidth>1</bitWidth>
  13057. </field>
  13058. <field>
  13059. <name>UIE</name>
  13060. <description>Update interrupt enable</description>
  13061. <bitOffset>0</bitOffset>
  13062. <bitWidth>1</bitWidth>
  13063. </field>
  13064. </fields>
  13065. </register>
  13066. <register>
  13067. <name>SR</name>
  13068. <displayName>SR</displayName>
  13069. <description>status register</description>
  13070. <addressOffset>0x10</addressOffset>
  13071. <size>0x20</size>
  13072. <access>read-write</access>
  13073. <resetValue>0x0000</resetValue>
  13074. <fields>
  13075. <field>
  13076. <name>CC2OF</name>
  13077. <description>Capture/compare 2 overcapture flag</description>
  13078. <bitOffset>10</bitOffset>
  13079. <bitWidth>1</bitWidth>
  13080. </field>
  13081. <field>
  13082. <name>CC1OF</name>
  13083. <description>Capture/Compare 1 overcapture flag</description>
  13084. <bitOffset>9</bitOffset>
  13085. <bitWidth>1</bitWidth>
  13086. </field>
  13087. <field>
  13088. <name>TIF</name>
  13089. <description>Trigger interrupt flag</description>
  13090. <bitOffset>6</bitOffset>
  13091. <bitWidth>1</bitWidth>
  13092. </field>
  13093. <field>
  13094. <name>CC2IF</name>
  13095. <description>Capture/Compare 2 interrupt flag</description>
  13096. <bitOffset>2</bitOffset>
  13097. <bitWidth>1</bitWidth>
  13098. </field>
  13099. <field>
  13100. <name>CC1IF</name>
  13101. <description>Capture/compare 1 interrupt flag</description>
  13102. <bitOffset>1</bitOffset>
  13103. <bitWidth>1</bitWidth>
  13104. </field>
  13105. <field>
  13106. <name>UIF</name>
  13107. <description>Update interrupt flag</description>
  13108. <bitOffset>0</bitOffset>
  13109. <bitWidth>1</bitWidth>
  13110. </field>
  13111. </fields>
  13112. </register>
  13113. <register>
  13114. <name>EGR</name>
  13115. <displayName>EGR</displayName>
  13116. <description>event generation register</description>
  13117. <addressOffset>0x14</addressOffset>
  13118. <size>0x20</size>
  13119. <access>write-only</access>
  13120. <resetValue>0x0000</resetValue>
  13121. <fields>
  13122. <field>
  13123. <name>TG</name>
  13124. <description>Trigger generation</description>
  13125. <bitOffset>6</bitOffset>
  13126. <bitWidth>1</bitWidth>
  13127. </field>
  13128. <field>
  13129. <name>CC2G</name>
  13130. <description>Capture/compare 2 generation</description>
  13131. <bitOffset>2</bitOffset>
  13132. <bitWidth>1</bitWidth>
  13133. </field>
  13134. <field>
  13135. <name>CC1G</name>
  13136. <description>Capture/compare 1 generation</description>
  13137. <bitOffset>1</bitOffset>
  13138. <bitWidth>1</bitWidth>
  13139. </field>
  13140. <field>
  13141. <name>UG</name>
  13142. <description>Update generation</description>
  13143. <bitOffset>0</bitOffset>
  13144. <bitWidth>1</bitWidth>
  13145. </field>
  13146. </fields>
  13147. </register>
  13148. <register>
  13149. <name>CCMR1_Output</name>
  13150. <displayName>CCMR1_Output</displayName>
  13151. <description>capture/compare mode register (output mode)</description>
  13152. <addressOffset>0x18</addressOffset>
  13153. <size>0x20</size>
  13154. <access>read-write</access>
  13155. <resetValue>0x00000000</resetValue>
  13156. <fields>
  13157. <field>
  13158. <name>OC2M</name>
  13159. <description>Output Compare 2 mode</description>
  13160. <bitOffset>12</bitOffset>
  13161. <bitWidth>3</bitWidth>
  13162. </field>
  13163. <field>
  13164. <name>OC2PE</name>
  13165. <description>Output Compare 2 preload enable</description>
  13166. <bitOffset>11</bitOffset>
  13167. <bitWidth>1</bitWidth>
  13168. </field>
  13169. <field>
  13170. <name>OC2FE</name>
  13171. <description>Output Compare 2 fast enable</description>
  13172. <bitOffset>10</bitOffset>
  13173. <bitWidth>1</bitWidth>
  13174. </field>
  13175. <field>
  13176. <name>CC2S</name>
  13177. <description>Capture/Compare 2 selection</description>
  13178. <bitOffset>8</bitOffset>
  13179. <bitWidth>2</bitWidth>
  13180. </field>
  13181. <field>
  13182. <name>OC1M</name>
  13183. <description>Output Compare 1 mode</description>
  13184. <bitOffset>4</bitOffset>
  13185. <bitWidth>3</bitWidth>
  13186. </field>
  13187. <field>
  13188. <name>OC1PE</name>
  13189. <description>Output Compare 1 preload enable</description>
  13190. <bitOffset>3</bitOffset>
  13191. <bitWidth>1</bitWidth>
  13192. </field>
  13193. <field>
  13194. <name>OC1FE</name>
  13195. <description>Output Compare 1 fast enable</description>
  13196. <bitOffset>2</bitOffset>
  13197. <bitWidth>1</bitWidth>
  13198. </field>
  13199. <field>
  13200. <name>CC1S</name>
  13201. <description>Capture/Compare 1 selection</description>
  13202. <bitOffset>0</bitOffset>
  13203. <bitWidth>2</bitWidth>
  13204. </field>
  13205. </fields>
  13206. </register>
  13207. <register>
  13208. <name>CCMR1_Input</name>
  13209. <displayName>CCMR1_Input</displayName>
  13210. <description>capture/compare mode register 1 (input mode)</description>
  13211. <alternateRegister>CCMR1_Output</alternateRegister>
  13212. <addressOffset>0x18</addressOffset>
  13213. <size>0x20</size>
  13214. <access>read-write</access>
  13215. <resetValue>0x00000000</resetValue>
  13216. <fields>
  13217. <field>
  13218. <name>IC2F</name>
  13219. <description>Input capture 2 filter</description>
  13220. <bitOffset>12</bitOffset>
  13221. <bitWidth>4</bitWidth>
  13222. </field>
  13223. <field>
  13224. <name>IC2PSC</name>
  13225. <description>Input capture 2 prescaler</description>
  13226. <bitOffset>10</bitOffset>
  13227. <bitWidth>2</bitWidth>
  13228. </field>
  13229. <field>
  13230. <name>CC2S</name>
  13231. <description>Capture/Compare 2 selection</description>
  13232. <bitOffset>8</bitOffset>
  13233. <bitWidth>2</bitWidth>
  13234. </field>
  13235. <field>
  13236. <name>IC1F</name>
  13237. <description>Input capture 1 filter</description>
  13238. <bitOffset>4</bitOffset>
  13239. <bitWidth>4</bitWidth>
  13240. </field>
  13241. <field>
  13242. <name>IC1PSC</name>
  13243. <description>Input capture 1 prescaler</description>
  13244. <bitOffset>2</bitOffset>
  13245. <bitWidth>2</bitWidth>
  13246. </field>
  13247. <field>
  13248. <name>CC1S</name>
  13249. <description>Capture/Compare 1 selection</description>
  13250. <bitOffset>0</bitOffset>
  13251. <bitWidth>2</bitWidth>
  13252. </field>
  13253. </fields>
  13254. </register>
  13255. <register>
  13256. <name>CCER</name>
  13257. <displayName>CCER</displayName>
  13258. <description>capture/compare enable register</description>
  13259. <addressOffset>0x20</addressOffset>
  13260. <size>0x20</size>
  13261. <access>read-write</access>
  13262. <resetValue>0x0000</resetValue>
  13263. <fields>
  13264. <field>
  13265. <name>CC2NP</name>
  13266. <description>Capture/Compare 2 output Polarity</description>
  13267. <bitOffset>7</bitOffset>
  13268. <bitWidth>1</bitWidth>
  13269. </field>
  13270. <field>
  13271. <name>CC2P</name>
  13272. <description>Capture/Compare 2 output Polarity</description>
  13273. <bitOffset>5</bitOffset>
  13274. <bitWidth>1</bitWidth>
  13275. </field>
  13276. <field>
  13277. <name>CC2E</name>
  13278. <description>Capture/Compare 2 output enable</description>
  13279. <bitOffset>4</bitOffset>
  13280. <bitWidth>1</bitWidth>
  13281. </field>
  13282. <field>
  13283. <name>CC1NP</name>
  13284. <description>Capture/Compare 1 output Polarity</description>
  13285. <bitOffset>3</bitOffset>
  13286. <bitWidth>1</bitWidth>
  13287. </field>
  13288. <field>
  13289. <name>CC1P</name>
  13290. <description>Capture/Compare 1 output Polarity</description>
  13291. <bitOffset>1</bitOffset>
  13292. <bitWidth>1</bitWidth>
  13293. </field>
  13294. <field>
  13295. <name>CC1E</name>
  13296. <description>Capture/Compare 1 output enable</description>
  13297. <bitOffset>0</bitOffset>
  13298. <bitWidth>1</bitWidth>
  13299. </field>
  13300. </fields>
  13301. </register>
  13302. <register>
  13303. <name>CNT</name>
  13304. <displayName>CNT</displayName>
  13305. <description>counter</description>
  13306. <addressOffset>0x24</addressOffset>
  13307. <size>0x20</size>
  13308. <access>read-write</access>
  13309. <resetValue>0x00000000</resetValue>
  13310. <fields>
  13311. <field>
  13312. <name>CNT</name>
  13313. <description>counter value</description>
  13314. <bitOffset>0</bitOffset>
  13315. <bitWidth>16</bitWidth>
  13316. </field>
  13317. </fields>
  13318. </register>
  13319. <register>
  13320. <name>PSC</name>
  13321. <displayName>PSC</displayName>
  13322. <description>prescaler</description>
  13323. <addressOffset>0x28</addressOffset>
  13324. <size>0x20</size>
  13325. <access>read-write</access>
  13326. <resetValue>0x0000</resetValue>
  13327. <fields>
  13328. <field>
  13329. <name>PSC</name>
  13330. <description>Prescaler value</description>
  13331. <bitOffset>0</bitOffset>
  13332. <bitWidth>16</bitWidth>
  13333. </field>
  13334. </fields>
  13335. </register>
  13336. <register>
  13337. <name>ARR</name>
  13338. <displayName>ARR</displayName>
  13339. <description>auto-reload register</description>
  13340. <addressOffset>0x2C</addressOffset>
  13341. <size>0x20</size>
  13342. <access>read-write</access>
  13343. <resetValue>0x00000000</resetValue>
  13344. <fields>
  13345. <field>
  13346. <name>ARR</name>
  13347. <description>Auto-reload value</description>
  13348. <bitOffset>0</bitOffset>
  13349. <bitWidth>16</bitWidth>
  13350. </field>
  13351. </fields>
  13352. </register>
  13353. <register>
  13354. <name>CCR1</name>
  13355. <displayName>CCR1</displayName>
  13356. <description>capture/compare register 1</description>
  13357. <addressOffset>0x34</addressOffset>
  13358. <size>0x20</size>
  13359. <access>read-write</access>
  13360. <resetValue>0x00000000</resetValue>
  13361. <fields>
  13362. <field>
  13363. <name>CCR1</name>
  13364. <description>Capture/Compare 1 value</description>
  13365. <bitOffset>0</bitOffset>
  13366. <bitWidth>16</bitWidth>
  13367. </field>
  13368. </fields>
  13369. </register>
  13370. <register>
  13371. <name>CCR2</name>
  13372. <displayName>CCR2</displayName>
  13373. <description>capture/compare register 2</description>
  13374. <addressOffset>0x38</addressOffset>
  13375. <size>0x20</size>
  13376. <access>read-write</access>
  13377. <resetValue>0x00000000</resetValue>
  13378. <fields>
  13379. <field>
  13380. <name>CCR2</name>
  13381. <description>Capture/Compare 2 value</description>
  13382. <bitOffset>0</bitOffset>
  13383. <bitWidth>16</bitWidth>
  13384. </field>
  13385. </fields>
  13386. </register>
  13387. <register>
  13388. <name>OR</name>
  13389. <displayName>OR</displayName>
  13390. <description>TIM22 option register</description>
  13391. <addressOffset>0x50</addressOffset>
  13392. <size>0x20</size>
  13393. <access>read-write</access>
  13394. <resetValue>0x00000000</resetValue>
  13395. <fields>
  13396. <field>
  13397. <name>ETR_RMP</name>
  13398. <description>Timer22 ETR remap</description>
  13399. <bitOffset>0</bitOffset>
  13400. <bitWidth>2</bitWidth>
  13401. </field>
  13402. <field>
  13403. <name>TI1_RMP</name>
  13404. <description>Timer22 TI1</description>
  13405. <bitOffset>2</bitOffset>
  13406. <bitWidth>2</bitWidth>
  13407. </field>
  13408. </fields>
  13409. </register>
  13410. </registers>
  13411. </peripheral>
  13412. <peripheral>
  13413. <name>LPUART1</name>
  13414. <description>Lower power Universal asynchronous receiver transmitter</description>
  13415. <groupName>USART</groupName>
  13416. <baseAddress>0x40004800</baseAddress>
  13417. <addressBlock>
  13418. <offset>0x0</offset>
  13419. <size>0x400</size>
  13420. <usage>registers</usage>
  13421. </addressBlock>
  13422. <interrupt>
  13423. <name>TIM22</name>
  13424. <description>TIMER22 global interrupt</description>
  13425. <value>22</value>
  13426. </interrupt>
  13427. <registers>
  13428. <register>
  13429. <name>CR1</name>
  13430. <displayName>CR1</displayName>
  13431. <description>Control register 1</description>
  13432. <addressOffset>0x0</addressOffset>
  13433. <size>0x20</size>
  13434. <access>read-write</access>
  13435. <resetValue>0x0000</resetValue>
  13436. <fields>
  13437. <field>
  13438. <name>M1</name>
  13439. <description>Word length</description>
  13440. <bitOffset>28</bitOffset>
  13441. <bitWidth>1</bitWidth>
  13442. </field>
  13443. <field>
  13444. <name>DEAT4</name>
  13445. <description>Driver Enable assertion time</description>
  13446. <bitOffset>25</bitOffset>
  13447. <bitWidth>1</bitWidth>
  13448. </field>
  13449. <field>
  13450. <name>DEAT3</name>
  13451. <description>DEAT3</description>
  13452. <bitOffset>24</bitOffset>
  13453. <bitWidth>1</bitWidth>
  13454. </field>
  13455. <field>
  13456. <name>DEAT2</name>
  13457. <description>DEAT2</description>
  13458. <bitOffset>23</bitOffset>
  13459. <bitWidth>1</bitWidth>
  13460. </field>
  13461. <field>
  13462. <name>DEAT1</name>
  13463. <description>DEAT1</description>
  13464. <bitOffset>22</bitOffset>
  13465. <bitWidth>1</bitWidth>
  13466. </field>
  13467. <field>
  13468. <name>DEAT0</name>
  13469. <description>DEAT0</description>
  13470. <bitOffset>21</bitOffset>
  13471. <bitWidth>1</bitWidth>
  13472. </field>
  13473. <field>
  13474. <name>DEDT4</name>
  13475. <description>Driver Enable de-assertion time</description>
  13476. <bitOffset>20</bitOffset>
  13477. <bitWidth>1</bitWidth>
  13478. </field>
  13479. <field>
  13480. <name>DEDT3</name>
  13481. <description>DEDT3</description>
  13482. <bitOffset>19</bitOffset>
  13483. <bitWidth>1</bitWidth>
  13484. </field>
  13485. <field>
  13486. <name>DEDT2</name>
  13487. <description>DEDT2</description>
  13488. <bitOffset>18</bitOffset>
  13489. <bitWidth>1</bitWidth>
  13490. </field>
  13491. <field>
  13492. <name>DEDT1</name>
  13493. <description>DEDT1</description>
  13494. <bitOffset>17</bitOffset>
  13495. <bitWidth>1</bitWidth>
  13496. </field>
  13497. <field>
  13498. <name>DEDT0</name>
  13499. <description>DEDT0</description>
  13500. <bitOffset>16</bitOffset>
  13501. <bitWidth>1</bitWidth>
  13502. </field>
  13503. <field>
  13504. <name>CMIE</name>
  13505. <description>Character match interrupt enable</description>
  13506. <bitOffset>14</bitOffset>
  13507. <bitWidth>1</bitWidth>
  13508. </field>
  13509. <field>
  13510. <name>MME</name>
  13511. <description>Mute mode enable</description>
  13512. <bitOffset>13</bitOffset>
  13513. <bitWidth>1</bitWidth>
  13514. </field>
  13515. <field>
  13516. <name>M0</name>
  13517. <description>Word length</description>
  13518. <bitOffset>12</bitOffset>
  13519. <bitWidth>1</bitWidth>
  13520. </field>
  13521. <field>
  13522. <name>WAKE</name>
  13523. <description>Receiver wakeup method</description>
  13524. <bitOffset>11</bitOffset>
  13525. <bitWidth>1</bitWidth>
  13526. </field>
  13527. <field>
  13528. <name>PCE</name>
  13529. <description>Parity control enable</description>
  13530. <bitOffset>10</bitOffset>
  13531. <bitWidth>1</bitWidth>
  13532. </field>
  13533. <field>
  13534. <name>PS</name>
  13535. <description>Parity selection</description>
  13536. <bitOffset>9</bitOffset>
  13537. <bitWidth>1</bitWidth>
  13538. </field>
  13539. <field>
  13540. <name>PEIE</name>
  13541. <description>PE interrupt enable</description>
  13542. <bitOffset>8</bitOffset>
  13543. <bitWidth>1</bitWidth>
  13544. </field>
  13545. <field>
  13546. <name>TXEIE</name>
  13547. <description>interrupt enable</description>
  13548. <bitOffset>7</bitOffset>
  13549. <bitWidth>1</bitWidth>
  13550. </field>
  13551. <field>
  13552. <name>TCIE</name>
  13553. <description>Transmission complete interrupt enable</description>
  13554. <bitOffset>6</bitOffset>
  13555. <bitWidth>1</bitWidth>
  13556. </field>
  13557. <field>
  13558. <name>RXNEIE</name>
  13559. <description>RXNE interrupt enable</description>
  13560. <bitOffset>5</bitOffset>
  13561. <bitWidth>1</bitWidth>
  13562. </field>
  13563. <field>
  13564. <name>IDLEIE</name>
  13565. <description>IDLE interrupt enable</description>
  13566. <bitOffset>4</bitOffset>
  13567. <bitWidth>1</bitWidth>
  13568. </field>
  13569. <field>
  13570. <name>TE</name>
  13571. <description>Transmitter enable</description>
  13572. <bitOffset>3</bitOffset>
  13573. <bitWidth>1</bitWidth>
  13574. </field>
  13575. <field>
  13576. <name>RE</name>
  13577. <description>Receiver enable</description>
  13578. <bitOffset>2</bitOffset>
  13579. <bitWidth>1</bitWidth>
  13580. </field>
  13581. <field>
  13582. <name>UESM</name>
  13583. <description>USART enable in Stop mode</description>
  13584. <bitOffset>1</bitOffset>
  13585. <bitWidth>1</bitWidth>
  13586. </field>
  13587. <field>
  13588. <name>UE</name>
  13589. <description>USART enable</description>
  13590. <bitOffset>0</bitOffset>
  13591. <bitWidth>1</bitWidth>
  13592. </field>
  13593. </fields>
  13594. </register>
  13595. <register>
  13596. <name>CR2</name>
  13597. <displayName>CR2</displayName>
  13598. <description>Control register 2</description>
  13599. <addressOffset>0x4</addressOffset>
  13600. <size>0x20</size>
  13601. <access>read-write</access>
  13602. <resetValue>0x0000</resetValue>
  13603. <fields>
  13604. <field>
  13605. <name>ADD4_7</name>
  13606. <description>Address of the USART node</description>
  13607. <bitOffset>28</bitOffset>
  13608. <bitWidth>4</bitWidth>
  13609. </field>
  13610. <field>
  13611. <name>ADD0_3</name>
  13612. <description>Address of the USART node</description>
  13613. <bitOffset>24</bitOffset>
  13614. <bitWidth>4</bitWidth>
  13615. </field>
  13616. <field>
  13617. <name>MSBFIRST</name>
  13618. <description>Most significant bit first</description>
  13619. <bitOffset>19</bitOffset>
  13620. <bitWidth>1</bitWidth>
  13621. </field>
  13622. <field>
  13623. <name>TAINV</name>
  13624. <description>Binary data inversion</description>
  13625. <bitOffset>18</bitOffset>
  13626. <bitWidth>1</bitWidth>
  13627. </field>
  13628. <field>
  13629. <name>TXINV</name>
  13630. <description>TX pin active level inversion</description>
  13631. <bitOffset>17</bitOffset>
  13632. <bitWidth>1</bitWidth>
  13633. </field>
  13634. <field>
  13635. <name>RXINV</name>
  13636. <description>RX pin active level inversion</description>
  13637. <bitOffset>16</bitOffset>
  13638. <bitWidth>1</bitWidth>
  13639. </field>
  13640. <field>
  13641. <name>SWAP</name>
  13642. <description>Swap TX/RX pins</description>
  13643. <bitOffset>15</bitOffset>
  13644. <bitWidth>1</bitWidth>
  13645. </field>
  13646. <field>
  13647. <name>STOP</name>
  13648. <description>STOP bits</description>
  13649. <bitOffset>12</bitOffset>
  13650. <bitWidth>2</bitWidth>
  13651. </field>
  13652. <field>
  13653. <name>CLKEN</name>
  13654. <description>Clock enable</description>
  13655. <bitOffset>11</bitOffset>
  13656. <bitWidth>1</bitWidth>
  13657. </field>
  13658. <field>
  13659. <name>ADDM7</name>
  13660. <description>7-bit Address Detection/4-bit Address Detection</description>
  13661. <bitOffset>4</bitOffset>
  13662. <bitWidth>1</bitWidth>
  13663. </field>
  13664. </fields>
  13665. </register>
  13666. <register>
  13667. <name>CR3</name>
  13668. <displayName>CR3</displayName>
  13669. <description>Control register 3</description>
  13670. <addressOffset>0x8</addressOffset>
  13671. <size>0x20</size>
  13672. <access>read-write</access>
  13673. <resetValue>0x0000</resetValue>
  13674. <fields>
  13675. <field>
  13676. <name>WUFIE</name>
  13677. <description>Wakeup from Stop mode interrupt enable</description>
  13678. <bitOffset>22</bitOffset>
  13679. <bitWidth>1</bitWidth>
  13680. </field>
  13681. <field>
  13682. <name>WUS</name>
  13683. <description>Wakeup from Stop mode interrupt flag selection</description>
  13684. <bitOffset>20</bitOffset>
  13685. <bitWidth>2</bitWidth>
  13686. </field>
  13687. <field>
  13688. <name>DEP</name>
  13689. <description>Driver enable polarity selection</description>
  13690. <bitOffset>15</bitOffset>
  13691. <bitWidth>1</bitWidth>
  13692. </field>
  13693. <field>
  13694. <name>DEM</name>
  13695. <description>Driver enable mode</description>
  13696. <bitOffset>14</bitOffset>
  13697. <bitWidth>1</bitWidth>
  13698. </field>
  13699. <field>
  13700. <name>DDRE</name>
  13701. <description>DMA Disable on Reception Error</description>
  13702. <bitOffset>13</bitOffset>
  13703. <bitWidth>1</bitWidth>
  13704. </field>
  13705. <field>
  13706. <name>OVRDIS</name>
  13707. <description>Overrun Disable</description>
  13708. <bitOffset>12</bitOffset>
  13709. <bitWidth>1</bitWidth>
  13710. </field>
  13711. <field>
  13712. <name>CTSIE</name>
  13713. <description>CTS interrupt enable</description>
  13714. <bitOffset>10</bitOffset>
  13715. <bitWidth>1</bitWidth>
  13716. </field>
  13717. <field>
  13718. <name>CTSE</name>
  13719. <description>CTS enable</description>
  13720. <bitOffset>9</bitOffset>
  13721. <bitWidth>1</bitWidth>
  13722. </field>
  13723. <field>
  13724. <name>RTSE</name>
  13725. <description>RTS enable</description>
  13726. <bitOffset>8</bitOffset>
  13727. <bitWidth>1</bitWidth>
  13728. </field>
  13729. <field>
  13730. <name>DMAT</name>
  13731. <description>DMA enable transmitter</description>
  13732. <bitOffset>7</bitOffset>
  13733. <bitWidth>1</bitWidth>
  13734. </field>
  13735. <field>
  13736. <name>DMAR</name>
  13737. <description>DMA enable receiver</description>
  13738. <bitOffset>6</bitOffset>
  13739. <bitWidth>1</bitWidth>
  13740. </field>
  13741. <field>
  13742. <name>HDSEL</name>
  13743. <description>Half-duplex selection</description>
  13744. <bitOffset>3</bitOffset>
  13745. <bitWidth>1</bitWidth>
  13746. </field>
  13747. <field>
  13748. <name>EIE</name>
  13749. <description>Error interrupt enable</description>
  13750. <bitOffset>0</bitOffset>
  13751. <bitWidth>1</bitWidth>
  13752. </field>
  13753. </fields>
  13754. </register>
  13755. <register>
  13756. <name>BRR</name>
  13757. <displayName>BRR</displayName>
  13758. <description>Baud rate register</description>
  13759. <addressOffset>0xC</addressOffset>
  13760. <size>0x20</size>
  13761. <access>read-write</access>
  13762. <resetValue>0x0000</resetValue>
  13763. <fields>
  13764. <field>
  13765. <name>BRR</name>
  13766. <description>BRR</description>
  13767. <bitOffset>0</bitOffset>
  13768. <bitWidth>20</bitWidth>
  13769. </field>
  13770. </fields>
  13771. </register>
  13772. <register>
  13773. <name>RQR</name>
  13774. <displayName>RQR</displayName>
  13775. <description>Request register</description>
  13776. <addressOffset>0x18</addressOffset>
  13777. <size>0x20</size>
  13778. <access>write-only</access>
  13779. <resetValue>0x0000</resetValue>
  13780. <fields>
  13781. <field>
  13782. <name>RXFRQ</name>
  13783. <description>Receive data flush request</description>
  13784. <bitOffset>3</bitOffset>
  13785. <bitWidth>1</bitWidth>
  13786. </field>
  13787. <field>
  13788. <name>MMRQ</name>
  13789. <description>Mute mode request</description>
  13790. <bitOffset>2</bitOffset>
  13791. <bitWidth>1</bitWidth>
  13792. </field>
  13793. <field>
  13794. <name>SBKRQ</name>
  13795. <description>Send break request</description>
  13796. <bitOffset>1</bitOffset>
  13797. <bitWidth>1</bitWidth>
  13798. </field>
  13799. </fields>
  13800. </register>
  13801. <register>
  13802. <name>ISR</name>
  13803. <displayName>ISR</displayName>
  13804. <description>Interrupt &amp; status register</description>
  13805. <addressOffset>0x1C</addressOffset>
  13806. <size>0x20</size>
  13807. <access>read-only</access>
  13808. <resetValue>0x00C0</resetValue>
  13809. <fields>
  13810. <field>
  13811. <name>REACK</name>
  13812. <description>REACK</description>
  13813. <bitOffset>22</bitOffset>
  13814. <bitWidth>1</bitWidth>
  13815. </field>
  13816. <field>
  13817. <name>TEACK</name>
  13818. <description>TEACK</description>
  13819. <bitOffset>21</bitOffset>
  13820. <bitWidth>1</bitWidth>
  13821. </field>
  13822. <field>
  13823. <name>WUF</name>
  13824. <description>WUF</description>
  13825. <bitOffset>20</bitOffset>
  13826. <bitWidth>1</bitWidth>
  13827. </field>
  13828. <field>
  13829. <name>RWU</name>
  13830. <description>RWU</description>
  13831. <bitOffset>19</bitOffset>
  13832. <bitWidth>1</bitWidth>
  13833. </field>
  13834. <field>
  13835. <name>SBKF</name>
  13836. <description>SBKF</description>
  13837. <bitOffset>18</bitOffset>
  13838. <bitWidth>1</bitWidth>
  13839. </field>
  13840. <field>
  13841. <name>CMF</name>
  13842. <description>CMF</description>
  13843. <bitOffset>17</bitOffset>
  13844. <bitWidth>1</bitWidth>
  13845. </field>
  13846. <field>
  13847. <name>BUSY</name>
  13848. <description>BUSY</description>
  13849. <bitOffset>16</bitOffset>
  13850. <bitWidth>1</bitWidth>
  13851. </field>
  13852. <field>
  13853. <name>CTS</name>
  13854. <description>CTS</description>
  13855. <bitOffset>10</bitOffset>
  13856. <bitWidth>1</bitWidth>
  13857. </field>
  13858. <field>
  13859. <name>CTSIF</name>
  13860. <description>CTSIF</description>
  13861. <bitOffset>9</bitOffset>
  13862. <bitWidth>1</bitWidth>
  13863. </field>
  13864. <field>
  13865. <name>TXE</name>
  13866. <description>TXE</description>
  13867. <bitOffset>7</bitOffset>
  13868. <bitWidth>1</bitWidth>
  13869. </field>
  13870. <field>
  13871. <name>TC</name>
  13872. <description>TC</description>
  13873. <bitOffset>6</bitOffset>
  13874. <bitWidth>1</bitWidth>
  13875. </field>
  13876. <field>
  13877. <name>RXNE</name>
  13878. <description>RXNE</description>
  13879. <bitOffset>5</bitOffset>
  13880. <bitWidth>1</bitWidth>
  13881. </field>
  13882. <field>
  13883. <name>IDLE</name>
  13884. <description>IDLE</description>
  13885. <bitOffset>4</bitOffset>
  13886. <bitWidth>1</bitWidth>
  13887. </field>
  13888. <field>
  13889. <name>ORE</name>
  13890. <description>ORE</description>
  13891. <bitOffset>3</bitOffset>
  13892. <bitWidth>1</bitWidth>
  13893. </field>
  13894. <field>
  13895. <name>NF</name>
  13896. <description>NF</description>
  13897. <bitOffset>2</bitOffset>
  13898. <bitWidth>1</bitWidth>
  13899. </field>
  13900. <field>
  13901. <name>FE</name>
  13902. <description>FE</description>
  13903. <bitOffset>1</bitOffset>
  13904. <bitWidth>1</bitWidth>
  13905. </field>
  13906. <field>
  13907. <name>PE</name>
  13908. <description>PE</description>
  13909. <bitOffset>0</bitOffset>
  13910. <bitWidth>1</bitWidth>
  13911. </field>
  13912. </fields>
  13913. </register>
  13914. <register>
  13915. <name>ICR</name>
  13916. <displayName>ICR</displayName>
  13917. <description>Interrupt flag clear register</description>
  13918. <addressOffset>0x20</addressOffset>
  13919. <size>0x20</size>
  13920. <access>write-only</access>
  13921. <resetValue>0x0000</resetValue>
  13922. <fields>
  13923. <field>
  13924. <name>WUCF</name>
  13925. <description>Wakeup from Stop mode clear flag</description>
  13926. <bitOffset>20</bitOffset>
  13927. <bitWidth>1</bitWidth>
  13928. </field>
  13929. <field>
  13930. <name>CMCF</name>
  13931. <description>Character match clear flag</description>
  13932. <bitOffset>17</bitOffset>
  13933. <bitWidth>1</bitWidth>
  13934. </field>
  13935. <field>
  13936. <name>CTSCF</name>
  13937. <description>CTS clear flag</description>
  13938. <bitOffset>9</bitOffset>
  13939. <bitWidth>1</bitWidth>
  13940. </field>
  13941. <field>
  13942. <name>TCCF</name>
  13943. <description>Transmission complete clear flag</description>
  13944. <bitOffset>6</bitOffset>
  13945. <bitWidth>1</bitWidth>
  13946. </field>
  13947. <field>
  13948. <name>IDLECF</name>
  13949. <description>Idle line detected clear flag</description>
  13950. <bitOffset>4</bitOffset>
  13951. <bitWidth>1</bitWidth>
  13952. </field>
  13953. <field>
  13954. <name>ORECF</name>
  13955. <description>Overrun error clear flag</description>
  13956. <bitOffset>3</bitOffset>
  13957. <bitWidth>1</bitWidth>
  13958. </field>
  13959. <field>
  13960. <name>NCF</name>
  13961. <description>Noise detected clear flag</description>
  13962. <bitOffset>2</bitOffset>
  13963. <bitWidth>1</bitWidth>
  13964. </field>
  13965. <field>
  13966. <name>FECF</name>
  13967. <description>Framing error clear flag</description>
  13968. <bitOffset>1</bitOffset>
  13969. <bitWidth>1</bitWidth>
  13970. </field>
  13971. <field>
  13972. <name>PECF</name>
  13973. <description>Parity error clear flag</description>
  13974. <bitOffset>0</bitOffset>
  13975. <bitWidth>1</bitWidth>
  13976. </field>
  13977. </fields>
  13978. </register>
  13979. <register>
  13980. <name>RDR</name>
  13981. <displayName>RDR</displayName>
  13982. <description>Receive data register</description>
  13983. <addressOffset>0x24</addressOffset>
  13984. <size>0x20</size>
  13985. <access>read-only</access>
  13986. <resetValue>0x0000</resetValue>
  13987. <fields>
  13988. <field>
  13989. <name>RDR</name>
  13990. <description>Receive data value</description>
  13991. <bitOffset>0</bitOffset>
  13992. <bitWidth>9</bitWidth>
  13993. </field>
  13994. </fields>
  13995. </register>
  13996. <register>
  13997. <name>TDR</name>
  13998. <displayName>TDR</displayName>
  13999. <description>Transmit data register</description>
  14000. <addressOffset>0x28</addressOffset>
  14001. <size>0x20</size>
  14002. <access>read-write</access>
  14003. <resetValue>0x0000</resetValue>
  14004. <fields>
  14005. <field>
  14006. <name>TDR</name>
  14007. <description>Transmit data value</description>
  14008. <bitOffset>0</bitOffset>
  14009. <bitWidth>9</bitWidth>
  14010. </field>
  14011. </fields>
  14012. </register>
  14013. </registers>
  14014. </peripheral>
  14015. <peripheral>
  14016. <name>NVIC</name>
  14017. <description>Nested Vectored Interrupt Controller</description>
  14018. <groupName>NVIC</groupName>
  14019. <baseAddress>0xE000E100</baseAddress>
  14020. <addressBlock>
  14021. <offset>0x0</offset>
  14022. <size>0x33D</size>
  14023. <usage>registers</usage>
  14024. </addressBlock>
  14025. <interrupt>
  14026. <name>LPUART1</name>
  14027. <description>LPUART1 global interrupt through</description>
  14028. <value>29</value>
  14029. </interrupt>
  14030. <registers>
  14031. <register>
  14032. <name>ISER</name>
  14033. <displayName>ISER</displayName>
  14034. <description>Interrupt Set Enable Register</description>
  14035. <addressOffset>0x0</addressOffset>
  14036. <size>0x20</size>
  14037. <access>read-write</access>
  14038. <resetValue>0x00000000</resetValue>
  14039. <fields>
  14040. <field>
  14041. <name>SETENA</name>
  14042. <description>SETENA</description>
  14043. <bitOffset>0</bitOffset>
  14044. <bitWidth>32</bitWidth>
  14045. </field>
  14046. </fields>
  14047. </register>
  14048. <register>
  14049. <name>ICER</name>
  14050. <displayName>ICER</displayName>
  14051. <description>Interrupt Clear Enable Register</description>
  14052. <addressOffset>0x80</addressOffset>
  14053. <size>0x20</size>
  14054. <access>read-write</access>
  14055. <resetValue>0x00000000</resetValue>
  14056. <fields>
  14057. <field>
  14058. <name>CLRENA</name>
  14059. <description>CLRENA</description>
  14060. <bitOffset>0</bitOffset>
  14061. <bitWidth>32</bitWidth>
  14062. </field>
  14063. </fields>
  14064. </register>
  14065. <register>
  14066. <name>ISPR</name>
  14067. <displayName>ISPR</displayName>
  14068. <description>Interrupt Set-Pending Register</description>
  14069. <addressOffset>0x100</addressOffset>
  14070. <size>0x20</size>
  14071. <access>read-write</access>
  14072. <resetValue>0x00000000</resetValue>
  14073. <fields>
  14074. <field>
  14075. <name>SETPEND</name>
  14076. <description>SETPEND</description>
  14077. <bitOffset>0</bitOffset>
  14078. <bitWidth>32</bitWidth>
  14079. </field>
  14080. </fields>
  14081. </register>
  14082. <register>
  14083. <name>ICPR</name>
  14084. <displayName>ICPR</displayName>
  14085. <description>Interrupt Clear-Pending Register</description>
  14086. <addressOffset>0x180</addressOffset>
  14087. <size>0x20</size>
  14088. <access>read-write</access>
  14089. <resetValue>0x00000000</resetValue>
  14090. <fields>
  14091. <field>
  14092. <name>CLRPEND</name>
  14093. <description>CLRPEND</description>
  14094. <bitOffset>0</bitOffset>
  14095. <bitWidth>32</bitWidth>
  14096. </field>
  14097. </fields>
  14098. </register>
  14099. <register>
  14100. <name>IPR0</name>
  14101. <displayName>IPR0</displayName>
  14102. <description>Interrupt Priority Register 0</description>
  14103. <addressOffset>0x300</addressOffset>
  14104. <size>0x20</size>
  14105. <access>read-write</access>
  14106. <resetValue>0x00000000</resetValue>
  14107. <fields>
  14108. <field>
  14109. <name>PRI_0</name>
  14110. <description>priority for interrupt 0</description>
  14111. <bitOffset>0</bitOffset>
  14112. <bitWidth>8</bitWidth>
  14113. </field>
  14114. <field>
  14115. <name>PRI_1</name>
  14116. <description>priority for interrupt 1</description>
  14117. <bitOffset>8</bitOffset>
  14118. <bitWidth>8</bitWidth>
  14119. </field>
  14120. <field>
  14121. <name>PRI_2</name>
  14122. <description>priority for interrupt 2</description>
  14123. <bitOffset>16</bitOffset>
  14124. <bitWidth>8</bitWidth>
  14125. </field>
  14126. <field>
  14127. <name>PRI_3</name>
  14128. <description>priority for interrupt 3</description>
  14129. <bitOffset>24</bitOffset>
  14130. <bitWidth>8</bitWidth>
  14131. </field>
  14132. </fields>
  14133. </register>
  14134. <register>
  14135. <name>IPR1</name>
  14136. <displayName>IPR1</displayName>
  14137. <description>Interrupt Priority Register 1</description>
  14138. <addressOffset>0x304</addressOffset>
  14139. <size>0x20</size>
  14140. <access>read-write</access>
  14141. <resetValue>0x00000000</resetValue>
  14142. <fields>
  14143. <field>
  14144. <name>PRI_4</name>
  14145. <description>priority for interrupt n</description>
  14146. <bitOffset>0</bitOffset>
  14147. <bitWidth>8</bitWidth>
  14148. </field>
  14149. <field>
  14150. <name>PRI_5</name>
  14151. <description>priority for interrupt n</description>
  14152. <bitOffset>8</bitOffset>
  14153. <bitWidth>8</bitWidth>
  14154. </field>
  14155. <field>
  14156. <name>PRI_6</name>
  14157. <description>priority for interrupt n</description>
  14158. <bitOffset>16</bitOffset>
  14159. <bitWidth>8</bitWidth>
  14160. </field>
  14161. <field>
  14162. <name>PRI_7</name>
  14163. <description>priority for interrupt n</description>
  14164. <bitOffset>24</bitOffset>
  14165. <bitWidth>8</bitWidth>
  14166. </field>
  14167. </fields>
  14168. </register>
  14169. <register>
  14170. <name>IPR2</name>
  14171. <displayName>IPR2</displayName>
  14172. <description>Interrupt Priority Register 2</description>
  14173. <addressOffset>0x308</addressOffset>
  14174. <size>0x20</size>
  14175. <access>read-write</access>
  14176. <resetValue>0x00000000</resetValue>
  14177. <fields>
  14178. <field>
  14179. <name>PRI_8</name>
  14180. <description>priority for interrupt n</description>
  14181. <bitOffset>0</bitOffset>
  14182. <bitWidth>8</bitWidth>
  14183. </field>
  14184. <field>
  14185. <name>PRI_9</name>
  14186. <description>priority for interrupt n</description>
  14187. <bitOffset>8</bitOffset>
  14188. <bitWidth>8</bitWidth>
  14189. </field>
  14190. <field>
  14191. <name>PRI_10</name>
  14192. <description>priority for interrupt n</description>
  14193. <bitOffset>16</bitOffset>
  14194. <bitWidth>8</bitWidth>
  14195. </field>
  14196. <field>
  14197. <name>PRI_11</name>
  14198. <description>priority for interrupt n</description>
  14199. <bitOffset>24</bitOffset>
  14200. <bitWidth>8</bitWidth>
  14201. </field>
  14202. </fields>
  14203. </register>
  14204. <register>
  14205. <name>IPR3</name>
  14206. <displayName>IPR3</displayName>
  14207. <description>Interrupt Priority Register 3</description>
  14208. <addressOffset>0x30C</addressOffset>
  14209. <size>0x20</size>
  14210. <access>read-write</access>
  14211. <resetValue>0x00000000</resetValue>
  14212. <fields>
  14213. <field>
  14214. <name>PRI_12</name>
  14215. <description>priority for interrupt n</description>
  14216. <bitOffset>0</bitOffset>
  14217. <bitWidth>8</bitWidth>
  14218. </field>
  14219. <field>
  14220. <name>PRI_13</name>
  14221. <description>priority for interrupt n</description>
  14222. <bitOffset>8</bitOffset>
  14223. <bitWidth>8</bitWidth>
  14224. </field>
  14225. <field>
  14226. <name>PRI_14</name>
  14227. <description>priority for interrupt n</description>
  14228. <bitOffset>16</bitOffset>
  14229. <bitWidth>8</bitWidth>
  14230. </field>
  14231. <field>
  14232. <name>PRI_15</name>
  14233. <description>priority for interrupt n</description>
  14234. <bitOffset>24</bitOffset>
  14235. <bitWidth>8</bitWidth>
  14236. </field>
  14237. </fields>
  14238. </register>
  14239. <register>
  14240. <name>IPR4</name>
  14241. <displayName>IPR4</displayName>
  14242. <description>Interrupt Priority Register 4</description>
  14243. <addressOffset>0x310</addressOffset>
  14244. <size>0x20</size>
  14245. <access>read-write</access>
  14246. <resetValue>0x00000000</resetValue>
  14247. <fields>
  14248. <field>
  14249. <name>PRI_16</name>
  14250. <description>priority for interrupt n</description>
  14251. <bitOffset>0</bitOffset>
  14252. <bitWidth>8</bitWidth>
  14253. </field>
  14254. <field>
  14255. <name>PRI_17</name>
  14256. <description>priority for interrupt n</description>
  14257. <bitOffset>8</bitOffset>
  14258. <bitWidth>8</bitWidth>
  14259. </field>
  14260. <field>
  14261. <name>PRI_18</name>
  14262. <description>priority for interrupt n</description>
  14263. <bitOffset>16</bitOffset>
  14264. <bitWidth>8</bitWidth>
  14265. </field>
  14266. <field>
  14267. <name>PRI_19</name>
  14268. <description>priority for interrupt n</description>
  14269. <bitOffset>24</bitOffset>
  14270. <bitWidth>8</bitWidth>
  14271. </field>
  14272. </fields>
  14273. </register>
  14274. <register>
  14275. <name>IPR5</name>
  14276. <displayName>IPR5</displayName>
  14277. <description>Interrupt Priority Register 5</description>
  14278. <addressOffset>0x314</addressOffset>
  14279. <size>0x20</size>
  14280. <access>read-write</access>
  14281. <resetValue>0x00000000</resetValue>
  14282. <fields>
  14283. <field>
  14284. <name>PRI_20</name>
  14285. <description>priority for interrupt n</description>
  14286. <bitOffset>0</bitOffset>
  14287. <bitWidth>8</bitWidth>
  14288. </field>
  14289. <field>
  14290. <name>PRI_21</name>
  14291. <description>priority for interrupt n</description>
  14292. <bitOffset>8</bitOffset>
  14293. <bitWidth>8</bitWidth>
  14294. </field>
  14295. <field>
  14296. <name>PRI_22</name>
  14297. <description>priority for interrupt n</description>
  14298. <bitOffset>16</bitOffset>
  14299. <bitWidth>8</bitWidth>
  14300. </field>
  14301. <field>
  14302. <name>PRI_23</name>
  14303. <description>priority for interrupt n</description>
  14304. <bitOffset>24</bitOffset>
  14305. <bitWidth>8</bitWidth>
  14306. </field>
  14307. </fields>
  14308. </register>
  14309. <register>
  14310. <name>IPR6</name>
  14311. <displayName>IPR6</displayName>
  14312. <description>Interrupt Priority Register 6</description>
  14313. <addressOffset>0x318</addressOffset>
  14314. <size>0x20</size>
  14315. <access>read-write</access>
  14316. <resetValue>0x00000000</resetValue>
  14317. <fields>
  14318. <field>
  14319. <name>PRI_24</name>
  14320. <description>priority for interrupt n</description>
  14321. <bitOffset>0</bitOffset>
  14322. <bitWidth>8</bitWidth>
  14323. </field>
  14324. <field>
  14325. <name>PRI_25</name>
  14326. <description>priority for interrupt n</description>
  14327. <bitOffset>8</bitOffset>
  14328. <bitWidth>8</bitWidth>
  14329. </field>
  14330. <field>
  14331. <name>PRI_26</name>
  14332. <description>priority for interrupt n</description>
  14333. <bitOffset>16</bitOffset>
  14334. <bitWidth>8</bitWidth>
  14335. </field>
  14336. <field>
  14337. <name>PRI_27</name>
  14338. <description>priority for interrupt n</description>
  14339. <bitOffset>24</bitOffset>
  14340. <bitWidth>8</bitWidth>
  14341. </field>
  14342. </fields>
  14343. </register>
  14344. <register>
  14345. <name>IPR7</name>
  14346. <displayName>IPR7</displayName>
  14347. <description>Interrupt Priority Register 7</description>
  14348. <addressOffset>0x31C</addressOffset>
  14349. <size>0x20</size>
  14350. <access>read-write</access>
  14351. <resetValue>0x00000000</resetValue>
  14352. <fields>
  14353. <field>
  14354. <name>PRI_28</name>
  14355. <description>priority for interrupt n</description>
  14356. <bitOffset>0</bitOffset>
  14357. <bitWidth>8</bitWidth>
  14358. </field>
  14359. <field>
  14360. <name>PRI_29</name>
  14361. <description>priority for interrupt n</description>
  14362. <bitOffset>8</bitOffset>
  14363. <bitWidth>8</bitWidth>
  14364. </field>
  14365. <field>
  14366. <name>PRI_30</name>
  14367. <description>priority for interrupt n</description>
  14368. <bitOffset>16</bitOffset>
  14369. <bitWidth>8</bitWidth>
  14370. </field>
  14371. <field>
  14372. <name>PRI_31</name>
  14373. <description>priority for interrupt n</description>
  14374. <bitOffset>24</bitOffset>
  14375. <bitWidth>8</bitWidth>
  14376. </field>
  14377. </fields>
  14378. </register>
  14379. </registers>
  14380. </peripheral>
  14381. <peripheral>
  14382. <name>MPU</name>
  14383. <description>Memory protection unit</description>
  14384. <groupName>MPU</groupName>
  14385. <baseAddress>0xE000ED90</baseAddress>
  14386. <addressBlock>
  14387. <offset>0x0</offset>
  14388. <size>0x15</size>
  14389. <usage>registers</usage>
  14390. </addressBlock>
  14391. <registers>
  14392. <register>
  14393. <name>MPU_TYPER</name>
  14394. <displayName>MPU_TYPER</displayName>
  14395. <description>MPU type register</description>
  14396. <addressOffset>0x0</addressOffset>
  14397. <size>0x20</size>
  14398. <access>read-only</access>
  14399. <resetValue>0X00000800</resetValue>
  14400. <fields>
  14401. <field>
  14402. <name>SEPARATE</name>
  14403. <description>Separate flag</description>
  14404. <bitOffset>0</bitOffset>
  14405. <bitWidth>1</bitWidth>
  14406. </field>
  14407. <field>
  14408. <name>DREGION</name>
  14409. <description>Number of MPU data regions</description>
  14410. <bitOffset>8</bitOffset>
  14411. <bitWidth>8</bitWidth>
  14412. </field>
  14413. <field>
  14414. <name>IREGION</name>
  14415. <description>Number of MPU instruction regions</description>
  14416. <bitOffset>16</bitOffset>
  14417. <bitWidth>8</bitWidth>
  14418. </field>
  14419. </fields>
  14420. </register>
  14421. <register>
  14422. <name>MPU_CTRL</name>
  14423. <displayName>MPU_CTRL</displayName>
  14424. <description>MPU control register</description>
  14425. <addressOffset>0x4</addressOffset>
  14426. <size>0x20</size>
  14427. <access>read-only</access>
  14428. <resetValue>0X00000000</resetValue>
  14429. <fields>
  14430. <field>
  14431. <name>ENABLE</name>
  14432. <description>Enables the MPU</description>
  14433. <bitOffset>0</bitOffset>
  14434. <bitWidth>1</bitWidth>
  14435. </field>
  14436. <field>
  14437. <name>HFNMIENA</name>
  14438. <description>Enables the operation of MPU during hard fault</description>
  14439. <bitOffset>1</bitOffset>
  14440. <bitWidth>1</bitWidth>
  14441. </field>
  14442. <field>
  14443. <name>PRIVDEFENA</name>
  14444. <description>Enable priviliged software access to default memory map</description>
  14445. <bitOffset>2</bitOffset>
  14446. <bitWidth>1</bitWidth>
  14447. </field>
  14448. </fields>
  14449. </register>
  14450. <register>
  14451. <name>MPU_RNR</name>
  14452. <displayName>MPU_RNR</displayName>
  14453. <description>MPU region number register</description>
  14454. <addressOffset>0x8</addressOffset>
  14455. <size>0x20</size>
  14456. <access>read-write</access>
  14457. <resetValue>0X00000000</resetValue>
  14458. <fields>
  14459. <field>
  14460. <name>REGION</name>
  14461. <description>MPU region</description>
  14462. <bitOffset>0</bitOffset>
  14463. <bitWidth>8</bitWidth>
  14464. </field>
  14465. </fields>
  14466. </register>
  14467. <register>
  14468. <name>MPU_RBAR</name>
  14469. <displayName>MPU_RBAR</displayName>
  14470. <description>MPU region base address register</description>
  14471. <addressOffset>0xC</addressOffset>
  14472. <size>0x20</size>
  14473. <access>read-write</access>
  14474. <resetValue>0X00000000</resetValue>
  14475. <fields>
  14476. <field>
  14477. <name>REGION</name>
  14478. <description>MPU region field</description>
  14479. <bitOffset>0</bitOffset>
  14480. <bitWidth>4</bitWidth>
  14481. </field>
  14482. <field>
  14483. <name>VALID</name>
  14484. <description>MPU region number valid</description>
  14485. <bitOffset>4</bitOffset>
  14486. <bitWidth>1</bitWidth>
  14487. </field>
  14488. <field>
  14489. <name>ADDR</name>
  14490. <description>Region base address field</description>
  14491. <bitOffset>5</bitOffset>
  14492. <bitWidth>27</bitWidth>
  14493. </field>
  14494. </fields>
  14495. </register>
  14496. <register>
  14497. <name>MPU_RASR</name>
  14498. <displayName>MPU_RASR</displayName>
  14499. <description>MPU region attribute and size register</description>
  14500. <addressOffset>0x10</addressOffset>
  14501. <size>0x20</size>
  14502. <access>read-write</access>
  14503. <resetValue>0X00000000</resetValue>
  14504. <fields>
  14505. <field>
  14506. <name>ENABLE</name>
  14507. <description>Region enable bit.</description>
  14508. <bitOffset>0</bitOffset>
  14509. <bitWidth>1</bitWidth>
  14510. </field>
  14511. <field>
  14512. <name>SIZE</name>
  14513. <description>Size of the MPU protection region</description>
  14514. <bitOffset>1</bitOffset>
  14515. <bitWidth>5</bitWidth>
  14516. </field>
  14517. <field>
  14518. <name>SRD</name>
  14519. <description>Subregion disable bits</description>
  14520. <bitOffset>8</bitOffset>
  14521. <bitWidth>8</bitWidth>
  14522. </field>
  14523. <field>
  14524. <name>B</name>
  14525. <description>memory attribute</description>
  14526. <bitOffset>16</bitOffset>
  14527. <bitWidth>1</bitWidth>
  14528. </field>
  14529. <field>
  14530. <name>C</name>
  14531. <description>memory attribute</description>
  14532. <bitOffset>17</bitOffset>
  14533. <bitWidth>1</bitWidth>
  14534. </field>
  14535. <field>
  14536. <name>S</name>
  14537. <description>Shareable memory attribute</description>
  14538. <bitOffset>18</bitOffset>
  14539. <bitWidth>1</bitWidth>
  14540. </field>
  14541. <field>
  14542. <name>TEX</name>
  14543. <description>memory attribute</description>
  14544. <bitOffset>19</bitOffset>
  14545. <bitWidth>3</bitWidth>
  14546. </field>
  14547. <field>
  14548. <name>AP</name>
  14549. <description>Access permission</description>
  14550. <bitOffset>24</bitOffset>
  14551. <bitWidth>3</bitWidth>
  14552. </field>
  14553. <field>
  14554. <name>XN</name>
  14555. <description>Instruction access disable bit</description>
  14556. <bitOffset>28</bitOffset>
  14557. <bitWidth>1</bitWidth>
  14558. </field>
  14559. </fields>
  14560. </register>
  14561. </registers>
  14562. </peripheral>
  14563. <peripheral>
  14564. <name>STK</name>
  14565. <description>SysTick timer</description>
  14566. <groupName>STK</groupName>
  14567. <baseAddress>0xE000E010</baseAddress>
  14568. <addressBlock>
  14569. <offset>0x0</offset>
  14570. <size>0x11</size>
  14571. <usage>registers</usage>
  14572. </addressBlock>
  14573. <registers>
  14574. <register>
  14575. <name>CSR</name>
  14576. <displayName>CSR</displayName>
  14577. <description>SysTick control and status register</description>
  14578. <addressOffset>0x0</addressOffset>
  14579. <size>0x20</size>
  14580. <access>read-write</access>
  14581. <resetValue>0X00000000</resetValue>
  14582. <fields>
  14583. <field>
  14584. <name>ENABLE</name>
  14585. <description>Counter enable</description>
  14586. <bitOffset>0</bitOffset>
  14587. <bitWidth>1</bitWidth>
  14588. </field>
  14589. <field>
  14590. <name>TICKINT</name>
  14591. <description>SysTick exception request enable</description>
  14592. <bitOffset>1</bitOffset>
  14593. <bitWidth>1</bitWidth>
  14594. </field>
  14595. <field>
  14596. <name>CLKSOURCE</name>
  14597. <description>Clock source selection</description>
  14598. <bitOffset>2</bitOffset>
  14599. <bitWidth>1</bitWidth>
  14600. </field>
  14601. <field>
  14602. <name>COUNTFLAG</name>
  14603. <description>COUNTFLAG</description>
  14604. <bitOffset>16</bitOffset>
  14605. <bitWidth>1</bitWidth>
  14606. </field>
  14607. </fields>
  14608. </register>
  14609. <register>
  14610. <name>RVR</name>
  14611. <displayName>RVR</displayName>
  14612. <description>SysTick reload value register</description>
  14613. <addressOffset>0x4</addressOffset>
  14614. <size>0x20</size>
  14615. <access>read-write</access>
  14616. <resetValue>0X00000000</resetValue>
  14617. <fields>
  14618. <field>
  14619. <name>RELOAD</name>
  14620. <description>RELOAD value</description>
  14621. <bitOffset>0</bitOffset>
  14622. <bitWidth>24</bitWidth>
  14623. </field>
  14624. </fields>
  14625. </register>
  14626. <register>
  14627. <name>CVR</name>
  14628. <displayName>CVR</displayName>
  14629. <description>SysTick current value register</description>
  14630. <addressOffset>0x8</addressOffset>
  14631. <size>0x20</size>
  14632. <access>read-write</access>
  14633. <resetValue>0X00000000</resetValue>
  14634. <fields>
  14635. <field>
  14636. <name>CURRENT</name>
  14637. <description>Current counter value</description>
  14638. <bitOffset>0</bitOffset>
  14639. <bitWidth>24</bitWidth>
  14640. </field>
  14641. </fields>
  14642. </register>
  14643. <register>
  14644. <name>CALIB</name>
  14645. <displayName>CALIB</displayName>
  14646. <description>SysTick calibration value register</description>
  14647. <addressOffset>0xC</addressOffset>
  14648. <size>0x20</size>
  14649. <access>read-write</access>
  14650. <resetValue>0X00000000</resetValue>
  14651. <fields>
  14652. <field>
  14653. <name>TENMS</name>
  14654. <description>Calibration value</description>
  14655. <bitOffset>0</bitOffset>
  14656. <bitWidth>24</bitWidth>
  14657. </field>
  14658. <field>
  14659. <name>SKEW</name>
  14660. <description>SKEW flag: Indicates whether the TENMS value is exact</description>
  14661. <bitOffset>30</bitOffset>
  14662. <bitWidth>1</bitWidth>
  14663. </field>
  14664. <field>
  14665. <name>NOREF</name>
  14666. <description>NOREF flag. Reads as zero</description>
  14667. <bitOffset>31</bitOffset>
  14668. <bitWidth>1</bitWidth>
  14669. </field>
  14670. </fields>
  14671. </register>
  14672. </registers>
  14673. </peripheral>
  14674. <peripheral>
  14675. <name>SCB</name>
  14676. <description>System control block</description>
  14677. <groupName>SCB</groupName>
  14678. <baseAddress>0xE000ED00</baseAddress>
  14679. <addressBlock>
  14680. <offset>0x0</offset>
  14681. <size>0x41</size>
  14682. <usage>registers</usage>
  14683. </addressBlock>
  14684. <registers>
  14685. <register>
  14686. <name>CPUID</name>
  14687. <displayName>CPUID</displayName>
  14688. <description>CPUID base register</description>
  14689. <addressOffset>0x0</addressOffset>
  14690. <size>0x20</size>
  14691. <access>read-only</access>
  14692. <resetValue>0x410FC241</resetValue>
  14693. <fields>
  14694. <field>
  14695. <name>Revision</name>
  14696. <description>Revision number</description>
  14697. <bitOffset>0</bitOffset>
  14698. <bitWidth>4</bitWidth>
  14699. </field>
  14700. <field>
  14701. <name>PartNo</name>
  14702. <description>Part number of the processor</description>
  14703. <bitOffset>4</bitOffset>
  14704. <bitWidth>12</bitWidth>
  14705. </field>
  14706. <field>
  14707. <name>Architecture</name>
  14708. <description>Reads as 0xF</description>
  14709. <bitOffset>16</bitOffset>
  14710. <bitWidth>4</bitWidth>
  14711. </field>
  14712. <field>
  14713. <name>Variant</name>
  14714. <description>Variant number</description>
  14715. <bitOffset>20</bitOffset>
  14716. <bitWidth>4</bitWidth>
  14717. </field>
  14718. <field>
  14719. <name>Implementer</name>
  14720. <description>Implementer code</description>
  14721. <bitOffset>24</bitOffset>
  14722. <bitWidth>8</bitWidth>
  14723. </field>
  14724. </fields>
  14725. </register>
  14726. <register>
  14727. <name>ICSR</name>
  14728. <displayName>ICSR</displayName>
  14729. <description>Interrupt control and state register</description>
  14730. <addressOffset>0x4</addressOffset>
  14731. <size>0x20</size>
  14732. <access>read-write</access>
  14733. <resetValue>0x00000000</resetValue>
  14734. <fields>
  14735. <field>
  14736. <name>VECTACTIVE</name>
  14737. <description>Active vector</description>
  14738. <bitOffset>0</bitOffset>
  14739. <bitWidth>9</bitWidth>
  14740. </field>
  14741. <field>
  14742. <name>RETTOBASE</name>
  14743. <description>Return to base level</description>
  14744. <bitOffset>11</bitOffset>
  14745. <bitWidth>1</bitWidth>
  14746. </field>
  14747. <field>
  14748. <name>VECTPENDING</name>
  14749. <description>Pending vector</description>
  14750. <bitOffset>12</bitOffset>
  14751. <bitWidth>7</bitWidth>
  14752. </field>
  14753. <field>
  14754. <name>ISRPENDING</name>
  14755. <description>Interrupt pending flag</description>
  14756. <bitOffset>22</bitOffset>
  14757. <bitWidth>1</bitWidth>
  14758. </field>
  14759. <field>
  14760. <name>PENDSTCLR</name>
  14761. <description>SysTick exception clear-pending bit</description>
  14762. <bitOffset>25</bitOffset>
  14763. <bitWidth>1</bitWidth>
  14764. </field>
  14765. <field>
  14766. <name>PENDSTSET</name>
  14767. <description>SysTick exception set-pending bit</description>
  14768. <bitOffset>26</bitOffset>
  14769. <bitWidth>1</bitWidth>
  14770. </field>
  14771. <field>
  14772. <name>PENDSVCLR</name>
  14773. <description>PendSV clear-pending bit</description>
  14774. <bitOffset>27</bitOffset>
  14775. <bitWidth>1</bitWidth>
  14776. </field>
  14777. <field>
  14778. <name>PENDSVSET</name>
  14779. <description>PendSV set-pending bit</description>
  14780. <bitOffset>28</bitOffset>
  14781. <bitWidth>1</bitWidth>
  14782. </field>
  14783. <field>
  14784. <name>NMIPENDSET</name>
  14785. <description>NMI set-pending bit.</description>
  14786. <bitOffset>31</bitOffset>
  14787. <bitWidth>1</bitWidth>
  14788. </field>
  14789. </fields>
  14790. </register>
  14791. <register>
  14792. <name>VTOR</name>
  14793. <displayName>VTOR</displayName>
  14794. <description>Vector table offset register</description>
  14795. <addressOffset>0x8</addressOffset>
  14796. <size>0x20</size>
  14797. <access>read-write</access>
  14798. <resetValue>0x00000000</resetValue>
  14799. <fields>
  14800. <field>
  14801. <name>TBLOFF</name>
  14802. <description>Vector table base offset field</description>
  14803. <bitOffset>7</bitOffset>
  14804. <bitWidth>25</bitWidth>
  14805. </field>
  14806. </fields>
  14807. </register>
  14808. <register>
  14809. <name>AIRCR</name>
  14810. <displayName>AIRCR</displayName>
  14811. <description>Application interrupt and reset control register</description>
  14812. <addressOffset>0xC</addressOffset>
  14813. <size>0x20</size>
  14814. <access>read-write</access>
  14815. <resetValue>0x00000000</resetValue>
  14816. <fields>
  14817. <field>
  14818. <name>VECTCLRACTIVE</name>
  14819. <description>VECTCLRACTIVE</description>
  14820. <bitOffset>1</bitOffset>
  14821. <bitWidth>1</bitWidth>
  14822. </field>
  14823. <field>
  14824. <name>SYSRESETREQ</name>
  14825. <description>SYSRESETREQ</description>
  14826. <bitOffset>2</bitOffset>
  14827. <bitWidth>1</bitWidth>
  14828. </field>
  14829. <field>
  14830. <name>ENDIANESS</name>
  14831. <description>ENDIANESS</description>
  14832. <bitOffset>15</bitOffset>
  14833. <bitWidth>1</bitWidth>
  14834. </field>
  14835. <field>
  14836. <name>VECTKEYSTAT</name>
  14837. <description>Register key</description>
  14838. <bitOffset>16</bitOffset>
  14839. <bitWidth>16</bitWidth>
  14840. </field>
  14841. </fields>
  14842. </register>
  14843. <register>
  14844. <name>SCR</name>
  14845. <displayName>SCR</displayName>
  14846. <description>System control register</description>
  14847. <addressOffset>0x10</addressOffset>
  14848. <size>0x20</size>
  14849. <access>read-write</access>
  14850. <resetValue>0x00000000</resetValue>
  14851. <fields>
  14852. <field>
  14853. <name>SLEEPONEXIT</name>
  14854. <description>SLEEPONEXIT</description>
  14855. <bitOffset>1</bitOffset>
  14856. <bitWidth>1</bitWidth>
  14857. </field>
  14858. <field>
  14859. <name>SLEEPDEEP</name>
  14860. <description>SLEEPDEEP</description>
  14861. <bitOffset>2</bitOffset>
  14862. <bitWidth>1</bitWidth>
  14863. </field>
  14864. <field>
  14865. <name>SEVEONPEND</name>
  14866. <description>Send Event on Pending bit</description>
  14867. <bitOffset>4</bitOffset>
  14868. <bitWidth>1</bitWidth>
  14869. </field>
  14870. </fields>
  14871. </register>
  14872. <register>
  14873. <name>CCR</name>
  14874. <displayName>CCR</displayName>
  14875. <description>Configuration and control register</description>
  14876. <addressOffset>0x14</addressOffset>
  14877. <size>0x20</size>
  14878. <access>read-write</access>
  14879. <resetValue>0x00000000</resetValue>
  14880. <fields>
  14881. <field>
  14882. <name>NONBASETHRDENA</name>
  14883. <description>Configures how the processor enters Thread mode</description>
  14884. <bitOffset>0</bitOffset>
  14885. <bitWidth>1</bitWidth>
  14886. </field>
  14887. <field>
  14888. <name>USERSETMPEND</name>
  14889. <description>USERSETMPEND</description>
  14890. <bitOffset>1</bitOffset>
  14891. <bitWidth>1</bitWidth>
  14892. </field>
  14893. <field>
  14894. <name>UNALIGN__TRP</name>
  14895. <description>UNALIGN_ TRP</description>
  14896. <bitOffset>3</bitOffset>
  14897. <bitWidth>1</bitWidth>
  14898. </field>
  14899. <field>
  14900. <name>DIV_0_TRP</name>
  14901. <description>DIV_0_TRP</description>
  14902. <bitOffset>4</bitOffset>
  14903. <bitWidth>1</bitWidth>
  14904. </field>
  14905. <field>
  14906. <name>BFHFNMIGN</name>
  14907. <description>BFHFNMIGN</description>
  14908. <bitOffset>8</bitOffset>
  14909. <bitWidth>1</bitWidth>
  14910. </field>
  14911. <field>
  14912. <name>STKALIGN</name>
  14913. <description>STKALIGN</description>
  14914. <bitOffset>9</bitOffset>
  14915. <bitWidth>1</bitWidth>
  14916. </field>
  14917. </fields>
  14918. </register>
  14919. <register>
  14920. <name>SHPR2</name>
  14921. <displayName>SHPR2</displayName>
  14922. <description>System handler priority registers</description>
  14923. <addressOffset>0x1C</addressOffset>
  14924. <size>0x20</size>
  14925. <access>read-write</access>
  14926. <resetValue>0x00000000</resetValue>
  14927. <fields>
  14928. <field>
  14929. <name>PRI_11</name>
  14930. <description>Priority of system handler 11</description>
  14931. <bitOffset>24</bitOffset>
  14932. <bitWidth>8</bitWidth>
  14933. </field>
  14934. </fields>
  14935. </register>
  14936. <register>
  14937. <name>SHPR3</name>
  14938. <displayName>SHPR3</displayName>
  14939. <description>System handler priority registers</description>
  14940. <addressOffset>0x20</addressOffset>
  14941. <size>0x20</size>
  14942. <access>read-write</access>
  14943. <resetValue>0x00000000</resetValue>
  14944. <fields>
  14945. <field>
  14946. <name>PRI_14</name>
  14947. <description>Priority of system handler 14</description>
  14948. <bitOffset>16</bitOffset>
  14949. <bitWidth>8</bitWidth>
  14950. </field>
  14951. <field>
  14952. <name>PRI_15</name>
  14953. <description>Priority of system handler 15</description>
  14954. <bitOffset>24</bitOffset>
  14955. <bitWidth>8</bitWidth>
  14956. </field>
  14957. </fields>
  14958. </register>
  14959. </registers>
  14960. </peripheral>
  14961. </peripherals>
  14962. </device>