STM32L0x1.svd 529 KB

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  1. <?xml version="1.0" encoding="utf-8" standalone="no"?>
  2. <device schemaVersion="1.1"
  3. xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
  4. xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
  5. <name>STM32L0x1</name>
  6. <version>1.0</version>
  7. <description>STM32L0x1</description>
  8. <!--Bus Interface Properties-->
  9. <!--Cortex-M3 is byte addressable-->
  10. <addressUnitBits>8</addressUnitBits>
  11. <!--the maximum data bit width accessible within a single transfer-->
  12. <width>32</width>
  13. <!--Register Default Properties-->
  14. <size>0x20</size>
  15. <resetValue>0x0</resetValue>
  16. <resetMask>0xFFFFFFFF</resetMask>
  17. <peripherals>
  18. <peripheral>
  19. <name>AES</name>
  20. <description>Advanced encryption standard hardware
  21. accelerator</description>
  22. <groupName>AES</groupName>
  23. <baseAddress>0x40026000</baseAddress>
  24. <addressBlock>
  25. <offset>0x0</offset>
  26. <size>0x400</size>
  27. <usage>registers</usage>
  28. </addressBlock>
  29. <interrupt>
  30. <name>AES_RNG_LPUART1</name>
  31. <description>AES global interrupt RNG global interrupt and
  32. LPUART1 global interrupt through</description>
  33. <value>29</value>
  34. </interrupt>
  35. <registers>
  36. <register>
  37. <name>CR</name>
  38. <displayName>CR</displayName>
  39. <description>control register</description>
  40. <addressOffset>0x0</addressOffset>
  41. <size>0x20</size>
  42. <access>read-write</access>
  43. <resetValue>0x00000000</resetValue>
  44. <fields>
  45. <field>
  46. <name>DMAOUTEN</name>
  47. <description>Enable DMA management of data output
  48. phase</description>
  49. <bitOffset>12</bitOffset>
  50. <bitWidth>1</bitWidth>
  51. </field>
  52. <field>
  53. <name>DMAINEN</name>
  54. <description>Enable DMA management of data input
  55. phase</description>
  56. <bitOffset>11</bitOffset>
  57. <bitWidth>1</bitWidth>
  58. </field>
  59. <field>
  60. <name>ERRIE</name>
  61. <description>Error interrupt enable</description>
  62. <bitOffset>10</bitOffset>
  63. <bitWidth>1</bitWidth>
  64. </field>
  65. <field>
  66. <name>CCFIE</name>
  67. <description>CCF flag interrupt enable</description>
  68. <bitOffset>9</bitOffset>
  69. <bitWidth>1</bitWidth>
  70. </field>
  71. <field>
  72. <name>ERRC</name>
  73. <description>Error clear</description>
  74. <bitOffset>8</bitOffset>
  75. <bitWidth>1</bitWidth>
  76. </field>
  77. <field>
  78. <name>CCFC</name>
  79. <description>Computation Complete Flag
  80. Clear</description>
  81. <bitOffset>7</bitOffset>
  82. <bitWidth>1</bitWidth>
  83. </field>
  84. <field>
  85. <name>CHMOD</name>
  86. <description>AES chaining mode</description>
  87. <bitOffset>5</bitOffset>
  88. <bitWidth>2</bitWidth>
  89. </field>
  90. <field>
  91. <name>MODE</name>
  92. <description>AES operating mode</description>
  93. <bitOffset>3</bitOffset>
  94. <bitWidth>2</bitWidth>
  95. </field>
  96. <field>
  97. <name>DATATYPE</name>
  98. <description>Data type selection (for data in and
  99. data out to/from the cryptographic
  100. block)</description>
  101. <bitOffset>1</bitOffset>
  102. <bitWidth>2</bitWidth>
  103. </field>
  104. <field>
  105. <name>EN</name>
  106. <description>AES enable</description>
  107. <bitOffset>0</bitOffset>
  108. <bitWidth>1</bitWidth>
  109. </field>
  110. </fields>
  111. </register>
  112. <register>
  113. <name>SR</name>
  114. <displayName>SR</displayName>
  115. <description>status register</description>
  116. <addressOffset>0x4</addressOffset>
  117. <size>0x20</size>
  118. <access>read-only</access>
  119. <resetValue>0x00000000</resetValue>
  120. <fields>
  121. <field>
  122. <name>WRERR</name>
  123. <description>Write error flag</description>
  124. <bitOffset>2</bitOffset>
  125. <bitWidth>1</bitWidth>
  126. </field>
  127. <field>
  128. <name>RDERR</name>
  129. <description>Read error flag</description>
  130. <bitOffset>1</bitOffset>
  131. <bitWidth>1</bitWidth>
  132. </field>
  133. <field>
  134. <name>CCF</name>
  135. <description>Computation complete flag</description>
  136. <bitOffset>0</bitOffset>
  137. <bitWidth>1</bitWidth>
  138. </field>
  139. </fields>
  140. </register>
  141. <register>
  142. <name>DINR</name>
  143. <displayName>DINR</displayName>
  144. <description>data input register</description>
  145. <addressOffset>0x8</addressOffset>
  146. <size>0x20</size>
  147. <access>read-write</access>
  148. <resetValue>0x00000000</resetValue>
  149. <fields>
  150. <field>
  151. <name>AES_DINR</name>
  152. <description>Data Input Register.</description>
  153. <bitOffset>0</bitOffset>
  154. <bitWidth>32</bitWidth>
  155. </field>
  156. </fields>
  157. </register>
  158. <register>
  159. <name>DOUTR</name>
  160. <displayName>DOUTR</displayName>
  161. <description>data output register</description>
  162. <addressOffset>0xC</addressOffset>
  163. <size>0x20</size>
  164. <access>read-only</access>
  165. <resetValue>0x00000000</resetValue>
  166. <fields>
  167. <field>
  168. <name>AES_DOUTR</name>
  169. <description>Data output register</description>
  170. <bitOffset>0</bitOffset>
  171. <bitWidth>32</bitWidth>
  172. </field>
  173. </fields>
  174. </register>
  175. <register>
  176. <name>KEYR0</name>
  177. <displayName>KEYR0</displayName>
  178. <description>key register 0</description>
  179. <addressOffset>0x10</addressOffset>
  180. <size>0x20</size>
  181. <access>read-write</access>
  182. <resetValue>0x00000000</resetValue>
  183. <fields>
  184. <field>
  185. <name>AES_KEYR0</name>
  186. <description>Data Output Register (LSB key
  187. [31:0])</description>
  188. <bitOffset>0</bitOffset>
  189. <bitWidth>32</bitWidth>
  190. </field>
  191. </fields>
  192. </register>
  193. <register>
  194. <name>KEYR1</name>
  195. <displayName>KEYR1</displayName>
  196. <description>key register 1</description>
  197. <addressOffset>0x14</addressOffset>
  198. <size>0x20</size>
  199. <access>read-write</access>
  200. <resetValue>0x00000000</resetValue>
  201. <fields>
  202. <field>
  203. <name>AES_KEYR1</name>
  204. <description>AES key register (key
  205. [63:32])</description>
  206. <bitOffset>0</bitOffset>
  207. <bitWidth>32</bitWidth>
  208. </field>
  209. </fields>
  210. </register>
  211. <register>
  212. <name>KEYR2</name>
  213. <displayName>KEYR2</displayName>
  214. <description>key register 2</description>
  215. <addressOffset>0x18</addressOffset>
  216. <size>0x20</size>
  217. <access>read-write</access>
  218. <resetValue>0x00000000</resetValue>
  219. <fields>
  220. <field>
  221. <name>AES_KEYR2</name>
  222. <description>AES key register (key
  223. [95:64])</description>
  224. <bitOffset>0</bitOffset>
  225. <bitWidth>32</bitWidth>
  226. </field>
  227. </fields>
  228. </register>
  229. <register>
  230. <name>KEYR3</name>
  231. <displayName>KEYR3</displayName>
  232. <description>key register 3</description>
  233. <addressOffset>0x1C</addressOffset>
  234. <size>0x20</size>
  235. <access>read-write</access>
  236. <resetValue>0x00000000</resetValue>
  237. <fields>
  238. <field>
  239. <name>AES_KEYR3</name>
  240. <description>AES key register (MSB key
  241. [127:96])</description>
  242. <bitOffset>0</bitOffset>
  243. <bitWidth>32</bitWidth>
  244. </field>
  245. </fields>
  246. </register>
  247. <register>
  248. <name>IVR0</name>
  249. <displayName>IVR0</displayName>
  250. <description>initialization vector register
  251. 0</description>
  252. <addressOffset>0x20</addressOffset>
  253. <size>0x20</size>
  254. <access>read-write</access>
  255. <resetValue>0x00000000</resetValue>
  256. <fields>
  257. <field>
  258. <name>AES_IVR0</name>
  259. <description>initialization vector register (LSB IVR
  260. [31:0])</description>
  261. <bitOffset>0</bitOffset>
  262. <bitWidth>32</bitWidth>
  263. </field>
  264. </fields>
  265. </register>
  266. <register>
  267. <name>IVR1</name>
  268. <displayName>IVR1</displayName>
  269. <description>initialization vector register
  270. 1</description>
  271. <addressOffset>0x24</addressOffset>
  272. <size>0x20</size>
  273. <access>read-write</access>
  274. <resetValue>0x00000000</resetValue>
  275. <fields>
  276. <field>
  277. <name>AES_IVR1</name>
  278. <description>Initialization Vector Register (IVR
  279. [63:32])</description>
  280. <bitOffset>0</bitOffset>
  281. <bitWidth>32</bitWidth>
  282. </field>
  283. </fields>
  284. </register>
  285. <register>
  286. <name>IVR2</name>
  287. <displayName>IVR2</displayName>
  288. <description>initialization vector register
  289. 2</description>
  290. <addressOffset>0x28</addressOffset>
  291. <size>0x20</size>
  292. <access>read-write</access>
  293. <resetValue>0x00000000</resetValue>
  294. <fields>
  295. <field>
  296. <name>AES_IVR2</name>
  297. <description>Initialization Vector Register (IVR
  298. [95:64])</description>
  299. <bitOffset>0</bitOffset>
  300. <bitWidth>32</bitWidth>
  301. </field>
  302. </fields>
  303. </register>
  304. <register>
  305. <name>IVR3</name>
  306. <displayName>IVR3</displayName>
  307. <description>initialization vector register
  308. 3</description>
  309. <addressOffset>0x2C</addressOffset>
  310. <size>0x20</size>
  311. <access>read-write</access>
  312. <resetValue>0x00000000</resetValue>
  313. <fields>
  314. <field>
  315. <name>AES_IVR3</name>
  316. <description>Initialization Vector Register (MSB IVR
  317. [127:96])</description>
  318. <bitOffset>0</bitOffset>
  319. <bitWidth>32</bitWidth>
  320. </field>
  321. </fields>
  322. </register>
  323. </registers>
  324. </peripheral>
  325. <peripheral>
  326. <name>DMA1</name>
  327. <description>Direct memory access controller</description>
  328. <groupName>DMA</groupName>
  329. <baseAddress>0x40020000</baseAddress>
  330. <addressBlock>
  331. <offset>0x0</offset>
  332. <size>0x400</size>
  333. <usage>registers</usage>
  334. </addressBlock>
  335. <interrupt>
  336. <name>DMA1_Channel1</name>
  337. <description>DMA1 Channel1 global interrupt</description>
  338. <value>9</value>
  339. </interrupt>
  340. <interrupt>
  341. <name>DMA1_Channel2_3</name>
  342. <description>DMA1 Channel2 and 3 interrupts</description>
  343. <value>10</value>
  344. </interrupt>
  345. <interrupt>
  346. <name>DMA1_Channel4_7</name>
  347. <description>DMA1 Channel4 to 7 interrupts</description>
  348. <value>11</value>
  349. </interrupt>
  350. <registers>
  351. <register>
  352. <name>ISR</name>
  353. <displayName>ISR</displayName>
  354. <description>interrupt status register</description>
  355. <addressOffset>0x0</addressOffset>
  356. <size>0x20</size>
  357. <access>read-only</access>
  358. <resetValue>0x00000000</resetValue>
  359. <fields>
  360. <field>
  361. <name>TEIF7</name>
  362. <description>Channel x transfer error flag (x = 1
  363. ..7)</description>
  364. <bitOffset>27</bitOffset>
  365. <bitWidth>1</bitWidth>
  366. </field>
  367. <field>
  368. <name>HTIF7</name>
  369. <description>Channel x half transfer flag (x = 1
  370. ..7)</description>
  371. <bitOffset>26</bitOffset>
  372. <bitWidth>1</bitWidth>
  373. </field>
  374. <field>
  375. <name>TCIF7</name>
  376. <description>Channel x transfer complete flag (x = 1
  377. ..7)</description>
  378. <bitOffset>25</bitOffset>
  379. <bitWidth>1</bitWidth>
  380. </field>
  381. <field>
  382. <name>GIF7</name>
  383. <description>Channel x global interrupt flag (x = 1
  384. ..7)</description>
  385. <bitOffset>24</bitOffset>
  386. <bitWidth>1</bitWidth>
  387. </field>
  388. <field>
  389. <name>TEIF6</name>
  390. <description>Channel x transfer error flag (x = 1
  391. ..7)</description>
  392. <bitOffset>23</bitOffset>
  393. <bitWidth>1</bitWidth>
  394. </field>
  395. <field>
  396. <name>HTIF6</name>
  397. <description>Channel x half transfer flag (x = 1
  398. ..7)</description>
  399. <bitOffset>22</bitOffset>
  400. <bitWidth>1</bitWidth>
  401. </field>
  402. <field>
  403. <name>TCIF6</name>
  404. <description>Channel x transfer complete flag (x = 1
  405. ..7)</description>
  406. <bitOffset>21</bitOffset>
  407. <bitWidth>1</bitWidth>
  408. </field>
  409. <field>
  410. <name>GIF6</name>
  411. <description>Channel x global interrupt flag (x = 1
  412. ..7)</description>
  413. <bitOffset>20</bitOffset>
  414. <bitWidth>1</bitWidth>
  415. </field>
  416. <field>
  417. <name>TEIF5</name>
  418. <description>Channel x transfer error flag (x = 1
  419. ..7)</description>
  420. <bitOffset>19</bitOffset>
  421. <bitWidth>1</bitWidth>
  422. </field>
  423. <field>
  424. <name>HTIF5</name>
  425. <description>Channel x half transfer flag (x = 1
  426. ..7)</description>
  427. <bitOffset>18</bitOffset>
  428. <bitWidth>1</bitWidth>
  429. </field>
  430. <field>
  431. <name>TCIF5</name>
  432. <description>Channel x transfer complete flag (x = 1
  433. ..7)</description>
  434. <bitOffset>17</bitOffset>
  435. <bitWidth>1</bitWidth>
  436. </field>
  437. <field>
  438. <name>GIF5</name>
  439. <description>Channel x global interrupt flag (x = 1
  440. ..7)</description>
  441. <bitOffset>16</bitOffset>
  442. <bitWidth>1</bitWidth>
  443. </field>
  444. <field>
  445. <name>TEIF4</name>
  446. <description>Channel x transfer error flag (x = 1
  447. ..7)</description>
  448. <bitOffset>15</bitOffset>
  449. <bitWidth>1</bitWidth>
  450. </field>
  451. <field>
  452. <name>HTIF4</name>
  453. <description>Channel x half transfer flag (x = 1
  454. ..7)</description>
  455. <bitOffset>14</bitOffset>
  456. <bitWidth>1</bitWidth>
  457. </field>
  458. <field>
  459. <name>TCIF4</name>
  460. <description>Channel x transfer complete flag (x = 1
  461. ..7)</description>
  462. <bitOffset>13</bitOffset>
  463. <bitWidth>1</bitWidth>
  464. </field>
  465. <field>
  466. <name>GIF4</name>
  467. <description>Channel x global interrupt flag (x = 1
  468. ..7)</description>
  469. <bitOffset>12</bitOffset>
  470. <bitWidth>1</bitWidth>
  471. </field>
  472. <field>
  473. <name>TEIF3</name>
  474. <description>Channel x transfer error flag (x = 1
  475. ..7)</description>
  476. <bitOffset>11</bitOffset>
  477. <bitWidth>1</bitWidth>
  478. </field>
  479. <field>
  480. <name>HTIF3</name>
  481. <description>Channel x half transfer flag (x = 1
  482. ..7)</description>
  483. <bitOffset>10</bitOffset>
  484. <bitWidth>1</bitWidth>
  485. </field>
  486. <field>
  487. <name>TCIF3</name>
  488. <description>Channel x transfer complete flag (x = 1
  489. ..7)</description>
  490. <bitOffset>9</bitOffset>
  491. <bitWidth>1</bitWidth>
  492. </field>
  493. <field>
  494. <name>GIF3</name>
  495. <description>Channel x global interrupt flag (x = 1
  496. ..7)</description>
  497. <bitOffset>8</bitOffset>
  498. <bitWidth>1</bitWidth>
  499. </field>
  500. <field>
  501. <name>TEIF2</name>
  502. <description>Channel x transfer error flag (x = 1
  503. ..7)</description>
  504. <bitOffset>7</bitOffset>
  505. <bitWidth>1</bitWidth>
  506. </field>
  507. <field>
  508. <name>HTIF2</name>
  509. <description>Channel x half transfer flag (x = 1
  510. ..7)</description>
  511. <bitOffset>6</bitOffset>
  512. <bitWidth>1</bitWidth>
  513. </field>
  514. <field>
  515. <name>TCIF2</name>
  516. <description>Channel x transfer complete flag (x = 1
  517. ..7)</description>
  518. <bitOffset>5</bitOffset>
  519. <bitWidth>1</bitWidth>
  520. </field>
  521. <field>
  522. <name>GIF2</name>
  523. <description>Channel x global interrupt flag (x = 1
  524. ..7)</description>
  525. <bitOffset>4</bitOffset>
  526. <bitWidth>1</bitWidth>
  527. </field>
  528. <field>
  529. <name>TEIF1</name>
  530. <description>Channel x transfer error flag (x = 1
  531. ..7)</description>
  532. <bitOffset>3</bitOffset>
  533. <bitWidth>1</bitWidth>
  534. </field>
  535. <field>
  536. <name>HTIF1</name>
  537. <description>Channel x half transfer flag (x = 1
  538. ..7)</description>
  539. <bitOffset>2</bitOffset>
  540. <bitWidth>1</bitWidth>
  541. </field>
  542. <field>
  543. <name>TCIF1</name>
  544. <description>Channel x transfer complete flag (x = 1
  545. ..7)</description>
  546. <bitOffset>1</bitOffset>
  547. <bitWidth>1</bitWidth>
  548. </field>
  549. <field>
  550. <name>GIF1</name>
  551. <description>Channel x global interrupt flag (x = 1
  552. ..7)</description>
  553. <bitOffset>0</bitOffset>
  554. <bitWidth>1</bitWidth>
  555. </field>
  556. </fields>
  557. </register>
  558. <register>
  559. <name>IFCR</name>
  560. <displayName>IFCR</displayName>
  561. <description>interrupt flag clear register</description>
  562. <addressOffset>0x4</addressOffset>
  563. <size>0x20</size>
  564. <access>write-only</access>
  565. <resetValue>0x00000000</resetValue>
  566. <fields>
  567. <field>
  568. <name>CTEIF7</name>
  569. <description>Channel x transfer error clear (x = 1
  570. ..7)</description>
  571. <bitOffset>27</bitOffset>
  572. <bitWidth>1</bitWidth>
  573. </field>
  574. <field>
  575. <name>CHTIF7</name>
  576. <description>Channel x half transfer clear (x = 1
  577. ..7)</description>
  578. <bitOffset>26</bitOffset>
  579. <bitWidth>1</bitWidth>
  580. </field>
  581. <field>
  582. <name>CTCIF7</name>
  583. <description>Channel x transfer complete clear (x = 1
  584. ..7)</description>
  585. <bitOffset>25</bitOffset>
  586. <bitWidth>1</bitWidth>
  587. </field>
  588. <field>
  589. <name>CGIF7</name>
  590. <description>Channel x global interrupt clear (x = 1
  591. ..7)</description>
  592. <bitOffset>24</bitOffset>
  593. <bitWidth>1</bitWidth>
  594. </field>
  595. <field>
  596. <name>CTEIF6</name>
  597. <description>Channel x transfer error clear (x = 1
  598. ..7)</description>
  599. <bitOffset>23</bitOffset>
  600. <bitWidth>1</bitWidth>
  601. </field>
  602. <field>
  603. <name>CHTIF6</name>
  604. <description>Channel x half transfer clear (x = 1
  605. ..7)</description>
  606. <bitOffset>22</bitOffset>
  607. <bitWidth>1</bitWidth>
  608. </field>
  609. <field>
  610. <name>CTCIF6</name>
  611. <description>Channel x transfer complete clear (x = 1
  612. ..7)</description>
  613. <bitOffset>21</bitOffset>
  614. <bitWidth>1</bitWidth>
  615. </field>
  616. <field>
  617. <name>CGIF6</name>
  618. <description>Channel x global interrupt clear (x = 1
  619. ..7)</description>
  620. <bitOffset>20</bitOffset>
  621. <bitWidth>1</bitWidth>
  622. </field>
  623. <field>
  624. <name>CTEIF5</name>
  625. <description>Channel x transfer error clear (x = 1
  626. ..7)</description>
  627. <bitOffset>19</bitOffset>
  628. <bitWidth>1</bitWidth>
  629. </field>
  630. <field>
  631. <name>CHTIF5</name>
  632. <description>Channel x half transfer clear (x = 1
  633. ..7)</description>
  634. <bitOffset>18</bitOffset>
  635. <bitWidth>1</bitWidth>
  636. </field>
  637. <field>
  638. <name>CTCIF5</name>
  639. <description>Channel x transfer complete clear (x = 1
  640. ..7)</description>
  641. <bitOffset>17</bitOffset>
  642. <bitWidth>1</bitWidth>
  643. </field>
  644. <field>
  645. <name>CGIF5</name>
  646. <description>Channel x global interrupt clear (x = 1
  647. ..7)</description>
  648. <bitOffset>16</bitOffset>
  649. <bitWidth>1</bitWidth>
  650. </field>
  651. <field>
  652. <name>CTEIF4</name>
  653. <description>Channel x transfer error clear (x = 1
  654. ..7)</description>
  655. <bitOffset>15</bitOffset>
  656. <bitWidth>1</bitWidth>
  657. </field>
  658. <field>
  659. <name>CHTIF4</name>
  660. <description>Channel x half transfer clear (x = 1
  661. ..7)</description>
  662. <bitOffset>14</bitOffset>
  663. <bitWidth>1</bitWidth>
  664. </field>
  665. <field>
  666. <name>CTCIF4</name>
  667. <description>Channel x transfer complete clear (x = 1
  668. ..7)</description>
  669. <bitOffset>13</bitOffset>
  670. <bitWidth>1</bitWidth>
  671. </field>
  672. <field>
  673. <name>CGIF4</name>
  674. <description>Channel x global interrupt clear (x = 1
  675. ..7)</description>
  676. <bitOffset>12</bitOffset>
  677. <bitWidth>1</bitWidth>
  678. </field>
  679. <field>
  680. <name>CTEIF3</name>
  681. <description>Channel x transfer error clear (x = 1
  682. ..7)</description>
  683. <bitOffset>11</bitOffset>
  684. <bitWidth>1</bitWidth>
  685. </field>
  686. <field>
  687. <name>CHTIF3</name>
  688. <description>Channel x half transfer clear (x = 1
  689. ..7)</description>
  690. <bitOffset>10</bitOffset>
  691. <bitWidth>1</bitWidth>
  692. </field>
  693. <field>
  694. <name>CTCIF3</name>
  695. <description>Channel x transfer complete clear (x = 1
  696. ..7)</description>
  697. <bitOffset>9</bitOffset>
  698. <bitWidth>1</bitWidth>
  699. </field>
  700. <field>
  701. <name>CGIF3</name>
  702. <description>Channel x global interrupt clear (x = 1
  703. ..7)</description>
  704. <bitOffset>8</bitOffset>
  705. <bitWidth>1</bitWidth>
  706. </field>
  707. <field>
  708. <name>CTEIF2</name>
  709. <description>Channel x transfer error clear (x = 1
  710. ..7)</description>
  711. <bitOffset>7</bitOffset>
  712. <bitWidth>1</bitWidth>
  713. </field>
  714. <field>
  715. <name>CHTIF2</name>
  716. <description>Channel x half transfer clear (x = 1
  717. ..7)</description>
  718. <bitOffset>6</bitOffset>
  719. <bitWidth>1</bitWidth>
  720. </field>
  721. <field>
  722. <name>CTCIF2</name>
  723. <description>Channel x transfer complete clear (x = 1
  724. ..7)</description>
  725. <bitOffset>5</bitOffset>
  726. <bitWidth>1</bitWidth>
  727. </field>
  728. <field>
  729. <name>CGIF2</name>
  730. <description>Channel x global interrupt clear (x = 1
  731. ..7)</description>
  732. <bitOffset>4</bitOffset>
  733. <bitWidth>1</bitWidth>
  734. </field>
  735. <field>
  736. <name>CTEIF1</name>
  737. <description>Channel x transfer error clear (x = 1
  738. ..7)</description>
  739. <bitOffset>3</bitOffset>
  740. <bitWidth>1</bitWidth>
  741. </field>
  742. <field>
  743. <name>CHTIF1</name>
  744. <description>Channel x half transfer clear (x = 1
  745. ..7)</description>
  746. <bitOffset>2</bitOffset>
  747. <bitWidth>1</bitWidth>
  748. </field>
  749. <field>
  750. <name>CTCIF1</name>
  751. <description>Channel x transfer complete clear (x = 1
  752. ..7)</description>
  753. <bitOffset>1</bitOffset>
  754. <bitWidth>1</bitWidth>
  755. </field>
  756. <field>
  757. <name>CGIF1</name>
  758. <description>Channel x global interrupt clear (x = 1
  759. ..7)</description>
  760. <bitOffset>0</bitOffset>
  761. <bitWidth>1</bitWidth>
  762. </field>
  763. </fields>
  764. </register>
  765. <register>
  766. <name>CCR1</name>
  767. <displayName>CCR1</displayName>
  768. <description>channel x configuration
  769. register</description>
  770. <addressOffset>0x8</addressOffset>
  771. <size>0x20</size>
  772. <access>read-write</access>
  773. <resetValue>0x00000000</resetValue>
  774. <fields>
  775. <field>
  776. <name>MEM2MEM</name>
  777. <description>Memory to memory mode</description>
  778. <bitOffset>14</bitOffset>
  779. <bitWidth>1</bitWidth>
  780. </field>
  781. <field>
  782. <name>PL</name>
  783. <description>Channel priority level</description>
  784. <bitOffset>12</bitOffset>
  785. <bitWidth>2</bitWidth>
  786. </field>
  787. <field>
  788. <name>MSIZE</name>
  789. <description>Memory size</description>
  790. <bitOffset>10</bitOffset>
  791. <bitWidth>2</bitWidth>
  792. </field>
  793. <field>
  794. <name>PSIZE</name>
  795. <description>Peripheral size</description>
  796. <bitOffset>8</bitOffset>
  797. <bitWidth>2</bitWidth>
  798. </field>
  799. <field>
  800. <name>MINC</name>
  801. <description>Memory increment mode</description>
  802. <bitOffset>7</bitOffset>
  803. <bitWidth>1</bitWidth>
  804. </field>
  805. <field>
  806. <name>PINC</name>
  807. <description>Peripheral increment mode</description>
  808. <bitOffset>6</bitOffset>
  809. <bitWidth>1</bitWidth>
  810. </field>
  811. <field>
  812. <name>CIRC</name>
  813. <description>Circular mode</description>
  814. <bitOffset>5</bitOffset>
  815. <bitWidth>1</bitWidth>
  816. </field>
  817. <field>
  818. <name>DIR</name>
  819. <description>Data transfer direction</description>
  820. <bitOffset>4</bitOffset>
  821. <bitWidth>1</bitWidth>
  822. </field>
  823. <field>
  824. <name>TEIE</name>
  825. <description>Transfer error interrupt
  826. enable</description>
  827. <bitOffset>3</bitOffset>
  828. <bitWidth>1</bitWidth>
  829. </field>
  830. <field>
  831. <name>HTIE</name>
  832. <description>Half transfer interrupt
  833. enable</description>
  834. <bitOffset>2</bitOffset>
  835. <bitWidth>1</bitWidth>
  836. </field>
  837. <field>
  838. <name>TCIE</name>
  839. <description>Transfer complete interrupt
  840. enable</description>
  841. <bitOffset>1</bitOffset>
  842. <bitWidth>1</bitWidth>
  843. </field>
  844. <field>
  845. <name>EN</name>
  846. <description>Channel enable</description>
  847. <bitOffset>0</bitOffset>
  848. <bitWidth>1</bitWidth>
  849. </field>
  850. </fields>
  851. </register>
  852. <register>
  853. <name>CNDTR1</name>
  854. <displayName>CNDTR1</displayName>
  855. <description>channel x number of data
  856. register</description>
  857. <addressOffset>0xC</addressOffset>
  858. <size>0x20</size>
  859. <access>read-write</access>
  860. <resetValue>0x00000000</resetValue>
  861. <fields>
  862. <field>
  863. <name>NDT</name>
  864. <description>Number of data to transfer</description>
  865. <bitOffset>0</bitOffset>
  866. <bitWidth>16</bitWidth>
  867. </field>
  868. </fields>
  869. </register>
  870. <register>
  871. <name>CPAR1</name>
  872. <displayName>CPAR1</displayName>
  873. <description>channel x peripheral address
  874. register</description>
  875. <addressOffset>0x10</addressOffset>
  876. <size>0x20</size>
  877. <access>read-write</access>
  878. <resetValue>0x00000000</resetValue>
  879. <fields>
  880. <field>
  881. <name>PA</name>
  882. <description>Peripheral address</description>
  883. <bitOffset>0</bitOffset>
  884. <bitWidth>32</bitWidth>
  885. </field>
  886. </fields>
  887. </register>
  888. <register>
  889. <name>CMAR1</name>
  890. <displayName>CMAR1</displayName>
  891. <description>channel x memory address
  892. register</description>
  893. <addressOffset>0x14</addressOffset>
  894. <size>0x20</size>
  895. <access>read-write</access>
  896. <resetValue>0x00000000</resetValue>
  897. <fields>
  898. <field>
  899. <name>MA</name>
  900. <description>Memory address</description>
  901. <bitOffset>0</bitOffset>
  902. <bitWidth>32</bitWidth>
  903. </field>
  904. </fields>
  905. </register>
  906. <register>
  907. <name>CCR2</name>
  908. <displayName>CCR2</displayName>
  909. <description>channel x configuration
  910. register</description>
  911. <addressOffset>0x1C</addressOffset>
  912. <size>0x20</size>
  913. <access>read-write</access>
  914. <resetValue>0x00000000</resetValue>
  915. <fields>
  916. <field>
  917. <name>MEM2MEM</name>
  918. <description>Memory to memory mode</description>
  919. <bitOffset>14</bitOffset>
  920. <bitWidth>1</bitWidth>
  921. </field>
  922. <field>
  923. <name>PL</name>
  924. <description>Channel priority level</description>
  925. <bitOffset>12</bitOffset>
  926. <bitWidth>2</bitWidth>
  927. </field>
  928. <field>
  929. <name>MSIZE</name>
  930. <description>Memory size</description>
  931. <bitOffset>10</bitOffset>
  932. <bitWidth>2</bitWidth>
  933. </field>
  934. <field>
  935. <name>PSIZE</name>
  936. <description>Peripheral size</description>
  937. <bitOffset>8</bitOffset>
  938. <bitWidth>2</bitWidth>
  939. </field>
  940. <field>
  941. <name>MINC</name>
  942. <description>Memory increment mode</description>
  943. <bitOffset>7</bitOffset>
  944. <bitWidth>1</bitWidth>
  945. </field>
  946. <field>
  947. <name>PINC</name>
  948. <description>Peripheral increment mode</description>
  949. <bitOffset>6</bitOffset>
  950. <bitWidth>1</bitWidth>
  951. </field>
  952. <field>
  953. <name>CIRC</name>
  954. <description>Circular mode</description>
  955. <bitOffset>5</bitOffset>
  956. <bitWidth>1</bitWidth>
  957. </field>
  958. <field>
  959. <name>DIR</name>
  960. <description>Data transfer direction</description>
  961. <bitOffset>4</bitOffset>
  962. <bitWidth>1</bitWidth>
  963. </field>
  964. <field>
  965. <name>TEIE</name>
  966. <description>Transfer error interrupt
  967. enable</description>
  968. <bitOffset>3</bitOffset>
  969. <bitWidth>1</bitWidth>
  970. </field>
  971. <field>
  972. <name>HTIE</name>
  973. <description>Half transfer interrupt
  974. enable</description>
  975. <bitOffset>2</bitOffset>
  976. <bitWidth>1</bitWidth>
  977. </field>
  978. <field>
  979. <name>TCIE</name>
  980. <description>Transfer complete interrupt
  981. enable</description>
  982. <bitOffset>1</bitOffset>
  983. <bitWidth>1</bitWidth>
  984. </field>
  985. <field>
  986. <name>EN</name>
  987. <description>Channel enable</description>
  988. <bitOffset>0</bitOffset>
  989. <bitWidth>1</bitWidth>
  990. </field>
  991. </fields>
  992. </register>
  993. <register>
  994. <name>CNDTR2</name>
  995. <displayName>CNDTR2</displayName>
  996. <description>channel x number of data
  997. register</description>
  998. <addressOffset>0x20</addressOffset>
  999. <size>0x20</size>
  1000. <access>read-write</access>
  1001. <resetValue>0x00000000</resetValue>
  1002. <fields>
  1003. <field>
  1004. <name>NDT</name>
  1005. <description>Number of data to transfer</description>
  1006. <bitOffset>0</bitOffset>
  1007. <bitWidth>16</bitWidth>
  1008. </field>
  1009. </fields>
  1010. </register>
  1011. <register>
  1012. <name>CPAR2</name>
  1013. <displayName>CPAR2</displayName>
  1014. <description>channel x peripheral address
  1015. register</description>
  1016. <addressOffset>0x24</addressOffset>
  1017. <size>0x20</size>
  1018. <access>read-write</access>
  1019. <resetValue>0x00000000</resetValue>
  1020. <fields>
  1021. <field>
  1022. <name>PA</name>
  1023. <description>Peripheral address</description>
  1024. <bitOffset>0</bitOffset>
  1025. <bitWidth>32</bitWidth>
  1026. </field>
  1027. </fields>
  1028. </register>
  1029. <register>
  1030. <name>CMAR2</name>
  1031. <displayName>CMAR2</displayName>
  1032. <description>channel x memory address
  1033. register</description>
  1034. <addressOffset>0x28</addressOffset>
  1035. <size>0x20</size>
  1036. <access>read-write</access>
  1037. <resetValue>0x00000000</resetValue>
  1038. <fields>
  1039. <field>
  1040. <name>MA</name>
  1041. <description>Memory address</description>
  1042. <bitOffset>0</bitOffset>
  1043. <bitWidth>32</bitWidth>
  1044. </field>
  1045. </fields>
  1046. </register>
  1047. <register>
  1048. <name>CCR3</name>
  1049. <displayName>CCR3</displayName>
  1050. <description>channel x configuration
  1051. register</description>
  1052. <addressOffset>0x30</addressOffset>
  1053. <size>0x20</size>
  1054. <access>read-write</access>
  1055. <resetValue>0x00000000</resetValue>
  1056. <fields>
  1057. <field>
  1058. <name>MEM2MEM</name>
  1059. <description>Memory to memory mode</description>
  1060. <bitOffset>14</bitOffset>
  1061. <bitWidth>1</bitWidth>
  1062. </field>
  1063. <field>
  1064. <name>PL</name>
  1065. <description>Channel priority level</description>
  1066. <bitOffset>12</bitOffset>
  1067. <bitWidth>2</bitWidth>
  1068. </field>
  1069. <field>
  1070. <name>MSIZE</name>
  1071. <description>Memory size</description>
  1072. <bitOffset>10</bitOffset>
  1073. <bitWidth>2</bitWidth>
  1074. </field>
  1075. <field>
  1076. <name>PSIZE</name>
  1077. <description>Peripheral size</description>
  1078. <bitOffset>8</bitOffset>
  1079. <bitWidth>2</bitWidth>
  1080. </field>
  1081. <field>
  1082. <name>MINC</name>
  1083. <description>Memory increment mode</description>
  1084. <bitOffset>7</bitOffset>
  1085. <bitWidth>1</bitWidth>
  1086. </field>
  1087. <field>
  1088. <name>PINC</name>
  1089. <description>Peripheral increment mode</description>
  1090. <bitOffset>6</bitOffset>
  1091. <bitWidth>1</bitWidth>
  1092. </field>
  1093. <field>
  1094. <name>CIRC</name>
  1095. <description>Circular mode</description>
  1096. <bitOffset>5</bitOffset>
  1097. <bitWidth>1</bitWidth>
  1098. </field>
  1099. <field>
  1100. <name>DIR</name>
  1101. <description>Data transfer direction</description>
  1102. <bitOffset>4</bitOffset>
  1103. <bitWidth>1</bitWidth>
  1104. </field>
  1105. <field>
  1106. <name>TEIE</name>
  1107. <description>Transfer error interrupt
  1108. enable</description>
  1109. <bitOffset>3</bitOffset>
  1110. <bitWidth>1</bitWidth>
  1111. </field>
  1112. <field>
  1113. <name>HTIE</name>
  1114. <description>Half transfer interrupt
  1115. enable</description>
  1116. <bitOffset>2</bitOffset>
  1117. <bitWidth>1</bitWidth>
  1118. </field>
  1119. <field>
  1120. <name>TCIE</name>
  1121. <description>Transfer complete interrupt
  1122. enable</description>
  1123. <bitOffset>1</bitOffset>
  1124. <bitWidth>1</bitWidth>
  1125. </field>
  1126. <field>
  1127. <name>EN</name>
  1128. <description>Channel enable</description>
  1129. <bitOffset>0</bitOffset>
  1130. <bitWidth>1</bitWidth>
  1131. </field>
  1132. </fields>
  1133. </register>
  1134. <register>
  1135. <name>CNDTR3</name>
  1136. <displayName>CNDTR3</displayName>
  1137. <description>channel x number of data
  1138. register</description>
  1139. <addressOffset>0x34</addressOffset>
  1140. <size>0x20</size>
  1141. <access>read-write</access>
  1142. <resetValue>0x00000000</resetValue>
  1143. <fields>
  1144. <field>
  1145. <name>NDT</name>
  1146. <description>Number of data to transfer</description>
  1147. <bitOffset>0</bitOffset>
  1148. <bitWidth>16</bitWidth>
  1149. </field>
  1150. </fields>
  1151. </register>
  1152. <register>
  1153. <name>CPAR3</name>
  1154. <displayName>CPAR3</displayName>
  1155. <description>channel x peripheral address
  1156. register</description>
  1157. <addressOffset>0x38</addressOffset>
  1158. <size>0x20</size>
  1159. <access>read-write</access>
  1160. <resetValue>0x00000000</resetValue>
  1161. <fields>
  1162. <field>
  1163. <name>PA</name>
  1164. <description>Peripheral address</description>
  1165. <bitOffset>0</bitOffset>
  1166. <bitWidth>32</bitWidth>
  1167. </field>
  1168. </fields>
  1169. </register>
  1170. <register>
  1171. <name>CMAR3</name>
  1172. <displayName>CMAR3</displayName>
  1173. <description>channel x memory address
  1174. register</description>
  1175. <addressOffset>0x3C</addressOffset>
  1176. <size>0x20</size>
  1177. <access>read-write</access>
  1178. <resetValue>0x00000000</resetValue>
  1179. <fields>
  1180. <field>
  1181. <name>MA</name>
  1182. <description>Memory address</description>
  1183. <bitOffset>0</bitOffset>
  1184. <bitWidth>32</bitWidth>
  1185. </field>
  1186. </fields>
  1187. </register>
  1188. <register>
  1189. <name>CCR4</name>
  1190. <displayName>CCR4</displayName>
  1191. <description>channel x configuration
  1192. register</description>
  1193. <addressOffset>0x44</addressOffset>
  1194. <size>0x20</size>
  1195. <access>read-write</access>
  1196. <resetValue>0x00000000</resetValue>
  1197. <fields>
  1198. <field>
  1199. <name>MEM2MEM</name>
  1200. <description>Memory to memory mode</description>
  1201. <bitOffset>14</bitOffset>
  1202. <bitWidth>1</bitWidth>
  1203. </field>
  1204. <field>
  1205. <name>PL</name>
  1206. <description>Channel priority level</description>
  1207. <bitOffset>12</bitOffset>
  1208. <bitWidth>2</bitWidth>
  1209. </field>
  1210. <field>
  1211. <name>MSIZE</name>
  1212. <description>Memory size</description>
  1213. <bitOffset>10</bitOffset>
  1214. <bitWidth>2</bitWidth>
  1215. </field>
  1216. <field>
  1217. <name>PSIZE</name>
  1218. <description>Peripheral size</description>
  1219. <bitOffset>8</bitOffset>
  1220. <bitWidth>2</bitWidth>
  1221. </field>
  1222. <field>
  1223. <name>MINC</name>
  1224. <description>Memory increment mode</description>
  1225. <bitOffset>7</bitOffset>
  1226. <bitWidth>1</bitWidth>
  1227. </field>
  1228. <field>
  1229. <name>PINC</name>
  1230. <description>Peripheral increment mode</description>
  1231. <bitOffset>6</bitOffset>
  1232. <bitWidth>1</bitWidth>
  1233. </field>
  1234. <field>
  1235. <name>CIRC</name>
  1236. <description>Circular mode</description>
  1237. <bitOffset>5</bitOffset>
  1238. <bitWidth>1</bitWidth>
  1239. </field>
  1240. <field>
  1241. <name>DIR</name>
  1242. <description>Data transfer direction</description>
  1243. <bitOffset>4</bitOffset>
  1244. <bitWidth>1</bitWidth>
  1245. </field>
  1246. <field>
  1247. <name>TEIE</name>
  1248. <description>Transfer error interrupt
  1249. enable</description>
  1250. <bitOffset>3</bitOffset>
  1251. <bitWidth>1</bitWidth>
  1252. </field>
  1253. <field>
  1254. <name>HTIE</name>
  1255. <description>Half transfer interrupt
  1256. enable</description>
  1257. <bitOffset>2</bitOffset>
  1258. <bitWidth>1</bitWidth>
  1259. </field>
  1260. <field>
  1261. <name>TCIE</name>
  1262. <description>Transfer complete interrupt
  1263. enable</description>
  1264. <bitOffset>1</bitOffset>
  1265. <bitWidth>1</bitWidth>
  1266. </field>
  1267. <field>
  1268. <name>EN</name>
  1269. <description>Channel enable</description>
  1270. <bitOffset>0</bitOffset>
  1271. <bitWidth>1</bitWidth>
  1272. </field>
  1273. </fields>
  1274. </register>
  1275. <register>
  1276. <name>CNDTR4</name>
  1277. <displayName>CNDTR4</displayName>
  1278. <description>channel x number of data
  1279. register</description>
  1280. <addressOffset>0x48</addressOffset>
  1281. <size>0x20</size>
  1282. <access>read-write</access>
  1283. <resetValue>0x00000000</resetValue>
  1284. <fields>
  1285. <field>
  1286. <name>NDT</name>
  1287. <description>Number of data to transfer</description>
  1288. <bitOffset>0</bitOffset>
  1289. <bitWidth>16</bitWidth>
  1290. </field>
  1291. </fields>
  1292. </register>
  1293. <register>
  1294. <name>CPAR4</name>
  1295. <displayName>CPAR4</displayName>
  1296. <description>channel x peripheral address
  1297. register</description>
  1298. <addressOffset>0x4C</addressOffset>
  1299. <size>0x20</size>
  1300. <access>read-write</access>
  1301. <resetValue>0x00000000</resetValue>
  1302. <fields>
  1303. <field>
  1304. <name>PA</name>
  1305. <description>Peripheral address</description>
  1306. <bitOffset>0</bitOffset>
  1307. <bitWidth>32</bitWidth>
  1308. </field>
  1309. </fields>
  1310. </register>
  1311. <register>
  1312. <name>CMAR4</name>
  1313. <displayName>CMAR4</displayName>
  1314. <description>channel x memory address
  1315. register</description>
  1316. <addressOffset>0x50</addressOffset>
  1317. <size>0x20</size>
  1318. <access>read-write</access>
  1319. <resetValue>0x00000000</resetValue>
  1320. <fields>
  1321. <field>
  1322. <name>MA</name>
  1323. <description>Memory address</description>
  1324. <bitOffset>0</bitOffset>
  1325. <bitWidth>32</bitWidth>
  1326. </field>
  1327. </fields>
  1328. </register>
  1329. <register>
  1330. <name>CCR5</name>
  1331. <displayName>CCR5</displayName>
  1332. <description>channel x configuration
  1333. register</description>
  1334. <addressOffset>0x58</addressOffset>
  1335. <size>0x20</size>
  1336. <access>read-write</access>
  1337. <resetValue>0x00000000</resetValue>
  1338. <fields>
  1339. <field>
  1340. <name>MEM2MEM</name>
  1341. <description>Memory to memory mode</description>
  1342. <bitOffset>14</bitOffset>
  1343. <bitWidth>1</bitWidth>
  1344. </field>
  1345. <field>
  1346. <name>PL</name>
  1347. <description>Channel priority level</description>
  1348. <bitOffset>12</bitOffset>
  1349. <bitWidth>2</bitWidth>
  1350. </field>
  1351. <field>
  1352. <name>MSIZE</name>
  1353. <description>Memory size</description>
  1354. <bitOffset>10</bitOffset>
  1355. <bitWidth>2</bitWidth>
  1356. </field>
  1357. <field>
  1358. <name>PSIZE</name>
  1359. <description>Peripheral size</description>
  1360. <bitOffset>8</bitOffset>
  1361. <bitWidth>2</bitWidth>
  1362. </field>
  1363. <field>
  1364. <name>MINC</name>
  1365. <description>Memory increment mode</description>
  1366. <bitOffset>7</bitOffset>
  1367. <bitWidth>1</bitWidth>
  1368. </field>
  1369. <field>
  1370. <name>PINC</name>
  1371. <description>Peripheral increment mode</description>
  1372. <bitOffset>6</bitOffset>
  1373. <bitWidth>1</bitWidth>
  1374. </field>
  1375. <field>
  1376. <name>CIRC</name>
  1377. <description>Circular mode</description>
  1378. <bitOffset>5</bitOffset>
  1379. <bitWidth>1</bitWidth>
  1380. </field>
  1381. <field>
  1382. <name>DIR</name>
  1383. <description>Data transfer direction</description>
  1384. <bitOffset>4</bitOffset>
  1385. <bitWidth>1</bitWidth>
  1386. </field>
  1387. <field>
  1388. <name>TEIE</name>
  1389. <description>Transfer error interrupt
  1390. enable</description>
  1391. <bitOffset>3</bitOffset>
  1392. <bitWidth>1</bitWidth>
  1393. </field>
  1394. <field>
  1395. <name>HTIE</name>
  1396. <description>Half transfer interrupt
  1397. enable</description>
  1398. <bitOffset>2</bitOffset>
  1399. <bitWidth>1</bitWidth>
  1400. </field>
  1401. <field>
  1402. <name>TCIE</name>
  1403. <description>Transfer complete interrupt
  1404. enable</description>
  1405. <bitOffset>1</bitOffset>
  1406. <bitWidth>1</bitWidth>
  1407. </field>
  1408. <field>
  1409. <name>EN</name>
  1410. <description>Channel enable</description>
  1411. <bitOffset>0</bitOffset>
  1412. <bitWidth>1</bitWidth>
  1413. </field>
  1414. </fields>
  1415. </register>
  1416. <register>
  1417. <name>CNDTR5</name>
  1418. <displayName>CNDTR5</displayName>
  1419. <description>channel x number of data
  1420. register</description>
  1421. <addressOffset>0x5C</addressOffset>
  1422. <size>0x20</size>
  1423. <access>read-write</access>
  1424. <resetValue>0x00000000</resetValue>
  1425. <fields>
  1426. <field>
  1427. <name>NDT</name>
  1428. <description>Number of data to transfer</description>
  1429. <bitOffset>0</bitOffset>
  1430. <bitWidth>16</bitWidth>
  1431. </field>
  1432. </fields>
  1433. </register>
  1434. <register>
  1435. <name>CPAR5</name>
  1436. <displayName>CPAR5</displayName>
  1437. <description>channel x peripheral address
  1438. register</description>
  1439. <addressOffset>0x60</addressOffset>
  1440. <size>0x20</size>
  1441. <access>read-write</access>
  1442. <resetValue>0x00000000</resetValue>
  1443. <fields>
  1444. <field>
  1445. <name>PA</name>
  1446. <description>Peripheral address</description>
  1447. <bitOffset>0</bitOffset>
  1448. <bitWidth>32</bitWidth>
  1449. </field>
  1450. </fields>
  1451. </register>
  1452. <register>
  1453. <name>CMAR5</name>
  1454. <displayName>CMAR5</displayName>
  1455. <description>channel x memory address
  1456. register</description>
  1457. <addressOffset>0x64</addressOffset>
  1458. <size>0x20</size>
  1459. <access>read-write</access>
  1460. <resetValue>0x00000000</resetValue>
  1461. <fields>
  1462. <field>
  1463. <name>MA</name>
  1464. <description>Memory address</description>
  1465. <bitOffset>0</bitOffset>
  1466. <bitWidth>32</bitWidth>
  1467. </field>
  1468. </fields>
  1469. </register>
  1470. <register>
  1471. <name>CCR6</name>
  1472. <displayName>CCR6</displayName>
  1473. <description>channel x configuration
  1474. register</description>
  1475. <addressOffset>0x6C</addressOffset>
  1476. <size>0x20</size>
  1477. <access>read-write</access>
  1478. <resetValue>0x00000000</resetValue>
  1479. <fields>
  1480. <field>
  1481. <name>MEM2MEM</name>
  1482. <description>Memory to memory mode</description>
  1483. <bitOffset>14</bitOffset>
  1484. <bitWidth>1</bitWidth>
  1485. </field>
  1486. <field>
  1487. <name>PL</name>
  1488. <description>Channel priority level</description>
  1489. <bitOffset>12</bitOffset>
  1490. <bitWidth>2</bitWidth>
  1491. </field>
  1492. <field>
  1493. <name>MSIZE</name>
  1494. <description>Memory size</description>
  1495. <bitOffset>10</bitOffset>
  1496. <bitWidth>2</bitWidth>
  1497. </field>
  1498. <field>
  1499. <name>PSIZE</name>
  1500. <description>Peripheral size</description>
  1501. <bitOffset>8</bitOffset>
  1502. <bitWidth>2</bitWidth>
  1503. </field>
  1504. <field>
  1505. <name>MINC</name>
  1506. <description>Memory increment mode</description>
  1507. <bitOffset>7</bitOffset>
  1508. <bitWidth>1</bitWidth>
  1509. </field>
  1510. <field>
  1511. <name>PINC</name>
  1512. <description>Peripheral increment mode</description>
  1513. <bitOffset>6</bitOffset>
  1514. <bitWidth>1</bitWidth>
  1515. </field>
  1516. <field>
  1517. <name>CIRC</name>
  1518. <description>Circular mode</description>
  1519. <bitOffset>5</bitOffset>
  1520. <bitWidth>1</bitWidth>
  1521. </field>
  1522. <field>
  1523. <name>DIR</name>
  1524. <description>Data transfer direction</description>
  1525. <bitOffset>4</bitOffset>
  1526. <bitWidth>1</bitWidth>
  1527. </field>
  1528. <field>
  1529. <name>TEIE</name>
  1530. <description>Transfer error interrupt
  1531. enable</description>
  1532. <bitOffset>3</bitOffset>
  1533. <bitWidth>1</bitWidth>
  1534. </field>
  1535. <field>
  1536. <name>HTIE</name>
  1537. <description>Half transfer interrupt
  1538. enable</description>
  1539. <bitOffset>2</bitOffset>
  1540. <bitWidth>1</bitWidth>
  1541. </field>
  1542. <field>
  1543. <name>TCIE</name>
  1544. <description>Transfer complete interrupt
  1545. enable</description>
  1546. <bitOffset>1</bitOffset>
  1547. <bitWidth>1</bitWidth>
  1548. </field>
  1549. <field>
  1550. <name>EN</name>
  1551. <description>Channel enable</description>
  1552. <bitOffset>0</bitOffset>
  1553. <bitWidth>1</bitWidth>
  1554. </field>
  1555. </fields>
  1556. </register>
  1557. <register>
  1558. <name>CNDTR6</name>
  1559. <displayName>CNDTR6</displayName>
  1560. <description>channel x number of data
  1561. register</description>
  1562. <addressOffset>0x70</addressOffset>
  1563. <size>0x20</size>
  1564. <access>read-write</access>
  1565. <resetValue>0x00000000</resetValue>
  1566. <fields>
  1567. <field>
  1568. <name>NDT</name>
  1569. <description>Number of data to transfer</description>
  1570. <bitOffset>0</bitOffset>
  1571. <bitWidth>16</bitWidth>
  1572. </field>
  1573. </fields>
  1574. </register>
  1575. <register>
  1576. <name>CPAR6</name>
  1577. <displayName>CPAR6</displayName>
  1578. <description>channel x peripheral address
  1579. register</description>
  1580. <addressOffset>0x74</addressOffset>
  1581. <size>0x20</size>
  1582. <access>read-write</access>
  1583. <resetValue>0x00000000</resetValue>
  1584. <fields>
  1585. <field>
  1586. <name>PA</name>
  1587. <description>Peripheral address</description>
  1588. <bitOffset>0</bitOffset>
  1589. <bitWidth>32</bitWidth>
  1590. </field>
  1591. </fields>
  1592. </register>
  1593. <register>
  1594. <name>CMAR6</name>
  1595. <displayName>CMAR6</displayName>
  1596. <description>channel x memory address
  1597. register</description>
  1598. <addressOffset>0x78</addressOffset>
  1599. <size>0x20</size>
  1600. <access>read-write</access>
  1601. <resetValue>0x00000000</resetValue>
  1602. <fields>
  1603. <field>
  1604. <name>MA</name>
  1605. <description>Memory address</description>
  1606. <bitOffset>0</bitOffset>
  1607. <bitWidth>32</bitWidth>
  1608. </field>
  1609. </fields>
  1610. </register>
  1611. <register>
  1612. <name>CCR7</name>
  1613. <displayName>CCR7</displayName>
  1614. <description>channel x configuration
  1615. register</description>
  1616. <addressOffset>0x80</addressOffset>
  1617. <size>0x20</size>
  1618. <access>read-write</access>
  1619. <resetValue>0x00000000</resetValue>
  1620. <fields>
  1621. <field>
  1622. <name>MEM2MEM</name>
  1623. <description>Memory to memory mode</description>
  1624. <bitOffset>14</bitOffset>
  1625. <bitWidth>1</bitWidth>
  1626. </field>
  1627. <field>
  1628. <name>PL</name>
  1629. <description>Channel priority level</description>
  1630. <bitOffset>12</bitOffset>
  1631. <bitWidth>2</bitWidth>
  1632. </field>
  1633. <field>
  1634. <name>MSIZE</name>
  1635. <description>Memory size</description>
  1636. <bitOffset>10</bitOffset>
  1637. <bitWidth>2</bitWidth>
  1638. </field>
  1639. <field>
  1640. <name>PSIZE</name>
  1641. <description>Peripheral size</description>
  1642. <bitOffset>8</bitOffset>
  1643. <bitWidth>2</bitWidth>
  1644. </field>
  1645. <field>
  1646. <name>MINC</name>
  1647. <description>Memory increment mode</description>
  1648. <bitOffset>7</bitOffset>
  1649. <bitWidth>1</bitWidth>
  1650. </field>
  1651. <field>
  1652. <name>PINC</name>
  1653. <description>Peripheral increment mode</description>
  1654. <bitOffset>6</bitOffset>
  1655. <bitWidth>1</bitWidth>
  1656. </field>
  1657. <field>
  1658. <name>CIRC</name>
  1659. <description>Circular mode</description>
  1660. <bitOffset>5</bitOffset>
  1661. <bitWidth>1</bitWidth>
  1662. </field>
  1663. <field>
  1664. <name>DIR</name>
  1665. <description>Data transfer direction</description>
  1666. <bitOffset>4</bitOffset>
  1667. <bitWidth>1</bitWidth>
  1668. </field>
  1669. <field>
  1670. <name>TEIE</name>
  1671. <description>Transfer error interrupt
  1672. enable</description>
  1673. <bitOffset>3</bitOffset>
  1674. <bitWidth>1</bitWidth>
  1675. </field>
  1676. <field>
  1677. <name>HTIE</name>
  1678. <description>Half transfer interrupt
  1679. enable</description>
  1680. <bitOffset>2</bitOffset>
  1681. <bitWidth>1</bitWidth>
  1682. </field>
  1683. <field>
  1684. <name>TCIE</name>
  1685. <description>Transfer complete interrupt
  1686. enable</description>
  1687. <bitOffset>1</bitOffset>
  1688. <bitWidth>1</bitWidth>
  1689. </field>
  1690. <field>
  1691. <name>EN</name>
  1692. <description>Channel enable</description>
  1693. <bitOffset>0</bitOffset>
  1694. <bitWidth>1</bitWidth>
  1695. </field>
  1696. </fields>
  1697. </register>
  1698. <register>
  1699. <name>CNDTR7</name>
  1700. <displayName>CNDTR7</displayName>
  1701. <description>channel x number of data
  1702. register</description>
  1703. <addressOffset>0x84</addressOffset>
  1704. <size>0x20</size>
  1705. <access>read-write</access>
  1706. <resetValue>0x00000000</resetValue>
  1707. <fields>
  1708. <field>
  1709. <name>NDT</name>
  1710. <description>Number of data to transfer</description>
  1711. <bitOffset>0</bitOffset>
  1712. <bitWidth>16</bitWidth>
  1713. </field>
  1714. </fields>
  1715. </register>
  1716. <register>
  1717. <name>CPAR7</name>
  1718. <displayName>CPAR7</displayName>
  1719. <description>channel x peripheral address
  1720. register</description>
  1721. <addressOffset>0x88</addressOffset>
  1722. <size>0x20</size>
  1723. <access>read-write</access>
  1724. <resetValue>0x00000000</resetValue>
  1725. <fields>
  1726. <field>
  1727. <name>PA</name>
  1728. <description>Peripheral address</description>
  1729. <bitOffset>0</bitOffset>
  1730. <bitWidth>32</bitWidth>
  1731. </field>
  1732. </fields>
  1733. </register>
  1734. <register>
  1735. <name>CMAR7</name>
  1736. <displayName>CMAR7</displayName>
  1737. <description>channel x memory address
  1738. register</description>
  1739. <addressOffset>0x8C</addressOffset>
  1740. <size>0x20</size>
  1741. <access>read-write</access>
  1742. <resetValue>0x00000000</resetValue>
  1743. <fields>
  1744. <field>
  1745. <name>MA</name>
  1746. <description>Memory address</description>
  1747. <bitOffset>0</bitOffset>
  1748. <bitWidth>32</bitWidth>
  1749. </field>
  1750. </fields>
  1751. </register>
  1752. <register>
  1753. <name>CSELR</name>
  1754. <displayName>CSELR</displayName>
  1755. <description>channel selection register</description>
  1756. <addressOffset>0xA8</addressOffset>
  1757. <size>0x20</size>
  1758. <access>read-write</access>
  1759. <resetValue>0x00000000</resetValue>
  1760. <fields>
  1761. <field>
  1762. <name>C7S</name>
  1763. <description>DMA channel 7 selection</description>
  1764. <bitOffset>24</bitOffset>
  1765. <bitWidth>4</bitWidth>
  1766. </field>
  1767. <field>
  1768. <name>C6S</name>
  1769. <description>DMA channel 6 selection</description>
  1770. <bitOffset>20</bitOffset>
  1771. <bitWidth>4</bitWidth>
  1772. </field>
  1773. <field>
  1774. <name>C5S</name>
  1775. <description>DMA channel 5 selection</description>
  1776. <bitOffset>16</bitOffset>
  1777. <bitWidth>4</bitWidth>
  1778. </field>
  1779. <field>
  1780. <name>C4S</name>
  1781. <description>DMA channel 4 selection</description>
  1782. <bitOffset>12</bitOffset>
  1783. <bitWidth>4</bitWidth>
  1784. </field>
  1785. <field>
  1786. <name>C3S</name>
  1787. <description>DMA channel 3 selection</description>
  1788. <bitOffset>8</bitOffset>
  1789. <bitWidth>4</bitWidth>
  1790. </field>
  1791. <field>
  1792. <name>C2S</name>
  1793. <description>DMA channel 2 selection</description>
  1794. <bitOffset>4</bitOffset>
  1795. <bitWidth>4</bitWidth>
  1796. </field>
  1797. <field>
  1798. <name>C1S</name>
  1799. <description>DMA channel 1 selection</description>
  1800. <bitOffset>0</bitOffset>
  1801. <bitWidth>4</bitWidth>
  1802. </field>
  1803. </fields>
  1804. </register>
  1805. </registers>
  1806. </peripheral>
  1807. <peripheral>
  1808. <name>CRC</name>
  1809. <description>Cyclic redundancy check calculation
  1810. unit</description>
  1811. <groupName>CRC</groupName>
  1812. <baseAddress>0x40023000</baseAddress>
  1813. <addressBlock>
  1814. <offset>0x0</offset>
  1815. <size>0x400</size>
  1816. <usage>registers</usage>
  1817. </addressBlock>
  1818. <registers>
  1819. <register>
  1820. <name>DR</name>
  1821. <displayName>DR</displayName>
  1822. <description>Data register</description>
  1823. <addressOffset>0x0</addressOffset>
  1824. <size>0x20</size>
  1825. <access>read-write</access>
  1826. <resetValue>0xFFFFFFFF</resetValue>
  1827. <fields>
  1828. <field>
  1829. <name>DR</name>
  1830. <description>Data register bits</description>
  1831. <bitOffset>0</bitOffset>
  1832. <bitWidth>32</bitWidth>
  1833. </field>
  1834. </fields>
  1835. </register>
  1836. <register>
  1837. <name>IDR</name>
  1838. <displayName>IDR</displayName>
  1839. <description>Independent data register</description>
  1840. <addressOffset>0x4</addressOffset>
  1841. <size>0x20</size>
  1842. <access>read-write</access>
  1843. <resetValue>0x00000000</resetValue>
  1844. <fields>
  1845. <field>
  1846. <name>IDR</name>
  1847. <description>General-purpose 8-bit data register
  1848. bits</description>
  1849. <bitOffset>0</bitOffset>
  1850. <bitWidth>8</bitWidth>
  1851. </field>
  1852. </fields>
  1853. </register>
  1854. <register>
  1855. <name>CR</name>
  1856. <displayName>CR</displayName>
  1857. <description>Control register</description>
  1858. <addressOffset>0x8</addressOffset>
  1859. <size>0x20</size>
  1860. <resetValue>0x00000000</resetValue>
  1861. <fields>
  1862. <field>
  1863. <name>REV_OUT</name>
  1864. <description>Reverse output data</description>
  1865. <bitOffset>7</bitOffset>
  1866. <bitWidth>1</bitWidth>
  1867. <access>read-write</access>
  1868. </field>
  1869. <field>
  1870. <name>REV_IN</name>
  1871. <description>Reverse input data</description>
  1872. <bitOffset>5</bitOffset>
  1873. <bitWidth>2</bitWidth>
  1874. <access>read-write</access>
  1875. </field>
  1876. <field>
  1877. <name>POLYSIZE</name>
  1878. <description>Polynomial size</description>
  1879. <bitOffset>3</bitOffset>
  1880. <bitWidth>2</bitWidth>
  1881. <access>read-write</access>
  1882. </field>
  1883. <field>
  1884. <name>RESET</name>
  1885. <description>RESET bit</description>
  1886. <bitOffset>0</bitOffset>
  1887. <bitWidth>1</bitWidth>
  1888. <access>write-only</access>
  1889. </field>
  1890. </fields>
  1891. </register>
  1892. <register>
  1893. <name>INIT</name>
  1894. <displayName>INIT</displayName>
  1895. <description>Initial CRC value</description>
  1896. <addressOffset>0x10</addressOffset>
  1897. <size>0x20</size>
  1898. <access>read-write</access>
  1899. <resetValue>0xFFFFFFFF</resetValue>
  1900. <fields>
  1901. <field>
  1902. <name>CRC_INIT</name>
  1903. <description>Programmable initial CRC
  1904. value</description>
  1905. <bitOffset>0</bitOffset>
  1906. <bitWidth>32</bitWidth>
  1907. </field>
  1908. </fields>
  1909. </register>
  1910. <register>
  1911. <name>POL</name>
  1912. <displayName>POL</displayName>
  1913. <description>polynomial</description>
  1914. <addressOffset>0x14</addressOffset>
  1915. <size>0x20</size>
  1916. <access>read-write</access>
  1917. <resetValue>0x04C11DB7</resetValue>
  1918. <fields>
  1919. <field>
  1920. <name>Polynomialcoefficients</name>
  1921. <description>Programmable polynomial</description>
  1922. <bitOffset>0</bitOffset>
  1923. <bitWidth>32</bitWidth>
  1924. </field>
  1925. </fields>
  1926. </register>
  1927. </registers>
  1928. </peripheral>
  1929. <peripheral>
  1930. <name>GPIOA</name>
  1931. <description>General-purpose I/Os</description>
  1932. <groupName>GPIO</groupName>
  1933. <baseAddress>0x50000000</baseAddress>
  1934. <addressBlock>
  1935. <offset>0x0</offset>
  1936. <size>0x400</size>
  1937. <usage>registers</usage>
  1938. </addressBlock>
  1939. <registers>
  1940. <register>
  1941. <name>MODER</name>
  1942. <displayName>MODER</displayName>
  1943. <description>GPIO port mode register</description>
  1944. <addressOffset>0x0</addressOffset>
  1945. <size>0x20</size>
  1946. <access>read-write</access>
  1947. <resetValue>0xEBFFFCFF</resetValue>
  1948. <fields>
  1949. <field>
  1950. <name>MODE0</name>
  1951. <description>Port x configuration bits (y =
  1952. 0..15)</description>
  1953. <bitOffset>0</bitOffset>
  1954. <bitWidth>2</bitWidth>
  1955. </field>
  1956. <field>
  1957. <name>MODE1</name>
  1958. <description>Port x configuration bits (y =
  1959. 0..15)</description>
  1960. <bitOffset>2</bitOffset>
  1961. <bitWidth>2</bitWidth>
  1962. </field>
  1963. <field>
  1964. <name>MODE2</name>
  1965. <description>Port x configuration bits (y =
  1966. 0..15)</description>
  1967. <bitOffset>4</bitOffset>
  1968. <bitWidth>2</bitWidth>
  1969. </field>
  1970. <field>
  1971. <name>MODE3</name>
  1972. <description>Port x configuration bits (y =
  1973. 0..15)</description>
  1974. <bitOffset>6</bitOffset>
  1975. <bitWidth>2</bitWidth>
  1976. </field>
  1977. <field>
  1978. <name>MODE4</name>
  1979. <description>Port x configuration bits (y =
  1980. 0..15)</description>
  1981. <bitOffset>8</bitOffset>
  1982. <bitWidth>2</bitWidth>
  1983. </field>
  1984. <field>
  1985. <name>MODE5</name>
  1986. <description>Port x configuration bits (y =
  1987. 0..15)</description>
  1988. <bitOffset>10</bitOffset>
  1989. <bitWidth>2</bitWidth>
  1990. </field>
  1991. <field>
  1992. <name>MODE6</name>
  1993. <description>Port x configuration bits (y =
  1994. 0..15)</description>
  1995. <bitOffset>12</bitOffset>
  1996. <bitWidth>2</bitWidth>
  1997. </field>
  1998. <field>
  1999. <name>MODE7</name>
  2000. <description>Port x configuration bits (y =
  2001. 0..15)</description>
  2002. <bitOffset>14</bitOffset>
  2003. <bitWidth>2</bitWidth>
  2004. </field>
  2005. <field>
  2006. <name>MODE8</name>
  2007. <description>Port x configuration bits (y =
  2008. 0..15)</description>
  2009. <bitOffset>16</bitOffset>
  2010. <bitWidth>2</bitWidth>
  2011. </field>
  2012. <field>
  2013. <name>MODE9</name>
  2014. <description>Port x configuration bits (y =
  2015. 0..15)</description>
  2016. <bitOffset>18</bitOffset>
  2017. <bitWidth>2</bitWidth>
  2018. </field>
  2019. <field>
  2020. <name>MODE10</name>
  2021. <description>Port x configuration bits (y =
  2022. 0..15)</description>
  2023. <bitOffset>20</bitOffset>
  2024. <bitWidth>2</bitWidth>
  2025. </field>
  2026. <field>
  2027. <name>MODE11</name>
  2028. <description>Port x configuration bits (y =
  2029. 0..15)</description>
  2030. <bitOffset>22</bitOffset>
  2031. <bitWidth>2</bitWidth>
  2032. </field>
  2033. <field>
  2034. <name>MODE12</name>
  2035. <description>Port x configuration bits (y =
  2036. 0..15)</description>
  2037. <bitOffset>24</bitOffset>
  2038. <bitWidth>2</bitWidth>
  2039. </field>
  2040. <field>
  2041. <name>MODE13</name>
  2042. <description>Port x configuration bits (y =
  2043. 0..15)</description>
  2044. <bitOffset>26</bitOffset>
  2045. <bitWidth>2</bitWidth>
  2046. </field>
  2047. <field>
  2048. <name>MODE14</name>
  2049. <description>Port x configuration bits (y =
  2050. 0..15)</description>
  2051. <bitOffset>28</bitOffset>
  2052. <bitWidth>2</bitWidth>
  2053. </field>
  2054. <field>
  2055. <name>MODE15</name>
  2056. <description>Port x configuration bits (y =
  2057. 0..15)</description>
  2058. <bitOffset>30</bitOffset>
  2059. <bitWidth>2</bitWidth>
  2060. </field>
  2061. </fields>
  2062. </register>
  2063. <register>
  2064. <name>OTYPER</name>
  2065. <displayName>OTYPER</displayName>
  2066. <description>GPIO port output type register</description>
  2067. <addressOffset>0x4</addressOffset>
  2068. <size>0x20</size>
  2069. <access>read-write</access>
  2070. <resetValue>0x00000000</resetValue>
  2071. <fields>
  2072. <field>
  2073. <name>OT15</name>
  2074. <description>Port x configuration bits (y =
  2075. 0..15)</description>
  2076. <bitOffset>15</bitOffset>
  2077. <bitWidth>1</bitWidth>
  2078. </field>
  2079. <field>
  2080. <name>OT14</name>
  2081. <description>Port x configuration bits (y =
  2082. 0..15)</description>
  2083. <bitOffset>14</bitOffset>
  2084. <bitWidth>1</bitWidth>
  2085. </field>
  2086. <field>
  2087. <name>OT13</name>
  2088. <description>Port x configuration bits (y =
  2089. 0..15)</description>
  2090. <bitOffset>13</bitOffset>
  2091. <bitWidth>1</bitWidth>
  2092. </field>
  2093. <field>
  2094. <name>OT12</name>
  2095. <description>Port x configuration bits (y =
  2096. 0..15)</description>
  2097. <bitOffset>12</bitOffset>
  2098. <bitWidth>1</bitWidth>
  2099. </field>
  2100. <field>
  2101. <name>OT11</name>
  2102. <description>Port x configuration bits (y =
  2103. 0..15)</description>
  2104. <bitOffset>11</bitOffset>
  2105. <bitWidth>1</bitWidth>
  2106. </field>
  2107. <field>
  2108. <name>OT10</name>
  2109. <description>Port x configuration bits (y =
  2110. 0..15)</description>
  2111. <bitOffset>10</bitOffset>
  2112. <bitWidth>1</bitWidth>
  2113. </field>
  2114. <field>
  2115. <name>OT9</name>
  2116. <description>Port x configuration bits (y =
  2117. 0..15)</description>
  2118. <bitOffset>9</bitOffset>
  2119. <bitWidth>1</bitWidth>
  2120. </field>
  2121. <field>
  2122. <name>OT8</name>
  2123. <description>Port x configuration bits (y =
  2124. 0..15)</description>
  2125. <bitOffset>8</bitOffset>
  2126. <bitWidth>1</bitWidth>
  2127. </field>
  2128. <field>
  2129. <name>OT7</name>
  2130. <description>Port x configuration bits (y =
  2131. 0..15)</description>
  2132. <bitOffset>7</bitOffset>
  2133. <bitWidth>1</bitWidth>
  2134. </field>
  2135. <field>
  2136. <name>OT6</name>
  2137. <description>Port x configuration bits (y =
  2138. 0..15)</description>
  2139. <bitOffset>6</bitOffset>
  2140. <bitWidth>1</bitWidth>
  2141. </field>
  2142. <field>
  2143. <name>OT5</name>
  2144. <description>Port x configuration bits (y =
  2145. 0..15)</description>
  2146. <bitOffset>5</bitOffset>
  2147. <bitWidth>1</bitWidth>
  2148. </field>
  2149. <field>
  2150. <name>OT4</name>
  2151. <description>Port x configuration bits (y =
  2152. 0..15)</description>
  2153. <bitOffset>4</bitOffset>
  2154. <bitWidth>1</bitWidth>
  2155. </field>
  2156. <field>
  2157. <name>OT3</name>
  2158. <description>Port x configuration bits (y =
  2159. 0..15)</description>
  2160. <bitOffset>3</bitOffset>
  2161. <bitWidth>1</bitWidth>
  2162. </field>
  2163. <field>
  2164. <name>OT2</name>
  2165. <description>Port x configuration bits (y =
  2166. 0..15)</description>
  2167. <bitOffset>2</bitOffset>
  2168. <bitWidth>1</bitWidth>
  2169. </field>
  2170. <field>
  2171. <name>OT1</name>
  2172. <description>Port x configuration bits (y =
  2173. 0..15)</description>
  2174. <bitOffset>1</bitOffset>
  2175. <bitWidth>1</bitWidth>
  2176. </field>
  2177. <field>
  2178. <name>OT0</name>
  2179. <description>Port x configuration bits (y =
  2180. 0..15)</description>
  2181. <bitOffset>0</bitOffset>
  2182. <bitWidth>1</bitWidth>
  2183. </field>
  2184. </fields>
  2185. </register>
  2186. <register>
  2187. <name>OSPEEDR</name>
  2188. <displayName>OSPEEDR</displayName>
  2189. <description>GPIO port output speed
  2190. register</description>
  2191. <addressOffset>0x8</addressOffset>
  2192. <size>0x20</size>
  2193. <access>read-write</access>
  2194. <resetValue>0x00000000</resetValue>
  2195. <fields>
  2196. <field>
  2197. <name>OSPEED15</name>
  2198. <description>Port x configuration bits (y =
  2199. 0..15)</description>
  2200. <bitOffset>30</bitOffset>
  2201. <bitWidth>2</bitWidth>
  2202. </field>
  2203. <field>
  2204. <name>OSPEED14</name>
  2205. <description>Port x configuration bits (y =
  2206. 0..15)</description>
  2207. <bitOffset>28</bitOffset>
  2208. <bitWidth>2</bitWidth>
  2209. </field>
  2210. <field>
  2211. <name>OSPEED13</name>
  2212. <description>Port x configuration bits (y =
  2213. 0..15)</description>
  2214. <bitOffset>26</bitOffset>
  2215. <bitWidth>2</bitWidth>
  2216. </field>
  2217. <field>
  2218. <name>OSPEED12</name>
  2219. <description>Port x configuration bits (y =
  2220. 0..15)</description>
  2221. <bitOffset>24</bitOffset>
  2222. <bitWidth>2</bitWidth>
  2223. </field>
  2224. <field>
  2225. <name>OSPEED11</name>
  2226. <description>Port x configuration bits (y =
  2227. 0..15)</description>
  2228. <bitOffset>22</bitOffset>
  2229. <bitWidth>2</bitWidth>
  2230. </field>
  2231. <field>
  2232. <name>OSPEED10</name>
  2233. <description>Port x configuration bits (y =
  2234. 0..15)</description>
  2235. <bitOffset>20</bitOffset>
  2236. <bitWidth>2</bitWidth>
  2237. </field>
  2238. <field>
  2239. <name>OSPEED9</name>
  2240. <description>Port x configuration bits (y =
  2241. 0..15)</description>
  2242. <bitOffset>18</bitOffset>
  2243. <bitWidth>2</bitWidth>
  2244. </field>
  2245. <field>
  2246. <name>OSPEED8</name>
  2247. <description>Port x configuration bits (y =
  2248. 0..15)</description>
  2249. <bitOffset>16</bitOffset>
  2250. <bitWidth>2</bitWidth>
  2251. </field>
  2252. <field>
  2253. <name>OSPEED7</name>
  2254. <description>Port x configuration bits (y =
  2255. 0..15)</description>
  2256. <bitOffset>14</bitOffset>
  2257. <bitWidth>2</bitWidth>
  2258. </field>
  2259. <field>
  2260. <name>OSPEED6</name>
  2261. <description>Port x configuration bits (y =
  2262. 0..15)</description>
  2263. <bitOffset>12</bitOffset>
  2264. <bitWidth>2</bitWidth>
  2265. </field>
  2266. <field>
  2267. <name>OSPEED5</name>
  2268. <description>Port x configuration bits (y =
  2269. 0..15)</description>
  2270. <bitOffset>10</bitOffset>
  2271. <bitWidth>2</bitWidth>
  2272. </field>
  2273. <field>
  2274. <name>OSPEED4</name>
  2275. <description>Port x configuration bits (y =
  2276. 0..15)</description>
  2277. <bitOffset>8</bitOffset>
  2278. <bitWidth>2</bitWidth>
  2279. </field>
  2280. <field>
  2281. <name>OSPEED3</name>
  2282. <description>Port x configuration bits (y =
  2283. 0..15)</description>
  2284. <bitOffset>6</bitOffset>
  2285. <bitWidth>2</bitWidth>
  2286. </field>
  2287. <field>
  2288. <name>OSPEED2</name>
  2289. <description>Port x configuration bits (y =
  2290. 0..15)</description>
  2291. <bitOffset>4</bitOffset>
  2292. <bitWidth>2</bitWidth>
  2293. </field>
  2294. <field>
  2295. <name>OSPEED1</name>
  2296. <description>Port x configuration bits (y =
  2297. 0..15)</description>
  2298. <bitOffset>2</bitOffset>
  2299. <bitWidth>2</bitWidth>
  2300. </field>
  2301. <field>
  2302. <name>OSPEED0</name>
  2303. <description>Port x configuration bits (y =
  2304. 0..15)</description>
  2305. <bitOffset>0</bitOffset>
  2306. <bitWidth>2</bitWidth>
  2307. </field>
  2308. </fields>
  2309. </register>
  2310. <register>
  2311. <name>PUPDR</name>
  2312. <displayName>PUPDR</displayName>
  2313. <description>GPIO port pull-up/pull-down
  2314. register</description>
  2315. <addressOffset>0xC</addressOffset>
  2316. <size>0x20</size>
  2317. <access>read-write</access>
  2318. <resetValue>0x24000000</resetValue>
  2319. <fields>
  2320. <field>
  2321. <name>PUPD15</name>
  2322. <description>Port x configuration bits (y =
  2323. 0..15)</description>
  2324. <bitOffset>30</bitOffset>
  2325. <bitWidth>2</bitWidth>
  2326. </field>
  2327. <field>
  2328. <name>PUPD14</name>
  2329. <description>Port x configuration bits (y =
  2330. 0..15)</description>
  2331. <bitOffset>28</bitOffset>
  2332. <bitWidth>2</bitWidth>
  2333. </field>
  2334. <field>
  2335. <name>PUPD13</name>
  2336. <description>Port x configuration bits (y =
  2337. 0..15)</description>
  2338. <bitOffset>26</bitOffset>
  2339. <bitWidth>2</bitWidth>
  2340. </field>
  2341. <field>
  2342. <name>PUPD12</name>
  2343. <description>Port x configuration bits (y =
  2344. 0..15)</description>
  2345. <bitOffset>24</bitOffset>
  2346. <bitWidth>2</bitWidth>
  2347. </field>
  2348. <field>
  2349. <name>PUPD11</name>
  2350. <description>Port x configuration bits (y =
  2351. 0..15)</description>
  2352. <bitOffset>22</bitOffset>
  2353. <bitWidth>2</bitWidth>
  2354. </field>
  2355. <field>
  2356. <name>PUPD10</name>
  2357. <description>Port x configuration bits (y =
  2358. 0..15)</description>
  2359. <bitOffset>20</bitOffset>
  2360. <bitWidth>2</bitWidth>
  2361. </field>
  2362. <field>
  2363. <name>PUPD9</name>
  2364. <description>Port x configuration bits (y =
  2365. 0..15)</description>
  2366. <bitOffset>18</bitOffset>
  2367. <bitWidth>2</bitWidth>
  2368. </field>
  2369. <field>
  2370. <name>PUPD8</name>
  2371. <description>Port x configuration bits (y =
  2372. 0..15)</description>
  2373. <bitOffset>16</bitOffset>
  2374. <bitWidth>2</bitWidth>
  2375. </field>
  2376. <field>
  2377. <name>PUPD7</name>
  2378. <description>Port x configuration bits (y =
  2379. 0..15)</description>
  2380. <bitOffset>14</bitOffset>
  2381. <bitWidth>2</bitWidth>
  2382. </field>
  2383. <field>
  2384. <name>PUPD6</name>
  2385. <description>Port x configuration bits (y =
  2386. 0..15)</description>
  2387. <bitOffset>12</bitOffset>
  2388. <bitWidth>2</bitWidth>
  2389. </field>
  2390. <field>
  2391. <name>PUPD5</name>
  2392. <description>Port x configuration bits (y =
  2393. 0..15)</description>
  2394. <bitOffset>10</bitOffset>
  2395. <bitWidth>2</bitWidth>
  2396. </field>
  2397. <field>
  2398. <name>PUPD4</name>
  2399. <description>Port x configuration bits (y =
  2400. 0..15)</description>
  2401. <bitOffset>8</bitOffset>
  2402. <bitWidth>2</bitWidth>
  2403. </field>
  2404. <field>
  2405. <name>PUPD3</name>
  2406. <description>Port x configuration bits (y =
  2407. 0..15)</description>
  2408. <bitOffset>6</bitOffset>
  2409. <bitWidth>2</bitWidth>
  2410. </field>
  2411. <field>
  2412. <name>PUPD2</name>
  2413. <description>Port x configuration bits (y =
  2414. 0..15)</description>
  2415. <bitOffset>4</bitOffset>
  2416. <bitWidth>2</bitWidth>
  2417. </field>
  2418. <field>
  2419. <name>PUPD1</name>
  2420. <description>Port x configuration bits (y =
  2421. 0..15)</description>
  2422. <bitOffset>2</bitOffset>
  2423. <bitWidth>2</bitWidth>
  2424. </field>
  2425. <field>
  2426. <name>PUPD0</name>
  2427. <description>Port x configuration bits (y =
  2428. 0..15)</description>
  2429. <bitOffset>0</bitOffset>
  2430. <bitWidth>2</bitWidth>
  2431. </field>
  2432. </fields>
  2433. </register>
  2434. <register>
  2435. <name>IDR</name>
  2436. <displayName>IDR</displayName>
  2437. <description>GPIO port input data register</description>
  2438. <addressOffset>0x10</addressOffset>
  2439. <size>0x20</size>
  2440. <access>read-only</access>
  2441. <resetValue>0x00000000</resetValue>
  2442. <fields>
  2443. <field>
  2444. <name>ID15</name>
  2445. <description>Port input data bit (y =
  2446. 0..15)</description>
  2447. <bitOffset>15</bitOffset>
  2448. <bitWidth>1</bitWidth>
  2449. </field>
  2450. <field>
  2451. <name>ID14</name>
  2452. <description>Port input data bit (y =
  2453. 0..15)</description>
  2454. <bitOffset>14</bitOffset>
  2455. <bitWidth>1</bitWidth>
  2456. </field>
  2457. <field>
  2458. <name>ID13</name>
  2459. <description>Port input data bit (y =
  2460. 0..15)</description>
  2461. <bitOffset>13</bitOffset>
  2462. <bitWidth>1</bitWidth>
  2463. </field>
  2464. <field>
  2465. <name>ID12</name>
  2466. <description>Port input data bit (y =
  2467. 0..15)</description>
  2468. <bitOffset>12</bitOffset>
  2469. <bitWidth>1</bitWidth>
  2470. </field>
  2471. <field>
  2472. <name>ID11</name>
  2473. <description>Port input data bit (y =
  2474. 0..15)</description>
  2475. <bitOffset>11</bitOffset>
  2476. <bitWidth>1</bitWidth>
  2477. </field>
  2478. <field>
  2479. <name>ID10</name>
  2480. <description>Port input data bit (y =
  2481. 0..15)</description>
  2482. <bitOffset>10</bitOffset>
  2483. <bitWidth>1</bitWidth>
  2484. </field>
  2485. <field>
  2486. <name>ID9</name>
  2487. <description>Port input data bit (y =
  2488. 0..15)</description>
  2489. <bitOffset>9</bitOffset>
  2490. <bitWidth>1</bitWidth>
  2491. </field>
  2492. <field>
  2493. <name>ID8</name>
  2494. <description>Port input data bit (y =
  2495. 0..15)</description>
  2496. <bitOffset>8</bitOffset>
  2497. <bitWidth>1</bitWidth>
  2498. </field>
  2499. <field>
  2500. <name>ID7</name>
  2501. <description>Port input data bit (y =
  2502. 0..15)</description>
  2503. <bitOffset>7</bitOffset>
  2504. <bitWidth>1</bitWidth>
  2505. </field>
  2506. <field>
  2507. <name>ID6</name>
  2508. <description>Port input data bit (y =
  2509. 0..15)</description>
  2510. <bitOffset>6</bitOffset>
  2511. <bitWidth>1</bitWidth>
  2512. </field>
  2513. <field>
  2514. <name>ID5</name>
  2515. <description>Port input data bit (y =
  2516. 0..15)</description>
  2517. <bitOffset>5</bitOffset>
  2518. <bitWidth>1</bitWidth>
  2519. </field>
  2520. <field>
  2521. <name>ID4</name>
  2522. <description>Port input data bit (y =
  2523. 0..15)</description>
  2524. <bitOffset>4</bitOffset>
  2525. <bitWidth>1</bitWidth>
  2526. </field>
  2527. <field>
  2528. <name>ID3</name>
  2529. <description>Port input data bit (y =
  2530. 0..15)</description>
  2531. <bitOffset>3</bitOffset>
  2532. <bitWidth>1</bitWidth>
  2533. </field>
  2534. <field>
  2535. <name>ID2</name>
  2536. <description>Port input data bit (y =
  2537. 0..15)</description>
  2538. <bitOffset>2</bitOffset>
  2539. <bitWidth>1</bitWidth>
  2540. </field>
  2541. <field>
  2542. <name>ID1</name>
  2543. <description>Port input data bit (y =
  2544. 0..15)</description>
  2545. <bitOffset>1</bitOffset>
  2546. <bitWidth>1</bitWidth>
  2547. </field>
  2548. <field>
  2549. <name>ID0</name>
  2550. <description>Port input data bit (y =
  2551. 0..15)</description>
  2552. <bitOffset>0</bitOffset>
  2553. <bitWidth>1</bitWidth>
  2554. </field>
  2555. </fields>
  2556. </register>
  2557. <register>
  2558. <name>ODR</name>
  2559. <displayName>ODR</displayName>
  2560. <description>GPIO port output data register</description>
  2561. <addressOffset>0x14</addressOffset>
  2562. <size>0x20</size>
  2563. <access>read-write</access>
  2564. <resetValue>0x00000000</resetValue>
  2565. <fields>
  2566. <field>
  2567. <name>OD15</name>
  2568. <description>Port output data bit (y =
  2569. 0..15)</description>
  2570. <bitOffset>15</bitOffset>
  2571. <bitWidth>1</bitWidth>
  2572. </field>
  2573. <field>
  2574. <name>OD14</name>
  2575. <description>Port output data bit (y =
  2576. 0..15)</description>
  2577. <bitOffset>14</bitOffset>
  2578. <bitWidth>1</bitWidth>
  2579. </field>
  2580. <field>
  2581. <name>OD13</name>
  2582. <description>Port output data bit (y =
  2583. 0..15)</description>
  2584. <bitOffset>13</bitOffset>
  2585. <bitWidth>1</bitWidth>
  2586. </field>
  2587. <field>
  2588. <name>OD12</name>
  2589. <description>Port output data bit (y =
  2590. 0..15)</description>
  2591. <bitOffset>12</bitOffset>
  2592. <bitWidth>1</bitWidth>
  2593. </field>
  2594. <field>
  2595. <name>OD11</name>
  2596. <description>Port output data bit (y =
  2597. 0..15)</description>
  2598. <bitOffset>11</bitOffset>
  2599. <bitWidth>1</bitWidth>
  2600. </field>
  2601. <field>
  2602. <name>OD10</name>
  2603. <description>Port output data bit (y =
  2604. 0..15)</description>
  2605. <bitOffset>10</bitOffset>
  2606. <bitWidth>1</bitWidth>
  2607. </field>
  2608. <field>
  2609. <name>OD9</name>
  2610. <description>Port output data bit (y =
  2611. 0..15)</description>
  2612. <bitOffset>9</bitOffset>
  2613. <bitWidth>1</bitWidth>
  2614. </field>
  2615. <field>
  2616. <name>OD8</name>
  2617. <description>Port output data bit (y =
  2618. 0..15)</description>
  2619. <bitOffset>8</bitOffset>
  2620. <bitWidth>1</bitWidth>
  2621. </field>
  2622. <field>
  2623. <name>OD7</name>
  2624. <description>Port output data bit (y =
  2625. 0..15)</description>
  2626. <bitOffset>7</bitOffset>
  2627. <bitWidth>1</bitWidth>
  2628. </field>
  2629. <field>
  2630. <name>OD6</name>
  2631. <description>Port output data bit (y =
  2632. 0..15)</description>
  2633. <bitOffset>6</bitOffset>
  2634. <bitWidth>1</bitWidth>
  2635. </field>
  2636. <field>
  2637. <name>OD5</name>
  2638. <description>Port output data bit (y =
  2639. 0..15)</description>
  2640. <bitOffset>5</bitOffset>
  2641. <bitWidth>1</bitWidth>
  2642. </field>
  2643. <field>
  2644. <name>OD4</name>
  2645. <description>Port output data bit (y =
  2646. 0..15)</description>
  2647. <bitOffset>4</bitOffset>
  2648. <bitWidth>1</bitWidth>
  2649. </field>
  2650. <field>
  2651. <name>OD3</name>
  2652. <description>Port output data bit (y =
  2653. 0..15)</description>
  2654. <bitOffset>3</bitOffset>
  2655. <bitWidth>1</bitWidth>
  2656. </field>
  2657. <field>
  2658. <name>OD2</name>
  2659. <description>Port output data bit (y =
  2660. 0..15)</description>
  2661. <bitOffset>2</bitOffset>
  2662. <bitWidth>1</bitWidth>
  2663. </field>
  2664. <field>
  2665. <name>OD1</name>
  2666. <description>Port output data bit (y =
  2667. 0..15)</description>
  2668. <bitOffset>1</bitOffset>
  2669. <bitWidth>1</bitWidth>
  2670. </field>
  2671. <field>
  2672. <name>OD0</name>
  2673. <description>Port output data bit (y =
  2674. 0..15)</description>
  2675. <bitOffset>0</bitOffset>
  2676. <bitWidth>1</bitWidth>
  2677. </field>
  2678. </fields>
  2679. </register>
  2680. <register>
  2681. <name>BSRR</name>
  2682. <displayName>BSRR</displayName>
  2683. <description>GPIO port bit set/reset
  2684. register</description>
  2685. <addressOffset>0x18</addressOffset>
  2686. <size>0x20</size>
  2687. <access>write-only</access>
  2688. <resetValue>0x00000000</resetValue>
  2689. <fields>
  2690. <field>
  2691. <name>BR15</name>
  2692. <description>Port x reset bit y (y =
  2693. 0..15)</description>
  2694. <bitOffset>31</bitOffset>
  2695. <bitWidth>1</bitWidth>
  2696. </field>
  2697. <field>
  2698. <name>BR14</name>
  2699. <description>Port x reset bit y (y =
  2700. 0..15)</description>
  2701. <bitOffset>30</bitOffset>
  2702. <bitWidth>1</bitWidth>
  2703. </field>
  2704. <field>
  2705. <name>BR13</name>
  2706. <description>Port x reset bit y (y =
  2707. 0..15)</description>
  2708. <bitOffset>29</bitOffset>
  2709. <bitWidth>1</bitWidth>
  2710. </field>
  2711. <field>
  2712. <name>BR12</name>
  2713. <description>Port x reset bit y (y =
  2714. 0..15)</description>
  2715. <bitOffset>28</bitOffset>
  2716. <bitWidth>1</bitWidth>
  2717. </field>
  2718. <field>
  2719. <name>BR11</name>
  2720. <description>Port x reset bit y (y =
  2721. 0..15)</description>
  2722. <bitOffset>27</bitOffset>
  2723. <bitWidth>1</bitWidth>
  2724. </field>
  2725. <field>
  2726. <name>BR10</name>
  2727. <description>Port x reset bit y (y =
  2728. 0..15)</description>
  2729. <bitOffset>26</bitOffset>
  2730. <bitWidth>1</bitWidth>
  2731. </field>
  2732. <field>
  2733. <name>BR9</name>
  2734. <description>Port x reset bit y (y =
  2735. 0..15)</description>
  2736. <bitOffset>25</bitOffset>
  2737. <bitWidth>1</bitWidth>
  2738. </field>
  2739. <field>
  2740. <name>BR8</name>
  2741. <description>Port x reset bit y (y =
  2742. 0..15)</description>
  2743. <bitOffset>24</bitOffset>
  2744. <bitWidth>1</bitWidth>
  2745. </field>
  2746. <field>
  2747. <name>BR7</name>
  2748. <description>Port x reset bit y (y =
  2749. 0..15)</description>
  2750. <bitOffset>23</bitOffset>
  2751. <bitWidth>1</bitWidth>
  2752. </field>
  2753. <field>
  2754. <name>BR6</name>
  2755. <description>Port x reset bit y (y =
  2756. 0..15)</description>
  2757. <bitOffset>22</bitOffset>
  2758. <bitWidth>1</bitWidth>
  2759. </field>
  2760. <field>
  2761. <name>BR5</name>
  2762. <description>Port x reset bit y (y =
  2763. 0..15)</description>
  2764. <bitOffset>21</bitOffset>
  2765. <bitWidth>1</bitWidth>
  2766. </field>
  2767. <field>
  2768. <name>BR4</name>
  2769. <description>Port x reset bit y (y =
  2770. 0..15)</description>
  2771. <bitOffset>20</bitOffset>
  2772. <bitWidth>1</bitWidth>
  2773. </field>
  2774. <field>
  2775. <name>BR3</name>
  2776. <description>Port x reset bit y (y =
  2777. 0..15)</description>
  2778. <bitOffset>19</bitOffset>
  2779. <bitWidth>1</bitWidth>
  2780. </field>
  2781. <field>
  2782. <name>BR2</name>
  2783. <description>Port x reset bit y (y =
  2784. 0..15)</description>
  2785. <bitOffset>18</bitOffset>
  2786. <bitWidth>1</bitWidth>
  2787. </field>
  2788. <field>
  2789. <name>BR1</name>
  2790. <description>Port x reset bit y (y =
  2791. 0..15)</description>
  2792. <bitOffset>17</bitOffset>
  2793. <bitWidth>1</bitWidth>
  2794. </field>
  2795. <field>
  2796. <name>BR0</name>
  2797. <description>Port x reset bit y (y =
  2798. 0..15)</description>
  2799. <bitOffset>16</bitOffset>
  2800. <bitWidth>1</bitWidth>
  2801. </field>
  2802. <field>
  2803. <name>BS15</name>
  2804. <description>Port x set bit y (y=
  2805. 0..15)</description>
  2806. <bitOffset>15</bitOffset>
  2807. <bitWidth>1</bitWidth>
  2808. </field>
  2809. <field>
  2810. <name>BS14</name>
  2811. <description>Port x set bit y (y=
  2812. 0..15)</description>
  2813. <bitOffset>14</bitOffset>
  2814. <bitWidth>1</bitWidth>
  2815. </field>
  2816. <field>
  2817. <name>BS13</name>
  2818. <description>Port x set bit y (y=
  2819. 0..15)</description>
  2820. <bitOffset>13</bitOffset>
  2821. <bitWidth>1</bitWidth>
  2822. </field>
  2823. <field>
  2824. <name>BS12</name>
  2825. <description>Port x set bit y (y=
  2826. 0..15)</description>
  2827. <bitOffset>12</bitOffset>
  2828. <bitWidth>1</bitWidth>
  2829. </field>
  2830. <field>
  2831. <name>BS11</name>
  2832. <description>Port x set bit y (y=
  2833. 0..15)</description>
  2834. <bitOffset>11</bitOffset>
  2835. <bitWidth>1</bitWidth>
  2836. </field>
  2837. <field>
  2838. <name>BS10</name>
  2839. <description>Port x set bit y (y=
  2840. 0..15)</description>
  2841. <bitOffset>10</bitOffset>
  2842. <bitWidth>1</bitWidth>
  2843. </field>
  2844. <field>
  2845. <name>BS9</name>
  2846. <description>Port x set bit y (y=
  2847. 0..15)</description>
  2848. <bitOffset>9</bitOffset>
  2849. <bitWidth>1</bitWidth>
  2850. </field>
  2851. <field>
  2852. <name>BS8</name>
  2853. <description>Port x set bit y (y=
  2854. 0..15)</description>
  2855. <bitOffset>8</bitOffset>
  2856. <bitWidth>1</bitWidth>
  2857. </field>
  2858. <field>
  2859. <name>BS7</name>
  2860. <description>Port x set bit y (y=
  2861. 0..15)</description>
  2862. <bitOffset>7</bitOffset>
  2863. <bitWidth>1</bitWidth>
  2864. </field>
  2865. <field>
  2866. <name>BS6</name>
  2867. <description>Port x set bit y (y=
  2868. 0..15)</description>
  2869. <bitOffset>6</bitOffset>
  2870. <bitWidth>1</bitWidth>
  2871. </field>
  2872. <field>
  2873. <name>BS5</name>
  2874. <description>Port x set bit y (y=
  2875. 0..15)</description>
  2876. <bitOffset>5</bitOffset>
  2877. <bitWidth>1</bitWidth>
  2878. </field>
  2879. <field>
  2880. <name>BS4</name>
  2881. <description>Port x set bit y (y=
  2882. 0..15)</description>
  2883. <bitOffset>4</bitOffset>
  2884. <bitWidth>1</bitWidth>
  2885. </field>
  2886. <field>
  2887. <name>BS3</name>
  2888. <description>Port x set bit y (y=
  2889. 0..15)</description>
  2890. <bitOffset>3</bitOffset>
  2891. <bitWidth>1</bitWidth>
  2892. </field>
  2893. <field>
  2894. <name>BS2</name>
  2895. <description>Port x set bit y (y=
  2896. 0..15)</description>
  2897. <bitOffset>2</bitOffset>
  2898. <bitWidth>1</bitWidth>
  2899. </field>
  2900. <field>
  2901. <name>BS1</name>
  2902. <description>Port x set bit y (y=
  2903. 0..15)</description>
  2904. <bitOffset>1</bitOffset>
  2905. <bitWidth>1</bitWidth>
  2906. </field>
  2907. <field>
  2908. <name>BS0</name>
  2909. <description>Port x set bit y (y=
  2910. 0..15)</description>
  2911. <bitOffset>0</bitOffset>
  2912. <bitWidth>1</bitWidth>
  2913. </field>
  2914. </fields>
  2915. </register>
  2916. <register>
  2917. <name>LCKR</name>
  2918. <displayName>LCKR</displayName>
  2919. <description>GPIO port configuration lock
  2920. register</description>
  2921. <addressOffset>0x1C</addressOffset>
  2922. <size>0x20</size>
  2923. <access>read-write</access>
  2924. <resetValue>0x00000000</resetValue>
  2925. <fields>
  2926. <field>
  2927. <name>LCKK</name>
  2928. <description>Port x lock bit y (y=
  2929. 0..15)</description>
  2930. <bitOffset>16</bitOffset>
  2931. <bitWidth>1</bitWidth>
  2932. </field>
  2933. <field>
  2934. <name>LCK15</name>
  2935. <description>Port x lock bit y (y=
  2936. 0..15)</description>
  2937. <bitOffset>15</bitOffset>
  2938. <bitWidth>1</bitWidth>
  2939. </field>
  2940. <field>
  2941. <name>LCK14</name>
  2942. <description>Port x lock bit y (y=
  2943. 0..15)</description>
  2944. <bitOffset>14</bitOffset>
  2945. <bitWidth>1</bitWidth>
  2946. </field>
  2947. <field>
  2948. <name>LCK13</name>
  2949. <description>Port x lock bit y (y=
  2950. 0..15)</description>
  2951. <bitOffset>13</bitOffset>
  2952. <bitWidth>1</bitWidth>
  2953. </field>
  2954. <field>
  2955. <name>LCK12</name>
  2956. <description>Port x lock bit y (y=
  2957. 0..15)</description>
  2958. <bitOffset>12</bitOffset>
  2959. <bitWidth>1</bitWidth>
  2960. </field>
  2961. <field>
  2962. <name>LCK11</name>
  2963. <description>Port x lock bit y (y=
  2964. 0..15)</description>
  2965. <bitOffset>11</bitOffset>
  2966. <bitWidth>1</bitWidth>
  2967. </field>
  2968. <field>
  2969. <name>LCK10</name>
  2970. <description>Port x lock bit y (y=
  2971. 0..15)</description>
  2972. <bitOffset>10</bitOffset>
  2973. <bitWidth>1</bitWidth>
  2974. </field>
  2975. <field>
  2976. <name>LCK9</name>
  2977. <description>Port x lock bit y (y=
  2978. 0..15)</description>
  2979. <bitOffset>9</bitOffset>
  2980. <bitWidth>1</bitWidth>
  2981. </field>
  2982. <field>
  2983. <name>LCK8</name>
  2984. <description>Port x lock bit y (y=
  2985. 0..15)</description>
  2986. <bitOffset>8</bitOffset>
  2987. <bitWidth>1</bitWidth>
  2988. </field>
  2989. <field>
  2990. <name>LCK7</name>
  2991. <description>Port x lock bit y (y=
  2992. 0..15)</description>
  2993. <bitOffset>7</bitOffset>
  2994. <bitWidth>1</bitWidth>
  2995. </field>
  2996. <field>
  2997. <name>LCK6</name>
  2998. <description>Port x lock bit y (y=
  2999. 0..15)</description>
  3000. <bitOffset>6</bitOffset>
  3001. <bitWidth>1</bitWidth>
  3002. </field>
  3003. <field>
  3004. <name>LCK5</name>
  3005. <description>Port x lock bit y (y=
  3006. 0..15)</description>
  3007. <bitOffset>5</bitOffset>
  3008. <bitWidth>1</bitWidth>
  3009. </field>
  3010. <field>
  3011. <name>LCK4</name>
  3012. <description>Port x lock bit y (y=
  3013. 0..15)</description>
  3014. <bitOffset>4</bitOffset>
  3015. <bitWidth>1</bitWidth>
  3016. </field>
  3017. <field>
  3018. <name>LCK3</name>
  3019. <description>Port x lock bit y (y=
  3020. 0..15)</description>
  3021. <bitOffset>3</bitOffset>
  3022. <bitWidth>1</bitWidth>
  3023. </field>
  3024. <field>
  3025. <name>LCK2</name>
  3026. <description>Port x lock bit y (y=
  3027. 0..15)</description>
  3028. <bitOffset>2</bitOffset>
  3029. <bitWidth>1</bitWidth>
  3030. </field>
  3031. <field>
  3032. <name>LCK1</name>
  3033. <description>Port x lock bit y (y=
  3034. 0..15)</description>
  3035. <bitOffset>1</bitOffset>
  3036. <bitWidth>1</bitWidth>
  3037. </field>
  3038. <field>
  3039. <name>LCK0</name>
  3040. <description>Port x lock bit y (y=
  3041. 0..15)</description>
  3042. <bitOffset>0</bitOffset>
  3043. <bitWidth>1</bitWidth>
  3044. </field>
  3045. </fields>
  3046. </register>
  3047. <register>
  3048. <name>AFRL</name>
  3049. <displayName>AFRL</displayName>
  3050. <description>GPIO alternate function low
  3051. register</description>
  3052. <addressOffset>0x20</addressOffset>
  3053. <size>0x20</size>
  3054. <access>read-write</access>
  3055. <resetValue>0x00000000</resetValue>
  3056. <fields>
  3057. <field>
  3058. <name>AFSEL7</name>
  3059. <description>Alternate function selection for port x
  3060. pin y (y = 0..7)</description>
  3061. <bitOffset>28</bitOffset>
  3062. <bitWidth>4</bitWidth>
  3063. </field>
  3064. <field>
  3065. <name>AFSEL6</name>
  3066. <description>Alternate function selection for port x
  3067. pin y (y = 0..7)</description>
  3068. <bitOffset>24</bitOffset>
  3069. <bitWidth>4</bitWidth>
  3070. </field>
  3071. <field>
  3072. <name>AFSEL5</name>
  3073. <description>Alternate function selection for port x
  3074. pin y (y = 0..7)</description>
  3075. <bitOffset>20</bitOffset>
  3076. <bitWidth>4</bitWidth>
  3077. </field>
  3078. <field>
  3079. <name>AFSEL4</name>
  3080. <description>Alternate function selection for port x
  3081. pin y (y = 0..7)</description>
  3082. <bitOffset>16</bitOffset>
  3083. <bitWidth>4</bitWidth>
  3084. </field>
  3085. <field>
  3086. <name>AFSEL3</name>
  3087. <description>Alternate function selection for port x
  3088. pin y (y = 0..7)</description>
  3089. <bitOffset>12</bitOffset>
  3090. <bitWidth>4</bitWidth>
  3091. </field>
  3092. <field>
  3093. <name>AFSEL2</name>
  3094. <description>Alternate function selection for port x
  3095. pin y (y = 0..7)</description>
  3096. <bitOffset>8</bitOffset>
  3097. <bitWidth>4</bitWidth>
  3098. </field>
  3099. <field>
  3100. <name>AFSEL1</name>
  3101. <description>Alternate function selection for port x
  3102. pin y (y = 0..7)</description>
  3103. <bitOffset>4</bitOffset>
  3104. <bitWidth>4</bitWidth>
  3105. </field>
  3106. <field>
  3107. <name>AFSEL0</name>
  3108. <description>Alternate function selection for port x
  3109. pin y (y = 0..7)</description>
  3110. <bitOffset>0</bitOffset>
  3111. <bitWidth>4</bitWidth>
  3112. </field>
  3113. </fields>
  3114. </register>
  3115. <register>
  3116. <name>AFRH</name>
  3117. <displayName>AFRH</displayName>
  3118. <description>GPIO alternate function high
  3119. register</description>
  3120. <addressOffset>0x24</addressOffset>
  3121. <size>0x20</size>
  3122. <access>read-write</access>
  3123. <resetValue>0x00000000</resetValue>
  3124. <fields>
  3125. <field>
  3126. <name>AFSEL15</name>
  3127. <description>Alternate function selection for port x
  3128. pin y (y = 8..15)</description>
  3129. <bitOffset>28</bitOffset>
  3130. <bitWidth>4</bitWidth>
  3131. </field>
  3132. <field>
  3133. <name>AFSEL14</name>
  3134. <description>Alternate function selection for port x
  3135. pin y (y = 8..15)</description>
  3136. <bitOffset>24</bitOffset>
  3137. <bitWidth>4</bitWidth>
  3138. </field>
  3139. <field>
  3140. <name>AFSEL13</name>
  3141. <description>Alternate function selection for port x
  3142. pin y (y = 8..15)</description>
  3143. <bitOffset>20</bitOffset>
  3144. <bitWidth>4</bitWidth>
  3145. </field>
  3146. <field>
  3147. <name>AFSEL12</name>
  3148. <description>Alternate function selection for port x
  3149. pin y (y = 8..15)</description>
  3150. <bitOffset>16</bitOffset>
  3151. <bitWidth>4</bitWidth>
  3152. </field>
  3153. <field>
  3154. <name>AFSEL11</name>
  3155. <description>Alternate function selection for port x
  3156. pin y (y = 8..15)</description>
  3157. <bitOffset>12</bitOffset>
  3158. <bitWidth>4</bitWidth>
  3159. </field>
  3160. <field>
  3161. <name>AFSEL10</name>
  3162. <description>Alternate function selection for port x
  3163. pin y (y = 8..15)</description>
  3164. <bitOffset>8</bitOffset>
  3165. <bitWidth>4</bitWidth>
  3166. </field>
  3167. <field>
  3168. <name>AFSEL9</name>
  3169. <description>Alternate function selection for port x
  3170. pin y (y = 8..15)</description>
  3171. <bitOffset>4</bitOffset>
  3172. <bitWidth>4</bitWidth>
  3173. </field>
  3174. <field>
  3175. <name>AFSEL8</name>
  3176. <description>Alternate function selection for port x
  3177. pin y (y = 8..15)</description>
  3178. <bitOffset>0</bitOffset>
  3179. <bitWidth>4</bitWidth>
  3180. </field>
  3181. </fields>
  3182. </register>
  3183. <register>
  3184. <name>BRR</name>
  3185. <displayName>BRR</displayName>
  3186. <description>GPIO port bit reset register</description>
  3187. <addressOffset>0x28</addressOffset>
  3188. <size>0x20</size>
  3189. <access>write-only</access>
  3190. <resetValue>0x00000000</resetValue>
  3191. <fields>
  3192. <field>
  3193. <name>BR15</name>
  3194. <description>Port x Reset bit y (y= 0 ..
  3195. 15)</description>
  3196. <bitOffset>15</bitOffset>
  3197. <bitWidth>1</bitWidth>
  3198. </field>
  3199. <field>
  3200. <name>BR14</name>
  3201. <description>Port x Reset bit y (y= 0 ..
  3202. 15)</description>
  3203. <bitOffset>14</bitOffset>
  3204. <bitWidth>1</bitWidth>
  3205. </field>
  3206. <field>
  3207. <name>BR13</name>
  3208. <description>Port x Reset bit y (y= 0 ..
  3209. 15)</description>
  3210. <bitOffset>13</bitOffset>
  3211. <bitWidth>1</bitWidth>
  3212. </field>
  3213. <field>
  3214. <name>BR12</name>
  3215. <description>Port x Reset bit y (y= 0 ..
  3216. 15)</description>
  3217. <bitOffset>12</bitOffset>
  3218. <bitWidth>1</bitWidth>
  3219. </field>
  3220. <field>
  3221. <name>BR11</name>
  3222. <description>Port x Reset bit y (y= 0 ..
  3223. 15)</description>
  3224. <bitOffset>11</bitOffset>
  3225. <bitWidth>1</bitWidth>
  3226. </field>
  3227. <field>
  3228. <name>BR10</name>
  3229. <description>Port x Reset bit y (y= 0 ..
  3230. 15)</description>
  3231. <bitOffset>10</bitOffset>
  3232. <bitWidth>1</bitWidth>
  3233. </field>
  3234. <field>
  3235. <name>BR9</name>
  3236. <description>Port x Reset bit y (y= 0 ..
  3237. 15)</description>
  3238. <bitOffset>9</bitOffset>
  3239. <bitWidth>1</bitWidth>
  3240. </field>
  3241. <field>
  3242. <name>BR8</name>
  3243. <description>Port x Reset bit y (y= 0 ..
  3244. 15)</description>
  3245. <bitOffset>8</bitOffset>
  3246. <bitWidth>1</bitWidth>
  3247. </field>
  3248. <field>
  3249. <name>BR7</name>
  3250. <description>Port x Reset bit y (y= 0 ..
  3251. 15)</description>
  3252. <bitOffset>7</bitOffset>
  3253. <bitWidth>1</bitWidth>
  3254. </field>
  3255. <field>
  3256. <name>BR6</name>
  3257. <description>Port x Reset bit y (y= 0 ..
  3258. 15)</description>
  3259. <bitOffset>6</bitOffset>
  3260. <bitWidth>1</bitWidth>
  3261. </field>
  3262. <field>
  3263. <name>BR5</name>
  3264. <description>Port x Reset bit y (y= 0 ..
  3265. 15)</description>
  3266. <bitOffset>5</bitOffset>
  3267. <bitWidth>1</bitWidth>
  3268. </field>
  3269. <field>
  3270. <name>BR4</name>
  3271. <description>Port x Reset bit y (y= 0 ..
  3272. 15)</description>
  3273. <bitOffset>4</bitOffset>
  3274. <bitWidth>1</bitWidth>
  3275. </field>
  3276. <field>
  3277. <name>BR3</name>
  3278. <description>Port x Reset bit y (y= 0 ..
  3279. 15)</description>
  3280. <bitOffset>3</bitOffset>
  3281. <bitWidth>1</bitWidth>
  3282. </field>
  3283. <field>
  3284. <name>BR2</name>
  3285. <description>Port x Reset bit y (y= 0 ..
  3286. 15)</description>
  3287. <bitOffset>2</bitOffset>
  3288. <bitWidth>1</bitWidth>
  3289. </field>
  3290. <field>
  3291. <name>BR1</name>
  3292. <description>Port x Reset bit y (y= 0 ..
  3293. 15)</description>
  3294. <bitOffset>1</bitOffset>
  3295. <bitWidth>1</bitWidth>
  3296. </field>
  3297. <field>
  3298. <name>BR0</name>
  3299. <description>Port x Reset bit y (y= 0 ..
  3300. 15)</description>
  3301. <bitOffset>0</bitOffset>
  3302. <bitWidth>1</bitWidth>
  3303. </field>
  3304. </fields>
  3305. </register>
  3306. </registers>
  3307. </peripheral>
  3308. <peripheral>
  3309. <name>GPIOB</name>
  3310. <description>General-purpose I/Os</description>
  3311. <groupName>GPIO</groupName>
  3312. <baseAddress>0x50000400</baseAddress>
  3313. <addressBlock>
  3314. <offset>0x0</offset>
  3315. <size>0x400</size>
  3316. <usage>registers</usage>
  3317. </addressBlock>
  3318. <registers>
  3319. <register>
  3320. <name>MODER</name>
  3321. <displayName>MODER</displayName>
  3322. <description>GPIO port mode register</description>
  3323. <addressOffset>0x0</addressOffset>
  3324. <size>0x20</size>
  3325. <access>read-write</access>
  3326. <resetValue>0xFFFFFFFF</resetValue>
  3327. <fields>
  3328. <field>
  3329. <name>MODE15</name>
  3330. <description>Port x configuration bits (y =
  3331. 0..15)</description>
  3332. <bitOffset>30</bitOffset>
  3333. <bitWidth>2</bitWidth>
  3334. </field>
  3335. <field>
  3336. <name>MODE14</name>
  3337. <description>Port x configuration bits (y =
  3338. 0..15)</description>
  3339. <bitOffset>28</bitOffset>
  3340. <bitWidth>2</bitWidth>
  3341. </field>
  3342. <field>
  3343. <name>MODE13</name>
  3344. <description>Port x configuration bits (y =
  3345. 0..15)</description>
  3346. <bitOffset>26</bitOffset>
  3347. <bitWidth>2</bitWidth>
  3348. </field>
  3349. <field>
  3350. <name>MODE12</name>
  3351. <description>Port x configuration bits (y =
  3352. 0..15)</description>
  3353. <bitOffset>24</bitOffset>
  3354. <bitWidth>2</bitWidth>
  3355. </field>
  3356. <field>
  3357. <name>MODE11</name>
  3358. <description>Port x configuration bits (y =
  3359. 0..15)</description>
  3360. <bitOffset>22</bitOffset>
  3361. <bitWidth>2</bitWidth>
  3362. </field>
  3363. <field>
  3364. <name>MODE10</name>
  3365. <description>Port x configuration bits (y =
  3366. 0..15)</description>
  3367. <bitOffset>20</bitOffset>
  3368. <bitWidth>2</bitWidth>
  3369. </field>
  3370. <field>
  3371. <name>MODE9</name>
  3372. <description>Port x configuration bits (y =
  3373. 0..15)</description>
  3374. <bitOffset>18</bitOffset>
  3375. <bitWidth>2</bitWidth>
  3376. </field>
  3377. <field>
  3378. <name>MODE8</name>
  3379. <description>Port x configuration bits (y =
  3380. 0..15)</description>
  3381. <bitOffset>16</bitOffset>
  3382. <bitWidth>2</bitWidth>
  3383. </field>
  3384. <field>
  3385. <name>MODE7</name>
  3386. <description>Port x configuration bits (y =
  3387. 0..15)</description>
  3388. <bitOffset>14</bitOffset>
  3389. <bitWidth>2</bitWidth>
  3390. </field>
  3391. <field>
  3392. <name>MODE6</name>
  3393. <description>Port x configuration bits (y =
  3394. 0..15)</description>
  3395. <bitOffset>12</bitOffset>
  3396. <bitWidth>2</bitWidth>
  3397. </field>
  3398. <field>
  3399. <name>MODE5</name>
  3400. <description>Port x configuration bits (y =
  3401. 0..15)</description>
  3402. <bitOffset>10</bitOffset>
  3403. <bitWidth>2</bitWidth>
  3404. </field>
  3405. <field>
  3406. <name>MODE4</name>
  3407. <description>Port x configuration bits (y =
  3408. 0..15)</description>
  3409. <bitOffset>8</bitOffset>
  3410. <bitWidth>2</bitWidth>
  3411. </field>
  3412. <field>
  3413. <name>MODE3</name>
  3414. <description>Port x configuration bits (y =
  3415. 0..15)</description>
  3416. <bitOffset>6</bitOffset>
  3417. <bitWidth>2</bitWidth>
  3418. </field>
  3419. <field>
  3420. <name>MODE2</name>
  3421. <description>Port x configuration bits (y =
  3422. 0..15)</description>
  3423. <bitOffset>4</bitOffset>
  3424. <bitWidth>2</bitWidth>
  3425. </field>
  3426. <field>
  3427. <name>MODE1</name>
  3428. <description>Port x configuration bits (y =
  3429. 0..15)</description>
  3430. <bitOffset>2</bitOffset>
  3431. <bitWidth>2</bitWidth>
  3432. </field>
  3433. <field>
  3434. <name>MODE0</name>
  3435. <description>Port x configuration bits (y =
  3436. 0..15)</description>
  3437. <bitOffset>0</bitOffset>
  3438. <bitWidth>2</bitWidth>
  3439. </field>
  3440. </fields>
  3441. </register>
  3442. <register>
  3443. <name>OTYPER</name>
  3444. <displayName>OTYPER</displayName>
  3445. <description>GPIO port output type register</description>
  3446. <addressOffset>0x4</addressOffset>
  3447. <size>0x20</size>
  3448. <access>read-write</access>
  3449. <resetValue>0x00000000</resetValue>
  3450. <fields>
  3451. <field>
  3452. <name>OT15</name>
  3453. <description>Port x configuration bits (y =
  3454. 0..15)</description>
  3455. <bitOffset>15</bitOffset>
  3456. <bitWidth>1</bitWidth>
  3457. </field>
  3458. <field>
  3459. <name>OT14</name>
  3460. <description>Port x configuration bits (y =
  3461. 0..15)</description>
  3462. <bitOffset>14</bitOffset>
  3463. <bitWidth>1</bitWidth>
  3464. </field>
  3465. <field>
  3466. <name>OT13</name>
  3467. <description>Port x configuration bits (y =
  3468. 0..15)</description>
  3469. <bitOffset>13</bitOffset>
  3470. <bitWidth>1</bitWidth>
  3471. </field>
  3472. <field>
  3473. <name>OT12</name>
  3474. <description>Port x configuration bits (y =
  3475. 0..15)</description>
  3476. <bitOffset>12</bitOffset>
  3477. <bitWidth>1</bitWidth>
  3478. </field>
  3479. <field>
  3480. <name>OT11</name>
  3481. <description>Port x configuration bits (y =
  3482. 0..15)</description>
  3483. <bitOffset>11</bitOffset>
  3484. <bitWidth>1</bitWidth>
  3485. </field>
  3486. <field>
  3487. <name>OT10</name>
  3488. <description>Port x configuration bits (y =
  3489. 0..15)</description>
  3490. <bitOffset>10</bitOffset>
  3491. <bitWidth>1</bitWidth>
  3492. </field>
  3493. <field>
  3494. <name>OT9</name>
  3495. <description>Port x configuration bits (y =
  3496. 0..15)</description>
  3497. <bitOffset>9</bitOffset>
  3498. <bitWidth>1</bitWidth>
  3499. </field>
  3500. <field>
  3501. <name>OT8</name>
  3502. <description>Port x configuration bits (y =
  3503. 0..15)</description>
  3504. <bitOffset>8</bitOffset>
  3505. <bitWidth>1</bitWidth>
  3506. </field>
  3507. <field>
  3508. <name>OT7</name>
  3509. <description>Port x configuration bits (y =
  3510. 0..15)</description>
  3511. <bitOffset>7</bitOffset>
  3512. <bitWidth>1</bitWidth>
  3513. </field>
  3514. <field>
  3515. <name>OT6</name>
  3516. <description>Port x configuration bits (y =
  3517. 0..15)</description>
  3518. <bitOffset>6</bitOffset>
  3519. <bitWidth>1</bitWidth>
  3520. </field>
  3521. <field>
  3522. <name>OT5</name>
  3523. <description>Port x configuration bits (y =
  3524. 0..15)</description>
  3525. <bitOffset>5</bitOffset>
  3526. <bitWidth>1</bitWidth>
  3527. </field>
  3528. <field>
  3529. <name>OT4</name>
  3530. <description>Port x configuration bits (y =
  3531. 0..15)</description>
  3532. <bitOffset>4</bitOffset>
  3533. <bitWidth>1</bitWidth>
  3534. </field>
  3535. <field>
  3536. <name>OT3</name>
  3537. <description>Port x configuration bits (y =
  3538. 0..15)</description>
  3539. <bitOffset>3</bitOffset>
  3540. <bitWidth>1</bitWidth>
  3541. </field>
  3542. <field>
  3543. <name>OT2</name>
  3544. <description>Port x configuration bits (y =
  3545. 0..15)</description>
  3546. <bitOffset>2</bitOffset>
  3547. <bitWidth>1</bitWidth>
  3548. </field>
  3549. <field>
  3550. <name>OT1</name>
  3551. <description>Port x configuration bits (y =
  3552. 0..15)</description>
  3553. <bitOffset>1</bitOffset>
  3554. <bitWidth>1</bitWidth>
  3555. </field>
  3556. <field>
  3557. <name>OT0</name>
  3558. <description>Port x configuration bits (y =
  3559. 0..15)</description>
  3560. <bitOffset>0</bitOffset>
  3561. <bitWidth>1</bitWidth>
  3562. </field>
  3563. </fields>
  3564. </register>
  3565. <register>
  3566. <name>OSPEEDR</name>
  3567. <displayName>OSPEEDR</displayName>
  3568. <description>GPIO port output speed
  3569. register</description>
  3570. <addressOffset>0x8</addressOffset>
  3571. <size>0x20</size>
  3572. <access>read-write</access>
  3573. <resetValue>0x00000000</resetValue>
  3574. <fields>
  3575. <field>
  3576. <name>OSPEED15</name>
  3577. <description>Port x configuration bits (y =
  3578. 0..15)</description>
  3579. <bitOffset>30</bitOffset>
  3580. <bitWidth>2</bitWidth>
  3581. </field>
  3582. <field>
  3583. <name>OSPEED14</name>
  3584. <description>Port x configuration bits (y =
  3585. 0..15)</description>
  3586. <bitOffset>28</bitOffset>
  3587. <bitWidth>2</bitWidth>
  3588. </field>
  3589. <field>
  3590. <name>OSPEED13</name>
  3591. <description>Port x configuration bits (y =
  3592. 0..15)</description>
  3593. <bitOffset>26</bitOffset>
  3594. <bitWidth>2</bitWidth>
  3595. </field>
  3596. <field>
  3597. <name>OSPEED12</name>
  3598. <description>Port x configuration bits (y =
  3599. 0..15)</description>
  3600. <bitOffset>24</bitOffset>
  3601. <bitWidth>2</bitWidth>
  3602. </field>
  3603. <field>
  3604. <name>OSPEED11</name>
  3605. <description>Port x configuration bits (y =
  3606. 0..15)</description>
  3607. <bitOffset>22</bitOffset>
  3608. <bitWidth>2</bitWidth>
  3609. </field>
  3610. <field>
  3611. <name>OSPEED10</name>
  3612. <description>Port x configuration bits (y =
  3613. 0..15)</description>
  3614. <bitOffset>20</bitOffset>
  3615. <bitWidth>2</bitWidth>
  3616. </field>
  3617. <field>
  3618. <name>OSPEED9</name>
  3619. <description>Port x configuration bits (y =
  3620. 0..15)</description>
  3621. <bitOffset>18</bitOffset>
  3622. <bitWidth>2</bitWidth>
  3623. </field>
  3624. <field>
  3625. <name>OSPEED8</name>
  3626. <description>Port x configuration bits (y =
  3627. 0..15)</description>
  3628. <bitOffset>16</bitOffset>
  3629. <bitWidth>2</bitWidth>
  3630. </field>
  3631. <field>
  3632. <name>OSPEED7</name>
  3633. <description>Port x configuration bits (y =
  3634. 0..15)</description>
  3635. <bitOffset>14</bitOffset>
  3636. <bitWidth>2</bitWidth>
  3637. </field>
  3638. <field>
  3639. <name>OSPEED6</name>
  3640. <description>Port x configuration bits (y =
  3641. 0..15)</description>
  3642. <bitOffset>12</bitOffset>
  3643. <bitWidth>2</bitWidth>
  3644. </field>
  3645. <field>
  3646. <name>OSPEED5</name>
  3647. <description>Port x configuration bits (y =
  3648. 0..15)</description>
  3649. <bitOffset>10</bitOffset>
  3650. <bitWidth>2</bitWidth>
  3651. </field>
  3652. <field>
  3653. <name>OSPEED4</name>
  3654. <description>Port x configuration bits (y =
  3655. 0..15)</description>
  3656. <bitOffset>8</bitOffset>
  3657. <bitWidth>2</bitWidth>
  3658. </field>
  3659. <field>
  3660. <name>OSPEED3</name>
  3661. <description>Port x configuration bits (y =
  3662. 0..15)</description>
  3663. <bitOffset>6</bitOffset>
  3664. <bitWidth>2</bitWidth>
  3665. </field>
  3666. <field>
  3667. <name>OSPEED2</name>
  3668. <description>Port x configuration bits (y =
  3669. 0..15)</description>
  3670. <bitOffset>4</bitOffset>
  3671. <bitWidth>2</bitWidth>
  3672. </field>
  3673. <field>
  3674. <name>OSPEED1</name>
  3675. <description>Port x configuration bits (y =
  3676. 0..15)</description>
  3677. <bitOffset>2</bitOffset>
  3678. <bitWidth>2</bitWidth>
  3679. </field>
  3680. <field>
  3681. <name>OSPEED0</name>
  3682. <description>Port x configuration bits (y =
  3683. 0..15)</description>
  3684. <bitOffset>0</bitOffset>
  3685. <bitWidth>2</bitWidth>
  3686. </field>
  3687. </fields>
  3688. </register>
  3689. <register>
  3690. <name>PUPDR</name>
  3691. <displayName>PUPDR</displayName>
  3692. <description>GPIO port pull-up/pull-down
  3693. register</description>
  3694. <addressOffset>0xC</addressOffset>
  3695. <size>0x20</size>
  3696. <access>read-write</access>
  3697. <resetValue>0x00000000</resetValue>
  3698. <fields>
  3699. <field>
  3700. <name>PUPD15</name>
  3701. <description>Port x configuration bits (y =
  3702. 0..15)</description>
  3703. <bitOffset>30</bitOffset>
  3704. <bitWidth>2</bitWidth>
  3705. </field>
  3706. <field>
  3707. <name>PUPD14</name>
  3708. <description>Port x configuration bits (y =
  3709. 0..15)</description>
  3710. <bitOffset>28</bitOffset>
  3711. <bitWidth>2</bitWidth>
  3712. </field>
  3713. <field>
  3714. <name>PUPD13</name>
  3715. <description>Port x configuration bits (y =
  3716. 0..15)</description>
  3717. <bitOffset>26</bitOffset>
  3718. <bitWidth>2</bitWidth>
  3719. </field>
  3720. <field>
  3721. <name>PUPD12</name>
  3722. <description>Port x configuration bits (y =
  3723. 0..15)</description>
  3724. <bitOffset>24</bitOffset>
  3725. <bitWidth>2</bitWidth>
  3726. </field>
  3727. <field>
  3728. <name>PUPD11</name>
  3729. <description>Port x configuration bits (y =
  3730. 0..15)</description>
  3731. <bitOffset>22</bitOffset>
  3732. <bitWidth>2</bitWidth>
  3733. </field>
  3734. <field>
  3735. <name>PUPD10</name>
  3736. <description>Port x configuration bits (y =
  3737. 0..15)</description>
  3738. <bitOffset>20</bitOffset>
  3739. <bitWidth>2</bitWidth>
  3740. </field>
  3741. <field>
  3742. <name>PUPD9</name>
  3743. <description>Port x configuration bits (y =
  3744. 0..15)</description>
  3745. <bitOffset>18</bitOffset>
  3746. <bitWidth>2</bitWidth>
  3747. </field>
  3748. <field>
  3749. <name>PUPD8</name>
  3750. <description>Port x configuration bits (y =
  3751. 0..15)</description>
  3752. <bitOffset>16</bitOffset>
  3753. <bitWidth>2</bitWidth>
  3754. </field>
  3755. <field>
  3756. <name>PUPD7</name>
  3757. <description>Port x configuration bits (y =
  3758. 0..15)</description>
  3759. <bitOffset>14</bitOffset>
  3760. <bitWidth>2</bitWidth>
  3761. </field>
  3762. <field>
  3763. <name>PUPD6</name>
  3764. <description>Port x configuration bits (y =
  3765. 0..15)</description>
  3766. <bitOffset>12</bitOffset>
  3767. <bitWidth>2</bitWidth>
  3768. </field>
  3769. <field>
  3770. <name>PUPD5</name>
  3771. <description>Port x configuration bits (y =
  3772. 0..15)</description>
  3773. <bitOffset>10</bitOffset>
  3774. <bitWidth>2</bitWidth>
  3775. </field>
  3776. <field>
  3777. <name>PUPD4</name>
  3778. <description>Port x configuration bits (y =
  3779. 0..15)</description>
  3780. <bitOffset>8</bitOffset>
  3781. <bitWidth>2</bitWidth>
  3782. </field>
  3783. <field>
  3784. <name>PUPD3</name>
  3785. <description>Port x configuration bits (y =
  3786. 0..15)</description>
  3787. <bitOffset>6</bitOffset>
  3788. <bitWidth>2</bitWidth>
  3789. </field>
  3790. <field>
  3791. <name>PUPD2</name>
  3792. <description>Port x configuration bits (y =
  3793. 0..15)</description>
  3794. <bitOffset>4</bitOffset>
  3795. <bitWidth>2</bitWidth>
  3796. </field>
  3797. <field>
  3798. <name>PUPD1</name>
  3799. <description>Port x configuration bits (y =
  3800. 0..15)</description>
  3801. <bitOffset>2</bitOffset>
  3802. <bitWidth>2</bitWidth>
  3803. </field>
  3804. <field>
  3805. <name>PUPD0</name>
  3806. <description>Port x configuration bits (y =
  3807. 0..15)</description>
  3808. <bitOffset>0</bitOffset>
  3809. <bitWidth>2</bitWidth>
  3810. </field>
  3811. </fields>
  3812. </register>
  3813. <register>
  3814. <name>IDR</name>
  3815. <displayName>IDR</displayName>
  3816. <description>GPIO port input data register</description>
  3817. <addressOffset>0x10</addressOffset>
  3818. <size>0x20</size>
  3819. <access>read-only</access>
  3820. <resetValue>0x00000000</resetValue>
  3821. <fields>
  3822. <field>
  3823. <name>ID15</name>
  3824. <description>Port input data bit (y =
  3825. 0..15)</description>
  3826. <bitOffset>15</bitOffset>
  3827. <bitWidth>1</bitWidth>
  3828. </field>
  3829. <field>
  3830. <name>ID14</name>
  3831. <description>Port input data bit (y =
  3832. 0..15)</description>
  3833. <bitOffset>14</bitOffset>
  3834. <bitWidth>1</bitWidth>
  3835. </field>
  3836. <field>
  3837. <name>ID13</name>
  3838. <description>Port input data bit (y =
  3839. 0..15)</description>
  3840. <bitOffset>13</bitOffset>
  3841. <bitWidth>1</bitWidth>
  3842. </field>
  3843. <field>
  3844. <name>ID12</name>
  3845. <description>Port input data bit (y =
  3846. 0..15)</description>
  3847. <bitOffset>12</bitOffset>
  3848. <bitWidth>1</bitWidth>
  3849. </field>
  3850. <field>
  3851. <name>ID11</name>
  3852. <description>Port input data bit (y =
  3853. 0..15)</description>
  3854. <bitOffset>11</bitOffset>
  3855. <bitWidth>1</bitWidth>
  3856. </field>
  3857. <field>
  3858. <name>ID10</name>
  3859. <description>Port input data bit (y =
  3860. 0..15)</description>
  3861. <bitOffset>10</bitOffset>
  3862. <bitWidth>1</bitWidth>
  3863. </field>
  3864. <field>
  3865. <name>ID9</name>
  3866. <description>Port input data bit (y =
  3867. 0..15)</description>
  3868. <bitOffset>9</bitOffset>
  3869. <bitWidth>1</bitWidth>
  3870. </field>
  3871. <field>
  3872. <name>ID8</name>
  3873. <description>Port input data bit (y =
  3874. 0..15)</description>
  3875. <bitOffset>8</bitOffset>
  3876. <bitWidth>1</bitWidth>
  3877. </field>
  3878. <field>
  3879. <name>ID7</name>
  3880. <description>Port input data bit (y =
  3881. 0..15)</description>
  3882. <bitOffset>7</bitOffset>
  3883. <bitWidth>1</bitWidth>
  3884. </field>
  3885. <field>
  3886. <name>ID6</name>
  3887. <description>Port input data bit (y =
  3888. 0..15)</description>
  3889. <bitOffset>6</bitOffset>
  3890. <bitWidth>1</bitWidth>
  3891. </field>
  3892. <field>
  3893. <name>ID5</name>
  3894. <description>Port input data bit (y =
  3895. 0..15)</description>
  3896. <bitOffset>5</bitOffset>
  3897. <bitWidth>1</bitWidth>
  3898. </field>
  3899. <field>
  3900. <name>ID4</name>
  3901. <description>Port input data bit (y =
  3902. 0..15)</description>
  3903. <bitOffset>4</bitOffset>
  3904. <bitWidth>1</bitWidth>
  3905. </field>
  3906. <field>
  3907. <name>ID3</name>
  3908. <description>Port input data bit (y =
  3909. 0..15)</description>
  3910. <bitOffset>3</bitOffset>
  3911. <bitWidth>1</bitWidth>
  3912. </field>
  3913. <field>
  3914. <name>ID2</name>
  3915. <description>Port input data bit (y =
  3916. 0..15)</description>
  3917. <bitOffset>2</bitOffset>
  3918. <bitWidth>1</bitWidth>
  3919. </field>
  3920. <field>
  3921. <name>ID1</name>
  3922. <description>Port input data bit (y =
  3923. 0..15)</description>
  3924. <bitOffset>1</bitOffset>
  3925. <bitWidth>1</bitWidth>
  3926. </field>
  3927. <field>
  3928. <name>ID0</name>
  3929. <description>Port input data bit (y =
  3930. 0..15)</description>
  3931. <bitOffset>0</bitOffset>
  3932. <bitWidth>1</bitWidth>
  3933. </field>
  3934. </fields>
  3935. </register>
  3936. <register>
  3937. <name>ODR</name>
  3938. <displayName>ODR</displayName>
  3939. <description>GPIO port output data register</description>
  3940. <addressOffset>0x14</addressOffset>
  3941. <size>0x20</size>
  3942. <access>read-write</access>
  3943. <resetValue>0x00000000</resetValue>
  3944. <fields>
  3945. <field>
  3946. <name>OD15</name>
  3947. <description>Port output data bit (y =
  3948. 0..15)</description>
  3949. <bitOffset>15</bitOffset>
  3950. <bitWidth>1</bitWidth>
  3951. </field>
  3952. <field>
  3953. <name>OD14</name>
  3954. <description>Port output data bit (y =
  3955. 0..15)</description>
  3956. <bitOffset>14</bitOffset>
  3957. <bitWidth>1</bitWidth>
  3958. </field>
  3959. <field>
  3960. <name>OD13</name>
  3961. <description>Port output data bit (y =
  3962. 0..15)</description>
  3963. <bitOffset>13</bitOffset>
  3964. <bitWidth>1</bitWidth>
  3965. </field>
  3966. <field>
  3967. <name>OD12</name>
  3968. <description>Port output data bit (y =
  3969. 0..15)</description>
  3970. <bitOffset>12</bitOffset>
  3971. <bitWidth>1</bitWidth>
  3972. </field>
  3973. <field>
  3974. <name>OD11</name>
  3975. <description>Port output data bit (y =
  3976. 0..15)</description>
  3977. <bitOffset>11</bitOffset>
  3978. <bitWidth>1</bitWidth>
  3979. </field>
  3980. <field>
  3981. <name>OD10</name>
  3982. <description>Port output data bit (y =
  3983. 0..15)</description>
  3984. <bitOffset>10</bitOffset>
  3985. <bitWidth>1</bitWidth>
  3986. </field>
  3987. <field>
  3988. <name>OD9</name>
  3989. <description>Port output data bit (y =
  3990. 0..15)</description>
  3991. <bitOffset>9</bitOffset>
  3992. <bitWidth>1</bitWidth>
  3993. </field>
  3994. <field>
  3995. <name>OD8</name>
  3996. <description>Port output data bit (y =
  3997. 0..15)</description>
  3998. <bitOffset>8</bitOffset>
  3999. <bitWidth>1</bitWidth>
  4000. </field>
  4001. <field>
  4002. <name>OD7</name>
  4003. <description>Port output data bit (y =
  4004. 0..15)</description>
  4005. <bitOffset>7</bitOffset>
  4006. <bitWidth>1</bitWidth>
  4007. </field>
  4008. <field>
  4009. <name>OD6</name>
  4010. <description>Port output data bit (y =
  4011. 0..15)</description>
  4012. <bitOffset>6</bitOffset>
  4013. <bitWidth>1</bitWidth>
  4014. </field>
  4015. <field>
  4016. <name>OD5</name>
  4017. <description>Port output data bit (y =
  4018. 0..15)</description>
  4019. <bitOffset>5</bitOffset>
  4020. <bitWidth>1</bitWidth>
  4021. </field>
  4022. <field>
  4023. <name>OD4</name>
  4024. <description>Port output data bit (y =
  4025. 0..15)</description>
  4026. <bitOffset>4</bitOffset>
  4027. <bitWidth>1</bitWidth>
  4028. </field>
  4029. <field>
  4030. <name>OD3</name>
  4031. <description>Port output data bit (y =
  4032. 0..15)</description>
  4033. <bitOffset>3</bitOffset>
  4034. <bitWidth>1</bitWidth>
  4035. </field>
  4036. <field>
  4037. <name>OD2</name>
  4038. <description>Port output data bit (y =
  4039. 0..15)</description>
  4040. <bitOffset>2</bitOffset>
  4041. <bitWidth>1</bitWidth>
  4042. </field>
  4043. <field>
  4044. <name>OD1</name>
  4045. <description>Port output data bit (y =
  4046. 0..15)</description>
  4047. <bitOffset>1</bitOffset>
  4048. <bitWidth>1</bitWidth>
  4049. </field>
  4050. <field>
  4051. <name>OD0</name>
  4052. <description>Port output data bit (y =
  4053. 0..15)</description>
  4054. <bitOffset>0</bitOffset>
  4055. <bitWidth>1</bitWidth>
  4056. </field>
  4057. </fields>
  4058. </register>
  4059. <register>
  4060. <name>BSRR</name>
  4061. <displayName>BSRR</displayName>
  4062. <description>GPIO port bit set/reset
  4063. register</description>
  4064. <addressOffset>0x18</addressOffset>
  4065. <size>0x20</size>
  4066. <access>write-only</access>
  4067. <resetValue>0x00000000</resetValue>
  4068. <fields>
  4069. <field>
  4070. <name>BR15</name>
  4071. <description>Port x reset bit y (y =
  4072. 0..15)</description>
  4073. <bitOffset>31</bitOffset>
  4074. <bitWidth>1</bitWidth>
  4075. </field>
  4076. <field>
  4077. <name>BR14</name>
  4078. <description>Port x reset bit y (y =
  4079. 0..15)</description>
  4080. <bitOffset>30</bitOffset>
  4081. <bitWidth>1</bitWidth>
  4082. </field>
  4083. <field>
  4084. <name>BR13</name>
  4085. <description>Port x reset bit y (y =
  4086. 0..15)</description>
  4087. <bitOffset>29</bitOffset>
  4088. <bitWidth>1</bitWidth>
  4089. </field>
  4090. <field>
  4091. <name>BR12</name>
  4092. <description>Port x reset bit y (y =
  4093. 0..15)</description>
  4094. <bitOffset>28</bitOffset>
  4095. <bitWidth>1</bitWidth>
  4096. </field>
  4097. <field>
  4098. <name>BR11</name>
  4099. <description>Port x reset bit y (y =
  4100. 0..15)</description>
  4101. <bitOffset>27</bitOffset>
  4102. <bitWidth>1</bitWidth>
  4103. </field>
  4104. <field>
  4105. <name>BR10</name>
  4106. <description>Port x reset bit y (y =
  4107. 0..15)</description>
  4108. <bitOffset>26</bitOffset>
  4109. <bitWidth>1</bitWidth>
  4110. </field>
  4111. <field>
  4112. <name>BR9</name>
  4113. <description>Port x reset bit y (y =
  4114. 0..15)</description>
  4115. <bitOffset>25</bitOffset>
  4116. <bitWidth>1</bitWidth>
  4117. </field>
  4118. <field>
  4119. <name>BR8</name>
  4120. <description>Port x reset bit y (y =
  4121. 0..15)</description>
  4122. <bitOffset>24</bitOffset>
  4123. <bitWidth>1</bitWidth>
  4124. </field>
  4125. <field>
  4126. <name>BR7</name>
  4127. <description>Port x reset bit y (y =
  4128. 0..15)</description>
  4129. <bitOffset>23</bitOffset>
  4130. <bitWidth>1</bitWidth>
  4131. </field>
  4132. <field>
  4133. <name>BR6</name>
  4134. <description>Port x reset bit y (y =
  4135. 0..15)</description>
  4136. <bitOffset>22</bitOffset>
  4137. <bitWidth>1</bitWidth>
  4138. </field>
  4139. <field>
  4140. <name>BR5</name>
  4141. <description>Port x reset bit y (y =
  4142. 0..15)</description>
  4143. <bitOffset>21</bitOffset>
  4144. <bitWidth>1</bitWidth>
  4145. </field>
  4146. <field>
  4147. <name>BR4</name>
  4148. <description>Port x reset bit y (y =
  4149. 0..15)</description>
  4150. <bitOffset>20</bitOffset>
  4151. <bitWidth>1</bitWidth>
  4152. </field>
  4153. <field>
  4154. <name>BR3</name>
  4155. <description>Port x reset bit y (y =
  4156. 0..15)</description>
  4157. <bitOffset>19</bitOffset>
  4158. <bitWidth>1</bitWidth>
  4159. </field>
  4160. <field>
  4161. <name>BR2</name>
  4162. <description>Port x reset bit y (y =
  4163. 0..15)</description>
  4164. <bitOffset>18</bitOffset>
  4165. <bitWidth>1</bitWidth>
  4166. </field>
  4167. <field>
  4168. <name>BR1</name>
  4169. <description>Port x reset bit y (y =
  4170. 0..15)</description>
  4171. <bitOffset>17</bitOffset>
  4172. <bitWidth>1</bitWidth>
  4173. </field>
  4174. <field>
  4175. <name>BR0</name>
  4176. <description>Port x reset bit y (y =
  4177. 0..15)</description>
  4178. <bitOffset>16</bitOffset>
  4179. <bitWidth>1</bitWidth>
  4180. </field>
  4181. <field>
  4182. <name>BS15</name>
  4183. <description>Port x set bit y (y=
  4184. 0..15)</description>
  4185. <bitOffset>15</bitOffset>
  4186. <bitWidth>1</bitWidth>
  4187. </field>
  4188. <field>
  4189. <name>BS14</name>
  4190. <description>Port x set bit y (y=
  4191. 0..15)</description>
  4192. <bitOffset>14</bitOffset>
  4193. <bitWidth>1</bitWidth>
  4194. </field>
  4195. <field>
  4196. <name>BS13</name>
  4197. <description>Port x set bit y (y=
  4198. 0..15)</description>
  4199. <bitOffset>13</bitOffset>
  4200. <bitWidth>1</bitWidth>
  4201. </field>
  4202. <field>
  4203. <name>BS12</name>
  4204. <description>Port x set bit y (y=
  4205. 0..15)</description>
  4206. <bitOffset>12</bitOffset>
  4207. <bitWidth>1</bitWidth>
  4208. </field>
  4209. <field>
  4210. <name>BS11</name>
  4211. <description>Port x set bit y (y=
  4212. 0..15)</description>
  4213. <bitOffset>11</bitOffset>
  4214. <bitWidth>1</bitWidth>
  4215. </field>
  4216. <field>
  4217. <name>BS10</name>
  4218. <description>Port x set bit y (y=
  4219. 0..15)</description>
  4220. <bitOffset>10</bitOffset>
  4221. <bitWidth>1</bitWidth>
  4222. </field>
  4223. <field>
  4224. <name>BS9</name>
  4225. <description>Port x set bit y (y=
  4226. 0..15)</description>
  4227. <bitOffset>9</bitOffset>
  4228. <bitWidth>1</bitWidth>
  4229. </field>
  4230. <field>
  4231. <name>BS8</name>
  4232. <description>Port x set bit y (y=
  4233. 0..15)</description>
  4234. <bitOffset>8</bitOffset>
  4235. <bitWidth>1</bitWidth>
  4236. </field>
  4237. <field>
  4238. <name>BS7</name>
  4239. <description>Port x set bit y (y=
  4240. 0..15)</description>
  4241. <bitOffset>7</bitOffset>
  4242. <bitWidth>1</bitWidth>
  4243. </field>
  4244. <field>
  4245. <name>BS6</name>
  4246. <description>Port x set bit y (y=
  4247. 0..15)</description>
  4248. <bitOffset>6</bitOffset>
  4249. <bitWidth>1</bitWidth>
  4250. </field>
  4251. <field>
  4252. <name>BS5</name>
  4253. <description>Port x set bit y (y=
  4254. 0..15)</description>
  4255. <bitOffset>5</bitOffset>
  4256. <bitWidth>1</bitWidth>
  4257. </field>
  4258. <field>
  4259. <name>BS4</name>
  4260. <description>Port x set bit y (y=
  4261. 0..15)</description>
  4262. <bitOffset>4</bitOffset>
  4263. <bitWidth>1</bitWidth>
  4264. </field>
  4265. <field>
  4266. <name>BS3</name>
  4267. <description>Port x set bit y (y=
  4268. 0..15)</description>
  4269. <bitOffset>3</bitOffset>
  4270. <bitWidth>1</bitWidth>
  4271. </field>
  4272. <field>
  4273. <name>BS2</name>
  4274. <description>Port x set bit y (y=
  4275. 0..15)</description>
  4276. <bitOffset>2</bitOffset>
  4277. <bitWidth>1</bitWidth>
  4278. </field>
  4279. <field>
  4280. <name>BS1</name>
  4281. <description>Port x set bit y (y=
  4282. 0..15)</description>
  4283. <bitOffset>1</bitOffset>
  4284. <bitWidth>1</bitWidth>
  4285. </field>
  4286. <field>
  4287. <name>BS0</name>
  4288. <description>Port x set bit y (y=
  4289. 0..15)</description>
  4290. <bitOffset>0</bitOffset>
  4291. <bitWidth>1</bitWidth>
  4292. </field>
  4293. </fields>
  4294. </register>
  4295. <register>
  4296. <name>LCKR</name>
  4297. <displayName>LCKR</displayName>
  4298. <description>GPIO port configuration lock
  4299. register</description>
  4300. <addressOffset>0x1C</addressOffset>
  4301. <size>0x20</size>
  4302. <access>read-write</access>
  4303. <resetValue>0x00000000</resetValue>
  4304. <fields>
  4305. <field>
  4306. <name>LCKK</name>
  4307. <description>Port x lock bit y (y=
  4308. 0..15)</description>
  4309. <bitOffset>16</bitOffset>
  4310. <bitWidth>1</bitWidth>
  4311. </field>
  4312. <field>
  4313. <name>LCK15</name>
  4314. <description>Port x lock bit y (y=
  4315. 0..15)</description>
  4316. <bitOffset>15</bitOffset>
  4317. <bitWidth>1</bitWidth>
  4318. </field>
  4319. <field>
  4320. <name>LCK14</name>
  4321. <description>Port x lock bit y (y=
  4322. 0..15)</description>
  4323. <bitOffset>14</bitOffset>
  4324. <bitWidth>1</bitWidth>
  4325. </field>
  4326. <field>
  4327. <name>LCK13</name>
  4328. <description>Port x lock bit y (y=
  4329. 0..15)</description>
  4330. <bitOffset>13</bitOffset>
  4331. <bitWidth>1</bitWidth>
  4332. </field>
  4333. <field>
  4334. <name>LCK12</name>
  4335. <description>Port x lock bit y (y=
  4336. 0..15)</description>
  4337. <bitOffset>12</bitOffset>
  4338. <bitWidth>1</bitWidth>
  4339. </field>
  4340. <field>
  4341. <name>LCK11</name>
  4342. <description>Port x lock bit y (y=
  4343. 0..15)</description>
  4344. <bitOffset>11</bitOffset>
  4345. <bitWidth>1</bitWidth>
  4346. </field>
  4347. <field>
  4348. <name>LCK10</name>
  4349. <description>Port x lock bit y (y=
  4350. 0..15)</description>
  4351. <bitOffset>10</bitOffset>
  4352. <bitWidth>1</bitWidth>
  4353. </field>
  4354. <field>
  4355. <name>LCK9</name>
  4356. <description>Port x lock bit y (y=
  4357. 0..15)</description>
  4358. <bitOffset>9</bitOffset>
  4359. <bitWidth>1</bitWidth>
  4360. </field>
  4361. <field>
  4362. <name>LCK8</name>
  4363. <description>Port x lock bit y (y=
  4364. 0..15)</description>
  4365. <bitOffset>8</bitOffset>
  4366. <bitWidth>1</bitWidth>
  4367. </field>
  4368. <field>
  4369. <name>LCK7</name>
  4370. <description>Port x lock bit y (y=
  4371. 0..15)</description>
  4372. <bitOffset>7</bitOffset>
  4373. <bitWidth>1</bitWidth>
  4374. </field>
  4375. <field>
  4376. <name>LCK6</name>
  4377. <description>Port x lock bit y (y=
  4378. 0..15)</description>
  4379. <bitOffset>6</bitOffset>
  4380. <bitWidth>1</bitWidth>
  4381. </field>
  4382. <field>
  4383. <name>LCK5</name>
  4384. <description>Port x lock bit y (y=
  4385. 0..15)</description>
  4386. <bitOffset>5</bitOffset>
  4387. <bitWidth>1</bitWidth>
  4388. </field>
  4389. <field>
  4390. <name>LCK4</name>
  4391. <description>Port x lock bit y (y=
  4392. 0..15)</description>
  4393. <bitOffset>4</bitOffset>
  4394. <bitWidth>1</bitWidth>
  4395. </field>
  4396. <field>
  4397. <name>LCK3</name>
  4398. <description>Port x lock bit y (y=
  4399. 0..15)</description>
  4400. <bitOffset>3</bitOffset>
  4401. <bitWidth>1</bitWidth>
  4402. </field>
  4403. <field>
  4404. <name>LCK2</name>
  4405. <description>Port x lock bit y (y=
  4406. 0..15)</description>
  4407. <bitOffset>2</bitOffset>
  4408. <bitWidth>1</bitWidth>
  4409. </field>
  4410. <field>
  4411. <name>LCK1</name>
  4412. <description>Port x lock bit y (y=
  4413. 0..15)</description>
  4414. <bitOffset>1</bitOffset>
  4415. <bitWidth>1</bitWidth>
  4416. </field>
  4417. <field>
  4418. <name>LCK0</name>
  4419. <description>Port x lock bit y (y=
  4420. 0..15)</description>
  4421. <bitOffset>0</bitOffset>
  4422. <bitWidth>1</bitWidth>
  4423. </field>
  4424. </fields>
  4425. </register>
  4426. <register>
  4427. <name>AFRL</name>
  4428. <displayName>AFRL</displayName>
  4429. <description>GPIO alternate function low
  4430. register</description>
  4431. <addressOffset>0x20</addressOffset>
  4432. <size>0x20</size>
  4433. <access>read-write</access>
  4434. <resetValue>0x00000000</resetValue>
  4435. <fields>
  4436. <field>
  4437. <name>AFSEL7</name>
  4438. <description>Alternate function selection for port x
  4439. pin y (y = 0..7)</description>
  4440. <bitOffset>28</bitOffset>
  4441. <bitWidth>4</bitWidth>
  4442. </field>
  4443. <field>
  4444. <name>AFSEL6</name>
  4445. <description>Alternate function selection for port x
  4446. pin y (y = 0..7)</description>
  4447. <bitOffset>24</bitOffset>
  4448. <bitWidth>4</bitWidth>
  4449. </field>
  4450. <field>
  4451. <name>AFSEL5</name>
  4452. <description>Alternate function selection for port x
  4453. pin y (y = 0..7)</description>
  4454. <bitOffset>20</bitOffset>
  4455. <bitWidth>4</bitWidth>
  4456. </field>
  4457. <field>
  4458. <name>AFSEL4</name>
  4459. <description>Alternate function selection for port x
  4460. pin y (y = 0..7)</description>
  4461. <bitOffset>16</bitOffset>
  4462. <bitWidth>4</bitWidth>
  4463. </field>
  4464. <field>
  4465. <name>AFSEL3</name>
  4466. <description>Alternate function selection for port x
  4467. pin y (y = 0..7)</description>
  4468. <bitOffset>12</bitOffset>
  4469. <bitWidth>4</bitWidth>
  4470. </field>
  4471. <field>
  4472. <name>AFSEL2</name>
  4473. <description>Alternate function selection for port x
  4474. pin y (y = 0..7)</description>
  4475. <bitOffset>8</bitOffset>
  4476. <bitWidth>4</bitWidth>
  4477. </field>
  4478. <field>
  4479. <name>AFSEL1</name>
  4480. <description>Alternate function selection for port x
  4481. pin y (y = 0..7)</description>
  4482. <bitOffset>4</bitOffset>
  4483. <bitWidth>4</bitWidth>
  4484. </field>
  4485. <field>
  4486. <name>AFSEL0</name>
  4487. <description>Alternate function selection for port x
  4488. pin y (y = 0..7)</description>
  4489. <bitOffset>0</bitOffset>
  4490. <bitWidth>4</bitWidth>
  4491. </field>
  4492. </fields>
  4493. </register>
  4494. <register>
  4495. <name>AFRH</name>
  4496. <displayName>AFRH</displayName>
  4497. <description>GPIO alternate function high
  4498. register</description>
  4499. <addressOffset>0x24</addressOffset>
  4500. <size>0x20</size>
  4501. <access>read-write</access>
  4502. <resetValue>0x00000000</resetValue>
  4503. <fields>
  4504. <field>
  4505. <name>AFSEL15</name>
  4506. <description>Alternate function selection for port x
  4507. pin y (y = 8..15)</description>
  4508. <bitOffset>28</bitOffset>
  4509. <bitWidth>4</bitWidth>
  4510. </field>
  4511. <field>
  4512. <name>AFSEL14</name>
  4513. <description>Alternate function selection for port x
  4514. pin y (y = 8..15)</description>
  4515. <bitOffset>24</bitOffset>
  4516. <bitWidth>4</bitWidth>
  4517. </field>
  4518. <field>
  4519. <name>AFSEL13</name>
  4520. <description>Alternate function selection for port x
  4521. pin y (y = 8..15)</description>
  4522. <bitOffset>20</bitOffset>
  4523. <bitWidth>4</bitWidth>
  4524. </field>
  4525. <field>
  4526. <name>AFSEL12</name>
  4527. <description>Alternate function selection for port x
  4528. pin y (y = 8..15)</description>
  4529. <bitOffset>16</bitOffset>
  4530. <bitWidth>4</bitWidth>
  4531. </field>
  4532. <field>
  4533. <name>AFSEL11</name>
  4534. <description>Alternate function selection for port x
  4535. pin y (y = 8..15)</description>
  4536. <bitOffset>12</bitOffset>
  4537. <bitWidth>4</bitWidth>
  4538. </field>
  4539. <field>
  4540. <name>AFSEL10</name>
  4541. <description>Alternate function selection for port x
  4542. pin y (y = 8..15)</description>
  4543. <bitOffset>8</bitOffset>
  4544. <bitWidth>4</bitWidth>
  4545. </field>
  4546. <field>
  4547. <name>AFSEL9</name>
  4548. <description>Alternate function selection for port x
  4549. pin y (y = 8..15)</description>
  4550. <bitOffset>4</bitOffset>
  4551. <bitWidth>4</bitWidth>
  4552. </field>
  4553. <field>
  4554. <name>AFSEL8</name>
  4555. <description>Alternate function selection for port x
  4556. pin y (y = 8..15)</description>
  4557. <bitOffset>0</bitOffset>
  4558. <bitWidth>4</bitWidth>
  4559. </field>
  4560. </fields>
  4561. </register>
  4562. <register>
  4563. <name>BRR</name>
  4564. <displayName>BRR</displayName>
  4565. <description>GPIO port bit reset register</description>
  4566. <addressOffset>0x28</addressOffset>
  4567. <size>0x20</size>
  4568. <access>write-only</access>
  4569. <resetValue>0x00000000</resetValue>
  4570. <fields>
  4571. <field>
  4572. <name>BR15</name>
  4573. <description>Port x Reset bit y (y= 0 ..
  4574. 15)</description>
  4575. <bitOffset>15</bitOffset>
  4576. <bitWidth>1</bitWidth>
  4577. </field>
  4578. <field>
  4579. <name>BR14</name>
  4580. <description>Port x Reset bit y (y= 0 ..
  4581. 15)</description>
  4582. <bitOffset>14</bitOffset>
  4583. <bitWidth>1</bitWidth>
  4584. </field>
  4585. <field>
  4586. <name>BR13</name>
  4587. <description>Port x Reset bit y (y= 0 ..
  4588. 15)</description>
  4589. <bitOffset>13</bitOffset>
  4590. <bitWidth>1</bitWidth>
  4591. </field>
  4592. <field>
  4593. <name>BR12</name>
  4594. <description>Port x Reset bit y (y= 0 ..
  4595. 15)</description>
  4596. <bitOffset>12</bitOffset>
  4597. <bitWidth>1</bitWidth>
  4598. </field>
  4599. <field>
  4600. <name>BR11</name>
  4601. <description>Port x Reset bit y (y= 0 ..
  4602. 15)</description>
  4603. <bitOffset>11</bitOffset>
  4604. <bitWidth>1</bitWidth>
  4605. </field>
  4606. <field>
  4607. <name>BR10</name>
  4608. <description>Port x Reset bit y (y= 0 ..
  4609. 15)</description>
  4610. <bitOffset>10</bitOffset>
  4611. <bitWidth>1</bitWidth>
  4612. </field>
  4613. <field>
  4614. <name>BR9</name>
  4615. <description>Port x Reset bit y (y= 0 ..
  4616. 15)</description>
  4617. <bitOffset>9</bitOffset>
  4618. <bitWidth>1</bitWidth>
  4619. </field>
  4620. <field>
  4621. <name>BR8</name>
  4622. <description>Port x Reset bit y (y= 0 ..
  4623. 15)</description>
  4624. <bitOffset>8</bitOffset>
  4625. <bitWidth>1</bitWidth>
  4626. </field>
  4627. <field>
  4628. <name>BR7</name>
  4629. <description>Port x Reset bit y (y= 0 ..
  4630. 15)</description>
  4631. <bitOffset>7</bitOffset>
  4632. <bitWidth>1</bitWidth>
  4633. </field>
  4634. <field>
  4635. <name>BR6</name>
  4636. <description>Port x Reset bit y (y= 0 ..
  4637. 15)</description>
  4638. <bitOffset>6</bitOffset>
  4639. <bitWidth>1</bitWidth>
  4640. </field>
  4641. <field>
  4642. <name>BR5</name>
  4643. <description>Port x Reset bit y (y= 0 ..
  4644. 15)</description>
  4645. <bitOffset>5</bitOffset>
  4646. <bitWidth>1</bitWidth>
  4647. </field>
  4648. <field>
  4649. <name>BR4</name>
  4650. <description>Port x Reset bit y (y= 0 ..
  4651. 15)</description>
  4652. <bitOffset>4</bitOffset>
  4653. <bitWidth>1</bitWidth>
  4654. </field>
  4655. <field>
  4656. <name>BR3</name>
  4657. <description>Port x Reset bit y (y= 0 ..
  4658. 15)</description>
  4659. <bitOffset>3</bitOffset>
  4660. <bitWidth>1</bitWidth>
  4661. </field>
  4662. <field>
  4663. <name>BR2</name>
  4664. <description>Port x Reset bit y (y= 0 ..
  4665. 15)</description>
  4666. <bitOffset>2</bitOffset>
  4667. <bitWidth>1</bitWidth>
  4668. </field>
  4669. <field>
  4670. <name>BR1</name>
  4671. <description>Port x Reset bit y (y= 0 ..
  4672. 15)</description>
  4673. <bitOffset>1</bitOffset>
  4674. <bitWidth>1</bitWidth>
  4675. </field>
  4676. <field>
  4677. <name>BR0</name>
  4678. <description>Port x Reset bit y (y= 0 ..
  4679. 15)</description>
  4680. <bitOffset>0</bitOffset>
  4681. <bitWidth>1</bitWidth>
  4682. </field>
  4683. </fields>
  4684. </register>
  4685. </registers>
  4686. </peripheral>
  4687. <peripheral derivedFrom="GPIOB">
  4688. <name>GPIOC</name>
  4689. <baseAddress>0x50000800</baseAddress>
  4690. </peripheral>
  4691. <peripheral derivedFrom="GPIOB">
  4692. <name>GPIOD</name>
  4693. <baseAddress>0x50000C00</baseAddress>
  4694. </peripheral>
  4695. <peripheral derivedFrom="GPIOB">
  4696. <name>GPIOH</name>
  4697. <baseAddress>0x50001C00</baseAddress>
  4698. </peripheral>
  4699. <peripheral derivedFrom="GPIOB">
  4700. <name>GPIOE</name>
  4701. <baseAddress>0x50001000</baseAddress>
  4702. </peripheral>
  4703. <peripheral>
  4704. <name>LPTIM</name>
  4705. <description>Low power timer</description>
  4706. <groupName>LPTIM</groupName>
  4707. <baseAddress>0x40007C00</baseAddress>
  4708. <addressBlock>
  4709. <offset>0x0</offset>
  4710. <size>0x400</size>
  4711. <usage>registers</usage>
  4712. </addressBlock>
  4713. <interrupt>
  4714. <name>LPTIM1</name>
  4715. <description>LPTIMER1 interrupt through
  4716. EXTI29</description>
  4717. <value>13</value>
  4718. </interrupt>
  4719. <registers>
  4720. <register>
  4721. <name>ISR</name>
  4722. <displayName>ISR</displayName>
  4723. <description>Interrupt and Status Register</description>
  4724. <addressOffset>0x0</addressOffset>
  4725. <size>0x20</size>
  4726. <access>read-only</access>
  4727. <resetValue>0x00000000</resetValue>
  4728. <fields>
  4729. <field>
  4730. <name>DOWN</name>
  4731. <description>Counter direction change up to
  4732. down</description>
  4733. <bitOffset>6</bitOffset>
  4734. <bitWidth>1</bitWidth>
  4735. </field>
  4736. <field>
  4737. <name>UP</name>
  4738. <description>Counter direction change down to
  4739. up</description>
  4740. <bitOffset>5</bitOffset>
  4741. <bitWidth>1</bitWidth>
  4742. </field>
  4743. <field>
  4744. <name>ARROK</name>
  4745. <description>Autoreload register update
  4746. OK</description>
  4747. <bitOffset>4</bitOffset>
  4748. <bitWidth>1</bitWidth>
  4749. </field>
  4750. <field>
  4751. <name>CMPOK</name>
  4752. <description>Compare register update OK</description>
  4753. <bitOffset>3</bitOffset>
  4754. <bitWidth>1</bitWidth>
  4755. </field>
  4756. <field>
  4757. <name>EXTTRIG</name>
  4758. <description>External trigger edge
  4759. event</description>
  4760. <bitOffset>2</bitOffset>
  4761. <bitWidth>1</bitWidth>
  4762. </field>
  4763. <field>
  4764. <name>ARRM</name>
  4765. <description>Autoreload match</description>
  4766. <bitOffset>1</bitOffset>
  4767. <bitWidth>1</bitWidth>
  4768. </field>
  4769. <field>
  4770. <name>CMPM</name>
  4771. <description>Compare match</description>
  4772. <bitOffset>0</bitOffset>
  4773. <bitWidth>1</bitWidth>
  4774. </field>
  4775. </fields>
  4776. </register>
  4777. <register>
  4778. <name>ICR</name>
  4779. <displayName>ICR</displayName>
  4780. <description>Interrupt Clear Register</description>
  4781. <addressOffset>0x4</addressOffset>
  4782. <size>0x20</size>
  4783. <access>write-only</access>
  4784. <resetValue>0x00000000</resetValue>
  4785. <fields>
  4786. <field>
  4787. <name>DOWNCF</name>
  4788. <description>Direction change to down Clear
  4789. Flag</description>
  4790. <bitOffset>6</bitOffset>
  4791. <bitWidth>1</bitWidth>
  4792. </field>
  4793. <field>
  4794. <name>UPCF</name>
  4795. <description>Direction change to UP Clear
  4796. Flag</description>
  4797. <bitOffset>5</bitOffset>
  4798. <bitWidth>1</bitWidth>
  4799. </field>
  4800. <field>
  4801. <name>ARROKCF</name>
  4802. <description>Autoreload register update OK Clear
  4803. Flag</description>
  4804. <bitOffset>4</bitOffset>
  4805. <bitWidth>1</bitWidth>
  4806. </field>
  4807. <field>
  4808. <name>CMPOKCF</name>
  4809. <description>Compare register update OK Clear
  4810. Flag</description>
  4811. <bitOffset>3</bitOffset>
  4812. <bitWidth>1</bitWidth>
  4813. </field>
  4814. <field>
  4815. <name>EXTTRIGCF</name>
  4816. <description>External trigger valid edge Clear
  4817. Flag</description>
  4818. <bitOffset>2</bitOffset>
  4819. <bitWidth>1</bitWidth>
  4820. </field>
  4821. <field>
  4822. <name>ARRMCF</name>
  4823. <description>Autoreload match Clear
  4824. Flag</description>
  4825. <bitOffset>1</bitOffset>
  4826. <bitWidth>1</bitWidth>
  4827. </field>
  4828. <field>
  4829. <name>CMPMCF</name>
  4830. <description>compare match Clear Flag</description>
  4831. <bitOffset>0</bitOffset>
  4832. <bitWidth>1</bitWidth>
  4833. </field>
  4834. </fields>
  4835. </register>
  4836. <register>
  4837. <name>IER</name>
  4838. <displayName>IER</displayName>
  4839. <description>Interrupt Enable Register</description>
  4840. <addressOffset>0x8</addressOffset>
  4841. <size>0x20</size>
  4842. <access>read-write</access>
  4843. <resetValue>0x00000000</resetValue>
  4844. <fields>
  4845. <field>
  4846. <name>DOWNIE</name>
  4847. <description>Direction change to down Interrupt
  4848. Enable</description>
  4849. <bitOffset>6</bitOffset>
  4850. <bitWidth>1</bitWidth>
  4851. </field>
  4852. <field>
  4853. <name>UPIE</name>
  4854. <description>Direction change to UP Interrupt
  4855. Enable</description>
  4856. <bitOffset>5</bitOffset>
  4857. <bitWidth>1</bitWidth>
  4858. </field>
  4859. <field>
  4860. <name>ARROKIE</name>
  4861. <description>Autoreload register update OK Interrupt
  4862. Enable</description>
  4863. <bitOffset>4</bitOffset>
  4864. <bitWidth>1</bitWidth>
  4865. </field>
  4866. <field>
  4867. <name>CMPOKIE</name>
  4868. <description>Compare register update OK Interrupt
  4869. Enable</description>
  4870. <bitOffset>3</bitOffset>
  4871. <bitWidth>1</bitWidth>
  4872. </field>
  4873. <field>
  4874. <name>EXTTRIGIE</name>
  4875. <description>External trigger valid edge Interrupt
  4876. Enable</description>
  4877. <bitOffset>2</bitOffset>
  4878. <bitWidth>1</bitWidth>
  4879. </field>
  4880. <field>
  4881. <name>ARRMIE</name>
  4882. <description>Autoreload match Interrupt
  4883. Enable</description>
  4884. <bitOffset>1</bitOffset>
  4885. <bitWidth>1</bitWidth>
  4886. </field>
  4887. <field>
  4888. <name>CMPMIE</name>
  4889. <description>Compare match Interrupt
  4890. Enable</description>
  4891. <bitOffset>0</bitOffset>
  4892. <bitWidth>1</bitWidth>
  4893. </field>
  4894. </fields>
  4895. </register>
  4896. <register>
  4897. <name>CFGR</name>
  4898. <displayName>CFGR</displayName>
  4899. <description>Configuration Register</description>
  4900. <addressOffset>0xC</addressOffset>
  4901. <size>0x20</size>
  4902. <access>read-write</access>
  4903. <resetValue>0x00000000</resetValue>
  4904. <fields>
  4905. <field>
  4906. <name>ENC</name>
  4907. <description>Encoder mode enable</description>
  4908. <bitOffset>24</bitOffset>
  4909. <bitWidth>1</bitWidth>
  4910. </field>
  4911. <field>
  4912. <name>COUNTMODE</name>
  4913. <description>counter mode enabled</description>
  4914. <bitOffset>23</bitOffset>
  4915. <bitWidth>1</bitWidth>
  4916. </field>
  4917. <field>
  4918. <name>PRELOAD</name>
  4919. <description>Registers update mode</description>
  4920. <bitOffset>22</bitOffset>
  4921. <bitWidth>1</bitWidth>
  4922. </field>
  4923. <field>
  4924. <name>WAVPOL</name>
  4925. <description>Waveform shape polarity</description>
  4926. <bitOffset>21</bitOffset>
  4927. <bitWidth>1</bitWidth>
  4928. </field>
  4929. <field>
  4930. <name>WAVE</name>
  4931. <description>Waveform shape</description>
  4932. <bitOffset>20</bitOffset>
  4933. <bitWidth>1</bitWidth>
  4934. </field>
  4935. <field>
  4936. <name>TIMOUT</name>
  4937. <description>Timeout enable</description>
  4938. <bitOffset>19</bitOffset>
  4939. <bitWidth>1</bitWidth>
  4940. </field>
  4941. <field>
  4942. <name>TRIGEN</name>
  4943. <description>Trigger enable and
  4944. polarity</description>
  4945. <bitOffset>17</bitOffset>
  4946. <bitWidth>2</bitWidth>
  4947. </field>
  4948. <field>
  4949. <name>TRIGSEL</name>
  4950. <description>Trigger selector</description>
  4951. <bitOffset>13</bitOffset>
  4952. <bitWidth>3</bitWidth>
  4953. </field>
  4954. <field>
  4955. <name>PRESC</name>
  4956. <description>Clock prescaler</description>
  4957. <bitOffset>9</bitOffset>
  4958. <bitWidth>3</bitWidth>
  4959. </field>
  4960. <field>
  4961. <name>TRGFLT</name>
  4962. <description>Configurable digital filter for
  4963. trigger</description>
  4964. <bitOffset>6</bitOffset>
  4965. <bitWidth>2</bitWidth>
  4966. </field>
  4967. <field>
  4968. <name>CKFLT</name>
  4969. <description>Configurable digital filter for external
  4970. clock</description>
  4971. <bitOffset>3</bitOffset>
  4972. <bitWidth>2</bitWidth>
  4973. </field>
  4974. <field>
  4975. <name>CKPOL</name>
  4976. <description>Clock Polarity</description>
  4977. <bitOffset>1</bitOffset>
  4978. <bitWidth>2</bitWidth>
  4979. </field>
  4980. <field>
  4981. <name>CKSEL</name>
  4982. <description>Clock selector</description>
  4983. <bitOffset>0</bitOffset>
  4984. <bitWidth>1</bitWidth>
  4985. </field>
  4986. </fields>
  4987. </register>
  4988. <register>
  4989. <name>CR</name>
  4990. <displayName>CR</displayName>
  4991. <description>Control Register</description>
  4992. <addressOffset>0x10</addressOffset>
  4993. <size>0x20</size>
  4994. <access>read-write</access>
  4995. <resetValue>0x00000000</resetValue>
  4996. <fields>
  4997. <field>
  4998. <name>CNTSTRT</name>
  4999. <description>Timer start in continuous
  5000. mode</description>
  5001. <bitOffset>2</bitOffset>
  5002. <bitWidth>1</bitWidth>
  5003. </field>
  5004. <field>
  5005. <name>SNGSTRT</name>
  5006. <description>LPTIM start in single mode</description>
  5007. <bitOffset>1</bitOffset>
  5008. <bitWidth>1</bitWidth>
  5009. </field>
  5010. <field>
  5011. <name>ENABLE</name>
  5012. <description>LPTIM Enable</description>
  5013. <bitOffset>0</bitOffset>
  5014. <bitWidth>1</bitWidth>
  5015. </field>
  5016. </fields>
  5017. </register>
  5018. <register>
  5019. <name>CMP</name>
  5020. <displayName>CMP</displayName>
  5021. <description>Compare Register</description>
  5022. <addressOffset>0x14</addressOffset>
  5023. <size>0x20</size>
  5024. <access>read-write</access>
  5025. <resetValue>0x00000000</resetValue>
  5026. <fields>
  5027. <field>
  5028. <name>CMP</name>
  5029. <description>Compare value.</description>
  5030. <bitOffset>0</bitOffset>
  5031. <bitWidth>16</bitWidth>
  5032. </field>
  5033. </fields>
  5034. </register>
  5035. <register>
  5036. <name>ARR</name>
  5037. <displayName>ARR</displayName>
  5038. <description>Autoreload Register</description>
  5039. <addressOffset>0x18</addressOffset>
  5040. <size>0x20</size>
  5041. <access>read-write</access>
  5042. <resetValue>0x00000001</resetValue>
  5043. <fields>
  5044. <field>
  5045. <name>ARR</name>
  5046. <description>Auto reload value.</description>
  5047. <bitOffset>0</bitOffset>
  5048. <bitWidth>16</bitWidth>
  5049. </field>
  5050. </fields>
  5051. </register>
  5052. <register>
  5053. <name>CNT</name>
  5054. <displayName>CNT</displayName>
  5055. <description>Counter Register</description>
  5056. <addressOffset>0x1C</addressOffset>
  5057. <size>0x20</size>
  5058. <access>read-only</access>
  5059. <resetValue>0x00000000</resetValue>
  5060. <fields>
  5061. <field>
  5062. <name>CNT</name>
  5063. <description>Counter value.</description>
  5064. <bitOffset>0</bitOffset>
  5065. <bitWidth>16</bitWidth>
  5066. </field>
  5067. </fields>
  5068. </register>
  5069. </registers>
  5070. </peripheral>
  5071. <peripheral>
  5072. <name>RTC</name>
  5073. <description>Real-time clock</description>
  5074. <groupName>RTC</groupName>
  5075. <baseAddress>0x40002800</baseAddress>
  5076. <addressBlock>
  5077. <offset>0x0</offset>
  5078. <size>0x400</size>
  5079. <usage>registers</usage>
  5080. </addressBlock>
  5081. <interrupt>
  5082. <name>RTC</name>
  5083. <description>RTC global interrupt</description>
  5084. <value>2</value>
  5085. </interrupt>
  5086. <registers>
  5087. <register>
  5088. <name>TR</name>
  5089. <displayName>TR</displayName>
  5090. <description>RTC time register</description>
  5091. <addressOffset>0x0</addressOffset>
  5092. <size>0x20</size>
  5093. <access>read-write</access>
  5094. <resetValue>0x00000000</resetValue>
  5095. <fields>
  5096. <field>
  5097. <name>PM</name>
  5098. <description>AM/PM notation</description>
  5099. <bitOffset>22</bitOffset>
  5100. <bitWidth>1</bitWidth>
  5101. </field>
  5102. <field>
  5103. <name>HT</name>
  5104. <description>Hour tens in BCD format</description>
  5105. <bitOffset>20</bitOffset>
  5106. <bitWidth>2</bitWidth>
  5107. </field>
  5108. <field>
  5109. <name>HU</name>
  5110. <description>Hour units in BCD format</description>
  5111. <bitOffset>16</bitOffset>
  5112. <bitWidth>4</bitWidth>
  5113. </field>
  5114. <field>
  5115. <name>MNT</name>
  5116. <description>Minute tens in BCD format</description>
  5117. <bitOffset>12</bitOffset>
  5118. <bitWidth>3</bitWidth>
  5119. </field>
  5120. <field>
  5121. <name>MNU</name>
  5122. <description>Minute units in BCD format</description>
  5123. <bitOffset>8</bitOffset>
  5124. <bitWidth>4</bitWidth>
  5125. </field>
  5126. <field>
  5127. <name>ST</name>
  5128. <description>Second tens in BCD format</description>
  5129. <bitOffset>4</bitOffset>
  5130. <bitWidth>3</bitWidth>
  5131. </field>
  5132. <field>
  5133. <name>SU</name>
  5134. <description>Second units in BCD format</description>
  5135. <bitOffset>0</bitOffset>
  5136. <bitWidth>4</bitWidth>
  5137. </field>
  5138. </fields>
  5139. </register>
  5140. <register>
  5141. <name>DR</name>
  5142. <displayName>DR</displayName>
  5143. <description>RTC date register</description>
  5144. <addressOffset>0x4</addressOffset>
  5145. <size>0x20</size>
  5146. <access>read-write</access>
  5147. <resetValue>0x00000000</resetValue>
  5148. <fields>
  5149. <field>
  5150. <name>YT</name>
  5151. <description>Year tens in BCD format</description>
  5152. <bitOffset>20</bitOffset>
  5153. <bitWidth>4</bitWidth>
  5154. </field>
  5155. <field>
  5156. <name>YU</name>
  5157. <description>Year units in BCD format</description>
  5158. <bitOffset>16</bitOffset>
  5159. <bitWidth>4</bitWidth>
  5160. </field>
  5161. <field>
  5162. <name>WDU</name>
  5163. <description>Week day units</description>
  5164. <bitOffset>13</bitOffset>
  5165. <bitWidth>3</bitWidth>
  5166. </field>
  5167. <field>
  5168. <name>MT</name>
  5169. <description>Month tens in BCD format</description>
  5170. <bitOffset>12</bitOffset>
  5171. <bitWidth>1</bitWidth>
  5172. </field>
  5173. <field>
  5174. <name>MU</name>
  5175. <description>Month units in BCD format</description>
  5176. <bitOffset>8</bitOffset>
  5177. <bitWidth>4</bitWidth>
  5178. </field>
  5179. <field>
  5180. <name>DT</name>
  5181. <description>Date tens in BCD format</description>
  5182. <bitOffset>4</bitOffset>
  5183. <bitWidth>2</bitWidth>
  5184. </field>
  5185. <field>
  5186. <name>DU</name>
  5187. <description>Date units in BCD format</description>
  5188. <bitOffset>0</bitOffset>
  5189. <bitWidth>4</bitWidth>
  5190. </field>
  5191. </fields>
  5192. </register>
  5193. <register>
  5194. <name>CR</name>
  5195. <displayName>CR</displayName>
  5196. <description>RTC control register</description>
  5197. <addressOffset>0x8</addressOffset>
  5198. <size>0x20</size>
  5199. <resetValue>0x00000000</resetValue>
  5200. <fields>
  5201. <field>
  5202. <name>COE</name>
  5203. <description>Calibration output enable</description>
  5204. <bitOffset>23</bitOffset>
  5205. <bitWidth>1</bitWidth>
  5206. <access>read-write</access>
  5207. </field>
  5208. <field>
  5209. <name>OSEL</name>
  5210. <description>Output selection</description>
  5211. <bitOffset>21</bitOffset>
  5212. <bitWidth>2</bitWidth>
  5213. <access>read-write</access>
  5214. </field>
  5215. <field>
  5216. <name>POL</name>
  5217. <description>Output polarity</description>
  5218. <bitOffset>20</bitOffset>
  5219. <bitWidth>1</bitWidth>
  5220. <access>read-write</access>
  5221. </field>
  5222. <field>
  5223. <name>COSEL</name>
  5224. <description>Calibration output
  5225. selection</description>
  5226. <bitOffset>19</bitOffset>
  5227. <bitWidth>1</bitWidth>
  5228. <access>read-write</access>
  5229. </field>
  5230. <field>
  5231. <name>BKP</name>
  5232. <description>Backup</description>
  5233. <bitOffset>18</bitOffset>
  5234. <bitWidth>1</bitWidth>
  5235. <access>read-write</access>
  5236. </field>
  5237. <field>
  5238. <name>SUB1H</name>
  5239. <description>Subtract 1 hour (winter time
  5240. change)</description>
  5241. <bitOffset>17</bitOffset>
  5242. <bitWidth>1</bitWidth>
  5243. <access>write-only</access>
  5244. </field>
  5245. <field>
  5246. <name>ADD1H</name>
  5247. <description>Add 1 hour (summer time
  5248. change)</description>
  5249. <bitOffset>16</bitOffset>
  5250. <bitWidth>1</bitWidth>
  5251. <access>write-only</access>
  5252. </field>
  5253. <field>
  5254. <name>TSIE</name>
  5255. <description>Time-stamp interrupt
  5256. enable</description>
  5257. <bitOffset>15</bitOffset>
  5258. <bitWidth>1</bitWidth>
  5259. <access>read-write</access>
  5260. </field>
  5261. <field>
  5262. <name>WUTIE</name>
  5263. <description>Wakeup timer interrupt
  5264. enable</description>
  5265. <bitOffset>14</bitOffset>
  5266. <bitWidth>1</bitWidth>
  5267. <access>read-write</access>
  5268. </field>
  5269. <field>
  5270. <name>ALRBIE</name>
  5271. <description>Alarm B interrupt enable</description>
  5272. <bitOffset>13</bitOffset>
  5273. <bitWidth>1</bitWidth>
  5274. <access>read-write</access>
  5275. </field>
  5276. <field>
  5277. <name>ALRAIE</name>
  5278. <description>Alarm A interrupt enable</description>
  5279. <bitOffset>12</bitOffset>
  5280. <bitWidth>1</bitWidth>
  5281. <access>read-write</access>
  5282. </field>
  5283. <field>
  5284. <name>TSE</name>
  5285. <description>timestamp enable</description>
  5286. <bitOffset>11</bitOffset>
  5287. <bitWidth>1</bitWidth>
  5288. <access>read-write</access>
  5289. </field>
  5290. <field>
  5291. <name>WUTE</name>
  5292. <description>Wakeup timer enable</description>
  5293. <bitOffset>10</bitOffset>
  5294. <bitWidth>1</bitWidth>
  5295. <access>read-write</access>
  5296. </field>
  5297. <field>
  5298. <name>ALRBE</name>
  5299. <description>Alarm B enable</description>
  5300. <bitOffset>9</bitOffset>
  5301. <bitWidth>1</bitWidth>
  5302. <access>read-write</access>
  5303. </field>
  5304. <field>
  5305. <name>ALRAE</name>
  5306. <description>Alarm A enable</description>
  5307. <bitOffset>8</bitOffset>
  5308. <bitWidth>1</bitWidth>
  5309. <access>read-write</access>
  5310. </field>
  5311. <field>
  5312. <name>FMT</name>
  5313. <description>Hour format</description>
  5314. <bitOffset>6</bitOffset>
  5315. <bitWidth>1</bitWidth>
  5316. <access>read-write</access>
  5317. </field>
  5318. <field>
  5319. <name>BYPSHAD</name>
  5320. <description>Bypass the shadow
  5321. registers</description>
  5322. <bitOffset>5</bitOffset>
  5323. <bitWidth>1</bitWidth>
  5324. <access>read-write</access>
  5325. </field>
  5326. <field>
  5327. <name>REFCKON</name>
  5328. <description>RTC_REFIN reference clock detection
  5329. enable (50 or 60 Hz)</description>
  5330. <bitOffset>4</bitOffset>
  5331. <bitWidth>1</bitWidth>
  5332. <access>read-write</access>
  5333. </field>
  5334. <field>
  5335. <name>TSEDGE</name>
  5336. <description>Time-stamp event active
  5337. edge</description>
  5338. <bitOffset>3</bitOffset>
  5339. <bitWidth>1</bitWidth>
  5340. <access>read-write</access>
  5341. </field>
  5342. <field>
  5343. <name>WUCKSEL</name>
  5344. <description>Wakeup clock selection</description>
  5345. <bitOffset>0</bitOffset>
  5346. <bitWidth>3</bitWidth>
  5347. <access>read-write</access>
  5348. </field>
  5349. </fields>
  5350. </register>
  5351. <register>
  5352. <name>ISR</name>
  5353. <displayName>ISR</displayName>
  5354. <description>RTC initialization and status
  5355. register</description>
  5356. <addressOffset>0xC</addressOffset>
  5357. <size>0x20</size>
  5358. <resetValue>0x00000000</resetValue>
  5359. <fields>
  5360. <field>
  5361. <name>TAMP2F</name>
  5362. <description>RTC_TAMP2 detection flag</description>
  5363. <bitOffset>14</bitOffset>
  5364. <bitWidth>1</bitWidth>
  5365. <access>read-write</access>
  5366. </field>
  5367. <field>
  5368. <name>TAMP1F</name>
  5369. <description>RTC_TAMP1 detection flag</description>
  5370. <bitOffset>13</bitOffset>
  5371. <bitWidth>1</bitWidth>
  5372. <access>read-write</access>
  5373. </field>
  5374. <field>
  5375. <name>TSOVF</name>
  5376. <description>Time-stamp overflow flag</description>
  5377. <bitOffset>12</bitOffset>
  5378. <bitWidth>1</bitWidth>
  5379. <access>read-write</access>
  5380. </field>
  5381. <field>
  5382. <name>TSF</name>
  5383. <description>Time-stamp flag</description>
  5384. <bitOffset>11</bitOffset>
  5385. <bitWidth>1</bitWidth>
  5386. <access>read-write</access>
  5387. </field>
  5388. <field>
  5389. <name>WUTF</name>
  5390. <description>Wakeup timer flag</description>
  5391. <bitOffset>10</bitOffset>
  5392. <bitWidth>1</bitWidth>
  5393. <access>read-write</access>
  5394. </field>
  5395. <field>
  5396. <name>ALRBF</name>
  5397. <description>Alarm B flag</description>
  5398. <bitOffset>9</bitOffset>
  5399. <bitWidth>1</bitWidth>
  5400. <access>read-write</access>
  5401. </field>
  5402. <field>
  5403. <name>ALRAF</name>
  5404. <description>Alarm A flag</description>
  5405. <bitOffset>8</bitOffset>
  5406. <bitWidth>1</bitWidth>
  5407. <access>read-write</access>
  5408. </field>
  5409. <field>
  5410. <name>INIT</name>
  5411. <description>Initialization mode</description>
  5412. <bitOffset>7</bitOffset>
  5413. <bitWidth>1</bitWidth>
  5414. <access>read-write</access>
  5415. </field>
  5416. <field>
  5417. <name>INITF</name>
  5418. <description>Initialization flag</description>
  5419. <bitOffset>6</bitOffset>
  5420. <bitWidth>1</bitWidth>
  5421. <access>read-only</access>
  5422. </field>
  5423. <field>
  5424. <name>RSF</name>
  5425. <description>Registers synchronization
  5426. flag</description>
  5427. <bitOffset>5</bitOffset>
  5428. <bitWidth>1</bitWidth>
  5429. <access>read-write</access>
  5430. </field>
  5431. <field>
  5432. <name>INITS</name>
  5433. <description>Initialization status flag</description>
  5434. <bitOffset>4</bitOffset>
  5435. <bitWidth>1</bitWidth>
  5436. <access>read-only</access>
  5437. </field>
  5438. <field>
  5439. <name>SHPF</name>
  5440. <description>Shift operation pending</description>
  5441. <bitOffset>3</bitOffset>
  5442. <bitWidth>1</bitWidth>
  5443. <access>read-only</access>
  5444. </field>
  5445. <field>
  5446. <name>WUTWF</name>
  5447. <description>Wakeup timer write flag</description>
  5448. <bitOffset>2</bitOffset>
  5449. <bitWidth>1</bitWidth>
  5450. <access>read-only</access>
  5451. </field>
  5452. <field>
  5453. <name>ALRBWF</name>
  5454. <description>Alarm B write flag</description>
  5455. <bitOffset>1</bitOffset>
  5456. <bitWidth>1</bitWidth>
  5457. <access>read-only</access>
  5458. </field>
  5459. <field>
  5460. <name>ALRAWF</name>
  5461. <description>Alarm A write flag</description>
  5462. <bitOffset>0</bitOffset>
  5463. <bitWidth>1</bitWidth>
  5464. <access>read-only</access>
  5465. </field>
  5466. </fields>
  5467. </register>
  5468. <register>
  5469. <name>PRER</name>
  5470. <displayName>PRER</displayName>
  5471. <description>RTC prescaler register</description>
  5472. <addressOffset>0x10</addressOffset>
  5473. <size>0x20</size>
  5474. <access>read-write</access>
  5475. <resetValue>0x00000000</resetValue>
  5476. <fields>
  5477. <field>
  5478. <name>PREDIV_A</name>
  5479. <description>Asynchronous prescaler
  5480. factor</description>
  5481. <bitOffset>16</bitOffset>
  5482. <bitWidth>7</bitWidth>
  5483. </field>
  5484. <field>
  5485. <name>PREDIV_S</name>
  5486. <description>Synchronous prescaler
  5487. factor</description>
  5488. <bitOffset>0</bitOffset>
  5489. <bitWidth>16</bitWidth>
  5490. </field>
  5491. </fields>
  5492. </register>
  5493. <register>
  5494. <name>WUTR</name>
  5495. <displayName>WUTR</displayName>
  5496. <description>RTC wakeup timer register</description>
  5497. <addressOffset>0x14</addressOffset>
  5498. <size>0x20</size>
  5499. <access>read-write</access>
  5500. <resetValue>0x00000000</resetValue>
  5501. <fields>
  5502. <field>
  5503. <name>WUT</name>
  5504. <description>Wakeup auto-reload value
  5505. bits</description>
  5506. <bitOffset>0</bitOffset>
  5507. <bitWidth>16</bitWidth>
  5508. </field>
  5509. </fields>
  5510. </register>
  5511. <register>
  5512. <name>ALRMAR</name>
  5513. <displayName>ALRMAR</displayName>
  5514. <description>RTC alarm A register</description>
  5515. <addressOffset>0x1C</addressOffset>
  5516. <size>0x20</size>
  5517. <access>read-write</access>
  5518. <resetValue>0x00000000</resetValue>
  5519. <fields>
  5520. <field>
  5521. <name>MSK4</name>
  5522. <description>Alarm A date mask</description>
  5523. <bitOffset>31</bitOffset>
  5524. <bitWidth>1</bitWidth>
  5525. </field>
  5526. <field>
  5527. <name>WDSEL</name>
  5528. <description>Week day selection</description>
  5529. <bitOffset>30</bitOffset>
  5530. <bitWidth>1</bitWidth>
  5531. </field>
  5532. <field>
  5533. <name>DT</name>
  5534. <description>Date tens in BCD format.</description>
  5535. <bitOffset>28</bitOffset>
  5536. <bitWidth>2</bitWidth>
  5537. </field>
  5538. <field>
  5539. <name>DU</name>
  5540. <description>Date units or day in BCD
  5541. format.</description>
  5542. <bitOffset>24</bitOffset>
  5543. <bitWidth>4</bitWidth>
  5544. </field>
  5545. <field>
  5546. <name>MSK3</name>
  5547. <description>Alarm A hours mask</description>
  5548. <bitOffset>23</bitOffset>
  5549. <bitWidth>1</bitWidth>
  5550. </field>
  5551. <field>
  5552. <name>PM</name>
  5553. <description>AM/PM notation</description>
  5554. <bitOffset>22</bitOffset>
  5555. <bitWidth>1</bitWidth>
  5556. </field>
  5557. <field>
  5558. <name>HT</name>
  5559. <description>Hour tens in BCD format.</description>
  5560. <bitOffset>20</bitOffset>
  5561. <bitWidth>2</bitWidth>
  5562. </field>
  5563. <field>
  5564. <name>HU</name>
  5565. <description>Hour units in BCD format.</description>
  5566. <bitOffset>16</bitOffset>
  5567. <bitWidth>4</bitWidth>
  5568. </field>
  5569. <field>
  5570. <name>MSK2</name>
  5571. <description>Alarm A minutes mask</description>
  5572. <bitOffset>15</bitOffset>
  5573. <bitWidth>1</bitWidth>
  5574. </field>
  5575. <field>
  5576. <name>MNT</name>
  5577. <description>Minute tens in BCD format.</description>
  5578. <bitOffset>12</bitOffset>
  5579. <bitWidth>3</bitWidth>
  5580. </field>
  5581. <field>
  5582. <name>MNU</name>
  5583. <description>Minute units in BCD
  5584. format.</description>
  5585. <bitOffset>8</bitOffset>
  5586. <bitWidth>4</bitWidth>
  5587. </field>
  5588. <field>
  5589. <name>MSK1</name>
  5590. <description>Alarm A seconds mask</description>
  5591. <bitOffset>7</bitOffset>
  5592. <bitWidth>1</bitWidth>
  5593. </field>
  5594. <field>
  5595. <name>ST</name>
  5596. <description>Second tens in BCD format.</description>
  5597. <bitOffset>4</bitOffset>
  5598. <bitWidth>3</bitWidth>
  5599. </field>
  5600. <field>
  5601. <name>SU</name>
  5602. <description>Second units in BCD
  5603. format.</description>
  5604. <bitOffset>0</bitOffset>
  5605. <bitWidth>4</bitWidth>
  5606. </field>
  5607. </fields>
  5608. </register>
  5609. <register>
  5610. <name>ALRMBR</name>
  5611. <displayName>ALRMBR</displayName>
  5612. <description>RTC alarm B register</description>
  5613. <addressOffset>0x20</addressOffset>
  5614. <size>0x20</size>
  5615. <access>read-write</access>
  5616. <resetValue>0x00000000</resetValue>
  5617. <fields>
  5618. <field>
  5619. <name>MSK4</name>
  5620. <description>Alarm B date mask</description>
  5621. <bitOffset>31</bitOffset>
  5622. <bitWidth>1</bitWidth>
  5623. </field>
  5624. <field>
  5625. <name>WDSEL</name>
  5626. <description>Week day selection</description>
  5627. <bitOffset>30</bitOffset>
  5628. <bitWidth>1</bitWidth>
  5629. </field>
  5630. <field>
  5631. <name>DT</name>
  5632. <description>Date tens in BCD format</description>
  5633. <bitOffset>28</bitOffset>
  5634. <bitWidth>2</bitWidth>
  5635. </field>
  5636. <field>
  5637. <name>DU</name>
  5638. <description>Date units or day in BCD
  5639. format</description>
  5640. <bitOffset>24</bitOffset>
  5641. <bitWidth>4</bitWidth>
  5642. </field>
  5643. <field>
  5644. <name>MSK3</name>
  5645. <description>Alarm B hours mask</description>
  5646. <bitOffset>23</bitOffset>
  5647. <bitWidth>1</bitWidth>
  5648. </field>
  5649. <field>
  5650. <name>PM</name>
  5651. <description>AM/PM notation</description>
  5652. <bitOffset>22</bitOffset>
  5653. <bitWidth>1</bitWidth>
  5654. </field>
  5655. <field>
  5656. <name>HT</name>
  5657. <description>Hour tens in BCD format</description>
  5658. <bitOffset>20</bitOffset>
  5659. <bitWidth>2</bitWidth>
  5660. </field>
  5661. <field>
  5662. <name>HU</name>
  5663. <description>Hour units in BCD format</description>
  5664. <bitOffset>16</bitOffset>
  5665. <bitWidth>4</bitWidth>
  5666. </field>
  5667. <field>
  5668. <name>MSK2</name>
  5669. <description>Alarm B minutes mask</description>
  5670. <bitOffset>15</bitOffset>
  5671. <bitWidth>1</bitWidth>
  5672. </field>
  5673. <field>
  5674. <name>MNT</name>
  5675. <description>Minute tens in BCD format</description>
  5676. <bitOffset>12</bitOffset>
  5677. <bitWidth>3</bitWidth>
  5678. </field>
  5679. <field>
  5680. <name>MNU</name>
  5681. <description>Minute units in BCD format</description>
  5682. <bitOffset>8</bitOffset>
  5683. <bitWidth>4</bitWidth>
  5684. </field>
  5685. <field>
  5686. <name>MSK1</name>
  5687. <description>Alarm B seconds mask</description>
  5688. <bitOffset>7</bitOffset>
  5689. <bitWidth>1</bitWidth>
  5690. </field>
  5691. <field>
  5692. <name>ST</name>
  5693. <description>Second tens in BCD format</description>
  5694. <bitOffset>4</bitOffset>
  5695. <bitWidth>3</bitWidth>
  5696. </field>
  5697. <field>
  5698. <name>SU</name>
  5699. <description>Second units in BCD format</description>
  5700. <bitOffset>0</bitOffset>
  5701. <bitWidth>4</bitWidth>
  5702. </field>
  5703. </fields>
  5704. </register>
  5705. <register>
  5706. <name>WPR</name>
  5707. <displayName>WPR</displayName>
  5708. <description>write protection register</description>
  5709. <addressOffset>0x24</addressOffset>
  5710. <size>0x20</size>
  5711. <access>write-only</access>
  5712. <resetValue>0x00000000</resetValue>
  5713. <fields>
  5714. <field>
  5715. <name>KEY</name>
  5716. <description>Write protection key</description>
  5717. <bitOffset>0</bitOffset>
  5718. <bitWidth>8</bitWidth>
  5719. </field>
  5720. </fields>
  5721. </register>
  5722. <register>
  5723. <name>SSR</name>
  5724. <displayName>SSR</displayName>
  5725. <description>RTC sub second register</description>
  5726. <addressOffset>0x28</addressOffset>
  5727. <size>0x20</size>
  5728. <access>read-only</access>
  5729. <resetValue>0x00000000</resetValue>
  5730. <fields>
  5731. <field>
  5732. <name>SS</name>
  5733. <description>Sub second value</description>
  5734. <bitOffset>0</bitOffset>
  5735. <bitWidth>16</bitWidth>
  5736. </field>
  5737. </fields>
  5738. </register>
  5739. <register>
  5740. <name>SHIFTR</name>
  5741. <displayName>SHIFTR</displayName>
  5742. <description>RTC shift control register</description>
  5743. <addressOffset>0x2C</addressOffset>
  5744. <size>0x20</size>
  5745. <access>write-only</access>
  5746. <resetValue>0x00000000</resetValue>
  5747. <fields>
  5748. <field>
  5749. <name>ADD1S</name>
  5750. <description>Add one second</description>
  5751. <bitOffset>31</bitOffset>
  5752. <bitWidth>1</bitWidth>
  5753. </field>
  5754. <field>
  5755. <name>SUBFS</name>
  5756. <description>Subtract a fraction of a
  5757. second</description>
  5758. <bitOffset>0</bitOffset>
  5759. <bitWidth>15</bitWidth>
  5760. </field>
  5761. </fields>
  5762. </register>
  5763. <register>
  5764. <name>TSTR</name>
  5765. <displayName>TSTR</displayName>
  5766. <description>RTC timestamp time register</description>
  5767. <addressOffset>0x30</addressOffset>
  5768. <size>0x20</size>
  5769. <access>read-only</access>
  5770. <resetValue>0x00000000</resetValue>
  5771. <fields>
  5772. <field>
  5773. <name>PM</name>
  5774. <description>AM/PM notation</description>
  5775. <bitOffset>22</bitOffset>
  5776. <bitWidth>1</bitWidth>
  5777. </field>
  5778. <field>
  5779. <name>HT</name>
  5780. <description>Hour tens in BCD format.</description>
  5781. <bitOffset>20</bitOffset>
  5782. <bitWidth>2</bitWidth>
  5783. </field>
  5784. <field>
  5785. <name>HU</name>
  5786. <description>Hour units in BCD format.</description>
  5787. <bitOffset>16</bitOffset>
  5788. <bitWidth>4</bitWidth>
  5789. </field>
  5790. <field>
  5791. <name>MNT</name>
  5792. <description>Minute tens in BCD format.</description>
  5793. <bitOffset>12</bitOffset>
  5794. <bitWidth>3</bitWidth>
  5795. </field>
  5796. <field>
  5797. <name>MNU</name>
  5798. <description>Minute units in BCD
  5799. format.</description>
  5800. <bitOffset>8</bitOffset>
  5801. <bitWidth>4</bitWidth>
  5802. </field>
  5803. <field>
  5804. <name>ST</name>
  5805. <description>Second tens in BCD format.</description>
  5806. <bitOffset>4</bitOffset>
  5807. <bitWidth>3</bitWidth>
  5808. </field>
  5809. <field>
  5810. <name>SU</name>
  5811. <description>Second units in BCD
  5812. format.</description>
  5813. <bitOffset>0</bitOffset>
  5814. <bitWidth>4</bitWidth>
  5815. </field>
  5816. </fields>
  5817. </register>
  5818. <register>
  5819. <name>TSDR</name>
  5820. <displayName>TSDR</displayName>
  5821. <description>RTC timestamp date register</description>
  5822. <addressOffset>0x34</addressOffset>
  5823. <size>0x20</size>
  5824. <access>read-only</access>
  5825. <resetValue>0x00000000</resetValue>
  5826. <fields>
  5827. <field>
  5828. <name>WDU</name>
  5829. <description>Week day units</description>
  5830. <bitOffset>13</bitOffset>
  5831. <bitWidth>3</bitWidth>
  5832. </field>
  5833. <field>
  5834. <name>MT</name>
  5835. <description>Month tens in BCD format</description>
  5836. <bitOffset>12</bitOffset>
  5837. <bitWidth>1</bitWidth>
  5838. </field>
  5839. <field>
  5840. <name>MU</name>
  5841. <description>Month units in BCD format</description>
  5842. <bitOffset>8</bitOffset>
  5843. <bitWidth>4</bitWidth>
  5844. </field>
  5845. <field>
  5846. <name>DT</name>
  5847. <description>Date tens in BCD format</description>
  5848. <bitOffset>4</bitOffset>
  5849. <bitWidth>2</bitWidth>
  5850. </field>
  5851. <field>
  5852. <name>DU</name>
  5853. <description>Date units in BCD format</description>
  5854. <bitOffset>0</bitOffset>
  5855. <bitWidth>4</bitWidth>
  5856. </field>
  5857. </fields>
  5858. </register>
  5859. <register>
  5860. <name>TSSSR</name>
  5861. <displayName>TSSSR</displayName>
  5862. <description>RTC time-stamp sub second
  5863. register</description>
  5864. <addressOffset>0x38</addressOffset>
  5865. <size>0x20</size>
  5866. <access>read-only</access>
  5867. <resetValue>0x00000000</resetValue>
  5868. <fields>
  5869. <field>
  5870. <name>SS</name>
  5871. <description>Sub second value</description>
  5872. <bitOffset>0</bitOffset>
  5873. <bitWidth>16</bitWidth>
  5874. </field>
  5875. </fields>
  5876. </register>
  5877. <register>
  5878. <name>CALR</name>
  5879. <displayName>CALR</displayName>
  5880. <description>RTC calibration register</description>
  5881. <addressOffset>0x3C</addressOffset>
  5882. <size>0x20</size>
  5883. <access>read-write</access>
  5884. <resetValue>0x00000000</resetValue>
  5885. <fields>
  5886. <field>
  5887. <name>CALP</name>
  5888. <description>Use an 8-second calibration cycle
  5889. period</description>
  5890. <bitOffset>15</bitOffset>
  5891. <bitWidth>1</bitWidth>
  5892. </field>
  5893. <field>
  5894. <name>CALW8</name>
  5895. <description>Use a 16-second calibration cycle
  5896. period</description>
  5897. <bitOffset>14</bitOffset>
  5898. <bitWidth>1</bitWidth>
  5899. </field>
  5900. <field>
  5901. <name>CALW16</name>
  5902. <description>Reserved</description>
  5903. <bitOffset>13</bitOffset>
  5904. <bitWidth>1</bitWidth>
  5905. </field>
  5906. <field>
  5907. <name>CALM</name>
  5908. <description>Calibration minus</description>
  5909. <bitOffset>0</bitOffset>
  5910. <bitWidth>9</bitWidth>
  5911. </field>
  5912. </fields>
  5913. </register>
  5914. <register>
  5915. <name>TAMPCR</name>
  5916. <displayName>TAMPCR</displayName>
  5917. <description>RTC tamper configuration
  5918. register</description>
  5919. <addressOffset>0x40</addressOffset>
  5920. <size>0x20</size>
  5921. <access>read-write</access>
  5922. <resetValue>0x00000000</resetValue>
  5923. <fields>
  5924. <field>
  5925. <name>TAMP2MF</name>
  5926. <description>Tamper 2 mask flag</description>
  5927. <bitOffset>21</bitOffset>
  5928. <bitWidth>1</bitWidth>
  5929. </field>
  5930. <field>
  5931. <name>TAMP2NOERASE</name>
  5932. <description>Tamper 2 no erase</description>
  5933. <bitOffset>20</bitOffset>
  5934. <bitWidth>1</bitWidth>
  5935. </field>
  5936. <field>
  5937. <name>TAMP2IE</name>
  5938. <description>Tamper 2 interrupt enable</description>
  5939. <bitOffset>19</bitOffset>
  5940. <bitWidth>1</bitWidth>
  5941. </field>
  5942. <field>
  5943. <name>TAMP1MF</name>
  5944. <description>Tamper 1 mask flag</description>
  5945. <bitOffset>18</bitOffset>
  5946. <bitWidth>1</bitWidth>
  5947. </field>
  5948. <field>
  5949. <name>TAMP1NOERASE</name>
  5950. <description>Tamper 1 no erase</description>
  5951. <bitOffset>17</bitOffset>
  5952. <bitWidth>1</bitWidth>
  5953. </field>
  5954. <field>
  5955. <name>TAMP1IE</name>
  5956. <description>Tamper 1 interrupt enable</description>
  5957. <bitOffset>16</bitOffset>
  5958. <bitWidth>1</bitWidth>
  5959. </field>
  5960. <field>
  5961. <name>TAMPPUDIS</name>
  5962. <description>RTC_TAMPx pull-up disable</description>
  5963. <bitOffset>15</bitOffset>
  5964. <bitWidth>1</bitWidth>
  5965. </field>
  5966. <field>
  5967. <name>TAMPPRCH</name>
  5968. <description>RTC_TAMPx precharge
  5969. duration</description>
  5970. <bitOffset>13</bitOffset>
  5971. <bitWidth>2</bitWidth>
  5972. </field>
  5973. <field>
  5974. <name>TAMPFLT</name>
  5975. <description>RTC_TAMPx filter count</description>
  5976. <bitOffset>11</bitOffset>
  5977. <bitWidth>2</bitWidth>
  5978. </field>
  5979. <field>
  5980. <name>TAMPFREQ</name>
  5981. <description>Tamper sampling frequency</description>
  5982. <bitOffset>8</bitOffset>
  5983. <bitWidth>3</bitWidth>
  5984. </field>
  5985. <field>
  5986. <name>TAMPTS</name>
  5987. <description>Activate timestamp on tamper detection
  5988. event</description>
  5989. <bitOffset>7</bitOffset>
  5990. <bitWidth>1</bitWidth>
  5991. </field>
  5992. <field>
  5993. <name>TAMP2_TRG</name>
  5994. <description>Active level for RTC_TAMP2
  5995. input</description>
  5996. <bitOffset>4</bitOffset>
  5997. <bitWidth>1</bitWidth>
  5998. </field>
  5999. <field>
  6000. <name>TAMP2E</name>
  6001. <description>RTC_TAMP2 input detection
  6002. enable</description>
  6003. <bitOffset>3</bitOffset>
  6004. <bitWidth>1</bitWidth>
  6005. </field>
  6006. <field>
  6007. <name>TAMPIE</name>
  6008. <description>Tamper interrupt enable</description>
  6009. <bitOffset>2</bitOffset>
  6010. <bitWidth>1</bitWidth>
  6011. </field>
  6012. <field>
  6013. <name>TAMP1TRG</name>
  6014. <description>Active level for RTC_TAMP1
  6015. input</description>
  6016. <bitOffset>1</bitOffset>
  6017. <bitWidth>1</bitWidth>
  6018. </field>
  6019. <field>
  6020. <name>TAMP1E</name>
  6021. <description>RTC_TAMP1 input detection
  6022. enable</description>
  6023. <bitOffset>0</bitOffset>
  6024. <bitWidth>1</bitWidth>
  6025. </field>
  6026. </fields>
  6027. </register>
  6028. <register>
  6029. <name>ALRMASSR</name>
  6030. <displayName>ALRMASSR</displayName>
  6031. <description>RTC alarm A sub second
  6032. register</description>
  6033. <addressOffset>0x44</addressOffset>
  6034. <size>0x20</size>
  6035. <access>read-write</access>
  6036. <resetValue>0x00000000</resetValue>
  6037. <fields>
  6038. <field>
  6039. <name>MASKSS</name>
  6040. <description>Mask the most-significant bits starting
  6041. at this bit</description>
  6042. <bitOffset>24</bitOffset>
  6043. <bitWidth>4</bitWidth>
  6044. </field>
  6045. <field>
  6046. <name>SS</name>
  6047. <description>Sub seconds value</description>
  6048. <bitOffset>0</bitOffset>
  6049. <bitWidth>15</bitWidth>
  6050. </field>
  6051. </fields>
  6052. </register>
  6053. <register>
  6054. <name>ALRMBSSR</name>
  6055. <displayName>ALRMBSSR</displayName>
  6056. <description>RTC alarm B sub second
  6057. register</description>
  6058. <addressOffset>0x48</addressOffset>
  6059. <size>0x20</size>
  6060. <access>read-write</access>
  6061. <resetValue>0x00000000</resetValue>
  6062. <fields>
  6063. <field>
  6064. <name>MASKSS</name>
  6065. <description>Mask the most-significant bits starting
  6066. at this bit</description>
  6067. <bitOffset>24</bitOffset>
  6068. <bitWidth>4</bitWidth>
  6069. </field>
  6070. <field>
  6071. <name>SS</name>
  6072. <description>Sub seconds value</description>
  6073. <bitOffset>0</bitOffset>
  6074. <bitWidth>15</bitWidth>
  6075. </field>
  6076. </fields>
  6077. </register>
  6078. <register>
  6079. <name>OR</name>
  6080. <displayName>OR</displayName>
  6081. <description>option register</description>
  6082. <addressOffset>0x4C</addressOffset>
  6083. <size>0x20</size>
  6084. <access>read-write</access>
  6085. <resetValue>0x00000000</resetValue>
  6086. <fields>
  6087. <field>
  6088. <name>RTC_OUT_RMP</name>
  6089. <description>RTC_ALARM on PC13 output
  6090. type</description>
  6091. <bitOffset>1</bitOffset>
  6092. <bitWidth>1</bitWidth>
  6093. </field>
  6094. <field>
  6095. <name>RTC_ALARM_TYPE</name>
  6096. <description>RTC_ALARM on PC13 output
  6097. type</description>
  6098. <bitOffset>0</bitOffset>
  6099. <bitWidth>1</bitWidth>
  6100. </field>
  6101. </fields>
  6102. </register>
  6103. <register>
  6104. <name>BKP0R</name>
  6105. <displayName>BKP0R</displayName>
  6106. <description>RTC backup registers</description>
  6107. <addressOffset>0x50</addressOffset>
  6108. <size>0x20</size>
  6109. <access>read-write</access>
  6110. <resetValue>0x00000000</resetValue>
  6111. <fields>
  6112. <field>
  6113. <name>BKP</name>
  6114. <description>BKP</description>
  6115. <bitOffset>0</bitOffset>
  6116. <bitWidth>32</bitWidth>
  6117. </field>
  6118. </fields>
  6119. </register>
  6120. <register>
  6121. <name>BKP1R</name>
  6122. <displayName>BKP1R</displayName>
  6123. <description>RTC backup registers</description>
  6124. <addressOffset>0x54</addressOffset>
  6125. <size>0x20</size>
  6126. <access>read-write</access>
  6127. <resetValue>0x00000000</resetValue>
  6128. <fields>
  6129. <field>
  6130. <name>BKP</name>
  6131. <description>BKP</description>
  6132. <bitOffset>0</bitOffset>
  6133. <bitWidth>32</bitWidth>
  6134. </field>
  6135. </fields>
  6136. </register>
  6137. <register>
  6138. <name>BKP2R</name>
  6139. <displayName>BKP2R</displayName>
  6140. <description>RTC backup registers</description>
  6141. <addressOffset>0x58</addressOffset>
  6142. <size>0x20</size>
  6143. <access>read-write</access>
  6144. <resetValue>0x00000000</resetValue>
  6145. <fields>
  6146. <field>
  6147. <name>BKP</name>
  6148. <description>BKP</description>
  6149. <bitOffset>0</bitOffset>
  6150. <bitWidth>32</bitWidth>
  6151. </field>
  6152. </fields>
  6153. </register>
  6154. <register>
  6155. <name>BKP3R</name>
  6156. <displayName>BKP3R</displayName>
  6157. <description>RTC backup registers</description>
  6158. <addressOffset>0x5C</addressOffset>
  6159. <size>0x20</size>
  6160. <access>read-write</access>
  6161. <resetValue>0x00000000</resetValue>
  6162. <fields>
  6163. <field>
  6164. <name>BKP</name>
  6165. <description>BKP</description>
  6166. <bitOffset>0</bitOffset>
  6167. <bitWidth>32</bitWidth>
  6168. </field>
  6169. </fields>
  6170. </register>
  6171. <register>
  6172. <name>BKP4R</name>
  6173. <displayName>BKP4R</displayName>
  6174. <description>RTC backup registers</description>
  6175. <addressOffset>0x60</addressOffset>
  6176. <size>0x20</size>
  6177. <access>read-write</access>
  6178. <resetValue>0x00000000</resetValue>
  6179. <fields>
  6180. <field>
  6181. <name>BKP</name>
  6182. <description>BKP</description>
  6183. <bitOffset>0</bitOffset>
  6184. <bitWidth>32</bitWidth>
  6185. </field>
  6186. </fields>
  6187. </register>
  6188. </registers>
  6189. </peripheral>
  6190. <peripheral>
  6191. <name>USART1</name>
  6192. <description>Universal synchronous asynchronous receiver
  6193. transmitter</description>
  6194. <groupName>USART</groupName>
  6195. <baseAddress>0x40013800</baseAddress>
  6196. <addressBlock>
  6197. <offset>0x0</offset>
  6198. <size>0x400</size>
  6199. <usage>registers</usage>
  6200. </addressBlock>
  6201. <interrupt>
  6202. <name>USART1</name>
  6203. <description>USART1 global interrupt</description>
  6204. <value>27</value>
  6205. </interrupt>
  6206. <registers>
  6207. <register>
  6208. <name>CR1</name>
  6209. <displayName>CR1</displayName>
  6210. <description>Control register 1</description>
  6211. <addressOffset>0x0</addressOffset>
  6212. <size>0x20</size>
  6213. <access>read-write</access>
  6214. <resetValue>0x0000</resetValue>
  6215. <fields>
  6216. <field>
  6217. <name>M1</name>
  6218. <description>Word length</description>
  6219. <bitOffset>28</bitOffset>
  6220. <bitWidth>1</bitWidth>
  6221. </field>
  6222. <field>
  6223. <name>EOBIE</name>
  6224. <description>End of Block interrupt
  6225. enable</description>
  6226. <bitOffset>27</bitOffset>
  6227. <bitWidth>1</bitWidth>
  6228. </field>
  6229. <field>
  6230. <name>RTOIE</name>
  6231. <description>Receiver timeout interrupt
  6232. enable</description>
  6233. <bitOffset>26</bitOffset>
  6234. <bitWidth>1</bitWidth>
  6235. </field>
  6236. <field>
  6237. <name>DEAT4</name>
  6238. <description>Driver Enable assertion
  6239. time</description>
  6240. <bitOffset>25</bitOffset>
  6241. <bitWidth>1</bitWidth>
  6242. </field>
  6243. <field>
  6244. <name>DEAT3</name>
  6245. <description>DEAT3</description>
  6246. <bitOffset>24</bitOffset>
  6247. <bitWidth>1</bitWidth>
  6248. </field>
  6249. <field>
  6250. <name>DEAT2</name>
  6251. <description>DEAT2</description>
  6252. <bitOffset>23</bitOffset>
  6253. <bitWidth>1</bitWidth>
  6254. </field>
  6255. <field>
  6256. <name>DEAT1</name>
  6257. <description>DEAT1</description>
  6258. <bitOffset>22</bitOffset>
  6259. <bitWidth>1</bitWidth>
  6260. </field>
  6261. <field>
  6262. <name>DEAT0</name>
  6263. <description>DEAT0</description>
  6264. <bitOffset>21</bitOffset>
  6265. <bitWidth>1</bitWidth>
  6266. </field>
  6267. <field>
  6268. <name>DEDT4</name>
  6269. <description>Driver Enable de-assertion
  6270. time</description>
  6271. <bitOffset>20</bitOffset>
  6272. <bitWidth>1</bitWidth>
  6273. </field>
  6274. <field>
  6275. <name>DEDT3</name>
  6276. <description>DEDT3</description>
  6277. <bitOffset>19</bitOffset>
  6278. <bitWidth>1</bitWidth>
  6279. </field>
  6280. <field>
  6281. <name>DEDT2</name>
  6282. <description>DEDT2</description>
  6283. <bitOffset>18</bitOffset>
  6284. <bitWidth>1</bitWidth>
  6285. </field>
  6286. <field>
  6287. <name>DEDT1</name>
  6288. <description>DEDT1</description>
  6289. <bitOffset>17</bitOffset>
  6290. <bitWidth>1</bitWidth>
  6291. </field>
  6292. <field>
  6293. <name>DEDT0</name>
  6294. <description>DEDT0</description>
  6295. <bitOffset>16</bitOffset>
  6296. <bitWidth>1</bitWidth>
  6297. </field>
  6298. <field>
  6299. <name>OVER8</name>
  6300. <description>Oversampling mode</description>
  6301. <bitOffset>15</bitOffset>
  6302. <bitWidth>1</bitWidth>
  6303. </field>
  6304. <field>
  6305. <name>CMIE</name>
  6306. <description>Character match interrupt
  6307. enable</description>
  6308. <bitOffset>14</bitOffset>
  6309. <bitWidth>1</bitWidth>
  6310. </field>
  6311. <field>
  6312. <name>MME</name>
  6313. <description>Mute mode enable</description>
  6314. <bitOffset>13</bitOffset>
  6315. <bitWidth>1</bitWidth>
  6316. </field>
  6317. <field>
  6318. <name>M0</name>
  6319. <description>Word length</description>
  6320. <bitOffset>12</bitOffset>
  6321. <bitWidth>1</bitWidth>
  6322. </field>
  6323. <field>
  6324. <name>WAKE</name>
  6325. <description>Receiver wakeup method</description>
  6326. <bitOffset>11</bitOffset>
  6327. <bitWidth>1</bitWidth>
  6328. </field>
  6329. <field>
  6330. <name>PCE</name>
  6331. <description>Parity control enable</description>
  6332. <bitOffset>10</bitOffset>
  6333. <bitWidth>1</bitWidth>
  6334. </field>
  6335. <field>
  6336. <name>PS</name>
  6337. <description>Parity selection</description>
  6338. <bitOffset>9</bitOffset>
  6339. <bitWidth>1</bitWidth>
  6340. </field>
  6341. <field>
  6342. <name>PEIE</name>
  6343. <description>PE interrupt enable</description>
  6344. <bitOffset>8</bitOffset>
  6345. <bitWidth>1</bitWidth>
  6346. </field>
  6347. <field>
  6348. <name>TXEIE</name>
  6349. <description>interrupt enable</description>
  6350. <bitOffset>7</bitOffset>
  6351. <bitWidth>1</bitWidth>
  6352. </field>
  6353. <field>
  6354. <name>TCIE</name>
  6355. <description>Transmission complete interrupt
  6356. enable</description>
  6357. <bitOffset>6</bitOffset>
  6358. <bitWidth>1</bitWidth>
  6359. </field>
  6360. <field>
  6361. <name>RXNEIE</name>
  6362. <description>RXNE interrupt enable</description>
  6363. <bitOffset>5</bitOffset>
  6364. <bitWidth>1</bitWidth>
  6365. </field>
  6366. <field>
  6367. <name>IDLEIE</name>
  6368. <description>IDLE interrupt enable</description>
  6369. <bitOffset>4</bitOffset>
  6370. <bitWidth>1</bitWidth>
  6371. </field>
  6372. <field>
  6373. <name>TE</name>
  6374. <description>Transmitter enable</description>
  6375. <bitOffset>3</bitOffset>
  6376. <bitWidth>1</bitWidth>
  6377. </field>
  6378. <field>
  6379. <name>RE</name>
  6380. <description>Receiver enable</description>
  6381. <bitOffset>2</bitOffset>
  6382. <bitWidth>1</bitWidth>
  6383. </field>
  6384. <field>
  6385. <name>UESM</name>
  6386. <description>USART enable in Stop mode</description>
  6387. <bitOffset>1</bitOffset>
  6388. <bitWidth>1</bitWidth>
  6389. </field>
  6390. <field>
  6391. <name>UE</name>
  6392. <description>USART enable</description>
  6393. <bitOffset>0</bitOffset>
  6394. <bitWidth>1</bitWidth>
  6395. </field>
  6396. </fields>
  6397. </register>
  6398. <register>
  6399. <name>CR2</name>
  6400. <displayName>CR2</displayName>
  6401. <description>Control register 2</description>
  6402. <addressOffset>0x4</addressOffset>
  6403. <size>0x20</size>
  6404. <access>read-write</access>
  6405. <resetValue>0x0000</resetValue>
  6406. <fields>
  6407. <field>
  6408. <name>ADD4_7</name>
  6409. <description>Address of the USART node</description>
  6410. <bitOffset>28</bitOffset>
  6411. <bitWidth>4</bitWidth>
  6412. </field>
  6413. <field>
  6414. <name>ADD0_3</name>
  6415. <description>Address of the USART node</description>
  6416. <bitOffset>24</bitOffset>
  6417. <bitWidth>4</bitWidth>
  6418. </field>
  6419. <field>
  6420. <name>RTOEN</name>
  6421. <description>Receiver timeout enable</description>
  6422. <bitOffset>23</bitOffset>
  6423. <bitWidth>1</bitWidth>
  6424. </field>
  6425. <field>
  6426. <name>ABRMOD1</name>
  6427. <description>Auto baud rate mode</description>
  6428. <bitOffset>22</bitOffset>
  6429. <bitWidth>1</bitWidth>
  6430. </field>
  6431. <field>
  6432. <name>ABRMOD0</name>
  6433. <description>ABRMOD0</description>
  6434. <bitOffset>21</bitOffset>
  6435. <bitWidth>1</bitWidth>
  6436. </field>
  6437. <field>
  6438. <name>ABREN</name>
  6439. <description>Auto baud rate enable</description>
  6440. <bitOffset>20</bitOffset>
  6441. <bitWidth>1</bitWidth>
  6442. </field>
  6443. <field>
  6444. <name>MSBFIRST</name>
  6445. <description>Most significant bit first</description>
  6446. <bitOffset>19</bitOffset>
  6447. <bitWidth>1</bitWidth>
  6448. </field>
  6449. <field>
  6450. <name>TAINV</name>
  6451. <description>Binary data inversion</description>
  6452. <bitOffset>18</bitOffset>
  6453. <bitWidth>1</bitWidth>
  6454. </field>
  6455. <field>
  6456. <name>TXINV</name>
  6457. <description>TX pin active level
  6458. inversion</description>
  6459. <bitOffset>17</bitOffset>
  6460. <bitWidth>1</bitWidth>
  6461. </field>
  6462. <field>
  6463. <name>RXINV</name>
  6464. <description>RX pin active level
  6465. inversion</description>
  6466. <bitOffset>16</bitOffset>
  6467. <bitWidth>1</bitWidth>
  6468. </field>
  6469. <field>
  6470. <name>SWAP</name>
  6471. <description>Swap TX/RX pins</description>
  6472. <bitOffset>15</bitOffset>
  6473. <bitWidth>1</bitWidth>
  6474. </field>
  6475. <field>
  6476. <name>LINEN</name>
  6477. <description>LIN mode enable</description>
  6478. <bitOffset>14</bitOffset>
  6479. <bitWidth>1</bitWidth>
  6480. </field>
  6481. <field>
  6482. <name>STOP</name>
  6483. <description>STOP bits</description>
  6484. <bitOffset>12</bitOffset>
  6485. <bitWidth>2</bitWidth>
  6486. </field>
  6487. <field>
  6488. <name>CLKEN</name>
  6489. <description>Clock enable</description>
  6490. <bitOffset>11</bitOffset>
  6491. <bitWidth>1</bitWidth>
  6492. </field>
  6493. <field>
  6494. <name>CPOL</name>
  6495. <description>Clock polarity</description>
  6496. <bitOffset>10</bitOffset>
  6497. <bitWidth>1</bitWidth>
  6498. </field>
  6499. <field>
  6500. <name>CPHA</name>
  6501. <description>Clock phase</description>
  6502. <bitOffset>9</bitOffset>
  6503. <bitWidth>1</bitWidth>
  6504. </field>
  6505. <field>
  6506. <name>LBCL</name>
  6507. <description>Last bit clock pulse</description>
  6508. <bitOffset>8</bitOffset>
  6509. <bitWidth>1</bitWidth>
  6510. </field>
  6511. <field>
  6512. <name>LBDIE</name>
  6513. <description>LIN break detection interrupt
  6514. enable</description>
  6515. <bitOffset>6</bitOffset>
  6516. <bitWidth>1</bitWidth>
  6517. </field>
  6518. <field>
  6519. <name>LBDL</name>
  6520. <description>LIN break detection length</description>
  6521. <bitOffset>5</bitOffset>
  6522. <bitWidth>1</bitWidth>
  6523. </field>
  6524. <field>
  6525. <name>ADDM7</name>
  6526. <description>7-bit Address Detection/4-bit Address
  6527. Detection</description>
  6528. <bitOffset>4</bitOffset>
  6529. <bitWidth>1</bitWidth>
  6530. </field>
  6531. </fields>
  6532. </register>
  6533. <register>
  6534. <name>CR3</name>
  6535. <displayName>CR3</displayName>
  6536. <description>Control register 3</description>
  6537. <addressOffset>0x8</addressOffset>
  6538. <size>0x20</size>
  6539. <access>read-write</access>
  6540. <resetValue>0x0000</resetValue>
  6541. <fields>
  6542. <field>
  6543. <name>WUFIE</name>
  6544. <description>Wakeup from Stop mode interrupt
  6545. enable</description>
  6546. <bitOffset>22</bitOffset>
  6547. <bitWidth>1</bitWidth>
  6548. </field>
  6549. <field>
  6550. <name>WUS</name>
  6551. <description>Wakeup from Stop mode interrupt flag
  6552. selection</description>
  6553. <bitOffset>20</bitOffset>
  6554. <bitWidth>2</bitWidth>
  6555. </field>
  6556. <field>
  6557. <name>SCARCNT</name>
  6558. <description>Smartcard auto-retry count</description>
  6559. <bitOffset>17</bitOffset>
  6560. <bitWidth>3</bitWidth>
  6561. </field>
  6562. <field>
  6563. <name>DEP</name>
  6564. <description>Driver enable polarity
  6565. selection</description>
  6566. <bitOffset>15</bitOffset>
  6567. <bitWidth>1</bitWidth>
  6568. </field>
  6569. <field>
  6570. <name>DEM</name>
  6571. <description>Driver enable mode</description>
  6572. <bitOffset>14</bitOffset>
  6573. <bitWidth>1</bitWidth>
  6574. </field>
  6575. <field>
  6576. <name>DDRE</name>
  6577. <description>DMA Disable on Reception
  6578. Error</description>
  6579. <bitOffset>13</bitOffset>
  6580. <bitWidth>1</bitWidth>
  6581. </field>
  6582. <field>
  6583. <name>OVRDIS</name>
  6584. <description>Overrun Disable</description>
  6585. <bitOffset>12</bitOffset>
  6586. <bitWidth>1</bitWidth>
  6587. </field>
  6588. <field>
  6589. <name>ONEBIT</name>
  6590. <description>One sample bit method
  6591. enable</description>
  6592. <bitOffset>11</bitOffset>
  6593. <bitWidth>1</bitWidth>
  6594. </field>
  6595. <field>
  6596. <name>CTSIE</name>
  6597. <description>CTS interrupt enable</description>
  6598. <bitOffset>10</bitOffset>
  6599. <bitWidth>1</bitWidth>
  6600. </field>
  6601. <field>
  6602. <name>CTSE</name>
  6603. <description>CTS enable</description>
  6604. <bitOffset>9</bitOffset>
  6605. <bitWidth>1</bitWidth>
  6606. </field>
  6607. <field>
  6608. <name>RTSE</name>
  6609. <description>RTS enable</description>
  6610. <bitOffset>8</bitOffset>
  6611. <bitWidth>1</bitWidth>
  6612. </field>
  6613. <field>
  6614. <name>DMAT</name>
  6615. <description>DMA enable transmitter</description>
  6616. <bitOffset>7</bitOffset>
  6617. <bitWidth>1</bitWidth>
  6618. </field>
  6619. <field>
  6620. <name>DMAR</name>
  6621. <description>DMA enable receiver</description>
  6622. <bitOffset>6</bitOffset>
  6623. <bitWidth>1</bitWidth>
  6624. </field>
  6625. <field>
  6626. <name>SCEN</name>
  6627. <description>Smartcard mode enable</description>
  6628. <bitOffset>5</bitOffset>
  6629. <bitWidth>1</bitWidth>
  6630. </field>
  6631. <field>
  6632. <name>NACK</name>
  6633. <description>Smartcard NACK enable</description>
  6634. <bitOffset>4</bitOffset>
  6635. <bitWidth>1</bitWidth>
  6636. </field>
  6637. <field>
  6638. <name>HDSEL</name>
  6639. <description>Half-duplex selection</description>
  6640. <bitOffset>3</bitOffset>
  6641. <bitWidth>1</bitWidth>
  6642. </field>
  6643. <field>
  6644. <name>IRLP</name>
  6645. <description>Ir low-power</description>
  6646. <bitOffset>2</bitOffset>
  6647. <bitWidth>1</bitWidth>
  6648. </field>
  6649. <field>
  6650. <name>IREN</name>
  6651. <description>Ir mode enable</description>
  6652. <bitOffset>1</bitOffset>
  6653. <bitWidth>1</bitWidth>
  6654. </field>
  6655. <field>
  6656. <name>EIE</name>
  6657. <description>Error interrupt enable</description>
  6658. <bitOffset>0</bitOffset>
  6659. <bitWidth>1</bitWidth>
  6660. </field>
  6661. </fields>
  6662. </register>
  6663. <register>
  6664. <name>BRR</name>
  6665. <displayName>BRR</displayName>
  6666. <description>Baud rate register</description>
  6667. <addressOffset>0xC</addressOffset>
  6668. <size>0x20</size>
  6669. <access>read-write</access>
  6670. <resetValue>0x0000</resetValue>
  6671. <fields>
  6672. <field>
  6673. <name>DIV_Mantissa</name>
  6674. <description>DIV_Mantissa</description>
  6675. <bitOffset>4</bitOffset>
  6676. <bitWidth>12</bitWidth>
  6677. </field>
  6678. <field>
  6679. <name>DIV_Fraction</name>
  6680. <description>DIV_Fraction</description>
  6681. <bitOffset>0</bitOffset>
  6682. <bitWidth>4</bitWidth>
  6683. </field>
  6684. </fields>
  6685. </register>
  6686. <register>
  6687. <name>GTPR</name>
  6688. <displayName>GTPR</displayName>
  6689. <description>Guard time and prescaler
  6690. register</description>
  6691. <addressOffset>0x10</addressOffset>
  6692. <size>0x20</size>
  6693. <access>read-write</access>
  6694. <resetValue>0x0000</resetValue>
  6695. <fields>
  6696. <field>
  6697. <name>GT</name>
  6698. <description>Guard time value</description>
  6699. <bitOffset>8</bitOffset>
  6700. <bitWidth>8</bitWidth>
  6701. </field>
  6702. <field>
  6703. <name>PSC</name>
  6704. <description>Prescaler value</description>
  6705. <bitOffset>0</bitOffset>
  6706. <bitWidth>8</bitWidth>
  6707. </field>
  6708. </fields>
  6709. </register>
  6710. <register>
  6711. <name>RTOR</name>
  6712. <displayName>RTOR</displayName>
  6713. <description>Receiver timeout register</description>
  6714. <addressOffset>0x14</addressOffset>
  6715. <size>0x20</size>
  6716. <access>read-write</access>
  6717. <resetValue>0x0000</resetValue>
  6718. <fields>
  6719. <field>
  6720. <name>BLEN</name>
  6721. <description>Block Length</description>
  6722. <bitOffset>24</bitOffset>
  6723. <bitWidth>8</bitWidth>
  6724. </field>
  6725. <field>
  6726. <name>RTO</name>
  6727. <description>Receiver timeout value</description>
  6728. <bitOffset>0</bitOffset>
  6729. <bitWidth>24</bitWidth>
  6730. </field>
  6731. </fields>
  6732. </register>
  6733. <register>
  6734. <name>RQR</name>
  6735. <displayName>RQR</displayName>
  6736. <description>Request register</description>
  6737. <addressOffset>0x18</addressOffset>
  6738. <size>0x20</size>
  6739. <access>write-only</access>
  6740. <resetValue>0x0000</resetValue>
  6741. <fields>
  6742. <field>
  6743. <name>TXFRQ</name>
  6744. <description>Transmit data flush
  6745. request</description>
  6746. <bitOffset>4</bitOffset>
  6747. <bitWidth>1</bitWidth>
  6748. </field>
  6749. <field>
  6750. <name>RXFRQ</name>
  6751. <description>Receive data flush request</description>
  6752. <bitOffset>3</bitOffset>
  6753. <bitWidth>1</bitWidth>
  6754. </field>
  6755. <field>
  6756. <name>MMRQ</name>
  6757. <description>Mute mode request</description>
  6758. <bitOffset>2</bitOffset>
  6759. <bitWidth>1</bitWidth>
  6760. </field>
  6761. <field>
  6762. <name>SBKRQ</name>
  6763. <description>Send break request</description>
  6764. <bitOffset>1</bitOffset>
  6765. <bitWidth>1</bitWidth>
  6766. </field>
  6767. <field>
  6768. <name>ABRRQ</name>
  6769. <description>Auto baud rate request</description>
  6770. <bitOffset>0</bitOffset>
  6771. <bitWidth>1</bitWidth>
  6772. </field>
  6773. </fields>
  6774. </register>
  6775. <register>
  6776. <name>ISR</name>
  6777. <displayName>ISR</displayName>
  6778. <description>Interrupt &amp; status
  6779. register</description>
  6780. <addressOffset>0x1C</addressOffset>
  6781. <size>0x20</size>
  6782. <access>read-only</access>
  6783. <resetValue>0x00C0</resetValue>
  6784. <fields>
  6785. <field>
  6786. <name>REACK</name>
  6787. <description>REACK</description>
  6788. <bitOffset>22</bitOffset>
  6789. <bitWidth>1</bitWidth>
  6790. </field>
  6791. <field>
  6792. <name>TEACK</name>
  6793. <description>TEACK</description>
  6794. <bitOffset>21</bitOffset>
  6795. <bitWidth>1</bitWidth>
  6796. </field>
  6797. <field>
  6798. <name>WUF</name>
  6799. <description>WUF</description>
  6800. <bitOffset>20</bitOffset>
  6801. <bitWidth>1</bitWidth>
  6802. </field>
  6803. <field>
  6804. <name>RWU</name>
  6805. <description>RWU</description>
  6806. <bitOffset>19</bitOffset>
  6807. <bitWidth>1</bitWidth>
  6808. </field>
  6809. <field>
  6810. <name>SBKF</name>
  6811. <description>SBKF</description>
  6812. <bitOffset>18</bitOffset>
  6813. <bitWidth>1</bitWidth>
  6814. </field>
  6815. <field>
  6816. <name>CMF</name>
  6817. <description>CMF</description>
  6818. <bitOffset>17</bitOffset>
  6819. <bitWidth>1</bitWidth>
  6820. </field>
  6821. <field>
  6822. <name>BUSY</name>
  6823. <description>BUSY</description>
  6824. <bitOffset>16</bitOffset>
  6825. <bitWidth>1</bitWidth>
  6826. </field>
  6827. <field>
  6828. <name>ABRF</name>
  6829. <description>ABRF</description>
  6830. <bitOffset>15</bitOffset>
  6831. <bitWidth>1</bitWidth>
  6832. </field>
  6833. <field>
  6834. <name>ABRE</name>
  6835. <description>ABRE</description>
  6836. <bitOffset>14</bitOffset>
  6837. <bitWidth>1</bitWidth>
  6838. </field>
  6839. <field>
  6840. <name>EOBF</name>
  6841. <description>EOBF</description>
  6842. <bitOffset>12</bitOffset>
  6843. <bitWidth>1</bitWidth>
  6844. </field>
  6845. <field>
  6846. <name>RTOF</name>
  6847. <description>RTOF</description>
  6848. <bitOffset>11</bitOffset>
  6849. <bitWidth>1</bitWidth>
  6850. </field>
  6851. <field>
  6852. <name>CTS</name>
  6853. <description>CTS</description>
  6854. <bitOffset>10</bitOffset>
  6855. <bitWidth>1</bitWidth>
  6856. </field>
  6857. <field>
  6858. <name>CTSIF</name>
  6859. <description>CTSIF</description>
  6860. <bitOffset>9</bitOffset>
  6861. <bitWidth>1</bitWidth>
  6862. </field>
  6863. <field>
  6864. <name>LBDF</name>
  6865. <description>LBDF</description>
  6866. <bitOffset>8</bitOffset>
  6867. <bitWidth>1</bitWidth>
  6868. </field>
  6869. <field>
  6870. <name>TXE</name>
  6871. <description>TXE</description>
  6872. <bitOffset>7</bitOffset>
  6873. <bitWidth>1</bitWidth>
  6874. </field>
  6875. <field>
  6876. <name>TC</name>
  6877. <description>TC</description>
  6878. <bitOffset>6</bitOffset>
  6879. <bitWidth>1</bitWidth>
  6880. </field>
  6881. <field>
  6882. <name>RXNE</name>
  6883. <description>RXNE</description>
  6884. <bitOffset>5</bitOffset>
  6885. <bitWidth>1</bitWidth>
  6886. </field>
  6887. <field>
  6888. <name>IDLE</name>
  6889. <description>IDLE</description>
  6890. <bitOffset>4</bitOffset>
  6891. <bitWidth>1</bitWidth>
  6892. </field>
  6893. <field>
  6894. <name>ORE</name>
  6895. <description>ORE</description>
  6896. <bitOffset>3</bitOffset>
  6897. <bitWidth>1</bitWidth>
  6898. </field>
  6899. <field>
  6900. <name>NF</name>
  6901. <description>NF</description>
  6902. <bitOffset>2</bitOffset>
  6903. <bitWidth>1</bitWidth>
  6904. </field>
  6905. <field>
  6906. <name>FE</name>
  6907. <description>FE</description>
  6908. <bitOffset>1</bitOffset>
  6909. <bitWidth>1</bitWidth>
  6910. </field>
  6911. <field>
  6912. <name>PE</name>
  6913. <description>PE</description>
  6914. <bitOffset>0</bitOffset>
  6915. <bitWidth>1</bitWidth>
  6916. </field>
  6917. </fields>
  6918. </register>
  6919. <register>
  6920. <name>ICR</name>
  6921. <displayName>ICR</displayName>
  6922. <description>Interrupt flag clear register</description>
  6923. <addressOffset>0x20</addressOffset>
  6924. <size>0x20</size>
  6925. <access>write-only</access>
  6926. <resetValue>0x0000</resetValue>
  6927. <fields>
  6928. <field>
  6929. <name>WUCF</name>
  6930. <description>Wakeup from Stop mode clear
  6931. flag</description>
  6932. <bitOffset>20</bitOffset>
  6933. <bitWidth>1</bitWidth>
  6934. </field>
  6935. <field>
  6936. <name>CMCF</name>
  6937. <description>Character match clear flag</description>
  6938. <bitOffset>17</bitOffset>
  6939. <bitWidth>1</bitWidth>
  6940. </field>
  6941. <field>
  6942. <name>EOBCF</name>
  6943. <description>End of block clear flag</description>
  6944. <bitOffset>12</bitOffset>
  6945. <bitWidth>1</bitWidth>
  6946. </field>
  6947. <field>
  6948. <name>RTOCF</name>
  6949. <description>Receiver timeout clear
  6950. flag</description>
  6951. <bitOffset>11</bitOffset>
  6952. <bitWidth>1</bitWidth>
  6953. </field>
  6954. <field>
  6955. <name>CTSCF</name>
  6956. <description>CTS clear flag</description>
  6957. <bitOffset>9</bitOffset>
  6958. <bitWidth>1</bitWidth>
  6959. </field>
  6960. <field>
  6961. <name>LBDCF</name>
  6962. <description>LIN break detection clear
  6963. flag</description>
  6964. <bitOffset>8</bitOffset>
  6965. <bitWidth>1</bitWidth>
  6966. </field>
  6967. <field>
  6968. <name>TCCF</name>
  6969. <description>Transmission complete clear
  6970. flag</description>
  6971. <bitOffset>6</bitOffset>
  6972. <bitWidth>1</bitWidth>
  6973. </field>
  6974. <field>
  6975. <name>IDLECF</name>
  6976. <description>Idle line detected clear
  6977. flag</description>
  6978. <bitOffset>4</bitOffset>
  6979. <bitWidth>1</bitWidth>
  6980. </field>
  6981. <field>
  6982. <name>ORECF</name>
  6983. <description>Overrun error clear flag</description>
  6984. <bitOffset>3</bitOffset>
  6985. <bitWidth>1</bitWidth>
  6986. </field>
  6987. <field>
  6988. <name>NCF</name>
  6989. <description>Noise detected clear flag</description>
  6990. <bitOffset>2</bitOffset>
  6991. <bitWidth>1</bitWidth>
  6992. </field>
  6993. <field>
  6994. <name>FECF</name>
  6995. <description>Framing error clear flag</description>
  6996. <bitOffset>1</bitOffset>
  6997. <bitWidth>1</bitWidth>
  6998. </field>
  6999. <field>
  7000. <name>PECF</name>
  7001. <description>Parity error clear flag</description>
  7002. <bitOffset>0</bitOffset>
  7003. <bitWidth>1</bitWidth>
  7004. </field>
  7005. </fields>
  7006. </register>
  7007. <register>
  7008. <name>RDR</name>
  7009. <displayName>RDR</displayName>
  7010. <description>Receive data register</description>
  7011. <addressOffset>0x24</addressOffset>
  7012. <size>0x20</size>
  7013. <access>read-only</access>
  7014. <resetValue>0x0000</resetValue>
  7015. <fields>
  7016. <field>
  7017. <name>RDR</name>
  7018. <description>Receive data value</description>
  7019. <bitOffset>0</bitOffset>
  7020. <bitWidth>9</bitWidth>
  7021. </field>
  7022. </fields>
  7023. </register>
  7024. <register>
  7025. <name>TDR</name>
  7026. <displayName>TDR</displayName>
  7027. <description>Transmit data register</description>
  7028. <addressOffset>0x28</addressOffset>
  7029. <size>0x20</size>
  7030. <access>read-write</access>
  7031. <resetValue>0x0000</resetValue>
  7032. <fields>
  7033. <field>
  7034. <name>TDR</name>
  7035. <description>Transmit data value</description>
  7036. <bitOffset>0</bitOffset>
  7037. <bitWidth>9</bitWidth>
  7038. </field>
  7039. </fields>
  7040. </register>
  7041. </registers>
  7042. </peripheral>
  7043. <peripheral derivedFrom="USART1">
  7044. <name>USART2</name>
  7045. <baseAddress>0x40004400</baseAddress>
  7046. <interrupt>
  7047. <name>USART2</name>
  7048. <description>USART2 global interrupt</description>
  7049. <value>28</value>
  7050. </interrupt>
  7051. </peripheral>
  7052. <peripheral derivedFrom="USART1">
  7053. <name>USART4</name>
  7054. <baseAddress>0x40004C00</baseAddress>
  7055. <interrupt>
  7056. <name>USART1</name>
  7057. <description>USART1 global interrupt</description>
  7058. <value>27</value>
  7059. </interrupt>
  7060. </peripheral>
  7061. <peripheral derivedFrom="USART1">
  7062. <name>USART5</name>
  7063. <baseAddress>0x40005000</baseAddress>
  7064. <interrupt>
  7065. <name>USART2</name>
  7066. <description>USART2 global interrupt</description>
  7067. <value>28</value>
  7068. </interrupt>
  7069. </peripheral>
  7070. <peripheral>
  7071. <name>IWDG</name>
  7072. <description>Independent watchdog</description>
  7073. <groupName>IWDG</groupName>
  7074. <baseAddress>0x40003000</baseAddress>
  7075. <addressBlock>
  7076. <offset>0x0</offset>
  7077. <size>0x400</size>
  7078. <usage>registers</usage>
  7079. </addressBlock>
  7080. <registers>
  7081. <register>
  7082. <name>KR</name>
  7083. <displayName>KR</displayName>
  7084. <description>Key register</description>
  7085. <addressOffset>0x0</addressOffset>
  7086. <size>0x20</size>
  7087. <access>write-only</access>
  7088. <resetValue>0x00000000</resetValue>
  7089. <fields>
  7090. <field>
  7091. <name>KEY</name>
  7092. <description>Key value (write only, read
  7093. 0x0000)</description>
  7094. <bitOffset>0</bitOffset>
  7095. <bitWidth>16</bitWidth>
  7096. </field>
  7097. </fields>
  7098. </register>
  7099. <register>
  7100. <name>PR</name>
  7101. <displayName>PR</displayName>
  7102. <description>Prescaler register</description>
  7103. <addressOffset>0x4</addressOffset>
  7104. <size>0x20</size>
  7105. <access>read-write</access>
  7106. <resetValue>0x00000000</resetValue>
  7107. <fields>
  7108. <field>
  7109. <name>PR</name>
  7110. <description>Prescaler divider</description>
  7111. <bitOffset>0</bitOffset>
  7112. <bitWidth>3</bitWidth>
  7113. </field>
  7114. </fields>
  7115. </register>
  7116. <register>
  7117. <name>RLR</name>
  7118. <displayName>RLR</displayName>
  7119. <description>Reload register</description>
  7120. <addressOffset>0x8</addressOffset>
  7121. <size>0x20</size>
  7122. <access>read-write</access>
  7123. <resetValue>0x00000FFF</resetValue>
  7124. <fields>
  7125. <field>
  7126. <name>RL</name>
  7127. <description>Watchdog counter reload
  7128. value</description>
  7129. <bitOffset>0</bitOffset>
  7130. <bitWidth>12</bitWidth>
  7131. </field>
  7132. </fields>
  7133. </register>
  7134. <register>
  7135. <name>SR</name>
  7136. <displayName>SR</displayName>
  7137. <description>Status register</description>
  7138. <addressOffset>0xC</addressOffset>
  7139. <size>0x20</size>
  7140. <access>read-only</access>
  7141. <resetValue>0x00000000</resetValue>
  7142. <fields>
  7143. <field>
  7144. <name>WVU</name>
  7145. <description>Watchdog counter window value
  7146. update</description>
  7147. <bitOffset>2</bitOffset>
  7148. <bitWidth>1</bitWidth>
  7149. </field>
  7150. <field>
  7151. <name>RVU</name>
  7152. <description>Watchdog counter reload value
  7153. update</description>
  7154. <bitOffset>1</bitOffset>
  7155. <bitWidth>1</bitWidth>
  7156. </field>
  7157. <field>
  7158. <name>PVU</name>
  7159. <description>Watchdog prescaler value
  7160. update</description>
  7161. <bitOffset>0</bitOffset>
  7162. <bitWidth>1</bitWidth>
  7163. </field>
  7164. </fields>
  7165. </register>
  7166. <register>
  7167. <name>WINR</name>
  7168. <displayName>WINR</displayName>
  7169. <description>Window register</description>
  7170. <addressOffset>0x10</addressOffset>
  7171. <size>0x20</size>
  7172. <access>read-write</access>
  7173. <resetValue>0x00000FFF</resetValue>
  7174. <fields>
  7175. <field>
  7176. <name>WIN</name>
  7177. <description>Watchdog counter window
  7178. value</description>
  7179. <bitOffset>0</bitOffset>
  7180. <bitWidth>12</bitWidth>
  7181. </field>
  7182. </fields>
  7183. </register>
  7184. </registers>
  7185. </peripheral>
  7186. <peripheral>
  7187. <name>WWDG</name>
  7188. <description>System window watchdog</description>
  7189. <groupName>WWDG</groupName>
  7190. <baseAddress>0x40002C00</baseAddress>
  7191. <addressBlock>
  7192. <offset>0x0</offset>
  7193. <size>0x400</size>
  7194. <usage>registers</usage>
  7195. </addressBlock>
  7196. <interrupt>
  7197. <name>WWDG</name>
  7198. <description>Window Watchdog interrupt</description>
  7199. <value>0</value>
  7200. </interrupt>
  7201. <registers>
  7202. <register>
  7203. <name>CR</name>
  7204. <displayName>CR</displayName>
  7205. <description>Control register</description>
  7206. <addressOffset>0x0</addressOffset>
  7207. <size>0x20</size>
  7208. <access>read-write</access>
  7209. <resetValue>0x0000007F</resetValue>
  7210. <fields>
  7211. <field>
  7212. <name>WDGA</name>
  7213. <description>Activation bit</description>
  7214. <bitOffset>7</bitOffset>
  7215. <bitWidth>1</bitWidth>
  7216. </field>
  7217. <field>
  7218. <name>T</name>
  7219. <description>7-bit counter (MSB to LSB)</description>
  7220. <bitOffset>0</bitOffset>
  7221. <bitWidth>7</bitWidth>
  7222. </field>
  7223. </fields>
  7224. </register>
  7225. <register>
  7226. <name>CFR</name>
  7227. <displayName>CFR</displayName>
  7228. <description>Configuration register</description>
  7229. <addressOffset>0x4</addressOffset>
  7230. <size>0x20</size>
  7231. <access>read-write</access>
  7232. <resetValue>0x0000007F</resetValue>
  7233. <fields>
  7234. <field>
  7235. <name>EWI</name>
  7236. <description>Early wakeup interrupt</description>
  7237. <bitOffset>9</bitOffset>
  7238. <bitWidth>1</bitWidth>
  7239. </field>
  7240. <field>
  7241. <name>WDGTB1</name>
  7242. <description>Timer base</description>
  7243. <bitOffset>8</bitOffset>
  7244. <bitWidth>1</bitWidth>
  7245. </field>
  7246. <field>
  7247. <name>WDGTB0</name>
  7248. <description>WDGTB0</description>
  7249. <bitOffset>7</bitOffset>
  7250. <bitWidth>1</bitWidth>
  7251. </field>
  7252. <field>
  7253. <name>W</name>
  7254. <description>7-bit window value</description>
  7255. <bitOffset>0</bitOffset>
  7256. <bitWidth>7</bitWidth>
  7257. </field>
  7258. </fields>
  7259. </register>
  7260. <register>
  7261. <name>SR</name>
  7262. <displayName>SR</displayName>
  7263. <description>Status register</description>
  7264. <addressOffset>0x8</addressOffset>
  7265. <size>0x20</size>
  7266. <access>read-writeOnce</access>
  7267. <resetValue>0x00000000</resetValue>
  7268. <fields>
  7269. <field>
  7270. <name>EWIF</name>
  7271. <description>Early wakeup interrupt
  7272. flag</description>
  7273. <bitOffset>0</bitOffset>
  7274. <bitWidth>1</bitWidth>
  7275. </field>
  7276. </fields>
  7277. </register>
  7278. </registers>
  7279. </peripheral>
  7280. <peripheral>
  7281. <name>Firewall</name>
  7282. <description>Firewall</description>
  7283. <groupName>Firewall</groupName>
  7284. <baseAddress>0x40011C00</baseAddress>
  7285. <addressBlock>
  7286. <offset>0x0</offset>
  7287. <size>0x400</size>
  7288. <usage>registers</usage>
  7289. </addressBlock>
  7290. <registers>
  7291. <register>
  7292. <name>FIREWALL_CSSA</name>
  7293. <displayName>FIREWALL_CSSA</displayName>
  7294. <description>Code segment start address</description>
  7295. <addressOffset>0x0</addressOffset>
  7296. <size>0x20</size>
  7297. <access>read-write</access>
  7298. <resetValue>0x00000000</resetValue>
  7299. <fields>
  7300. <field>
  7301. <name>ADD</name>
  7302. <description>code segment start address</description>
  7303. <bitOffset>8</bitOffset>
  7304. <bitWidth>16</bitWidth>
  7305. </field>
  7306. </fields>
  7307. </register>
  7308. <register>
  7309. <name>FIREWALL_CSL</name>
  7310. <displayName>FIREWALL_CSL</displayName>
  7311. <description>Code segment length</description>
  7312. <addressOffset>0x4</addressOffset>
  7313. <size>0x20</size>
  7314. <access>read-write</access>
  7315. <resetValue>0x00000000</resetValue>
  7316. <fields>
  7317. <field>
  7318. <name>LENG</name>
  7319. <description>code segment length</description>
  7320. <bitOffset>8</bitOffset>
  7321. <bitWidth>14</bitWidth>
  7322. </field>
  7323. </fields>
  7324. </register>
  7325. <register>
  7326. <name>FIREWALL_NVDSSA</name>
  7327. <displayName>FIREWALL_NVDSSA</displayName>
  7328. <description>Non-volatile data segment start
  7329. address</description>
  7330. <addressOffset>0x8</addressOffset>
  7331. <size>0x20</size>
  7332. <access>read-write</access>
  7333. <resetValue>0x00000000</resetValue>
  7334. <fields>
  7335. <field>
  7336. <name>ADD</name>
  7337. <description>Non-volatile data segment start
  7338. address</description>
  7339. <bitOffset>8</bitOffset>
  7340. <bitWidth>16</bitWidth>
  7341. </field>
  7342. </fields>
  7343. </register>
  7344. <register>
  7345. <name>FIREWALL_NVDSL</name>
  7346. <displayName>FIREWALL_NVDSL</displayName>
  7347. <description>Non-volatile data segment
  7348. length</description>
  7349. <addressOffset>0xC</addressOffset>
  7350. <size>0x20</size>
  7351. <access>read-write</access>
  7352. <resetValue>0x00000000</resetValue>
  7353. <fields>
  7354. <field>
  7355. <name>LENG</name>
  7356. <description>Non-volatile data segment
  7357. length</description>
  7358. <bitOffset>8</bitOffset>
  7359. <bitWidth>14</bitWidth>
  7360. </field>
  7361. </fields>
  7362. </register>
  7363. <register>
  7364. <name>FIREWALL_VDSSA</name>
  7365. <displayName>FIREWALL_VDSSA</displayName>
  7366. <description>Volatile data segment start
  7367. address</description>
  7368. <addressOffset>0x10</addressOffset>
  7369. <size>0x20</size>
  7370. <access>read-write</access>
  7371. <resetValue>0x00000000</resetValue>
  7372. <fields>
  7373. <field>
  7374. <name>ADD</name>
  7375. <description>Volatile data segment start
  7376. address</description>
  7377. <bitOffset>6</bitOffset>
  7378. <bitWidth>10</bitWidth>
  7379. </field>
  7380. </fields>
  7381. </register>
  7382. <register>
  7383. <name>FIREWALL_VDSL</name>
  7384. <displayName>FIREWALL_VDSL</displayName>
  7385. <description>Volatile data segment length</description>
  7386. <addressOffset>0x14</addressOffset>
  7387. <size>0x20</size>
  7388. <access>read-write</access>
  7389. <resetValue>0x00000000</resetValue>
  7390. <fields>
  7391. <field>
  7392. <name>LENG</name>
  7393. <description>Non-volatile data segment
  7394. length</description>
  7395. <bitOffset>6</bitOffset>
  7396. <bitWidth>10</bitWidth>
  7397. </field>
  7398. </fields>
  7399. </register>
  7400. <register>
  7401. <name>FIREWALL_CR</name>
  7402. <displayName>FIREWALL_CR</displayName>
  7403. <description>Configuration register</description>
  7404. <addressOffset>0x20</addressOffset>
  7405. <size>0x20</size>
  7406. <access>read-write</access>
  7407. <resetValue>0x00000000</resetValue>
  7408. <fields>
  7409. <field>
  7410. <name>VDE</name>
  7411. <description>Volatile data execution</description>
  7412. <bitOffset>2</bitOffset>
  7413. <bitWidth>1</bitWidth>
  7414. </field>
  7415. <field>
  7416. <name>VDS</name>
  7417. <description>Volatile data shared</description>
  7418. <bitOffset>1</bitOffset>
  7419. <bitWidth>1</bitWidth>
  7420. </field>
  7421. <field>
  7422. <name>FPA</name>
  7423. <description>Firewall pre alarm</description>
  7424. <bitOffset>0</bitOffset>
  7425. <bitWidth>1</bitWidth>
  7426. </field>
  7427. </fields>
  7428. </register>
  7429. </registers>
  7430. </peripheral>
  7431. <peripheral>
  7432. <name>RCC</name>
  7433. <description>Reset and clock control</description>
  7434. <groupName>RCC</groupName>
  7435. <baseAddress>0x40021000</baseAddress>
  7436. <addressBlock>
  7437. <offset>0x0</offset>
  7438. <size>0x400</size>
  7439. <usage>registers</usage>
  7440. </addressBlock>
  7441. <interrupt>
  7442. <name>RCC</name>
  7443. <description>RCC global interrupt</description>
  7444. <value>4</value>
  7445. </interrupt>
  7446. <registers>
  7447. <register>
  7448. <name>CR</name>
  7449. <displayName>CR</displayName>
  7450. <description>Clock control register</description>
  7451. <addressOffset>0x0</addressOffset>
  7452. <size>0x20</size>
  7453. <resetValue>0x00000300</resetValue>
  7454. <fields>
  7455. <field>
  7456. <name>PLLRDY</name>
  7457. <description>PLL clock ready flag</description>
  7458. <bitOffset>25</bitOffset>
  7459. <bitWidth>1</bitWidth>
  7460. <access>read-only</access>
  7461. </field>
  7462. <field>
  7463. <name>PLLON</name>
  7464. <description>PLL enable bit</description>
  7465. <bitOffset>24</bitOffset>
  7466. <bitWidth>1</bitWidth>
  7467. <access>read-write</access>
  7468. </field>
  7469. <field>
  7470. <name>RTCPRE</name>
  7471. <description>TC/LCD prescaler</description>
  7472. <bitOffset>20</bitOffset>
  7473. <bitWidth>2</bitWidth>
  7474. <access>read-write</access>
  7475. </field>
  7476. <field>
  7477. <name>CSSLSEON</name>
  7478. <description>Clock security system on HSE enable
  7479. bit</description>
  7480. <bitOffset>19</bitOffset>
  7481. <bitWidth>1</bitWidth>
  7482. <access>read-write</access>
  7483. </field>
  7484. <field>
  7485. <name>HSEBYP</name>
  7486. <description>HSE clock bypass bit</description>
  7487. <bitOffset>18</bitOffset>
  7488. <bitWidth>1</bitWidth>
  7489. <access>read-write</access>
  7490. </field>
  7491. <field>
  7492. <name>HSERDY</name>
  7493. <description>HSE clock ready flag</description>
  7494. <bitOffset>17</bitOffset>
  7495. <bitWidth>1</bitWidth>
  7496. <access>read-only</access>
  7497. </field>
  7498. <field>
  7499. <name>HSEON</name>
  7500. <description>HSE clock enable bit</description>
  7501. <bitOffset>16</bitOffset>
  7502. <bitWidth>1</bitWidth>
  7503. <access>read-write</access>
  7504. </field>
  7505. <field>
  7506. <name>MSIRDY</name>
  7507. <description>MSI clock ready flag</description>
  7508. <bitOffset>9</bitOffset>
  7509. <bitWidth>1</bitWidth>
  7510. <access>read-only</access>
  7511. </field>
  7512. <field>
  7513. <name>MSION</name>
  7514. <description>MSI clock enable bit</description>
  7515. <bitOffset>8</bitOffset>
  7516. <bitWidth>1</bitWidth>
  7517. <access>read-write</access>
  7518. </field>
  7519. <field>
  7520. <name>HSI16DIVF</name>
  7521. <description>HSI16DIVF</description>
  7522. <bitOffset>4</bitOffset>
  7523. <bitWidth>1</bitWidth>
  7524. <access>read-only</access>
  7525. </field>
  7526. <field>
  7527. <name>HSI16DIVEN</name>
  7528. <description>HSI16DIVEN</description>
  7529. <bitOffset>3</bitOffset>
  7530. <bitWidth>1</bitWidth>
  7531. <access>read-write</access>
  7532. </field>
  7533. <field>
  7534. <name>HSI16RDYF</name>
  7535. <description>Internal high-speed clock ready
  7536. flag</description>
  7537. <bitOffset>2</bitOffset>
  7538. <bitWidth>1</bitWidth>
  7539. <access>read-write</access>
  7540. </field>
  7541. <field>
  7542. <name>HSI16KERON</name>
  7543. <description>High-speed internal clock enable bit for
  7544. some IP kernels</description>
  7545. <bitOffset>1</bitOffset>
  7546. <bitWidth>1</bitWidth>
  7547. <access>read-only</access>
  7548. </field>
  7549. <field>
  7550. <name>HSI16ON</name>
  7551. <description>16 MHz high-speed internal clock
  7552. enable</description>
  7553. <bitOffset>0</bitOffset>
  7554. <bitWidth>1</bitWidth>
  7555. <access>read-write</access>
  7556. </field>
  7557. <field>
  7558. <name>HSI16OUTEN</name>
  7559. <description>16 MHz high-speed internal clock output
  7560. enable</description>
  7561. <bitOffset>5</bitOffset>
  7562. <bitWidth>1</bitWidth>
  7563. <access>read-write</access>
  7564. </field>
  7565. </fields>
  7566. </register>
  7567. <register>
  7568. <name>ICSCR</name>
  7569. <displayName>ICSCR</displayName>
  7570. <description>Internal clock sources calibration
  7571. register</description>
  7572. <addressOffset>0x4</addressOffset>
  7573. <size>0x20</size>
  7574. <resetValue>0x0000B000</resetValue>
  7575. <fields>
  7576. <field>
  7577. <name>MSITRIM</name>
  7578. <description>MSI clock trimming</description>
  7579. <bitOffset>24</bitOffset>
  7580. <bitWidth>8</bitWidth>
  7581. <access>read-write</access>
  7582. </field>
  7583. <field>
  7584. <name>MSICAL</name>
  7585. <description>MSI clock calibration</description>
  7586. <bitOffset>16</bitOffset>
  7587. <bitWidth>8</bitWidth>
  7588. <access>read-only</access>
  7589. </field>
  7590. <field>
  7591. <name>MSIRANGE</name>
  7592. <description>MSI clock ranges</description>
  7593. <bitOffset>13</bitOffset>
  7594. <bitWidth>3</bitWidth>
  7595. <access>read-write</access>
  7596. </field>
  7597. <field>
  7598. <name>HSI16TRIM</name>
  7599. <description>High speed internal clock
  7600. trimming</description>
  7601. <bitOffset>8</bitOffset>
  7602. <bitWidth>5</bitWidth>
  7603. <access>read-write</access>
  7604. </field>
  7605. <field>
  7606. <name>HSI16CAL</name>
  7607. <description>nternal high speed clock
  7608. calibration</description>
  7609. <bitOffset>0</bitOffset>
  7610. <bitWidth>8</bitWidth>
  7611. <access>read-only</access>
  7612. </field>
  7613. </fields>
  7614. </register>
  7615. <register>
  7616. <name>CFGR</name>
  7617. <displayName>CFGR</displayName>
  7618. <description>Clock configuration register</description>
  7619. <addressOffset>0xC</addressOffset>
  7620. <size>0x20</size>
  7621. <resetValue>0x00000000</resetValue>
  7622. <fields>
  7623. <field>
  7624. <name>MCOPRE</name>
  7625. <description>Microcontroller clock output
  7626. prescaler</description>
  7627. <bitOffset>28</bitOffset>
  7628. <bitWidth>3</bitWidth>
  7629. <access>read-write</access>
  7630. </field>
  7631. <field>
  7632. <name>MCOSEL</name>
  7633. <description>Microcontroller clock output
  7634. selection</description>
  7635. <bitOffset>24</bitOffset>
  7636. <bitWidth>3</bitWidth>
  7637. <access>read-write</access>
  7638. </field>
  7639. <field>
  7640. <name>PLLDIV</name>
  7641. <description>PLL output division</description>
  7642. <bitOffset>22</bitOffset>
  7643. <bitWidth>2</bitWidth>
  7644. <access>read-write</access>
  7645. </field>
  7646. <field>
  7647. <name>PLLMUL</name>
  7648. <description>PLL multiplication factor</description>
  7649. <bitOffset>18</bitOffset>
  7650. <bitWidth>4</bitWidth>
  7651. <access>read-write</access>
  7652. </field>
  7653. <field>
  7654. <name>PLLSRC</name>
  7655. <description>PLL entry clock source</description>
  7656. <bitOffset>16</bitOffset>
  7657. <bitWidth>1</bitWidth>
  7658. <access>read-write</access>
  7659. </field>
  7660. <field>
  7661. <name>STOPWUCK</name>
  7662. <description>Wake-up from stop clock
  7663. selection</description>
  7664. <bitOffset>15</bitOffset>
  7665. <bitWidth>1</bitWidth>
  7666. <access>read-write</access>
  7667. </field>
  7668. <field>
  7669. <name>PPRE2</name>
  7670. <description>APB high-speed prescaler
  7671. (APB2)</description>
  7672. <bitOffset>11</bitOffset>
  7673. <bitWidth>3</bitWidth>
  7674. <access>read-write</access>
  7675. </field>
  7676. <field>
  7677. <name>PPRE1</name>
  7678. <description>APB low-speed prescaler
  7679. (APB1)</description>
  7680. <bitOffset>8</bitOffset>
  7681. <bitWidth>3</bitWidth>
  7682. <access>read-write</access>
  7683. </field>
  7684. <field>
  7685. <name>HPRE</name>
  7686. <description>AHB prescaler</description>
  7687. <bitOffset>4</bitOffset>
  7688. <bitWidth>4</bitWidth>
  7689. <access>read-write</access>
  7690. </field>
  7691. <field>
  7692. <name>SWS</name>
  7693. <description>System clock switch status</description>
  7694. <bitOffset>2</bitOffset>
  7695. <bitWidth>2</bitWidth>
  7696. <access>read-only</access>
  7697. </field>
  7698. <field>
  7699. <name>SW</name>
  7700. <description>System clock switch</description>
  7701. <bitOffset>0</bitOffset>
  7702. <bitWidth>2</bitWidth>
  7703. <access>read-write</access>
  7704. </field>
  7705. </fields>
  7706. </register>
  7707. <register>
  7708. <name>CIER</name>
  7709. <displayName>CIER</displayName>
  7710. <description>Clock interrupt enable
  7711. register</description>
  7712. <addressOffset>0x10</addressOffset>
  7713. <size>0x20</size>
  7714. <access>read-only</access>
  7715. <resetValue>0x00000000</resetValue>
  7716. <fields>
  7717. <field>
  7718. <name>CSSLSE</name>
  7719. <description>LSE CSS interrupt flag</description>
  7720. <bitOffset>7</bitOffset>
  7721. <bitWidth>1</bitWidth>
  7722. </field>
  7723. <field>
  7724. <name>MSIRDYIE</name>
  7725. <description>MSI ready interrupt flag</description>
  7726. <bitOffset>5</bitOffset>
  7727. <bitWidth>1</bitWidth>
  7728. </field>
  7729. <field>
  7730. <name>PLLRDYIE</name>
  7731. <description>PLL ready interrupt flag</description>
  7732. <bitOffset>4</bitOffset>
  7733. <bitWidth>1</bitWidth>
  7734. </field>
  7735. <field>
  7736. <name>HSERDYIE</name>
  7737. <description>HSE ready interrupt flag</description>
  7738. <bitOffset>3</bitOffset>
  7739. <bitWidth>1</bitWidth>
  7740. </field>
  7741. <field>
  7742. <name>HSI16RDYIE</name>
  7743. <description>HSI16 ready interrupt flag</description>
  7744. <bitOffset>2</bitOffset>
  7745. <bitWidth>1</bitWidth>
  7746. </field>
  7747. <field>
  7748. <name>LSERDYIE</name>
  7749. <description>LSE ready interrupt flag</description>
  7750. <bitOffset>1</bitOffset>
  7751. <bitWidth>1</bitWidth>
  7752. </field>
  7753. <field>
  7754. <name>LSIRDYIE</name>
  7755. <description>LSI ready interrupt flag</description>
  7756. <bitOffset>0</bitOffset>
  7757. <bitWidth>1</bitWidth>
  7758. </field>
  7759. </fields>
  7760. </register>
  7761. <register>
  7762. <name>CIFR</name>
  7763. <displayName>CIFR</displayName>
  7764. <description>Clock interrupt flag register</description>
  7765. <addressOffset>0x14</addressOffset>
  7766. <size>0x20</size>
  7767. <access>read-only</access>
  7768. <resetValue>0x00000000</resetValue>
  7769. <fields>
  7770. <field>
  7771. <name>CSSHSEF</name>
  7772. <description>Clock Security System Interrupt
  7773. flag</description>
  7774. <bitOffset>8</bitOffset>
  7775. <bitWidth>1</bitWidth>
  7776. </field>
  7777. <field>
  7778. <name>CSSLSEF</name>
  7779. <description>LSE Clock Security System Interrupt
  7780. flag</description>
  7781. <bitOffset>7</bitOffset>
  7782. <bitWidth>1</bitWidth>
  7783. </field>
  7784. <field>
  7785. <name>MSIRDYF</name>
  7786. <description>MSI ready interrupt flag</description>
  7787. <bitOffset>5</bitOffset>
  7788. <bitWidth>1</bitWidth>
  7789. </field>
  7790. <field>
  7791. <name>PLLRDYF</name>
  7792. <description>PLL ready interrupt flag</description>
  7793. <bitOffset>4</bitOffset>
  7794. <bitWidth>1</bitWidth>
  7795. </field>
  7796. <field>
  7797. <name>HSERDYF</name>
  7798. <description>HSE ready interrupt flag</description>
  7799. <bitOffset>3</bitOffset>
  7800. <bitWidth>1</bitWidth>
  7801. </field>
  7802. <field>
  7803. <name>HSI16RDYF</name>
  7804. <description>HSI16 ready interrupt flag</description>
  7805. <bitOffset>2</bitOffset>
  7806. <bitWidth>1</bitWidth>
  7807. </field>
  7808. <field>
  7809. <name>LSERDYF</name>
  7810. <description>LSE ready interrupt flag</description>
  7811. <bitOffset>1</bitOffset>
  7812. <bitWidth>1</bitWidth>
  7813. </field>
  7814. <field>
  7815. <name>LSIRDYF</name>
  7816. <description>LSI ready interrupt flag</description>
  7817. <bitOffset>0</bitOffset>
  7818. <bitWidth>1</bitWidth>
  7819. </field>
  7820. </fields>
  7821. </register>
  7822. <register>
  7823. <name>CICR</name>
  7824. <displayName>CICR</displayName>
  7825. <description>Clock interrupt clear register</description>
  7826. <addressOffset>0x18</addressOffset>
  7827. <size>0x20</size>
  7828. <access>read-only</access>
  7829. <resetValue>0x00000000</resetValue>
  7830. <fields>
  7831. <field>
  7832. <name>CSSHSEC</name>
  7833. <description>Clock Security System Interrupt
  7834. clear</description>
  7835. <bitOffset>8</bitOffset>
  7836. <bitWidth>1</bitWidth>
  7837. </field>
  7838. <field>
  7839. <name>CSSLSEC</name>
  7840. <description>LSE Clock Security System Interrupt
  7841. clear</description>
  7842. <bitOffset>7</bitOffset>
  7843. <bitWidth>1</bitWidth>
  7844. </field>
  7845. <field>
  7846. <name>MSIRDYC</name>
  7847. <description>MSI ready Interrupt clear</description>
  7848. <bitOffset>5</bitOffset>
  7849. <bitWidth>1</bitWidth>
  7850. </field>
  7851. <field>
  7852. <name>PLLRDYC</name>
  7853. <description>PLL ready Interrupt clear</description>
  7854. <bitOffset>4</bitOffset>
  7855. <bitWidth>1</bitWidth>
  7856. </field>
  7857. <field>
  7858. <name>HSERDYC</name>
  7859. <description>HSE ready Interrupt clear</description>
  7860. <bitOffset>3</bitOffset>
  7861. <bitWidth>1</bitWidth>
  7862. </field>
  7863. <field>
  7864. <name>HSI16RDYC</name>
  7865. <description>HSI16 ready Interrupt
  7866. clear</description>
  7867. <bitOffset>2</bitOffset>
  7868. <bitWidth>1</bitWidth>
  7869. </field>
  7870. <field>
  7871. <name>LSERDYC</name>
  7872. <description>LSE ready Interrupt clear</description>
  7873. <bitOffset>1</bitOffset>
  7874. <bitWidth>1</bitWidth>
  7875. </field>
  7876. <field>
  7877. <name>LSIRDYC</name>
  7878. <description>LSI ready Interrupt clear</description>
  7879. <bitOffset>0</bitOffset>
  7880. <bitWidth>1</bitWidth>
  7881. </field>
  7882. </fields>
  7883. </register>
  7884. <register>
  7885. <name>IOPRSTR</name>
  7886. <displayName>IOPRSTR</displayName>
  7887. <description>GPIO reset register</description>
  7888. <addressOffset>0x1C</addressOffset>
  7889. <size>0x20</size>
  7890. <access>read-write</access>
  7891. <resetValue>0x00000000</resetValue>
  7892. <fields>
  7893. <field>
  7894. <name>IOPHRST</name>
  7895. <description>I/O port H reset</description>
  7896. <bitOffset>7</bitOffset>
  7897. <bitWidth>1</bitWidth>
  7898. </field>
  7899. <field>
  7900. <name>IOPDRST</name>
  7901. <description>I/O port D reset</description>
  7902. <bitOffset>3</bitOffset>
  7903. <bitWidth>1</bitWidth>
  7904. </field>
  7905. <field>
  7906. <name>IOPCRST</name>
  7907. <description>I/O port A reset</description>
  7908. <bitOffset>2</bitOffset>
  7909. <bitWidth>1</bitWidth>
  7910. </field>
  7911. <field>
  7912. <name>IOPBRST</name>
  7913. <description>I/O port B reset</description>
  7914. <bitOffset>1</bitOffset>
  7915. <bitWidth>1</bitWidth>
  7916. </field>
  7917. <field>
  7918. <name>IOPARST</name>
  7919. <description>I/O port A reset</description>
  7920. <bitOffset>0</bitOffset>
  7921. <bitWidth>1</bitWidth>
  7922. </field>
  7923. <field>
  7924. <name>IOPERST</name>
  7925. <description>I/O port E reset</description>
  7926. <bitOffset>4</bitOffset>
  7927. <bitWidth>1</bitWidth>
  7928. </field>
  7929. </fields>
  7930. </register>
  7931. <register>
  7932. <name>AHBRSTR</name>
  7933. <displayName>AHBRSTR</displayName>
  7934. <description>AHB peripheral reset register</description>
  7935. <addressOffset>0x20</addressOffset>
  7936. <size>0x20</size>
  7937. <access>read-write</access>
  7938. <resetValue>0x00000000</resetValue>
  7939. <fields>
  7940. <field>
  7941. <name>CRYPRST</name>
  7942. <description>Crypto module reset</description>
  7943. <bitOffset>24</bitOffset>
  7944. <bitWidth>1</bitWidth>
  7945. </field>
  7946. <field>
  7947. <name>CRCRST</name>
  7948. <description>Test integration module
  7949. reset</description>
  7950. <bitOffset>12</bitOffset>
  7951. <bitWidth>1</bitWidth>
  7952. </field>
  7953. <field>
  7954. <name>MIFRST</name>
  7955. <description>Memory interface reset</description>
  7956. <bitOffset>8</bitOffset>
  7957. <bitWidth>1</bitWidth>
  7958. </field>
  7959. <field>
  7960. <name>DMARST</name>
  7961. <description>DMA reset</description>
  7962. <bitOffset>0</bitOffset>
  7963. <bitWidth>1</bitWidth>
  7964. </field>
  7965. </fields>
  7966. </register>
  7967. <register>
  7968. <name>APB2RSTR</name>
  7969. <displayName>APB2RSTR</displayName>
  7970. <description>APB2 peripheral reset register</description>
  7971. <addressOffset>0x24</addressOffset>
  7972. <size>0x20</size>
  7973. <access>read-write</access>
  7974. <resetValue>0x000000000</resetValue>
  7975. <fields>
  7976. <field>
  7977. <name>DBGRST</name>
  7978. <description>DBG reset</description>
  7979. <bitOffset>22</bitOffset>
  7980. <bitWidth>1</bitWidth>
  7981. </field>
  7982. <field>
  7983. <name>USART1RST</name>
  7984. <description>USART1 reset</description>
  7985. <bitOffset>14</bitOffset>
  7986. <bitWidth>1</bitWidth>
  7987. </field>
  7988. <field>
  7989. <name>SPI1RST</name>
  7990. <description>SPI 1 reset</description>
  7991. <bitOffset>12</bitOffset>
  7992. <bitWidth>1</bitWidth>
  7993. </field>
  7994. <field>
  7995. <name>ADCRST</name>
  7996. <description>ADC interface reset</description>
  7997. <bitOffset>9</bitOffset>
  7998. <bitWidth>1</bitWidth>
  7999. </field>
  8000. <field>
  8001. <name>TIM22RST</name>
  8002. <description>TIM22 timer reset</description>
  8003. <bitOffset>5</bitOffset>
  8004. <bitWidth>1</bitWidth>
  8005. </field>
  8006. <field>
  8007. <name>TIM21RST</name>
  8008. <description>TIM21 timer reset</description>
  8009. <bitOffset>2</bitOffset>
  8010. <bitWidth>1</bitWidth>
  8011. </field>
  8012. <field>
  8013. <name>SYSCFGRST</name>
  8014. <description>System configuration controller
  8015. reset</description>
  8016. <bitOffset>0</bitOffset>
  8017. <bitWidth>1</bitWidth>
  8018. </field>
  8019. </fields>
  8020. </register>
  8021. <register>
  8022. <name>APB1RSTR</name>
  8023. <displayName>APB1RSTR</displayName>
  8024. <description>APB1 peripheral reset register</description>
  8025. <addressOffset>0x28</addressOffset>
  8026. <size>0x20</size>
  8027. <access>read-write</access>
  8028. <resetValue>0x00000000</resetValue>
  8029. <fields>
  8030. <field>
  8031. <name>LPTIM1RST</name>
  8032. <description>Low power timer reset</description>
  8033. <bitOffset>31</bitOffset>
  8034. <bitWidth>1</bitWidth>
  8035. </field>
  8036. <field>
  8037. <name>PWRRST</name>
  8038. <description>Power interface reset</description>
  8039. <bitOffset>28</bitOffset>
  8040. <bitWidth>1</bitWidth>
  8041. </field>
  8042. <field>
  8043. <name>I2C2RST</name>
  8044. <description>I2C2 reset</description>
  8045. <bitOffset>22</bitOffset>
  8046. <bitWidth>1</bitWidth>
  8047. </field>
  8048. <field>
  8049. <name>I2C1RST</name>
  8050. <description>I2C1 reset</description>
  8051. <bitOffset>21</bitOffset>
  8052. <bitWidth>1</bitWidth>
  8053. </field>
  8054. <field>
  8055. <name>LPUART1RST</name>
  8056. <description>LPUART1 reset</description>
  8057. <bitOffset>18</bitOffset>
  8058. <bitWidth>1</bitWidth>
  8059. </field>
  8060. <field>
  8061. <name>USART2RST</name>
  8062. <description>USART2 reset</description>
  8063. <bitOffset>17</bitOffset>
  8064. <bitWidth>1</bitWidth>
  8065. </field>
  8066. <field>
  8067. <name>SPI2RST</name>
  8068. <description>SPI2 reset</description>
  8069. <bitOffset>14</bitOffset>
  8070. <bitWidth>1</bitWidth>
  8071. </field>
  8072. <field>
  8073. <name>WWDGRST</name>
  8074. <description>Window watchdog reset</description>
  8075. <bitOffset>11</bitOffset>
  8076. <bitWidth>1</bitWidth>
  8077. </field>
  8078. <field>
  8079. <name>TIM6RST</name>
  8080. <description>Timer 6 reset</description>
  8081. <bitOffset>4</bitOffset>
  8082. <bitWidth>1</bitWidth>
  8083. </field>
  8084. <field>
  8085. <name>TIM2RST</name>
  8086. <description>Timer 2 reset</description>
  8087. <bitOffset>0</bitOffset>
  8088. <bitWidth>1</bitWidth>
  8089. </field>
  8090. <field>
  8091. <name>TIM3RST</name>
  8092. <description>Timer 3 reset</description>
  8093. <bitOffset>1</bitOffset>
  8094. <bitWidth>1</bitWidth>
  8095. </field>
  8096. <field>
  8097. <name>TIM7RST</name>
  8098. <description>Timer 7 reset</description>
  8099. <bitOffset>5</bitOffset>
  8100. <bitWidth>1</bitWidth>
  8101. </field>
  8102. <field>
  8103. <name>USART4RST</name>
  8104. <description>USART4 reset</description>
  8105. <bitOffset>19</bitOffset>
  8106. <bitWidth>1</bitWidth>
  8107. </field>
  8108. <field>
  8109. <name>USART5RST</name>
  8110. <description>USART5 reset</description>
  8111. <bitOffset>20</bitOffset>
  8112. <bitWidth>1</bitWidth>
  8113. </field>
  8114. <field>
  8115. <name>CRCRST</name>
  8116. <description>CRC reset</description>
  8117. <bitOffset>27</bitOffset>
  8118. <bitWidth>1</bitWidth>
  8119. </field>
  8120. <field>
  8121. <name>I2C3</name>
  8122. <description>I2C3 reset</description>
  8123. <bitOffset>30</bitOffset>
  8124. <bitWidth>1</bitWidth>
  8125. </field>
  8126. </fields>
  8127. </register>
  8128. <register>
  8129. <name>IOPENR</name>
  8130. <displayName>IOPENR</displayName>
  8131. <description>GPIO clock enable register</description>
  8132. <addressOffset>0x2C</addressOffset>
  8133. <size>0x20</size>
  8134. <access>read-write</access>
  8135. <resetValue>0x00000000</resetValue>
  8136. <fields>
  8137. <field>
  8138. <name>IOPHEN</name>
  8139. <description>I/O port H clock enable
  8140. bit</description>
  8141. <bitOffset>7</bitOffset>
  8142. <bitWidth>1</bitWidth>
  8143. </field>
  8144. <field>
  8145. <name>IOPDEN</name>
  8146. <description>I/O port D clock enable
  8147. bit</description>
  8148. <bitOffset>3</bitOffset>
  8149. <bitWidth>1</bitWidth>
  8150. </field>
  8151. <field>
  8152. <name>IOPCEN</name>
  8153. <description>IO port A clock enable bit</description>
  8154. <bitOffset>2</bitOffset>
  8155. <bitWidth>1</bitWidth>
  8156. </field>
  8157. <field>
  8158. <name>IOPBEN</name>
  8159. <description>IO port B clock enable bit</description>
  8160. <bitOffset>1</bitOffset>
  8161. <bitWidth>1</bitWidth>
  8162. </field>
  8163. <field>
  8164. <name>IOPAEN</name>
  8165. <description>IO port A clock enable bit</description>
  8166. <bitOffset>0</bitOffset>
  8167. <bitWidth>1</bitWidth>
  8168. </field>
  8169. <field>
  8170. <name>IOPEEN</name>
  8171. <description>IO port E clock enable bit</description>
  8172. <bitOffset>4</bitOffset>
  8173. <bitWidth>1</bitWidth>
  8174. </field>
  8175. </fields>
  8176. </register>
  8177. <register>
  8178. <name>AHBENR</name>
  8179. <displayName>AHBENR</displayName>
  8180. <description>AHB peripheral clock enable
  8181. register</description>
  8182. <addressOffset>0x30</addressOffset>
  8183. <size>0x20</size>
  8184. <access>read-write</access>
  8185. <resetValue>0x00000100</resetValue>
  8186. <fields>
  8187. <field>
  8188. <name>CRYPEN</name>
  8189. <description>Crypto clock enable bit</description>
  8190. <bitOffset>24</bitOffset>
  8191. <bitWidth>1</bitWidth>
  8192. </field>
  8193. <field>
  8194. <name>CRCEN</name>
  8195. <description>CRC clock enable bit</description>
  8196. <bitOffset>12</bitOffset>
  8197. <bitWidth>1</bitWidth>
  8198. </field>
  8199. <field>
  8200. <name>MIFEN</name>
  8201. <description>NVM interface clock enable
  8202. bit</description>
  8203. <bitOffset>8</bitOffset>
  8204. <bitWidth>1</bitWidth>
  8205. </field>
  8206. <field>
  8207. <name>DMAEN</name>
  8208. <description>DMA clock enable bit</description>
  8209. <bitOffset>0</bitOffset>
  8210. <bitWidth>1</bitWidth>
  8211. </field>
  8212. </fields>
  8213. </register>
  8214. <register>
  8215. <name>APB2ENR</name>
  8216. <displayName>APB2ENR</displayName>
  8217. <description>APB2 peripheral clock enable
  8218. register</description>
  8219. <addressOffset>0x34</addressOffset>
  8220. <size>0x20</size>
  8221. <access>read-write</access>
  8222. <resetValue>0x00000000</resetValue>
  8223. <fields>
  8224. <field>
  8225. <name>DBGEN</name>
  8226. <description>DBG clock enable bit</description>
  8227. <bitOffset>22</bitOffset>
  8228. <bitWidth>1</bitWidth>
  8229. </field>
  8230. <field>
  8231. <name>USART1EN</name>
  8232. <description>USART1 clock enable bit</description>
  8233. <bitOffset>14</bitOffset>
  8234. <bitWidth>1</bitWidth>
  8235. </field>
  8236. <field>
  8237. <name>SPI1EN</name>
  8238. <description>SPI1 clock enable bit</description>
  8239. <bitOffset>12</bitOffset>
  8240. <bitWidth>1</bitWidth>
  8241. </field>
  8242. <field>
  8243. <name>ADCEN</name>
  8244. <description>ADC clock enable bit</description>
  8245. <bitOffset>9</bitOffset>
  8246. <bitWidth>1</bitWidth>
  8247. </field>
  8248. <field>
  8249. <name>FWEN</name>
  8250. <description>Firewall clock enable bit</description>
  8251. <bitOffset>7</bitOffset>
  8252. <bitWidth>1</bitWidth>
  8253. </field>
  8254. <field>
  8255. <name>TIM22EN</name>
  8256. <description>TIM22 timer clock enable
  8257. bit</description>
  8258. <bitOffset>5</bitOffset>
  8259. <bitWidth>1</bitWidth>
  8260. </field>
  8261. <field>
  8262. <name>TIM21EN</name>
  8263. <description>TIM21 timer clock enable
  8264. bit</description>
  8265. <bitOffset>2</bitOffset>
  8266. <bitWidth>1</bitWidth>
  8267. </field>
  8268. <field>
  8269. <name>SYSCFGEN</name>
  8270. <description>System configuration controller clock
  8271. enable bit</description>
  8272. <bitOffset>0</bitOffset>
  8273. <bitWidth>1</bitWidth>
  8274. </field>
  8275. </fields>
  8276. </register>
  8277. <register>
  8278. <name>APB1ENR</name>
  8279. <displayName>APB1ENR</displayName>
  8280. <description>APB1 peripheral clock enable
  8281. register</description>
  8282. <addressOffset>0x38</addressOffset>
  8283. <size>0x20</size>
  8284. <access>read-write</access>
  8285. <resetValue>0x00000000</resetValue>
  8286. <fields>
  8287. <field>
  8288. <name>LPTIM1EN</name>
  8289. <description>Low power timer clock enable
  8290. bit</description>
  8291. <bitOffset>31</bitOffset>
  8292. <bitWidth>1</bitWidth>
  8293. </field>
  8294. <field>
  8295. <name>PWREN</name>
  8296. <description>Power interface clock enable
  8297. bit</description>
  8298. <bitOffset>28</bitOffset>
  8299. <bitWidth>1</bitWidth>
  8300. </field>
  8301. <field>
  8302. <name>I2C2EN</name>
  8303. <description>I2C2 clock enable bit</description>
  8304. <bitOffset>22</bitOffset>
  8305. <bitWidth>1</bitWidth>
  8306. </field>
  8307. <field>
  8308. <name>I2C1EN</name>
  8309. <description>I2C1 clock enable bit</description>
  8310. <bitOffset>21</bitOffset>
  8311. <bitWidth>1</bitWidth>
  8312. </field>
  8313. <field>
  8314. <name>LPUART1EN</name>
  8315. <description>LPUART1 clock enable bit</description>
  8316. <bitOffset>18</bitOffset>
  8317. <bitWidth>1</bitWidth>
  8318. </field>
  8319. <field>
  8320. <name>USART2EN</name>
  8321. <description>UART2 clock enable bit</description>
  8322. <bitOffset>17</bitOffset>
  8323. <bitWidth>1</bitWidth>
  8324. </field>
  8325. <field>
  8326. <name>SPI2EN</name>
  8327. <description>SPI2 clock enable bit</description>
  8328. <bitOffset>14</bitOffset>
  8329. <bitWidth>1</bitWidth>
  8330. </field>
  8331. <field>
  8332. <name>WWDGEN</name>
  8333. <description>Window watchdog clock enable
  8334. bit</description>
  8335. <bitOffset>11</bitOffset>
  8336. <bitWidth>1</bitWidth>
  8337. </field>
  8338. <field>
  8339. <name>TIM6EN</name>
  8340. <description>Timer 6 clock enable bit</description>
  8341. <bitOffset>4</bitOffset>
  8342. <bitWidth>1</bitWidth>
  8343. </field>
  8344. <field>
  8345. <name>TIM2EN</name>
  8346. <description>Timer2 clock enable bit</description>
  8347. <bitOffset>0</bitOffset>
  8348. <bitWidth>1</bitWidth>
  8349. </field>
  8350. <field>
  8351. <name>TIM3EN</name>
  8352. <description>Timer 3 clock enbale bit</description>
  8353. <bitOffset>2</bitOffset>
  8354. <bitWidth>1</bitWidth>
  8355. </field>
  8356. <field>
  8357. <name>TIM7EN</name>
  8358. <description>Timer 7 clock enable bit</description>
  8359. <bitOffset>5</bitOffset>
  8360. <bitWidth>1</bitWidth>
  8361. </field>
  8362. <field>
  8363. <name>USART4EN</name>
  8364. <description>USART4 clock enable bit</description>
  8365. <bitOffset>19</bitOffset>
  8366. <bitWidth>1</bitWidth>
  8367. </field>
  8368. <field>
  8369. <name>USART5EN</name>
  8370. <description>USART5 clock enable bit</description>
  8371. <bitOffset>20</bitOffset>
  8372. <bitWidth>1</bitWidth>
  8373. </field>
  8374. <field>
  8375. <name>I2C3EN</name>
  8376. <description>I2C3 clock enable bit</description>
  8377. <bitOffset>30</bitOffset>
  8378. <bitWidth>1</bitWidth>
  8379. </field>
  8380. </fields>
  8381. </register>
  8382. <register>
  8383. <name>IOPSMEN</name>
  8384. <displayName>IOPSMEN</displayName>
  8385. <description>GPIO clock enable in sleep mode
  8386. register</description>
  8387. <addressOffset>0x3C</addressOffset>
  8388. <size>0x20</size>
  8389. <access>read-write</access>
  8390. <resetValue>0x0000008F</resetValue>
  8391. <fields>
  8392. <field>
  8393. <name>IOPHSMEN</name>
  8394. <description>Port H clock enable during Sleep mode
  8395. bit</description>
  8396. <bitOffset>7</bitOffset>
  8397. <bitWidth>1</bitWidth>
  8398. </field>
  8399. <field>
  8400. <name>IOPDSMEN</name>
  8401. <description>Port D clock enable during Sleep mode
  8402. bit</description>
  8403. <bitOffset>3</bitOffset>
  8404. <bitWidth>1</bitWidth>
  8405. </field>
  8406. <field>
  8407. <name>IOPCSMEN</name>
  8408. <description>Port C clock enable during Sleep mode
  8409. bit</description>
  8410. <bitOffset>2</bitOffset>
  8411. <bitWidth>1</bitWidth>
  8412. </field>
  8413. <field>
  8414. <name>IOPBSMEN</name>
  8415. <description>Port B clock enable during Sleep mode
  8416. bit</description>
  8417. <bitOffset>1</bitOffset>
  8418. <bitWidth>1</bitWidth>
  8419. </field>
  8420. <field>
  8421. <name>IOPASMEN</name>
  8422. <description>Port A clock enable during Sleep mode
  8423. bit</description>
  8424. <bitOffset>0</bitOffset>
  8425. <bitWidth>1</bitWidth>
  8426. </field>
  8427. <field>
  8428. <name>IOPESMEN</name>
  8429. <description>Port E clock enable during Sleep mode
  8430. bit</description>
  8431. <bitOffset>4</bitOffset>
  8432. <bitWidth>1</bitWidth>
  8433. </field>
  8434. </fields>
  8435. </register>
  8436. <register>
  8437. <name>AHBSMENR</name>
  8438. <displayName>AHBSMENR</displayName>
  8439. <description>AHB peripheral clock enable in sleep mode
  8440. register</description>
  8441. <addressOffset>0x40</addressOffset>
  8442. <size>0x20</size>
  8443. <access>read-write</access>
  8444. <resetValue>0x01111301</resetValue>
  8445. <fields>
  8446. <field>
  8447. <name>CRYPTSMEN</name>
  8448. <description>Crypto clock enable during sleep mode
  8449. bit</description>
  8450. <bitOffset>24</bitOffset>
  8451. <bitWidth>1</bitWidth>
  8452. </field>
  8453. <field>
  8454. <name>CRCSMEN</name>
  8455. <description>CRC clock enable during sleep mode
  8456. bit</description>
  8457. <bitOffset>12</bitOffset>
  8458. <bitWidth>1</bitWidth>
  8459. </field>
  8460. <field>
  8461. <name>SRAMSMEN</name>
  8462. <description>SRAM interface clock enable during sleep
  8463. mode bit</description>
  8464. <bitOffset>9</bitOffset>
  8465. <bitWidth>1</bitWidth>
  8466. </field>
  8467. <field>
  8468. <name>MIFSMEN</name>
  8469. <description>NVM interface clock enable during sleep
  8470. mode bit</description>
  8471. <bitOffset>8</bitOffset>
  8472. <bitWidth>1</bitWidth>
  8473. </field>
  8474. <field>
  8475. <name>DMASMEN</name>
  8476. <description>DMA clock enable during sleep mode
  8477. bit</description>
  8478. <bitOffset>0</bitOffset>
  8479. <bitWidth>1</bitWidth>
  8480. </field>
  8481. </fields>
  8482. </register>
  8483. <register>
  8484. <name>APB2SMENR</name>
  8485. <displayName>APB2SMENR</displayName>
  8486. <description>APB2 peripheral clock enable in sleep mode
  8487. register</description>
  8488. <addressOffset>0x44</addressOffset>
  8489. <size>0x20</size>
  8490. <access>read-write</access>
  8491. <resetValue>0x00405225</resetValue>
  8492. <fields>
  8493. <field>
  8494. <name>DBGSMEN</name>
  8495. <description>DBG clock enable during sleep mode
  8496. bit</description>
  8497. <bitOffset>22</bitOffset>
  8498. <bitWidth>1</bitWidth>
  8499. </field>
  8500. <field>
  8501. <name>USART1SMEN</name>
  8502. <description>USART1 clock enable during sleep mode
  8503. bit</description>
  8504. <bitOffset>14</bitOffset>
  8505. <bitWidth>1</bitWidth>
  8506. </field>
  8507. <field>
  8508. <name>SPI1SMEN</name>
  8509. <description>SPI1 clock enable during sleep mode
  8510. bit</description>
  8511. <bitOffset>12</bitOffset>
  8512. <bitWidth>1</bitWidth>
  8513. </field>
  8514. <field>
  8515. <name>ADCSMEN</name>
  8516. <description>ADC clock enable during sleep mode
  8517. bit</description>
  8518. <bitOffset>9</bitOffset>
  8519. <bitWidth>1</bitWidth>
  8520. </field>
  8521. <field>
  8522. <name>TIM22SMEN</name>
  8523. <description>TIM22 timer clock enable during sleep
  8524. mode bit</description>
  8525. <bitOffset>5</bitOffset>
  8526. <bitWidth>1</bitWidth>
  8527. </field>
  8528. <field>
  8529. <name>TIM21SMEN</name>
  8530. <description>TIM21 timer clock enable during sleep
  8531. mode bit</description>
  8532. <bitOffset>2</bitOffset>
  8533. <bitWidth>1</bitWidth>
  8534. </field>
  8535. <field>
  8536. <name>SYSCFGSMEN</name>
  8537. <description>System configuration controller clock
  8538. enable during sleep mode bit</description>
  8539. <bitOffset>0</bitOffset>
  8540. <bitWidth>1</bitWidth>
  8541. </field>
  8542. </fields>
  8543. </register>
  8544. <register>
  8545. <name>APB1SMENR</name>
  8546. <displayName>APB1SMENR</displayName>
  8547. <description>APB1 peripheral clock enable in sleep mode
  8548. register</description>
  8549. <addressOffset>0x48</addressOffset>
  8550. <size>0x20</size>
  8551. <access>read-write</access>
  8552. <resetValue>0xB8E64A11</resetValue>
  8553. <fields>
  8554. <field>
  8555. <name>LPTIM1SMEN</name>
  8556. <description>Low power timer clock enable during
  8557. sleep mode bit</description>
  8558. <bitOffset>31</bitOffset>
  8559. <bitWidth>1</bitWidth>
  8560. </field>
  8561. <field>
  8562. <name>PWRSMEN</name>
  8563. <description>Power interface clock enable during
  8564. sleep mode bit</description>
  8565. <bitOffset>28</bitOffset>
  8566. <bitWidth>1</bitWidth>
  8567. </field>
  8568. <field>
  8569. <name>CRSSMEN</name>
  8570. <description>Clock recovery system clock enable
  8571. during sleep mode bit</description>
  8572. <bitOffset>27</bitOffset>
  8573. <bitWidth>1</bitWidth>
  8574. </field>
  8575. <field>
  8576. <name>I2C2SMEN</name>
  8577. <description>I2C2 clock enable during sleep mode
  8578. bit</description>
  8579. <bitOffset>22</bitOffset>
  8580. <bitWidth>1</bitWidth>
  8581. </field>
  8582. <field>
  8583. <name>I2C1SMEN</name>
  8584. <description>I2C1 clock enable during sleep mode
  8585. bit</description>
  8586. <bitOffset>21</bitOffset>
  8587. <bitWidth>1</bitWidth>
  8588. </field>
  8589. <field>
  8590. <name>LPUART1SMEN</name>
  8591. <description>LPUART1 clock enable during sleep mode
  8592. bit</description>
  8593. <bitOffset>18</bitOffset>
  8594. <bitWidth>1</bitWidth>
  8595. </field>
  8596. <field>
  8597. <name>USART2SMEN</name>
  8598. <description>UART2 clock enable during sleep mode
  8599. bit</description>
  8600. <bitOffset>17</bitOffset>
  8601. <bitWidth>1</bitWidth>
  8602. </field>
  8603. <field>
  8604. <name>SPI2SMEN</name>
  8605. <description>SPI2 clock enable during sleep mode
  8606. bit</description>
  8607. <bitOffset>14</bitOffset>
  8608. <bitWidth>1</bitWidth>
  8609. </field>
  8610. <field>
  8611. <name>WWDGSMEN</name>
  8612. <description>Window watchdog clock enable during
  8613. sleep mode bit</description>
  8614. <bitOffset>11</bitOffset>
  8615. <bitWidth>1</bitWidth>
  8616. </field>
  8617. <field>
  8618. <name>TIM6SMEN</name>
  8619. <description>Timer 6 clock enable during sleep mode
  8620. bit</description>
  8621. <bitOffset>4</bitOffset>
  8622. <bitWidth>1</bitWidth>
  8623. </field>
  8624. <field>
  8625. <name>TIM2SMEN</name>
  8626. <description>Timer2 clock enable during sleep mode
  8627. bit</description>
  8628. <bitOffset>0</bitOffset>
  8629. <bitWidth>1</bitWidth>
  8630. </field>
  8631. <field>
  8632. <name>TIM3SMEN</name>
  8633. <description>Timer 3 clock enable during sleep mode
  8634. bit</description>
  8635. <bitOffset>1</bitOffset>
  8636. <bitWidth>1</bitWidth>
  8637. </field>
  8638. <field>
  8639. <name>TIM7SMEN</name>
  8640. <description>Timer 7 clock enable during sleep mode
  8641. bit</description>
  8642. <bitOffset>5</bitOffset>
  8643. <bitWidth>1</bitWidth>
  8644. </field>
  8645. <field>
  8646. <name>USART4SMEN</name>
  8647. <description>USART4 clock enabe during sleep mode
  8648. bit</description>
  8649. <bitOffset>19</bitOffset>
  8650. <bitWidth>1</bitWidth>
  8651. </field>
  8652. <field>
  8653. <name>USART5SMEN</name>
  8654. <description>USART5 clock enable during sleep mode
  8655. bit</description>
  8656. <bitOffset>20</bitOffset>
  8657. <bitWidth>1</bitWidth>
  8658. </field>
  8659. <field>
  8660. <name>I2C3SMEN</name>
  8661. <description>I2C3 clock enable during sleep mode
  8662. bit</description>
  8663. <bitOffset>30</bitOffset>
  8664. <bitWidth>1</bitWidth>
  8665. </field>
  8666. </fields>
  8667. </register>
  8668. <register>
  8669. <name>CCIPR</name>
  8670. <displayName>CCIPR</displayName>
  8671. <description>Clock configuration register</description>
  8672. <addressOffset>0x4C</addressOffset>
  8673. <size>0x20</size>
  8674. <access>read-write</access>
  8675. <resetValue>0x00000000</resetValue>
  8676. <fields>
  8677. <field>
  8678. <name>LPTIM1SEL1</name>
  8679. <description>Low Power Timer clock source selection
  8680. bits</description>
  8681. <bitOffset>19</bitOffset>
  8682. <bitWidth>1</bitWidth>
  8683. </field>
  8684. <field>
  8685. <name>LPTIM1SEL0</name>
  8686. <description>LPTIM1SEL0</description>
  8687. <bitOffset>18</bitOffset>
  8688. <bitWidth>1</bitWidth>
  8689. </field>
  8690. <field>
  8691. <name>I2C1SEL1</name>
  8692. <description>I2C1 clock source selection
  8693. bits</description>
  8694. <bitOffset>13</bitOffset>
  8695. <bitWidth>1</bitWidth>
  8696. </field>
  8697. <field>
  8698. <name>I2C1SEL0</name>
  8699. <description>I2C1SEL0</description>
  8700. <bitOffset>12</bitOffset>
  8701. <bitWidth>1</bitWidth>
  8702. </field>
  8703. <field>
  8704. <name>LPUART1SEL1</name>
  8705. <description>LPUART1 clock source selection
  8706. bits</description>
  8707. <bitOffset>11</bitOffset>
  8708. <bitWidth>1</bitWidth>
  8709. </field>
  8710. <field>
  8711. <name>LPUART1SEL0</name>
  8712. <description>LPUART1SEL0</description>
  8713. <bitOffset>10</bitOffset>
  8714. <bitWidth>1</bitWidth>
  8715. </field>
  8716. <field>
  8717. <name>USART2SEL1</name>
  8718. <description>USART2 clock source selection
  8719. bits</description>
  8720. <bitOffset>3</bitOffset>
  8721. <bitWidth>1</bitWidth>
  8722. </field>
  8723. <field>
  8724. <name>USART2SEL0</name>
  8725. <description>USART2SEL0</description>
  8726. <bitOffset>2</bitOffset>
  8727. <bitWidth>1</bitWidth>
  8728. </field>
  8729. <field>
  8730. <name>USART1SEL1</name>
  8731. <description>USART1 clock source selection
  8732. bits</description>
  8733. <bitOffset>1</bitOffset>
  8734. <bitWidth>1</bitWidth>
  8735. </field>
  8736. <field>
  8737. <name>USART1SEL0</name>
  8738. <description>USART1SEL0</description>
  8739. <bitOffset>0</bitOffset>
  8740. <bitWidth>1</bitWidth>
  8741. </field>
  8742. <field>
  8743. <name>I2C3SEL0</name>
  8744. <description>I2C3 clock source selection
  8745. bits</description>
  8746. <bitOffset>16</bitOffset>
  8747. <bitWidth>1</bitWidth>
  8748. </field>
  8749. <field>
  8750. <name>I2C3SEL1</name>
  8751. <description>I2C3 clock source selection
  8752. bits</description>
  8753. <bitOffset>17</bitOffset>
  8754. <bitWidth>1</bitWidth>
  8755. </field>
  8756. </fields>
  8757. </register>
  8758. <register>
  8759. <name>CSR</name>
  8760. <displayName>CSR</displayName>
  8761. <description>Control and status register</description>
  8762. <addressOffset>0x50</addressOffset>
  8763. <size>0x20</size>
  8764. <resetValue>0x0C000000</resetValue>
  8765. <fields>
  8766. <field>
  8767. <name>LPWRSTF</name>
  8768. <description>Low-power reset flag</description>
  8769. <bitOffset>31</bitOffset>
  8770. <bitWidth>1</bitWidth>
  8771. <access>read-write</access>
  8772. </field>
  8773. <field>
  8774. <name>WWDGRSTF</name>
  8775. <description>Window watchdog reset flag</description>
  8776. <bitOffset>30</bitOffset>
  8777. <bitWidth>1</bitWidth>
  8778. <access>read-write</access>
  8779. </field>
  8780. <field>
  8781. <name>IWDGRSTF</name>
  8782. <description>Independent watchdog reset
  8783. flag</description>
  8784. <bitOffset>29</bitOffset>
  8785. <bitWidth>1</bitWidth>
  8786. <access>read-write</access>
  8787. </field>
  8788. <field>
  8789. <name>SFTRSTF</name>
  8790. <description>Software reset flag</description>
  8791. <bitOffset>28</bitOffset>
  8792. <bitWidth>1</bitWidth>
  8793. <access>read-write</access>
  8794. </field>
  8795. <field>
  8796. <name>PORRSTF</name>
  8797. <description>POR/PDR reset flag</description>
  8798. <bitOffset>27</bitOffset>
  8799. <bitWidth>1</bitWidth>
  8800. <access>read-write</access>
  8801. </field>
  8802. <field>
  8803. <name>PINRSTF</name>
  8804. <description>PIN reset flag</description>
  8805. <bitOffset>26</bitOffset>
  8806. <bitWidth>1</bitWidth>
  8807. <access>read-write</access>
  8808. </field>
  8809. <field>
  8810. <name>OBLRSTF</name>
  8811. <description>OBLRSTF</description>
  8812. <bitOffset>25</bitOffset>
  8813. <bitWidth>1</bitWidth>
  8814. <access>read-write</access>
  8815. </field>
  8816. <field>
  8817. <name>FWRSTF</name>
  8818. <description>Firewall reset flag</description>
  8819. <bitOffset>24</bitOffset>
  8820. <bitWidth>1</bitWidth>
  8821. <access>read-write</access>
  8822. </field>
  8823. <field>
  8824. <name>RTCRST</name>
  8825. <description>RTC software reset bit</description>
  8826. <bitOffset>19</bitOffset>
  8827. <bitWidth>1</bitWidth>
  8828. <access>read-write</access>
  8829. </field>
  8830. <field>
  8831. <name>RTCEN</name>
  8832. <description>RTC clock enable bit</description>
  8833. <bitOffset>18</bitOffset>
  8834. <bitWidth>1</bitWidth>
  8835. <access>read-write</access>
  8836. </field>
  8837. <field>
  8838. <name>RTCSEL</name>
  8839. <description>RTC and LCD clock source selection
  8840. bits</description>
  8841. <bitOffset>16</bitOffset>
  8842. <bitWidth>2</bitWidth>
  8843. <access>read-write</access>
  8844. </field>
  8845. <field>
  8846. <name>CSSLSED</name>
  8847. <description>CSS on LSE failure detection
  8848. flag</description>
  8849. <bitOffset>14</bitOffset>
  8850. <bitWidth>1</bitWidth>
  8851. <access>read-write</access>
  8852. </field>
  8853. <field>
  8854. <name>CSSLSEON</name>
  8855. <description>CSSLSEON</description>
  8856. <bitOffset>13</bitOffset>
  8857. <bitWidth>1</bitWidth>
  8858. <access>read-write</access>
  8859. </field>
  8860. <field>
  8861. <name>LSEDRV</name>
  8862. <description>LSEDRV</description>
  8863. <bitOffset>11</bitOffset>
  8864. <bitWidth>2</bitWidth>
  8865. <access>read-write</access>
  8866. </field>
  8867. <field>
  8868. <name>LSEBYP</name>
  8869. <description>External low-speed oscillator bypass
  8870. bit</description>
  8871. <bitOffset>10</bitOffset>
  8872. <bitWidth>1</bitWidth>
  8873. <access>read-write</access>
  8874. </field>
  8875. <field>
  8876. <name>LSERDY</name>
  8877. <description>External low-speed oscillator ready
  8878. bit</description>
  8879. <bitOffset>9</bitOffset>
  8880. <bitWidth>1</bitWidth>
  8881. <access>read-only</access>
  8882. </field>
  8883. <field>
  8884. <name>LSEON</name>
  8885. <description>External low-speed oscillator enable
  8886. bit</description>
  8887. <bitOffset>8</bitOffset>
  8888. <bitWidth>1</bitWidth>
  8889. <access>read-write</access>
  8890. </field>
  8891. <field>
  8892. <name>LSIRDY</name>
  8893. <description>Internal low-speed oscillator ready
  8894. bit</description>
  8895. <bitOffset>1</bitOffset>
  8896. <bitWidth>1</bitWidth>
  8897. <access>read-only</access>
  8898. </field>
  8899. <field>
  8900. <name>LSION</name>
  8901. <description>Internal low-speed oscillator
  8902. enable</description>
  8903. <bitOffset>0</bitOffset>
  8904. <bitWidth>1</bitWidth>
  8905. <access>read-write</access>
  8906. </field>
  8907. <field>
  8908. <name>LSIIWDGLP</name>
  8909. <description>LSI clock input to IWDG in
  8910. Ultra-low-power mode (Stop and Standby) enable
  8911. bit</description>
  8912. <bitOffset>2</bitOffset>
  8913. <bitWidth>1</bitWidth>
  8914. <access>read-write</access>
  8915. </field>
  8916. <field>
  8917. <name>RMVF</name>
  8918. <description>Remove reset flag</description>
  8919. <bitOffset>23</bitOffset>
  8920. <bitWidth>1</bitWidth>
  8921. <access>read-write</access>
  8922. </field>
  8923. </fields>
  8924. </register>
  8925. </registers>
  8926. </peripheral>
  8927. <peripheral>
  8928. <name>SYSCFG</name>
  8929. <description>System configuration controller</description>
  8930. <groupName>SYSCFG</groupName>
  8931. <baseAddress>0x40010000</baseAddress>
  8932. <addressBlock>
  8933. <offset>0x0</offset>
  8934. <size>0x400</size>
  8935. <usage>registers</usage>
  8936. </addressBlock>
  8937. <registers>
  8938. <register>
  8939. <name>CFGR1</name>
  8940. <displayName>CFGR1</displayName>
  8941. <description>SYSCFG configuration register
  8942. 1</description>
  8943. <addressOffset>0x0</addressOffset>
  8944. <size>0x20</size>
  8945. <resetValue>0x00000000</resetValue>
  8946. <fields>
  8947. <field>
  8948. <name>BOOT_MODE</name>
  8949. <description>Boot mode selected by the boot pins
  8950. status bits</description>
  8951. <bitOffset>8</bitOffset>
  8952. <bitWidth>2</bitWidth>
  8953. <access>read-only</access>
  8954. </field>
  8955. <field>
  8956. <name>MEM_MODE</name>
  8957. <description>Memory mapping selection
  8958. bits</description>
  8959. <bitOffset>0</bitOffset>
  8960. <bitWidth>2</bitWidth>
  8961. <access>read-write</access>
  8962. </field>
  8963. </fields>
  8964. </register>
  8965. <register>
  8966. <name>CFGR2</name>
  8967. <displayName>CFGR2</displayName>
  8968. <description>SYSCFG configuration register
  8969. 2</description>
  8970. <addressOffset>0x4</addressOffset>
  8971. <size>0x20</size>
  8972. <access>read-write</access>
  8973. <resetValue>0x00000000</resetValue>
  8974. <fields>
  8975. <field>
  8976. <name>I2C2_FMP</name>
  8977. <description>I2C2 Fm+ drive capability enable
  8978. bit</description>
  8979. <bitOffset>13</bitOffset>
  8980. <bitWidth>1</bitWidth>
  8981. </field>
  8982. <field>
  8983. <name>I2C1_FMP</name>
  8984. <description>I2C1 Fm+ drive capability enable
  8985. bit</description>
  8986. <bitOffset>12</bitOffset>
  8987. <bitWidth>1</bitWidth>
  8988. </field>
  8989. <field>
  8990. <name>I2C_PB9_FMP</name>
  8991. <description>Fm+ drive capability on PB9 enable
  8992. bit</description>
  8993. <bitOffset>11</bitOffset>
  8994. <bitWidth>1</bitWidth>
  8995. </field>
  8996. <field>
  8997. <name>I2C_PB8_FMP</name>
  8998. <description>Fm+ drive capability on PB8 enable
  8999. bit</description>
  9000. <bitOffset>10</bitOffset>
  9001. <bitWidth>1</bitWidth>
  9002. </field>
  9003. <field>
  9004. <name>I2C_PB7_FMP</name>
  9005. <description>Fm+ drive capability on PB7 enable
  9006. bit</description>
  9007. <bitOffset>9</bitOffset>
  9008. <bitWidth>1</bitWidth>
  9009. </field>
  9010. <field>
  9011. <name>I2C_PB6_FMP</name>
  9012. <description>Fm+ drive capability on PB6 enable
  9013. bit</description>
  9014. <bitOffset>8</bitOffset>
  9015. <bitWidth>1</bitWidth>
  9016. </field>
  9017. <field>
  9018. <name>CAPA</name>
  9019. <description>Configuration of internal VLCD rail
  9020. connection to optional external
  9021. capacitor</description>
  9022. <bitOffset>1</bitOffset>
  9023. <bitWidth>3</bitWidth>
  9024. </field>
  9025. <field>
  9026. <name>FWDISEN</name>
  9027. <description>Firewall disable bit</description>
  9028. <bitOffset>0</bitOffset>
  9029. <bitWidth>1</bitWidth>
  9030. </field>
  9031. </fields>
  9032. </register>
  9033. <register>
  9034. <name>EXTICR1</name>
  9035. <displayName>EXTICR1</displayName>
  9036. <description>external interrupt configuration register
  9037. 1</description>
  9038. <addressOffset>0x8</addressOffset>
  9039. <size>0x20</size>
  9040. <access>read-write</access>
  9041. <resetValue>0x0000</resetValue>
  9042. <fields>
  9043. <field>
  9044. <name>EXTI3</name>
  9045. <description>EXTI x configuration (x = 0 to
  9046. 3)</description>
  9047. <bitOffset>12</bitOffset>
  9048. <bitWidth>4</bitWidth>
  9049. </field>
  9050. <field>
  9051. <name>EXTI2</name>
  9052. <description>EXTI x configuration (x = 0 to
  9053. 3)</description>
  9054. <bitOffset>8</bitOffset>
  9055. <bitWidth>4</bitWidth>
  9056. </field>
  9057. <field>
  9058. <name>EXTI1</name>
  9059. <description>EXTI x configuration (x = 0 to
  9060. 3)</description>
  9061. <bitOffset>4</bitOffset>
  9062. <bitWidth>4</bitWidth>
  9063. </field>
  9064. <field>
  9065. <name>EXTI0</name>
  9066. <description>EXTI x configuration (x = 0 to
  9067. 3)</description>
  9068. <bitOffset>0</bitOffset>
  9069. <bitWidth>4</bitWidth>
  9070. </field>
  9071. </fields>
  9072. </register>
  9073. <register>
  9074. <name>EXTICR2</name>
  9075. <displayName>EXTICR2</displayName>
  9076. <description>external interrupt configuration register
  9077. 2</description>
  9078. <addressOffset>0xC</addressOffset>
  9079. <size>0x20</size>
  9080. <access>read-write</access>
  9081. <resetValue>0x0000</resetValue>
  9082. <fields>
  9083. <field>
  9084. <name>EXTI7</name>
  9085. <description>EXTI x configuration (x = 4 to
  9086. 7)</description>
  9087. <bitOffset>12</bitOffset>
  9088. <bitWidth>4</bitWidth>
  9089. </field>
  9090. <field>
  9091. <name>EXTI6</name>
  9092. <description>EXTI x configuration (x = 4 to
  9093. 7)</description>
  9094. <bitOffset>8</bitOffset>
  9095. <bitWidth>4</bitWidth>
  9096. </field>
  9097. <field>
  9098. <name>EXTI5</name>
  9099. <description>EXTI x configuration (x = 4 to
  9100. 7)</description>
  9101. <bitOffset>4</bitOffset>
  9102. <bitWidth>4</bitWidth>
  9103. </field>
  9104. <field>
  9105. <name>EXTI4</name>
  9106. <description>EXTI x configuration (x = 4 to
  9107. 7)</description>
  9108. <bitOffset>0</bitOffset>
  9109. <bitWidth>4</bitWidth>
  9110. </field>
  9111. </fields>
  9112. </register>
  9113. <register>
  9114. <name>EXTICR3</name>
  9115. <displayName>EXTICR3</displayName>
  9116. <description>external interrupt configuration register
  9117. 3</description>
  9118. <addressOffset>0x10</addressOffset>
  9119. <size>0x20</size>
  9120. <access>read-write</access>
  9121. <resetValue>0x0000</resetValue>
  9122. <fields>
  9123. <field>
  9124. <name>EXTI11</name>
  9125. <description>EXTI x configuration (x = 8 to
  9126. 11)</description>
  9127. <bitOffset>12</bitOffset>
  9128. <bitWidth>4</bitWidth>
  9129. </field>
  9130. <field>
  9131. <name>EXTI10</name>
  9132. <description>EXTI10</description>
  9133. <bitOffset>8</bitOffset>
  9134. <bitWidth>4</bitWidth>
  9135. </field>
  9136. <field>
  9137. <name>EXTI9</name>
  9138. <description>EXTI x configuration (x = 8 to
  9139. 11)</description>
  9140. <bitOffset>4</bitOffset>
  9141. <bitWidth>4</bitWidth>
  9142. </field>
  9143. <field>
  9144. <name>EXTI8</name>
  9145. <description>EXTI x configuration (x = 8 to
  9146. 11)</description>
  9147. <bitOffset>0</bitOffset>
  9148. <bitWidth>4</bitWidth>
  9149. </field>
  9150. </fields>
  9151. </register>
  9152. <register>
  9153. <name>EXTICR4</name>
  9154. <displayName>EXTICR4</displayName>
  9155. <description>external interrupt configuration register
  9156. 4</description>
  9157. <addressOffset>0x14</addressOffset>
  9158. <size>0x20</size>
  9159. <access>read-write</access>
  9160. <resetValue>0x0000</resetValue>
  9161. <fields>
  9162. <field>
  9163. <name>EXTI15</name>
  9164. <description>EXTI x configuration (x = 12 to
  9165. 15)</description>
  9166. <bitOffset>12</bitOffset>
  9167. <bitWidth>4</bitWidth>
  9168. </field>
  9169. <field>
  9170. <name>EXTI14</name>
  9171. <description>EXTI14</description>
  9172. <bitOffset>8</bitOffset>
  9173. <bitWidth>4</bitWidth>
  9174. </field>
  9175. <field>
  9176. <name>EXTI13</name>
  9177. <description>EXTI13</description>
  9178. <bitOffset>4</bitOffset>
  9179. <bitWidth>4</bitWidth>
  9180. </field>
  9181. <field>
  9182. <name>EXTI12</name>
  9183. <description>EXTI12</description>
  9184. <bitOffset>0</bitOffset>
  9185. <bitWidth>4</bitWidth>
  9186. </field>
  9187. </fields>
  9188. </register>
  9189. <register>
  9190. <name>CFGR3</name>
  9191. <displayName>CFGR3</displayName>
  9192. <description>SYSCFG configuration register
  9193. 3</description>
  9194. <addressOffset>0x20</addressOffset>
  9195. <size>0x20</size>
  9196. <resetValue>0x00000000</resetValue>
  9197. <fields>
  9198. <field>
  9199. <name>REF_LOCK</name>
  9200. <description>REF_CTRL lock bit</description>
  9201. <bitOffset>31</bitOffset>
  9202. <bitWidth>1</bitWidth>
  9203. <access>write-only</access>
  9204. </field>
  9205. <field>
  9206. <name>VREFINT_RDYF</name>
  9207. <description>VREFINT ready flag</description>
  9208. <bitOffset>30</bitOffset>
  9209. <bitWidth>1</bitWidth>
  9210. <access>read-only</access>
  9211. </field>
  9212. <field>
  9213. <name>VREFINT_COMP_RDYF</name>
  9214. <description>VREFINT for comparator ready
  9215. flag</description>
  9216. <bitOffset>29</bitOffset>
  9217. <bitWidth>1</bitWidth>
  9218. <access>read-only</access>
  9219. </field>
  9220. <field>
  9221. <name>VREFINT_ADC_RDYF</name>
  9222. <description>VREFINT for ADC ready flag</description>
  9223. <bitOffset>28</bitOffset>
  9224. <bitWidth>1</bitWidth>
  9225. <access>read-only</access>
  9226. </field>
  9227. <field>
  9228. <name>SENSOR_ADC_RDYF</name>
  9229. <description>Sensor for ADC ready flag</description>
  9230. <bitOffset>27</bitOffset>
  9231. <bitWidth>1</bitWidth>
  9232. <access>read-only</access>
  9233. </field>
  9234. <field>
  9235. <name>REF_RC48MHz_RDYF</name>
  9236. <description>VREFINT for 48 MHz RC oscillator ready
  9237. flag</description>
  9238. <bitOffset>26</bitOffset>
  9239. <bitWidth>1</bitWidth>
  9240. <access>read-only</access>
  9241. </field>
  9242. <field>
  9243. <name>ENREF_RC48MHz</name>
  9244. <description>VREFINT reference for 48 MHz RC
  9245. oscillator enable bit</description>
  9246. <bitOffset>13</bitOffset>
  9247. <bitWidth>1</bitWidth>
  9248. <access>read-write</access>
  9249. </field>
  9250. <field>
  9251. <name>ENBUF_VREFINT_COMP</name>
  9252. <description>VREFINT reference for comparator 2
  9253. enable bit</description>
  9254. <bitOffset>12</bitOffset>
  9255. <bitWidth>1</bitWidth>
  9256. <access>read-write</access>
  9257. </field>
  9258. <field>
  9259. <name>ENBUF_SENSOR_ADC</name>
  9260. <description>Sensor reference for ADC enable
  9261. bit</description>
  9262. <bitOffset>9</bitOffset>
  9263. <bitWidth>1</bitWidth>
  9264. <access>read-write</access>
  9265. </field>
  9266. <field>
  9267. <name>ENBUF_BGAP_ADC</name>
  9268. <description>VREFINT reference for ADC enable
  9269. bit</description>
  9270. <bitOffset>8</bitOffset>
  9271. <bitWidth>1</bitWidth>
  9272. <access>read-write</access>
  9273. </field>
  9274. <field>
  9275. <name>SEL_VREF_OUT</name>
  9276. <description>BGAP_ADC connection bit</description>
  9277. <bitOffset>4</bitOffset>
  9278. <bitWidth>2</bitWidth>
  9279. <access>read-write</access>
  9280. </field>
  9281. <field>
  9282. <name>EN_BGAP</name>
  9283. <description>Vref Enable bit</description>
  9284. <bitOffset>0</bitOffset>
  9285. <bitWidth>1</bitWidth>
  9286. <access>read-write</access>
  9287. </field>
  9288. </fields>
  9289. </register>
  9290. </registers>
  9291. </peripheral>
  9292. <peripheral>
  9293. <name>SPI1</name>
  9294. <description>Serial peripheral interface</description>
  9295. <groupName>SPI</groupName>
  9296. <baseAddress>0x40013000</baseAddress>
  9297. <addressBlock>
  9298. <offset>0x0</offset>
  9299. <size>0x400</size>
  9300. <usage>registers</usage>
  9301. </addressBlock>
  9302. <interrupt>
  9303. <name>SPI1</name>
  9304. <description>SPI1_global_interrupt</description>
  9305. <value>25</value>
  9306. </interrupt>
  9307. <registers>
  9308. <register>
  9309. <name>CR1</name>
  9310. <displayName>CR1</displayName>
  9311. <description>control register 1</description>
  9312. <addressOffset>0x0</addressOffset>
  9313. <size>0x20</size>
  9314. <access>read-write</access>
  9315. <resetValue>0x0000</resetValue>
  9316. <fields>
  9317. <field>
  9318. <name>BIDIMODE</name>
  9319. <description>Bidirectional data mode
  9320. enable</description>
  9321. <bitOffset>15</bitOffset>
  9322. <bitWidth>1</bitWidth>
  9323. </field>
  9324. <field>
  9325. <name>BIDIOE</name>
  9326. <description>Output enable in bidirectional
  9327. mode</description>
  9328. <bitOffset>14</bitOffset>
  9329. <bitWidth>1</bitWidth>
  9330. </field>
  9331. <field>
  9332. <name>CRCEN</name>
  9333. <description>Hardware CRC calculation
  9334. enable</description>
  9335. <bitOffset>13</bitOffset>
  9336. <bitWidth>1</bitWidth>
  9337. </field>
  9338. <field>
  9339. <name>CRCNEXT</name>
  9340. <description>CRC transfer next</description>
  9341. <bitOffset>12</bitOffset>
  9342. <bitWidth>1</bitWidth>
  9343. </field>
  9344. <field>
  9345. <name>DFF</name>
  9346. <description>Data frame format</description>
  9347. <bitOffset>11</bitOffset>
  9348. <bitWidth>1</bitWidth>
  9349. </field>
  9350. <field>
  9351. <name>RXONLY</name>
  9352. <description>Receive only</description>
  9353. <bitOffset>10</bitOffset>
  9354. <bitWidth>1</bitWidth>
  9355. </field>
  9356. <field>
  9357. <name>SSM</name>
  9358. <description>Software slave management</description>
  9359. <bitOffset>9</bitOffset>
  9360. <bitWidth>1</bitWidth>
  9361. </field>
  9362. <field>
  9363. <name>SSI</name>
  9364. <description>Internal slave select</description>
  9365. <bitOffset>8</bitOffset>
  9366. <bitWidth>1</bitWidth>
  9367. </field>
  9368. <field>
  9369. <name>LSBFIRST</name>
  9370. <description>Frame format</description>
  9371. <bitOffset>7</bitOffset>
  9372. <bitWidth>1</bitWidth>
  9373. </field>
  9374. <field>
  9375. <name>SPE</name>
  9376. <description>SPI enable</description>
  9377. <bitOffset>6</bitOffset>
  9378. <bitWidth>1</bitWidth>
  9379. </field>
  9380. <field>
  9381. <name>BR</name>
  9382. <description>Baud rate control</description>
  9383. <bitOffset>3</bitOffset>
  9384. <bitWidth>3</bitWidth>
  9385. </field>
  9386. <field>
  9387. <name>MSTR</name>
  9388. <description>Master selection</description>
  9389. <bitOffset>2</bitOffset>
  9390. <bitWidth>1</bitWidth>
  9391. </field>
  9392. <field>
  9393. <name>CPOL</name>
  9394. <description>Clock polarity</description>
  9395. <bitOffset>1</bitOffset>
  9396. <bitWidth>1</bitWidth>
  9397. </field>
  9398. <field>
  9399. <name>CPHA</name>
  9400. <description>Clock phase</description>
  9401. <bitOffset>0</bitOffset>
  9402. <bitWidth>1</bitWidth>
  9403. </field>
  9404. </fields>
  9405. </register>
  9406. <register>
  9407. <name>CR2</name>
  9408. <displayName>CR2</displayName>
  9409. <description>control register 2</description>
  9410. <addressOffset>0x4</addressOffset>
  9411. <size>0x20</size>
  9412. <access>read-write</access>
  9413. <resetValue>0x0000</resetValue>
  9414. <fields>
  9415. <field>
  9416. <name>RXDMAEN</name>
  9417. <description>Rx buffer DMA enable</description>
  9418. <bitOffset>0</bitOffset>
  9419. <bitWidth>1</bitWidth>
  9420. </field>
  9421. <field>
  9422. <name>TXDMAEN</name>
  9423. <description>Tx buffer DMA enable</description>
  9424. <bitOffset>1</bitOffset>
  9425. <bitWidth>1</bitWidth>
  9426. </field>
  9427. <field>
  9428. <name>SSOE</name>
  9429. <description>SS output enable</description>
  9430. <bitOffset>2</bitOffset>
  9431. <bitWidth>1</bitWidth>
  9432. </field>
  9433. <field>
  9434. <name>FRF</name>
  9435. <description>Frame format</description>
  9436. <bitOffset>4</bitOffset>
  9437. <bitWidth>1</bitWidth>
  9438. </field>
  9439. <field>
  9440. <name>ERRIE</name>
  9441. <description>Error interrupt enable</description>
  9442. <bitOffset>5</bitOffset>
  9443. <bitWidth>1</bitWidth>
  9444. </field>
  9445. <field>
  9446. <name>RXNEIE</name>
  9447. <description>RX buffer not empty interrupt
  9448. enable</description>
  9449. <bitOffset>6</bitOffset>
  9450. <bitWidth>1</bitWidth>
  9451. </field>
  9452. <field>
  9453. <name>TXEIE</name>
  9454. <description>Tx buffer empty interrupt
  9455. enable</description>
  9456. <bitOffset>7</bitOffset>
  9457. <bitWidth>1</bitWidth>
  9458. </field>
  9459. </fields>
  9460. </register>
  9461. <register>
  9462. <name>SR</name>
  9463. <displayName>SR</displayName>
  9464. <description>status register</description>
  9465. <addressOffset>0x8</addressOffset>
  9466. <size>0x20</size>
  9467. <resetValue>0x0002</resetValue>
  9468. <fields>
  9469. <field>
  9470. <name>RXNE</name>
  9471. <description>Receive buffer not empty</description>
  9472. <bitOffset>0</bitOffset>
  9473. <bitWidth>1</bitWidth>
  9474. <access>read-only</access>
  9475. </field>
  9476. <field>
  9477. <name>TXE</name>
  9478. <description>Transmit buffer empty</description>
  9479. <bitOffset>1</bitOffset>
  9480. <bitWidth>1</bitWidth>
  9481. <access>read-only</access>
  9482. </field>
  9483. <field>
  9484. <name>CHSIDE</name>
  9485. <description>Channel side</description>
  9486. <bitOffset>2</bitOffset>
  9487. <bitWidth>1</bitWidth>
  9488. <access>read-only</access>
  9489. </field>
  9490. <field>
  9491. <name>UDR</name>
  9492. <description>Underrun flag</description>
  9493. <bitOffset>3</bitOffset>
  9494. <bitWidth>1</bitWidth>
  9495. <access>read-only</access>
  9496. </field>
  9497. <field>
  9498. <name>CRCERR</name>
  9499. <description>CRC error flag</description>
  9500. <bitOffset>4</bitOffset>
  9501. <bitWidth>1</bitWidth>
  9502. <access>read-write</access>
  9503. </field>
  9504. <field>
  9505. <name>MODF</name>
  9506. <description>Mode fault</description>
  9507. <bitOffset>5</bitOffset>
  9508. <bitWidth>1</bitWidth>
  9509. <access>read-only</access>
  9510. </field>
  9511. <field>
  9512. <name>OVR</name>
  9513. <description>Overrun flag</description>
  9514. <bitOffset>6</bitOffset>
  9515. <bitWidth>1</bitWidth>
  9516. <access>read-only</access>
  9517. </field>
  9518. <field>
  9519. <name>BSY</name>
  9520. <description>Busy flag</description>
  9521. <bitOffset>7</bitOffset>
  9522. <bitWidth>1</bitWidth>
  9523. <access>read-only</access>
  9524. </field>
  9525. <field>
  9526. <name>TIFRFE</name>
  9527. <description>TI frame format error</description>
  9528. <bitOffset>8</bitOffset>
  9529. <bitWidth>1</bitWidth>
  9530. <access>read-only</access>
  9531. </field>
  9532. </fields>
  9533. </register>
  9534. <register>
  9535. <name>DR</name>
  9536. <displayName>DR</displayName>
  9537. <description>data register</description>
  9538. <addressOffset>0xC</addressOffset>
  9539. <size>0x20</size>
  9540. <access>read-write</access>
  9541. <resetValue>0x0000</resetValue>
  9542. <fields>
  9543. <field>
  9544. <name>DR</name>
  9545. <description>Data register</description>
  9546. <bitOffset>0</bitOffset>
  9547. <bitWidth>16</bitWidth>
  9548. </field>
  9549. </fields>
  9550. </register>
  9551. <register>
  9552. <name>CRCPR</name>
  9553. <displayName>CRCPR</displayName>
  9554. <description>CRC polynomial register</description>
  9555. <addressOffset>0x10</addressOffset>
  9556. <size>0x20</size>
  9557. <access>read-write</access>
  9558. <resetValue>0x0007</resetValue>
  9559. <fields>
  9560. <field>
  9561. <name>CRCPOLY</name>
  9562. <description>CRC polynomial register</description>
  9563. <bitOffset>0</bitOffset>
  9564. <bitWidth>16</bitWidth>
  9565. </field>
  9566. </fields>
  9567. </register>
  9568. <register>
  9569. <name>RXCRCR</name>
  9570. <displayName>RXCRCR</displayName>
  9571. <description>RX CRC register</description>
  9572. <addressOffset>0x14</addressOffset>
  9573. <size>0x20</size>
  9574. <access>read-only</access>
  9575. <resetValue>0x0000</resetValue>
  9576. <fields>
  9577. <field>
  9578. <name>RxCRC</name>
  9579. <description>Rx CRC register</description>
  9580. <bitOffset>0</bitOffset>
  9581. <bitWidth>16</bitWidth>
  9582. </field>
  9583. </fields>
  9584. </register>
  9585. <register>
  9586. <name>TXCRCR</name>
  9587. <displayName>TXCRCR</displayName>
  9588. <description>TX CRC register</description>
  9589. <addressOffset>0x18</addressOffset>
  9590. <size>0x20</size>
  9591. <access>read-only</access>
  9592. <resetValue>0x0000</resetValue>
  9593. <fields>
  9594. <field>
  9595. <name>TxCRC</name>
  9596. <description>Tx CRC register</description>
  9597. <bitOffset>0</bitOffset>
  9598. <bitWidth>16</bitWidth>
  9599. </field>
  9600. </fields>
  9601. </register>
  9602. <register>
  9603. <name>I2SCFGR</name>
  9604. <displayName>I2SCFGR</displayName>
  9605. <description>I2S configuration register</description>
  9606. <addressOffset>0x1C</addressOffset>
  9607. <size>0x20</size>
  9608. <access>read-write</access>
  9609. <resetValue>0x0000</resetValue>
  9610. <fields>
  9611. <field>
  9612. <name>I2SMOD</name>
  9613. <description>I2S mode selection</description>
  9614. <bitOffset>11</bitOffset>
  9615. <bitWidth>1</bitWidth>
  9616. </field>
  9617. <field>
  9618. <name>I2SE</name>
  9619. <description>I2S Enable</description>
  9620. <bitOffset>10</bitOffset>
  9621. <bitWidth>1</bitWidth>
  9622. </field>
  9623. <field>
  9624. <name>I2SCFG</name>
  9625. <description>I2S configuration mode</description>
  9626. <bitOffset>8</bitOffset>
  9627. <bitWidth>2</bitWidth>
  9628. </field>
  9629. <field>
  9630. <name>PCMSYNC</name>
  9631. <description>PCM frame synchronization</description>
  9632. <bitOffset>7</bitOffset>
  9633. <bitWidth>1</bitWidth>
  9634. </field>
  9635. <field>
  9636. <name>I2SSTD</name>
  9637. <description>I2S standard selection</description>
  9638. <bitOffset>4</bitOffset>
  9639. <bitWidth>2</bitWidth>
  9640. </field>
  9641. <field>
  9642. <name>CKPOL</name>
  9643. <description>Steady state clock
  9644. polarity</description>
  9645. <bitOffset>3</bitOffset>
  9646. <bitWidth>1</bitWidth>
  9647. </field>
  9648. <field>
  9649. <name>DATLEN</name>
  9650. <description>Data length to be
  9651. transferred</description>
  9652. <bitOffset>1</bitOffset>
  9653. <bitWidth>2</bitWidth>
  9654. </field>
  9655. <field>
  9656. <name>CHLEN</name>
  9657. <description>Channel length (number of bits per audio
  9658. channel)</description>
  9659. <bitOffset>0</bitOffset>
  9660. <bitWidth>1</bitWidth>
  9661. </field>
  9662. </fields>
  9663. </register>
  9664. <register>
  9665. <name>I2SPR</name>
  9666. <displayName>I2SPR</displayName>
  9667. <description>I2S prescaler register</description>
  9668. <addressOffset>0x20</addressOffset>
  9669. <size>0x20</size>
  9670. <access>read-write</access>
  9671. <resetValue>0x00000010</resetValue>
  9672. <fields>
  9673. <field>
  9674. <name>MCKOE</name>
  9675. <description>Master clock output enable</description>
  9676. <bitOffset>9</bitOffset>
  9677. <bitWidth>1</bitWidth>
  9678. </field>
  9679. <field>
  9680. <name>ODD</name>
  9681. <description>Odd factor for the
  9682. prescaler</description>
  9683. <bitOffset>8</bitOffset>
  9684. <bitWidth>1</bitWidth>
  9685. </field>
  9686. <field>
  9687. <name>I2SDIV</name>
  9688. <description>I2S Linear prescaler</description>
  9689. <bitOffset>0</bitOffset>
  9690. <bitWidth>8</bitWidth>
  9691. </field>
  9692. </fields>
  9693. </register>
  9694. </registers>
  9695. </peripheral>
  9696. <peripheral derivedFrom="SPI1">
  9697. <name>SPI2</name>
  9698. <baseAddress>0x40003800</baseAddress>
  9699. <interrupt>
  9700. <name>SPI2</name>
  9701. <description>SPI2 global interrupt</description>
  9702. <value>26</value>
  9703. </interrupt>
  9704. </peripheral>
  9705. <peripheral>
  9706. <name>I2C1</name>
  9707. <description>Inter-integrated circuit</description>
  9708. <groupName>I2C</groupName>
  9709. <baseAddress>0x40005400</baseAddress>
  9710. <addressBlock>
  9711. <offset>0x0</offset>
  9712. <size>0x400</size>
  9713. <usage>registers</usage>
  9714. </addressBlock>
  9715. <interrupt>
  9716. <name>I2C1</name>
  9717. <description>I2C1 global interrupt</description>
  9718. <value>23</value>
  9719. </interrupt>
  9720. <registers>
  9721. <register>
  9722. <name>CR1</name>
  9723. <displayName>CR1</displayName>
  9724. <description>Control register 1</description>
  9725. <addressOffset>0x0</addressOffset>
  9726. <size>0x20</size>
  9727. <access>read-write</access>
  9728. <resetValue>0x00000000</resetValue>
  9729. <fields>
  9730. <field>
  9731. <name>PE</name>
  9732. <description>Peripheral enable</description>
  9733. <bitOffset>0</bitOffset>
  9734. <bitWidth>1</bitWidth>
  9735. </field>
  9736. <field>
  9737. <name>TXIE</name>
  9738. <description>TX Interrupt enable</description>
  9739. <bitOffset>1</bitOffset>
  9740. <bitWidth>1</bitWidth>
  9741. </field>
  9742. <field>
  9743. <name>RXIE</name>
  9744. <description>RX Interrupt enable</description>
  9745. <bitOffset>2</bitOffset>
  9746. <bitWidth>1</bitWidth>
  9747. </field>
  9748. <field>
  9749. <name>ADDRIE</name>
  9750. <description>Address match interrupt enable (slave
  9751. only)</description>
  9752. <bitOffset>3</bitOffset>
  9753. <bitWidth>1</bitWidth>
  9754. </field>
  9755. <field>
  9756. <name>NACKIE</name>
  9757. <description>Not acknowledge received interrupt
  9758. enable</description>
  9759. <bitOffset>4</bitOffset>
  9760. <bitWidth>1</bitWidth>
  9761. </field>
  9762. <field>
  9763. <name>STOPIE</name>
  9764. <description>STOP detection Interrupt
  9765. enable</description>
  9766. <bitOffset>5</bitOffset>
  9767. <bitWidth>1</bitWidth>
  9768. </field>
  9769. <field>
  9770. <name>TCIE</name>
  9771. <description>Transfer Complete interrupt
  9772. enable</description>
  9773. <bitOffset>6</bitOffset>
  9774. <bitWidth>1</bitWidth>
  9775. </field>
  9776. <field>
  9777. <name>ERRIE</name>
  9778. <description>Error interrupts enable</description>
  9779. <bitOffset>7</bitOffset>
  9780. <bitWidth>1</bitWidth>
  9781. </field>
  9782. <field>
  9783. <name>DNF</name>
  9784. <description>Digital noise filter</description>
  9785. <bitOffset>8</bitOffset>
  9786. <bitWidth>4</bitWidth>
  9787. </field>
  9788. <field>
  9789. <name>ANFOFF</name>
  9790. <description>Analog noise filter OFF</description>
  9791. <bitOffset>12</bitOffset>
  9792. <bitWidth>1</bitWidth>
  9793. </field>
  9794. <field>
  9795. <name>TXDMAEN</name>
  9796. <description>DMA transmission requests
  9797. enable</description>
  9798. <bitOffset>14</bitOffset>
  9799. <bitWidth>1</bitWidth>
  9800. </field>
  9801. <field>
  9802. <name>RXDMAEN</name>
  9803. <description>DMA reception requests
  9804. enable</description>
  9805. <bitOffset>15</bitOffset>
  9806. <bitWidth>1</bitWidth>
  9807. </field>
  9808. <field>
  9809. <name>SBC</name>
  9810. <description>Slave byte control</description>
  9811. <bitOffset>16</bitOffset>
  9812. <bitWidth>1</bitWidth>
  9813. </field>
  9814. <field>
  9815. <name>NOSTRETCH</name>
  9816. <description>Clock stretching disable</description>
  9817. <bitOffset>17</bitOffset>
  9818. <bitWidth>1</bitWidth>
  9819. </field>
  9820. <field>
  9821. <name>WUPEN</name>
  9822. <description>Wakeup from STOP enable</description>
  9823. <bitOffset>18</bitOffset>
  9824. <bitWidth>1</bitWidth>
  9825. </field>
  9826. <field>
  9827. <name>GCEN</name>
  9828. <description>General call enable</description>
  9829. <bitOffset>19</bitOffset>
  9830. <bitWidth>1</bitWidth>
  9831. </field>
  9832. <field>
  9833. <name>SMBHEN</name>
  9834. <description>SMBus Host address enable</description>
  9835. <bitOffset>20</bitOffset>
  9836. <bitWidth>1</bitWidth>
  9837. </field>
  9838. <field>
  9839. <name>SMBDEN</name>
  9840. <description>SMBus Device Default address
  9841. enable</description>
  9842. <bitOffset>21</bitOffset>
  9843. <bitWidth>1</bitWidth>
  9844. </field>
  9845. <field>
  9846. <name>ALERTEN</name>
  9847. <description>SMBUS alert enable</description>
  9848. <bitOffset>22</bitOffset>
  9849. <bitWidth>1</bitWidth>
  9850. </field>
  9851. <field>
  9852. <name>PECEN</name>
  9853. <description>PEC enable</description>
  9854. <bitOffset>23</bitOffset>
  9855. <bitWidth>1</bitWidth>
  9856. </field>
  9857. </fields>
  9858. </register>
  9859. <register>
  9860. <name>CR2</name>
  9861. <displayName>CR2</displayName>
  9862. <description>Control register 2</description>
  9863. <addressOffset>0x4</addressOffset>
  9864. <size>0x20</size>
  9865. <access>read-write</access>
  9866. <resetValue>0x00000000</resetValue>
  9867. <fields>
  9868. <field>
  9869. <name>PECBYTE</name>
  9870. <description>Packet error checking byte</description>
  9871. <bitOffset>26</bitOffset>
  9872. <bitWidth>1</bitWidth>
  9873. </field>
  9874. <field>
  9875. <name>AUTOEND</name>
  9876. <description>Automatic end mode (master
  9877. mode)</description>
  9878. <bitOffset>25</bitOffset>
  9879. <bitWidth>1</bitWidth>
  9880. </field>
  9881. <field>
  9882. <name>RELOAD</name>
  9883. <description>NBYTES reload mode</description>
  9884. <bitOffset>24</bitOffset>
  9885. <bitWidth>1</bitWidth>
  9886. </field>
  9887. <field>
  9888. <name>NBYTES</name>
  9889. <description>Number of bytes</description>
  9890. <bitOffset>16</bitOffset>
  9891. <bitWidth>8</bitWidth>
  9892. </field>
  9893. <field>
  9894. <name>NACK</name>
  9895. <description>NACK generation (slave
  9896. mode)</description>
  9897. <bitOffset>15</bitOffset>
  9898. <bitWidth>1</bitWidth>
  9899. </field>
  9900. <field>
  9901. <name>STOP</name>
  9902. <description>Stop generation (master
  9903. mode)</description>
  9904. <bitOffset>14</bitOffset>
  9905. <bitWidth>1</bitWidth>
  9906. </field>
  9907. <field>
  9908. <name>START</name>
  9909. <description>Start generation</description>
  9910. <bitOffset>13</bitOffset>
  9911. <bitWidth>1</bitWidth>
  9912. </field>
  9913. <field>
  9914. <name>HEAD10R</name>
  9915. <description>10-bit address header only read
  9916. direction (master receiver mode)</description>
  9917. <bitOffset>12</bitOffset>
  9918. <bitWidth>1</bitWidth>
  9919. </field>
  9920. <field>
  9921. <name>ADD10</name>
  9922. <description>10-bit addressing mode (master
  9923. mode)</description>
  9924. <bitOffset>11</bitOffset>
  9925. <bitWidth>1</bitWidth>
  9926. </field>
  9927. <field>
  9928. <name>RD_WRN</name>
  9929. <description>Transfer direction (master
  9930. mode)</description>
  9931. <bitOffset>10</bitOffset>
  9932. <bitWidth>1</bitWidth>
  9933. </field>
  9934. <field>
  9935. <name>SADD</name>
  9936. <description>Slave address bit (master
  9937. mode)</description>
  9938. <bitOffset>0</bitOffset>
  9939. <bitWidth>10</bitWidth>
  9940. </field>
  9941. </fields>
  9942. </register>
  9943. <register>
  9944. <name>OAR1</name>
  9945. <displayName>OAR1</displayName>
  9946. <description>Own address register 1</description>
  9947. <addressOffset>0x8</addressOffset>
  9948. <size>0x20</size>
  9949. <access>read-write</access>
  9950. <resetValue>0x00000000</resetValue>
  9951. <fields>
  9952. <field>
  9953. <name>OA1</name>
  9954. <description>Interface address</description>
  9955. <bitOffset>0</bitOffset>
  9956. <bitWidth>10</bitWidth>
  9957. </field>
  9958. <field>
  9959. <name>OA1MODE</name>
  9960. <description>Own Address 1 10-bit mode</description>
  9961. <bitOffset>10</bitOffset>
  9962. <bitWidth>1</bitWidth>
  9963. </field>
  9964. <field>
  9965. <name>OA1EN</name>
  9966. <description>Own Address 1 enable</description>
  9967. <bitOffset>15</bitOffset>
  9968. <bitWidth>1</bitWidth>
  9969. </field>
  9970. </fields>
  9971. </register>
  9972. <register>
  9973. <name>OAR2</name>
  9974. <displayName>OAR2</displayName>
  9975. <description>Own address register 2</description>
  9976. <addressOffset>0xC</addressOffset>
  9977. <size>0x20</size>
  9978. <access>read-write</access>
  9979. <resetValue>0x00000000</resetValue>
  9980. <fields>
  9981. <field>
  9982. <name>OA2</name>
  9983. <description>Interface address</description>
  9984. <bitOffset>1</bitOffset>
  9985. <bitWidth>7</bitWidth>
  9986. </field>
  9987. <field>
  9988. <name>OA2MSK</name>
  9989. <description>Own Address 2 masks</description>
  9990. <bitOffset>8</bitOffset>
  9991. <bitWidth>3</bitWidth>
  9992. </field>
  9993. <field>
  9994. <name>OA2EN</name>
  9995. <description>Own Address 2 enable</description>
  9996. <bitOffset>15</bitOffset>
  9997. <bitWidth>1</bitWidth>
  9998. </field>
  9999. </fields>
  10000. </register>
  10001. <register>
  10002. <name>TIMINGR</name>
  10003. <displayName>TIMINGR</displayName>
  10004. <description>Timing register</description>
  10005. <addressOffset>0x10</addressOffset>
  10006. <size>0x20</size>
  10007. <access>read-write</access>
  10008. <resetValue>0x00000000</resetValue>
  10009. <fields>
  10010. <field>
  10011. <name>SCLL</name>
  10012. <description>SCL low period (master
  10013. mode)</description>
  10014. <bitOffset>0</bitOffset>
  10015. <bitWidth>8</bitWidth>
  10016. </field>
  10017. <field>
  10018. <name>SCLH</name>
  10019. <description>SCL high period (master
  10020. mode)</description>
  10021. <bitOffset>8</bitOffset>
  10022. <bitWidth>8</bitWidth>
  10023. </field>
  10024. <field>
  10025. <name>SDADEL</name>
  10026. <description>Data hold time</description>
  10027. <bitOffset>16</bitOffset>
  10028. <bitWidth>4</bitWidth>
  10029. </field>
  10030. <field>
  10031. <name>SCLDEL</name>
  10032. <description>Data setup time</description>
  10033. <bitOffset>20</bitOffset>
  10034. <bitWidth>4</bitWidth>
  10035. </field>
  10036. <field>
  10037. <name>PRESC</name>
  10038. <description>Timing prescaler</description>
  10039. <bitOffset>28</bitOffset>
  10040. <bitWidth>4</bitWidth>
  10041. </field>
  10042. </fields>
  10043. </register>
  10044. <register>
  10045. <name>TIMEOUTR</name>
  10046. <displayName>TIMEOUTR</displayName>
  10047. <description>Status register 1</description>
  10048. <addressOffset>0x14</addressOffset>
  10049. <size>0x20</size>
  10050. <access>read-write</access>
  10051. <resetValue>0x00000000</resetValue>
  10052. <fields>
  10053. <field>
  10054. <name>TIMEOUTA</name>
  10055. <description>Bus timeout A</description>
  10056. <bitOffset>0</bitOffset>
  10057. <bitWidth>12</bitWidth>
  10058. </field>
  10059. <field>
  10060. <name>TIDLE</name>
  10061. <description>Idle clock timeout
  10062. detection</description>
  10063. <bitOffset>12</bitOffset>
  10064. <bitWidth>1</bitWidth>
  10065. </field>
  10066. <field>
  10067. <name>TIMOUTEN</name>
  10068. <description>Clock timeout enable</description>
  10069. <bitOffset>15</bitOffset>
  10070. <bitWidth>1</bitWidth>
  10071. </field>
  10072. <field>
  10073. <name>TIMEOUTB</name>
  10074. <description>Bus timeout B</description>
  10075. <bitOffset>16</bitOffset>
  10076. <bitWidth>12</bitWidth>
  10077. </field>
  10078. <field>
  10079. <name>TEXTEN</name>
  10080. <description>Extended clock timeout
  10081. enable</description>
  10082. <bitOffset>31</bitOffset>
  10083. <bitWidth>1</bitWidth>
  10084. </field>
  10085. </fields>
  10086. </register>
  10087. <register>
  10088. <name>ISR</name>
  10089. <displayName>ISR</displayName>
  10090. <description>Interrupt and Status register</description>
  10091. <addressOffset>0x18</addressOffset>
  10092. <size>0x20</size>
  10093. <resetValue>0x00000001</resetValue>
  10094. <fields>
  10095. <field>
  10096. <name>ADDCODE</name>
  10097. <description>Address match code (Slave
  10098. mode)</description>
  10099. <bitOffset>17</bitOffset>
  10100. <bitWidth>7</bitWidth>
  10101. <access>read-only</access>
  10102. </field>
  10103. <field>
  10104. <name>DIR</name>
  10105. <description>Transfer direction (Slave
  10106. mode)</description>
  10107. <bitOffset>16</bitOffset>
  10108. <bitWidth>1</bitWidth>
  10109. <access>read-only</access>
  10110. </field>
  10111. <field>
  10112. <name>BUSY</name>
  10113. <description>Bus busy</description>
  10114. <bitOffset>15</bitOffset>
  10115. <bitWidth>1</bitWidth>
  10116. <access>read-only</access>
  10117. </field>
  10118. <field>
  10119. <name>ALERT</name>
  10120. <description>SMBus alert</description>
  10121. <bitOffset>13</bitOffset>
  10122. <bitWidth>1</bitWidth>
  10123. <access>read-only</access>
  10124. </field>
  10125. <field>
  10126. <name>TIMEOUT</name>
  10127. <description>Timeout or t_low detection
  10128. flag</description>
  10129. <bitOffset>12</bitOffset>
  10130. <bitWidth>1</bitWidth>
  10131. <access>read-only</access>
  10132. </field>
  10133. <field>
  10134. <name>PECERR</name>
  10135. <description>PEC Error in reception</description>
  10136. <bitOffset>11</bitOffset>
  10137. <bitWidth>1</bitWidth>
  10138. <access>read-only</access>
  10139. </field>
  10140. <field>
  10141. <name>OVR</name>
  10142. <description>Overrun/Underrun (slave
  10143. mode)</description>
  10144. <bitOffset>10</bitOffset>
  10145. <bitWidth>1</bitWidth>
  10146. <access>read-only</access>
  10147. </field>
  10148. <field>
  10149. <name>ARLO</name>
  10150. <description>Arbitration lost</description>
  10151. <bitOffset>9</bitOffset>
  10152. <bitWidth>1</bitWidth>
  10153. <access>read-only</access>
  10154. </field>
  10155. <field>
  10156. <name>BERR</name>
  10157. <description>Bus error</description>
  10158. <bitOffset>8</bitOffset>
  10159. <bitWidth>1</bitWidth>
  10160. <access>read-only</access>
  10161. </field>
  10162. <field>
  10163. <name>TCR</name>
  10164. <description>Transfer Complete Reload</description>
  10165. <bitOffset>7</bitOffset>
  10166. <bitWidth>1</bitWidth>
  10167. <access>read-only</access>
  10168. </field>
  10169. <field>
  10170. <name>TC</name>
  10171. <description>Transfer Complete (master
  10172. mode)</description>
  10173. <bitOffset>6</bitOffset>
  10174. <bitWidth>1</bitWidth>
  10175. <access>read-only</access>
  10176. </field>
  10177. <field>
  10178. <name>STOPF</name>
  10179. <description>Stop detection flag</description>
  10180. <bitOffset>5</bitOffset>
  10181. <bitWidth>1</bitWidth>
  10182. <access>read-only</access>
  10183. </field>
  10184. <field>
  10185. <name>NACKF</name>
  10186. <description>Not acknowledge received
  10187. flag</description>
  10188. <bitOffset>4</bitOffset>
  10189. <bitWidth>1</bitWidth>
  10190. <access>read-only</access>
  10191. </field>
  10192. <field>
  10193. <name>ADDR</name>
  10194. <description>Address matched (slave
  10195. mode)</description>
  10196. <bitOffset>3</bitOffset>
  10197. <bitWidth>1</bitWidth>
  10198. <access>read-only</access>
  10199. </field>
  10200. <field>
  10201. <name>RXNE</name>
  10202. <description>Receive data register not empty
  10203. (receivers)</description>
  10204. <bitOffset>2</bitOffset>
  10205. <bitWidth>1</bitWidth>
  10206. <access>read-only</access>
  10207. </field>
  10208. <field>
  10209. <name>TXIS</name>
  10210. <description>Transmit interrupt status
  10211. (transmitters)</description>
  10212. <bitOffset>1</bitOffset>
  10213. <bitWidth>1</bitWidth>
  10214. <access>read-write</access>
  10215. </field>
  10216. <field>
  10217. <name>TXE</name>
  10218. <description>Transmit data register empty
  10219. (transmitters)</description>
  10220. <bitOffset>0</bitOffset>
  10221. <bitWidth>1</bitWidth>
  10222. <access>read-write</access>
  10223. </field>
  10224. </fields>
  10225. </register>
  10226. <register>
  10227. <name>ICR</name>
  10228. <displayName>ICR</displayName>
  10229. <description>Interrupt clear register</description>
  10230. <addressOffset>0x1C</addressOffset>
  10231. <size>0x20</size>
  10232. <access>write-only</access>
  10233. <resetValue>0x00000000</resetValue>
  10234. <fields>
  10235. <field>
  10236. <name>ALERTCF</name>
  10237. <description>Alert flag clear</description>
  10238. <bitOffset>13</bitOffset>
  10239. <bitWidth>1</bitWidth>
  10240. </field>
  10241. <field>
  10242. <name>TIMOUTCF</name>
  10243. <description>Timeout detection flag
  10244. clear</description>
  10245. <bitOffset>12</bitOffset>
  10246. <bitWidth>1</bitWidth>
  10247. </field>
  10248. <field>
  10249. <name>PECCF</name>
  10250. <description>PEC Error flag clear</description>
  10251. <bitOffset>11</bitOffset>
  10252. <bitWidth>1</bitWidth>
  10253. </field>
  10254. <field>
  10255. <name>OVRCF</name>
  10256. <description>Overrun/Underrun flag
  10257. clear</description>
  10258. <bitOffset>10</bitOffset>
  10259. <bitWidth>1</bitWidth>
  10260. </field>
  10261. <field>
  10262. <name>ARLOCF</name>
  10263. <description>Arbitration lost flag
  10264. clear</description>
  10265. <bitOffset>9</bitOffset>
  10266. <bitWidth>1</bitWidth>
  10267. </field>
  10268. <field>
  10269. <name>BERRCF</name>
  10270. <description>Bus error flag clear</description>
  10271. <bitOffset>8</bitOffset>
  10272. <bitWidth>1</bitWidth>
  10273. </field>
  10274. <field>
  10275. <name>STOPCF</name>
  10276. <description>Stop detection flag clear</description>
  10277. <bitOffset>5</bitOffset>
  10278. <bitWidth>1</bitWidth>
  10279. </field>
  10280. <field>
  10281. <name>NACKCF</name>
  10282. <description>Not Acknowledge flag clear</description>
  10283. <bitOffset>4</bitOffset>
  10284. <bitWidth>1</bitWidth>
  10285. </field>
  10286. <field>
  10287. <name>ADDRCF</name>
  10288. <description>Address Matched flag clear</description>
  10289. <bitOffset>3</bitOffset>
  10290. <bitWidth>1</bitWidth>
  10291. </field>
  10292. </fields>
  10293. </register>
  10294. <register>
  10295. <name>PECR</name>
  10296. <displayName>PECR</displayName>
  10297. <description>PEC register</description>
  10298. <addressOffset>0x20</addressOffset>
  10299. <size>0x20</size>
  10300. <access>read-only</access>
  10301. <resetValue>0x00000000</resetValue>
  10302. <fields>
  10303. <field>
  10304. <name>PEC</name>
  10305. <description>Packet error checking
  10306. register</description>
  10307. <bitOffset>0</bitOffset>
  10308. <bitWidth>8</bitWidth>
  10309. </field>
  10310. </fields>
  10311. </register>
  10312. <register>
  10313. <name>RXDR</name>
  10314. <displayName>RXDR</displayName>
  10315. <description>Receive data register</description>
  10316. <addressOffset>0x24</addressOffset>
  10317. <size>0x20</size>
  10318. <access>read-only</access>
  10319. <resetValue>0x00000000</resetValue>
  10320. <fields>
  10321. <field>
  10322. <name>RXDATA</name>
  10323. <description>8-bit receive data</description>
  10324. <bitOffset>0</bitOffset>
  10325. <bitWidth>8</bitWidth>
  10326. </field>
  10327. </fields>
  10328. </register>
  10329. <register>
  10330. <name>TXDR</name>
  10331. <displayName>TXDR</displayName>
  10332. <description>Transmit data register</description>
  10333. <addressOffset>0x28</addressOffset>
  10334. <size>0x20</size>
  10335. <access>read-write</access>
  10336. <resetValue>0x00000000</resetValue>
  10337. <fields>
  10338. <field>
  10339. <name>TXDATA</name>
  10340. <description>8-bit transmit data</description>
  10341. <bitOffset>0</bitOffset>
  10342. <bitWidth>8</bitWidth>
  10343. </field>
  10344. </fields>
  10345. </register>
  10346. </registers>
  10347. </peripheral>
  10348. <peripheral derivedFrom="I2C1">
  10349. <name>I2C2</name>
  10350. <baseAddress>0x40005800</baseAddress>
  10351. <interrupt>
  10352. <name>I2C2</name>
  10353. <description>I2C2 global interrupt</description>
  10354. <value>24</value>
  10355. </interrupt>
  10356. </peripheral>
  10357. <peripheral derivedFrom="I2C1">
  10358. <name>I2C3</name>
  10359. <baseAddress>0x40007800</baseAddress>
  10360. </peripheral>
  10361. <peripheral>
  10362. <name>PWR</name>
  10363. <description>Power control</description>
  10364. <groupName>PWR</groupName>
  10365. <baseAddress>0x40007000</baseAddress>
  10366. <addressBlock>
  10367. <offset>0x0</offset>
  10368. <size>0x400</size>
  10369. <usage>registers</usage>
  10370. </addressBlock>
  10371. <registers>
  10372. <register>
  10373. <name>CR</name>
  10374. <displayName>CR</displayName>
  10375. <description>power control register</description>
  10376. <addressOffset>0x0</addressOffset>
  10377. <size>0x20</size>
  10378. <access>read-write</access>
  10379. <resetValue>0x00001000</resetValue>
  10380. <fields>
  10381. <field>
  10382. <name>LPDS</name>
  10383. <description>Low-power deep sleep</description>
  10384. <bitOffset>0</bitOffset>
  10385. <bitWidth>1</bitWidth>
  10386. </field>
  10387. <field>
  10388. <name>PDDS</name>
  10389. <description>Power down deepsleep</description>
  10390. <bitOffset>1</bitOffset>
  10391. <bitWidth>1</bitWidth>
  10392. </field>
  10393. <field>
  10394. <name>CWUF</name>
  10395. <description>Clear wakeup flag</description>
  10396. <bitOffset>2</bitOffset>
  10397. <bitWidth>1</bitWidth>
  10398. </field>
  10399. <field>
  10400. <name>CSBF</name>
  10401. <description>Clear standby flag</description>
  10402. <bitOffset>3</bitOffset>
  10403. <bitWidth>1</bitWidth>
  10404. </field>
  10405. <field>
  10406. <name>PVDE</name>
  10407. <description>Power voltage detector
  10408. enable</description>
  10409. <bitOffset>4</bitOffset>
  10410. <bitWidth>1</bitWidth>
  10411. </field>
  10412. <field>
  10413. <name>PLS</name>
  10414. <description>PVD level selection</description>
  10415. <bitOffset>5</bitOffset>
  10416. <bitWidth>3</bitWidth>
  10417. </field>
  10418. <field>
  10419. <name>DBP</name>
  10420. <description>Disable backup domain write
  10421. protection</description>
  10422. <bitOffset>8</bitOffset>
  10423. <bitWidth>1</bitWidth>
  10424. </field>
  10425. <field>
  10426. <name>ULP</name>
  10427. <description>Ultra-low-power mode</description>
  10428. <bitOffset>9</bitOffset>
  10429. <bitWidth>1</bitWidth>
  10430. </field>
  10431. <field>
  10432. <name>FWU</name>
  10433. <description>Fast wakeup</description>
  10434. <bitOffset>10</bitOffset>
  10435. <bitWidth>1</bitWidth>
  10436. </field>
  10437. <field>
  10438. <name>VOS</name>
  10439. <description>Voltage scaling range
  10440. selection</description>
  10441. <bitOffset>11</bitOffset>
  10442. <bitWidth>2</bitWidth>
  10443. </field>
  10444. <field>
  10445. <name>DS_EE_KOFF</name>
  10446. <description>Deep sleep mode with Flash memory kept
  10447. off</description>
  10448. <bitOffset>13</bitOffset>
  10449. <bitWidth>1</bitWidth>
  10450. </field>
  10451. <field>
  10452. <name>LPRUN</name>
  10453. <description>Low power run mode</description>
  10454. <bitOffset>14</bitOffset>
  10455. <bitWidth>1</bitWidth>
  10456. </field>
  10457. </fields>
  10458. </register>
  10459. <register>
  10460. <name>CSR</name>
  10461. <displayName>CSR</displayName>
  10462. <description>power control/status register</description>
  10463. <addressOffset>0x4</addressOffset>
  10464. <size>0x20</size>
  10465. <resetValue>0x00000000</resetValue>
  10466. <fields>
  10467. <field>
  10468. <name>BRE</name>
  10469. <description>Backup regulator enable</description>
  10470. <bitOffset>9</bitOffset>
  10471. <bitWidth>1</bitWidth>
  10472. <access>read-write</access>
  10473. </field>
  10474. <field>
  10475. <name>EWUP</name>
  10476. <description>Enable WKUP pin</description>
  10477. <bitOffset>8</bitOffset>
  10478. <bitWidth>1</bitWidth>
  10479. <access>read-write</access>
  10480. </field>
  10481. <field>
  10482. <name>BRR</name>
  10483. <description>Backup regulator ready</description>
  10484. <bitOffset>3</bitOffset>
  10485. <bitWidth>1</bitWidth>
  10486. <access>read-only</access>
  10487. </field>
  10488. <field>
  10489. <name>PVDO</name>
  10490. <description>PVD output</description>
  10491. <bitOffset>2</bitOffset>
  10492. <bitWidth>1</bitWidth>
  10493. <access>read-only</access>
  10494. </field>
  10495. <field>
  10496. <name>SBF</name>
  10497. <description>Standby flag</description>
  10498. <bitOffset>1</bitOffset>
  10499. <bitWidth>1</bitWidth>
  10500. <access>read-only</access>
  10501. </field>
  10502. <field>
  10503. <name>WUF</name>
  10504. <description>Wakeup flag</description>
  10505. <bitOffset>0</bitOffset>
  10506. <bitWidth>1</bitWidth>
  10507. <access>read-only</access>
  10508. </field>
  10509. <field>
  10510. <name>VOSF</name>
  10511. <description>Voltage Scaling select
  10512. flag</description>
  10513. <bitOffset>4</bitOffset>
  10514. <bitWidth>1</bitWidth>
  10515. <access>read-only</access>
  10516. </field>
  10517. <field>
  10518. <name>REGLPF</name>
  10519. <description>Regulator LP flag</description>
  10520. <bitOffset>5</bitOffset>
  10521. <bitWidth>1</bitWidth>
  10522. <access>read-only</access>
  10523. </field>
  10524. </fields>
  10525. </register>
  10526. </registers>
  10527. </peripheral>
  10528. <peripheral>
  10529. <name>Flash</name>
  10530. <description>Flash</description>
  10531. <groupName>Flash</groupName>
  10532. <baseAddress>0x40022000</baseAddress>
  10533. <addressBlock>
  10534. <offset>0x0</offset>
  10535. <size>0x400</size>
  10536. <usage>registers</usage>
  10537. </addressBlock>
  10538. <interrupt>
  10539. <name>FLASH</name>
  10540. <description>Flash global interrupt</description>
  10541. <value>3</value>
  10542. </interrupt>
  10543. <registers>
  10544. <register>
  10545. <name>ACR</name>
  10546. <displayName>ACR</displayName>
  10547. <description>Access control register</description>
  10548. <addressOffset>0x0</addressOffset>
  10549. <size>0x20</size>
  10550. <access>read-write</access>
  10551. <resetValue>0x00000000</resetValue>
  10552. <fields>
  10553. <field>
  10554. <name>LATENCY</name>
  10555. <description>Latency</description>
  10556. <bitOffset>0</bitOffset>
  10557. <bitWidth>1</bitWidth>
  10558. </field>
  10559. <field>
  10560. <name>PRFTEN</name>
  10561. <description>Prefetch enable</description>
  10562. <bitOffset>1</bitOffset>
  10563. <bitWidth>1</bitWidth>
  10564. </field>
  10565. <field>
  10566. <name>SLEEP_PD</name>
  10567. <description>Flash mode during Sleep</description>
  10568. <bitOffset>3</bitOffset>
  10569. <bitWidth>1</bitWidth>
  10570. </field>
  10571. <field>
  10572. <name>RUN_PD</name>
  10573. <description>Flash mode during Run</description>
  10574. <bitOffset>4</bitOffset>
  10575. <bitWidth>1</bitWidth>
  10576. </field>
  10577. <field>
  10578. <name>DESAB_BUF</name>
  10579. <description>Disable Buffer</description>
  10580. <bitOffset>5</bitOffset>
  10581. <bitWidth>1</bitWidth>
  10582. </field>
  10583. <field>
  10584. <name>PRE_READ</name>
  10585. <description>Pre-read data address</description>
  10586. <bitOffset>6</bitOffset>
  10587. <bitWidth>1</bitWidth>
  10588. </field>
  10589. </fields>
  10590. </register>
  10591. <register>
  10592. <name>PECR</name>
  10593. <displayName>PECR</displayName>
  10594. <description>Program/erase control register</description>
  10595. <addressOffset>0x4</addressOffset>
  10596. <size>0x20</size>
  10597. <access>read-write</access>
  10598. <resetValue>0x00000007</resetValue>
  10599. <fields>
  10600. <field>
  10601. <name>PELOCK</name>
  10602. <description>FLASH_PECR and data EEPROM
  10603. lock</description>
  10604. <bitOffset>0</bitOffset>
  10605. <bitWidth>1</bitWidth>
  10606. </field>
  10607. <field>
  10608. <name>PRGLOCK</name>
  10609. <description>Program memory lock</description>
  10610. <bitOffset>1</bitOffset>
  10611. <bitWidth>1</bitWidth>
  10612. </field>
  10613. <field>
  10614. <name>OPTLOCK</name>
  10615. <description>Option bytes block lock</description>
  10616. <bitOffset>2</bitOffset>
  10617. <bitWidth>1</bitWidth>
  10618. </field>
  10619. <field>
  10620. <name>PROG</name>
  10621. <description>Program memory selection</description>
  10622. <bitOffset>3</bitOffset>
  10623. <bitWidth>1</bitWidth>
  10624. </field>
  10625. <field>
  10626. <name>DATA</name>
  10627. <description>Data EEPROM selection</description>
  10628. <bitOffset>4</bitOffset>
  10629. <bitWidth>1</bitWidth>
  10630. </field>
  10631. <field>
  10632. <name>FTDW</name>
  10633. <description>Fixed time data write for Byte, Half
  10634. Word and Word programming</description>
  10635. <bitOffset>8</bitOffset>
  10636. <bitWidth>1</bitWidth>
  10637. </field>
  10638. <field>
  10639. <name>ERASE</name>
  10640. <description>Page or Double Word erase
  10641. mode</description>
  10642. <bitOffset>9</bitOffset>
  10643. <bitWidth>1</bitWidth>
  10644. </field>
  10645. <field>
  10646. <name>FPRG</name>
  10647. <description>Half Page/Double Word programming
  10648. mode</description>
  10649. <bitOffset>10</bitOffset>
  10650. <bitWidth>1</bitWidth>
  10651. </field>
  10652. <field>
  10653. <name>PARALLELBANK</name>
  10654. <description>Parallel bank mode</description>
  10655. <bitOffset>15</bitOffset>
  10656. <bitWidth>1</bitWidth>
  10657. </field>
  10658. <field>
  10659. <name>EOPIE</name>
  10660. <description>End of programming interrupt
  10661. enable</description>
  10662. <bitOffset>16</bitOffset>
  10663. <bitWidth>1</bitWidth>
  10664. </field>
  10665. <field>
  10666. <name>ERRIE</name>
  10667. <description>Error interrupt enable</description>
  10668. <bitOffset>17</bitOffset>
  10669. <bitWidth>1</bitWidth>
  10670. </field>
  10671. <field>
  10672. <name>OBL_LAUNCH</name>
  10673. <description>Launch the option byte
  10674. loading</description>
  10675. <bitOffset>18</bitOffset>
  10676. <bitWidth>1</bitWidth>
  10677. </field>
  10678. </fields>
  10679. </register>
  10680. <register>
  10681. <name>PDKEYR</name>
  10682. <displayName>PDKEYR</displayName>
  10683. <description>Power down key register</description>
  10684. <addressOffset>0x8</addressOffset>
  10685. <size>0x20</size>
  10686. <access>write-only</access>
  10687. <resetValue>0x00000000</resetValue>
  10688. <fields>
  10689. <field>
  10690. <name>PDKEYR</name>
  10691. <description>RUN_PD in FLASH_ACR key</description>
  10692. <bitOffset>0</bitOffset>
  10693. <bitWidth>32</bitWidth>
  10694. </field>
  10695. </fields>
  10696. </register>
  10697. <register>
  10698. <name>PEKEYR</name>
  10699. <displayName>PEKEYR</displayName>
  10700. <description>Program/erase key register</description>
  10701. <addressOffset>0xC</addressOffset>
  10702. <size>0x20</size>
  10703. <access>write-only</access>
  10704. <resetValue>0x00000000</resetValue>
  10705. <fields>
  10706. <field>
  10707. <name>PEKEYR</name>
  10708. <description>FLASH_PEC and data EEPROM
  10709. key</description>
  10710. <bitOffset>0</bitOffset>
  10711. <bitWidth>32</bitWidth>
  10712. </field>
  10713. </fields>
  10714. </register>
  10715. <register>
  10716. <name>PRGKEYR</name>
  10717. <displayName>PRGKEYR</displayName>
  10718. <description>Program memory key register</description>
  10719. <addressOffset>0x10</addressOffset>
  10720. <size>0x20</size>
  10721. <access>write-only</access>
  10722. <resetValue>0x00000000</resetValue>
  10723. <fields>
  10724. <field>
  10725. <name>PRGKEYR</name>
  10726. <description>Program memory key</description>
  10727. <bitOffset>0</bitOffset>
  10728. <bitWidth>32</bitWidth>
  10729. </field>
  10730. </fields>
  10731. </register>
  10732. <register>
  10733. <name>OPTKEYR</name>
  10734. <displayName>OPTKEYR</displayName>
  10735. <description>Option byte key register</description>
  10736. <addressOffset>0x14</addressOffset>
  10737. <size>0x20</size>
  10738. <access>write-only</access>
  10739. <resetValue>0x00000000</resetValue>
  10740. <fields>
  10741. <field>
  10742. <name>OPTKEYR</name>
  10743. <description>Option byte key</description>
  10744. <bitOffset>0</bitOffset>
  10745. <bitWidth>32</bitWidth>
  10746. </field>
  10747. </fields>
  10748. </register>
  10749. <register>
  10750. <name>SR</name>
  10751. <displayName>SR</displayName>
  10752. <description>Status register</description>
  10753. <addressOffset>0x18</addressOffset>
  10754. <size>0x20</size>
  10755. <resetValue>0x00000004</resetValue>
  10756. <fields>
  10757. <field>
  10758. <name>BSY</name>
  10759. <description>Write/erase operations in
  10760. progress</description>
  10761. <bitOffset>0</bitOffset>
  10762. <bitWidth>1</bitWidth>
  10763. <access>read-only</access>
  10764. </field>
  10765. <field>
  10766. <name>EOP</name>
  10767. <description>End of operation</description>
  10768. <bitOffset>1</bitOffset>
  10769. <bitWidth>1</bitWidth>
  10770. <access>read-only</access>
  10771. </field>
  10772. <field>
  10773. <name>ENDHV</name>
  10774. <description>End of high voltage</description>
  10775. <bitOffset>2</bitOffset>
  10776. <bitWidth>1</bitWidth>
  10777. <access>read-only</access>
  10778. </field>
  10779. <field>
  10780. <name>READY</name>
  10781. <description>Flash memory module ready after low
  10782. power mode</description>
  10783. <bitOffset>3</bitOffset>
  10784. <bitWidth>1</bitWidth>
  10785. <access>read-only</access>
  10786. </field>
  10787. <field>
  10788. <name>WRPERR</name>
  10789. <description>Write protected error</description>
  10790. <bitOffset>8</bitOffset>
  10791. <bitWidth>1</bitWidth>
  10792. <access>read-write</access>
  10793. </field>
  10794. <field>
  10795. <name>PGAERR</name>
  10796. <description>Programming alignment
  10797. error</description>
  10798. <bitOffset>9</bitOffset>
  10799. <bitWidth>1</bitWidth>
  10800. <access>read-write</access>
  10801. </field>
  10802. <field>
  10803. <name>SIZERR</name>
  10804. <description>Size error</description>
  10805. <bitOffset>10</bitOffset>
  10806. <bitWidth>1</bitWidth>
  10807. <access>read-write</access>
  10808. </field>
  10809. <field>
  10810. <name>OPTVERR</name>
  10811. <description>Option validity error</description>
  10812. <bitOffset>11</bitOffset>
  10813. <bitWidth>1</bitWidth>
  10814. <access>read-write</access>
  10815. </field>
  10816. <field>
  10817. <name>RDERR</name>
  10818. <description>RDERR</description>
  10819. <bitOffset>14</bitOffset>
  10820. <bitWidth>1</bitWidth>
  10821. <access>read-write</access>
  10822. </field>
  10823. <field>
  10824. <name>NOTZEROERR</name>
  10825. <description>NOTZEROERR</description>
  10826. <bitOffset>16</bitOffset>
  10827. <bitWidth>1</bitWidth>
  10828. <access>read-write</access>
  10829. </field>
  10830. <field>
  10831. <name>FWWERR</name>
  10832. <description>FWWERR</description>
  10833. <bitOffset>17</bitOffset>
  10834. <bitWidth>1</bitWidth>
  10835. <access>read-write</access>
  10836. </field>
  10837. </fields>
  10838. </register>
  10839. <register>
  10840. <name>OBR</name>
  10841. <displayName>OBR</displayName>
  10842. <description>Option byte register</description>
  10843. <addressOffset>0x1C</addressOffset>
  10844. <size>0x20</size>
  10845. <access>read-only</access>
  10846. <resetValue>0x00F80000</resetValue>
  10847. <fields>
  10848. <field>
  10849. <name>RDPRT</name>
  10850. <description>Read protection</description>
  10851. <bitOffset>0</bitOffset>
  10852. <bitWidth>8</bitWidth>
  10853. </field>
  10854. <field>
  10855. <name>BOR_LEV</name>
  10856. <description>BOR_LEV</description>
  10857. <bitOffset>16</bitOffset>
  10858. <bitWidth>4</bitWidth>
  10859. </field>
  10860. <field>
  10861. <name>SPRMOD</name>
  10862. <description>Selection of protection mode of WPR
  10863. bits</description>
  10864. <bitOffset>8</bitOffset>
  10865. <bitWidth>1</bitWidth>
  10866. </field>
  10867. </fields>
  10868. </register>
  10869. <register>
  10870. <name>WRPR</name>
  10871. <displayName>WRPR</displayName>
  10872. <description>Write protection register</description>
  10873. <addressOffset>0x20</addressOffset>
  10874. <size>0x20</size>
  10875. <access>read-write</access>
  10876. <resetValue>0x00000000</resetValue>
  10877. <fields>
  10878. <field>
  10879. <name>WRP</name>
  10880. <description>Write protection</description>
  10881. <bitOffset>0</bitOffset>
  10882. <bitWidth>16</bitWidth>
  10883. </field>
  10884. </fields>
  10885. </register>
  10886. </registers>
  10887. </peripheral>
  10888. <peripheral>
  10889. <name>EXTI</name>
  10890. <description>External interrupt/event
  10891. controller</description>
  10892. <groupName>EXTI</groupName>
  10893. <baseAddress>0x40010400</baseAddress>
  10894. <addressBlock>
  10895. <offset>0x0</offset>
  10896. <size>0x400</size>
  10897. <usage>registers</usage>
  10898. </addressBlock>
  10899. <interrupt>
  10900. <name>PVD</name>
  10901. <description>PVD through EXTI line detection</description>
  10902. <value>1</value>
  10903. </interrupt>
  10904. <interrupt>
  10905. <name>EXTI0_1</name>
  10906. <description>EXTI Line[1:0] interrupts</description>
  10907. <value>5</value>
  10908. </interrupt>
  10909. <interrupt>
  10910. <name>EXTI2_3</name>
  10911. <description>EXTI Line[3:2] interrupts</description>
  10912. <value>6</value>
  10913. </interrupt>
  10914. <interrupt>
  10915. <name>EXTI4_15</name>
  10916. <description>EXTI Line15 and EXTI4 interrupts</description>
  10917. <value>7</value>
  10918. </interrupt>
  10919. <registers>
  10920. <register>
  10921. <name>IMR</name>
  10922. <displayName>IMR</displayName>
  10923. <description>Interrupt mask register
  10924. (EXTI_IMR)</description>
  10925. <addressOffset>0x0</addressOffset>
  10926. <size>0x20</size>
  10927. <access>read-write</access>
  10928. <resetValue>0xFF840000</resetValue>
  10929. <fields>
  10930. <field>
  10931. <name>MR0</name>
  10932. <description>Interrupt Mask on line 0</description>
  10933. <bitOffset>0</bitOffset>
  10934. <bitWidth>1</bitWidth>
  10935. </field>
  10936. <field>
  10937. <name>MR1</name>
  10938. <description>Interrupt Mask on line 1</description>
  10939. <bitOffset>1</bitOffset>
  10940. <bitWidth>1</bitWidth>
  10941. </field>
  10942. <field>
  10943. <name>MR2</name>
  10944. <description>Interrupt Mask on line 2</description>
  10945. <bitOffset>2</bitOffset>
  10946. <bitWidth>1</bitWidth>
  10947. </field>
  10948. <field>
  10949. <name>MR3</name>
  10950. <description>Interrupt Mask on line 3</description>
  10951. <bitOffset>3</bitOffset>
  10952. <bitWidth>1</bitWidth>
  10953. </field>
  10954. <field>
  10955. <name>MR4</name>
  10956. <description>Interrupt Mask on line 4</description>
  10957. <bitOffset>4</bitOffset>
  10958. <bitWidth>1</bitWidth>
  10959. </field>
  10960. <field>
  10961. <name>MR5</name>
  10962. <description>Interrupt Mask on line 5</description>
  10963. <bitOffset>5</bitOffset>
  10964. <bitWidth>1</bitWidth>
  10965. </field>
  10966. <field>
  10967. <name>MR6</name>
  10968. <description>Interrupt Mask on line 6</description>
  10969. <bitOffset>6</bitOffset>
  10970. <bitWidth>1</bitWidth>
  10971. </field>
  10972. <field>
  10973. <name>MR7</name>
  10974. <description>Interrupt Mask on line 7</description>
  10975. <bitOffset>7</bitOffset>
  10976. <bitWidth>1</bitWidth>
  10977. </field>
  10978. <field>
  10979. <name>MR8</name>
  10980. <description>Interrupt Mask on line 8</description>
  10981. <bitOffset>8</bitOffset>
  10982. <bitWidth>1</bitWidth>
  10983. </field>
  10984. <field>
  10985. <name>MR9</name>
  10986. <description>Interrupt Mask on line 9</description>
  10987. <bitOffset>9</bitOffset>
  10988. <bitWidth>1</bitWidth>
  10989. </field>
  10990. <field>
  10991. <name>MR10</name>
  10992. <description>Interrupt Mask on line 10</description>
  10993. <bitOffset>10</bitOffset>
  10994. <bitWidth>1</bitWidth>
  10995. </field>
  10996. <field>
  10997. <name>MR11</name>
  10998. <description>Interrupt Mask on line 11</description>
  10999. <bitOffset>11</bitOffset>
  11000. <bitWidth>1</bitWidth>
  11001. </field>
  11002. <field>
  11003. <name>MR12</name>
  11004. <description>Interrupt Mask on line 12</description>
  11005. <bitOffset>12</bitOffset>
  11006. <bitWidth>1</bitWidth>
  11007. </field>
  11008. <field>
  11009. <name>MR13</name>
  11010. <description>Interrupt Mask on line 13</description>
  11011. <bitOffset>13</bitOffset>
  11012. <bitWidth>1</bitWidth>
  11013. </field>
  11014. <field>
  11015. <name>MR14</name>
  11016. <description>Interrupt Mask on line 14</description>
  11017. <bitOffset>14</bitOffset>
  11018. <bitWidth>1</bitWidth>
  11019. </field>
  11020. <field>
  11021. <name>MR15</name>
  11022. <description>Interrupt Mask on line 15</description>
  11023. <bitOffset>15</bitOffset>
  11024. <bitWidth>1</bitWidth>
  11025. </field>
  11026. <field>
  11027. <name>MR16</name>
  11028. <description>Interrupt Mask on line 16</description>
  11029. <bitOffset>16</bitOffset>
  11030. <bitWidth>1</bitWidth>
  11031. </field>
  11032. <field>
  11033. <name>MR17</name>
  11034. <description>Interrupt Mask on line 17</description>
  11035. <bitOffset>17</bitOffset>
  11036. <bitWidth>1</bitWidth>
  11037. </field>
  11038. <field>
  11039. <name>MR19</name>
  11040. <description>Interrupt Mask on line 19</description>
  11041. <bitOffset>19</bitOffset>
  11042. <bitWidth>1</bitWidth>
  11043. </field>
  11044. <field>
  11045. <name>MR21</name>
  11046. <description>Interrupt Mask on line 21</description>
  11047. <bitOffset>21</bitOffset>
  11048. <bitWidth>1</bitWidth>
  11049. </field>
  11050. <field>
  11051. <name>MR22</name>
  11052. <description>Interrupt Mask on line 22</description>
  11053. <bitOffset>22</bitOffset>
  11054. <bitWidth>1</bitWidth>
  11055. </field>
  11056. <field>
  11057. <name>MR23</name>
  11058. <description>Interrupt Mask on line 23</description>
  11059. <bitOffset>23</bitOffset>
  11060. <bitWidth>1</bitWidth>
  11061. </field>
  11062. <field>
  11063. <name>MR25</name>
  11064. <description>Interrupt Mask on line 25</description>
  11065. <bitOffset>25</bitOffset>
  11066. <bitWidth>1</bitWidth>
  11067. </field>
  11068. <field>
  11069. <name>MR27</name>
  11070. <description>Interrupt Mask on line 27</description>
  11071. <bitOffset>27</bitOffset>
  11072. <bitWidth>1</bitWidth>
  11073. </field>
  11074. </fields>
  11075. </register>
  11076. <register>
  11077. <name>EMR</name>
  11078. <displayName>EMR</displayName>
  11079. <description>Event mask register (EXTI_EMR)</description>
  11080. <addressOffset>0x4</addressOffset>
  11081. <size>0x20</size>
  11082. <access>read-write</access>
  11083. <resetValue>0x00000000</resetValue>
  11084. <fields>
  11085. <field>
  11086. <name>MR0</name>
  11087. <description>Event Mask on line 0</description>
  11088. <bitOffset>0</bitOffset>
  11089. <bitWidth>1</bitWidth>
  11090. </field>
  11091. <field>
  11092. <name>MR1</name>
  11093. <description>Event Mask on line 1</description>
  11094. <bitOffset>1</bitOffset>
  11095. <bitWidth>1</bitWidth>
  11096. </field>
  11097. <field>
  11098. <name>MR2</name>
  11099. <description>Event Mask on line 2</description>
  11100. <bitOffset>2</bitOffset>
  11101. <bitWidth>1</bitWidth>
  11102. </field>
  11103. <field>
  11104. <name>MR3</name>
  11105. <description>Event Mask on line 3</description>
  11106. <bitOffset>3</bitOffset>
  11107. <bitWidth>1</bitWidth>
  11108. </field>
  11109. <field>
  11110. <name>MR4</name>
  11111. <description>Event Mask on line 4</description>
  11112. <bitOffset>4</bitOffset>
  11113. <bitWidth>1</bitWidth>
  11114. </field>
  11115. <field>
  11116. <name>MR5</name>
  11117. <description>Event Mask on line 5</description>
  11118. <bitOffset>5</bitOffset>
  11119. <bitWidth>1</bitWidth>
  11120. </field>
  11121. <field>
  11122. <name>MR6</name>
  11123. <description>Event Mask on line 6</description>
  11124. <bitOffset>6</bitOffset>
  11125. <bitWidth>1</bitWidth>
  11126. </field>
  11127. <field>
  11128. <name>MR7</name>
  11129. <description>Event Mask on line 7</description>
  11130. <bitOffset>7</bitOffset>
  11131. <bitWidth>1</bitWidth>
  11132. </field>
  11133. <field>
  11134. <name>MR8</name>
  11135. <description>Event Mask on line 8</description>
  11136. <bitOffset>8</bitOffset>
  11137. <bitWidth>1</bitWidth>
  11138. </field>
  11139. <field>
  11140. <name>MR9</name>
  11141. <description>Event Mask on line 9</description>
  11142. <bitOffset>9</bitOffset>
  11143. <bitWidth>1</bitWidth>
  11144. </field>
  11145. <field>
  11146. <name>MR10</name>
  11147. <description>Event Mask on line 10</description>
  11148. <bitOffset>10</bitOffset>
  11149. <bitWidth>1</bitWidth>
  11150. </field>
  11151. <field>
  11152. <name>MR11</name>
  11153. <description>Event Mask on line 11</description>
  11154. <bitOffset>11</bitOffset>
  11155. <bitWidth>1</bitWidth>
  11156. </field>
  11157. <field>
  11158. <name>MR12</name>
  11159. <description>Event Mask on line 12</description>
  11160. <bitOffset>12</bitOffset>
  11161. <bitWidth>1</bitWidth>
  11162. </field>
  11163. <field>
  11164. <name>MR13</name>
  11165. <description>Event Mask on line 13</description>
  11166. <bitOffset>13</bitOffset>
  11167. <bitWidth>1</bitWidth>
  11168. </field>
  11169. <field>
  11170. <name>MR14</name>
  11171. <description>Event Mask on line 14</description>
  11172. <bitOffset>14</bitOffset>
  11173. <bitWidth>1</bitWidth>
  11174. </field>
  11175. <field>
  11176. <name>MR15</name>
  11177. <description>Event Mask on line 15</description>
  11178. <bitOffset>15</bitOffset>
  11179. <bitWidth>1</bitWidth>
  11180. </field>
  11181. <field>
  11182. <name>MR16</name>
  11183. <description>Event Mask on line 16</description>
  11184. <bitOffset>16</bitOffset>
  11185. <bitWidth>1</bitWidth>
  11186. </field>
  11187. <field>
  11188. <name>MR17</name>
  11189. <description>Event Mask on line 17</description>
  11190. <bitOffset>17</bitOffset>
  11191. <bitWidth>1</bitWidth>
  11192. </field>
  11193. <field>
  11194. <name>MR19</name>
  11195. <description>Event Mask on line 19</description>
  11196. <bitOffset>19</bitOffset>
  11197. <bitWidth>1</bitWidth>
  11198. </field>
  11199. <field>
  11200. <name>MR21</name>
  11201. <description>Event Mask on line 21</description>
  11202. <bitOffset>21</bitOffset>
  11203. <bitWidth>1</bitWidth>
  11204. </field>
  11205. <field>
  11206. <name>MR22</name>
  11207. <description>Event Mask on line 22</description>
  11208. <bitOffset>22</bitOffset>
  11209. <bitWidth>1</bitWidth>
  11210. </field>
  11211. <field>
  11212. <name>MR23</name>
  11213. <description>Event Mask on line 23</description>
  11214. <bitOffset>23</bitOffset>
  11215. <bitWidth>1</bitWidth>
  11216. </field>
  11217. <field>
  11218. <name>MR25</name>
  11219. <description>Event Mask on line 25</description>
  11220. <bitOffset>25</bitOffset>
  11221. <bitWidth>1</bitWidth>
  11222. </field>
  11223. <field>
  11224. <name>MR27</name>
  11225. <description>Event Mask on line 27</description>
  11226. <bitOffset>27</bitOffset>
  11227. <bitWidth>1</bitWidth>
  11228. </field>
  11229. </fields>
  11230. </register>
  11231. <register>
  11232. <name>RTSR</name>
  11233. <displayName>RTSR</displayName>
  11234. <description>Rising Trigger selection register
  11235. (EXTI_RTSR)</description>
  11236. <addressOffset>0x8</addressOffset>
  11237. <size>0x20</size>
  11238. <access>read-write</access>
  11239. <resetValue>0x00000000</resetValue>
  11240. <fields>
  11241. <field>
  11242. <name>TR0</name>
  11243. <description>Rising trigger event configuration of
  11244. line 0</description>
  11245. <bitOffset>0</bitOffset>
  11246. <bitWidth>1</bitWidth>
  11247. </field>
  11248. <field>
  11249. <name>TR1</name>
  11250. <description>Rising trigger event configuration of
  11251. line 1</description>
  11252. <bitOffset>1</bitOffset>
  11253. <bitWidth>1</bitWidth>
  11254. </field>
  11255. <field>
  11256. <name>TR2</name>
  11257. <description>Rising trigger event configuration of
  11258. line 2</description>
  11259. <bitOffset>2</bitOffset>
  11260. <bitWidth>1</bitWidth>
  11261. </field>
  11262. <field>
  11263. <name>TR3</name>
  11264. <description>Rising trigger event configuration of
  11265. line 3</description>
  11266. <bitOffset>3</bitOffset>
  11267. <bitWidth>1</bitWidth>
  11268. </field>
  11269. <field>
  11270. <name>TR4</name>
  11271. <description>Rising trigger event configuration of
  11272. line 4</description>
  11273. <bitOffset>4</bitOffset>
  11274. <bitWidth>1</bitWidth>
  11275. </field>
  11276. <field>
  11277. <name>TR5</name>
  11278. <description>Rising trigger event configuration of
  11279. line 5</description>
  11280. <bitOffset>5</bitOffset>
  11281. <bitWidth>1</bitWidth>
  11282. </field>
  11283. <field>
  11284. <name>TR6</name>
  11285. <description>Rising trigger event configuration of
  11286. line 6</description>
  11287. <bitOffset>6</bitOffset>
  11288. <bitWidth>1</bitWidth>
  11289. </field>
  11290. <field>
  11291. <name>TR7</name>
  11292. <description>Rising trigger event configuration of
  11293. line 7</description>
  11294. <bitOffset>7</bitOffset>
  11295. <bitWidth>1</bitWidth>
  11296. </field>
  11297. <field>
  11298. <name>TR8</name>
  11299. <description>Rising trigger event configuration of
  11300. line 8</description>
  11301. <bitOffset>8</bitOffset>
  11302. <bitWidth>1</bitWidth>
  11303. </field>
  11304. <field>
  11305. <name>TR9</name>
  11306. <description>Rising trigger event configuration of
  11307. line 9</description>
  11308. <bitOffset>9</bitOffset>
  11309. <bitWidth>1</bitWidth>
  11310. </field>
  11311. <field>
  11312. <name>TR10</name>
  11313. <description>Rising trigger event configuration of
  11314. line 10</description>
  11315. <bitOffset>10</bitOffset>
  11316. <bitWidth>1</bitWidth>
  11317. </field>
  11318. <field>
  11319. <name>TR11</name>
  11320. <description>Rising trigger event configuration of
  11321. line 11</description>
  11322. <bitOffset>11</bitOffset>
  11323. <bitWidth>1</bitWidth>
  11324. </field>
  11325. <field>
  11326. <name>TR12</name>
  11327. <description>Rising trigger event configuration of
  11328. line 12</description>
  11329. <bitOffset>12</bitOffset>
  11330. <bitWidth>1</bitWidth>
  11331. </field>
  11332. <field>
  11333. <name>TR13</name>
  11334. <description>Rising trigger event configuration of
  11335. line 13</description>
  11336. <bitOffset>13</bitOffset>
  11337. <bitWidth>1</bitWidth>
  11338. </field>
  11339. <field>
  11340. <name>TR14</name>
  11341. <description>Rising trigger event configuration of
  11342. line 14</description>
  11343. <bitOffset>14</bitOffset>
  11344. <bitWidth>1</bitWidth>
  11345. </field>
  11346. <field>
  11347. <name>TR15</name>
  11348. <description>Rising trigger event configuration of
  11349. line 15</description>
  11350. <bitOffset>15</bitOffset>
  11351. <bitWidth>1</bitWidth>
  11352. </field>
  11353. <field>
  11354. <name>TR16</name>
  11355. <description>Rising trigger event configuration of
  11356. line 16</description>
  11357. <bitOffset>16</bitOffset>
  11358. <bitWidth>1</bitWidth>
  11359. </field>
  11360. <field>
  11361. <name>TR17</name>
  11362. <description>Rising trigger event configuration of
  11363. line 17</description>
  11364. <bitOffset>17</bitOffset>
  11365. <bitWidth>1</bitWidth>
  11366. </field>
  11367. <field>
  11368. <name>TR19</name>
  11369. <description>Rising trigger event configuration of
  11370. line 19</description>
  11371. <bitOffset>19</bitOffset>
  11372. <bitWidth>1</bitWidth>
  11373. </field>
  11374. </fields>
  11375. </register>
  11376. <register>
  11377. <name>FTSR</name>
  11378. <displayName>FTSR</displayName>
  11379. <description>Falling Trigger selection register
  11380. (EXTI_FTSR)</description>
  11381. <addressOffset>0xC</addressOffset>
  11382. <size>0x20</size>
  11383. <access>read-write</access>
  11384. <resetValue>0x00000000</resetValue>
  11385. <fields>
  11386. <field>
  11387. <name>TR0</name>
  11388. <description>Falling trigger event configuration of
  11389. line 0</description>
  11390. <bitOffset>0</bitOffset>
  11391. <bitWidth>1</bitWidth>
  11392. </field>
  11393. <field>
  11394. <name>TR1</name>
  11395. <description>Falling trigger event configuration of
  11396. line 1</description>
  11397. <bitOffset>1</bitOffset>
  11398. <bitWidth>1</bitWidth>
  11399. </field>
  11400. <field>
  11401. <name>TR2</name>
  11402. <description>Falling trigger event configuration of
  11403. line 2</description>
  11404. <bitOffset>2</bitOffset>
  11405. <bitWidth>1</bitWidth>
  11406. </field>
  11407. <field>
  11408. <name>TR3</name>
  11409. <description>Falling trigger event configuration of
  11410. line 3</description>
  11411. <bitOffset>3</bitOffset>
  11412. <bitWidth>1</bitWidth>
  11413. </field>
  11414. <field>
  11415. <name>TR4</name>
  11416. <description>Falling trigger event configuration of
  11417. line 4</description>
  11418. <bitOffset>4</bitOffset>
  11419. <bitWidth>1</bitWidth>
  11420. </field>
  11421. <field>
  11422. <name>TR5</name>
  11423. <description>Falling trigger event configuration of
  11424. line 5</description>
  11425. <bitOffset>5</bitOffset>
  11426. <bitWidth>1</bitWidth>
  11427. </field>
  11428. <field>
  11429. <name>TR6</name>
  11430. <description>Falling trigger event configuration of
  11431. line 6</description>
  11432. <bitOffset>6</bitOffset>
  11433. <bitWidth>1</bitWidth>
  11434. </field>
  11435. <field>
  11436. <name>TR7</name>
  11437. <description>Falling trigger event configuration of
  11438. line 7</description>
  11439. <bitOffset>7</bitOffset>
  11440. <bitWidth>1</bitWidth>
  11441. </field>
  11442. <field>
  11443. <name>TR8</name>
  11444. <description>Falling trigger event configuration of
  11445. line 8</description>
  11446. <bitOffset>8</bitOffset>
  11447. <bitWidth>1</bitWidth>
  11448. </field>
  11449. <field>
  11450. <name>TR9</name>
  11451. <description>Falling trigger event configuration of
  11452. line 9</description>
  11453. <bitOffset>9</bitOffset>
  11454. <bitWidth>1</bitWidth>
  11455. </field>
  11456. <field>
  11457. <name>TR10</name>
  11458. <description>Falling trigger event configuration of
  11459. line 10</description>
  11460. <bitOffset>10</bitOffset>
  11461. <bitWidth>1</bitWidth>
  11462. </field>
  11463. <field>
  11464. <name>TR11</name>
  11465. <description>Falling trigger event configuration of
  11466. line 11</description>
  11467. <bitOffset>11</bitOffset>
  11468. <bitWidth>1</bitWidth>
  11469. </field>
  11470. <field>
  11471. <name>TR12</name>
  11472. <description>Falling trigger event configuration of
  11473. line 12</description>
  11474. <bitOffset>12</bitOffset>
  11475. <bitWidth>1</bitWidth>
  11476. </field>
  11477. <field>
  11478. <name>TR13</name>
  11479. <description>Falling trigger event configuration of
  11480. line 13</description>
  11481. <bitOffset>13</bitOffset>
  11482. <bitWidth>1</bitWidth>
  11483. </field>
  11484. <field>
  11485. <name>TR14</name>
  11486. <description>Falling trigger event configuration of
  11487. line 14</description>
  11488. <bitOffset>14</bitOffset>
  11489. <bitWidth>1</bitWidth>
  11490. </field>
  11491. <field>
  11492. <name>TR15</name>
  11493. <description>Falling trigger event configuration of
  11494. line 15</description>
  11495. <bitOffset>15</bitOffset>
  11496. <bitWidth>1</bitWidth>
  11497. </field>
  11498. <field>
  11499. <name>TR16</name>
  11500. <description>Falling trigger event configuration of
  11501. line 16</description>
  11502. <bitOffset>16</bitOffset>
  11503. <bitWidth>1</bitWidth>
  11504. </field>
  11505. <field>
  11506. <name>TR17</name>
  11507. <description>Falling trigger event configuration of
  11508. line 17</description>
  11509. <bitOffset>17</bitOffset>
  11510. <bitWidth>1</bitWidth>
  11511. </field>
  11512. <field>
  11513. <name>TR19</name>
  11514. <description>Falling trigger event configuration of
  11515. line 19</description>
  11516. <bitOffset>19</bitOffset>
  11517. <bitWidth>1</bitWidth>
  11518. </field>
  11519. </fields>
  11520. </register>
  11521. <register>
  11522. <name>SWIER</name>
  11523. <displayName>SWIER</displayName>
  11524. <description>Software interrupt event register
  11525. (EXTI_SWIER)</description>
  11526. <addressOffset>0x10</addressOffset>
  11527. <size>0x20</size>
  11528. <access>read-write</access>
  11529. <resetValue>0x00000000</resetValue>
  11530. <fields>
  11531. <field>
  11532. <name>SWIER0</name>
  11533. <description>Software Interrupt on line
  11534. 0</description>
  11535. <bitOffset>0</bitOffset>
  11536. <bitWidth>1</bitWidth>
  11537. </field>
  11538. <field>
  11539. <name>SWIER1</name>
  11540. <description>Software Interrupt on line
  11541. 1</description>
  11542. <bitOffset>1</bitOffset>
  11543. <bitWidth>1</bitWidth>
  11544. </field>
  11545. <field>
  11546. <name>SWIER2</name>
  11547. <description>Software Interrupt on line
  11548. 2</description>
  11549. <bitOffset>2</bitOffset>
  11550. <bitWidth>1</bitWidth>
  11551. </field>
  11552. <field>
  11553. <name>SWIER3</name>
  11554. <description>Software Interrupt on line
  11555. 3</description>
  11556. <bitOffset>3</bitOffset>
  11557. <bitWidth>1</bitWidth>
  11558. </field>
  11559. <field>
  11560. <name>SWIER4</name>
  11561. <description>Software Interrupt on line
  11562. 4</description>
  11563. <bitOffset>4</bitOffset>
  11564. <bitWidth>1</bitWidth>
  11565. </field>
  11566. <field>
  11567. <name>SWIER5</name>
  11568. <description>Software Interrupt on line
  11569. 5</description>
  11570. <bitOffset>5</bitOffset>
  11571. <bitWidth>1</bitWidth>
  11572. </field>
  11573. <field>
  11574. <name>SWIER6</name>
  11575. <description>Software Interrupt on line
  11576. 6</description>
  11577. <bitOffset>6</bitOffset>
  11578. <bitWidth>1</bitWidth>
  11579. </field>
  11580. <field>
  11581. <name>SWIER7</name>
  11582. <description>Software Interrupt on line
  11583. 7</description>
  11584. <bitOffset>7</bitOffset>
  11585. <bitWidth>1</bitWidth>
  11586. </field>
  11587. <field>
  11588. <name>SWIER8</name>
  11589. <description>Software Interrupt on line
  11590. 8</description>
  11591. <bitOffset>8</bitOffset>
  11592. <bitWidth>1</bitWidth>
  11593. </field>
  11594. <field>
  11595. <name>SWIER9</name>
  11596. <description>Software Interrupt on line
  11597. 9</description>
  11598. <bitOffset>9</bitOffset>
  11599. <bitWidth>1</bitWidth>
  11600. </field>
  11601. <field>
  11602. <name>SWIER10</name>
  11603. <description>Software Interrupt on line
  11604. 10</description>
  11605. <bitOffset>10</bitOffset>
  11606. <bitWidth>1</bitWidth>
  11607. </field>
  11608. <field>
  11609. <name>SWIER11</name>
  11610. <description>Software Interrupt on line
  11611. 11</description>
  11612. <bitOffset>11</bitOffset>
  11613. <bitWidth>1</bitWidth>
  11614. </field>
  11615. <field>
  11616. <name>SWIER12</name>
  11617. <description>Software Interrupt on line
  11618. 12</description>
  11619. <bitOffset>12</bitOffset>
  11620. <bitWidth>1</bitWidth>
  11621. </field>
  11622. <field>
  11623. <name>SWIER13</name>
  11624. <description>Software Interrupt on line
  11625. 13</description>
  11626. <bitOffset>13</bitOffset>
  11627. <bitWidth>1</bitWidth>
  11628. </field>
  11629. <field>
  11630. <name>SWIER14</name>
  11631. <description>Software Interrupt on line
  11632. 14</description>
  11633. <bitOffset>14</bitOffset>
  11634. <bitWidth>1</bitWidth>
  11635. </field>
  11636. <field>
  11637. <name>SWIER15</name>
  11638. <description>Software Interrupt on line
  11639. 15</description>
  11640. <bitOffset>15</bitOffset>
  11641. <bitWidth>1</bitWidth>
  11642. </field>
  11643. <field>
  11644. <name>SWIER16</name>
  11645. <description>Software Interrupt on line
  11646. 16</description>
  11647. <bitOffset>16</bitOffset>
  11648. <bitWidth>1</bitWidth>
  11649. </field>
  11650. <field>
  11651. <name>SWIER17</name>
  11652. <description>Software Interrupt on line
  11653. 17</description>
  11654. <bitOffset>17</bitOffset>
  11655. <bitWidth>1</bitWidth>
  11656. </field>
  11657. <field>
  11658. <name>SWIER19</name>
  11659. <description>Software Interrupt on line
  11660. 19</description>
  11661. <bitOffset>19</bitOffset>
  11662. <bitWidth>1</bitWidth>
  11663. </field>
  11664. </fields>
  11665. </register>
  11666. <register>
  11667. <name>PR</name>
  11668. <displayName>PR</displayName>
  11669. <description>Pending register (EXTI_PR)</description>
  11670. <addressOffset>0x14</addressOffset>
  11671. <size>0x20</size>
  11672. <access>read-write</access>
  11673. <resetValue>0x00000000</resetValue>
  11674. <fields>
  11675. <field>
  11676. <name>PR0</name>
  11677. <description>Pending bit 0</description>
  11678. <bitOffset>0</bitOffset>
  11679. <bitWidth>1</bitWidth>
  11680. </field>
  11681. <field>
  11682. <name>PR1</name>
  11683. <description>Pending bit 1</description>
  11684. <bitOffset>1</bitOffset>
  11685. <bitWidth>1</bitWidth>
  11686. </field>
  11687. <field>
  11688. <name>PR2</name>
  11689. <description>Pending bit 2</description>
  11690. <bitOffset>2</bitOffset>
  11691. <bitWidth>1</bitWidth>
  11692. </field>
  11693. <field>
  11694. <name>PR3</name>
  11695. <description>Pending bit 3</description>
  11696. <bitOffset>3</bitOffset>
  11697. <bitWidth>1</bitWidth>
  11698. </field>
  11699. <field>
  11700. <name>PR4</name>
  11701. <description>Pending bit 4</description>
  11702. <bitOffset>4</bitOffset>
  11703. <bitWidth>1</bitWidth>
  11704. </field>
  11705. <field>
  11706. <name>PR5</name>
  11707. <description>Pending bit 5</description>
  11708. <bitOffset>5</bitOffset>
  11709. <bitWidth>1</bitWidth>
  11710. </field>
  11711. <field>
  11712. <name>PR6</name>
  11713. <description>Pending bit 6</description>
  11714. <bitOffset>6</bitOffset>
  11715. <bitWidth>1</bitWidth>
  11716. </field>
  11717. <field>
  11718. <name>PR7</name>
  11719. <description>Pending bit 7</description>
  11720. <bitOffset>7</bitOffset>
  11721. <bitWidth>1</bitWidth>
  11722. </field>
  11723. <field>
  11724. <name>PR8</name>
  11725. <description>Pending bit 8</description>
  11726. <bitOffset>8</bitOffset>
  11727. <bitWidth>1</bitWidth>
  11728. </field>
  11729. <field>
  11730. <name>PR9</name>
  11731. <description>Pending bit 9</description>
  11732. <bitOffset>9</bitOffset>
  11733. <bitWidth>1</bitWidth>
  11734. </field>
  11735. <field>
  11736. <name>PR10</name>
  11737. <description>Pending bit 10</description>
  11738. <bitOffset>10</bitOffset>
  11739. <bitWidth>1</bitWidth>
  11740. </field>
  11741. <field>
  11742. <name>PR11</name>
  11743. <description>Pending bit 11</description>
  11744. <bitOffset>11</bitOffset>
  11745. <bitWidth>1</bitWidth>
  11746. </field>
  11747. <field>
  11748. <name>PR12</name>
  11749. <description>Pending bit 12</description>
  11750. <bitOffset>12</bitOffset>
  11751. <bitWidth>1</bitWidth>
  11752. </field>
  11753. <field>
  11754. <name>PR13</name>
  11755. <description>Pending bit 13</description>
  11756. <bitOffset>13</bitOffset>
  11757. <bitWidth>1</bitWidth>
  11758. </field>
  11759. <field>
  11760. <name>PR14</name>
  11761. <description>Pending bit 14</description>
  11762. <bitOffset>14</bitOffset>
  11763. <bitWidth>1</bitWidth>
  11764. </field>
  11765. <field>
  11766. <name>PR15</name>
  11767. <description>Pending bit 15</description>
  11768. <bitOffset>15</bitOffset>
  11769. <bitWidth>1</bitWidth>
  11770. </field>
  11771. <field>
  11772. <name>PR16</name>
  11773. <description>Pending bit 16</description>
  11774. <bitOffset>16</bitOffset>
  11775. <bitWidth>1</bitWidth>
  11776. </field>
  11777. <field>
  11778. <name>PR17</name>
  11779. <description>Pending bit 17</description>
  11780. <bitOffset>17</bitOffset>
  11781. <bitWidth>1</bitWidth>
  11782. </field>
  11783. <field>
  11784. <name>PR19</name>
  11785. <description>Pending bit 19</description>
  11786. <bitOffset>19</bitOffset>
  11787. <bitWidth>1</bitWidth>
  11788. </field>
  11789. </fields>
  11790. </register>
  11791. </registers>
  11792. </peripheral>
  11793. <peripheral>
  11794. <name>ADC</name>
  11795. <description>Analog-to-digital converter</description>
  11796. <groupName>ADC</groupName>
  11797. <baseAddress>0x40012400</baseAddress>
  11798. <addressBlock>
  11799. <offset>0x0</offset>
  11800. <size>0x400</size>
  11801. <usage>registers</usage>
  11802. </addressBlock>
  11803. <interrupt>
  11804. <name>ADC_COMP</name>
  11805. <description>ADC and comparator 1 and 2</description>
  11806. <value>12</value>
  11807. </interrupt>
  11808. <registers>
  11809. <register>
  11810. <name>ISR</name>
  11811. <displayName>ISR</displayName>
  11812. <description>interrupt and status register</description>
  11813. <addressOffset>0x0</addressOffset>
  11814. <size>0x20</size>
  11815. <access>read-write</access>
  11816. <resetValue>0x00000000</resetValue>
  11817. <fields>
  11818. <field>
  11819. <name>ADRDY</name>
  11820. <description>ADC ready</description>
  11821. <bitOffset>0</bitOffset>
  11822. <bitWidth>1</bitWidth>
  11823. </field>
  11824. <field>
  11825. <name>EOSMP</name>
  11826. <description>End of sampling flag</description>
  11827. <bitOffset>1</bitOffset>
  11828. <bitWidth>1</bitWidth>
  11829. </field>
  11830. <field>
  11831. <name>EOC</name>
  11832. <description>End of conversion flag</description>
  11833. <bitOffset>2</bitOffset>
  11834. <bitWidth>1</bitWidth>
  11835. </field>
  11836. <field>
  11837. <name>EOS</name>
  11838. <description>End of sequence flag</description>
  11839. <bitOffset>3</bitOffset>
  11840. <bitWidth>1</bitWidth>
  11841. </field>
  11842. <field>
  11843. <name>OVR</name>
  11844. <description>ADC overrun</description>
  11845. <bitOffset>4</bitOffset>
  11846. <bitWidth>1</bitWidth>
  11847. </field>
  11848. <field>
  11849. <name>AWD</name>
  11850. <description>Analog watchdog flag</description>
  11851. <bitOffset>7</bitOffset>
  11852. <bitWidth>1</bitWidth>
  11853. </field>
  11854. <field>
  11855. <name>EOCAL</name>
  11856. <description>End Of Calibration flag</description>
  11857. <bitOffset>11</bitOffset>
  11858. <bitWidth>1</bitWidth>
  11859. </field>
  11860. </fields>
  11861. </register>
  11862. <register>
  11863. <name>IER</name>
  11864. <displayName>IER</displayName>
  11865. <description>interrupt enable register</description>
  11866. <addressOffset>0x4</addressOffset>
  11867. <size>0x20</size>
  11868. <access>read-write</access>
  11869. <resetValue>0x00000000</resetValue>
  11870. <fields>
  11871. <field>
  11872. <name>ADRDYIE</name>
  11873. <description>ADC ready interrupt enable</description>
  11874. <bitOffset>0</bitOffset>
  11875. <bitWidth>1</bitWidth>
  11876. </field>
  11877. <field>
  11878. <name>EOSMPIE</name>
  11879. <description>End of sampling flag interrupt
  11880. enable</description>
  11881. <bitOffset>1</bitOffset>
  11882. <bitWidth>1</bitWidth>
  11883. </field>
  11884. <field>
  11885. <name>EOCIE</name>
  11886. <description>End of conversion interrupt
  11887. enable</description>
  11888. <bitOffset>2</bitOffset>
  11889. <bitWidth>1</bitWidth>
  11890. </field>
  11891. <field>
  11892. <name>EOSIE</name>
  11893. <description>End of conversion sequence interrupt
  11894. enable</description>
  11895. <bitOffset>3</bitOffset>
  11896. <bitWidth>1</bitWidth>
  11897. </field>
  11898. <field>
  11899. <name>OVRIE</name>
  11900. <description>Overrun interrupt enable</description>
  11901. <bitOffset>4</bitOffset>
  11902. <bitWidth>1</bitWidth>
  11903. </field>
  11904. <field>
  11905. <name>AWDIE</name>
  11906. <description>Analog watchdog interrupt
  11907. enable</description>
  11908. <bitOffset>7</bitOffset>
  11909. <bitWidth>1</bitWidth>
  11910. </field>
  11911. <field>
  11912. <name>EOCALIE</name>
  11913. <description>End of calibration interrupt
  11914. enable</description>
  11915. <bitOffset>11</bitOffset>
  11916. <bitWidth>1</bitWidth>
  11917. </field>
  11918. </fields>
  11919. </register>
  11920. <register>
  11921. <name>CR</name>
  11922. <displayName>CR</displayName>
  11923. <description>control register</description>
  11924. <addressOffset>0x8</addressOffset>
  11925. <size>0x20</size>
  11926. <access>read-write</access>
  11927. <resetValue>0x00000000</resetValue>
  11928. <fields>
  11929. <field>
  11930. <name>ADEN</name>
  11931. <description>ADC enable command</description>
  11932. <bitOffset>0</bitOffset>
  11933. <bitWidth>1</bitWidth>
  11934. </field>
  11935. <field>
  11936. <name>ADDIS</name>
  11937. <description>ADC disable command</description>
  11938. <bitOffset>1</bitOffset>
  11939. <bitWidth>1</bitWidth>
  11940. </field>
  11941. <field>
  11942. <name>ADSTART</name>
  11943. <description>ADC start conversion
  11944. command</description>
  11945. <bitOffset>2</bitOffset>
  11946. <bitWidth>1</bitWidth>
  11947. </field>
  11948. <field>
  11949. <name>ADSTP</name>
  11950. <description>ADC stop conversion
  11951. command</description>
  11952. <bitOffset>4</bitOffset>
  11953. <bitWidth>1</bitWidth>
  11954. </field>
  11955. <field>
  11956. <name>ADVREGEN</name>
  11957. <description>ADC Voltage Regulator
  11958. Enable</description>
  11959. <bitOffset>28</bitOffset>
  11960. <bitWidth>1</bitWidth>
  11961. </field>
  11962. <field>
  11963. <name>ADCAL</name>
  11964. <description>ADC calibration</description>
  11965. <bitOffset>31</bitOffset>
  11966. <bitWidth>1</bitWidth>
  11967. </field>
  11968. </fields>
  11969. </register>
  11970. <register>
  11971. <name>CFGR1</name>
  11972. <displayName>CFGR1</displayName>
  11973. <description>configuration register 1</description>
  11974. <addressOffset>0xC</addressOffset>
  11975. <size>0x20</size>
  11976. <access>read-write</access>
  11977. <resetValue>0x00000000</resetValue>
  11978. <fields>
  11979. <field>
  11980. <name>AWDCH</name>
  11981. <description>Analog watchdog channel
  11982. selection</description>
  11983. <bitOffset>26</bitOffset>
  11984. <bitWidth>5</bitWidth>
  11985. </field>
  11986. <field>
  11987. <name>AWDEN</name>
  11988. <description>Analog watchdog enable</description>
  11989. <bitOffset>23</bitOffset>
  11990. <bitWidth>1</bitWidth>
  11991. </field>
  11992. <field>
  11993. <name>AWDSGL</name>
  11994. <description>Enable the watchdog on a single channel
  11995. or on all channels</description>
  11996. <bitOffset>22</bitOffset>
  11997. <bitWidth>1</bitWidth>
  11998. </field>
  11999. <field>
  12000. <name>DISCEN</name>
  12001. <description>Discontinuous mode</description>
  12002. <bitOffset>16</bitOffset>
  12003. <bitWidth>1</bitWidth>
  12004. </field>
  12005. <field>
  12006. <name>AUTOFF</name>
  12007. <description>Auto-off mode</description>
  12008. <bitOffset>15</bitOffset>
  12009. <bitWidth>1</bitWidth>
  12010. </field>
  12011. <field>
  12012. <name>AUTDLY</name>
  12013. <description>Auto-delayed conversion
  12014. mode</description>
  12015. <bitOffset>14</bitOffset>
  12016. <bitWidth>1</bitWidth>
  12017. </field>
  12018. <field>
  12019. <name>CONT</name>
  12020. <description>Single / continuous conversion
  12021. mode</description>
  12022. <bitOffset>13</bitOffset>
  12023. <bitWidth>1</bitWidth>
  12024. </field>
  12025. <field>
  12026. <name>OVRMOD</name>
  12027. <description>Overrun management mode</description>
  12028. <bitOffset>12</bitOffset>
  12029. <bitWidth>1</bitWidth>
  12030. </field>
  12031. <field>
  12032. <name>EXTEN</name>
  12033. <description>External trigger enable and polarity
  12034. selection</description>
  12035. <bitOffset>10</bitOffset>
  12036. <bitWidth>2</bitWidth>
  12037. </field>
  12038. <field>
  12039. <name>EXTSEL</name>
  12040. <description>External trigger selection</description>
  12041. <bitOffset>6</bitOffset>
  12042. <bitWidth>3</bitWidth>
  12043. </field>
  12044. <field>
  12045. <name>ALIGN</name>
  12046. <description>Data alignment</description>
  12047. <bitOffset>5</bitOffset>
  12048. <bitWidth>1</bitWidth>
  12049. </field>
  12050. <field>
  12051. <name>RES</name>
  12052. <description>Data resolution</description>
  12053. <bitOffset>3</bitOffset>
  12054. <bitWidth>2</bitWidth>
  12055. </field>
  12056. <field>
  12057. <name>SCANDIR</name>
  12058. <description>Scan sequence direction</description>
  12059. <bitOffset>2</bitOffset>
  12060. <bitWidth>1</bitWidth>
  12061. </field>
  12062. <field>
  12063. <name>DMACFG</name>
  12064. <description>Direct memery access
  12065. configuration</description>
  12066. <bitOffset>1</bitOffset>
  12067. <bitWidth>1</bitWidth>
  12068. </field>
  12069. <field>
  12070. <name>DMAEN</name>
  12071. <description>Direct memory access
  12072. enable</description>
  12073. <bitOffset>0</bitOffset>
  12074. <bitWidth>1</bitWidth>
  12075. </field>
  12076. </fields>
  12077. </register>
  12078. <register>
  12079. <name>CFGR2</name>
  12080. <displayName>CFGR2</displayName>
  12081. <description>configuration register 2</description>
  12082. <addressOffset>0x10</addressOffset>
  12083. <size>0x20</size>
  12084. <access>read-write</access>
  12085. <resetValue>0x00000000</resetValue>
  12086. <fields>
  12087. <field>
  12088. <name>OVSE</name>
  12089. <description>Oversampler Enable</description>
  12090. <bitOffset>0</bitOffset>
  12091. <bitWidth>1</bitWidth>
  12092. </field>
  12093. <field>
  12094. <name>OVSR</name>
  12095. <description>Oversampling ratio</description>
  12096. <bitOffset>2</bitOffset>
  12097. <bitWidth>3</bitWidth>
  12098. </field>
  12099. <field>
  12100. <name>OVSS</name>
  12101. <description>Oversampling shift</description>
  12102. <bitOffset>5</bitOffset>
  12103. <bitWidth>4</bitWidth>
  12104. </field>
  12105. <field>
  12106. <name>TOVS</name>
  12107. <description>Triggered Oversampling</description>
  12108. <bitOffset>9</bitOffset>
  12109. <bitWidth>1</bitWidth>
  12110. </field>
  12111. <field>
  12112. <name>CKMODE</name>
  12113. <description>ADC clock mode</description>
  12114. <bitOffset>30</bitOffset>
  12115. <bitWidth>2</bitWidth>
  12116. </field>
  12117. </fields>
  12118. </register>
  12119. <register>
  12120. <name>SMPR</name>
  12121. <displayName>SMPR</displayName>
  12122. <description>sampling time register</description>
  12123. <addressOffset>0x14</addressOffset>
  12124. <size>0x20</size>
  12125. <access>read-write</access>
  12126. <resetValue>0x00000000</resetValue>
  12127. <fields>
  12128. <field>
  12129. <name>SMPR</name>
  12130. <description>Sampling time selection</description>
  12131. <bitOffset>0</bitOffset>
  12132. <bitWidth>3</bitWidth>
  12133. </field>
  12134. </fields>
  12135. </register>
  12136. <register>
  12137. <name>TR</name>
  12138. <displayName>TR</displayName>
  12139. <description>watchdog threshold register</description>
  12140. <addressOffset>0x20</addressOffset>
  12141. <size>0x20</size>
  12142. <access>read-write</access>
  12143. <resetValue>0x0FFF0000</resetValue>
  12144. <fields>
  12145. <field>
  12146. <name>HT</name>
  12147. <description>Analog watchdog higher
  12148. threshold</description>
  12149. <bitOffset>16</bitOffset>
  12150. <bitWidth>12</bitWidth>
  12151. </field>
  12152. <field>
  12153. <name>LT</name>
  12154. <description>Analog watchdog lower
  12155. threshold</description>
  12156. <bitOffset>0</bitOffset>
  12157. <bitWidth>12</bitWidth>
  12158. </field>
  12159. </fields>
  12160. </register>
  12161. <register>
  12162. <name>CHSELR</name>
  12163. <displayName>CHSELR</displayName>
  12164. <description>channel selection register</description>
  12165. <addressOffset>0x28</addressOffset>
  12166. <size>0x20</size>
  12167. <access>read-write</access>
  12168. <resetValue>0x00000000</resetValue>
  12169. <fields>
  12170. <field>
  12171. <name>CHSEL18</name>
  12172. <description>Channel-x selection</description>
  12173. <bitOffset>18</bitOffset>
  12174. <bitWidth>1</bitWidth>
  12175. </field>
  12176. <field>
  12177. <name>CHSEL17</name>
  12178. <description>Channel-x selection</description>
  12179. <bitOffset>17</bitOffset>
  12180. <bitWidth>1</bitWidth>
  12181. </field>
  12182. <field>
  12183. <name>CHSEL16</name>
  12184. <description>Channel-x selection</description>
  12185. <bitOffset>16</bitOffset>
  12186. <bitWidth>1</bitWidth>
  12187. </field>
  12188. <field>
  12189. <name>CHSEL15</name>
  12190. <description>Channel-x selection</description>
  12191. <bitOffset>15</bitOffset>
  12192. <bitWidth>1</bitWidth>
  12193. </field>
  12194. <field>
  12195. <name>CHSEL14</name>
  12196. <description>Channel-x selection</description>
  12197. <bitOffset>14</bitOffset>
  12198. <bitWidth>1</bitWidth>
  12199. </field>
  12200. <field>
  12201. <name>CHSEL13</name>
  12202. <description>Channel-x selection</description>
  12203. <bitOffset>13</bitOffset>
  12204. <bitWidth>1</bitWidth>
  12205. </field>
  12206. <field>
  12207. <name>CHSEL12</name>
  12208. <description>Channel-x selection</description>
  12209. <bitOffset>12</bitOffset>
  12210. <bitWidth>1</bitWidth>
  12211. </field>
  12212. <field>
  12213. <name>CHSEL11</name>
  12214. <description>Channel-x selection</description>
  12215. <bitOffset>11</bitOffset>
  12216. <bitWidth>1</bitWidth>
  12217. </field>
  12218. <field>
  12219. <name>CHSEL10</name>
  12220. <description>Channel-x selection</description>
  12221. <bitOffset>10</bitOffset>
  12222. <bitWidth>1</bitWidth>
  12223. </field>
  12224. <field>
  12225. <name>CHSEL9</name>
  12226. <description>Channel-x selection</description>
  12227. <bitOffset>9</bitOffset>
  12228. <bitWidth>1</bitWidth>
  12229. </field>
  12230. <field>
  12231. <name>CHSEL8</name>
  12232. <description>Channel-x selection</description>
  12233. <bitOffset>8</bitOffset>
  12234. <bitWidth>1</bitWidth>
  12235. </field>
  12236. <field>
  12237. <name>CHSEL7</name>
  12238. <description>Channel-x selection</description>
  12239. <bitOffset>7</bitOffset>
  12240. <bitWidth>1</bitWidth>
  12241. </field>
  12242. <field>
  12243. <name>CHSEL6</name>
  12244. <description>Channel-x selection</description>
  12245. <bitOffset>6</bitOffset>
  12246. <bitWidth>1</bitWidth>
  12247. </field>
  12248. <field>
  12249. <name>CHSEL5</name>
  12250. <description>Channel-x selection</description>
  12251. <bitOffset>5</bitOffset>
  12252. <bitWidth>1</bitWidth>
  12253. </field>
  12254. <field>
  12255. <name>CHSEL4</name>
  12256. <description>Channel-x selection</description>
  12257. <bitOffset>4</bitOffset>
  12258. <bitWidth>1</bitWidth>
  12259. </field>
  12260. <field>
  12261. <name>CHSEL3</name>
  12262. <description>Channel-x selection</description>
  12263. <bitOffset>3</bitOffset>
  12264. <bitWidth>1</bitWidth>
  12265. </field>
  12266. <field>
  12267. <name>CHSEL2</name>
  12268. <description>Channel-x selection</description>
  12269. <bitOffset>2</bitOffset>
  12270. <bitWidth>1</bitWidth>
  12271. </field>
  12272. <field>
  12273. <name>CHSEL1</name>
  12274. <description>Channel-x selection</description>
  12275. <bitOffset>1</bitOffset>
  12276. <bitWidth>1</bitWidth>
  12277. </field>
  12278. <field>
  12279. <name>CHSEL0</name>
  12280. <description>Channel-x selection</description>
  12281. <bitOffset>0</bitOffset>
  12282. <bitWidth>1</bitWidth>
  12283. </field>
  12284. </fields>
  12285. </register>
  12286. <register>
  12287. <name>DR</name>
  12288. <displayName>DR</displayName>
  12289. <description>data register</description>
  12290. <addressOffset>0x40</addressOffset>
  12291. <size>0x20</size>
  12292. <access>read-only</access>
  12293. <resetValue>0x00000000</resetValue>
  12294. <fields>
  12295. <field>
  12296. <name>DATA</name>
  12297. <description>Converted data</description>
  12298. <bitOffset>0</bitOffset>
  12299. <bitWidth>16</bitWidth>
  12300. </field>
  12301. </fields>
  12302. </register>
  12303. <register>
  12304. <name>CALFACT</name>
  12305. <displayName>CALFACT</displayName>
  12306. <description>ADC Calibration factor</description>
  12307. <addressOffset>0xB4</addressOffset>
  12308. <size>0x20</size>
  12309. <access>read-write</access>
  12310. <resetValue>0x00000000</resetValue>
  12311. <fields>
  12312. <field>
  12313. <name>CALFACT</name>
  12314. <description>Calibration factor</description>
  12315. <bitOffset>0</bitOffset>
  12316. <bitWidth>7</bitWidth>
  12317. </field>
  12318. </fields>
  12319. </register>
  12320. <register>
  12321. <name>CCR</name>
  12322. <displayName>CCR</displayName>
  12323. <description>ADC common configuration
  12324. register</description>
  12325. <addressOffset>0x308</addressOffset>
  12326. <size>0x20</size>
  12327. <access>read-write</access>
  12328. <resetValue>0x00000000</resetValue>
  12329. <fields>
  12330. <field>
  12331. <name>PRESC</name>
  12332. <description>ADC prescaler</description>
  12333. <bitOffset>18</bitOffset>
  12334. <bitWidth>4</bitWidth>
  12335. </field>
  12336. <field>
  12337. <name>VREFEN</name>
  12338. <description>VREFINT enable</description>
  12339. <bitOffset>22</bitOffset>
  12340. <bitWidth>1</bitWidth>
  12341. </field>
  12342. <field>
  12343. <name>TSEN</name>
  12344. <description>Temperature sensor enable</description>
  12345. <bitOffset>23</bitOffset>
  12346. <bitWidth>1</bitWidth>
  12347. </field>
  12348. <field>
  12349. <name>VLCDEN</name>
  12350. <description>VLCD enable</description>
  12351. <bitOffset>24</bitOffset>
  12352. <bitWidth>1</bitWidth>
  12353. </field>
  12354. <field>
  12355. <name>LFMEN</name>
  12356. <description>Low Frequency Mode enable</description>
  12357. <bitOffset>25</bitOffset>
  12358. <bitWidth>1</bitWidth>
  12359. </field>
  12360. </fields>
  12361. </register>
  12362. </registers>
  12363. </peripheral>
  12364. <peripheral>
  12365. <name>DBG</name>
  12366. <description>Debug support</description>
  12367. <groupName>DBGMCU</groupName>
  12368. <baseAddress>0x40015800</baseAddress>
  12369. <addressBlock>
  12370. <offset>0x0</offset>
  12371. <size>0x400</size>
  12372. <usage>registers</usage>
  12373. </addressBlock>
  12374. <registers>
  12375. <register>
  12376. <name>IDCODE</name>
  12377. <displayName>IDCODE</displayName>
  12378. <description>MCU Device ID Code Register</description>
  12379. <addressOffset>0x0</addressOffset>
  12380. <size>0x20</size>
  12381. <access>read-only</access>
  12382. <resetValue>0x0</resetValue>
  12383. <fields>
  12384. <field>
  12385. <name>DEV_ID</name>
  12386. <description>Device Identifier</description>
  12387. <bitOffset>0</bitOffset>
  12388. <bitWidth>12</bitWidth>
  12389. </field>
  12390. <field>
  12391. <name>REV_ID</name>
  12392. <description>Revision Identifier</description>
  12393. <bitOffset>16</bitOffset>
  12394. <bitWidth>16</bitWidth>
  12395. </field>
  12396. </fields>
  12397. </register>
  12398. <register>
  12399. <name>CR</name>
  12400. <displayName>CR</displayName>
  12401. <description>Debug MCU Configuration
  12402. Register</description>
  12403. <addressOffset>0x4</addressOffset>
  12404. <size>0x20</size>
  12405. <access>read-write</access>
  12406. <resetValue>0x0</resetValue>
  12407. <fields>
  12408. <field>
  12409. <name>DBG_STOP</name>
  12410. <description>Debug Stop Mode</description>
  12411. <bitOffset>1</bitOffset>
  12412. <bitWidth>1</bitWidth>
  12413. </field>
  12414. <field>
  12415. <name>DBG_STANDBY</name>
  12416. <description>Debug Standby Mode</description>
  12417. <bitOffset>2</bitOffset>
  12418. <bitWidth>1</bitWidth>
  12419. </field>
  12420. <field>
  12421. <name>DBG_SLEEP</name>
  12422. <description>Debug Sleep Mode</description>
  12423. <bitOffset>0</bitOffset>
  12424. <bitWidth>1</bitWidth>
  12425. </field>
  12426. </fields>
  12427. </register>
  12428. <register>
  12429. <name>APB1_FZ</name>
  12430. <displayName>APB1_FZ</displayName>
  12431. <description>APB Low Freeze Register</description>
  12432. <addressOffset>0x8</addressOffset>
  12433. <size>0x20</size>
  12434. <access>read-write</access>
  12435. <resetValue>0x0</resetValue>
  12436. <fields>
  12437. <field>
  12438. <name>DBG_TIMER2_STOP</name>
  12439. <description>Debug Timer 2 stopped when Core is
  12440. halted</description>
  12441. <bitOffset>0</bitOffset>
  12442. <bitWidth>1</bitWidth>
  12443. </field>
  12444. <field>
  12445. <name>DBG_TIMER6_STOP</name>
  12446. <description>Debug Timer 6 stopped when Core is
  12447. halted</description>
  12448. <bitOffset>4</bitOffset>
  12449. <bitWidth>1</bitWidth>
  12450. </field>
  12451. <field>
  12452. <name>DBG_RTC_STOP</name>
  12453. <description>Debug RTC stopped when Core is
  12454. halted</description>
  12455. <bitOffset>10</bitOffset>
  12456. <bitWidth>1</bitWidth>
  12457. </field>
  12458. <field>
  12459. <name>DBG_WWDG_STOP</name>
  12460. <description>Debug Window Wachdog stopped when Core
  12461. is halted</description>
  12462. <bitOffset>11</bitOffset>
  12463. <bitWidth>1</bitWidth>
  12464. </field>
  12465. <field>
  12466. <name>DBG_IWDG_STOP</name>
  12467. <description>Debug Independent Wachdog stopped when
  12468. Core is halted</description>
  12469. <bitOffset>12</bitOffset>
  12470. <bitWidth>1</bitWidth>
  12471. </field>
  12472. <field>
  12473. <name>DBG_I2C1_STOP</name>
  12474. <description>I2C1 SMBUS timeout mode stopped when
  12475. core is halted</description>
  12476. <bitOffset>21</bitOffset>
  12477. <bitWidth>1</bitWidth>
  12478. </field>
  12479. <field>
  12480. <name>DBG_I2C2_STOP</name>
  12481. <description>I2C2 SMBUS timeout mode stopped when
  12482. core is halted</description>
  12483. <bitOffset>22</bitOffset>
  12484. <bitWidth>1</bitWidth>
  12485. </field>
  12486. <field>
  12487. <name>DBG_I2C3_STOP</name>
  12488. <description>I2C3 SMBUS timeout mode stopped when
  12489. core is halted</description>
  12490. <bitOffset>30</bitOffset>
  12491. <bitWidth>1</bitWidth>
  12492. </field>
  12493. <field>
  12494. <name>DBG_LPTIMER_STOP</name>
  12495. <description>LPTIM1 counter stopped when core is
  12496. halted</description>
  12497. <bitOffset>31</bitOffset>
  12498. <bitWidth>1</bitWidth>
  12499. </field>
  12500. </fields>
  12501. </register>
  12502. <register>
  12503. <name>APB2_FZ</name>
  12504. <displayName>APB2_FZ</displayName>
  12505. <description>APB High Freeze Register</description>
  12506. <addressOffset>0xC</addressOffset>
  12507. <size>0x20</size>
  12508. <access>read-write</access>
  12509. <resetValue>0x0</resetValue>
  12510. <fields>
  12511. <field>
  12512. <name>DBG_TIMER21_STOP</name>
  12513. <description>Debug Timer 21 stopped when Core is
  12514. halted</description>
  12515. <bitOffset>2</bitOffset>
  12516. <bitWidth>1</bitWidth>
  12517. </field>
  12518. <field>
  12519. <name>DBG_TIMER22_STOP</name>
  12520. <description>Debug Timer 22 stopped when Core is
  12521. halted</description>
  12522. <bitOffset>5</bitOffset>
  12523. <bitWidth>1</bitWidth>
  12524. </field>
  12525. </fields>
  12526. </register>
  12527. </registers>
  12528. </peripheral>
  12529. <peripheral>
  12530. <name>TIM2</name>
  12531. <description>General-purpose-timers</description>
  12532. <groupName>TIM</groupName>
  12533. <baseAddress>0x40000000</baseAddress>
  12534. <addressBlock>
  12535. <offset>0x0</offset>
  12536. <size>0x400</size>
  12537. <usage>registers</usage>
  12538. </addressBlock>
  12539. <interrupt>
  12540. <name>TIM2</name>
  12541. <description>TIM2 global interrupt</description>
  12542. <value>15</value>
  12543. </interrupt>
  12544. <registers>
  12545. <register>
  12546. <name>CR1</name>
  12547. <displayName>CR1</displayName>
  12548. <description>control register 1</description>
  12549. <addressOffset>0x0</addressOffset>
  12550. <size>0x20</size>
  12551. <access>read-write</access>
  12552. <resetValue>0x0000</resetValue>
  12553. <fields>
  12554. <field>
  12555. <name>CKD</name>
  12556. <description>Clock division</description>
  12557. <bitOffset>8</bitOffset>
  12558. <bitWidth>2</bitWidth>
  12559. </field>
  12560. <field>
  12561. <name>ARPE</name>
  12562. <description>Auto-reload preload enable</description>
  12563. <bitOffset>7</bitOffset>
  12564. <bitWidth>1</bitWidth>
  12565. </field>
  12566. <field>
  12567. <name>CMS</name>
  12568. <description>Center-aligned mode
  12569. selection</description>
  12570. <bitOffset>5</bitOffset>
  12571. <bitWidth>2</bitWidth>
  12572. </field>
  12573. <field>
  12574. <name>DIR</name>
  12575. <description>Direction</description>
  12576. <bitOffset>4</bitOffset>
  12577. <bitWidth>1</bitWidth>
  12578. </field>
  12579. <field>
  12580. <name>OPM</name>
  12581. <description>One-pulse mode</description>
  12582. <bitOffset>3</bitOffset>
  12583. <bitWidth>1</bitWidth>
  12584. </field>
  12585. <field>
  12586. <name>URS</name>
  12587. <description>Update request source</description>
  12588. <bitOffset>2</bitOffset>
  12589. <bitWidth>1</bitWidth>
  12590. </field>
  12591. <field>
  12592. <name>UDIS</name>
  12593. <description>Update disable</description>
  12594. <bitOffset>1</bitOffset>
  12595. <bitWidth>1</bitWidth>
  12596. </field>
  12597. <field>
  12598. <name>CEN</name>
  12599. <description>Counter enable</description>
  12600. <bitOffset>0</bitOffset>
  12601. <bitWidth>1</bitWidth>
  12602. </field>
  12603. </fields>
  12604. </register>
  12605. <register>
  12606. <name>CR2</name>
  12607. <displayName>CR2</displayName>
  12608. <description>control register 2</description>
  12609. <addressOffset>0x4</addressOffset>
  12610. <size>0x20</size>
  12611. <access>read-write</access>
  12612. <resetValue>0x0000</resetValue>
  12613. <fields>
  12614. <field>
  12615. <name>TI1S</name>
  12616. <description>TI1 selection</description>
  12617. <bitOffset>7</bitOffset>
  12618. <bitWidth>1</bitWidth>
  12619. </field>
  12620. <field>
  12621. <name>MMS</name>
  12622. <description>Master mode selection</description>
  12623. <bitOffset>4</bitOffset>
  12624. <bitWidth>3</bitWidth>
  12625. </field>
  12626. <field>
  12627. <name>CCDS</name>
  12628. <description>Capture/compare DMA
  12629. selection</description>
  12630. <bitOffset>3</bitOffset>
  12631. <bitWidth>1</bitWidth>
  12632. </field>
  12633. </fields>
  12634. </register>
  12635. <register>
  12636. <name>SMCR</name>
  12637. <displayName>SMCR</displayName>
  12638. <description>slave mode control register</description>
  12639. <addressOffset>0x8</addressOffset>
  12640. <size>0x20</size>
  12641. <access>read-write</access>
  12642. <resetValue>0x0000</resetValue>
  12643. <fields>
  12644. <field>
  12645. <name>ETP</name>
  12646. <description>External trigger polarity</description>
  12647. <bitOffset>15</bitOffset>
  12648. <bitWidth>1</bitWidth>
  12649. </field>
  12650. <field>
  12651. <name>ECE</name>
  12652. <description>External clock enable</description>
  12653. <bitOffset>14</bitOffset>
  12654. <bitWidth>1</bitWidth>
  12655. </field>
  12656. <field>
  12657. <name>ETPS</name>
  12658. <description>External trigger prescaler</description>
  12659. <bitOffset>12</bitOffset>
  12660. <bitWidth>2</bitWidth>
  12661. </field>
  12662. <field>
  12663. <name>ETF</name>
  12664. <description>External trigger filter</description>
  12665. <bitOffset>8</bitOffset>
  12666. <bitWidth>4</bitWidth>
  12667. </field>
  12668. <field>
  12669. <name>MSM</name>
  12670. <description>Master/Slave mode</description>
  12671. <bitOffset>7</bitOffset>
  12672. <bitWidth>1</bitWidth>
  12673. </field>
  12674. <field>
  12675. <name>TS</name>
  12676. <description>Trigger selection</description>
  12677. <bitOffset>4</bitOffset>
  12678. <bitWidth>3</bitWidth>
  12679. </field>
  12680. <field>
  12681. <name>SMS</name>
  12682. <description>Slave mode selection</description>
  12683. <bitOffset>0</bitOffset>
  12684. <bitWidth>3</bitWidth>
  12685. </field>
  12686. </fields>
  12687. </register>
  12688. <register>
  12689. <name>DIER</name>
  12690. <displayName>DIER</displayName>
  12691. <description>DMA/Interrupt enable register</description>
  12692. <addressOffset>0xC</addressOffset>
  12693. <size>0x20</size>
  12694. <access>read-write</access>
  12695. <resetValue>0x0000</resetValue>
  12696. <fields>
  12697. <field>
  12698. <name>TDE</name>
  12699. <description>Trigger DMA request enable</description>
  12700. <bitOffset>14</bitOffset>
  12701. <bitWidth>1</bitWidth>
  12702. </field>
  12703. <field>
  12704. <name>COMDE</name>
  12705. <description>Reserved</description>
  12706. <bitOffset>13</bitOffset>
  12707. <bitWidth>1</bitWidth>
  12708. </field>
  12709. <field>
  12710. <name>CC4DE</name>
  12711. <description>Capture/Compare 4 DMA request
  12712. enable</description>
  12713. <bitOffset>12</bitOffset>
  12714. <bitWidth>1</bitWidth>
  12715. </field>
  12716. <field>
  12717. <name>CC3DE</name>
  12718. <description>Capture/Compare 3 DMA request
  12719. enable</description>
  12720. <bitOffset>11</bitOffset>
  12721. <bitWidth>1</bitWidth>
  12722. </field>
  12723. <field>
  12724. <name>CC2DE</name>
  12725. <description>Capture/Compare 2 DMA request
  12726. enable</description>
  12727. <bitOffset>10</bitOffset>
  12728. <bitWidth>1</bitWidth>
  12729. </field>
  12730. <field>
  12731. <name>CC1DE</name>
  12732. <description>Capture/Compare 1 DMA request
  12733. enable</description>
  12734. <bitOffset>9</bitOffset>
  12735. <bitWidth>1</bitWidth>
  12736. </field>
  12737. <field>
  12738. <name>UDE</name>
  12739. <description>Update DMA request enable</description>
  12740. <bitOffset>8</bitOffset>
  12741. <bitWidth>1</bitWidth>
  12742. </field>
  12743. <field>
  12744. <name>TIE</name>
  12745. <description>Trigger interrupt enable</description>
  12746. <bitOffset>6</bitOffset>
  12747. <bitWidth>1</bitWidth>
  12748. </field>
  12749. <field>
  12750. <name>CC4IE</name>
  12751. <description>Capture/Compare 4 interrupt
  12752. enable</description>
  12753. <bitOffset>4</bitOffset>
  12754. <bitWidth>1</bitWidth>
  12755. </field>
  12756. <field>
  12757. <name>CC3IE</name>
  12758. <description>Capture/Compare 3 interrupt
  12759. enable</description>
  12760. <bitOffset>3</bitOffset>
  12761. <bitWidth>1</bitWidth>
  12762. </field>
  12763. <field>
  12764. <name>CC2IE</name>
  12765. <description>Capture/Compare 2 interrupt
  12766. enable</description>
  12767. <bitOffset>2</bitOffset>
  12768. <bitWidth>1</bitWidth>
  12769. </field>
  12770. <field>
  12771. <name>CC1IE</name>
  12772. <description>Capture/Compare 1 interrupt
  12773. enable</description>
  12774. <bitOffset>1</bitOffset>
  12775. <bitWidth>1</bitWidth>
  12776. </field>
  12777. <field>
  12778. <name>UIE</name>
  12779. <description>Update interrupt enable</description>
  12780. <bitOffset>0</bitOffset>
  12781. <bitWidth>1</bitWidth>
  12782. </field>
  12783. </fields>
  12784. </register>
  12785. <register>
  12786. <name>SR</name>
  12787. <displayName>SR</displayName>
  12788. <description>status register</description>
  12789. <addressOffset>0x10</addressOffset>
  12790. <size>0x20</size>
  12791. <access>read-write</access>
  12792. <resetValue>0x0000</resetValue>
  12793. <fields>
  12794. <field>
  12795. <name>CC4OF</name>
  12796. <description>Capture/Compare 4 overcapture
  12797. flag</description>
  12798. <bitOffset>12</bitOffset>
  12799. <bitWidth>1</bitWidth>
  12800. </field>
  12801. <field>
  12802. <name>CC3OF</name>
  12803. <description>Capture/Compare 3 overcapture
  12804. flag</description>
  12805. <bitOffset>11</bitOffset>
  12806. <bitWidth>1</bitWidth>
  12807. </field>
  12808. <field>
  12809. <name>CC2OF</name>
  12810. <description>Capture/compare 2 overcapture
  12811. flag</description>
  12812. <bitOffset>10</bitOffset>
  12813. <bitWidth>1</bitWidth>
  12814. </field>
  12815. <field>
  12816. <name>CC1OF</name>
  12817. <description>Capture/Compare 1 overcapture
  12818. flag</description>
  12819. <bitOffset>9</bitOffset>
  12820. <bitWidth>1</bitWidth>
  12821. </field>
  12822. <field>
  12823. <name>TIF</name>
  12824. <description>Trigger interrupt flag</description>
  12825. <bitOffset>6</bitOffset>
  12826. <bitWidth>1</bitWidth>
  12827. </field>
  12828. <field>
  12829. <name>CC4IF</name>
  12830. <description>Capture/Compare 4 interrupt
  12831. flag</description>
  12832. <bitOffset>4</bitOffset>
  12833. <bitWidth>1</bitWidth>
  12834. </field>
  12835. <field>
  12836. <name>CC3IF</name>
  12837. <description>Capture/Compare 3 interrupt
  12838. flag</description>
  12839. <bitOffset>3</bitOffset>
  12840. <bitWidth>1</bitWidth>
  12841. </field>
  12842. <field>
  12843. <name>CC2IF</name>
  12844. <description>Capture/Compare 2 interrupt
  12845. flag</description>
  12846. <bitOffset>2</bitOffset>
  12847. <bitWidth>1</bitWidth>
  12848. </field>
  12849. <field>
  12850. <name>CC1IF</name>
  12851. <description>Capture/compare 1 interrupt
  12852. flag</description>
  12853. <bitOffset>1</bitOffset>
  12854. <bitWidth>1</bitWidth>
  12855. </field>
  12856. <field>
  12857. <name>UIF</name>
  12858. <description>Update interrupt flag</description>
  12859. <bitOffset>0</bitOffset>
  12860. <bitWidth>1</bitWidth>
  12861. </field>
  12862. </fields>
  12863. </register>
  12864. <register>
  12865. <name>EGR</name>
  12866. <displayName>EGR</displayName>
  12867. <description>event generation register</description>
  12868. <addressOffset>0x14</addressOffset>
  12869. <size>0x20</size>
  12870. <access>write-only</access>
  12871. <resetValue>0x0000</resetValue>
  12872. <fields>
  12873. <field>
  12874. <name>TG</name>
  12875. <description>Trigger generation</description>
  12876. <bitOffset>6</bitOffset>
  12877. <bitWidth>1</bitWidth>
  12878. </field>
  12879. <field>
  12880. <name>CC4G</name>
  12881. <description>Capture/compare 4
  12882. generation</description>
  12883. <bitOffset>4</bitOffset>
  12884. <bitWidth>1</bitWidth>
  12885. </field>
  12886. <field>
  12887. <name>CC3G</name>
  12888. <description>Capture/compare 3
  12889. generation</description>
  12890. <bitOffset>3</bitOffset>
  12891. <bitWidth>1</bitWidth>
  12892. </field>
  12893. <field>
  12894. <name>CC2G</name>
  12895. <description>Capture/compare 2
  12896. generation</description>
  12897. <bitOffset>2</bitOffset>
  12898. <bitWidth>1</bitWidth>
  12899. </field>
  12900. <field>
  12901. <name>CC1G</name>
  12902. <description>Capture/compare 1
  12903. generation</description>
  12904. <bitOffset>1</bitOffset>
  12905. <bitWidth>1</bitWidth>
  12906. </field>
  12907. <field>
  12908. <name>UG</name>
  12909. <description>Update generation</description>
  12910. <bitOffset>0</bitOffset>
  12911. <bitWidth>1</bitWidth>
  12912. </field>
  12913. </fields>
  12914. </register>
  12915. <register>
  12916. <name>CCMR1_Output</name>
  12917. <displayName>CCMR1_Output</displayName>
  12918. <description>capture/compare mode register 1 (output
  12919. mode)</description>
  12920. <addressOffset>0x18</addressOffset>
  12921. <size>0x20</size>
  12922. <access>read-write</access>
  12923. <resetValue>0x00000000</resetValue>
  12924. <fields>
  12925. <field>
  12926. <name>OC2CE</name>
  12927. <description>Output compare 2 clear
  12928. enable</description>
  12929. <bitOffset>15</bitOffset>
  12930. <bitWidth>1</bitWidth>
  12931. </field>
  12932. <field>
  12933. <name>OC2M</name>
  12934. <description>Output compare 2 mode</description>
  12935. <bitOffset>12</bitOffset>
  12936. <bitWidth>3</bitWidth>
  12937. </field>
  12938. <field>
  12939. <name>OC2PE</name>
  12940. <description>Output compare 2 preload
  12941. enable</description>
  12942. <bitOffset>11</bitOffset>
  12943. <bitWidth>1</bitWidth>
  12944. </field>
  12945. <field>
  12946. <name>OC2FE</name>
  12947. <description>Output compare 2 fast
  12948. enable</description>
  12949. <bitOffset>10</bitOffset>
  12950. <bitWidth>1</bitWidth>
  12951. </field>
  12952. <field>
  12953. <name>CC2S</name>
  12954. <description>Capture/Compare 2
  12955. selection</description>
  12956. <bitOffset>8</bitOffset>
  12957. <bitWidth>2</bitWidth>
  12958. </field>
  12959. <field>
  12960. <name>OC1CE</name>
  12961. <description>Output compare 1 clear
  12962. enable</description>
  12963. <bitOffset>7</bitOffset>
  12964. <bitWidth>1</bitWidth>
  12965. </field>
  12966. <field>
  12967. <name>OC1M</name>
  12968. <description>Output compare 1 mode</description>
  12969. <bitOffset>4</bitOffset>
  12970. <bitWidth>3</bitWidth>
  12971. </field>
  12972. <field>
  12973. <name>OC1PE</name>
  12974. <description>Output compare 1 preload
  12975. enable</description>
  12976. <bitOffset>3</bitOffset>
  12977. <bitWidth>1</bitWidth>
  12978. </field>
  12979. <field>
  12980. <name>OC1FE</name>
  12981. <description>Output compare 1 fast
  12982. enable</description>
  12983. <bitOffset>2</bitOffset>
  12984. <bitWidth>1</bitWidth>
  12985. </field>
  12986. <field>
  12987. <name>CC1S</name>
  12988. <description>Capture/Compare 1
  12989. selection</description>
  12990. <bitOffset>0</bitOffset>
  12991. <bitWidth>2</bitWidth>
  12992. </field>
  12993. </fields>
  12994. </register>
  12995. <register>
  12996. <name>CCMR1_Input</name>
  12997. <displayName>CCMR1_Input</displayName>
  12998. <description>capture/compare mode register 1 (input
  12999. mode)</description>
  13000. <alternateRegister>CCMR1_Output</alternateRegister>
  13001. <addressOffset>0x18</addressOffset>
  13002. <size>0x20</size>
  13003. <access>read-write</access>
  13004. <resetValue>0x00000000</resetValue>
  13005. <fields>
  13006. <field>
  13007. <name>IC2F</name>
  13008. <description>Input capture 2 filter</description>
  13009. <bitOffset>12</bitOffset>
  13010. <bitWidth>4</bitWidth>
  13011. </field>
  13012. <field>
  13013. <name>IC2PSC</name>
  13014. <description>Input capture 2 prescaler</description>
  13015. <bitOffset>10</bitOffset>
  13016. <bitWidth>2</bitWidth>
  13017. </field>
  13018. <field>
  13019. <name>CC2S</name>
  13020. <description>Capture/compare 2
  13021. selection</description>
  13022. <bitOffset>8</bitOffset>
  13023. <bitWidth>2</bitWidth>
  13024. </field>
  13025. <field>
  13026. <name>IC1F</name>
  13027. <description>Input capture 1 filter</description>
  13028. <bitOffset>4</bitOffset>
  13029. <bitWidth>4</bitWidth>
  13030. </field>
  13031. <field>
  13032. <name>IC1PSC</name>
  13033. <description>Input capture 1 prescaler</description>
  13034. <bitOffset>2</bitOffset>
  13035. <bitWidth>2</bitWidth>
  13036. </field>
  13037. <field>
  13038. <name>CC1S</name>
  13039. <description>Capture/Compare 1
  13040. selection</description>
  13041. <bitOffset>0</bitOffset>
  13042. <bitWidth>2</bitWidth>
  13043. </field>
  13044. </fields>
  13045. </register>
  13046. <register>
  13047. <name>CCMR2_Output</name>
  13048. <displayName>CCMR2_Output</displayName>
  13049. <description>capture/compare mode register 2 (output
  13050. mode)</description>
  13051. <addressOffset>0x1C</addressOffset>
  13052. <size>0x20</size>
  13053. <access>read-write</access>
  13054. <resetValue>0x00000000</resetValue>
  13055. <fields>
  13056. <field>
  13057. <name>OC4CE</name>
  13058. <description>Output compare 4 clear
  13059. enable</description>
  13060. <bitOffset>15</bitOffset>
  13061. <bitWidth>1</bitWidth>
  13062. </field>
  13063. <field>
  13064. <name>OC4M</name>
  13065. <description>Output compare 4 mode</description>
  13066. <bitOffset>12</bitOffset>
  13067. <bitWidth>3</bitWidth>
  13068. </field>
  13069. <field>
  13070. <name>OC4PE</name>
  13071. <description>Output compare 4 preload
  13072. enable</description>
  13073. <bitOffset>11</bitOffset>
  13074. <bitWidth>1</bitWidth>
  13075. </field>
  13076. <field>
  13077. <name>OC4FE</name>
  13078. <description>Output compare 4 fast
  13079. enable</description>
  13080. <bitOffset>10</bitOffset>
  13081. <bitWidth>1</bitWidth>
  13082. </field>
  13083. <field>
  13084. <name>CC4S</name>
  13085. <description>Capture/Compare 4
  13086. selection</description>
  13087. <bitOffset>8</bitOffset>
  13088. <bitWidth>2</bitWidth>
  13089. </field>
  13090. <field>
  13091. <name>OC3CE</name>
  13092. <description>Output compare 3 clear
  13093. enable</description>
  13094. <bitOffset>7</bitOffset>
  13095. <bitWidth>1</bitWidth>
  13096. </field>
  13097. <field>
  13098. <name>OC3M</name>
  13099. <description>Output compare 3 mode</description>
  13100. <bitOffset>4</bitOffset>
  13101. <bitWidth>3</bitWidth>
  13102. </field>
  13103. <field>
  13104. <name>OC3PE</name>
  13105. <description>Output compare 3 preload
  13106. enable</description>
  13107. <bitOffset>3</bitOffset>
  13108. <bitWidth>1</bitWidth>
  13109. </field>
  13110. <field>
  13111. <name>OC3FE</name>
  13112. <description>Output compare 3 fast
  13113. enable</description>
  13114. <bitOffset>2</bitOffset>
  13115. <bitWidth>1</bitWidth>
  13116. </field>
  13117. <field>
  13118. <name>CC3S</name>
  13119. <description>Capture/Compare 3
  13120. selection</description>
  13121. <bitOffset>0</bitOffset>
  13122. <bitWidth>2</bitWidth>
  13123. </field>
  13124. </fields>
  13125. </register>
  13126. <register>
  13127. <name>CCMR2_Input</name>
  13128. <displayName>CCMR2_Input</displayName>
  13129. <description>capture/compare mode register 2 (input
  13130. mode)</description>
  13131. <alternateRegister>CCMR2_Output</alternateRegister>
  13132. <addressOffset>0x1C</addressOffset>
  13133. <size>0x20</size>
  13134. <access>read-write</access>
  13135. <resetValue>0x00000000</resetValue>
  13136. <fields>
  13137. <field>
  13138. <name>IC4F</name>
  13139. <description>Input capture 4 filter</description>
  13140. <bitOffset>12</bitOffset>
  13141. <bitWidth>4</bitWidth>
  13142. </field>
  13143. <field>
  13144. <name>IC4PSC</name>
  13145. <description>Input capture 4 prescaler</description>
  13146. <bitOffset>10</bitOffset>
  13147. <bitWidth>2</bitWidth>
  13148. </field>
  13149. <field>
  13150. <name>CC4S</name>
  13151. <description>Capture/Compare 4
  13152. selection</description>
  13153. <bitOffset>8</bitOffset>
  13154. <bitWidth>2</bitWidth>
  13155. </field>
  13156. <field>
  13157. <name>IC3F</name>
  13158. <description>Input capture 3 filter</description>
  13159. <bitOffset>4</bitOffset>
  13160. <bitWidth>4</bitWidth>
  13161. </field>
  13162. <field>
  13163. <name>IC3PSC</name>
  13164. <description>Input capture 3 prescaler</description>
  13165. <bitOffset>2</bitOffset>
  13166. <bitWidth>2</bitWidth>
  13167. </field>
  13168. <field>
  13169. <name>CC3S</name>
  13170. <description>Capture/Compare 3
  13171. selection</description>
  13172. <bitOffset>0</bitOffset>
  13173. <bitWidth>2</bitWidth>
  13174. </field>
  13175. </fields>
  13176. </register>
  13177. <register>
  13178. <name>CCER</name>
  13179. <displayName>CCER</displayName>
  13180. <description>capture/compare enable
  13181. register</description>
  13182. <addressOffset>0x20</addressOffset>
  13183. <size>0x20</size>
  13184. <access>read-write</access>
  13185. <resetValue>0x0000</resetValue>
  13186. <fields>
  13187. <field>
  13188. <name>CC4NP</name>
  13189. <description>Capture/Compare 4 output
  13190. Polarity</description>
  13191. <bitOffset>15</bitOffset>
  13192. <bitWidth>1</bitWidth>
  13193. </field>
  13194. <field>
  13195. <name>CC4P</name>
  13196. <description>Capture/Compare 3 output
  13197. Polarity</description>
  13198. <bitOffset>13</bitOffset>
  13199. <bitWidth>1</bitWidth>
  13200. </field>
  13201. <field>
  13202. <name>CC4E</name>
  13203. <description>Capture/Compare 4 output
  13204. enable</description>
  13205. <bitOffset>12</bitOffset>
  13206. <bitWidth>1</bitWidth>
  13207. </field>
  13208. <field>
  13209. <name>CC3NP</name>
  13210. <description>Capture/Compare 3 output
  13211. Polarity</description>
  13212. <bitOffset>11</bitOffset>
  13213. <bitWidth>1</bitWidth>
  13214. </field>
  13215. <field>
  13216. <name>CC3P</name>
  13217. <description>Capture/Compare 3 output
  13218. Polarity</description>
  13219. <bitOffset>9</bitOffset>
  13220. <bitWidth>1</bitWidth>
  13221. </field>
  13222. <field>
  13223. <name>CC3E</name>
  13224. <description>Capture/Compare 3 output
  13225. enable</description>
  13226. <bitOffset>8</bitOffset>
  13227. <bitWidth>1</bitWidth>
  13228. </field>
  13229. <field>
  13230. <name>CC2NP</name>
  13231. <description>Capture/Compare 2 output
  13232. Polarity</description>
  13233. <bitOffset>7</bitOffset>
  13234. <bitWidth>1</bitWidth>
  13235. </field>
  13236. <field>
  13237. <name>CC2P</name>
  13238. <description>Capture/Compare 2 output
  13239. Polarity</description>
  13240. <bitOffset>5</bitOffset>
  13241. <bitWidth>1</bitWidth>
  13242. </field>
  13243. <field>
  13244. <name>CC2E</name>
  13245. <description>Capture/Compare 2 output
  13246. enable</description>
  13247. <bitOffset>4</bitOffset>
  13248. <bitWidth>1</bitWidth>
  13249. </field>
  13250. <field>
  13251. <name>CC1NP</name>
  13252. <description>Capture/Compare 1 output
  13253. Polarity</description>
  13254. <bitOffset>3</bitOffset>
  13255. <bitWidth>1</bitWidth>
  13256. </field>
  13257. <field>
  13258. <name>CC1P</name>
  13259. <description>Capture/Compare 1 output
  13260. Polarity</description>
  13261. <bitOffset>1</bitOffset>
  13262. <bitWidth>1</bitWidth>
  13263. </field>
  13264. <field>
  13265. <name>CC1E</name>
  13266. <description>Capture/Compare 1 output
  13267. enable</description>
  13268. <bitOffset>0</bitOffset>
  13269. <bitWidth>1</bitWidth>
  13270. </field>
  13271. </fields>
  13272. </register>
  13273. <register>
  13274. <name>CNT</name>
  13275. <displayName>CNT</displayName>
  13276. <description>counter</description>
  13277. <addressOffset>0x24</addressOffset>
  13278. <size>0x20</size>
  13279. <access>read-write</access>
  13280. <resetValue>0x00000000</resetValue>
  13281. <fields>
  13282. <field>
  13283. <name>CNT_H</name>
  13284. <description>High counter value (TIM2
  13285. only)</description>
  13286. <bitOffset>16</bitOffset>
  13287. <bitWidth>16</bitWidth>
  13288. </field>
  13289. <field>
  13290. <name>CNT_L</name>
  13291. <description>Low counter value</description>
  13292. <bitOffset>0</bitOffset>
  13293. <bitWidth>16</bitWidth>
  13294. </field>
  13295. </fields>
  13296. </register>
  13297. <register>
  13298. <name>PSC</name>
  13299. <displayName>PSC</displayName>
  13300. <description>prescaler</description>
  13301. <addressOffset>0x28</addressOffset>
  13302. <size>0x20</size>
  13303. <access>read-write</access>
  13304. <resetValue>0x0000</resetValue>
  13305. <fields>
  13306. <field>
  13307. <name>PSC</name>
  13308. <description>Prescaler value</description>
  13309. <bitOffset>0</bitOffset>
  13310. <bitWidth>16</bitWidth>
  13311. </field>
  13312. </fields>
  13313. </register>
  13314. <register>
  13315. <name>ARR</name>
  13316. <displayName>ARR</displayName>
  13317. <description>auto-reload register</description>
  13318. <addressOffset>0x2C</addressOffset>
  13319. <size>0x20</size>
  13320. <access>read-write</access>
  13321. <resetValue>0x00000000</resetValue>
  13322. <fields>
  13323. <field>
  13324. <name>ARR_H</name>
  13325. <description>High Auto-reload value (TIM2
  13326. only)</description>
  13327. <bitOffset>16</bitOffset>
  13328. <bitWidth>16</bitWidth>
  13329. </field>
  13330. <field>
  13331. <name>ARR_L</name>
  13332. <description>Low Auto-reload value</description>
  13333. <bitOffset>0</bitOffset>
  13334. <bitWidth>16</bitWidth>
  13335. </field>
  13336. </fields>
  13337. </register>
  13338. <register>
  13339. <name>CCR1</name>
  13340. <displayName>CCR1</displayName>
  13341. <description>capture/compare register 1</description>
  13342. <addressOffset>0x34</addressOffset>
  13343. <size>0x20</size>
  13344. <access>read-write</access>
  13345. <resetValue>0x00000000</resetValue>
  13346. <fields>
  13347. <field>
  13348. <name>CCR1_H</name>
  13349. <description>High Capture/Compare 1 value (TIM2
  13350. only)</description>
  13351. <bitOffset>16</bitOffset>
  13352. <bitWidth>16</bitWidth>
  13353. </field>
  13354. <field>
  13355. <name>CCR1_L</name>
  13356. <description>Low Capture/Compare 1
  13357. value</description>
  13358. <bitOffset>0</bitOffset>
  13359. <bitWidth>16</bitWidth>
  13360. </field>
  13361. </fields>
  13362. </register>
  13363. <register>
  13364. <name>CCR2</name>
  13365. <displayName>CCR2</displayName>
  13366. <description>capture/compare register 2</description>
  13367. <addressOffset>0x38</addressOffset>
  13368. <size>0x20</size>
  13369. <access>read-write</access>
  13370. <resetValue>0x00000000</resetValue>
  13371. <fields>
  13372. <field>
  13373. <name>CCR2_H</name>
  13374. <description>High Capture/Compare 2 value (TIM2
  13375. only)</description>
  13376. <bitOffset>16</bitOffset>
  13377. <bitWidth>16</bitWidth>
  13378. </field>
  13379. <field>
  13380. <name>CCR2_L</name>
  13381. <description>Low Capture/Compare 2
  13382. value</description>
  13383. <bitOffset>0</bitOffset>
  13384. <bitWidth>16</bitWidth>
  13385. </field>
  13386. </fields>
  13387. </register>
  13388. <register>
  13389. <name>CCR3</name>
  13390. <displayName>CCR3</displayName>
  13391. <description>capture/compare register 3</description>
  13392. <addressOffset>0x3C</addressOffset>
  13393. <size>0x20</size>
  13394. <access>read-write</access>
  13395. <resetValue>0x00000000</resetValue>
  13396. <fields>
  13397. <field>
  13398. <name>CCR3_H</name>
  13399. <description>High Capture/Compare value (TIM2
  13400. only)</description>
  13401. <bitOffset>16</bitOffset>
  13402. <bitWidth>16</bitWidth>
  13403. </field>
  13404. <field>
  13405. <name>CCR3_L</name>
  13406. <description>Low Capture/Compare value</description>
  13407. <bitOffset>0</bitOffset>
  13408. <bitWidth>16</bitWidth>
  13409. </field>
  13410. </fields>
  13411. </register>
  13412. <register>
  13413. <name>CCR4</name>
  13414. <displayName>CCR4</displayName>
  13415. <description>capture/compare register 4</description>
  13416. <addressOffset>0x40</addressOffset>
  13417. <size>0x20</size>
  13418. <access>read-write</access>
  13419. <resetValue>0x00000000</resetValue>
  13420. <fields>
  13421. <field>
  13422. <name>CCR4_H</name>
  13423. <description>High Capture/Compare value (TIM2
  13424. only)</description>
  13425. <bitOffset>16</bitOffset>
  13426. <bitWidth>16</bitWidth>
  13427. </field>
  13428. <field>
  13429. <name>CCR4_L</name>
  13430. <description>Low Capture/Compare value</description>
  13431. <bitOffset>0</bitOffset>
  13432. <bitWidth>16</bitWidth>
  13433. </field>
  13434. </fields>
  13435. </register>
  13436. <register>
  13437. <name>DCR</name>
  13438. <displayName>DCR</displayName>
  13439. <description>DMA control register</description>
  13440. <addressOffset>0x48</addressOffset>
  13441. <size>0x20</size>
  13442. <access>read-write</access>
  13443. <resetValue>0x0000</resetValue>
  13444. <fields>
  13445. <field>
  13446. <name>DBL</name>
  13447. <description>DMA burst length</description>
  13448. <bitOffset>8</bitOffset>
  13449. <bitWidth>5</bitWidth>
  13450. </field>
  13451. <field>
  13452. <name>DBA</name>
  13453. <description>DMA base address</description>
  13454. <bitOffset>0</bitOffset>
  13455. <bitWidth>5</bitWidth>
  13456. </field>
  13457. </fields>
  13458. </register>
  13459. <register>
  13460. <name>DMAR</name>
  13461. <displayName>DMAR</displayName>
  13462. <description>DMA address for full transfer</description>
  13463. <addressOffset>0x4C</addressOffset>
  13464. <size>0x20</size>
  13465. <access>read-write</access>
  13466. <resetValue>0x0000</resetValue>
  13467. <fields>
  13468. <field>
  13469. <name>DMAB</name>
  13470. <description>DMA register for burst
  13471. accesses</description>
  13472. <bitOffset>0</bitOffset>
  13473. <bitWidth>16</bitWidth>
  13474. </field>
  13475. </fields>
  13476. </register>
  13477. <register>
  13478. <name>OR</name>
  13479. <displayName>OR</displayName>
  13480. <description>TIM2 option register</description>
  13481. <addressOffset>0x50</addressOffset>
  13482. <size>0x20</size>
  13483. <access>read-write</access>
  13484. <resetValue>0x0000</resetValue>
  13485. <fields>
  13486. <field>
  13487. <name>ETR_RMP</name>
  13488. <description>Timer2 ETR remap</description>
  13489. <bitOffset>0</bitOffset>
  13490. <bitWidth>3</bitWidth>
  13491. </field>
  13492. <field>
  13493. <name>TI4_RMP</name>
  13494. <description>Internal trigger</description>
  13495. <bitOffset>3</bitOffset>
  13496. <bitWidth>2</bitWidth>
  13497. </field>
  13498. </fields>
  13499. </register>
  13500. </registers>
  13501. </peripheral>
  13502. <peripheral derivedFrom="TIM2">
  13503. <name>TIM3</name>
  13504. <baseAddress>0x40000400</baseAddress>
  13505. <interrupt>
  13506. <name>TIM2</name>
  13507. <description>TIM2 global interrupt</description>
  13508. <value>15</value>
  13509. </interrupt>
  13510. </peripheral>
  13511. <peripheral>
  13512. <name>TIM6</name>
  13513. <description>Basic-timers</description>
  13514. <groupName>TIM</groupName>
  13515. <baseAddress>0x40001000</baseAddress>
  13516. <addressBlock>
  13517. <offset>0x0</offset>
  13518. <size>0x400</size>
  13519. <usage>registers</usage>
  13520. </addressBlock>
  13521. <interrupt>
  13522. <name>TIM6_DAC</name>
  13523. <description>TIM6 global interrupt and DAC</description>
  13524. <value>17</value>
  13525. </interrupt>
  13526. <registers>
  13527. <register>
  13528. <name>CR1</name>
  13529. <displayName>CR1</displayName>
  13530. <description>control register 1</description>
  13531. <addressOffset>0x0</addressOffset>
  13532. <size>0x20</size>
  13533. <access>read-write</access>
  13534. <resetValue>0x0000</resetValue>
  13535. <fields>
  13536. <field>
  13537. <name>ARPE</name>
  13538. <description>Auto-reload preload enable</description>
  13539. <bitOffset>7</bitOffset>
  13540. <bitWidth>1</bitWidth>
  13541. </field>
  13542. <field>
  13543. <name>OPM</name>
  13544. <description>One-pulse mode</description>
  13545. <bitOffset>3</bitOffset>
  13546. <bitWidth>1</bitWidth>
  13547. </field>
  13548. <field>
  13549. <name>URS</name>
  13550. <description>Update request source</description>
  13551. <bitOffset>2</bitOffset>
  13552. <bitWidth>1</bitWidth>
  13553. </field>
  13554. <field>
  13555. <name>UDIS</name>
  13556. <description>Update disable</description>
  13557. <bitOffset>1</bitOffset>
  13558. <bitWidth>1</bitWidth>
  13559. </field>
  13560. <field>
  13561. <name>CEN</name>
  13562. <description>Counter enable</description>
  13563. <bitOffset>0</bitOffset>
  13564. <bitWidth>1</bitWidth>
  13565. </field>
  13566. </fields>
  13567. </register>
  13568. <register>
  13569. <name>CR2</name>
  13570. <displayName>CR2</displayName>
  13571. <description>control register 2</description>
  13572. <addressOffset>0x4</addressOffset>
  13573. <size>0x20</size>
  13574. <access>read-write</access>
  13575. <resetValue>0x0000</resetValue>
  13576. <fields>
  13577. <field>
  13578. <name>MMS</name>
  13579. <description>Master mode selection</description>
  13580. <bitOffset>4</bitOffset>
  13581. <bitWidth>3</bitWidth>
  13582. </field>
  13583. </fields>
  13584. </register>
  13585. <register>
  13586. <name>DIER</name>
  13587. <displayName>DIER</displayName>
  13588. <description>DMA/Interrupt enable register</description>
  13589. <addressOffset>0xC</addressOffset>
  13590. <size>0x20</size>
  13591. <access>read-write</access>
  13592. <resetValue>0x0000</resetValue>
  13593. <fields>
  13594. <field>
  13595. <name>UDE</name>
  13596. <description>Update DMA request enable</description>
  13597. <bitOffset>8</bitOffset>
  13598. <bitWidth>1</bitWidth>
  13599. </field>
  13600. <field>
  13601. <name>UIE</name>
  13602. <description>Update interrupt enable</description>
  13603. <bitOffset>0</bitOffset>
  13604. <bitWidth>1</bitWidth>
  13605. </field>
  13606. </fields>
  13607. </register>
  13608. <register>
  13609. <name>SR</name>
  13610. <displayName>SR</displayName>
  13611. <description>status register</description>
  13612. <addressOffset>0x10</addressOffset>
  13613. <size>0x20</size>
  13614. <access>read-write</access>
  13615. <resetValue>0x0000</resetValue>
  13616. <fields>
  13617. <field>
  13618. <name>UIF</name>
  13619. <description>Update interrupt flag</description>
  13620. <bitOffset>0</bitOffset>
  13621. <bitWidth>1</bitWidth>
  13622. </field>
  13623. </fields>
  13624. </register>
  13625. <register>
  13626. <name>EGR</name>
  13627. <displayName>EGR</displayName>
  13628. <description>event generation register</description>
  13629. <addressOffset>0x14</addressOffset>
  13630. <size>0x20</size>
  13631. <access>write-only</access>
  13632. <resetValue>0x0000</resetValue>
  13633. <fields>
  13634. <field>
  13635. <name>UG</name>
  13636. <description>Update generation</description>
  13637. <bitOffset>0</bitOffset>
  13638. <bitWidth>1</bitWidth>
  13639. </field>
  13640. </fields>
  13641. </register>
  13642. <register>
  13643. <name>CNT</name>
  13644. <displayName>CNT</displayName>
  13645. <description>counter</description>
  13646. <addressOffset>0x24</addressOffset>
  13647. <size>0x20</size>
  13648. <access>read-write</access>
  13649. <resetValue>0x00000000</resetValue>
  13650. <fields>
  13651. <field>
  13652. <name>CNT</name>
  13653. <description>Low counter value</description>
  13654. <bitOffset>0</bitOffset>
  13655. <bitWidth>16</bitWidth>
  13656. </field>
  13657. </fields>
  13658. </register>
  13659. <register>
  13660. <name>PSC</name>
  13661. <displayName>PSC</displayName>
  13662. <description>prescaler</description>
  13663. <addressOffset>0x28</addressOffset>
  13664. <size>0x20</size>
  13665. <access>read-write</access>
  13666. <resetValue>0x0000</resetValue>
  13667. <fields>
  13668. <field>
  13669. <name>PSC</name>
  13670. <description>Prescaler value</description>
  13671. <bitOffset>0</bitOffset>
  13672. <bitWidth>16</bitWidth>
  13673. </field>
  13674. </fields>
  13675. </register>
  13676. <register>
  13677. <name>ARR</name>
  13678. <displayName>ARR</displayName>
  13679. <description>auto-reload register</description>
  13680. <addressOffset>0x2C</addressOffset>
  13681. <size>0x20</size>
  13682. <access>read-write</access>
  13683. <resetValue>0x00000000</resetValue>
  13684. <fields>
  13685. <field>
  13686. <name>ARR</name>
  13687. <description>Low Auto-reload value</description>
  13688. <bitOffset>0</bitOffset>
  13689. <bitWidth>16</bitWidth>
  13690. </field>
  13691. </fields>
  13692. </register>
  13693. </registers>
  13694. </peripheral>
  13695. <peripheral derivedFrom="TIM6">
  13696. <name>TIM7</name>
  13697. <baseAddress>0x40000C00</baseAddress>
  13698. <interrupt>
  13699. <name>TIM6_DAC</name>
  13700. <description>TIM6 global interrupt and DAC</description>
  13701. <value>17</value>
  13702. </interrupt>
  13703. </peripheral>
  13704. <peripheral>
  13705. <name>TIM21</name>
  13706. <description>General-purpose-timers</description>
  13707. <groupName>TIM</groupName>
  13708. <baseAddress>0x40010800</baseAddress>
  13709. <addressBlock>
  13710. <offset>0x0</offset>
  13711. <size>0x400</size>
  13712. <usage>registers</usage>
  13713. </addressBlock>
  13714. <interrupt>
  13715. <name>TIM21</name>
  13716. <description>TIMER21 global interrupt</description>
  13717. <value>20</value>
  13718. </interrupt>
  13719. <registers>
  13720. <register>
  13721. <name>CR1</name>
  13722. <displayName>CR1</displayName>
  13723. <description>control register 1</description>
  13724. <addressOffset>0x0</addressOffset>
  13725. <size>0x20</size>
  13726. <access>read-write</access>
  13727. <resetValue>0x0000</resetValue>
  13728. <fields>
  13729. <field>
  13730. <name>CEN</name>
  13731. <description>Counter enable</description>
  13732. <bitOffset>0</bitOffset>
  13733. <bitWidth>1</bitWidth>
  13734. </field>
  13735. <field>
  13736. <name>UDIS</name>
  13737. <description>Update disable</description>
  13738. <bitOffset>1</bitOffset>
  13739. <bitWidth>1</bitWidth>
  13740. </field>
  13741. <field>
  13742. <name>URS</name>
  13743. <description>Update request source</description>
  13744. <bitOffset>2</bitOffset>
  13745. <bitWidth>1</bitWidth>
  13746. </field>
  13747. <field>
  13748. <name>OPM</name>
  13749. <description>One-pulse mode</description>
  13750. <bitOffset>3</bitOffset>
  13751. <bitWidth>1</bitWidth>
  13752. </field>
  13753. <field>
  13754. <name>DIR</name>
  13755. <description>Direction</description>
  13756. <bitOffset>4</bitOffset>
  13757. <bitWidth>1</bitWidth>
  13758. </field>
  13759. <field>
  13760. <name>CMS</name>
  13761. <description>Center-aligned mode
  13762. selection</description>
  13763. <bitOffset>5</bitOffset>
  13764. <bitWidth>2</bitWidth>
  13765. </field>
  13766. <field>
  13767. <name>ARPE</name>
  13768. <description>Auto-reload preload enable</description>
  13769. <bitOffset>7</bitOffset>
  13770. <bitWidth>1</bitWidth>
  13771. </field>
  13772. <field>
  13773. <name>CKD</name>
  13774. <description>Clock division</description>
  13775. <bitOffset>8</bitOffset>
  13776. <bitWidth>2</bitWidth>
  13777. </field>
  13778. </fields>
  13779. </register>
  13780. <register>
  13781. <name>CR2</name>
  13782. <displayName>CR2</displayName>
  13783. <description>control register 2</description>
  13784. <addressOffset>0x4</addressOffset>
  13785. <size>0x20</size>
  13786. <access>read-write</access>
  13787. <resetValue>0x0000</resetValue>
  13788. <fields>
  13789. <field>
  13790. <name>MMS</name>
  13791. <description>Master mode selection</description>
  13792. <bitOffset>4</bitOffset>
  13793. <bitWidth>3</bitWidth>
  13794. </field>
  13795. </fields>
  13796. </register>
  13797. <register>
  13798. <name>SMCR</name>
  13799. <displayName>SMCR</displayName>
  13800. <description>slave mode control register</description>
  13801. <addressOffset>0x8</addressOffset>
  13802. <size>0x20</size>
  13803. <access>read-write</access>
  13804. <resetValue>0x0000</resetValue>
  13805. <fields>
  13806. <field>
  13807. <name>SMS</name>
  13808. <description>Slave mode selection</description>
  13809. <bitOffset>0</bitOffset>
  13810. <bitWidth>3</bitWidth>
  13811. </field>
  13812. <field>
  13813. <name>TS</name>
  13814. <description>Trigger selection</description>
  13815. <bitOffset>4</bitOffset>
  13816. <bitWidth>3</bitWidth>
  13817. </field>
  13818. <field>
  13819. <name>MSM</name>
  13820. <description>Master/Slave mode</description>
  13821. <bitOffset>7</bitOffset>
  13822. <bitWidth>1</bitWidth>
  13823. </field>
  13824. <field>
  13825. <name>ETF</name>
  13826. <description>External trigger filter</description>
  13827. <bitOffset>8</bitOffset>
  13828. <bitWidth>4</bitWidth>
  13829. </field>
  13830. <field>
  13831. <name>ETPS</name>
  13832. <description>External trigger prescaler</description>
  13833. <bitOffset>12</bitOffset>
  13834. <bitWidth>2</bitWidth>
  13835. </field>
  13836. <field>
  13837. <name>ECE</name>
  13838. <description>External clock enable</description>
  13839. <bitOffset>14</bitOffset>
  13840. <bitWidth>1</bitWidth>
  13841. </field>
  13842. <field>
  13843. <name>ETP</name>
  13844. <description>External trigger polarity</description>
  13845. <bitOffset>15</bitOffset>
  13846. <bitWidth>1</bitWidth>
  13847. </field>
  13848. </fields>
  13849. </register>
  13850. <register>
  13851. <name>DIER</name>
  13852. <displayName>DIER</displayName>
  13853. <description>DMA/Interrupt enable register</description>
  13854. <addressOffset>0xC</addressOffset>
  13855. <size>0x20</size>
  13856. <access>read-write</access>
  13857. <resetValue>0x0000</resetValue>
  13858. <fields>
  13859. <field>
  13860. <name>TIE</name>
  13861. <description>Trigger interrupt enable</description>
  13862. <bitOffset>6</bitOffset>
  13863. <bitWidth>1</bitWidth>
  13864. </field>
  13865. <field>
  13866. <name>CC2IE</name>
  13867. <description>Capture/Compare 2 interrupt
  13868. enable</description>
  13869. <bitOffset>2</bitOffset>
  13870. <bitWidth>1</bitWidth>
  13871. </field>
  13872. <field>
  13873. <name>CC1IE</name>
  13874. <description>Capture/Compare 1 interrupt
  13875. enable</description>
  13876. <bitOffset>1</bitOffset>
  13877. <bitWidth>1</bitWidth>
  13878. </field>
  13879. <field>
  13880. <name>UIE</name>
  13881. <description>Update interrupt enable</description>
  13882. <bitOffset>0</bitOffset>
  13883. <bitWidth>1</bitWidth>
  13884. </field>
  13885. </fields>
  13886. </register>
  13887. <register>
  13888. <name>SR</name>
  13889. <displayName>SR</displayName>
  13890. <description>status register</description>
  13891. <addressOffset>0x10</addressOffset>
  13892. <size>0x20</size>
  13893. <access>read-write</access>
  13894. <resetValue>0x0000</resetValue>
  13895. <fields>
  13896. <field>
  13897. <name>CC2OF</name>
  13898. <description>Capture/compare 2 overcapture
  13899. flag</description>
  13900. <bitOffset>10</bitOffset>
  13901. <bitWidth>1</bitWidth>
  13902. </field>
  13903. <field>
  13904. <name>CC1OF</name>
  13905. <description>Capture/Compare 1 overcapture
  13906. flag</description>
  13907. <bitOffset>9</bitOffset>
  13908. <bitWidth>1</bitWidth>
  13909. </field>
  13910. <field>
  13911. <name>TIF</name>
  13912. <description>Trigger interrupt flag</description>
  13913. <bitOffset>6</bitOffset>
  13914. <bitWidth>1</bitWidth>
  13915. </field>
  13916. <field>
  13917. <name>CC2IF</name>
  13918. <description>Capture/Compare 2 interrupt
  13919. flag</description>
  13920. <bitOffset>2</bitOffset>
  13921. <bitWidth>1</bitWidth>
  13922. </field>
  13923. <field>
  13924. <name>CC1IF</name>
  13925. <description>Capture/compare 1 interrupt
  13926. flag</description>
  13927. <bitOffset>1</bitOffset>
  13928. <bitWidth>1</bitWidth>
  13929. </field>
  13930. <field>
  13931. <name>UIF</name>
  13932. <description>Update interrupt flag</description>
  13933. <bitOffset>0</bitOffset>
  13934. <bitWidth>1</bitWidth>
  13935. </field>
  13936. </fields>
  13937. </register>
  13938. <register>
  13939. <name>EGR</name>
  13940. <displayName>EGR</displayName>
  13941. <description>event generation register</description>
  13942. <addressOffset>0x14</addressOffset>
  13943. <size>0x20</size>
  13944. <access>write-only</access>
  13945. <resetValue>0x0000</resetValue>
  13946. <fields>
  13947. <field>
  13948. <name>TG</name>
  13949. <description>Trigger generation</description>
  13950. <bitOffset>6</bitOffset>
  13951. <bitWidth>1</bitWidth>
  13952. </field>
  13953. <field>
  13954. <name>CC2G</name>
  13955. <description>Capture/compare 2
  13956. generation</description>
  13957. <bitOffset>2</bitOffset>
  13958. <bitWidth>1</bitWidth>
  13959. </field>
  13960. <field>
  13961. <name>CC1G</name>
  13962. <description>Capture/compare 1
  13963. generation</description>
  13964. <bitOffset>1</bitOffset>
  13965. <bitWidth>1</bitWidth>
  13966. </field>
  13967. <field>
  13968. <name>UG</name>
  13969. <description>Update generation</description>
  13970. <bitOffset>0</bitOffset>
  13971. <bitWidth>1</bitWidth>
  13972. </field>
  13973. </fields>
  13974. </register>
  13975. <register>
  13976. <name>CCMR1_Output</name>
  13977. <displayName>CCMR1_Output</displayName>
  13978. <description>capture/compare mode register (output
  13979. mode)</description>
  13980. <addressOffset>0x18</addressOffset>
  13981. <size>0x20</size>
  13982. <access>read-write</access>
  13983. <resetValue>0x00000000</resetValue>
  13984. <fields>
  13985. <field>
  13986. <name>OC2M</name>
  13987. <description>Output Compare 2 mode</description>
  13988. <bitOffset>12</bitOffset>
  13989. <bitWidth>3</bitWidth>
  13990. </field>
  13991. <field>
  13992. <name>OC2PE</name>
  13993. <description>Output Compare 2 preload
  13994. enable</description>
  13995. <bitOffset>11</bitOffset>
  13996. <bitWidth>1</bitWidth>
  13997. </field>
  13998. <field>
  13999. <name>OC2FE</name>
  14000. <description>Output Compare 2 fast
  14001. enable</description>
  14002. <bitOffset>10</bitOffset>
  14003. <bitWidth>1</bitWidth>
  14004. </field>
  14005. <field>
  14006. <name>CC2S</name>
  14007. <description>Capture/Compare 2
  14008. selection</description>
  14009. <bitOffset>8</bitOffset>
  14010. <bitWidth>2</bitWidth>
  14011. </field>
  14012. <field>
  14013. <name>OC1M</name>
  14014. <description>Output Compare 1 mode</description>
  14015. <bitOffset>4</bitOffset>
  14016. <bitWidth>3</bitWidth>
  14017. </field>
  14018. <field>
  14019. <name>OC1PE</name>
  14020. <description>Output Compare 1 preload
  14021. enable</description>
  14022. <bitOffset>3</bitOffset>
  14023. <bitWidth>1</bitWidth>
  14024. </field>
  14025. <field>
  14026. <name>OC1FE</name>
  14027. <description>Output Compare 1 fast
  14028. enable</description>
  14029. <bitOffset>2</bitOffset>
  14030. <bitWidth>1</bitWidth>
  14031. </field>
  14032. <field>
  14033. <name>CC1S</name>
  14034. <description>Capture/Compare 1
  14035. selection</description>
  14036. <bitOffset>0</bitOffset>
  14037. <bitWidth>2</bitWidth>
  14038. </field>
  14039. </fields>
  14040. </register>
  14041. <register>
  14042. <name>CCMR1_Input</name>
  14043. <displayName>CCMR1_Input</displayName>
  14044. <description>capture/compare mode register 1 (input
  14045. mode)</description>
  14046. <alternateRegister>CCMR1_Output</alternateRegister>
  14047. <addressOffset>0x18</addressOffset>
  14048. <size>0x20</size>
  14049. <access>read-write</access>
  14050. <resetValue>0x00000000</resetValue>
  14051. <fields>
  14052. <field>
  14053. <name>IC2F</name>
  14054. <description>Input capture 2 filter</description>
  14055. <bitOffset>12</bitOffset>
  14056. <bitWidth>4</bitWidth>
  14057. </field>
  14058. <field>
  14059. <name>IC2PSC</name>
  14060. <description>Input capture 2 prescaler</description>
  14061. <bitOffset>10</bitOffset>
  14062. <bitWidth>2</bitWidth>
  14063. </field>
  14064. <field>
  14065. <name>CC2S</name>
  14066. <description>Capture/Compare 2
  14067. selection</description>
  14068. <bitOffset>8</bitOffset>
  14069. <bitWidth>2</bitWidth>
  14070. </field>
  14071. <field>
  14072. <name>IC1F</name>
  14073. <description>Input capture 1 filter</description>
  14074. <bitOffset>4</bitOffset>
  14075. <bitWidth>4</bitWidth>
  14076. </field>
  14077. <field>
  14078. <name>IC1PSC</name>
  14079. <description>Input capture 1 prescaler</description>
  14080. <bitOffset>2</bitOffset>
  14081. <bitWidth>2</bitWidth>
  14082. </field>
  14083. <field>
  14084. <name>CC1S</name>
  14085. <description>Capture/Compare 1
  14086. selection</description>
  14087. <bitOffset>0</bitOffset>
  14088. <bitWidth>2</bitWidth>
  14089. </field>
  14090. </fields>
  14091. </register>
  14092. <register>
  14093. <name>CCER</name>
  14094. <displayName>CCER</displayName>
  14095. <description>capture/compare enable
  14096. register</description>
  14097. <addressOffset>0x20</addressOffset>
  14098. <size>0x20</size>
  14099. <access>read-write</access>
  14100. <resetValue>0x0000</resetValue>
  14101. <fields>
  14102. <field>
  14103. <name>CC2NP</name>
  14104. <description>Capture/Compare 2 output
  14105. Polarity</description>
  14106. <bitOffset>7</bitOffset>
  14107. <bitWidth>1</bitWidth>
  14108. </field>
  14109. <field>
  14110. <name>CC2P</name>
  14111. <description>Capture/Compare 2 output
  14112. Polarity</description>
  14113. <bitOffset>5</bitOffset>
  14114. <bitWidth>1</bitWidth>
  14115. </field>
  14116. <field>
  14117. <name>CC2E</name>
  14118. <description>Capture/Compare 2 output
  14119. enable</description>
  14120. <bitOffset>4</bitOffset>
  14121. <bitWidth>1</bitWidth>
  14122. </field>
  14123. <field>
  14124. <name>CC1NP</name>
  14125. <description>Capture/Compare 1 output
  14126. Polarity</description>
  14127. <bitOffset>3</bitOffset>
  14128. <bitWidth>1</bitWidth>
  14129. </field>
  14130. <field>
  14131. <name>CC1P</name>
  14132. <description>Capture/Compare 1 output
  14133. Polarity</description>
  14134. <bitOffset>1</bitOffset>
  14135. <bitWidth>1</bitWidth>
  14136. </field>
  14137. <field>
  14138. <name>CC1E</name>
  14139. <description>Capture/Compare 1 output
  14140. enable</description>
  14141. <bitOffset>0</bitOffset>
  14142. <bitWidth>1</bitWidth>
  14143. </field>
  14144. </fields>
  14145. </register>
  14146. <register>
  14147. <name>CNT</name>
  14148. <displayName>CNT</displayName>
  14149. <description>counter</description>
  14150. <addressOffset>0x24</addressOffset>
  14151. <size>0x20</size>
  14152. <access>read-write</access>
  14153. <resetValue>0x00000000</resetValue>
  14154. <fields>
  14155. <field>
  14156. <name>CNT</name>
  14157. <description>counter value</description>
  14158. <bitOffset>0</bitOffset>
  14159. <bitWidth>16</bitWidth>
  14160. </field>
  14161. </fields>
  14162. </register>
  14163. <register>
  14164. <name>PSC</name>
  14165. <displayName>PSC</displayName>
  14166. <description>prescaler</description>
  14167. <addressOffset>0x28</addressOffset>
  14168. <size>0x20</size>
  14169. <access>read-write</access>
  14170. <resetValue>0x0000</resetValue>
  14171. <fields>
  14172. <field>
  14173. <name>PSC</name>
  14174. <description>Prescaler value</description>
  14175. <bitOffset>0</bitOffset>
  14176. <bitWidth>16</bitWidth>
  14177. </field>
  14178. </fields>
  14179. </register>
  14180. <register>
  14181. <name>ARR</name>
  14182. <displayName>ARR</displayName>
  14183. <description>auto-reload register</description>
  14184. <addressOffset>0x2C</addressOffset>
  14185. <size>0x20</size>
  14186. <access>read-write</access>
  14187. <resetValue>0x00000000</resetValue>
  14188. <fields>
  14189. <field>
  14190. <name>ARR</name>
  14191. <description>Auto-reload value</description>
  14192. <bitOffset>0</bitOffset>
  14193. <bitWidth>16</bitWidth>
  14194. </field>
  14195. </fields>
  14196. </register>
  14197. <register>
  14198. <name>CCR1</name>
  14199. <displayName>CCR1</displayName>
  14200. <description>capture/compare register 1</description>
  14201. <addressOffset>0x34</addressOffset>
  14202. <size>0x20</size>
  14203. <access>read-write</access>
  14204. <resetValue>0x00000000</resetValue>
  14205. <fields>
  14206. <field>
  14207. <name>CCR1</name>
  14208. <description>Capture/Compare 1 value</description>
  14209. <bitOffset>0</bitOffset>
  14210. <bitWidth>16</bitWidth>
  14211. </field>
  14212. </fields>
  14213. </register>
  14214. <register>
  14215. <name>CCR2</name>
  14216. <displayName>CCR2</displayName>
  14217. <description>capture/compare register 2</description>
  14218. <addressOffset>0x38</addressOffset>
  14219. <size>0x20</size>
  14220. <access>read-write</access>
  14221. <resetValue>0x00000000</resetValue>
  14222. <fields>
  14223. <field>
  14224. <name>CCR2</name>
  14225. <description>Capture/Compare 2 value</description>
  14226. <bitOffset>0</bitOffset>
  14227. <bitWidth>16</bitWidth>
  14228. </field>
  14229. </fields>
  14230. </register>
  14231. <register>
  14232. <name>OR</name>
  14233. <displayName>OR</displayName>
  14234. <description>TIM21 option register</description>
  14235. <addressOffset>0x50</addressOffset>
  14236. <size>0x20</size>
  14237. <access>read-write</access>
  14238. <resetValue>0x00000000</resetValue>
  14239. <fields>
  14240. <field>
  14241. <name>ETR_RMP</name>
  14242. <description>Timer21 ETR remap</description>
  14243. <bitOffset>0</bitOffset>
  14244. <bitWidth>2</bitWidth>
  14245. </field>
  14246. <field>
  14247. <name>TI1_RMP</name>
  14248. <description>Timer21 TI1</description>
  14249. <bitOffset>2</bitOffset>
  14250. <bitWidth>3</bitWidth>
  14251. </field>
  14252. <field>
  14253. <name>TI2_RMP</name>
  14254. <description>Timer21 TI2</description>
  14255. <bitOffset>5</bitOffset>
  14256. <bitWidth>1</bitWidth>
  14257. </field>
  14258. </fields>
  14259. </register>
  14260. </registers>
  14261. </peripheral>
  14262. <peripheral>
  14263. <name>TIM22</name>
  14264. <description>General-purpose-timers</description>
  14265. <groupName>TIM</groupName>
  14266. <baseAddress>0x40011400</baseAddress>
  14267. <addressBlock>
  14268. <offset>0x0</offset>
  14269. <size>0x400</size>
  14270. <usage>registers</usage>
  14271. </addressBlock>
  14272. <interrupt>
  14273. <name>TIM22</name>
  14274. <description>TIMER22 global interrupt</description>
  14275. <value>22</value>
  14276. </interrupt>
  14277. <registers>
  14278. <register>
  14279. <name>CR1</name>
  14280. <displayName>CR1</displayName>
  14281. <description>control register 1</description>
  14282. <addressOffset>0x0</addressOffset>
  14283. <size>0x20</size>
  14284. <access>read-write</access>
  14285. <resetValue>0x0000</resetValue>
  14286. <fields>
  14287. <field>
  14288. <name>CEN</name>
  14289. <description>Counter enable</description>
  14290. <bitOffset>0</bitOffset>
  14291. <bitWidth>1</bitWidth>
  14292. </field>
  14293. <field>
  14294. <name>UDIS</name>
  14295. <description>Update disable</description>
  14296. <bitOffset>1</bitOffset>
  14297. <bitWidth>1</bitWidth>
  14298. </field>
  14299. <field>
  14300. <name>URS</name>
  14301. <description>Update request source</description>
  14302. <bitOffset>2</bitOffset>
  14303. <bitWidth>1</bitWidth>
  14304. </field>
  14305. <field>
  14306. <name>OPM</name>
  14307. <description>One-pulse mode</description>
  14308. <bitOffset>3</bitOffset>
  14309. <bitWidth>1</bitWidth>
  14310. </field>
  14311. <field>
  14312. <name>DIR</name>
  14313. <description>Direction</description>
  14314. <bitOffset>4</bitOffset>
  14315. <bitWidth>1</bitWidth>
  14316. </field>
  14317. <field>
  14318. <name>CMS</name>
  14319. <description>Center-aligned mode
  14320. selection</description>
  14321. <bitOffset>5</bitOffset>
  14322. <bitWidth>2</bitWidth>
  14323. </field>
  14324. <field>
  14325. <name>ARPE</name>
  14326. <description>Auto-reload preload enable</description>
  14327. <bitOffset>7</bitOffset>
  14328. <bitWidth>1</bitWidth>
  14329. </field>
  14330. <field>
  14331. <name>CKD</name>
  14332. <description>Clock division</description>
  14333. <bitOffset>8</bitOffset>
  14334. <bitWidth>2</bitWidth>
  14335. </field>
  14336. </fields>
  14337. </register>
  14338. <register>
  14339. <name>CR2</name>
  14340. <displayName>CR2</displayName>
  14341. <description>control register 2</description>
  14342. <addressOffset>0x4</addressOffset>
  14343. <size>0x20</size>
  14344. <access>read-write</access>
  14345. <resetValue>0x0000</resetValue>
  14346. <fields>
  14347. <field>
  14348. <name>MMS</name>
  14349. <description>Master mode selection</description>
  14350. <bitOffset>4</bitOffset>
  14351. <bitWidth>3</bitWidth>
  14352. </field>
  14353. </fields>
  14354. </register>
  14355. <register>
  14356. <name>SMCR</name>
  14357. <displayName>SMCR</displayName>
  14358. <description>slave mode control register</description>
  14359. <addressOffset>0x8</addressOffset>
  14360. <size>0x20</size>
  14361. <access>read-write</access>
  14362. <resetValue>0x0000</resetValue>
  14363. <fields>
  14364. <field>
  14365. <name>SMS</name>
  14366. <description>Slave mode selection</description>
  14367. <bitOffset>0</bitOffset>
  14368. <bitWidth>3</bitWidth>
  14369. </field>
  14370. <field>
  14371. <name>TS</name>
  14372. <description>Trigger selection</description>
  14373. <bitOffset>4</bitOffset>
  14374. <bitWidth>3</bitWidth>
  14375. </field>
  14376. <field>
  14377. <name>MSM</name>
  14378. <description>Master/Slave mode</description>
  14379. <bitOffset>7</bitOffset>
  14380. <bitWidth>1</bitWidth>
  14381. </field>
  14382. <field>
  14383. <name>ETF</name>
  14384. <description>External trigger filter</description>
  14385. <bitOffset>8</bitOffset>
  14386. <bitWidth>4</bitWidth>
  14387. </field>
  14388. <field>
  14389. <name>ETPS</name>
  14390. <description>External trigger prescaler</description>
  14391. <bitOffset>12</bitOffset>
  14392. <bitWidth>2</bitWidth>
  14393. </field>
  14394. <field>
  14395. <name>ECE</name>
  14396. <description>External clock enable</description>
  14397. <bitOffset>14</bitOffset>
  14398. <bitWidth>1</bitWidth>
  14399. </field>
  14400. <field>
  14401. <name>ETP</name>
  14402. <description>External trigger polarity</description>
  14403. <bitOffset>15</bitOffset>
  14404. <bitWidth>1</bitWidth>
  14405. </field>
  14406. </fields>
  14407. </register>
  14408. <register>
  14409. <name>DIER</name>
  14410. <displayName>DIER</displayName>
  14411. <description>DMA/Interrupt enable register</description>
  14412. <addressOffset>0xC</addressOffset>
  14413. <size>0x20</size>
  14414. <access>read-write</access>
  14415. <resetValue>0x0000</resetValue>
  14416. <fields>
  14417. <field>
  14418. <name>TIE</name>
  14419. <description>Trigger interrupt enable</description>
  14420. <bitOffset>6</bitOffset>
  14421. <bitWidth>1</bitWidth>
  14422. </field>
  14423. <field>
  14424. <name>CC2IE</name>
  14425. <description>Capture/Compare 2 interrupt
  14426. enable</description>
  14427. <bitOffset>2</bitOffset>
  14428. <bitWidth>1</bitWidth>
  14429. </field>
  14430. <field>
  14431. <name>CC1IE</name>
  14432. <description>Capture/Compare 1 interrupt
  14433. enable</description>
  14434. <bitOffset>1</bitOffset>
  14435. <bitWidth>1</bitWidth>
  14436. </field>
  14437. <field>
  14438. <name>UIE</name>
  14439. <description>Update interrupt enable</description>
  14440. <bitOffset>0</bitOffset>
  14441. <bitWidth>1</bitWidth>
  14442. </field>
  14443. </fields>
  14444. </register>
  14445. <register>
  14446. <name>SR</name>
  14447. <displayName>SR</displayName>
  14448. <description>status register</description>
  14449. <addressOffset>0x10</addressOffset>
  14450. <size>0x20</size>
  14451. <access>read-write</access>
  14452. <resetValue>0x0000</resetValue>
  14453. <fields>
  14454. <field>
  14455. <name>CC2OF</name>
  14456. <description>Capture/compare 2 overcapture
  14457. flag</description>
  14458. <bitOffset>10</bitOffset>
  14459. <bitWidth>1</bitWidth>
  14460. </field>
  14461. <field>
  14462. <name>CC1OF</name>
  14463. <description>Capture/Compare 1 overcapture
  14464. flag</description>
  14465. <bitOffset>9</bitOffset>
  14466. <bitWidth>1</bitWidth>
  14467. </field>
  14468. <field>
  14469. <name>TIF</name>
  14470. <description>Trigger interrupt flag</description>
  14471. <bitOffset>6</bitOffset>
  14472. <bitWidth>1</bitWidth>
  14473. </field>
  14474. <field>
  14475. <name>CC2IF</name>
  14476. <description>Capture/Compare 2 interrupt
  14477. flag</description>
  14478. <bitOffset>2</bitOffset>
  14479. <bitWidth>1</bitWidth>
  14480. </field>
  14481. <field>
  14482. <name>CC1IF</name>
  14483. <description>Capture/compare 1 interrupt
  14484. flag</description>
  14485. <bitOffset>1</bitOffset>
  14486. <bitWidth>1</bitWidth>
  14487. </field>
  14488. <field>
  14489. <name>UIF</name>
  14490. <description>Update interrupt flag</description>
  14491. <bitOffset>0</bitOffset>
  14492. <bitWidth>1</bitWidth>
  14493. </field>
  14494. </fields>
  14495. </register>
  14496. <register>
  14497. <name>EGR</name>
  14498. <displayName>EGR</displayName>
  14499. <description>event generation register</description>
  14500. <addressOffset>0x14</addressOffset>
  14501. <size>0x20</size>
  14502. <access>write-only</access>
  14503. <resetValue>0x0000</resetValue>
  14504. <fields>
  14505. <field>
  14506. <name>TG</name>
  14507. <description>Trigger generation</description>
  14508. <bitOffset>6</bitOffset>
  14509. <bitWidth>1</bitWidth>
  14510. </field>
  14511. <field>
  14512. <name>CC2G</name>
  14513. <description>Capture/compare 2
  14514. generation</description>
  14515. <bitOffset>2</bitOffset>
  14516. <bitWidth>1</bitWidth>
  14517. </field>
  14518. <field>
  14519. <name>CC1G</name>
  14520. <description>Capture/compare 1
  14521. generation</description>
  14522. <bitOffset>1</bitOffset>
  14523. <bitWidth>1</bitWidth>
  14524. </field>
  14525. <field>
  14526. <name>UG</name>
  14527. <description>Update generation</description>
  14528. <bitOffset>0</bitOffset>
  14529. <bitWidth>1</bitWidth>
  14530. </field>
  14531. </fields>
  14532. </register>
  14533. <register>
  14534. <name>CCMR1_Output</name>
  14535. <displayName>CCMR1_Output</displayName>
  14536. <description>capture/compare mode register (output
  14537. mode)</description>
  14538. <addressOffset>0x18</addressOffset>
  14539. <size>0x20</size>
  14540. <access>read-write</access>
  14541. <resetValue>0x00000000</resetValue>
  14542. <fields>
  14543. <field>
  14544. <name>OC2M</name>
  14545. <description>Output Compare 2 mode</description>
  14546. <bitOffset>12</bitOffset>
  14547. <bitWidth>3</bitWidth>
  14548. </field>
  14549. <field>
  14550. <name>OC2PE</name>
  14551. <description>Output Compare 2 preload
  14552. enable</description>
  14553. <bitOffset>11</bitOffset>
  14554. <bitWidth>1</bitWidth>
  14555. </field>
  14556. <field>
  14557. <name>OC2FE</name>
  14558. <description>Output Compare 2 fast
  14559. enable</description>
  14560. <bitOffset>10</bitOffset>
  14561. <bitWidth>1</bitWidth>
  14562. </field>
  14563. <field>
  14564. <name>CC2S</name>
  14565. <description>Capture/Compare 2
  14566. selection</description>
  14567. <bitOffset>8</bitOffset>
  14568. <bitWidth>2</bitWidth>
  14569. </field>
  14570. <field>
  14571. <name>OC1M</name>
  14572. <description>Output Compare 1 mode</description>
  14573. <bitOffset>4</bitOffset>
  14574. <bitWidth>3</bitWidth>
  14575. </field>
  14576. <field>
  14577. <name>OC1PE</name>
  14578. <description>Output Compare 1 preload
  14579. enable</description>
  14580. <bitOffset>3</bitOffset>
  14581. <bitWidth>1</bitWidth>
  14582. </field>
  14583. <field>
  14584. <name>OC1FE</name>
  14585. <description>Output Compare 1 fast
  14586. enable</description>
  14587. <bitOffset>2</bitOffset>
  14588. <bitWidth>1</bitWidth>
  14589. </field>
  14590. <field>
  14591. <name>CC1S</name>
  14592. <description>Capture/Compare 1
  14593. selection</description>
  14594. <bitOffset>0</bitOffset>
  14595. <bitWidth>2</bitWidth>
  14596. </field>
  14597. </fields>
  14598. </register>
  14599. <register>
  14600. <name>CCMR1_Input</name>
  14601. <displayName>CCMR1_Input</displayName>
  14602. <description>capture/compare mode register 1 (input
  14603. mode)</description>
  14604. <alternateRegister>CCMR1_Output</alternateRegister>
  14605. <addressOffset>0x18</addressOffset>
  14606. <size>0x20</size>
  14607. <access>read-write</access>
  14608. <resetValue>0x00000000</resetValue>
  14609. <fields>
  14610. <field>
  14611. <name>IC2F</name>
  14612. <description>Input capture 2 filter</description>
  14613. <bitOffset>12</bitOffset>
  14614. <bitWidth>4</bitWidth>
  14615. </field>
  14616. <field>
  14617. <name>IC2PSC</name>
  14618. <description>Input capture 2 prescaler</description>
  14619. <bitOffset>10</bitOffset>
  14620. <bitWidth>2</bitWidth>
  14621. </field>
  14622. <field>
  14623. <name>CC2S</name>
  14624. <description>Capture/Compare 2
  14625. selection</description>
  14626. <bitOffset>8</bitOffset>
  14627. <bitWidth>2</bitWidth>
  14628. </field>
  14629. <field>
  14630. <name>IC1F</name>
  14631. <description>Input capture 1 filter</description>
  14632. <bitOffset>4</bitOffset>
  14633. <bitWidth>4</bitWidth>
  14634. </field>
  14635. <field>
  14636. <name>IC1PSC</name>
  14637. <description>Input capture 1 prescaler</description>
  14638. <bitOffset>2</bitOffset>
  14639. <bitWidth>2</bitWidth>
  14640. </field>
  14641. <field>
  14642. <name>CC1S</name>
  14643. <description>Capture/Compare 1
  14644. selection</description>
  14645. <bitOffset>0</bitOffset>
  14646. <bitWidth>2</bitWidth>
  14647. </field>
  14648. </fields>
  14649. </register>
  14650. <register>
  14651. <name>CCER</name>
  14652. <displayName>CCER</displayName>
  14653. <description>capture/compare enable
  14654. register</description>
  14655. <addressOffset>0x20</addressOffset>
  14656. <size>0x20</size>
  14657. <access>read-write</access>
  14658. <resetValue>0x0000</resetValue>
  14659. <fields>
  14660. <field>
  14661. <name>CC2NP</name>
  14662. <description>Capture/Compare 2 output
  14663. Polarity</description>
  14664. <bitOffset>7</bitOffset>
  14665. <bitWidth>1</bitWidth>
  14666. </field>
  14667. <field>
  14668. <name>CC2P</name>
  14669. <description>Capture/Compare 2 output
  14670. Polarity</description>
  14671. <bitOffset>5</bitOffset>
  14672. <bitWidth>1</bitWidth>
  14673. </field>
  14674. <field>
  14675. <name>CC2E</name>
  14676. <description>Capture/Compare 2 output
  14677. enable</description>
  14678. <bitOffset>4</bitOffset>
  14679. <bitWidth>1</bitWidth>
  14680. </field>
  14681. <field>
  14682. <name>CC1NP</name>
  14683. <description>Capture/Compare 1 output
  14684. Polarity</description>
  14685. <bitOffset>3</bitOffset>
  14686. <bitWidth>1</bitWidth>
  14687. </field>
  14688. <field>
  14689. <name>CC1P</name>
  14690. <description>Capture/Compare 1 output
  14691. Polarity</description>
  14692. <bitOffset>1</bitOffset>
  14693. <bitWidth>1</bitWidth>
  14694. </field>
  14695. <field>
  14696. <name>CC1E</name>
  14697. <description>Capture/Compare 1 output
  14698. enable</description>
  14699. <bitOffset>0</bitOffset>
  14700. <bitWidth>1</bitWidth>
  14701. </field>
  14702. </fields>
  14703. </register>
  14704. <register>
  14705. <name>CNT</name>
  14706. <displayName>CNT</displayName>
  14707. <description>counter</description>
  14708. <addressOffset>0x24</addressOffset>
  14709. <size>0x20</size>
  14710. <access>read-write</access>
  14711. <resetValue>0x00000000</resetValue>
  14712. <fields>
  14713. <field>
  14714. <name>CNT</name>
  14715. <description>counter value</description>
  14716. <bitOffset>0</bitOffset>
  14717. <bitWidth>16</bitWidth>
  14718. </field>
  14719. </fields>
  14720. </register>
  14721. <register>
  14722. <name>PSC</name>
  14723. <displayName>PSC</displayName>
  14724. <description>prescaler</description>
  14725. <addressOffset>0x28</addressOffset>
  14726. <size>0x20</size>
  14727. <access>read-write</access>
  14728. <resetValue>0x0000</resetValue>
  14729. <fields>
  14730. <field>
  14731. <name>PSC</name>
  14732. <description>Prescaler value</description>
  14733. <bitOffset>0</bitOffset>
  14734. <bitWidth>16</bitWidth>
  14735. </field>
  14736. </fields>
  14737. </register>
  14738. <register>
  14739. <name>ARR</name>
  14740. <displayName>ARR</displayName>
  14741. <description>auto-reload register</description>
  14742. <addressOffset>0x2C</addressOffset>
  14743. <size>0x20</size>
  14744. <access>read-write</access>
  14745. <resetValue>0x00000000</resetValue>
  14746. <fields>
  14747. <field>
  14748. <name>ARR</name>
  14749. <description>Auto-reload value</description>
  14750. <bitOffset>0</bitOffset>
  14751. <bitWidth>16</bitWidth>
  14752. </field>
  14753. </fields>
  14754. </register>
  14755. <register>
  14756. <name>CCR1</name>
  14757. <displayName>CCR1</displayName>
  14758. <description>capture/compare register 1</description>
  14759. <addressOffset>0x34</addressOffset>
  14760. <size>0x20</size>
  14761. <access>read-write</access>
  14762. <resetValue>0x00000000</resetValue>
  14763. <fields>
  14764. <field>
  14765. <name>CCR1</name>
  14766. <description>Capture/Compare 1 value</description>
  14767. <bitOffset>0</bitOffset>
  14768. <bitWidth>16</bitWidth>
  14769. </field>
  14770. </fields>
  14771. </register>
  14772. <register>
  14773. <name>CCR2</name>
  14774. <displayName>CCR2</displayName>
  14775. <description>capture/compare register 2</description>
  14776. <addressOffset>0x38</addressOffset>
  14777. <size>0x20</size>
  14778. <access>read-write</access>
  14779. <resetValue>0x00000000</resetValue>
  14780. <fields>
  14781. <field>
  14782. <name>CCR2</name>
  14783. <description>Capture/Compare 2 value</description>
  14784. <bitOffset>0</bitOffset>
  14785. <bitWidth>16</bitWidth>
  14786. </field>
  14787. </fields>
  14788. </register>
  14789. <register>
  14790. <name>OR</name>
  14791. <displayName>OR</displayName>
  14792. <description>TIM22 option register</description>
  14793. <addressOffset>0x50</addressOffset>
  14794. <size>0x20</size>
  14795. <access>read-write</access>
  14796. <resetValue>0x00000000</resetValue>
  14797. <fields>
  14798. <field>
  14799. <name>ETR_RMP</name>
  14800. <description>Timer22 ETR remap</description>
  14801. <bitOffset>0</bitOffset>
  14802. <bitWidth>2</bitWidth>
  14803. </field>
  14804. <field>
  14805. <name>TI1_RMP</name>
  14806. <description>Timer22 TI1</description>
  14807. <bitOffset>2</bitOffset>
  14808. <bitWidth>2</bitWidth>
  14809. </field>
  14810. </fields>
  14811. </register>
  14812. </registers>
  14813. </peripheral>
  14814. <peripheral>
  14815. <name>LPUART1</name>
  14816. <description>Lower power Universal asynchronous receiver
  14817. transmitter</description>
  14818. <groupName>USART</groupName>
  14819. <baseAddress>0x40004800</baseAddress>
  14820. <addressBlock>
  14821. <offset>0x0</offset>
  14822. <size>0x400</size>
  14823. <usage>registers</usage>
  14824. </addressBlock>
  14825. <registers>
  14826. <register>
  14827. <name>CR1</name>
  14828. <displayName>CR1</displayName>
  14829. <description>Control register 1</description>
  14830. <addressOffset>0x0</addressOffset>
  14831. <size>0x20</size>
  14832. <access>read-write</access>
  14833. <resetValue>0x0000</resetValue>
  14834. <fields>
  14835. <field>
  14836. <name>M1</name>
  14837. <description>Word length</description>
  14838. <bitOffset>28</bitOffset>
  14839. <bitWidth>1</bitWidth>
  14840. </field>
  14841. <field>
  14842. <name>DEAT4</name>
  14843. <description>Driver Enable assertion
  14844. time</description>
  14845. <bitOffset>25</bitOffset>
  14846. <bitWidth>1</bitWidth>
  14847. </field>
  14848. <field>
  14849. <name>DEAT3</name>
  14850. <description>DEAT3</description>
  14851. <bitOffset>24</bitOffset>
  14852. <bitWidth>1</bitWidth>
  14853. </field>
  14854. <field>
  14855. <name>DEAT2</name>
  14856. <description>DEAT2</description>
  14857. <bitOffset>23</bitOffset>
  14858. <bitWidth>1</bitWidth>
  14859. </field>
  14860. <field>
  14861. <name>DEAT1</name>
  14862. <description>DEAT1</description>
  14863. <bitOffset>22</bitOffset>
  14864. <bitWidth>1</bitWidth>
  14865. </field>
  14866. <field>
  14867. <name>DEAT0</name>
  14868. <description>DEAT0</description>
  14869. <bitOffset>21</bitOffset>
  14870. <bitWidth>1</bitWidth>
  14871. </field>
  14872. <field>
  14873. <name>DEDT4</name>
  14874. <description>Driver Enable de-assertion
  14875. time</description>
  14876. <bitOffset>20</bitOffset>
  14877. <bitWidth>1</bitWidth>
  14878. </field>
  14879. <field>
  14880. <name>DEDT3</name>
  14881. <description>DEDT3</description>
  14882. <bitOffset>19</bitOffset>
  14883. <bitWidth>1</bitWidth>
  14884. </field>
  14885. <field>
  14886. <name>DEDT2</name>
  14887. <description>DEDT2</description>
  14888. <bitOffset>18</bitOffset>
  14889. <bitWidth>1</bitWidth>
  14890. </field>
  14891. <field>
  14892. <name>DEDT1</name>
  14893. <description>DEDT1</description>
  14894. <bitOffset>17</bitOffset>
  14895. <bitWidth>1</bitWidth>
  14896. </field>
  14897. <field>
  14898. <name>DEDT0</name>
  14899. <description>DEDT0</description>
  14900. <bitOffset>16</bitOffset>
  14901. <bitWidth>1</bitWidth>
  14902. </field>
  14903. <field>
  14904. <name>CMIE</name>
  14905. <description>Character match interrupt
  14906. enable</description>
  14907. <bitOffset>14</bitOffset>
  14908. <bitWidth>1</bitWidth>
  14909. </field>
  14910. <field>
  14911. <name>MME</name>
  14912. <description>Mute mode enable</description>
  14913. <bitOffset>13</bitOffset>
  14914. <bitWidth>1</bitWidth>
  14915. </field>
  14916. <field>
  14917. <name>M0</name>
  14918. <description>Word length</description>
  14919. <bitOffset>12</bitOffset>
  14920. <bitWidth>1</bitWidth>
  14921. </field>
  14922. <field>
  14923. <name>WAKE</name>
  14924. <description>Receiver wakeup method</description>
  14925. <bitOffset>11</bitOffset>
  14926. <bitWidth>1</bitWidth>
  14927. </field>
  14928. <field>
  14929. <name>PCE</name>
  14930. <description>Parity control enable</description>
  14931. <bitOffset>10</bitOffset>
  14932. <bitWidth>1</bitWidth>
  14933. </field>
  14934. <field>
  14935. <name>PS</name>
  14936. <description>Parity selection</description>
  14937. <bitOffset>9</bitOffset>
  14938. <bitWidth>1</bitWidth>
  14939. </field>
  14940. <field>
  14941. <name>PEIE</name>
  14942. <description>PE interrupt enable</description>
  14943. <bitOffset>8</bitOffset>
  14944. <bitWidth>1</bitWidth>
  14945. </field>
  14946. <field>
  14947. <name>TXEIE</name>
  14948. <description>interrupt enable</description>
  14949. <bitOffset>7</bitOffset>
  14950. <bitWidth>1</bitWidth>
  14951. </field>
  14952. <field>
  14953. <name>TCIE</name>
  14954. <description>Transmission complete interrupt
  14955. enable</description>
  14956. <bitOffset>6</bitOffset>
  14957. <bitWidth>1</bitWidth>
  14958. </field>
  14959. <field>
  14960. <name>RXNEIE</name>
  14961. <description>RXNE interrupt enable</description>
  14962. <bitOffset>5</bitOffset>
  14963. <bitWidth>1</bitWidth>
  14964. </field>
  14965. <field>
  14966. <name>IDLEIE</name>
  14967. <description>IDLE interrupt enable</description>
  14968. <bitOffset>4</bitOffset>
  14969. <bitWidth>1</bitWidth>
  14970. </field>
  14971. <field>
  14972. <name>TE</name>
  14973. <description>Transmitter enable</description>
  14974. <bitOffset>3</bitOffset>
  14975. <bitWidth>1</bitWidth>
  14976. </field>
  14977. <field>
  14978. <name>RE</name>
  14979. <description>Receiver enable</description>
  14980. <bitOffset>2</bitOffset>
  14981. <bitWidth>1</bitWidth>
  14982. </field>
  14983. <field>
  14984. <name>UESM</name>
  14985. <description>USART enable in Stop mode</description>
  14986. <bitOffset>1</bitOffset>
  14987. <bitWidth>1</bitWidth>
  14988. </field>
  14989. <field>
  14990. <name>UE</name>
  14991. <description>USART enable</description>
  14992. <bitOffset>0</bitOffset>
  14993. <bitWidth>1</bitWidth>
  14994. </field>
  14995. </fields>
  14996. </register>
  14997. <register>
  14998. <name>CR2</name>
  14999. <displayName>CR2</displayName>
  15000. <description>Control register 2</description>
  15001. <addressOffset>0x4</addressOffset>
  15002. <size>0x20</size>
  15003. <access>read-write</access>
  15004. <resetValue>0x0000</resetValue>
  15005. <fields>
  15006. <field>
  15007. <name>ADD4_7</name>
  15008. <description>Address of the USART node</description>
  15009. <bitOffset>28</bitOffset>
  15010. <bitWidth>4</bitWidth>
  15011. </field>
  15012. <field>
  15013. <name>ADD0_3</name>
  15014. <description>Address of the USART node</description>
  15015. <bitOffset>24</bitOffset>
  15016. <bitWidth>4</bitWidth>
  15017. </field>
  15018. <field>
  15019. <name>MSBFIRST</name>
  15020. <description>Most significant bit first</description>
  15021. <bitOffset>19</bitOffset>
  15022. <bitWidth>1</bitWidth>
  15023. </field>
  15024. <field>
  15025. <name>TAINV</name>
  15026. <description>Binary data inversion</description>
  15027. <bitOffset>18</bitOffset>
  15028. <bitWidth>1</bitWidth>
  15029. </field>
  15030. <field>
  15031. <name>TXINV</name>
  15032. <description>TX pin active level
  15033. inversion</description>
  15034. <bitOffset>17</bitOffset>
  15035. <bitWidth>1</bitWidth>
  15036. </field>
  15037. <field>
  15038. <name>RXINV</name>
  15039. <description>RX pin active level
  15040. inversion</description>
  15041. <bitOffset>16</bitOffset>
  15042. <bitWidth>1</bitWidth>
  15043. </field>
  15044. <field>
  15045. <name>SWAP</name>
  15046. <description>Swap TX/RX pins</description>
  15047. <bitOffset>15</bitOffset>
  15048. <bitWidth>1</bitWidth>
  15049. </field>
  15050. <field>
  15051. <name>STOP</name>
  15052. <description>STOP bits</description>
  15053. <bitOffset>12</bitOffset>
  15054. <bitWidth>2</bitWidth>
  15055. </field>
  15056. <field>
  15057. <name>CLKEN</name>
  15058. <description>Clock enable</description>
  15059. <bitOffset>11</bitOffset>
  15060. <bitWidth>1</bitWidth>
  15061. </field>
  15062. <field>
  15063. <name>ADDM7</name>
  15064. <description>7-bit Address Detection/4-bit Address
  15065. Detection</description>
  15066. <bitOffset>4</bitOffset>
  15067. <bitWidth>1</bitWidth>
  15068. </field>
  15069. </fields>
  15070. </register>
  15071. <register>
  15072. <name>CR3</name>
  15073. <displayName>CR3</displayName>
  15074. <description>Control register 3</description>
  15075. <addressOffset>0x8</addressOffset>
  15076. <size>0x20</size>
  15077. <access>read-write</access>
  15078. <resetValue>0x0000</resetValue>
  15079. <fields>
  15080. <field>
  15081. <name>WUFIE</name>
  15082. <description>Wakeup from Stop mode interrupt
  15083. enable</description>
  15084. <bitOffset>22</bitOffset>
  15085. <bitWidth>1</bitWidth>
  15086. </field>
  15087. <field>
  15088. <name>WUS</name>
  15089. <description>Wakeup from Stop mode interrupt flag
  15090. selection</description>
  15091. <bitOffset>20</bitOffset>
  15092. <bitWidth>2</bitWidth>
  15093. </field>
  15094. <field>
  15095. <name>DEP</name>
  15096. <description>Driver enable polarity
  15097. selection</description>
  15098. <bitOffset>15</bitOffset>
  15099. <bitWidth>1</bitWidth>
  15100. </field>
  15101. <field>
  15102. <name>DEM</name>
  15103. <description>Driver enable mode</description>
  15104. <bitOffset>14</bitOffset>
  15105. <bitWidth>1</bitWidth>
  15106. </field>
  15107. <field>
  15108. <name>DDRE</name>
  15109. <description>DMA Disable on Reception
  15110. Error</description>
  15111. <bitOffset>13</bitOffset>
  15112. <bitWidth>1</bitWidth>
  15113. </field>
  15114. <field>
  15115. <name>OVRDIS</name>
  15116. <description>Overrun Disable</description>
  15117. <bitOffset>12</bitOffset>
  15118. <bitWidth>1</bitWidth>
  15119. </field>
  15120. <field>
  15121. <name>CTSIE</name>
  15122. <description>CTS interrupt enable</description>
  15123. <bitOffset>10</bitOffset>
  15124. <bitWidth>1</bitWidth>
  15125. </field>
  15126. <field>
  15127. <name>CTSE</name>
  15128. <description>CTS enable</description>
  15129. <bitOffset>9</bitOffset>
  15130. <bitWidth>1</bitWidth>
  15131. </field>
  15132. <field>
  15133. <name>RTSE</name>
  15134. <description>RTS enable</description>
  15135. <bitOffset>8</bitOffset>
  15136. <bitWidth>1</bitWidth>
  15137. </field>
  15138. <field>
  15139. <name>DMAT</name>
  15140. <description>DMA enable transmitter</description>
  15141. <bitOffset>7</bitOffset>
  15142. <bitWidth>1</bitWidth>
  15143. </field>
  15144. <field>
  15145. <name>DMAR</name>
  15146. <description>DMA enable receiver</description>
  15147. <bitOffset>6</bitOffset>
  15148. <bitWidth>1</bitWidth>
  15149. </field>
  15150. <field>
  15151. <name>HDSEL</name>
  15152. <description>Half-duplex selection</description>
  15153. <bitOffset>3</bitOffset>
  15154. <bitWidth>1</bitWidth>
  15155. </field>
  15156. <field>
  15157. <name>EIE</name>
  15158. <description>Error interrupt enable</description>
  15159. <bitOffset>0</bitOffset>
  15160. <bitWidth>1</bitWidth>
  15161. </field>
  15162. </fields>
  15163. </register>
  15164. <register>
  15165. <name>BRR</name>
  15166. <displayName>BRR</displayName>
  15167. <description>Baud rate register</description>
  15168. <addressOffset>0xC</addressOffset>
  15169. <size>0x20</size>
  15170. <access>read-write</access>
  15171. <resetValue>0x0000</resetValue>
  15172. <fields>
  15173. <field>
  15174. <name>BRR</name>
  15175. <description>BRR</description>
  15176. <bitOffset>0</bitOffset>
  15177. <bitWidth>20</bitWidth>
  15178. </field>
  15179. </fields>
  15180. </register>
  15181. <register>
  15182. <name>RQR</name>
  15183. <displayName>RQR</displayName>
  15184. <description>Request register</description>
  15185. <addressOffset>0x18</addressOffset>
  15186. <size>0x20</size>
  15187. <access>write-only</access>
  15188. <resetValue>0x0000</resetValue>
  15189. <fields>
  15190. <field>
  15191. <name>RXFRQ</name>
  15192. <description>Receive data flush request</description>
  15193. <bitOffset>3</bitOffset>
  15194. <bitWidth>1</bitWidth>
  15195. </field>
  15196. <field>
  15197. <name>MMRQ</name>
  15198. <description>Mute mode request</description>
  15199. <bitOffset>2</bitOffset>
  15200. <bitWidth>1</bitWidth>
  15201. </field>
  15202. <field>
  15203. <name>SBKRQ</name>
  15204. <description>Send break request</description>
  15205. <bitOffset>1</bitOffset>
  15206. <bitWidth>1</bitWidth>
  15207. </field>
  15208. </fields>
  15209. </register>
  15210. <register>
  15211. <name>ISR</name>
  15212. <displayName>ISR</displayName>
  15213. <description>Interrupt &amp; status
  15214. register</description>
  15215. <addressOffset>0x1C</addressOffset>
  15216. <size>0x20</size>
  15217. <access>read-only</access>
  15218. <resetValue>0x00C0</resetValue>
  15219. <fields>
  15220. <field>
  15221. <name>REACK</name>
  15222. <description>REACK</description>
  15223. <bitOffset>22</bitOffset>
  15224. <bitWidth>1</bitWidth>
  15225. </field>
  15226. <field>
  15227. <name>TEACK</name>
  15228. <description>TEACK</description>
  15229. <bitOffset>21</bitOffset>
  15230. <bitWidth>1</bitWidth>
  15231. </field>
  15232. <field>
  15233. <name>WUF</name>
  15234. <description>WUF</description>
  15235. <bitOffset>20</bitOffset>
  15236. <bitWidth>1</bitWidth>
  15237. </field>
  15238. <field>
  15239. <name>RWU</name>
  15240. <description>RWU</description>
  15241. <bitOffset>19</bitOffset>
  15242. <bitWidth>1</bitWidth>
  15243. </field>
  15244. <field>
  15245. <name>SBKF</name>
  15246. <description>SBKF</description>
  15247. <bitOffset>18</bitOffset>
  15248. <bitWidth>1</bitWidth>
  15249. </field>
  15250. <field>
  15251. <name>CMF</name>
  15252. <description>CMF</description>
  15253. <bitOffset>17</bitOffset>
  15254. <bitWidth>1</bitWidth>
  15255. </field>
  15256. <field>
  15257. <name>BUSY</name>
  15258. <description>BUSY</description>
  15259. <bitOffset>16</bitOffset>
  15260. <bitWidth>1</bitWidth>
  15261. </field>
  15262. <field>
  15263. <name>CTS</name>
  15264. <description>CTS</description>
  15265. <bitOffset>10</bitOffset>
  15266. <bitWidth>1</bitWidth>
  15267. </field>
  15268. <field>
  15269. <name>CTSIF</name>
  15270. <description>CTSIF</description>
  15271. <bitOffset>9</bitOffset>
  15272. <bitWidth>1</bitWidth>
  15273. </field>
  15274. <field>
  15275. <name>TXE</name>
  15276. <description>TXE</description>
  15277. <bitOffset>7</bitOffset>
  15278. <bitWidth>1</bitWidth>
  15279. </field>
  15280. <field>
  15281. <name>TC</name>
  15282. <description>TC</description>
  15283. <bitOffset>6</bitOffset>
  15284. <bitWidth>1</bitWidth>
  15285. </field>
  15286. <field>
  15287. <name>RXNE</name>
  15288. <description>RXNE</description>
  15289. <bitOffset>5</bitOffset>
  15290. <bitWidth>1</bitWidth>
  15291. </field>
  15292. <field>
  15293. <name>IDLE</name>
  15294. <description>IDLE</description>
  15295. <bitOffset>4</bitOffset>
  15296. <bitWidth>1</bitWidth>
  15297. </field>
  15298. <field>
  15299. <name>ORE</name>
  15300. <description>ORE</description>
  15301. <bitOffset>3</bitOffset>
  15302. <bitWidth>1</bitWidth>
  15303. </field>
  15304. <field>
  15305. <name>NF</name>
  15306. <description>NF</description>
  15307. <bitOffset>2</bitOffset>
  15308. <bitWidth>1</bitWidth>
  15309. </field>
  15310. <field>
  15311. <name>FE</name>
  15312. <description>FE</description>
  15313. <bitOffset>1</bitOffset>
  15314. <bitWidth>1</bitWidth>
  15315. </field>
  15316. <field>
  15317. <name>PE</name>
  15318. <description>PE</description>
  15319. <bitOffset>0</bitOffset>
  15320. <bitWidth>1</bitWidth>
  15321. </field>
  15322. </fields>
  15323. </register>
  15324. <register>
  15325. <name>ICR</name>
  15326. <displayName>ICR</displayName>
  15327. <description>Interrupt flag clear register</description>
  15328. <addressOffset>0x20</addressOffset>
  15329. <size>0x20</size>
  15330. <access>write-only</access>
  15331. <resetValue>0x0000</resetValue>
  15332. <fields>
  15333. <field>
  15334. <name>WUCF</name>
  15335. <description>Wakeup from Stop mode clear
  15336. flag</description>
  15337. <bitOffset>20</bitOffset>
  15338. <bitWidth>1</bitWidth>
  15339. </field>
  15340. <field>
  15341. <name>CMCF</name>
  15342. <description>Character match clear flag</description>
  15343. <bitOffset>17</bitOffset>
  15344. <bitWidth>1</bitWidth>
  15345. </field>
  15346. <field>
  15347. <name>CTSCF</name>
  15348. <description>CTS clear flag</description>
  15349. <bitOffset>9</bitOffset>
  15350. <bitWidth>1</bitWidth>
  15351. </field>
  15352. <field>
  15353. <name>TCCF</name>
  15354. <description>Transmission complete clear
  15355. flag</description>
  15356. <bitOffset>6</bitOffset>
  15357. <bitWidth>1</bitWidth>
  15358. </field>
  15359. <field>
  15360. <name>IDLECF</name>
  15361. <description>Idle line detected clear
  15362. flag</description>
  15363. <bitOffset>4</bitOffset>
  15364. <bitWidth>1</bitWidth>
  15365. </field>
  15366. <field>
  15367. <name>ORECF</name>
  15368. <description>Overrun error clear flag</description>
  15369. <bitOffset>3</bitOffset>
  15370. <bitWidth>1</bitWidth>
  15371. </field>
  15372. <field>
  15373. <name>NCF</name>
  15374. <description>Noise detected clear flag</description>
  15375. <bitOffset>2</bitOffset>
  15376. <bitWidth>1</bitWidth>
  15377. </field>
  15378. <field>
  15379. <name>FECF</name>
  15380. <description>Framing error clear flag</description>
  15381. <bitOffset>1</bitOffset>
  15382. <bitWidth>1</bitWidth>
  15383. </field>
  15384. <field>
  15385. <name>PECF</name>
  15386. <description>Parity error clear flag</description>
  15387. <bitOffset>0</bitOffset>
  15388. <bitWidth>1</bitWidth>
  15389. </field>
  15390. </fields>
  15391. </register>
  15392. <register>
  15393. <name>RDR</name>
  15394. <displayName>RDR</displayName>
  15395. <description>Receive data register</description>
  15396. <addressOffset>0x24</addressOffset>
  15397. <size>0x20</size>
  15398. <access>read-only</access>
  15399. <resetValue>0x0000</resetValue>
  15400. <fields>
  15401. <field>
  15402. <name>RDR</name>
  15403. <description>Receive data value</description>
  15404. <bitOffset>0</bitOffset>
  15405. <bitWidth>9</bitWidth>
  15406. </field>
  15407. </fields>
  15408. </register>
  15409. <register>
  15410. <name>TDR</name>
  15411. <displayName>TDR</displayName>
  15412. <description>Transmit data register</description>
  15413. <addressOffset>0x28</addressOffset>
  15414. <size>0x20</size>
  15415. <access>read-write</access>
  15416. <resetValue>0x0000</resetValue>
  15417. <fields>
  15418. <field>
  15419. <name>TDR</name>
  15420. <description>Transmit data value</description>
  15421. <bitOffset>0</bitOffset>
  15422. <bitWidth>9</bitWidth>
  15423. </field>
  15424. </fields>
  15425. </register>
  15426. </registers>
  15427. </peripheral>
  15428. <peripheral>
  15429. <name>NVIC</name>
  15430. <description>Nested Vectored Interrupt
  15431. Controller</description>
  15432. <groupName>NVIC</groupName>
  15433. <baseAddress>0xE000E100</baseAddress>
  15434. <addressBlock>
  15435. <offset>0x0</offset>
  15436. <size>0x33D</size>
  15437. <usage>registers</usage>
  15438. </addressBlock>
  15439. <registers>
  15440. <register>
  15441. <name>ISER</name>
  15442. <displayName>ISER</displayName>
  15443. <description>Interrupt Set Enable Register</description>
  15444. <addressOffset>0x0</addressOffset>
  15445. <size>0x20</size>
  15446. <access>read-write</access>
  15447. <resetValue>0x00000000</resetValue>
  15448. <fields>
  15449. <field>
  15450. <name>SETENA</name>
  15451. <description>SETENA</description>
  15452. <bitOffset>0</bitOffset>
  15453. <bitWidth>32</bitWidth>
  15454. </field>
  15455. </fields>
  15456. </register>
  15457. <register>
  15458. <name>ICER</name>
  15459. <displayName>ICER</displayName>
  15460. <description>Interrupt Clear Enable
  15461. Register</description>
  15462. <addressOffset>0x80</addressOffset>
  15463. <size>0x20</size>
  15464. <access>read-write</access>
  15465. <resetValue>0x00000000</resetValue>
  15466. <fields>
  15467. <field>
  15468. <name>CLRENA</name>
  15469. <description>CLRENA</description>
  15470. <bitOffset>0</bitOffset>
  15471. <bitWidth>32</bitWidth>
  15472. </field>
  15473. </fields>
  15474. </register>
  15475. <register>
  15476. <name>ISPR</name>
  15477. <displayName>ISPR</displayName>
  15478. <description>Interrupt Set-Pending Register</description>
  15479. <addressOffset>0x100</addressOffset>
  15480. <size>0x20</size>
  15481. <access>read-write</access>
  15482. <resetValue>0x00000000</resetValue>
  15483. <fields>
  15484. <field>
  15485. <name>SETPEND</name>
  15486. <description>SETPEND</description>
  15487. <bitOffset>0</bitOffset>
  15488. <bitWidth>32</bitWidth>
  15489. </field>
  15490. </fields>
  15491. </register>
  15492. <register>
  15493. <name>ICPR</name>
  15494. <displayName>ICPR</displayName>
  15495. <description>Interrupt Clear-Pending
  15496. Register</description>
  15497. <addressOffset>0x180</addressOffset>
  15498. <size>0x20</size>
  15499. <access>read-write</access>
  15500. <resetValue>0x00000000</resetValue>
  15501. <fields>
  15502. <field>
  15503. <name>CLRPEND</name>
  15504. <description>CLRPEND</description>
  15505. <bitOffset>0</bitOffset>
  15506. <bitWidth>32</bitWidth>
  15507. </field>
  15508. </fields>
  15509. </register>
  15510. <register>
  15511. <name>IPR0</name>
  15512. <displayName>IPR0</displayName>
  15513. <description>Interrupt Priority Register 0</description>
  15514. <addressOffset>0x300</addressOffset>
  15515. <size>0x20</size>
  15516. <access>read-write</access>
  15517. <resetValue>0x00000000</resetValue>
  15518. <fields>
  15519. <field>
  15520. <name>PRI_0</name>
  15521. <description>priority for interrupt 0</description>
  15522. <bitOffset>0</bitOffset>
  15523. <bitWidth>8</bitWidth>
  15524. </field>
  15525. <field>
  15526. <name>PRI_1</name>
  15527. <description>priority for interrupt 1</description>
  15528. <bitOffset>8</bitOffset>
  15529. <bitWidth>8</bitWidth>
  15530. </field>
  15531. <field>
  15532. <name>PRI_2</name>
  15533. <description>priority for interrupt 2</description>
  15534. <bitOffset>16</bitOffset>
  15535. <bitWidth>8</bitWidth>
  15536. </field>
  15537. <field>
  15538. <name>PRI_3</name>
  15539. <description>priority for interrupt 3</description>
  15540. <bitOffset>24</bitOffset>
  15541. <bitWidth>8</bitWidth>
  15542. </field>
  15543. </fields>
  15544. </register>
  15545. <register>
  15546. <name>IPR1</name>
  15547. <displayName>IPR1</displayName>
  15548. <description>Interrupt Priority Register 1</description>
  15549. <addressOffset>0x304</addressOffset>
  15550. <size>0x20</size>
  15551. <access>read-write</access>
  15552. <resetValue>0x00000000</resetValue>
  15553. <fields>
  15554. <field>
  15555. <name>PRI_4</name>
  15556. <description>priority for interrupt n</description>
  15557. <bitOffset>0</bitOffset>
  15558. <bitWidth>8</bitWidth>
  15559. </field>
  15560. <field>
  15561. <name>PRI_5</name>
  15562. <description>priority for interrupt n</description>
  15563. <bitOffset>8</bitOffset>
  15564. <bitWidth>8</bitWidth>
  15565. </field>
  15566. <field>
  15567. <name>PRI_6</name>
  15568. <description>priority for interrupt n</description>
  15569. <bitOffset>16</bitOffset>
  15570. <bitWidth>8</bitWidth>
  15571. </field>
  15572. <field>
  15573. <name>PRI_7</name>
  15574. <description>priority for interrupt n</description>
  15575. <bitOffset>24</bitOffset>
  15576. <bitWidth>8</bitWidth>
  15577. </field>
  15578. </fields>
  15579. </register>
  15580. <register>
  15581. <name>IPR2</name>
  15582. <displayName>IPR2</displayName>
  15583. <description>Interrupt Priority Register 2</description>
  15584. <addressOffset>0x308</addressOffset>
  15585. <size>0x20</size>
  15586. <access>read-write</access>
  15587. <resetValue>0x00000000</resetValue>
  15588. <fields>
  15589. <field>
  15590. <name>PRI_8</name>
  15591. <description>priority for interrupt n</description>
  15592. <bitOffset>0</bitOffset>
  15593. <bitWidth>8</bitWidth>
  15594. </field>
  15595. <field>
  15596. <name>PRI_9</name>
  15597. <description>priority for interrupt n</description>
  15598. <bitOffset>8</bitOffset>
  15599. <bitWidth>8</bitWidth>
  15600. </field>
  15601. <field>
  15602. <name>PRI_10</name>
  15603. <description>priority for interrupt n</description>
  15604. <bitOffset>16</bitOffset>
  15605. <bitWidth>8</bitWidth>
  15606. </field>
  15607. <field>
  15608. <name>PRI_11</name>
  15609. <description>priority for interrupt n</description>
  15610. <bitOffset>24</bitOffset>
  15611. <bitWidth>8</bitWidth>
  15612. </field>
  15613. </fields>
  15614. </register>
  15615. <register>
  15616. <name>IPR3</name>
  15617. <displayName>IPR3</displayName>
  15618. <description>Interrupt Priority Register 3</description>
  15619. <addressOffset>0x30C</addressOffset>
  15620. <size>0x20</size>
  15621. <access>read-write</access>
  15622. <resetValue>0x00000000</resetValue>
  15623. <fields>
  15624. <field>
  15625. <name>PRI_12</name>
  15626. <description>priority for interrupt n</description>
  15627. <bitOffset>0</bitOffset>
  15628. <bitWidth>8</bitWidth>
  15629. </field>
  15630. <field>
  15631. <name>PRI_13</name>
  15632. <description>priority for interrupt n</description>
  15633. <bitOffset>8</bitOffset>
  15634. <bitWidth>8</bitWidth>
  15635. </field>
  15636. <field>
  15637. <name>PRI_14</name>
  15638. <description>priority for interrupt n</description>
  15639. <bitOffset>16</bitOffset>
  15640. <bitWidth>8</bitWidth>
  15641. </field>
  15642. <field>
  15643. <name>PRI_15</name>
  15644. <description>priority for interrupt n</description>
  15645. <bitOffset>24</bitOffset>
  15646. <bitWidth>8</bitWidth>
  15647. </field>
  15648. </fields>
  15649. </register>
  15650. <register>
  15651. <name>IPR4</name>
  15652. <displayName>IPR4</displayName>
  15653. <description>Interrupt Priority Register 4</description>
  15654. <addressOffset>0x310</addressOffset>
  15655. <size>0x20</size>
  15656. <access>read-write</access>
  15657. <resetValue>0x00000000</resetValue>
  15658. <fields>
  15659. <field>
  15660. <name>PRI_16</name>
  15661. <description>priority for interrupt n</description>
  15662. <bitOffset>0</bitOffset>
  15663. <bitWidth>8</bitWidth>
  15664. </field>
  15665. <field>
  15666. <name>PRI_17</name>
  15667. <description>priority for interrupt n</description>
  15668. <bitOffset>8</bitOffset>
  15669. <bitWidth>8</bitWidth>
  15670. </field>
  15671. <field>
  15672. <name>PRI_18</name>
  15673. <description>priority for interrupt n</description>
  15674. <bitOffset>16</bitOffset>
  15675. <bitWidth>8</bitWidth>
  15676. </field>
  15677. <field>
  15678. <name>PRI_19</name>
  15679. <description>priority for interrupt n</description>
  15680. <bitOffset>24</bitOffset>
  15681. <bitWidth>8</bitWidth>
  15682. </field>
  15683. </fields>
  15684. </register>
  15685. <register>
  15686. <name>IPR5</name>
  15687. <displayName>IPR5</displayName>
  15688. <description>Interrupt Priority Register 5</description>
  15689. <addressOffset>0x314</addressOffset>
  15690. <size>0x20</size>
  15691. <access>read-write</access>
  15692. <resetValue>0x00000000</resetValue>
  15693. <fields>
  15694. <field>
  15695. <name>PRI_20</name>
  15696. <description>priority for interrupt n</description>
  15697. <bitOffset>0</bitOffset>
  15698. <bitWidth>8</bitWidth>
  15699. </field>
  15700. <field>
  15701. <name>PRI_21</name>
  15702. <description>priority for interrupt n</description>
  15703. <bitOffset>8</bitOffset>
  15704. <bitWidth>8</bitWidth>
  15705. </field>
  15706. <field>
  15707. <name>PRI_22</name>
  15708. <description>priority for interrupt n</description>
  15709. <bitOffset>16</bitOffset>
  15710. <bitWidth>8</bitWidth>
  15711. </field>
  15712. <field>
  15713. <name>PRI_23</name>
  15714. <description>priority for interrupt n</description>
  15715. <bitOffset>24</bitOffset>
  15716. <bitWidth>8</bitWidth>
  15717. </field>
  15718. </fields>
  15719. </register>
  15720. <register>
  15721. <name>IPR6</name>
  15722. <displayName>IPR6</displayName>
  15723. <description>Interrupt Priority Register 6</description>
  15724. <addressOffset>0x318</addressOffset>
  15725. <size>0x20</size>
  15726. <access>read-write</access>
  15727. <resetValue>0x00000000</resetValue>
  15728. <fields>
  15729. <field>
  15730. <name>PRI_24</name>
  15731. <description>priority for interrupt n</description>
  15732. <bitOffset>0</bitOffset>
  15733. <bitWidth>8</bitWidth>
  15734. </field>
  15735. <field>
  15736. <name>PRI_25</name>
  15737. <description>priority for interrupt n</description>
  15738. <bitOffset>8</bitOffset>
  15739. <bitWidth>8</bitWidth>
  15740. </field>
  15741. <field>
  15742. <name>PRI_26</name>
  15743. <description>priority for interrupt n</description>
  15744. <bitOffset>16</bitOffset>
  15745. <bitWidth>8</bitWidth>
  15746. </field>
  15747. <field>
  15748. <name>PRI_27</name>
  15749. <description>priority for interrupt n</description>
  15750. <bitOffset>24</bitOffset>
  15751. <bitWidth>8</bitWidth>
  15752. </field>
  15753. </fields>
  15754. </register>
  15755. <register>
  15756. <name>IPR7</name>
  15757. <displayName>IPR7</displayName>
  15758. <description>Interrupt Priority Register 7</description>
  15759. <addressOffset>0x31C</addressOffset>
  15760. <size>0x20</size>
  15761. <access>read-write</access>
  15762. <resetValue>0x00000000</resetValue>
  15763. <fields>
  15764. <field>
  15765. <name>PRI_28</name>
  15766. <description>priority for interrupt n</description>
  15767. <bitOffset>0</bitOffset>
  15768. <bitWidth>8</bitWidth>
  15769. </field>
  15770. <field>
  15771. <name>PRI_29</name>
  15772. <description>priority for interrupt n</description>
  15773. <bitOffset>8</bitOffset>
  15774. <bitWidth>8</bitWidth>
  15775. </field>
  15776. <field>
  15777. <name>PRI_30</name>
  15778. <description>priority for interrupt n</description>
  15779. <bitOffset>16</bitOffset>
  15780. <bitWidth>8</bitWidth>
  15781. </field>
  15782. <field>
  15783. <name>PRI_31</name>
  15784. <description>priority for interrupt n</description>
  15785. <bitOffset>24</bitOffset>
  15786. <bitWidth>8</bitWidth>
  15787. </field>
  15788. </fields>
  15789. </register>
  15790. </registers>
  15791. </peripheral>
  15792. </peripherals>
  15793. </device>