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Devices/Altera/Cyclone_V/Altera_Cyclone_V.JLinkScript

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+/*********************************************************************
+*               (c) SEGGER Microcontroller GmbH & Co. KG             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : Altera_Cyclone_V.JLinkScript
+Purpose : Script file for Cyclone V series devices
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings
+*/
+int ConfigTargetSettings(void) {
+  //
+  // For the Cyclone V device to work with J-Link the Core type needs to be set manually.
+  //
+  CPU = CORTEX_A9;
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/AnalogDevices/ADSP-CM41/CM41x_M4.JLinkScript

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+// Reset script for ADSP-CM41x, Cortex-M4 core.
+// Copyright (c) 2016 Analog Devices, Inc. All Rights Reserved.
+//
+// This script is for use with Segger JLink Lite emulators, to
+// connect to the Cortex-M4 core of the ADSP-CM41x processor.
+//
+// When the processor's security is enabled, debugger access is
+// disabled until secure keys are provided. If using custom key
+// values instead of the default key values, modify the values
+// passed by this script.
+// Note that there TWO sets of locations to change in this script 
+// - one for JTAG connections, and one for SWD connections.
+
+int GetScriptVersion(void) {
+  //
+  // Make sure that J-Link DLL does not ignore InitTraget() from script file
+  // Return values for Analog Devices:
+  //   <  100: Perform DLL internal connect sequence
+  //   >= 100: Perform InitTarget() from script file
+  //
+  return 100;                   
+}
+
+void ResetTarget(void) {
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe0002008);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x8001031b);   // don't vector flash
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000200c);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x800102f7);   // don't vector uart
+  SYS_Sleep(300);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe0002000);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x00000007);   // enable fpb patch 0+1
+  SYS_Sleep(300);
+
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000ed0c);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x05fa0004);   // reset
+
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000edf0);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xa05f0001);   // enable debug
+  SYS_Sleep(300);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0xe000edf0);
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0xa05f0003);   // halt
+
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: Resetting and halting Cortex-M4 core.");
+}
+
+
+/*********************************************************************
+*
+*       _InitTargetSWD
+*
+**********************************************************************/
+int _InitTargetSWD(void) {
+  CPU                = CORTEX_M4;
+  JTAG_AllowTAPReset = 0;
+
+  // reset the board
+
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: SWD connection");
+  JTAG_ResetPin=0;
+  SYS_Sleep(300);
+  JTAG_ResetPin=1;
+  SYS_Sleep(300);
+
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: SWD: send secure keys");
+
+  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0x50000031);  // Set SYSPWRUPREQ and DBGPWRUPREQ and overrun detection
+  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 24) | (0 << 4));      // Select AHB-AP bank 0 (data read/write registers)
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, 0x23000042);
+
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017050);                  // SDBGKEYCOMP0	
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x11111111);                  // Replace 0x11111111 with your value
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017054);                  // SDBGKEYCOMP1	
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x22222222);                  // Replace 0x22222222 with your value
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x40017058);                  // SDBGKEYCOMP2	
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x33333333);                  // Replace 0x33333333 with your value
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, 0x4001705c);                  // SDBGKEYCOMP3	
+  JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, 0x44444444);                  // Replace 0x44444444 with your value
+  return 0;
+}
+
+/*********************************************************************
+*
+*       _InitTargetJTAG
+*
+**********************************************************************/
+int _InitTargetJTAG(void) {
+  int TAPCIdCode;
+  int DPIdCode;
+  int BitPos;
+  int TryAgain;
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: JTAG connection");
+
+  TryAgain = 0;
+Reconnect:
+  JTAG_Reset();                           // Perform TAP reset and J-Link JTAG auto-detection
+  if (JTAG_TotalIRLen != 5) {
+    if (TryAgain == 0) {
+      //
+      // Toggle reset and retry the connect sequence
+      //
+      Report("CM41x_M4.JLinkScript-v1.0.0.0: ADI TAPC not found (IRLen mismatch). Performing recovery sequence");
+      JTAG_ResetPin = 0;
+      SYS_Sleep(300);
+      JTAG_ResetPin = 1;
+      SYS_Sleep(300);
+      TryAgain = 1;
+      goto Reconnect;
+    }
+    Report1("CM41x_M4.JLinkScript-v1.0.0.0: ADI TAPC not found (IRLen mismatch), Found: ", JTAG_TotalIRLen);
+    return -1;
+  }
+  //
+  // Configure JTAG chain
+  //
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=5");          // Does not hurt to configure the JTAG chain if SWD is used, as these params are simply not used for SWD
+  //
+  // Check TAPC device ID
+  //
+  JTAG_WriteIR(0x2); // IDCODE instruction for TAPC device
+  BitPos = JTAG_WriteDR(0x00000000, 32);
+  TAPCIdCode = JTAG_GetU32(BitPos);
+  if ((TAPCIdCode & 0x0FFFFFFF) != 0x0280b0cb) {    // Highest nibble holds version information, so it can not be used for verification.
+    Report1("CM41x_M4.JLinkScript-v1.0.0.0: Can not find TAPC (IDCODE mismatch). Expected 0x0280b0cb, found: ", TAPCIdCode & 0x0FFFFFFF);
+    return -1;
+  }
+  //
+  // Send 128-bit unlock key to device
+  //
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: JTAG: Send secure keys");
+  JTAG_WriteIR(0xA);  
+  JTAG_StartDR();
+  JTAG_WriteDRCont(0x11111111, 32);  // SDBKEY 0: Replace 0x11111111 with your value
+  JTAG_WriteDRCont(0x22222222, 32);  // SDBKEY 1: Replace 0x22222222 with your value
+  JTAG_WriteDRCont(0x33333333, 32);  // SDBKEY 2: Replace 0x33333333 with your value
+  JTAG_WriteDREnd(0x44444444, 32);   // SDBKEY 3: Replace 0x44444444 with your value
+  JTAG_WriteClocks(1);               // Make sure that we go through Idle state in TAP controller
+  // set bit 0 in JTAG_CTL
+  // This adds the M4 and M0 to the chain
+  // New chain layout:
+  // #0 M0 (closest to TDO)
+  // #1 M4
+  // #2 TAPC
+  //  
+  JTAG_WriteIR(5);
+  BitPos = JTAG_WriteDR(0x5, 0x8);
+  //
+  // Select M4 TAP to communicate with
+  // Get DAP-Id
+  // Set DLL variables for further debugging
+  //
+  JTAG_AllowTAPReset = 0;
+  JLINK_CORESIGHT_Configure("IRPre=4;DRPre=1;IRPost=5;DRPost=1;IRLenDevice=4; PerformTIFInit=0");          // Does not hurt to configure the JTAG chain if SWD is used, as these params are simply not used for SWD
+  CPU=CORTEX_M4;
+  Report("CM41x_M4.JLinkScript-v1.0.0.0: starting Cortex-M4 core");
+  JTAG_WriteIR(0xE);
+  BitPos = JTAG_WriteDR(0x00000000, 32);
+  DPIdCode = JTAG_GetU32(BitPos);
+  if (((DPIdCode & 0xFFFFFFFF) != 0x4BA00477)) {
+    Report1("CM41x_M4.JLinkScript-v1.0.0.0: Can not find Cortex-M4 (IDCODE mismatch). Expected 0x4BA00477, found: ", DPIdCode);
+    return -1;
+  } else {
+    Report ("CM41x_M4.JLinkScript-v1.0.0.0: Found Cortex-M4");
+    //
+    // Set Device Ids (needed by DLL in case JTAG is used)
+    //
+    JTAG_SetDeviceId(0, 0x0BA00000);   // M0
+    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 0");
+    JTAG_SetDeviceId(1, DPIdCode);     // M4
+    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 1");
+    JTAG_SetDeviceId(2, TAPCIdCode);   // TAPC
+    Report ("CM41x_M4.JLinkScript-v1.0.0.0: set device id 2");
+  }
+  return 0;
+}
+
+void InitTarget(void) {
+  int r;
+  int Speed;
+
+  Report("*********************************");
+  Report("* CM41x_M4.JLinkScript-v1.0.0.0 *");
+  Report("*********************************"); 
+  //
+  // Remember original target interface speed and set new one
+  //
+  Speed       = JTAG_Speed;
+  JTAG_Speed  = 0x1000;
+  //
+  // Perform target interface specific connect sequence
+  //
+  if (MAIN_ActiveTIF == JLINK_TIF_JTAG) {
+    r = _InitTargetJTAG();
+  } else {
+    r = _InitTargetSWD();
+  }
+  //
+  // Restore original target interface speed settings
+  //
+  JTAG_Speed = Speed;
+  return r;
+}
+
+
+

Devices/AnalogDevices/Readme.txt

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+The Analog Devices ADSP-CM41x series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Analog Devices only.
+For support, please contact: processor.tools.support@analog.com
+
+

Devices/Broadcom/BCM43907.JLinkScript

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+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : BCM43907.JLinkScript
+Purpose : Handle reset for Broadcom BCM43907 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+//
+// User-specified constants to be used by PCode
+//
+__constant U32 _DBG_REG_VCR         = 0x007;      // Vector Catch Register
+__constant U32 _DBG_REG_PRCR        = 0x0C4;      // Device Power-down and Reset Control Register
+__constant U32 _DBG_REG_PRSR        = 0x0C5;      // Device Power-down and Reset Status Register
+__constant U32 _DBG_REG_LOCKACCESS  = 0x3EC;
+__constant U32 _DBG_REG_LOCKSTATUS  = 0x3ED;
+__constant U32 _ACTIVATION_KEY      = 0xC5ACCE55;
+__constant U32 _DBG_REG_DSCR        = 0x022;      // Debug Status and Control Register
+__constant U32 _DBG_REG_DRCR        = 0x024;      // Debug Run Control Register
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  int Ctrl;
+  int v;
+  int BaseAddr;
+
+  BaseAddr = 0x80001000;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (0 << 24) | (0 << 4));  // Select AP[0], bank 0
+  Ctrl =  0
+       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
+       | (0 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
+       | (1 << 31)   // Enable software access to the Debug APB bus.
+       ;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);  
+  //
+  // Prepare CPU to be halted immediately after reset (vector catch)
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_VCR << 2));          // DBG_REG_VCR
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);                                // Set reset vector catch
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRCR << 2));          // DBG_REG_PRCR
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);                                // Make sure that device is not held in reset
+  //
+  // Reset CPU by toggling reset pin
+  // Wait some time after reset release to give pin some time to get HIGH
+  // and to give ROM BTL of SAMA5 some time to finish its work and enable debug access
+  //
+  JLINK_JTAG_ResetPin = 0;
+  JLINK_SYS_Sleep(100);
+  JLINK_JTAG_ResetPin = 1;
+  JLINK_SYS_Sleep(100);
+  //
+  // Check if CPU is halted. If not, halt it.
+  // Select & setup APB-AP
+  //
+  Report("J-Link script: Reset");
+  JTAG_Write(0x1F, 0, 6);                                                            // Perform TAP reset
+  v = (1 << 1) | (1 << 30) | (1 << 28);                                              // Request power-up on debug and system port, Make sure that sticky overrun bit gets cleared
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (0 << 24) | (0 << 4));  // Select AP[0], bank 0
+  Ctrl =  0
+       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
+       | (0 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
+       | (1 << 31)   // Enable software access to the Debug APB bus.
+       ;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);
+  //
+  // Init debug logic
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_LOCKACCESS << 2));
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, _ACTIVATION_KEY);                        // Unlock access to the debug registers
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_LOCKSTATUS << 2));
+  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRCR << 2));
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x1);                                    // Disable power-down mode
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRSR << 2));
+  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
+  //
+  // Read DSCR to check if CPU is halted and halt it, if necessary
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DSCR << 2));
+  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
+  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
+  if ((v & 1) == 0) {
+    JLINK_SYS_Report("J-Link script: Core did not halt after reset. Halting core...");
+    v |= (1 << 14);
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DSCR << 2));   // Enable debug halt mode by writing the DSCR
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, v);
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DRCR << 2));   // Write DRCR to halt CPU
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);
+    v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);                                     // Write to AP may be delayed until next read/write, so perform a dummy read
+  }
+  //
+  // Clear vector catch
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_VCR << 2));
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0);
+  Report("J-Link script: Done");
+}
+

Devices/ClouderSemi/CR600/CR600.JLinkScript

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+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : ClouderSemi_CR600.JLinkScript
+Purpose : Contains device specific handling for ClouderSemi's CR600 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+int AfterResetTarget(void) {
+  //
+  // The flash of the CR600 (Cortex-M0) is located at address 0x20000000. This makes problems
+  // for the IDE / debug probe as a default debug session start would fail as no breakpoint can
+  // be set at the beginning of the application (flash) for two reasons:
+  //   1) HW breakpoint --> Does not work due to the limitation of the core (does not allow HW BPs at addresses >= 0x20000000)
+  //   2) Software breakpoint --> Does not work as it is flash memory
+  //
+  // Respecting those limitations, the only way to perform a correct debug session start (CPU
+  // is halted at the application start (using a breakpoint) is to use flash breakpoints. Unfortunately,
+  // the flash cannot be access after reset as it is enabled when the bootloader is executed. As there
+  // is no option to halt the CPU *after* bootloader execution and *before* any target application code has been executed,
+  // we perform some parts of the bootloader manually which allow us to program the flash and therefore allow us to set a
+  // flash breakpoint at the application start.
+  //
+  // The sequence below comes from ClouderSemi.
+  // SEGGER does neither provide any support for it nor guarantees the correct functionality.
+  //
+  JLINK_SYS_Report("Executing AfterResetTarget()");  
+  JLINK_MEM_WriteU32(0x4009B050, 0x3C);
+  JLINK_MEM_WriteU32(0x40085000, 0x10);
+  JLINK_MEM_WriteU32(0x40085008, 0x8);
+  JLINK_MEM_WriteU32(0x4008500C, 0x3);
+  JLINK_MEM_WriteU32(0x40085010, 0x18);
+  JLINK_MEM_WriteU32(0x4008502C, 0x0);
+  JLINK_MEM_WriteU32(0x40085004, 0x3012);  
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/ClouderSemi/CR600/Readme.txt

@@ -0,0 +1,2 @@
+The ClouderSemi CR600 series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via ClouderSemi only.
+For support, please contact: chang.nan@cloudersemi.com

Devices/Cypress/PSoC6/CY8C6xxx_CM0p.JLinkScript

@@ -0,0 +1,32 @@
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+  
+  // Exclude eFuse
+  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+}
+
+void InitTarget(void) {
+  Report("********************************************");
+  Report("InitTarget for PSoC6 Cortex-M0+ script");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 1;
+  CPU=CORTEX_M0;
+  Report("********************************************");
+}

Devices/Cypress/PSoC6/CY8C6xxx_CM0p_tm_xA.JLinkScript

@@ -0,0 +1,327 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC 6 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _CPUSS_CM0_VTBASE                 = 0x402102B0; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
+__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK         = 0xFFFFFF00; // Set by boot code if flash is empty or secure application
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 1000);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+//  // Exclude eFuse
+//  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  U32 vtBase;
+  U32 resetAddr;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  //
+  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
+  // In this case boot code jumps to infinite loop in ROM.
+  // This case is sufficient condition for programming, but has no sense for debugging
+  // Otherwise, application exist, so need to set correct PC/SP for debugging
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _CPUSS_CM0_VTBASE);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &vtBase);
+  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
+  
+  if (vtBase != 0 && vtBase != _CPUSS_CMX_VTBASE_ERR_MSK) {
+
+    // Get address at reset vector
+    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase + 4);
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &resetAddr);
+    if (resetAddr != 0) {
+  
+      // Set PC with address at reset
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, resetAddr);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+    
+      // Get address at vector table & set SP
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, vtBase);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+    
+      //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+      v |= 0x01000000;
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+      JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+	}
+  }
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxx_CM0p_tm_xx.JLinkScript

@@ -0,0 +1,309 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : CY8C6xxx_CM0p_tm.JLinkScript
+Purpose : J-Link script file for Cypress PSoC 6 series
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+
+__constant U32 _ACCESS_DP                        = 0;
+__constant U32 _ACCESS_AP                        = 1;
+__constant U32 _DHCSR_ADDR                       = 0xE000EDF0; // Debug Halting Control and Status Register
+__constant U32 _DEMCR_ADDR                       = 0xE000EDFC; // Debug Exception and Monitor Control Register
+__constant U32 _DCRDR_ADDR                       = 0xE000EDF8; // Debug Core Register Data Register
+__constant U32 _DCRSR_ADDR                       = 0xE000EDF4; // Debug Core Register Selector Register
+__constant U32 _DAP_ACC_32BIT_NO_AUTO_INC        = (1 << 29) | (1 << 25) | (1 << 24) | (0 << 4) | (2 << 0);
+__constant U32 _VECTOR_ADDR                      = 0x10000000; // Vector table for M0+ application
+
+
+/*********************************************************************
+*
+*       Static data
+*
+**********************************************************************
+*/
+
+const U8 _aData_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x9E, 0xE7,                                            // Switching sequence STM32
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,              // Line reset (min. 50 clocks SWDIO == HIGH)
+  0x00, 0x00                                             // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
+};
+
+const U8 _aDir_SeqSwitchToSWD[] = {
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF,
+  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+  0xFF, 0xFF
+};
+
+U8 _aDataOut[18];                                  // Needs to be big enough to hold data for longest sequence
+
+/*********************************************************************
+*
+*       Local functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       _PerformChipAcquisitionSeq()
+*
+*  Function description
+*    Performs the Cypress PSoC6-specific chip acquisition sequence.
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
+*/
+int _PerformChipAcquisitionSeq(void) {
+  U32 v;
+  U32 OrgTIFSpeed;
+  int t;
+  int tDelta;
+  //
+  // Perform Cypress PSoC 6 chip acquisition sequence
+  // This is the recommended connection sequence, to make sure that we can gain control over the device again, even if there is bad code running on it
+  //   nRESET == LOW
+  //   nRESET == HIGH
+  //   xx us (Wait for reset release)
+  //   xx us (wait for secure boot code to finish)
+  //   JTAGToSWDSwitching()
+  //   Set TST_CTRL
+  //   Device waits for app. 1500 us to receive the switching sequence + set TST_CTRL before it starts the user application
+  //
+  // We do not wait any fixed delay after reset release.
+  // We just output the switching sequence and try to read the SW-DP Id. This is repeated, until successful.
+  // This is done because the whole chip acquisition sequence is very time critical
+  //
+  //
+  // Make sure that J-Link is using a high target interface speed,
+  // so we can meet the timing requirements for "chip acquisition sequence"
+  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
+  //
+  OrgTIFSpeed = JLINK_JTAG_Speed;
+  JLINK_JTAG_Speed = 4000;
+  //
+  // Preconfigure some CoreSight settings as time is not critical at this point
+  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP
+  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Reset device, so it will wait for "device acquisition sequence"
+  //
+  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
+  JLINK_SYS_Sleep(10);      // Make sure that device recognizes the reset
+  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
+  //
+  // Wait until device becomes responsive
+  //
+  t = JLINK_GetTime();
+  do {
+    JLINK_SWD_ReadWriteBits(&_aData_SeqSwitchToSWD[0], &_aDir_SeqSwitchToSWD[0], &_aDataOut[0], 18 * 8);
+    v = 0;
+    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, 0, &v);
+    v &= 0x0F000FFF;
+    if (v == 0x0B000477) {                      // DAP is responsive?
+      break;
+    }
+    tDelta = JLINK_GetTime() - t;
+  } while (tDelta < 50);                        // Timeout reached?
+  //
+  // Put device into test mode, so it does not start the user application
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, 0x50000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, 0x00000000);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, 0x00000002);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, 0x40260100);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x80000000);  
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, 0, &v);   // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  //
+  // Restore CORESIGHT settings (See beginning of this function call for more info)
+  //
+  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0"); // Suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
+  //
+  // Restore original TIF speed
+  //
+  JLINK_JTAG_Speed = OrgTIFSpeed;
+  return 0;
+}
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings()
+*
+*  Function description
+*    Called before InitTarget(). Maninly used to set some global DLL variables to customize the normal connect procedure.
+*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
+*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
+*    May also be used to specify the device name in case debugger does not pass it to the DLL.
+*
+*  Notes
+*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
+*    (2) Should only set some global DLL variables
+*/
+int ConfigTargetSettings(void) {
+  Report("*****************************************************************");
+  Report("JLinkScript: Start 'ConfigTargetSettings' for PSoC6xxx Cortex-M0+");
+
+  //
+  // The PSoC 6 has the following APs:
+  // AP[0]  SYS-AP (used for chip acquisition sequence)
+  // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
+  // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);
+  JLINK_CORESIGHT_IndexAHBAPToUse = 1; // AP-Index of AHB-AP to use for communication with core
+  CPU=CORTEX_M0;
+
+//  //
+//  // Mark a specific memory region as memory type illegal
+//  // in order to make sure that the software is not allowed to access these regions
+//  // Note: This does not work for J-Flash tool
+//  //
+//  // Exclude SFLASH regions
+//  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+//  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+//  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+//  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+//  // Exclude Cy Metadata
+//  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+//  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+//  // Exclude eFuse
+//  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+
+  Report("*****************************************************************");
+  return 0;
+}
+
+/*********************************************************************
+*
+*       ResetTarget()
+*
+*  Function description
+*    Replaces selected reset strategy of J-Link software.
+*    No matter what reset type is selected, if this function is present, it will be called instead of the selected reset strategy
+*
+*  Return value
+*    >= 0  O.K.
+*    <  0  Error
+*
+*  Notes
+*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
+*    (2) May use MEM_ API functions
+*/
+__probe int ResetTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  U32 iAPBank;
+  U32 iAP;
+  U32 v;
+  //
+  // Perform standard chip acquisition sequence which also includes a reset
+  //
+  _PerformChipAcquisitionSeq();   // Requires __probe attribute for caller
+  //
+  // Make sure that the CPU is halted. See (1)
+  // No rush here, as chip acquisition sequence makes sure that user application is not started
+  //
+  // DAP has already been powered-up etc. by _PerformChipAcquisitionSeq(), so no need to configure CoreSight here again
+  //
+  JLINK_SYS_Sleep(5);   // Give BTL some time to enter WFI
+  iAPBank = 0;
+  iAP = 1;    // AHB-AP for M0
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACCESS_DP, (iAP << 24) | (iAPBank << 4));
+  //
+  // Reset of PSoC6 also resets debug logic, so we need to restore some registers
+  // Luckily, we need to touch most of these registers anyhow, to halt the core
+  //
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACCESS_AP, _DAP_ACC_32BIT_NO_AUTO_INC);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DHCSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0xA05F0003);  // Key + C_DEBUGEN + C_HALT
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DEMCR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, (1 << 24));   // TRCENA
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACCESS_DP, &v);          // Make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
+  JLINK_SYS_Sleep(2);  // Give CPU some time to handle halt request (should not be necessary, but as user-initiated reset is not really a time critical operation that happens rarely, it does not hurt)
+
+  // Get address at reset vector & set PC
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR + 4);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x0001000F);  
+
+  // Get address at vector table & set SP
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _VECTOR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010011);  
+
+  //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00000010);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA,  _ACCESS_AP, &v);  
+  v |= 0x01000000;
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRDR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, v);  
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, _DCRSR_ADDR);
+  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, 0x00010010);  
+  
+  return 0;
+}
+
+/*********************************************************************
+*
+*       InitTarget()
+*
+*  Function description
+*    If present, called right before performing generic connect sequence.
+*    Usually used for targets which need a special connect sequence.
+*    E.g.: TI devices with ICEPick TAP on them where core TAP needs to be enabled via specific ICEPick sequences first
+*
+*  Return value
+*    >= 0:  O.K.
+*     < 0:  Error
+*
+*  Notes
+*    (1) Must not use high-level API functions like JLINK_MEM_ etc.
+*    (2) For target interface JTAG, this device has to setup the JTAG chain + JTAG TAP Ids.
+*    (3) This function is called before J-Link performed any communication with the device
+*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+*/
+__probe int InitTarget(void) {   // __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side, so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
+  _PerformChipAcquisitionSeq();  // Requires __probe attribute for caller
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxx_CM4.JLinkScript

@@ -0,0 +1,32 @@
+int ConfigTargetSettings(void) {
+  //
+  // Mark a specific memory region as memory type illegal
+  // in order to make sure that the software is not allowed to access these regions
+  // 
+  // Note: This does not work for J-Flash tool
+  //
+
+  // Exclude SFLASH regions
+  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
+  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
+  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
+  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
+
+  // Exclude Cy Metadata
+  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
+  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
+  
+  // Exclude eFuse
+  JLINK_ExecCommand("map region 0x90700000-0x907FFFFF XI");
+}
+
+void InitTarget(void) {
+  Report("********************************************");
+  Report("InitTarget for PSoC6 Cortex-M4 script");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
+  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
+  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
+  CORESIGHT_IndexAHBAPToUse = 2;
+  CPU=CORTEX_M4;
+  Report("********************************************");
+}

Devices/Cypress/PSoC6/Readme_Cypress.txt

@@ -0,0 +1,2 @@
+The Cypress devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Cypress only.
+For support, please contact: cytechsupport@cypress.com

Devices/Infineon/Readme.txt

@@ -0,0 +1,2 @@
+Infineon Technologies TLE98xy series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Infineon Technologies only.
+For support, please contact: kay.claussen@infineon.com

Devices/NXP/LPC5411x/LPC5411x_M0.JLinkScript

@@ -0,0 +1,32 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : LPC5411x_M0.JLinkScript
+Purpose : Script file for NXP LPC5411 series that has a Cortex-M4 and Cortex-M0+ in it.
+          This script connects to the M0+
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  //
+  // Set AP register layout
+  // Usually only needed if core is not accessible via the first AHB-AP / APB-AP found
+  //
+  JLINK_CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);              // AHB-AP (Cortex-M4)
+  JLINK_CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);              // AHB-AP (Cortex-M0+)
+  CORESIGHT_IndexAHBAPToUse = 1;
+}

Devices/NXP/iMX6SX/iMX6SX_CortexA9.JLinkScript

@@ -0,0 +1,53 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*        Solutions for real time microcontroller applications        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                                                                    *
+* Internet: www.segger.com Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+----------------------------------------------------------------------
+Purpose : 
+---------------------------END-OF-HEADER------------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  // In case cores 1-3 are reset, we do nothing, 
+  //  as we would lose connection to these cores, when resetting the device
+  //  as a reset disables the clock to them.
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int WordAcc;
+  int v;
+  
+  JTAG_Reset();                                                                 // Perform TAP reset and J-Link JTAG auto-detection
+  if (JTAG_TotalIRLen == 5) {                                                   // Freescale System JTAG Controller (SJC) in MOD 1 detected?
+    JTAG_TRSTPin = 0;                                                           // Set JTAG_MOD to 0 in order to set Freescale System JTAG Controller (SJC) MOD to 0 ("Daisy chain ALL")
+    SYS_Sleep(10);                                                              // Give pin some time to get low
+  }
+  Report("******************************************************");
+  Report("J-Link script: iMX6 SoloX Cortex-A9 core J-Link script");
+  Report("******************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=4;DRPre=1;IRPost=9;DRPost=2;IRLenDevice=4");
+  CPU = CORTEX_A9;                                                              // Pre-select that we have a Cortex-A9 connected
+  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  CORESIGHT_CoreBaseAddr = 0x02150000;
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_IndexAPBAPToUse = 1;
+  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
+  JTAG_SetDeviceId(1, 0x4BA00477);  // 4-bits IRLen
+  JTAG_SetDeviceId(2, 0x00000001);  // 5-bits IRLen
+  JTAG_SetDeviceId(3, 0x0891C01D);  // 4-bits IRLen
+}

Devices/NXP/iMX6SX/iMX6SX_CortexM4.JLinkScript

@@ -0,0 +1,47 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*        Solutions for real time microcontroller applications        *
+**********************************************************************
+*                                                                    *
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                                                                    *
+* Internet: www.segger.com Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+----------------------------------------------------------------------
+Purpose : 
+---------------------------END-OF-HEADER------------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  // In case cores 1-3 are reset, we do nothing, 
+  //  as we would lose connection to these cores, when resetting the device
+  //  as a reset disables the clock to them.
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  int WordAcc;
+  int v;
+
+  Report("******************************************************");
+  Report("J-Link script: iMX6 SoloX Cortex-M4 core J-Link script");
+  Report("******************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=13;DRPost=3;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-A5 connected
+  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_IndexAHBAPToUse = 0;
+  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
+  JTAG_SetDeviceId(1, 0x4BA00477);  // 4-bits IRLen
+  JTAG_SetDeviceId(2, 0x00000001);  // 5-bits IRLen
+  JTAG_SetDeviceId(3, 0x0891C01D);  // 4-bits IRLen
+}

Devices/NXP/iMX6UL/NXP_iMX6ULL.JLinkScript

@@ -0,0 +1,35 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : NXP_iMX6ULL.JLinkScript
+Purpose : Script file for iMX6 ULL series devices
+Literature:
+  [1]  J-Link User Guide
+
+Additional information:
+  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
+*/
+
+/*********************************************************************
+*
+*       ConfigTargetSettings
+*/
+int ConfigTargetSettings(void) {
+  //
+  // The i.MX6ULL series does not like scanning the AP map because accessing
+  // a non-existing AP causes the whole DAP to crash and hang until power cycle
+  // Therefore, we manually setup the AP map so the J-Link SW skips the scanning
+  //
+  Report("J-Link script: Setting up AP map");
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_IndexAPBAPToUse = 1;
+  return 0;
+}
+
+/*************************** end of file ****************************/

Devices/NXP/iMX7D/NXP_iMX7D_Connect_CortexA7_0.JLinkScript

@@ -0,0 +1,61 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+/*********************************************************************
+*
+*       Constants (similar to defines)
+*
+**********************************************************************
+*/
+__constant U32 _SRC_M4RCR_ADDR              = 0x3039000C;
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  // In case cores 1-3 are reset, we do nothing, 
+  //  as we would lose connection to these cores, when resetting the device
+  //  as a reset disables the clock to them.
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void) {
+  U32 v;
+  //
+  // Enable Cortex-A7 Core1 by setting the A7_CORE1_ENABLE bit in the SRC_A7RCR1 register
+  //
+  v = JLINK_MEM_ReadU32(0x30390008);   // A7 Reset Control Register 
+  v |= (1 << 1);                       // Set A7_CORE1_ENABLE
+  JLINK_MEM_WriteU32(0x30390008, v);
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  Report("***************************************************");
+  Report("J-Link script: iMX7D Cortex-A7_0 core J-Link script");
+  Report("***************************************************");
+  CPU = CORTEX_A7;                                                              // Pre-select that we have a Cortex-A7 connected
+  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);
+  CORESIGHT_IndexAPBAPToUse = 1;  
+}

Devices/NXP/iMX7D/NXP_iMX7D_Connect_CortexA7_1.JLinkScript

@@ -0,0 +1,38 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  // In case cores 1-3 are reset, we do nothing, 
+  //  as we would lose connection to these cores, when resetting the device
+  //  as a reset disables the clock to them.
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  Report("****************************************************");
+  Report("J-Link script: iMX7D Cortex-A7_1 core J-Link script");
+  Report("****************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_A7;                                                              // Pre-select that we have a Cortex-A7 connected
+  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  CORESIGHT_CoreBaseAddr = 0x30072000;
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);
+  CORESIGHT_IndexAPBAPToUse = 1;
+}

Devices/NXP/iMX7D/NXP_iMX7D_Connect_CortexM4.JLinkScript

@@ -0,0 +1,38 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  // In case cores 1-3 are reset, we do nothing, 
+  //  as we would lose connection to these cores, when resetting the device
+  //  as a reset disables the clock to them.
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) { 
+  Report("*************************************************");
+  Report("J-Link script: iMX7D Cortex-M4 core J-Link script");
+  Report("*************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_AHB_AP);
+  CORESIGHT_IndexAHBAPToUse = 4;
+}

Devices/NXP/iMX7ULP/NXP_iMX7ULP_CortexA7.JLinkScript

@@ -0,0 +1,45 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+  JLINK_TARGET_Halt(); // Make sure that the CPU is halted when reset is called
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) {
+  Report("***************************************************");
+  Report("J-Link script: iMX7ULP Cortex-A7 core J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_A7;                                                              // Pre-select that we have a Cortex-A7 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  CORESIGHT_CoreBaseAddr = 0x80030000;
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(5, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_IndexAPBAPToUse = 1;  
+  JTAG_SetDeviceId(0, 0x6BA00477);  // 4-bits IRLen
+}

Devices/NXP/iMX7ULP/NXP_iMX7ULP_CortexM4.JLinkScript

@@ -0,0 +1,56 @@
+/*********************************************************************
+*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
+*                        The Embedded Experts                        *
+*                           www.segger.com                           *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+*/
+
+/*********************************************************************
+*
+*       ResetTarget
+*/
+void ResetTarget(void) {
+  //
+  // This device requires a special reset as default reset does not work for this device.
+  // TBD
+  //
+  JLINK_TARGET_Halt(); // Make sure that the CPU is halted when reset is called
+}
+
+/*********************************************************************
+*
+*       InitTarget
+*/
+void InitTarget(void) { 
+  Report("***************************************************");
+  Report("J-Link script: iMX7ULP Cortex-M4 core J-Link script");
+  Report("***************************************************");
+  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
+  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-M4 connected
+  JTAG_AllowTAPReset = 0;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
+  //
+  // Manually configure which APs are present on the CoreSight device
+  //
+  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
+  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
+  CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);
+  CORESIGHT_AddAP(4, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_AddAP(5, CORESIGHT_CUSTOM_AP);
+  CORESIGHT_IndexAHBAPToUse = 3;
+  JTAG_SetDeviceId(0, 0x6BA00477);  // 4-bits IRLen
+}
+
+/*********************************************************************
+*
+*       SetupTarget
+*/
+void SetupTarget(void) {
+  //
+  //  Map alias area of M4 core for flash to 0x04000000 instead of 0xC0000000 as in certain circumstances the 0xC0000000 is not initialized
+  //
+  JLINK_ExecCommand("map add 0xC0000000-0xC7FFFFFF A FLASH 0x04000000 0x07FFFFFF");
+}

Devices/ONSemiconductor/RSL10/ONSemiconductor_RSL10.JLinkScript

@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------------
+ * Copyright (c) 2017 Semiconductor Components Industries, LLC (d/b/a
+ * ON Semiconductor), All Rights Reserved
+ *
+ * This code is the property of ON Semiconductor and may not be redistributed
+ * in any form without prior written permission from ON Semiconductor.
+ * The terms of use and warranty for this code are covered by contractual
+ * agreements between ON Semiconductor and the licensee.
+ *
+ * This is Reusable Code.
+ *
+ * ----------------------------------------------------------------------------
+ * ONSemiconductor_RSL10.JLinkScript
+ * - RSL10 JLink Script
+ *
+ *   Provides a custom reset function for RSL10
+ * ----------------------------------------------------------------------------
+ * $Revision: 1.7 $
+ * $Date: 2017/06/19 16:15:11 $
+ * ------------------------------------------------------------------------- */
+
+/* Registers */
+__constant U32 FP_CTRL_ADDR     = 0xE0002000;
+__constant U32 FP_COMP0_ADDR    = 0xE0002008;
+__constant U32 AIRCR_ADDR       = 0xE000ED0C;
+__constant U32 NVR1_ENTRY_ADDR  = 0x00800000;
+__constant U32 FLASH_ENTRY_ADDR = 0x00100004;
+
+/* Constants */
+__constant U32 FP_CTRL_EN        = 0x00000003;           /* Enable flash patch unit */ 
+__constant U32 FCOMP_EN_BP_LOWER = (1 << 30) | (1 << 0); /* Bitband to set BP on lower halfword of addr and enable BP */
+
+/* Global variables */
+U32 fp_ctrl_old;  /* Used to restore previous fp_ctrl value */
+U32 fp_comp0_old; /* Used to restore previous fp_comp0 value */
+U32 entry_point;  /* Stores application's entry point and is set by ResetCatchSet */
+
+
+/*******************************************************************
+ * Set a breakpoint when a valid application's entry point is found.
+ * If NVR1 has no valid entry point, read it from Flash.
+ *******************************************************************/
+void ResetCatchSet()
+{  
+    /* Get user's application entry point from NVR1 */
+    entry_point = JLINK_MEM_ReadU32(NVR1_ENTRY_ADDR);
+    if (entry_point == 0xFFFFFFFF) /* If entry point is not set in NVR1 */
+    {
+        entry_point = JLINK_MEM_ReadU32(FLASH_ENTRY_ADDR); /* Get entry point from FLASH */
+    }
+
+    /* Set a hardware breakpoint on application's entry point (set flash patch unit manually)
+     * If reset address points to 0xFFFFFFFF, the device is empty and CPU will be halted after 100ms. */
+    fp_ctrl_old  = JLINK_MEM_ReadU32(FP_CTRL_ADDR);   /* Remember flash patch unit settings */
+    fp_comp0_old = JLINK_MEM_ReadU32(FP_COMP0_ADDR);  /* Remember settings for comparator 0 */                             
+    if (entry_point != 0xFFFFFFFF) 
+    {
+        JLINK_MEM_WriteU32(FP_CTRL_ADDR, FP_CTRL_EN);                       /* Enable flash patch unit */                                 
+        JLINK_MEM_WriteU32(FP_COMP0_ADDR, entry_point | FCOMP_EN_BP_LOWER); /* Set BP on lower halfword of addr. Enable BP */
+    }
+}
+
+/*******************************************************************
+ * Restore previous FPB settings for the flash patch control 
+ * and comparator0 registers
+ *******************************************************************/
+void ResetCatchClear()
+{
+    JLINK_MEM_WriteU32(FP_COMP0_ADDR, fp_comp0_old);
+    JLINK_MEM_WriteU32(FP_CTRL_ADDR, fp_ctrl_old);
+}
+
+/*******************************************************************
+ * Execute a software reset via AIRCR.
+ * If aircr_value=0x05FA0001, execute core-only reset (VECTRESET)
+ * If aircr_value=0x05FA0004, execute system-wide reset (SYSRESETREQ)
+ * After reset, the CPU is expected to halt at the breakpoint set by 
+ * ResetCatchSet. If no program is loaded or a timeout occurs, 
+ * CPU is manually halted.
+ *******************************************************************/
+int SoftwareReset(U32 aircr_value) 
+{
+    int end_time, is_halted, timeout;
+
+    /* Request reset via AIRCR */
+    JLINK_MEM_WriteU32(AIRCR_ADDR, aircr_value);
+    SYS_Sleep(100);  /* Boot loader runs after reset */
+    
+    if (entry_point == 0xFFFFFFFF) 
+    {
+        Report("No application found. Manually halting CPU.");
+        JLINK_TARGET_Halt();
+    }
+    else
+    {
+        /* Wait until CPU is halted or timeout occurs */
+        end_time = JLINK_GetTime() + 1000;
+        do {
+            is_halted = JLINK_TARGET_IsHalted();
+            timeout   = end_time < JLINK_GetTime()
+        } while ( is_halted==0 && timeout==0 );
+
+        if(is_halted == -1)
+        {
+            Report("Error while checking CPU state after reset.");
+            return -1;
+        }
+
+        if (timeout)
+        {
+            Report("Timeout while waiting for CPU to halt after reset. Manually halting CPU.");
+            JLINK_TARGET_Halt();
+        }
+    }
+    return 0;
+}
+
+/*******************************************************************
+ * Override default J-Link reset strategy.  
+ * CPU is halted by a breakpoint at application's entry point.
+ * When no valid entry point is found, CPU is manually halted after reset.
+ * Support reset types 0 and 1.
+ *******************************************************************/
+int ResetTarget(void) 
+{
+    int r,reset_type;
+
+    ResetCatchSet(); /* Set a breakpoint at application's entry point */
+
+    reset_type = MAIN_ResetType;
+    Report1("Executing RSL10 reset type: ",reset_type);
+    if(MAIN_ResetType == 0)
+    {
+        r = SoftwareReset(0x05FA0004); /* Software System-wide reset (SYSRESETREQ via AIRCR) */
+    }
+    else if(MAIN_ResetType == 1)
+    {
+        r = SoftwareReset(0x05FA0001); /* Processor reset (VECTRESET via AIRCR) */
+    }
+    else 
+    {
+        Report1("Unsupported RSL10 Reset Type: ",reset_type);
+        r = -1;
+    }
+
+    ResetCatchClear(); /* Restore previous settings of FPB unit */
+
+    return r;
+}

Devices/ONSemiconductor/RSL10/Readme_ONSemiconductor.txt

@@ -0,0 +1,5 @@
+The ON Semiconductor devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via ON Semiconductor only.
+For support, please contact: dsp.support@onsemi.com
+On the ON Semiconductor website, other documents, such as the datasheet, etc. can be found 
+
+