Merge pull request #7 from jianbojason/windows

upgrade jlink to V780a

Devices/AnalogDevices/Readme.txt

@@ -1,4 +0,0 @@
-The Analog Devices ADSP-CM41x series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Analog Devices only.
-For support, please contact: processor.tools.support@analog.com
-
-

Devices/Broadcom/BCM43907.JLinkScript

@@ -1,118 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : BCM43907.JLinkScript
-Purpose : Handle reset for Broadcom BCM43907 series
-Literature:
-  [1]  J-Link User Guide
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*
-*       Constants (similar to defines)
-*
-**********************************************************************
-*/
-
-//
-// User-specified constants to be used by PCode
-//
-__constant U32 _DBG_REG_VCR         = 0x007;      // Vector Catch Register
-__constant U32 _DBG_REG_PRCR        = 0x0C4;      // Device Power-down and Reset Control Register
-__constant U32 _DBG_REG_PRSR        = 0x0C5;      // Device Power-down and Reset Status Register
-__constant U32 _DBG_REG_LOCKACCESS  = 0x3EC;
-__constant U32 _DBG_REG_LOCKSTATUS  = 0x3ED;
-__constant U32 _ACTIVATION_KEY      = 0xC5ACCE55;
-__constant U32 _DBG_REG_DSCR        = 0x022;      // Debug Status and Control Register
-__constant U32 _DBG_REG_DRCR        = 0x024;      // Debug Run Control Register
-
-/*********************************************************************
-*
-*       ResetTarget
-*/
-void ResetTarget(void) {
-  int Ctrl;
-  int v;
-  int BaseAddr;
-
-  BaseAddr = 0x80001000;
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (0 << 24) | (0 << 4));  // Select AP[0], bank 0
-  Ctrl =  0
-       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
-       | (0 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
-       | (1 << 31)   // Enable software access to the Debug APB bus.
-       ;
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);  
-  //
-  // Prepare CPU to be halted immediately after reset (vector catch)
-  //
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_VCR << 2));          // DBG_REG_VCR
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);                                // Set reset vector catch
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRCR << 2));          // DBG_REG_PRCR
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);                                // Make sure that device is not held in reset
-  //
-  // Reset CPU by toggling reset pin
-  // Wait some time after reset release to give pin some time to get HIGH
-  // and to give ROM BTL of SAMA5 some time to finish its work and enable debug access
-  //
-  JLINK_JTAG_ResetPin = 0;
-  JLINK_SYS_Sleep(100);
-  JLINK_JTAG_ResetPin = 1;
-  JLINK_SYS_Sleep(100);
-  //
-  // Check if CPU is halted. If not, halt it.
-  // Select & setup APB-AP
-  //
-  Report("J-Link script: Reset");
-  JTAG_Write(0x1F, 0, 6);                                                            // Perform TAP reset
-  v = (1 << 1) | (1 << 30) | (1 << 28);                                              // Request power-up on debug and system port, Make sure that sticky overrun bit gets cleared
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, 0, v);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, (0 << 24) | (0 << 4));  // Select AP[0], bank 0
-  Ctrl =  0
-       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
-       | (0 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
-       | (1 << 31)   // Enable software access to the Debug APB bus.
-       ;
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, 1, Ctrl);
-  //
-  // Init debug logic
-  //
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_LOCKACCESS << 2));
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, _ACTIVATION_KEY);                        // Unlock access to the debug registers
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_LOCKSTATUS << 2));
-  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRCR << 2));
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0x1);                                    // Disable power-down mode
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_PRSR << 2));
-  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
-  //
-  // Read DSCR to check if CPU is halted and halt it, if necessary
-  //
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DSCR << 2));
-  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
-  v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);
-  if ((v & 1) == 0) {
-    JLINK_SYS_Report("J-Link script: Core did not halt after reset. Halting core...");
-    v |= (1 << 14);
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DSCR << 2));   // Enable debug halt mode by writing the DSCR
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, v);
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_DRCR << 2));   // Write DRCR to halt CPU
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 1);
-    v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA);                                     // Write to AP may be delayed until next read/write, so perform a dummy read
-  }
-  //
-  // Clear vector catch
-  //
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, 1, BaseAddr + (_DBG_REG_VCR << 2));
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, 1, 0);
-  Report("J-Link script: Done");
-}
-

Devices/ClouderSemi/CR600/CR600.JLinkScript

@@ -1,58 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : ClouderSemi_CR600.JLinkScript
-Purpose : Contains device specific handling for ClouderSemi's CR600 series
-Literature:
-  [1]  J-Link User Guide
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-*       ResetTarget
-*/
-int AfterResetTarget(void) {
-  //
-  // The flash of the CR600 (Cortex-M0) is located at address 0x20000000. This makes problems
-  // for the IDE / debug probe as a default debug session start would fail as no breakpoint can
-  // be set at the beginning of the application (flash) for two reasons:
-  //   1) HW breakpoint --> Does not work due to the limitation of the core (does not allow HW BPs at addresses >= 0x20000000)
-  //   2) Software breakpoint --> Does not work as it is flash memory
-  //
-  // Respecting those limitations, the only way to perform a correct debug session start (CPU
-  // is halted at the application start (using a breakpoint) is to use flash breakpoints. Unfortunately,
-  // the flash cannot be access after reset as it is enabled when the bootloader is executed. As there
-  // is no option to halt the CPU *after* bootloader execution and *before* any target application code has been executed,
-  // we perform some parts of the bootloader manually which allow us to program the flash and therefore allow us to set a
-  // flash breakpoint at the application start.
-  //
-  // The sequence below comes from ClouderSemi.
-  // SEGGER does neither provide any support for it nor guarantees the correct functionality.
-  //
-  JLINK_SYS_Report("Executing AfterResetTarget()");  
-  JLINK_MEM_WriteU32(0x4009B050, 0x3C);
-  JLINK_MEM_WriteU32(0x40085000, 0x10);
-  JLINK_MEM_WriteU32(0x40085008, 0x8);
-  JLINK_MEM_WriteU32(0x4008500C, 0x3);
-  JLINK_MEM_WriteU32(0x40085010, 0x18);
-  JLINK_MEM_WriteU32(0x4008502C, 0x0);
-  JLINK_MEM_WriteU32(0x40085004, 0x3012);  
-  return 0;
-}
-
-/*************************** end of file ****************************/

Devices/ClouderSemi/CR600/Readme.txt

@@ -1,2 +0,0 @@
-The ClouderSemi CR600 series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via ClouderSemi only.
-For support, please contact: chang.nan@cloudersemi.com

Devices/Cypress/PSoC6/CY8C6xx7_CM0p.JLinkScript

@@ -1,30 +0,0 @@
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("********************************************");
-  Report("InitTarget for PSoC6 Cortex-M0+ script");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 1;
-  CPU=CORTEX_M0;
-  JLINK_ExecCommand("SetETBIsPresent = 1");
-  Report("********************************************");
-}

Devices/Cypress/PSoC6/CY8C6xx7_CM0p_tm.JLinkScript

@@ -1,1051 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : CY8C6xx7_CM0p_tm.JLinkScript
-Purpose : J-Link script file for Cypress PSoC6A-BLE2 devices (CY8C6xx6 and CY8C6xx7)
-Literature:
-  [1] J-Link User Guide
-  [2] PSoC® 6 MCU Programming Specifications (Document Number: 002-15554 http://www.cypress.com/file/385671/download)
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*       Constants (similar to defines) 
-*********************************************************************/
-
-/* --- Flags --- */
-__constant U8 _DO_ACQUIRE_TEST_MODE         = 1; // Perform or skip Test Mode acquisition sequence
-__constant U8 _DO_ACQUIRE_ALTERNATE         = 1; // Perform or skip Alternate acquisition sequence
-
-/* --- Misc. --- */
-__constant int _STATUS_OK                   = 0;  // Function return status: O.K.
-__constant int _STATUS_ERR                  = -1; // Function return status: Error
-__constant U32 _TIMEOUT_HANDSHAKE           = 3000;
-__constant U32 _TIMEOUT_HALT_CPU            = 300;
-__constant U32 _TIMEOUT_SLEEP_LISTEN_WINDOW = 200;
-__constant U32 _TEST_MODE_SWD_SPEED         = 4000;
-
-/* PSoC® 6 MCU definitions */
-__constant U32 _AP_SYS                      = 0; // AP[0]  SYS-AP (used for chip acquisition sequence)
-__constant U32 _AP_CM0                      = 1; // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-__constant U32 _AP_CM4                      = 2; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _AP_MYCORE                   = 1; // AP[1]  CM0+ Core is used as the default for this script
-__constant U32 _DP_IDCODE_MSK               = 0xFFF00FFF; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _DP_IDCODE_VAL               = 0x6BA00477; // AP[2]  0x6BA02477 for SWD or 0x6BA00477 for JTAG
-__constant U32 _CPUSS_CM0_VTBASE_ADDR       = 0x402102B0; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
-__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK    = 0xFFFF0000; // Set by boot code if flash is empty or secure application
-__constant U32 _SRSS_TST_MODE_ADDR          = 0x40260100; // SRSS_TST_MODE: Test Mode Control Register
-__constant U32 _SRSS_TST_MODE_TEST_MODE     = (1 << 31);  // SRSS_TST_MODE.TEST_MODE (bit[31], 0x80000000): 1 - Indicates the chip is in test mode. 0 - Normal operation mode
-__constant U32 _MEM_BASE_ROM                = 0x00000000; // Base address of System ROM
-__constant U32 _MEM_SIZE_ROM                = 0x00020000; // Size of System ROM
-__constant U32 _MEM_BASE_SFLASH             = 0x16000000; // Base address of supervisory flash
-__constant U32 _MEM_SIZE_SFLASH             = 0x00008000; // Size of supervisory flash
-__constant U32 _SRAM_ERROR_ADDR             = 0x080002FC; // Address in SRAM for error code
-__constant U32 _SRAM_LOOP_ADDR              = 0x08000300; // Address in SRAM for infinite loop
-__constant U32 _SRAM_TOP_ADDR               = 0x0800FFF0; // Top of SRAM address for SP set by acquisition sequence. Use minimum SRAM size devices (65 KB)
-
-/* --- AP/DP registers --- */
-__constant U32 _ACC_DP                      = 0; // APnDP for DP access
-__constant U32 _ACC_AP                      = 1; // APnDP for AP access
-__constant U32 _AP_ABORT_ORUNERRCLR         = (1 << 4);   // AP->ABORT.ORUNERRCLR (bit[4], 0x00000010): Clears CTRL/STAT.STICKYORUN
-__constant U32 _AP_ABORT_WDERRCLR           = (1 << 3);   // AP->ABORT.WDERRCLR   (bit[3], 0x00000008): Clears CTRL/STAT.WDATAERR
-__constant U32 _AP_ABORT_STKERRCLR          = (1 << 2);   // AP->ABORT.STKERRCLR  (bit[2], 0x00000004): Clears CTRL/STAT.STICKYERR
-__constant U32 _AP_ABORT_STKCMPCLR          = (1 << 1);   // AP->ABORT.STKCMPCLR  (bit[1], 0x00000002): Clears CTRL/STAT.STICKYERR
-                                                          //                      (     |= 0x0000001E)
-__constant U32 _AP_SELECT_APSEL_RSH         = 24;         // AP->SELECT.APSEL (bits[31:24], 0xFF000000): Selects an AP
-__constant U32 _DP_CTRL_STAT_CSYSPWRUPREQ   = (1 << 30);  // DP->CTRL/STAT.CSYSPWRUPREQ (bit[30], 0x40000000): System powerup request
-__constant U32 _DP_CTRL_STAT_CDBGPRWUPREQ   = (1 << 28);  // DP->CTRL/STAT.CDBGPRWUPREQ (bit[28], 0x10000000): Debug powerup request
-__constant U32 _DP_CTRL_STAT_CDBGRSTREQ     = (1 << 26);  // DP->CTRL/STAT.CDBGRSTREQ   (bit[26], 0x04000000): Debug reset request
-__constant U32 _DP_CTRL_STAT_STICKYERR      = (1 << 5);   // DP->CTRL/STAT.STICKYERR    ( bit[5], 0x00000020): Error in AP transaction
-__constant U32 _DP_CTRL_STAT_STICKYCMP      = (1 << 4);   // DP->CTRL/STAT.STICKYCMP    ( bit[4], 0x00000010): Match on a pushed operations
-__constant U32 _DP_CTRL_STAT_STICKYORUN     = (1 << 1);   // DP->CTRL/STAT.STICKYORUN   ( bit[1], 0x00000002): Overrun detection
-                                                          //                                   |= 0x50000032
-__constant U32 _DP_CSW_PROT_VAL             = (0x23 << 24); // DP->CSW.Prot (bits[30:24], 0x23000000): Bus access protection control
-                                                            // Set to 0x23, otherwise no access to CPU registers via M4 AP
-__constant U32 _DP_CSW_SIZE_WORD            = (2 << 0);     // DP->CSW.Size (  bits[2:0], 0x00000002): Size of access <- Word (32-bits)
-                                                            //                         |= 0x23000002
-/* --- ARMv6-M & ARMv7-M --- */
-__constant U32 _LOOP_CODE                   = 0xE7FEE7FE; // Endless loop
-__constant U32 _BP_CTRL_ADDR                = 0xE0002000; // BP_CTRL: Breakpoint Control register in ARMv6-M. In ARMv7-M, it is FP_CTRL: FlashPatch Control Register.
-__constant U32 _BP_CTRL_KEY                 = (1 << 1);   // BP_CTRL.KEY    (bit[1], 0x00000002): Enables write to the register
-__constant U32 _BP_CTRL_ENABLE              = (1 << 0);   // BP_CTRL.ENABLE (bit[0], 0x00000001): Enables the BPU
-__constant U32 _BP_COMP0_ADDR               = 0xE0002008; // BP_COMP0: Breakpoint Comparator registers
-__constant U32 _BP_COMP_BPMATCH             = (3 << 30);  // BP_COMP.BP_MATCH (bits[31:30], 0xC0000000): Defines the behavior when the COMP address is matched
-__constant U32 _BP_COMP_COMP_MSK            = 0x1FFFFFFC; // BP_COMP.COMP     ( bits[28:2], 0x07FFFFFF): Stores bits [28:2] of the comparison address
-__constant U32 _BP_COMP_ENABLE              = (1 << 0);   // BP_COMP.ENABLE   (     bit[0], 0x00000001): Enables the comparator
-__constant U32 _AIRCR_ADDR                  = 0xE000ED0C;     // AIRCR: Application Interrupt and Reset Control Register
-__constant U32 _AIRCR_VECTKEY_VAL           = (0x05FA << 16); // AIRCR.VECTKEY       (bits[31:16], 0x05FA0000): Vector Key. The value 0x05FA must be written to this register
-__constant U32 _AIRCR_SYSRESETREQ           = (1 << 2);       // AIRCR.SYSRESETREQ   (     bit[2], 0x00000004): System Reset Request
-__constant U32 _DHCSR_ADDR                  = 0xE000EDF0;     // DHCSR: Debug Halting Control and Status Register
-__constant U32 _DHCSR_DBGKEY_VAL            = (0xA05F << 16); // DHCSR.DBGKEY    (bits[31:16], 0xA05F0000): Must write 0xA05F to DBGKEY to enable write accesses to bits[15:0]
-__constant U32 _DHCSR_S_SLEEP               = (1 << 18);      // DHCSR.S_SLEEP   (    bit[18], 0x00040000): Indicates whether the processor is sleeping
-__constant U32 _DHCSR_S_HALT                = (1 << 17);      // DHCSR.S_HALT    (    bit[17], 0x00020000): Indicates whether the processor is in Debug state
-__constant U32 _DHCSR_C_HALT                = (1 << 1);       // DHCSR.C_HALT    (     bit[1], 0x00000002): Processor halt bit
-__constant U32 _DHCSR_C_DEBUGEN             = (1 << 0);       // DHCSR.C_DEBUGEN (     bit[0], 0x00000001): Halting debug enable bit
-                                                              //                 (DBGKEY|C_HALT|C_DEBUGEN = 0xA05F0003)
-__constant U32 _DCRSR_ADDR                  = 0xE000EDF4; // DCRSR: Debug Core Register Selector Register
-__constant U32 _DCRSR_REGWnR                = (1 << 16);  // DCRSR.REGWnR (  bit[16], 0x00010000): Specifies the access type for the transfer ('0' - Read, '1' - Write)
-__constant U32 _DCRSR_REGSEL_MSK            = 0x0000007F; // DCRSR.REGSEL (bits[6:0], 0x0000007F): Specifies the ARM core register, special-purpose register, or Floating-point extension register
-__constant U32 _xPSR_T                      = (1 << 24);  // xPSR.T (bit[24], 0x01000000): Thumb bit
-__constant U32 _REGSEL_xPSR                 = 0x10;       // xPSR
-__constant U32 _REGSEL_MSP                  = 0x11;       // Main stack pointer, MSP
-__constant U32 _REGSEL_PC                   = 0x0F;       // PC / DebugReturnAddress
-__constant U32 _DCRDR_ADDR                  = 0xE000EDF8; // DCRDR: Debug Core Register Data Register
-__constant U32 _DEMCR_ADDR                  = 0xE000EDFC; // DEMCR: Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_TRCENA                = (1 << 24);  // DEMCR.TRCENA (bit[24], 0x01000000): Global enable for all DWT and ITM features
-
-
-/*********************************************************************
-*       Static data
-*********************************************************************/
-
-// Standard ARM command to switch SWJ-DP from JTAG to SWD operations:
-const U8 _aData_JTAGtoSWD[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The JTAG interface detects only the 16-bit JTAG-to-SWD sequence starting from the test-logic-reset state.
-  0x9E, 0xE7,                                    // Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS: 0b0111 1001 1110 0111, most significant bit (MSb) first.
-                                                 // This can be represented as 0x79E7, transmitted MSB first or 0xE79E, transmitted least significant bit (LSb) first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in SWD operation
-                                                 // before sending the select sequence, the SWD interface enters line reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Standard ARM command to switch SWJ-DP from SWD to JTAG operations
-const U8 _aData_SWDtoJTAG[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The SWD interface detects the 16-bit SWD-to-JTAG sequence only when it is in reset state.
-  0x3C, 0xE7,                                    // Send the 16-bit SWD-to-JTAG select sequence on SWDIOTMS: 0b0011 1100 1110 0111, MSb first.
-                                                 // This can be represented as 0x3CE7, transmitted MSb first or 0xE73C, transmitted LSb first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least five SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in JTAG
-                                                 // operation before sending the select sequence, the JTAG TAP enters the test-logic-reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Direction buffer
-const U8 _aDir_SWJDPSwitch[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF
-};
-
-// Buffer for receiving data from target. Needs to be big enough to hold data for above sequences
-U8 _aDataOut[18];
-
-/*********************************************************************
-*       Local functions
-*********************************************************************/
-
-/*********************************************************************
-*  Checks function result
-*
-*  Return value
-*    true   O.K.
-*    false  Error
-*/
-int _CheckStatus(int status) {
-  if (status >= _STATUS_OK) {
-    return _STATUS_OK;
-  } else {
-    // Push error code to SWD that is it easier to debug the issues
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRAM_ERROR_ADDR);
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0xDEADBEEF);   	  
-    return _STATUS_ERR;
-  }
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_ReadU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadMem(U32 address, U32* value) { 
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value);  // AP.DRW -> value
-  }
-  
-  return status; 
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_WriteU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteMem(U32 address, U32 value) { 
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value); // AP.DRW <- value
-  }
-  
-  return status; 
-}
-
-/*********************************************************************
-*  Polls for the expected bit-field value in given register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error/Timeout
-*/
-int _PollMem(U32 regAddr, U32 fieldMsk, U32 rsh, U32 expectedValue, U32 timeout, U32 sleepBetweenPolling) {
-  int status;  
-  int t;
-  int tDelta;
-  U32 v;
-  tDelta = -1;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, regAddr); // AP.ADDR <- regAddr
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _STATUS_ERR;
-    t = JLINK_GetTime();
-    do {
-      // Sleep some time between polling: let CPU do its job and avoid too much garbage on SWD
-      if ((sleepBetweenPolling > 0) && (tDelta >= 0 /* not first iteration*/)) {
-        JLINK_SYS_Sleep(sleepBetweenPolling);
-      }
-      v = 0;
-      status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-      break;
-      }
-      if (((v & fieldMsk) >> rsh) == expectedValue) {
-        status = _STATUS_OK;
-        break;
-      }	  
-      tDelta = JLINK_GetTime() - t;
-    } while (tDelta < timeout);
-  }
-  
-  return _CheckStatus(status); 
-}
-
-/*********************************************************************
-*  Reads ARM core register, special-purpose register, or Floating-point extension register
-*  CPU must be halted for this operation
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadCoreReg(U32 regsel, U32* value) { 
-  int status;
-
-  status = _WriteMem(_DCRSR_ADDR, (regsel & _DCRSR_REGSEL_MSK)); // DCRSR (0xE000EDF4) <- REGWnR == read) | REGSEL
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _ReadMem(_DCRDR_ADDR, value);                       // DCRDR (0xE000EDF8) -> value
-  }
- 
-  return status; 
-}
-
-/*********************************************************************
-*  Writes ARM core register, special-purpose register, or Floating-point extension register
-*  CPU must be halted for this operation
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteCoreReg(U32 regsel, U32 value) { 
-  int status;
-
-  status = _WriteMem(_DCRDR_ADDR, value); // DCRDR (0xE000EDF8) <- value
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _WriteMem(_DCRSR_ADDR, (_DCRSR_REGWnR | (regsel & _DCRSR_REGSEL_MSK))); // DCRSR (0xE000EDF4) <- (REGWnR == write) | REGSEL	  
-  }
-   
-  return status; 
-}
-
-/*********************************************************************
-*  Handshake: wait for debug interface becomes enabled after device reset (tboot).
-*  In worst case, when the boot code performs application HASH verification,
-*  tboot is around 600ms and depends on CPU clock used by boot code.
-*  For PowerCycle, timeout depends on the design schematic and must be longer.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _Handshake(void) {
-  U32 v;
-  int t;
-  int tDelta;
-  int status;
-
-  status = _STATUS_ERR;
-  t = JLINK_GetTime();
-  do {
-    if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-      JLINK_SWD_ReadWriteBits(&_aData_SWDtoJTAG[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-      JLINK_SWD_ReadWriteBits(&_aData_JTAGtoSWD[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    }  
-    v = 0;
-    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, _ACC_DP, &v);
-    if ((v & _DP_IDCODE_MSK) == _DP_IDCODE_VAL) { // DAP is responsive if we can read IDCODE (0x6BA02477 for SWD or 0x6BA00477 for JTAG)
-      status = _STATUS_OK;
-      break;
-    }
-    tDelta = JLINK_GetTime() - t;
-  } while (tDelta < _TIMEOUT_HANDSHAKE); // Timeout reached?
-  
-  return status;
-}
-
-/*********************************************************************
-*  Clears any sticky errors which could be left from previous sessions.
-*  Otherwise only power-down-up cycle helps to restore DAP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _ClearStickyErrors() {
-  int status;
-  U32 abort_reg;
-  U32 abort_val;
-
-  if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {	  
-    // Power up DAP and clear sticky errors using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ, [5]:STICKYERR, [4]:STICKYCMP, [1]:STICKYORUN
-    // Note: for JTAG, sticky error bits are read-write enabled and writing ‘1’ to these bits clears associated sticky errors.
-    // For SWD, these bits are read-only and to clean the sticky errors, you should write to appropriate bits of DP.ABORT register
-    abort_reg = JLINK_CORESIGHT_DP_REG_CTRL_STAT;
-    abort_val = _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_STICKYERR | _DP_CTRL_STAT_STICKYCMP | _DP_CTRL_STAT_STICKYORUN; // 0x50000032	
-  } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-    abort_reg = JLINK_CORESIGHT_DP_REG_ABORT;
-    abort_val = _AP_ABORT_ORUNERRCLR | _AP_ABORT_WDERRCLR | _AP_ABORT_STKERRCLR | _AP_ABORT_STKCMPCLR; // 0x0000001E
-  }
-
-  status = JLINK_CORESIGHT_WriteDAP(abort_reg, _ACC_DP, abort_val);
-  
-  return status;
-}
-
-/*********************************************************************
-*  Initialize the Debug Port for programing operations.
-*  Accepts Access Port number as input: 0 – System AP; 1 – CM0+ AP; 2 – CM4 AP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _InitDAP(U8 apNum, U8 doPowerUp) {
-  int status;
-
-  status = _ClearStickyErrors();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  if (doPowerUp != 0) {
-    // Power up DAP using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _ACC_DP, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ); // 0x50000000	  
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-  }
-  
-  // Select desired Access Port and set bank 0 in APACC space
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACC_DP, (apNum << _AP_SELECT_APSEL_RSH) ); // DP->SELECT.APSEL <- apNum
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Set CSW (DbgSwEnable=0, Prot=0x23, SPIDEN=0, Mode=0x0, TrInProg=0, DeviceEn=0, AddrInc=Auto-increment off, Size=Word (32 bits))
-  // Note: Set Prot bits in DAP CSW register, because of no access to CPU registers via M4 AP without these bits
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACC_AP, _DP_CSW_PROT_VAL | _DP_CSW_SIZE_WORD); // 0x23000002
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs hardware reset by toggling XRES pin
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _HardReset(void) {
-  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
-  JLINK_SYS_Sleep(50);      // Make sure that device recognizes the reset
-  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Performs software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-*  DAP communication must be established before this method call (e.g. use _Handshake + _InitDAP function)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _SoftReset() {
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _AIRCR_ADDR); // AP.TAR <- @AIRCR (0xE000ED0C)
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Note: do not check OK/WAIT/FAULT ACKs for the data write phase since the target immediately reboots
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_AP_REG_DATA, (_AIRCR_VECTKEY_VAL | _AIRCR_SYSRESETREQ) ); // AP.DRW <- 0x05FA0004
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs either of:
-*    a. Hardware reset (XRES)
-*    b. Software reset (AIRCR.SYSRESETREQ)
-*    c. Software reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_Reset(U8 doXRES) {
-  int status;
-  
-  if (doXRES != 0) {
-    status = _HardReset();
-  } else {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) == _STATUS_OK) {
-      // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-      status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-      if (_CheckStatus(status) == _STATUS_OK) {
-       status = _SoftReset(); // AIRCR.SYSRESETREQ
-      }
-
-      // In worst case, if standard software reset via SYSRESETREQ failed, it may mean that the firmware did
-      // very bad things disabling the debug pins or AHB_AP access (anything behind the DAP).
-      // However, if we still can access DAP registers, the last thing we could try is to reset the target
-      // via DP->CTRL/STAT.CDBGRSTREQ. In MXS40, setting the CDBGRSTREQ bit will result in a System wide Debug
-      // DeepSleep reset, what resets both (CM0+ and CM4) cores.
-      // Note that CDBGRSTREQ will reset the target only at first attempt after the hardware reset (XRES or Power Cycle).
-      // You need to do the additional hardware reset manually before the acquisition sequence execution if the target
-      // stucked in 'bad' state and you already used the CDBGRSTREQ bit since the previous hardware reset.
-      // If such case happens and we managed to reset the target using CDBGRSTREQ,
-      // the next thing would be to halt the CPU as quickly as possible to prevent firmware to do the bad things again.
-      if (_CheckStatus(status) != _STATUS_OK) {
-        status = _Handshake();
-        if (_CheckStatus(status) == _STATUS_OK) {
-          JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_CDBGRSTREQ); // 0x54000000
-        }
-      }
-
-    }
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Enables debug and halts or resumes the CPU using the DHCSR register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _HaltResumeCPU(U8 haltNresume) {
-  int status;
-  U32 v;
-  int t;
-  int tDelta;
-  U32 dhcsrVal;
-  U32 shaltExpectedVal;
-  
-  if (haltNresume == 0) { // Resume	
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_DEBUGEN; // 0xA05F0001
-    shaltExpectedVal = 0;
-  } else { // Halt
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN; // 0xA05F0003
-    shaltExpectedVal = _DHCSR_S_HALT;
-  }
-
-  // Enable debug, and halt the CPU using the DHCSR register
-  status = _WriteMem(_DHCSR_ADDR, dhcsrVal); // _DHCSR_ADDR (0xE000EDF0) <- dhcsrVal
-
-  if (_CheckStatus(status) == _STATUS_OK) {
-    // Poll for S_HALT bit [17] in DHCSR register (@0xE000EDF0)
-    status = _PollMem(_DHCSR_ADDR, _DHCSR_S_HALT, 0, shaltExpectedVal, _TIMEOUT_HALT_CPU, 0);
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Gets Reset Address and Initial SP values from application Vector Table
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_GetVectorTableData(U32* resetAddress, U32* sp) {
-  int status;
-  U32 v;
-  U32 vtBase;
-
-  *resetAddress = 0;
-  *sp = 0;
-  
-  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
-  // In this case boot code jumps to infinite loop in ROM or executes ‘dummy’ application.
-  // This case is sufficient condition for programming, but has no sense for debugging.
-  // Otherwise, application exist, so need to set correct PC/SP for debugging
-  
-  status = _ReadMem(_CPUSS_CM0_VTBASE_ADDR, &vtBase);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
-  
-  if ((vtBase != 0) && (vtBase != _CPUSS_CMX_VTBASE_ERR_MSK)) {
-
-    // Get Initial SP value from Vector Table
-    status = _ReadMem(vtBase, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    *sp = v;
-  
-    // Get Reset Address from Vector Table
-    status = _ReadMem(vtBase + 4, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    *resetAddress = v;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*    Sets PC and SP getting the values from Vector Table
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_SetPCandSPFromVectorTable(void) {
-  int status;
-  U32 v;
-  U32 pc;
-  U32 sp;
-
-  // Get PC and SP for the application in flash
-  status = _PSoC6_GetVectorTableData(&pc, &sp);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
- 
-  if ((pc > 0) && (sp > 0)) {
-  
-    // Set PC
-    status = _WriteCoreReg(_REGSEL_PC, pc);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    
-    // Set MSP
-    status = _WriteCoreReg(_REGSEL_MSP, sp);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    
-    //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
-    status = _ReadCoreReg(_REGSEL_xPSR, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    status = _WriteCoreReg(_REGSEL_xPSR, (v | _xPSR_T) );
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition in test mode:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Set TEST_MODE bit in TST_MODE SRSS register
-*    4. Check CPU is sleeping (executes WFI)
-*    5. Check PC is in ROM or in SFLASH (CPU must be halted to read PC)
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _PSoC6_AcquireTestMode(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 OrgTIFSpeed;
-
-  // Make sure that J-Link is using a high target interface speed, so we can meet the timing requirements as per programming specifications
-  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
-  OrgTIFSpeed = JLINK_JTAG_Speed;
-  JLINK_JTAG_Speed = _TEST_MODE_SWD_SPEED;
-  
-  // Preconfigure some CoreSight settings as time is not critical at this point
-  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP.
-  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call.
-  // Additionally, suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0");
-
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset
-  // It is critical for Test Mode acquisition, so stop and in case of failure
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 2 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0-AP (AP[1])
-  status = _InitDAP(_AP_CM0, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 3 ----------------------------------------------------------------------
-  // Enter CPU into Test Mode, so it does not start the user application
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR); // Set TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, _SRSS_TST_MODE_TEST_MODE);   
-  // Read RDBUFF to make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
-  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACC_DP, &v);
-
-  // The steps above are time critical and must be executed without delays immediately after reset.
-  // No hurry for further steps - target already acquired in Test Mode
-
-  // Restore CORESIGHT settings (See beginning of this function call for more info) and restore original TIF speed
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0");
-  JLINK_JTAG_Speed = OrgTIFSpeed;
-  
-  // - 4 ----------------------------------------------------------------------
-  // Wait for the boot code to finish with Listen window and jump to WFI instruction
-  // Polls for S_SLEEP bit [18] in DHCSR register (@0xE000EDF0) what will indicate that the Listen window ended and CPU executes WFI instruction
-  status = _PollMem(_DHCSR_ADDR, _DHCSR_S_SLEEP, 0, _DHCSR_S_SLEEP, _TIMEOUT_SLEEP_LISTEN_WINDOW, 1);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 5 ----------------------------------------------------------------------
-  // However, the WFI instruction may be executed by user application as well,
-  // so additional verification is to check PC is in ROM or in SFLASH.  
-  // CPU must be halted to read the PC
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Read PC and check it points to address in ROM or in SFLASH
-  _ReadCoreReg(_REGSEL_PC, &v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  if (((v >= _MEM_BASE_ROM) && (v < (_MEM_BASE_ROM + _MEM_SIZE_ROM))) || ((v >= _MEM_BASE_SFLASH) && (v < (_MEM_BASE_SFLASH + _MEM_SIZE_SFLASH)))) {
-    status = _STATUS_OK;
-  } else {
-    status = _STATUS_ERR;
-  }
-  
-  // If S_SLEEP is set and PC points to the address in SROM or in SFLASH, it means either of:
-  //   a. Test Mode acquisition succeeded and we fit timings
-  //   b. flash is empty or TOC2 is corrupted, so the boot code jumped to WFI or dummy application in ROM/SFLASH
-  // Either of this case is sufficient for programming
-  
-  // Clear TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0);   
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition using alternate sequence:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Halt CPU, enable debug
-*    4. Get Reset Address and Initial SP value from the vector table
-*    5. Enable Breakpoint unit and set the breakpoint at Reset Address
-*    6. Issue software reset using the SYSRESETREQ bit in AIRCR register
-*    7. Handshake + Init DAP
-*    8. Verify CPU is halted at breakpoint being set at Reset Address
-*    9. Load infinite loop into SRAM and set PC to this address
-*   10. Load SP with top of SRAM address, set thumb bit in xPSR
-*   11. Disable breakpoint unit and resume the CPU
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _PSoC6_AcquireAlternate(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 resetAddress;
-  U32 sp;
- 
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset.
-  // It is good to do even for the alternate method
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-	// Stop and return failure status if initial reset failed because it is critical for Test Mode acquisition
-    return status;
-  }
-
-  // - 2 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-  status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 3 ----------------------------------------------------------------------
-  // Enable debug and halt CPU as quickly as possible right after Reset+Handshake+InitDAP
-  // It is not absolutely mandatory to do this quickly, but there is a good chance to stop in Listen window or at least prevent user application from doing too much "bad" stuff
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 4 ----------------------------------------------------------------------
-  // Get Reset Address and Initial SP values for the current application from the vector table
-  status = _PSoC6_GetVectorTableData(&resetAddress, &sp);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Zero or error code means that the Flash is empty or TOC2 is corrupted
-  // In this case boot code jumps to infinite loop in ROM or executes ‘dummy’ application, what is sufficient condition for programming.
-  // Otherwise, user application exists, so need to do clean-up.
-  if ((resetAddress == 0) || sp == 0) {
-	  // Note that CPU is halted at this point and resume is required for system calls used during programming
-	  return _STATUS_OK;
-  }
-   
-  // - 5 ----------------------------------------------------------------------
-  // Enable Breakpoint unit
-  status = _WriteMem(_BP_CTRL_ADDR, _BP_CTRL_KEY | _BP_CTRL_ENABLE); // BP_CTRL (0xE0002000) <- 0x00000003
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Map the address bits to the breakpoint compare register bit-map, set the ENABLE and BPMATCH bits
-  v = (resetAddress & _BP_COMP_COMP_MSK) | _BP_COMP_BPMATCH | _BP_COMP_ENABLE; //(resetAddress & 0x1FFFFFFC) | 0xC0000001
-  // Update the breakpoint compare register
-  status = _WriteMem(_BP_COMP0_ADDR, v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 6 ----------------------------------------------------------------------
-  // Issue software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-  _SoftReset();
-
-  // - 7 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-  status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 8 ----------------------------------------------------------------------
-  // Verify CPU is halted at breakpoint being set at Reset Address
-  // S_HALT (bit[17]) and C_DEBUGE (bit[0]) in DHCSR register (@0xE000EDF0) must be set
-  // Polling is required in order to wait till boot code finished execution (Listen window closed) and CPU halted at the user application entry
-  v = _DHCSR_S_HALT | _DHCSR_C_DEBUGEN;
-  status = _PollMem(_DHCSR_ADDR, v, 0, v, _TIMEOUT_SLEEP_LISTEN_WINDOW, 1);
-  
-  // - 9 ----------------------------------------------------------------------
-  // Load infinite loop code into SRAM (0x08000300 <- 0xE7FEE7FE)
-  status = _WriteMem(_SRAM_LOOP_ADDR, _LOOP_CODE);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Load PC with address of infinite for loop SRAM address with thumb bit (bit [0]) set
-  status = _WriteCoreReg(_REGSEL_PC, (_SRAM_LOOP_ADDR | 1));
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 10 ---------------------------------------------------------------------
-  // Load SP with top of SRAM address – Set for minimum SRAM size devices (65 KB size)
-  status = _WriteCoreReg(_REGSEL_MSP, _SRAM_TOP_ADDR); // SP <- 0x0800FFF0
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Read xPSR register, set the thumb bit, and restore modified value to xPSR register
-  status = _ReadCoreReg(_REGSEL_xPSR, &v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  status = _WriteCoreReg(_REGSEL_xPSR, (v | _xPSR_T));
-
-  // - 11 ---------------------------------------------------------------------
-  // Disable Breakpoint unit so CPU will jump to endless loop execution in SRAM
-  status = _WriteMem(_BP_CTRL_ADDR, _BP_CTRL_KEY); // BP_CTRL (0xE0002000) <- 0x00000002 (ENABLE == "0")
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs variety of PSoC 6 chip acquisition attempts:
-*    1. Acquire in Test Mode so the boot code will not start the application
-*    1.a. Using hardware pre-reset (XRES).
-*         This is recommended and the only 100% reliable method.
-*         But it will not work if XRES pin is not connected or debugger cannot meet timing requirements.
-*    1.b. Using software pre-reset (AIRCR.SYSRESETREQ).
-*         Do it in case XRES pin is not connected.
-*    1.c. Acquire in Test Mode using software pre-reset (DP->CTRL/STAT.CDBGRSTREQ)
-*         Do it in case firmware disabled anything behind the DAP so we can't use SYSRESETREQ.
-* 
-*    If all above steps failed, Test Mode acquisition is not possible because of
-*    Listen window is turned off or the debugger cannot meet timing requirements.
-*    In this case, use one following Alternate acquisition methods with same as above pre-reset strategies:
-*
-*    2. Acquire with "Alternate Method" based on setting the breakpoint at reset address
-*    2.a. Using hardware pre-reset (XRES).
-*    2.b. Using software pre-reset (AIRCR.SYSRESETREQ)
-*    2.c. Using software pre-reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-* ! Note that XRES connection is strongly required for the hardware reset.
-*   Otherwise, neither of above methods will work if the firmware does really "bad" things such as:
-*   - Repurposes the debug pins (intentionally or unintentionally)
-*   - Disables/Protects access ports and the Listen window is turned off or too short
-*   - Intentionally or unintentionally corrupts values in MMIO registers and the Listen window is turned off or too short
-*   In this case, there is no way for debugger to establish even basic communication with target
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-
-int _PSoC6_Acquire(U32 resumeCPU) {
-  int status;
-  status = _STATUS_ERR;
-  
-  if (_DO_ACQUIRE_TEST_MODE != 0) {
-    // 1. Acquire PSoC 6 in Test Mode:  
-    //   1.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-    //   1.2. Handshake + Init DAP
-    //   1.3. Set TEST_MODE bit in TST_MODE SRSS register
-    //   1.4. Check CPU is sleeping (executes WFI)
-    //   1.5. Check PC is in ROM or in SFLASH (CPU must be halted to read PC)
-    // Items 1.1 to 1.3 are time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-    status = _PSoC6_AcquireTestMode(1 /* "1" - do hardware pre-reset (XRES) */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      // If acquisition failed for some reason (e.g. XRES is not connected), try to acquire in test mode using software reset
-      // This should work if the Listen window is wide enough and the application did not disable the debug pins
-      status = _PSoC6_AcquireTestMode(0 /* "0" - do software pre-reset (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) */);
-    }
-  }
-
-  if ((status != _STATUS_OK) && (_DO_ACQUIRE_ALTERNATE != 0) ) {
-    // 2. Performs PSoC 6 acquisition using alternate sequence:
-    //   2.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-    //   2.2. Handshake + Init DAP
-    //   2.3. Halt CPU, enable debug
-    //   2.4. Get Reset Address and Initial SP value from the vector table
-    //   2.5. Enable Breakpoint unit and set the breakpoint at Reset Address
-    //   2.6. Issue software reset using the SYSRESETREQ bit in AIRCR register
-    //   2.7. Handshake + Init DAP
-    //   2.8. Verify CPU is halted at breakpoint being set at Reset Address
-    //   2.9. Load infinite loop into SRAM and set PC to this address
-    //   2.10. Load SP with top of SRAM address, set thumb bit in xPSR
-    //   2.11. Disable breakpoint unit and resume the CPU
-    status = _PSoC6_AcquireAlternate(1 /* "1" - do hardware pre-reset (XRES) */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      // Last chance is to acquire using alternate method and software pre-reset
-      status = _PSoC6_AcquireAlternate(0 /* "0" - do software pre-reset (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) */);
-    }
-  }
-
-  // Sets PC and SP for further debugging
-  status = _PSoC6_SetPCandSPFromVectorTable();
-
-  // Resume CPU that was halted above if it is required for caller
-  if ((_CheckStatus(status) == _STATUS_OK) && (resumeCPU != 0)) {
-    status = _HaltResumeCPU(0 /* "0" - resume */);
-  }
- 
-  return _CheckStatus(status);
-}
-/*********************************************************************
-*       Global functions
-*********************************************************************/
-
-/*********************************************************************
-*  Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
-*  For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
-*  that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
-*  May also be used to specify the device name in case debugger does not pass it to the DLL.
-*
-*  Notes
-*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
-*    (2) Should only set some global DLL variables
-*/
-int ConfigTargetSettings(void) {
-  Report("*****************************************************************");
-  Report("JLinkScript: Start 'ConfigTargetSettings' for Cortex-M0+ of CY8C6xx6/CY8C6xx7");
-
-  JLINK_CORESIGHT_AddAP(_AP_SYS, CORESIGHT_CUSTOM_AP); // AP[0]  SYS-AP (used for chip acquisition sequence)
-  JLINK_CORESIGHT_AddAP(_AP_CM0, CORESIGHT_AHB_AP);    // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-  JLINK_CORESIGHT_AddAP(_AP_CM4, CORESIGHT_AHB_AP);    // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-  JLINK_CORESIGHT_IndexAHBAPToUse = _AP_MYCORE;        // AP-Index of AHB-AP to use for communication with core
-  CPU=CORTEX_M0;
-
-  Report("*****************************************************************");
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Replaces reset strategies of DLL.
-*  No matter what reset type is selected in the DLL, if this function is present, it will be called instead of the DLL internal reset.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*    (3) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int ResetTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode or using Alternate Method
-  // Note: Test Mode acquisition is time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition since DLL expects target CPU to be halted / in debug mode, when leaving ResetTarget function
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // Enable DWT, ITM, TPIU, and ETM units by setting TRCENA bit in DEMCR register
-  status = _WriteMem(_DEMCR_ADDR, _DEMCR_TRCENA); // DEMCR (0xE000EDFC) <- TRCENA
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Replaces the target-CPU-auto-find procedure of the J-Link DLL.
-*  Useful for target CPUs that are not accessible by default and need some special steps
-*  to be executed before the normal debug probe connect procedure can be executed successfully.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) If target interface JTAG is used: JTAG chain has to be specified manually before leaving this function
-*        (meaning all devices and their TAP IDs have to be specified by the user).
-*        Also appropriate JTAG TAP number to communicate with during the debug session has to be manually specified in this function.
-*    (2) MUST NOT use any MEM_ API functions
-*    (3) Global DLL variable “CPU” MUST be set when implementing this function, so the DLL knows which CPU module to use internally.
-*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int InitTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode (a. ToggleXRES; b. Handshake; c. Init DAP; d. Set TEST_MODE bit in TST_MODE SRSS register)
-  // Sequence is time critical, so executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(1); // "1" - Resume CPU that was halted during acquisition
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  JLINK_ExecCommand("SetETBIsPresent = 1"); // ETB is available
-
-  return status;
-}
-
-/*********************************************************************
-*  Called right after flash programming Usually used to restore initialized peripherals
-*  which have been used during the flash download like for example clocks or port pins
-*  (e.g. QSPI alternate function)
-*
-*  Notes / Limitations
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int HandleAfterFlashProg(void) {
-  int status;
-
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset.
-  // Otherwise, device remains acquired because the reset command sent by IDE after programming,
-  // calls ResetTarget function, which will acquire target again.
-  // This is required to start the application for normal execution and for "Attach" actions after programming.
-  status = _PSoC6_Reset(1); // "1" do XRES
-  return status;
-}
-
-/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xx7_CM4.JLinkScript

@@ -1,290 +0,0 @@
-/*********************************************************************
-*
-*       Constants (similar to defines)
-*
-**********************************************************************
-*/
-
-/*----------------- Pin mapping for the TRACE signals ----------------
-  Copy 0
-    P6_4  DS #5   cpuss.swj_swo_tdo     (SWO DATA)
-    P7_0  ACT #14 cpuss.trace_clock     (ETM/SWO TRACECLK)
-    P9_3  ACT #15 cpuss.trace_data[0]:0 (ETM TRACEDATA[0])
-    P9_2  ACT #15 cpuss.trace_data[1]:0 (ETM TRACEDATA[1])
-    P9_1  ACT #15 cpuss.trace_data[2]:0 (ETM TRACEDATA[2])
-    P9_0  ACT #15 cpuss.trace_data[3]:0 (ETM TRACEDATA[3])
-  Copy 1
-    P10_3 ACT #15 cpuss.trace_data[0]:1 (ETM TRACEDATA[0])
-    P10_2 ACT #15 cpuss.trace_data[1]:1 (ETM TRACEDATA[1])
-    P10_1 ACT #15 cpuss.trace_data[2]:1 (ETM TRACEDATA[2])
-    P10_0 ACT #15 cpuss.trace_data[3]:1 (ETM TRACEDATA[3])
-  Copy 2
-    P7_7  ACT #15 cpuss.trace_data[0]:2 (ETM TRACEDATA[0])
-    P7_6  ACT #15 cpuss.trace_data[1]:2 (ETM TRACEDATA[1])
-    P7_5  ACT #15 cpuss.trace_data[2]:2 (ETM TRACEDATA[2])
-    P7_4  ACT #15 cpuss.trace_data[3]:2 (ETM TRACEDATA[3])
-  See 'Multiple Alternate Functions' table in device datasheet.
-
-  Examples:
-  1) CY8CKIT-062-WIFI-BT Pioneer Kit, J12:
-     TCLK => P7_0, TD0 => P9_3, TD1 => P7_6, TD2 => P7_5, TD3 => P7_4  
-*/
-
-/* Global variables */
-U32 _IS_TRACE_CONFIGURED = 0x0;
-
-/* Trace clock setup registers */
-__constant U32 _PERI_CLOCK_CTL54_ADDR       = 0x40010CD8; // Clock control register for cpuss.clock_trace_in
-__constant U32 _PERI_CLOCK_CTL_DIV_SEL_MASK = 0x0000000F; // PERI_CLOCK_CTL.DIV_SEL
-__constant U32 _PERI_DIV_8_CTL0_ADDR        = 0x40010800; // Divider control (for 8.0 divider)
-__constant U32 _PERI_DIV_CMD_ADDR           = 0x40010400; // Divider command
-__constant U32 _PERI_DIV_CMD_ENABLE_MASK    = 0x80000000; // ENABLE field in PERI_DIV_CMD
-__constant U32 _PERI_DIV_CMD_DISABLE_MASK   = 0x40000000; // DISABLE field in PERI_DIV_CMD
-__constant U32 _PERI_DIV_CMD_PA_SEL_ROL     = 0x00000008; // PA_TYPE_SEL + PA_DIV_SEL fields offset in PERI_DIV_CMD
-__constant U32 _PERI_DIV_PA_SEL_MASK        = 0x000000FF; // PA_TYPE_SEL + PA_DIV_SEL fields mask (size)
-/* Trace pins setup registers */
-__constant U32 _HSIOM_PRT7_PORT_SEL0        = 0x40310070; // Port 7 selection 0
-__constant U32 _HSIOM_PRT9_PORT_SEL0        = 0x40310090; // Port 9 selection 0
-__constant U32 _HSIOM_PRT10_PORT_SEL0       = 0x403100A0; // Port 10 selection 0
-__constant U32 _GPIO_PRT7_CFG               = 0x403203A8; // Port 7 configuration
-__constant U32 _GPIO_PRT9_CFG               = 0x403204A8; // Port 9 configuration
-__constant U32 _GPIO_PRT10_CFG              = 0x40320528; // Port 10 configuration
-__constant U32 _GPIO_PRT7_CFG_OUT           = 0x403203B0; // Port 7 output buffer configuration
-__constant U32 _GPIO_PRT9_CFG_OUT           = 0x403204B0; // Port 9 output buffer configuration
-__constant U32 _GPIO_PRT10_CFG_OUT          = 0x40320530; // Port 10 output buffer configuration
-__constant U32 _PRT_IO_SEL_MASK             = 0x1F; // Mask for IO[pin]_SEL field in HSIOM_PRT[port]_PORT_SEL[0/1] register
-__constant U32 _PRT_DRIVE_MODE_MASK         = 0xF;  // Mask for IN_EN[pin] & DRIVE_MODE[pin] fields in GPIO_PRT[port]_CFG register
-__constant U32 _PRT_SLOW_MASK               = 0x1;  // Mask for SLOW[pin] field in GPIO_PRT[port]_CFG_OUT register
-__constant U32 _PRT_DRIVE_SEL_MASK          = 0x3;  // Mask for DRIVE_SEL[pin] field in GPIO_PRT[port]_CFG_OUT register
-
-/*********************************************************************
-*
-*       Local functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-* _SetupTraceClock() - Selects TPIU Clock divider for ETM Trace.
-*/
-int _SetupTraceClock(void) {	
-  U32 ClockCtlVal;
-  U32 ClockDivCtlVal;
-  U32 ClockDivSel;
-  U32 ClockDivVal;
-  U32 ClockDivCmd;
-  U32 TRACE_CLOCK_CTL_ADDR;
-  U32 TRACE_CLOCK_DIV_CTL_ADDR;
-  U32 TRACE_CLOCK_DIV_CMD_ADDR;
-  
-  TRACE_CLOCK_CTL_ADDR     = _PERI_CLOCK_CTL54_ADDR;
-  TRACE_CLOCK_DIV_CTL_ADDR = _PERI_DIV_8_CTL0_ADDR;
-  TRACE_CLOCK_DIV_CMD_ADDR = _PERI_DIV_CMD_ADDR;
-
-  ClockDivSel = (7 & _PERI_CLOCK_CTL_DIV_SEL_MASK); // Peripheral clock divider index to use for trace clock
-  ClockDivVal = (0 & _PERI_DIV_PA_SEL_MASK);        // Peripheral clock divider value for trace clock
-                                                    // Actual divider is (1+ClockDivVal)
-
-  ClockCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_CTL_ADDR);
-  ClockDivCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_DIV_CTL_ADDR + (ClockDivSel*4));
-  if((ClockCtlVal != ClockDivSel) || (ClockDivCtlVal != ((ClockDivVal << _PERI_DIV_CMD_PA_SEL_ROL) | 0x1))){
-    JLINK_SYS_Report("JLinkScript/Trace: Setup TPIU clock");
-    //
-    // Select TPIU Clock divider
-    //
-    
-    // DISABLE 8.0 DIV in PERI_DIV_CMD:
-    ClockDivCmd = _PERI_DIV_CMD_DISABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
-    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
-    // Use selected divider (8.0) for cpuss.clock_trace_in
-    JLINK_MEM_WriteU32(TRACE_CLOCK_CTL_ADDR, ClockDivSel);
-    // Set 8.0 DIV = ClockDivVal
-    JLINK_MEM_WriteU32((TRACE_CLOCK_DIV_CTL_ADDR+(ClockDivSel*4)), (ClockDivVal << 8));
-    // ENABLE 8.0 DIV 
-    ClockDivCmd = _PERI_DIV_CMD_ENABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
-    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
-  }
-
-  return 0;  
-}
-
-/*********************************************************************
-*
-* _SetupTracePin() - Configures Trace Pin.
-* Parameters:
-*   pin:                  Pin number
-*   hsiomPrtPortSel0Addr: HSIOM_PRT[port]_PORT_SEL0 register address
-*   ioSelVal:             IO[pin]_SEL field value (connection) for HSIOM_PRT[port]_PORT_SEL register
-*   gpioPrtCfgAddr:       GPIO_PRT[port]_CFG register address
-*   gpioPrtCfgOutAddr:    GPIO_PRT[port]_CFG_OUT register address
-*/
-int _SetupTracePin(U32 pin,
-                   U32 hsiomPrtPortSel0Addr, U32 ioSelVal,
-                   U32 gpioPrtCfgAddr,
-                   U32 gpioPrtCfgOutAddr) {	
-  U32 reg0;
-  U32 reg1;
-  U32 offset;
-  U32 hsiomRegAddr; // Address of HSIOM_PRT[port]_PORT_SEL0 or HSIOM_PRT[port]_PORT_SEL1
-  U32 pMode;        // pin drive mode
-  U32 pSlew;        // pin slew rate
-  U32 pStrange;     // pin drive strange
-  
-  //
-  // Select pin route connection in HSIOM_PRT[port]_PORT_SEL[0/1] register
-  // See HSIOM_PRT0_PORT_SEL0 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL0 registers
-  // See HSIOM_PRT2_PORT_SEL1 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL1 registers
-  if (pin < 4) { /* Pin[0-3] selection is in HSIOM_PRT[port]_PORT_SEL0 register */
-    hsiomRegAddr = hsiomPrtPortSel0Addr; // Use HSIOM_PRT[port]_PORT_SEL0
-    offset = pin * 8; // Offset of the IO[pin]_SEL field for required pin number,
-                      // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
-  }
-  else { /* Pin[4-7] selection is in HSIOM_PRT[port]_PORT_SEL1 register */
-    hsiomRegAddr = hsiomPrtPortSel0Addr + 4; // Use HSIOM_PRT[port]_PORT_SEL1
-    offset = (pin - 4) * 8; // Offset of the IO[pin]_SEL field for required pin number,
-                            // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
-  }
-  reg0 = JLINK_MEM_ReadU32(hsiomRegAddr);
-  reg1 = reg0;
-  reg1 &= ~(_PRT_IO_SEL_MASK << offset); // Clear IO[pin]_SEL field
-  reg1 |=  (ioSelVal         << offset); // Set field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(hsiomRegAddr, reg1);
-  }
-  
-  //
-  // Disable input buffer and set drive mode in GPIO_PRT[port]_CFG register
-  // See GPIO_PRT2_CFG in registers TRM for the bit-field map:
-  pMode = 6;      // DRIVE_MODE[pin]:
-                  //  0: HIGHZ:         Output buffer is off creating a high impedance input (default)
-                  //  1: RESERVED:      This mode is reserved and should not be used
-                  //  2: PULLUP:        Resistive pull up
-                  //  3: PULLDOWN:      Resistive pull down
-                  //  4: OD_DRIVESLOW:  Open drain, drives low
-                  //  5: OD_DRIVESHIGH: Open drain, drives high
-                  //  6: STRONG:        Strong D_OUTput buffer
-                  //  7: PULLUP_DOWN:   Pull up or pull down
-  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgAddr);
-  reg1 = reg0;
-  offset = pin * 4; // Offset of the DRIVE_MODE[pin] field for required pin number,
-                    // where 4 = 3 bits for DRIVE_MODE[pin] + 1 bit for IN_EN fields
-  reg1 &= ~(_PRT_DRIVE_MODE_MASK << offset); // Clear IN_EN[pin] and DRIVE_MODE[pin] fields
-  reg1 |=  (pMode                << offset); // Set DRIVE_MODE[pin] field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(gpioPrtCfgAddr, reg1);
-  }
-  
-  //
-  // Set slew rate and drive strength in GPIO_PRT[port]_CFG_OUT register
-  // See GPIO_PRT2_CFG_OUT in registers TRM for the bit-field map:
-  pSlew = 0x0;    // SLOW[pin]:  
-                  //  0 - Fast slew rate (default)
-                  //  1 - Slow slew rate
-  pStrange = 0x3; // DRIVE_SEL[pin]:  
-                  //  0 - FULL_DRIVE:        Full drive strength: GPIO drives current at its max rated spec.
-                  //  1 - ONE_HALF_DRIVE:    1/2 drive strength: GPIO drives current at 1/2 of its max rated spec (default)
-                  //  2 - ONE_QUARTER_DRIVE: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
-                  //  3 - ONE_EIGHTH_DRIVE:  1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
-  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgOutAddr);
-  reg1 = reg0;
-  offset = pin;
-  reg1 &= ~(_PRT_SLOW_MASK << offset); // Clear SLOW[pin] field
-  reg1 |=  (pSlew          << offset); // Set field value
-  offset = 16 + pin * 2;               // Offset of the DRIVE_SEL[pin] field for required pin number,
-                                       // where '16' is the offset of DRIVE_SEL[pin] for pin 0 and '2' is the size of DRIVE_SEL[pin]
-  reg1 &= ~(_PRT_DRIVE_SEL_MASK << offset); // Clear DRIVE_SEL[pin] field
-  reg1 |=  (pStrange            << offset); // Set field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(gpioPrtCfgOutAddr, reg1);
-  }
-  
-  return 0;
-}
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("JLinkScript/InitTarget: CORESIGHT setup");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 2;
-  CPU=CORTEX_M4;
-}
-
-/*********************************************************************
-*
-*       OnTraceStart()
-*
-*  Function description
-*    If present, called right before trace is started.
-*    Used to initialize MCU specific trace related things like configuring the trace pins for alternate function.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) May use high-level API functions like JLINK_MEM_ etc.
-*    (2) Should not call JLINK_TARGET_Halt(). Can rely on target being halted when entering this function
-*/
-int OnTraceStart(void) {
-  U32 PortWidth;
-  U32 IO_SEL_ACT14;
-  U32 IO_SEL_ACT15;
-  //U32 IO_SEL_DS5;
-
-  if (_IS_TRACE_CONFIGURED) {
-	  return 0;
-  }
-
-  // Adjust sampling point of trace pin (Optional: not needed for this cpu)
-  // JLINK_ExecCommand("TraceSampleAdjust TD=2000");   
-  
-  // Setup peripheral clocks for tracing
-  _SetupTraceClock();     
-  
-  // Setup pins for tracing: TCLK > P7_0, TD0 > P9_3, TD1 > P7_6, TD2 > P7_5, TD3 > P7_4
-  PortWidth = JLINK_TRACE_PortWidth;      
-  JLINK_SYS_Report("JLinkScript/Trace: Setup clock and data pins");
-  IO_SEL_ACT14 = 0x1A; // Connection route for 'cpuss.trace_clock' signal (P7_0)
-  IO_SEL_ACT15 = 0x1B; // Connection route for 'cpuss.trace_data[0-3]' signals (P7, P9 and P10)
-  //IO_SEL_DS5 =   0x1D; // Connection route for 'cpuss.swj_swo_tdo' signal (P6_4)
-
-  _SetupTracePin( /*P7_0*/ 0, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT14, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);
-  _SetupTracePin( /*P9_3*/ 3, _HSIOM_PRT9_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT9_CFG, _GPIO_PRT9_CFG_OUT);
-  _SetupTracePin( /*P7_6*/ 6, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-  if (PortWidth > 2) {
-    _SetupTracePin( /*P7_5*/ 5, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-    _SetupTracePin( /*P7_4*/ 4, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-  }
-  
-  _IS_TRACE_CONFIGURED = 1;
-  return 0;
-}
-

Devices/Cypress/PSoC6/CY8C6xxA_CM0p.JLinkScript

@@ -1,30 +0,0 @@
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("********************************************");
-  Report("InitTarget for PSoC6 Cortex-M0+ script");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 1;
-  CPU=CORTEX_M0;
-  JLINK_ExecCommand("SetETBIsPresent = 1");
-  Report("********************************************");
-}

Devices/Cypress/PSoC6/CY8C6xxA_CM0p_tm.JLinkScript

@@ -1,1051 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : CY8C6xxA_CM0p_tm.JLinkScript
-Purpose : J-Link script file for Cypress PSoC6A-2M/512K devices (CY8C6xxA and CY8C6xx5)
-Literature:
-  [1] J-Link User Guide
-  [2] PSoC® 6 MCU Programming Specifications (Document Number: 002-15554 http://www.cypress.com/file/385671/download)
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*       Constants (similar to defines) 
-*********************************************************************/
-
-/* --- Flags --- */
-__constant U8 _DO_ACQUIRE_TEST_MODE         = 1; // Perform or skip Test Mode acquisition sequence
-__constant U8 _DO_ACQUIRE_ALTERNATE         = 1; // Perform or skip Alternate acquisition sequence
-
-/* --- Misc. --- */
-__constant int _STATUS_OK                   = 0;  // Function return status: O.K.
-__constant int _STATUS_ERR                  = -1; // Function return status: Error
-__constant U32 _TIMEOUT_HANDSHAKE           = 3000;
-__constant U32 _TIMEOUT_HALT_CPU            = 300;
-__constant U32 _TIMEOUT_SLEEP_LISTEN_WINDOW = 200;
-__constant U32 _TEST_MODE_SWD_SPEED         = 4000;
-
-/* PSoC® 6 MCU definitions */
-__constant U32 _AP_SYS                      = 0; // AP[0]  SYS-AP (used for chip acquisition sequence)
-__constant U32 _AP_CM0                      = 1; // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-__constant U32 _AP_CM4                      = 2; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _AP_MYCORE                   = 1; // AP[1]  CM0+ Core is used as the default for this script
-__constant U32 _DP_IDCODE_MSK               = 0xFFF00FFF; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _DP_IDCODE_VAL               = 0x6BA00477; // AP[2]  0x6BA02477 for SWD or 0x6BA00477 for JTAG
-__constant U32 _CPUSS_CM0_VTBASE_ADDR       = 0x40201120; // Vector table base address for CM0+ core (CPUSS_CM0_VECTOR_TABLE_BASE reg.)
-__constant U32 _CPUSS_CMX_VTBASE_ERR_MSK    = 0xFFFF0000; // Set by boot code if flash is empty or secure application
-__constant U32 _SRSS_TST_MODE_ADDR          = 0x40260100; // SRSS_TST_MODE: Test Mode Control Register
-__constant U32 _SRSS_TST_MODE_TEST_MODE     = (1 << 31);  // SRSS_TST_MODE.TEST_MODE (bit[31], 0x80000000): 1 - Indicates the chip is in test mode. 0 - Normal operation mode
-__constant U32 _MEM_BASE_ROM                = 0x00000000; // Base address of System ROM
-__constant U32 _MEM_SIZE_ROM                = 0x00020000; // Size of System ROM
-__constant U32 _MEM_BASE_SFLASH             = 0x16000000; // Base address of supervisory flash
-__constant U32 _MEM_SIZE_SFLASH             = 0x00008000; // Size of supervisory flash
-__constant U32 _SRAM_ERROR_ADDR             = 0x080002FC; // Address in SRAM for error code
-__constant U32 _SRAM_LOOP_ADDR              = 0x08000300; // Address in SRAM for infinite loop
-__constant U32 _SRAM_TOP_ADDR               = 0x0800FFF0; // Top of SRAM address for SP set by acquisition sequence. Use minimum SRAM size devices (65 KB)
-
-/* --- AP/DP registers --- */
-__constant U32 _ACC_DP                      = 0; // APnDP for DP access
-__constant U32 _ACC_AP                      = 1; // APnDP for AP access
-__constant U32 _AP_ABORT_ORUNERRCLR         = (1 << 4);   // AP->ABORT.ORUNERRCLR (bit[4], 0x00000010): Clears CTRL/STAT.STICKYORUN
-__constant U32 _AP_ABORT_WDERRCLR           = (1 << 3);   // AP->ABORT.WDERRCLR   (bit[3], 0x00000008): Clears CTRL/STAT.WDATAERR
-__constant U32 _AP_ABORT_STKERRCLR          = (1 << 2);   // AP->ABORT.STKERRCLR  (bit[2], 0x00000004): Clears CTRL/STAT.STICKYERR
-__constant U32 _AP_ABORT_STKCMPCLR          = (1 << 1);   // AP->ABORT.STKCMPCLR  (bit[1], 0x00000002): Clears CTRL/STAT.STICKYERR
-                                                          //                      (     |= 0x0000001E)
-__constant U32 _AP_SELECT_APSEL_RSH         = 24;         // AP->SELECT.APSEL (bits[31:24], 0xFF000000): Selects an AP
-__constant U32 _DP_CTRL_STAT_CSYSPWRUPREQ   = (1 << 30);  // DP->CTRL/STAT.CSYSPWRUPREQ (bit[30], 0x40000000): System powerup request
-__constant U32 _DP_CTRL_STAT_CDBGPRWUPREQ   = (1 << 28);  // DP->CTRL/STAT.CDBGPRWUPREQ (bit[28], 0x10000000): Debug powerup request
-__constant U32 _DP_CTRL_STAT_CDBGRSTREQ     = (1 << 26);  // DP->CTRL/STAT.CDBGRSTREQ   (bit[26], 0x04000000): Debug reset request
-__constant U32 _DP_CTRL_STAT_STICKYERR      = (1 << 5);   // DP->CTRL/STAT.STICKYERR    ( bit[5], 0x00000020): Error in AP transaction
-__constant U32 _DP_CTRL_STAT_STICKYCMP      = (1 << 4);   // DP->CTRL/STAT.STICKYCMP    ( bit[4], 0x00000010): Match on a pushed operations
-__constant U32 _DP_CTRL_STAT_STICKYORUN     = (1 << 1);   // DP->CTRL/STAT.STICKYORUN   ( bit[1], 0x00000002): Overrun detection
-                                                          //                                   |= 0x50000032
-__constant U32 _DP_CSW_PROT_VAL             = (0x23 << 24); // DP->CSW.Prot (bits[30:24], 0x23000000): Bus access protection control
-                                                            // Set to 0x23, otherwise no access to CPU registers via M4 AP
-__constant U32 _DP_CSW_SIZE_WORD            = (2 << 0);     // DP->CSW.Size (  bits[2:0], 0x00000002): Size of access <- Word (32-bits)
-                                                            //                         |= 0x23000002
-/* --- ARMv6-M & ARMv7-M --- */
-__constant U32 _LOOP_CODE                   = 0xE7FEE7FE; // Endless loop
-__constant U32 _BP_CTRL_ADDR                = 0xE0002000; // BP_CTRL: Breakpoint Control register in ARMv6-M. In ARMv7-M, it is FP_CTRL: FlashPatch Control Register.
-__constant U32 _BP_CTRL_KEY                 = (1 << 1);   // BP_CTRL.KEY    (bit[1], 0x00000002): Enables write to the register
-__constant U32 _BP_CTRL_ENABLE              = (1 << 0);   // BP_CTRL.ENABLE (bit[0], 0x00000001): Enables the BPU
-__constant U32 _BP_COMP0_ADDR               = 0xE0002008; // BP_COMP0: Breakpoint Comparator registers
-__constant U32 _BP_COMP_BPMATCH             = (3 << 30);  // BP_COMP.BP_MATCH (bits[31:30], 0xC0000000): Defines the behavior when the COMP address is matched
-__constant U32 _BP_COMP_COMP_MSK            = 0x1FFFFFFC; // BP_COMP.COMP     ( bits[28:2], 0x07FFFFFF): Stores bits [28:2] of the comparison address
-__constant U32 _BP_COMP_ENABLE              = (1 << 0);   // BP_COMP.ENABLE   (     bit[0], 0x00000001): Enables the comparator
-__constant U32 _AIRCR_ADDR                  = 0xE000ED0C;     // AIRCR: Application Interrupt and Reset Control Register
-__constant U32 _AIRCR_VECTKEY_VAL           = (0x05FA << 16); // AIRCR.VECTKEY       (bits[31:16], 0x05FA0000): Vector Key. The value 0x05FA must be written to this register
-__constant U32 _AIRCR_SYSRESETREQ           = (1 << 2);       // AIRCR.SYSRESETREQ   (     bit[2], 0x00000004): System Reset Request
-__constant U32 _DHCSR_ADDR                  = 0xE000EDF0;     // DHCSR: Debug Halting Control and Status Register
-__constant U32 _DHCSR_DBGKEY_VAL            = (0xA05F << 16); // DHCSR.DBGKEY    (bits[31:16], 0xA05F0000): Must write 0xA05F to DBGKEY to enable write accesses to bits[15:0]
-__constant U32 _DHCSR_S_SLEEP               = (1 << 18);      // DHCSR.S_SLEEP   (    bit[18], 0x00040000): Indicates whether the processor is sleeping
-__constant U32 _DHCSR_S_HALT                = (1 << 17);      // DHCSR.S_HALT    (    bit[17], 0x00020000): Indicates whether the processor is in Debug state
-__constant U32 _DHCSR_C_HALT                = (1 << 1);       // DHCSR.C_HALT    (     bit[1], 0x00000002): Processor halt bit
-__constant U32 _DHCSR_C_DEBUGEN             = (1 << 0);       // DHCSR.C_DEBUGEN (     bit[0], 0x00000001): Halting debug enable bit
-                                                              //                 (DBGKEY|C_HALT|C_DEBUGEN = 0xA05F0003)
-__constant U32 _DCRSR_ADDR                  = 0xE000EDF4; // DCRSR: Debug Core Register Selector Register
-__constant U32 _DCRSR_REGWnR                = (1 << 16);  // DCRSR.REGWnR (  bit[16], 0x00010000): Specifies the access type for the transfer ('0' - Read, '1' - Write)
-__constant U32 _DCRSR_REGSEL_MSK            = 0x0000007F; // DCRSR.REGSEL (bits[6:0], 0x0000007F): Specifies the ARM core register, special-purpose register, or Floating-point extension register
-__constant U32 _xPSR_T                      = (1 << 24);  // xPSR.T (bit[24], 0x01000000): Thumb bit
-__constant U32 _REGSEL_xPSR                 = 0x10;       // xPSR
-__constant U32 _REGSEL_MSP                  = 0x11;       // Main stack pointer, MSP
-__constant U32 _REGSEL_PC                   = 0x0F;       // PC / DebugReturnAddress
-__constant U32 _DCRDR_ADDR                  = 0xE000EDF8; // DCRDR: Debug Core Register Data Register
-__constant U32 _DEMCR_ADDR                  = 0xE000EDFC; // DEMCR: Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_TRCENA                = (1 << 24);  // DEMCR.TRCENA (bit[24], 0x01000000): Global enable for all DWT and ITM features
-
-
-/*********************************************************************
-*       Static data
-*********************************************************************/
-
-// Standard ARM command to switch SWJ-DP from JTAG to SWD operations:
-const U8 _aData_JTAGtoSWD[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The JTAG interface detects only the 16-bit JTAG-to-SWD sequence starting from the test-logic-reset state.
-  0x9E, 0xE7,                                    // Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS: 0b0111 1001 1110 0111, most significant bit (MSb) first.
-                                                 // This can be represented as 0x79E7, transmitted MSB first or 0xE79E, transmitted least significant bit (LSb) first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in SWD operation
-                                                 // before sending the select sequence, the SWD interface enters line reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Standard ARM command to switch SWJ-DP from SWD to JTAG operations
-const U8 _aData_SWDtoJTAG[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The SWD interface detects the 16-bit SWD-to-JTAG sequence only when it is in reset state.
-  0x3C, 0xE7,                                    // Send the 16-bit SWD-to-JTAG select sequence on SWDIOTMS: 0b0011 1100 1110 0111, MSb first.
-                                                 // This can be represented as 0x3CE7, transmitted MSb first or 0xE73C, transmitted LSb first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least five SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in JTAG
-                                                 // operation before sending the select sequence, the JTAG TAP enters the test-logic-reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Direction buffer
-const U8 _aDir_SWJDPSwitch[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF
-};
-
-// Buffer for receiving data from target. Needs to be big enough to hold data for above sequences
-U8 _aDataOut[18];
-
-/*********************************************************************
-*       Local functions
-*********************************************************************/
-
-/*********************************************************************
-*  Checks function result
-*
-*  Return value
-*    true   O.K.
-*    false  Error
-*/
-int _CheckStatus(int status) {
-  if (status >= _STATUS_OK) {
-    return _STATUS_OK;
-  } else {
-    // Push error code to SWD that is it easier to debug the issues
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRAM_ERROR_ADDR);
-    JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0xDEADBEEF);   	  
-    return _STATUS_ERR;
-  }
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_ReadU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadMem(U32 address, U32* value) { 
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value);  // AP.DRW -> value
-  }
-  
-  return status; 
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_WriteU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteMem(U32 address, U32 value) { 
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value); // AP.DRW <- value
-  }
-  
-  return status; 
-}
-
-/*********************************************************************
-*  Polls for the expected bit-field value in given register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error/Timeout
-*/
-int _PollMem(U32 regAddr, U32 fieldMsk, U32 rsh, U32 expectedValue, U32 timeout, U32 sleepBetweenPolling) {
-  int status;  
-  int t;
-  int tDelta;
-  U32 v;
-  tDelta = -1;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, regAddr); // AP.ADDR <- regAddr
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _STATUS_ERR;
-    t = JLINK_GetTime();
-    do {
-      // Sleep some time between polling: let CPU do its job and avoid too much garbage on SWD
-      if ((sleepBetweenPolling > 0) && (tDelta >= 0 /* not first iteration*/)) {
-        JLINK_SYS_Sleep(sleepBetweenPolling);
-      }
-      v = 0;
-      status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-      break;
-      }
-      if (((v & fieldMsk) >> rsh) == expectedValue) {
-        status = _STATUS_OK;
-        break;
-      }	  
-      tDelta = JLINK_GetTime() - t;
-    } while (tDelta < timeout);
-  }
-  
-  return _CheckStatus(status); 
-}
-
-/*********************************************************************
-*  Reads ARM core register, special-purpose register, or Floating-point extension register
-*  CPU must be halted for this operation
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadCoreReg(U32 regsel, U32* value) { 
-  int status;
-
-  status = _WriteMem(_DCRSR_ADDR, (regsel & _DCRSR_REGSEL_MSK)); // DCRSR (0xE000EDF4) <- REGWnR == read) | REGSEL
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _ReadMem(_DCRDR_ADDR, value);                       // DCRDR (0xE000EDF8) -> value
-  }
- 
-  return status; 
-}
-
-/*********************************************************************
-*  Writes ARM core register, special-purpose register, or Floating-point extension register
-*  CPU must be halted for this operation
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteCoreReg(U32 regsel, U32 value) { 
-  int status;
-
-  status = _WriteMem(_DCRDR_ADDR, value); // DCRDR (0xE000EDF8) <- value
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _WriteMem(_DCRSR_ADDR, (_DCRSR_REGWnR | (regsel & _DCRSR_REGSEL_MSK))); // DCRSR (0xE000EDF4) <- (REGWnR == write) | REGSEL	  
-  }
-   
-  return status; 
-}
-
-/*********************************************************************
-*  Handshake: wait for debug interface becomes enabled after device reset (tboot).
-*  In worst case, when the boot code performs application HASH verification,
-*  tboot is around 600ms and depends on CPU clock used by boot code.
-*  For PowerCycle, timeout depends on the design schematic and must be longer.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _Handshake(void) {
-  U32 v;
-  int t;
-  int tDelta;
-  int status;
-
-  status = _STATUS_ERR;
-  t = JLINK_GetTime();
-  do {
-    if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-      JLINK_SWD_ReadWriteBits(&_aData_SWDtoJTAG[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-      JLINK_SWD_ReadWriteBits(&_aData_JTAGtoSWD[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    }  
-    v = 0;
-    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, _ACC_DP, &v);
-    if ((v & _DP_IDCODE_MSK) == _DP_IDCODE_VAL) { // DAP is responsive if we can read IDCODE (0x6BA02477 for SWD or 0x6BA00477 for JTAG)
-      status = _STATUS_OK;
-      break;
-    }
-    tDelta = JLINK_GetTime() - t;
-  } while (tDelta < _TIMEOUT_HANDSHAKE); // Timeout reached?
-  
-  return status;
-}
-
-/*********************************************************************
-*  Clears any sticky errors which could be left from previous sessions.
-*  Otherwise only power-down-up cycle helps to restore DAP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _ClearStickyErrors() {
-  int status;
-  U32 abort_reg;
-  U32 abort_val;
-
-  if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {	  
-    // Power up DAP and clear sticky errors using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ, [5]:STICKYERR, [4]:STICKYCMP, [1]:STICKYORUN
-    // Note: for JTAG, sticky error bits are read-write enabled and writing ‘1’ to these bits clears associated sticky errors.
-    // For SWD, these bits are read-only and to clean the sticky errors, you should write to appropriate bits of DP.ABORT register
-    abort_reg = JLINK_CORESIGHT_DP_REG_CTRL_STAT;
-    abort_val = _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_STICKYERR | _DP_CTRL_STAT_STICKYCMP | _DP_CTRL_STAT_STICKYORUN; // 0x50000032	
-  } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-    abort_reg = JLINK_CORESIGHT_DP_REG_ABORT;
-    abort_val = _AP_ABORT_ORUNERRCLR | _AP_ABORT_WDERRCLR | _AP_ABORT_STKERRCLR | _AP_ABORT_STKCMPCLR; // 0x0000001E
-  }
-
-  status = JLINK_CORESIGHT_WriteDAP(abort_reg, _ACC_DP, abort_val);
-  
-  return status;
-}
-
-/*********************************************************************
-*  Initialize the Debug Port for programing operations.
-*  Accepts Access Port number as input: 0 – System AP; 1 – CM0+ AP; 2 – CM4 AP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _InitDAP(U8 apNum, U8 doPowerUp) {
-  int status;
-
-  status = _ClearStickyErrors();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  if (doPowerUp != 0) {
-    // Power up DAP using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _ACC_DP, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ); // 0x50000000	  
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-  }
-  
-  // Select desired Access Port and set bank 0 in APACC space
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACC_DP, (apNum << _AP_SELECT_APSEL_RSH) ); // DP->SELECT.APSEL <- apNum
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Set CSW (DbgSwEnable=0, Prot=0x23, SPIDEN=0, Mode=0x0, TrInProg=0, DeviceEn=0, AddrInc=Auto-increment off, Size=Word (32 bits))
-  // Note: Set Prot bits in DAP CSW register, because of no access to CPU registers via M4 AP without these bits
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACC_AP, _DP_CSW_PROT_VAL | _DP_CSW_SIZE_WORD); // 0x23000002
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs hardware reset by toggling XRES pin
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _HardReset(void) {
-  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
-  JLINK_SYS_Sleep(50);      // Make sure that device recognizes the reset
-  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Performs software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-*  DAP communication must be established before this method call (e.g. use _Handshake + _InitDAP function)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _SoftReset() {
-  int status;
-  
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _AIRCR_ADDR); // AP.TAR <- @AIRCR (0xE000ED0C)
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Note: do not check OK/WAIT/FAULT ACKs for the data write phase since the target immediately reboots
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_AP_REG_DATA, (_AIRCR_VECTKEY_VAL | _AIRCR_SYSRESETREQ) ); // AP.DRW <- 0x05FA0004
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs either of:
-*    a. Hardware reset (XRES)
-*    b. Software reset (AIRCR.SYSRESETREQ)
-*    c. Software reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_Reset(U8 doXRES) {
-  int status;
-  
-  if (doXRES != 0) {
-    status = _HardReset();
-  } else {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) == _STATUS_OK) {
-      // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-      status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-      if (_CheckStatus(status) == _STATUS_OK) {
-       status = _SoftReset(); // AIRCR.SYSRESETREQ
-      }
-
-      // In worst case, if standard software reset via SYSRESETREQ failed, it may mean that the firmware did
-      // very bad things disabling the debug pins or AHB_AP access (anything behind the DAP).
-      // However, if we still can access DAP registers, the last thing we could try is to reset the target
-      // via DP->CTRL/STAT.CDBGRSTREQ. In MXS40, setting the CDBGRSTREQ bit will result in a System wide Debug
-      // DeepSleep reset, what resets both (CM0+ and CM4) cores.
-      // Note that CDBGRSTREQ will reset the target only at first attempt after the hardware reset (XRES or Power Cycle).
-      // You need to do the additional hardware reset manually before the acquisition sequence execution if the target
-      // stucked in 'bad' state and you already used the CDBGRSTREQ bit since the previous hardware reset.
-      // If such case happens and we managed to reset the target using CDBGRSTREQ,
-      // the next thing would be to halt the CPU as quickly as possible to prevent firmware to do the bad things again.
-      if (_CheckStatus(status) != _STATUS_OK) {
-        status = _Handshake();
-        if (_CheckStatus(status) == _STATUS_OK) {
-          JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_CDBGRSTREQ); // 0x54000000
-        }
-      }
-
-    }
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Enables debug and halts or resumes the CPU using the DHCSR register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _HaltResumeCPU(U8 haltNresume) {
-  int status;
-  U32 v;
-  int t;
-  int tDelta;
-  U32 dhcsrVal;
-  U32 shaltExpectedVal;
-  
-  if (haltNresume == 0) { // Resume	
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_DEBUGEN; // 0xA05F0001
-    shaltExpectedVal = 0;
-  } else { // Halt
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN; // 0xA05F0003
-    shaltExpectedVal = _DHCSR_S_HALT;
-  }
-
-  // Enable debug, and halt the CPU using the DHCSR register
-  status = _WriteMem(_DHCSR_ADDR, dhcsrVal); // _DHCSR_ADDR (0xE000EDF0) <- dhcsrVal
-
-  if (_CheckStatus(status) == _STATUS_OK) {
-    // Poll for S_HALT bit [17] in DHCSR register (@0xE000EDF0)
-    status = _PollMem(_DHCSR_ADDR, _DHCSR_S_HALT, 0, shaltExpectedVal, _TIMEOUT_HALT_CPU, 0);
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Gets Reset Address and Initial SP values from application Vector Table
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_GetVectorTableData(U32* resetAddress, U32* sp) {
-  int status;
-  U32 v;
-  U32 vtBase;
-
-  *resetAddress = 0;
-  *sp = 0;
-  
-  // Check CPUSS_CM0_VECTOR_TABLE_BASE. Zero or error code there means that the Flash is empty or TOC is corrupted.
-  // In this case boot code jumps to infinite loop in ROM or executes ‘dummy’ application.
-  // This case is sufficient condition for programming, but has no sense for debugging.
-  // Otherwise, application exist, so need to set correct PC/SP for debugging
-  
-  status = _ReadMem(_CPUSS_CM0_VTBASE_ADDR, &vtBase);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  vtBase &= _CPUSS_CMX_VTBASE_ERR_MSK;
-  
-  if ((vtBase != 0) && (vtBase != _CPUSS_CMX_VTBASE_ERR_MSK)) {
-
-    // Get Initial SP value from Vector Table
-    status = _ReadMem(vtBase, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    *sp = v;
-  
-    // Get Reset Address from Vector Table
-    status = _ReadMem(vtBase + 4, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    *resetAddress = v;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*    Sets PC and SP getting the values from Vector Table
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_SetPCandSPFromVectorTable(void) {
-  int status;
-  U32 v;
-  U32 pc;
-  U32 sp;
-
-  // Get PC and SP for the application in flash
-  status = _PSoC6_GetVectorTableData(&pc, &sp);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
- 
-  if ((pc > 0) && (sp > 0)) {
-  
-    // Set PC
-    status = _WriteCoreReg(_REGSEL_PC, pc);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    
-    // Set MSP
-    status = _WriteCoreReg(_REGSEL_MSP, sp);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    
-    //Read xPSR register, set the thumb bit, and restore modified value to xPSR register
-    status = _ReadCoreReg(_REGSEL_xPSR, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    status = _WriteCoreReg(_REGSEL_xPSR, (v | _xPSR_T) );
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition in test mode:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Set TEST_MODE bit in TST_MODE SRSS register
-*    4. Check CPU is sleeping (executes WFI)
-*    5. Check PC is in ROM or in SFLASH (CPU must be halted to read PC)
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _PSoC6_AcquireTestMode(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 OrgTIFSpeed;
-
-  // Make sure that J-Link is using a high target interface speed, so we can meet the timing requirements as per programming specifications
-  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
-  OrgTIFSpeed = JLINK_JTAG_Speed;
-  JLINK_JTAG_Speed = _TEST_MODE_SWD_SPEED;
-  
-  // Preconfigure some CoreSight settings as time is not critical at this point
-  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP.
-  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call.
-  // Additionally, suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0");
-
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset
-  // It is critical for Test Mode acquisition, so stop and in case of failure
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 2 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0-AP (AP[1])
-  status = _InitDAP(_AP_CM0, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 3 ----------------------------------------------------------------------
-  // Enter CPU into Test Mode, so it does not start the user application
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR); // Set TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, _SRSS_TST_MODE_TEST_MODE);   
-  // Read RDBUFF to make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
-  JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACC_DP, &v);
-
-  // The steps above are time critical and must be executed without delays immediately after reset.
-  // No hurry for further steps - target already acquired in Test Mode
-
-  // Restore CORESIGHT settings (See beginning of this function call for more info) and restore original TIF speed
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0");
-  JLINK_JTAG_Speed = OrgTIFSpeed;
-  
-  // - 4 ----------------------------------------------------------------------
-  // Wait for the boot code to finish with Listen window and jump to WFI instruction
-  // Polls for S_SLEEP bit [18] in DHCSR register (@0xE000EDF0) what will indicate that the Listen window ended and CPU executes WFI instruction
-  status = _PollMem(_DHCSR_ADDR, _DHCSR_S_SLEEP, 0, _DHCSR_S_SLEEP, _TIMEOUT_SLEEP_LISTEN_WINDOW, 1);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 5 ----------------------------------------------------------------------
-  // However, the WFI instruction may be executed by user application as well,
-  // so additional verification is to check PC is in ROM or in SFLASH.  
-  // CPU must be halted to read the PC
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Read PC and check it points to address in ROM or in SFLASH
-  _ReadCoreReg(_REGSEL_PC, &v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  if (((v >= _MEM_BASE_ROM) && (v < (_MEM_BASE_ROM + _MEM_SIZE_ROM))) || ((v >= _MEM_BASE_SFLASH) && (v < (_MEM_BASE_SFLASH + _MEM_SIZE_SFLASH)))) {
-    status = _STATUS_OK;
-  } else {
-    status = _STATUS_ERR;
-  }
-  
-  // If S_SLEEP is set and PC points to the address in SROM or in SFLASH, it means either of:
-  //   a. Test Mode acquisition succeeded and we fit timings
-  //   b. flash is empty or TOC2 is corrupted, so the boot code jumped to WFI or dummy application in ROM/SFLASH
-  // Either of this case is sufficient for programming
-  
-  // Clear TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0);   
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition using alternate sequence:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Halt CPU, enable debug
-*    4. Get Reset Address and Initial SP value from the vector table
-*    5. Enable Breakpoint unit and set the breakpoint at Reset Address
-*    6. Issue software reset using the SYSRESETREQ bit in AIRCR register
-*    7. Handshake + Init DAP
-*    8. Verify CPU is halted at breakpoint being set at Reset Address
-*    9. Load infinite loop into SRAM and set PC to this address
-*   10. Load SP with top of SRAM address, set thumb bit in xPSR
-*   11. Disable breakpoint unit and resume the CPU
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _PSoC6_AcquireAlternate(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 resetAddress;
-  U32 sp;
- 
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset.
-  // It is good to do even for the alternate method
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-	// Stop and return failure status if initial reset failed because it is critical for Test Mode acquisition
-    return status;
-  }
-
-  // - 2 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-  status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 3 ----------------------------------------------------------------------
-  // Enable debug and halt CPU as quickly as possible right after Reset+Handshake+InitDAP
-  // It is not absolutely mandatory to do this quickly, but there is a good chance to stop in Listen window or at least prevent user application from doing too much "bad" stuff
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 4 ----------------------------------------------------------------------
-  // Get Reset Address and Initial SP values for the current application from the vector table
-  status = _PSoC6_GetVectorTableData(&resetAddress, &sp);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Zero or error code means that the Flash is empty or TOC2 is corrupted
-  // In this case boot code jumps to infinite loop in ROM or executes ‘dummy’ application, what is sufficient condition for programming.
-  // Otherwise, user application exists, so need to do clean-up.
-  if ((resetAddress == 0) || sp == 0) {
-	  // Note that CPU is halted at this point and resume is required for system calls used during programming
-	  return _STATUS_OK;
-  }
-   
-  // - 5 ----------------------------------------------------------------------
-  // Enable Breakpoint unit
-  status = _WriteMem(_BP_CTRL_ADDR, _BP_CTRL_KEY | _BP_CTRL_ENABLE); // BP_CTRL (0xE0002000) <- 0x00000003
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Map the address bits to the breakpoint compare register bit-map, set the ENABLE and BPMATCH bits
-  v = (resetAddress & _BP_COMP_COMP_MSK) | _BP_COMP_BPMATCH | _BP_COMP_ENABLE; //(resetAddress & 0x1FFFFFFC) | 0xC0000001
-  // Update the breakpoint compare register
-  status = _WriteMem(_BP_COMP0_ADDR, v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // - 6 ----------------------------------------------------------------------
-  // Issue software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-  _SoftReset();
-
-  // - 7 ----------------------------------------------------------------------
-  // Handshake: wait for debug interface becomes enabled after device reset
-  status = _Handshake();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-  status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 8 ----------------------------------------------------------------------
-  // Verify CPU is halted at breakpoint being set at Reset Address
-  // S_HALT (bit[17]) and C_DEBUGE (bit[0]) in DHCSR register (@0xE000EDF0) must be set
-  // Polling is required in order to wait till boot code finished execution (Listen window closed) and CPU halted at the user application entry
-  v = _DHCSR_S_HALT | _DHCSR_C_DEBUGEN;
-  status = _PollMem(_DHCSR_ADDR, v, 0, v, _TIMEOUT_SLEEP_LISTEN_WINDOW, 1);
-  
-  // - 9 ----------------------------------------------------------------------
-  // Load infinite loop code into SRAM (0x08000300 <- 0xE7FEE7FE)
-  status = _WriteMem(_SRAM_LOOP_ADDR, _LOOP_CODE);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Load PC with address of infinite for loop SRAM address with thumb bit (bit [0]) set
-  status = _WriteCoreReg(_REGSEL_PC, (_SRAM_LOOP_ADDR | 1));
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // - 10 ---------------------------------------------------------------------
-  // Load SP with top of SRAM address – Set for minimum SRAM size devices (65 KB size)
-  status = _WriteCoreReg(_REGSEL_MSP, _SRAM_TOP_ADDR); // SP <- 0x0800FFF0
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Read xPSR register, set the thumb bit, and restore modified value to xPSR register
-  status = _ReadCoreReg(_REGSEL_xPSR, &v);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  status = _WriteCoreReg(_REGSEL_xPSR, (v | _xPSR_T));
-
-  // - 11 ---------------------------------------------------------------------
-  // Disable Breakpoint unit so CPU will jump to endless loop execution in SRAM
-  status = _WriteMem(_BP_CTRL_ADDR, _BP_CTRL_KEY); // BP_CTRL (0xE0002000) <- 0x00000002 (ENABLE == "0")
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs variety of PSoC 6 chip acquisition attempts:
-*    1. Acquire in Test Mode so the boot code will not start the application
-*    1.a. Using hardware pre-reset (XRES).
-*         This is recommended and the only 100% reliable method.
-*         But it will not work if XRES pin is not connected or debugger cannot meet timing requirements.
-*    1.b. Using software pre-reset (AIRCR.SYSRESETREQ).
-*         Do it in case XRES pin is not connected.
-*    1.c. Acquire in Test Mode using software pre-reset (DP->CTRL/STAT.CDBGRSTREQ)
-*         Do it in case firmware disabled anything behind the DAP so we can't use SYSRESETREQ.
-* 
-*    If all above steps failed, Test Mode acquisition is not possible because of
-*    Listen window is turned off or the debugger cannot meet timing requirements.
-*    In this case, use one following Alternate acquisition methods with same as above pre-reset strategies:
-*
-*    2. Acquire with "Alternate Method" based on setting the breakpoint at reset address
-*    2.a. Using hardware pre-reset (XRES).
-*    2.b. Using software pre-reset (AIRCR.SYSRESETREQ)
-*    2.c. Using software pre-reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-* ! Note that XRES connection is strongly required for the hardware reset.
-*   Otherwise, neither of above methods will work if the firmware does really "bad" things such as:
-*   - Repurposes the debug pins (intentionally or unintentionally)
-*   - Disables/Protects access ports and the Listen window is turned off or too short
-*   - Intentionally or unintentionally corrupts values in MMIO registers and the Listen window is turned off or too short
-*   In this case, there is no way for debugger to establish even basic communication with target
-*   
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-
-int _PSoC6_Acquire(U32 resumeCPU) {
-  int status;
-  status = _STATUS_ERR;
-  
-  if (_DO_ACQUIRE_TEST_MODE != 0) {
-    // 1. Acquire PSoC 6 in Test Mode:  
-    //   1.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-    //   1.2. Handshake + Init DAP
-    //   1.3. Set TEST_MODE bit in TST_MODE SRSS register
-    //   1.4. Check CPU is sleeping (executes WFI)
-    //   1.5. Check PC is in ROM or in SFLASH (CPU must be halted to read PC)
-    // Items 1.1 to 1.3 are time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-    status = _PSoC6_AcquireTestMode(1 /* "1" - do hardware pre-reset (XRES) */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      // If acquisition failed for some reason (e.g. XRES is not connected), try to acquire in test mode using software reset
-      // This should work if the Listen window is wide enough and the application did not disable the debug pins
-      status = _PSoC6_AcquireTestMode(0 /* "0" - do software pre-reset (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) */);
-    }
-  }
-
-  if ((status != _STATUS_OK) && (_DO_ACQUIRE_ALTERNATE != 0) ) {
-    // 2. Performs PSoC 6 acquisition using alternate sequence:
-    //   2.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-    //   2.2. Handshake + Init DAP
-    //   2.3. Halt CPU, enable debug
-    //   2.4. Get Reset Address and Initial SP value from the vector table
-    //   2.5. Enable Breakpoint unit and set the breakpoint at Reset Address
-    //   2.6. Issue software reset using the SYSRESETREQ bit in AIRCR register
-    //   2.7. Handshake + Init DAP
-    //   2.8. Verify CPU is halted at breakpoint being set at Reset Address
-    //   2.9. Load infinite loop into SRAM and set PC to this address
-    //   2.10. Load SP with top of SRAM address, set thumb bit in xPSR
-    //   2.11. Disable breakpoint unit and resume the CPU
-    status = _PSoC6_AcquireAlternate(1 /* "1" - do hardware pre-reset (XRES) */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      // Last chance is to acquire using alternate method and software pre-reset
-      status = _PSoC6_AcquireAlternate(0 /* "0" - do software pre-reset (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) */);
-    }
-  }
-
-  // Sets PC and SP for further debugging
-  status = _PSoC6_SetPCandSPFromVectorTable();
-
-  // Resume CPU that was halted above if it is required for caller
-  if ((_CheckStatus(status) == _STATUS_OK) && (resumeCPU != 0)) {
-    status = _HaltResumeCPU(0 /* "0" - resume */);
-  }
- 
-  return _CheckStatus(status);
-}
-/*********************************************************************
-*       Global functions
-*********************************************************************/
-
-/*********************************************************************
-*  Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
-*  For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
-*  that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
-*  May also be used to specify the device name in case debugger does not pass it to the DLL.
-*
-*  Notes
-*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
-*    (2) Should only set some global DLL variables
-*/
-int ConfigTargetSettings(void) {
-  Report("*****************************************************************");
-  Report("JLinkScript: Start 'ConfigTargetSettings' for Cortex-M0+ of CY8C6xx5/CY8C6xxA");
-
-  JLINK_CORESIGHT_AddAP(_AP_SYS, CORESIGHT_CUSTOM_AP); // AP[0]  SYS-AP (used for chip acquisition sequence)
-  JLINK_CORESIGHT_AddAP(_AP_CM0, CORESIGHT_AHB_AP);    // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-  JLINK_CORESIGHT_AddAP(_AP_CM4, CORESIGHT_AHB_AP);    // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-  JLINK_CORESIGHT_IndexAHBAPToUse = _AP_MYCORE;        // AP-Index of AHB-AP to use for communication with core
-  CPU=CORTEX_M0;
-
-  Report("*****************************************************************");
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Replaces reset strategies of DLL.
-*  No matter what reset type is selected in the DLL, if this function is present, it will be called instead of the DLL internal reset.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*    (3) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int ResetTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode or using Alternate Method
-  // Note: Test Mode acquisition is time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition since DLL expects target CPU to be halted / in debug mode, when leaving ResetTarget function
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  
-  // Enable DWT, ITM, TPIU, and ETM units by setting TRCENA bit in DEMCR register
-  status = _WriteMem(_DEMCR_ADDR, _DEMCR_TRCENA); // DEMCR (0xE000EDFC) <- TRCENA
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Replaces the target-CPU-auto-find procedure of the J-Link DLL.
-*  Useful for target CPUs that are not accessible by default and need some special steps
-*  to be executed before the normal debug probe connect procedure can be executed successfully.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) If target interface JTAG is used: JTAG chain has to be specified manually before leaving this function
-*        (meaning all devices and their TAP IDs have to be specified by the user).
-*        Also appropriate JTAG TAP number to communicate with during the debug session has to be manually specified in this function.
-*    (2) MUST NOT use any MEM_ API functions
-*    (3) Global DLL variable “CPU” MUST be set when implementing this function, so the DLL knows which CPU module to use internally.
-*    (4) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int InitTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode (a. ToggleXRES; b. Handshake; c. Init DAP; d. Set TEST_MODE bit in TST_MODE SRSS register)
-  // Sequence is time critical, so executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(1); // "1" - Resume CPU that was halted during acquisition
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  JLINK_ExecCommand("SetETBIsPresent = 1"); // ETB is available
-
-  return status;
-}
-
-/*********************************************************************
-*  Called right after flash programming Usually used to restore initialized peripherals
-*  which have been used during the flash download like for example clocks or port pins
-*  (e.g. QSPI alternate function)
-*
-*  Notes / Limitations
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int HandleAfterFlashProg(void) {
-  int status;
-
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset.
-  // Otherwise, device remains acquired because the reset command sent by IDE after programming,
-  // calls ResetTarget function, which will acquire target again.
-  // This is required to start the application for normal execution and for "Attach" actions after programming.
-  status = _PSoC6_Reset(1); // "1" do XRES
-  return status;
-}
-
-/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CY8C6xxA_CM4.JLinkScript

@@ -1,290 +0,0 @@
-/*********************************************************************
-*
-*       Constants (similar to defines)
-*
-**********************************************************************
-*/
-
-/*----------------- Pin mapping for the TRACE signals ----------------
-  Copy 0
-    P6_4  DS #5   cpuss.swj_swo_tdo     (SWO DATA)
-    P7_0  ACT #14 cpuss.trace_clock     (ETM/SWO TRACECLK)
-    P9_3  ACT #15 cpuss.trace_data[0]:0 (ETM TRACEDATA[0])
-    P9_2  ACT #15 cpuss.trace_data[1]:0 (ETM TRACEDATA[1])
-    P9_1  ACT #15 cpuss.trace_data[2]:0 (ETM TRACEDATA[2])
-    P9_0  ACT #15 cpuss.trace_data[3]:0 (ETM TRACEDATA[3])
-  Copy 1
-    P10_3 ACT #15 cpuss.trace_data[0]:1 (ETM TRACEDATA[0])
-    P10_2 ACT #15 cpuss.trace_data[1]:1 (ETM TRACEDATA[1])
-    P10_1 ACT #15 cpuss.trace_data[2]:1 (ETM TRACEDATA[2])
-    P10_0 ACT #15 cpuss.trace_data[3]:1 (ETM TRACEDATA[3])
-  Copy 2
-    P7_7  ACT #15 cpuss.trace_data[0]:2 (ETM TRACEDATA[0])
-    P7_6  ACT #15 cpuss.trace_data[1]:2 (ETM TRACEDATA[1])
-    P7_5  ACT #15 cpuss.trace_data[2]:2 (ETM TRACEDATA[2])
-    P7_4  ACT #15 cpuss.trace_data[3]:2 (ETM TRACEDATA[3])
-  See 'Multiple Alternate Functions' table in device datasheet.
-
-  Examples:
-  1) CY8CKIT-062-WIFI-BT Pioneer Kit, J12:
-     TCLK => P7_0, TD0 => P9_3, TD1 => P7_6, TD2 => P7_5, TD3 => P7_4  
-*/
-
-/* Global variables */
-U32 _IS_TRACE_CONFIGURED = 0x0;
-
-/* Trace clock setup registers */
-__constant U32 _PERI_CLOCK_CTL50_ADDR       = 0x40000CC8; // Clock control register for cpuss.clock_trace_in
-__constant U32 _PERI_CLOCK_CTL_DIV_SEL_MASK = 0x0000000F; // PERI_CLOCK_CTL.DIV_SEL
-__constant U32 _PERI_DIV_8_CTL0_ADDR        = 0x40001000; // Divider control (for 8.0 divider)
-__constant U32 _PERI_DIV_CMD_ADDR           = 0x40000400; // Divider command
-__constant U32 _PERI_DIV_CMD_ENABLE_MASK    = 0x80000000; // ENABLE field in PERI_DIV_CMD
-__constant U32 _PERI_DIV_CMD_DISABLE_MASK   = 0x40000000; // DISABLE field in PERI_DIV_CMD
-__constant U32 _PERI_DIV_CMD_PA_SEL_ROL     = 0x00000010; // PA_TYPE_SEL + PA_DIV_SEL fields offset in PERI_DIV_CMD
-__constant U32 _PERI_DIV_PA_SEL_MASK        = 0x000003FF; // PA_TYPE_SEL + PA_DIV_SEL fields mask (size)
-/* Trace pins setup registers */
-__constant U32 _HSIOM_PRT7_PORT_SEL0        = 0x40300070; // Port 7 selection 0
-__constant U32 _HSIOM_PRT9_PORT_SEL0        = 0x40300090; // Port 9 selection 0
-__constant U32 _HSIOM_PRT10_PORT_SEL0       = 0x403000A0; // Port 10 selection 0
-__constant U32 _GPIO_PRT7_CFG               = 0x403103C4; // Port 7 configuration
-__constant U32 _GPIO_PRT9_CFG               = 0x403104C4; // Port 9 configuration
-__constant U32 _GPIO_PRT10_CFG              = 0x40310544; // Port 10 configuration
-__constant U32 _GPIO_PRT7_CFG_OUT           = 0x403103CC; // Port 7 output buffer configuration
-__constant U32 _GPIO_PRT9_CFG_OUT           = 0x403104CC; // Port 9 output buffer configuration
-__constant U32 _GPIO_PRT10_CFG_OUT          = 0x4031054C; // Port 10 output buffer configuration
-__constant U32 _PRT_IO_SEL_MASK             = 0x1F; // Mask for IO[pin]_SEL field in HSIOM_PRT[port]_PORT_SEL[0/1] register
-__constant U32 _PRT_DRIVE_MODE_MASK         = 0xF;  // Mask for IN_EN[pin] & DRIVE_MODE[pin] fields in GPIO_PRT[port]_CFG register
-__constant U32 _PRT_SLOW_MASK               = 0x1;  // Mask for SLOW[pin] field in GPIO_PRT[port]_CFG_OUT register
-__constant U32 _PRT_DRIVE_SEL_MASK          = 0x3;  // Mask for DRIVE_SEL[pin] field in GPIO_PRT[port]_CFG_OUT register
-
-/*********************************************************************
-*
-*       Local functions
-*
-**********************************************************************
-*/
-
-/*********************************************************************
-*
-* _SetupTraceClock() - Selects TPIU Clock divider for ETM Trace.
-*/
-int _SetupTraceClock(void) {	
-  U32 ClockCtlVal;
-  U32 ClockDivCtlVal;
-  U32 ClockDivSel;
-  U32 ClockDivVal;
-  U32 ClockDivCmd;
-  U32 TRACE_CLOCK_CTL_ADDR;
-  U32 TRACE_CLOCK_DIV_CTL_ADDR;
-  U32 TRACE_CLOCK_DIV_CMD_ADDR;
-  
-  TRACE_CLOCK_CTL_ADDR     = _PERI_CLOCK_CTL50_ADDR;
-  TRACE_CLOCK_DIV_CTL_ADDR = _PERI_DIV_8_CTL0_ADDR;
-  TRACE_CLOCK_DIV_CMD_ADDR = _PERI_DIV_CMD_ADDR;
-
-  ClockDivSel = (7 & _PERI_CLOCK_CTL_DIV_SEL_MASK); // Peripheral clock divider index to use for trace clock
-  ClockDivVal = (0 & _PERI_DIV_PA_SEL_MASK);        // Peripheral clock divider value for trace clock
-                                                    // Actual divider is (1+ClockDivVal)
-
-  ClockCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_CTL_ADDR);
-  ClockDivCtlVal = JLINK_MEM_ReadU32(TRACE_CLOCK_DIV_CTL_ADDR + (ClockDivSel*4));
-  if((ClockCtlVal != ClockDivSel) || (ClockDivCtlVal != ((ClockDivVal << _PERI_DIV_CMD_PA_SEL_ROL) | 0x1))){
-    JLINK_SYS_Report("JLinkScript/Trace: Setup TPIU clock");
-    //
-    // Select TPIU Clock divider
-    //
-    
-    // DISABLE 8.0 DIV in PERI_DIV_CMD:
-    ClockDivCmd = _PERI_DIV_CMD_DISABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
-    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
-    // Use selected divider (8.0) for cpuss.clock_trace_in
-    JLINK_MEM_WriteU32(TRACE_CLOCK_CTL_ADDR, ClockDivSel);
-    // Set 8.0 DIV = ClockDivVal
-    JLINK_MEM_WriteU32((TRACE_CLOCK_DIV_CTL_ADDR+(ClockDivSel*4)), (ClockDivVal << 8));
-    // ENABLE 8.0 DIV 
-    ClockDivCmd = _PERI_DIV_CMD_ENABLE_MASK | (_PERI_DIV_PA_SEL_MASK << _PERI_DIV_CMD_PA_SEL_ROL) | ClockDivSel;
-    JLINK_MEM_WriteU32(TRACE_CLOCK_DIV_CMD_ADDR, ClockDivCmd);
-  }
-
-  return 0;  
-}
-
-/*********************************************************************
-*
-* _SetupTracePin() - Configures Trace Pin.
-* Parameters:
-*   pin:                  Pin number
-*   hsiomPrtPortSel0Addr: HSIOM_PRT[port]_PORT_SEL0 register address
-*   ioSelVal:             IO[pin]_SEL field value (connection) for HSIOM_PRT[port]_PORT_SEL register
-*   gpioPrtCfgAddr:       GPIO_PRT[port]_CFG register address
-*   gpioPrtCfgOutAddr:    GPIO_PRT[port]_CFG_OUT register address
-*/
-int _SetupTracePin(U32 pin,
-                   U32 hsiomPrtPortSel0Addr, U32 ioSelVal,
-                   U32 gpioPrtCfgAddr,
-                   U32 gpioPrtCfgOutAddr) {	
-  U32 reg0;
-  U32 reg1;
-  U32 offset;
-  U32 hsiomRegAddr; // Address of HSIOM_PRT[port]_PORT_SEL0 or HSIOM_PRT[port]_PORT_SEL1
-  U32 pMode;        // pin drive mode
-  U32 pSlew;        // pin slew rate
-  U32 pStrange;     // pin drive strange
-  
-  //
-  // Select pin route connection in HSIOM_PRT[port]_PORT_SEL[0/1] register
-  // See HSIOM_PRT0_PORT_SEL0 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL0 registers
-  // See HSIOM_PRT2_PORT_SEL1 in registers TRM for the bit-field map of HSIOM_PRT[port]_PORT_SEL1 registers
-  if (pin < 4) { /* Pin[0-3] selection is in HSIOM_PRT[port]_PORT_SEL0 register */
-    hsiomRegAddr = hsiomPrtPortSel0Addr; // Use HSIOM_PRT[port]_PORT_SEL0
-    offset = pin * 8; // Offset of the IO[pin]_SEL field for required pin number,
-                      // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
-  }
-  else { /* Pin[4-7] selection is in HSIOM_PRT[port]_PORT_SEL1 register */
-    hsiomRegAddr = hsiomPrtPortSel0Addr + 4; // Use HSIOM_PRT[port]_PORT_SEL1
-    offset = (pin - 4) * 8; // Offset of the IO[pin]_SEL field for required pin number,
-                            // where 8 = 5 bits for IO[pin]_SEL field + 3 not used bits
-  }
-  reg0 = JLINK_MEM_ReadU32(hsiomRegAddr);
-  reg1 = reg0;
-  reg1 &= ~(_PRT_IO_SEL_MASK << offset); // Clear IO[pin]_SEL field
-  reg1 |=  (ioSelVal         << offset); // Set field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(hsiomRegAddr, reg1);
-  }
-  
-  //
-  // Disable input buffer and set drive mode in GPIO_PRT[port]_CFG register
-  // See GPIO_PRT2_CFG in registers TRM for the bit-field map:
-  pMode = 6;      // DRIVE_MODE[pin]:
-                  //  0: HIGHZ:         Output buffer is off creating a high impedance input (default)
-                  //  1: RESERVED:      This mode is reserved and should not be used
-                  //  2: PULLUP:        Resistive pull up
-                  //  3: PULLDOWN:      Resistive pull down
-                  //  4: OD_DRIVESLOW:  Open drain, drives low
-                  //  5: OD_DRIVESHIGH: Open drain, drives high
-                  //  6: STRONG:        Strong D_OUTput buffer
-                  //  7: PULLUP_DOWN:   Pull up or pull down
-  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgAddr);
-  reg1 = reg0;
-  offset = pin * 4; // Offset of the DRIVE_MODE[pin] field for required pin number,
-                    // where 4 = 3 bits for DRIVE_MODE[pin] + 1 bit for IN_EN fields
-  reg1 &= ~(_PRT_DRIVE_MODE_MASK << offset); // Clear IN_EN[pin] and DRIVE_MODE[pin] fields
-  reg1 |=  (pMode                << offset); // Set DRIVE_MODE[pin] field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(gpioPrtCfgAddr, reg1);
-  }
-  
-  //
-  // Set slew rate and drive strength in GPIO_PRT[port]_CFG_OUT register
-  // See GPIO_PRT2_CFG_OUT in registers TRM for the bit-field map:
-  pSlew = 0x0;    // SLOW[pin]:  
-                  //  0 - Fast slew rate (default)
-                  //  1 - Slow slew rate
-  pStrange = 0x3; // DRIVE_SEL[pin]:  
-                  //  0 - FULL_DRIVE:        Full drive strength: GPIO drives current at its max rated spec.
-                  //  1 - ONE_HALF_DRIVE:    1/2 drive strength: GPIO drives current at 1/2 of its max rated spec (default)
-                  //  2 - ONE_QUARTER_DRIVE: 1/4 drive strength: GPIO drives current at 1/4 of its max rated spec.
-                  //  3 - ONE_EIGHTH_DRIVE:  1/8 drive strength: GPIO drives current at 1/8 of its max rated spec.
-  reg0 = JLINK_MEM_ReadU32(gpioPrtCfgOutAddr);
-  reg1 = reg0;
-  offset = pin;
-  reg1 &= ~(_PRT_SLOW_MASK << offset); // Clear SLOW[pin] field
-  reg1 |=  (pSlew          << offset); // Set field value
-  offset = 16 + pin * 2;               // Offset of the DRIVE_SEL[pin] field for required pin number,
-                                       // where '16' is the offset of DRIVE_SEL[pin] for pin 0 and '2' is the size of DRIVE_SEL[pin]
-  reg1 &= ~(_PRT_DRIVE_SEL_MASK << offset); // Clear DRIVE_SEL[pin] field
-  reg1 |=  (pStrange            << offset); // Set field value
-  if (reg0 |= reg1) {
-    JLINK_MEM_WriteU32(gpioPrtCfgOutAddr, reg1);
-  }
-  
-  return 0;
-}
-
-/*********************************************************************
-*
-*       Global functions
-*
-**********************************************************************
-*/
-
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("JLinkScript/InitTarget: CORESIGHT setup");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 2;
-  CPU=CORTEX_M4;
-}
-
-/*********************************************************************
-*
-*       OnTraceStart()
-*
-*  Function description
-*    If present, called right before trace is started.
-*    Used to initialize MCU specific trace related things like configuring the trace pins for alternate function.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) May use high-level API functions like JLINK_MEM_ etc.
-*    (2) Should not call JLINK_TARGET_Halt(). Can rely on target being halted when entering this function
-*/
-int OnTraceStart(void) {
-  U32 PortWidth;
-  U32 IO_SEL_ACT14;
-  U32 IO_SEL_ACT15;
-  //U32 IO_SEL_DS5;
-
-  if (_IS_TRACE_CONFIGURED) {
-	  return 0;
-  }
-
-  // Adjust sampling point of trace pin (Optional: not needed for this cpu)
-  // JLINK_ExecCommand("TraceSampleAdjust TD=2000");   
-  
-  // Setup peripheral clocks for tracing
-  _SetupTraceClock();     
-  
-  // Setup pins for tracing: TCLK > P7_0, TD0 > P9_3, TD1 > P7_6, TD2 > P7_5, TD3 > P7_4
-  PortWidth = JLINK_TRACE_PortWidth;      
-  JLINK_SYS_Report("JLinkScript/Trace: Setup clock and data pins");
-  IO_SEL_ACT14 = 0x1A; // Connection route for 'cpuss.trace_clock' signal (P7_0)
-  IO_SEL_ACT15 = 0x1B; // Connection route for 'cpuss.trace_data[0-3]' signals (P7, P9 and P10)
-  //IO_SEL_DS5 =   0x1D; // Connection route for 'cpuss.swj_swo_tdo' signal (P6_4)
-
-  _SetupTracePin( /*P7_0*/ 0, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT14, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);
-  _SetupTracePin( /*P9_3*/ 3, _HSIOM_PRT9_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT9_CFG, _GPIO_PRT9_CFG_OUT);
-  _SetupTracePin( /*P7_6*/ 6, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-  if (PortWidth > 2) {
-    _SetupTracePin( /*P7_5*/ 5, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-    _SetupTracePin( /*P7_4*/ 4, _HSIOM_PRT7_PORT_SEL0, IO_SEL_ACT15, _GPIO_PRT7_CFG, _GPIO_PRT7_CFG_OUT);  
-  }
-  
-  _IS_TRACE_CONFIGURED = 1;
-  return 0;
-}
-

Devices/Cypress/PSoC6/CYxx64xx_CM0p.JLinkScript

@@ -1,30 +0,0 @@
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("********************************************");
-  Report("InitTarget for PSoC6 Cortex-M0+ script");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 1;
-  CPU=CORTEX_M0;
-  JLINK_ExecCommand("SetETBIsPresent = 1");
-  Report("********************************************");
-}

Devices/Cypress/PSoC6/CYxx64xx_CM0p_tm.JLinkScript

@@ -1,837 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : CYxx64xx_CM0p_tm.JLinkScript
-Purpose : J-Link script file for Cypress PSoC64-2M/1M/512K devices (CYB064xA, CYS064xA, CYB064x7 and CYB064x5)
-Literature:
-  [1] J-Link User Guide
-  [2] PSoC® 64 MCU Programming Specifications (Document Number: 002-31353)
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*       Constants (similar to defines)
-*********************************************************************/
-
-/* --- Misc. --- */
-__constant int _STATUS_OK                   = 0;  // Function return status: O.K.
-__constant int _STATUS_ERR                  = -1; // Function return status: Error
-__constant U32 _TIMEOUT_HANDSHAKE           = 30000; // For 30 seconds for secure device
-__constant U32 _TIMEOUT_HALT_CPU            = 300;
-__constant U32 _TEST_MODE_SWD_SPEED         = 4000;
-
-/* PSoC® 6 MCU definitions */
-__constant U32 _AP_SYS                      = 0; // AP[0]  SYS-AP (used for chip acquisition sequence)
-__constant U32 _AP_CM0                      = 1; // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-__constant U32 _AP_CM4                      = 2; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _AP_MYCORE                   = 1; // AP[1]  CM0+ Core is used as the default for this script
-__constant U32 _DP_IDCODE_MSK               = 0xFFF00FFF; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _DP_IDCODE_VAL               = 0x6BA00477; // AP[2]  0x6BA02477 for SWD or 0x6BA00477 for JTAG
-__constant U32 _SRSS_TST_MODE_ADDR          = 0x40260100; // SRSS_TST_MODE: Test Mode Control Register
-__constant U32 _SRSS_TST_MODE_TEST_MODE     = (1 << 31);  // SRSS_TST_MODE.TEST_MODE (bit[31], 0x80000000): 1 - Indicates the chip is in test mode. 0 - Normal operation mode
-__constant U32 _SRAM_ERROR_ADDR             = 0x080002FC; // Address in SRAM for error code
-
-/* --- AP/DP registers --- */
-__constant U32 _ACC_DP                      = 0; // APnDP for DP access
-__constant U32 _ACC_AP                      = 1; // APnDP for AP access
-__constant U32 _AP_ABORT_ORUNERRCLR         = (1 << 4);   // AP->ABORT.ORUNERRCLR (bit[4], 0x00000010): Clears CTRL/STAT.STICKYORUN
-__constant U32 _AP_ABORT_WDERRCLR           = (1 << 3);   // AP->ABORT.WDERRCLR   (bit[3], 0x00000008): Clears CTRL/STAT.WDATAERR
-__constant U32 _AP_ABORT_STKERRCLR          = (1 << 2);   // AP->ABORT.STKERRCLR  (bit[2], 0x00000004): Clears CTRL/STAT.STICKYERR
-__constant U32 _AP_ABORT_STKCMPCLR          = (1 << 1);   // AP->ABORT.STKCMPCLR  (bit[1], 0x00000002): Clears CTRL/STAT.STICKYERR
-                                                          //                      (     |= 0x0000001E)
-__constant U32 _AP_SELECT_APSEL_RSH         = 24;         // AP->SELECT.APSEL (bits[31:24], 0xFF000000): Selects an AP
-__constant U32 _DP_CTRL_STAT_CSYSPWRUPREQ   = (1 << 30);  // DP->CTRL/STAT.CSYSPWRUPREQ (bit[30], 0x40000000): System powerup request
-__constant U32 _DP_CTRL_STAT_CDBGPRWUPREQ   = (1 << 28);  // DP->CTRL/STAT.CDBGPRWUPREQ (bit[28], 0x10000000): Debug powerup request
-__constant U32 _DP_CTRL_STAT_CDBGRSTREQ     = (1 << 26);  // DP->CTRL/STAT.CDBGRSTREQ   (bit[26], 0x04000000): Debug reset request
-__constant U32 _DP_CTRL_STAT_STICKYERR      = (1 << 5);   // DP->CTRL/STAT.STICKYERR    ( bit[5], 0x00000020): Error in AP transaction
-__constant U32 _DP_CTRL_STAT_STICKYCMP      = (1 << 4);   // DP->CTRL/STAT.STICKYCMP    ( bit[4], 0x00000010): Match on a pushed operations
-__constant U32 _DP_CTRL_STAT_STICKYORUN     = (1 << 1);   // DP->CTRL/STAT.STICKYORUN   ( bit[1], 0x00000002): Overrun detection
-                                                          //                                   |= 0x50000032
-__constant U32 _DP_CSW_PROT_VAL             = (0x23 << 24); // DP->CSW.Prot (bits[30:24], 0x23000000): Bus access protection control
-                                                            // Set to 0x23, otherwise no access to CPU registers via M4 AP
-__constant U32 _DP_CSW_SIZE_WORD            = (2 << 0);     // DP->CSW.Size (  bits[2:0], 0x00000002): Size of access <- Word (32-bits)
-                                                            //                         |= 0x23000002
-/* --- ARMv6-M & ARMv7-M --- */
-__constant U32 _AIRCR_ADDR                  = 0xE000ED0C;     // AIRCR: Application Interrupt and Reset Control Register
-__constant U32 _AIRCR_VECTKEY_VAL           = (0x05FA << 16); // AIRCR.VECTKEY       (bits[31:16], 0x05FA0000): Vector Key. The value 0x05FA must be written to this register
-__constant U32 _AIRCR_SYSRESETREQ           = (1 << 2);       // AIRCR.SYSRESETREQ   (     bit[2], 0x00000004): System Reset Request
-__constant U32 _DHCSR_ADDR                  = 0xE000EDF0;     // DHCSR: Debug Halting Control and Status Register
-__constant U32 _DHCSR_DBGKEY_VAL            = (0xA05F << 16); // DHCSR.DBGKEY    (bits[31:16], 0xA05F0000): Must write 0xA05F to DBGKEY to enable write accesses to bits[15:0]
-__constant U32 _DHCSR_S_HALT                = (1 << 17);      // DHCSR.S_HALT    (    bit[17], 0x00020000): Indicates whether the processor is in Debug state
-__constant U32 _DHCSR_C_HALT                = (1 << 1);       // DHCSR.C_HALT    (     bit[1], 0x00000002): Processor halt bit
-__constant U32 _DHCSR_C_DEBUGEN             = (1 << 0);       // DHCSR.C_DEBUGEN (     bit[0], 0x00000001): Halting debug enable bit
-                                                              //                 (DBGKEY|C_HALT|C_DEBUGEN = 0xA05F0003)
-__constant U32 _DEMCR_ADDR                  = 0xE000EDFC; // DEMCR: Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_TRCENA                = (1 << 24);  // DEMCR.TRCENA (bit[24], 0x01000000): Global enable for all DWT and ITM features
-
-// Secure magic
-__constant U32 _SRAM_MAGIC_NUMBER_VAL       = 0x12344321;  // Magic Number value
-__constant U32 _SRAM_MAGIC_NUMBER_MSK       = 0xFFFFFFFF;  // Magic Number mask
-
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_512K_FAMILY = 0x0803E004;
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_1M_FAMILY   = 0x08044804;
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_2M_FAMILY   = 0x080FE004;
-
-// Device family defines
-__constant U16 _PSOC64_UNKNOWN_FAMILY       = 0;
-__constant U16 _PSOC64_2M_FAMILY            = 0x102;
-__constant U16 _PSOC64_1M_FAMILY            = 0x100;
-__constant U16 _PSOC64_512K_FAMILY          = 0x105;
-
-// ROM table defines
-__constant U32 _BASE_ADDR_MASK               = 0xFFFFF000;
-__constant U32 _BASE_FORMAT_MASK             = 0x00000003;
-__constant U32 _PIDR0_ADDR                   = 0x00000FE0;
-__constant U32 _PIDR4_ADDR                   = 0x00000FD0;
-__constant U32 _PIDR_0_3_VALID_MASK          = 0x000FF000;
-__constant U32 _PIDR_0_3_VALID_VAL           = 0x000B4000;
-__constant U32 _FAMILY_ID_MASK               = 0x00000FFF;
-
-
-/*********************************************************************
-*       Static data
-*********************************************************************/
-
-// Standard ARM command to switch SWJ-DP from JTAG to SWD operations:
-const U8 _aData_JTAGtoSWD[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The JTAG interface detects only the 16-bit JTAG-to-SWD sequence starting from the test-logic-reset state.
-  0x9E, 0xE7,                                    // Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS: 0b0111 1001 1110 0111, most significant bit (MSb) first.
-                                                 // This can be represented as 0x79E7, transmitted MSB first or 0xE79E, transmitted least significant bit (LSb) first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in SWD operation
-                                                 // before sending the select sequence, the SWD interface enters line reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Standard ARM command to switch SWJ-DP from SWD to JTAG operations
-const U8 _aData_SWDtoJTAG[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The SWD interface detects the 16-bit SWD-to-JTAG sequence only when it is in reset state.
-  0x3C, 0xE7,                                    // Send the 16-bit SWD-to-JTAG select sequence on SWDIOTMS: 0b0011 1100 1110 0111, MSb first.
-                                                 // This can be represented as 0x3CE7, transmitted MSb first or 0xE73C, transmitted LSb first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least five SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in JTAG
-                                                 // operation before sending the select sequence, the JTAG TAP enters the test-logic-reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Direction buffer
-const U8 _aDir_SWJDPSwitch[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF
-};
-
-// Buffer for receiving data from target. Needs to be big enough to hold data for above sequences
-U8 _aDataOut[18];
-// Acquiring stat time mark
-int _aStartTime;
-// Si Family ID value
-U16 _familyID;
-// Acquisition acknowledge location (magic number address)
-U32 _sramMagicNumberAddr;
-
-/*********************************************************************
-*       Local functions
-*********************************************************************/
-
-/*********************************************************************
-*  Checks function result
-*
-*  Return value
-*    true   O.K.
-*    false  Error
-*/
-int _CheckStatus(int status) {
-  if (status >= _STATUS_OK) {
-    return _STATUS_OK;
-  } else {
-    // Push error code to SWD that is it easier to debug the issues
-    //JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRAM_ERROR_ADDR);
-    //JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0xDEADBEEF);
-    return _STATUS_ERR;
-  }
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_ReadU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadMem(U32 address, U32* value) {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value);  // AP.DRW -> value
-  }
-
-  return status;
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_WriteU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteMem(U32 address, U32 value) {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value); // AP.DRW <- value
-  }
-
-  return status;
-}
-
-/*********************************************************************
-*  Polls for the expected bit-field value in given register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error/Timeout
-*/
-int _PollMem(U32 regAddr, U32 fieldMsk, U32 rsh, U32 expectedValue, U32 timeout, U32 sleepBetweenPolling) {
-  int status;
-  int t;
-  int tDelta;
-  U32 v;
-  tDelta = -1;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, regAddr); // AP.ADDR <- regAddr
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _STATUS_ERR;
-    t = JLINK_GetTime();
-    do {
-      // Sleep some time between polling: let CPU do its job and avoid too much garbage on SWD
-      if ((sleepBetweenPolling > 0) && (tDelta >= 0 /* not first iteration*/)) {
-        JLINK_SYS_Sleep(sleepBetweenPolling);
-      }
-      v = 0;
-      status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-      break;
-      }
-      if (((v & fieldMsk) >> rsh) == expectedValue) {
-        status = _STATUS_OK;
-        break;
-      }
-      tDelta = JLINK_GetTime() - t;
-    } while (tDelta < timeout);
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Clears any sticky errors which could be left from previous sessions.
-*  Otherwise only power-down-up cycle helps to restore DAP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _ClearStickyErrors() {
-  int status;
-  U32 abort_reg;
-  U32 abort_val;
-
-  if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-    // Power up DAP and clear sticky errors using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ, [5]:STICKYERR, [4]:STICKYCMP, [1]:STICKYORUN
-    // Note: for JTAG, sticky error bits are read-write enabled and writing ‘1’ to these bits clears associated sticky errors.
-    // For SWD, these bits are read-only and to clean the sticky errors, you should write to appropriate bits of DP.ABORT register
-    abort_reg = JLINK_CORESIGHT_DP_REG_CTRL_STAT;
-    abort_val = _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_STICKYERR | _DP_CTRL_STAT_STICKYCMP | _DP_CTRL_STAT_STICKYORUN; // 0x50000032
-  } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-    abort_reg = JLINK_CORESIGHT_DP_REG_ABORT;
-    abort_val = _AP_ABORT_ORUNERRCLR | _AP_ABORT_WDERRCLR | _AP_ABORT_STKERRCLR | _AP_ABORT_STKCMPCLR; // 0x0000001E
-  }
-
-  status = JLINK_CORESIGHT_WriteDAP(abort_reg, _ACC_DP, abort_val);
-
-  return status;
-}
-
-/*********************************************************************
-*  Handshake: wait for debug interface becomes enabled after device reset (tboot).
-*  In worst case, when the boot code performs application HASH verification,
-*  tboot is around 600ms and depends on CPU clock used by boot code.
-*  For PowerCycle, timeout depends on the design schematic and must be longer.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _Handshake(void) {
-  U32 v;
-  int tDelta;
-  int status;
-
-  status = _STATUS_ERR;
-  do {
-    if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-      JLINK_SWD_ReadWriteBits(&_aData_SWDtoJTAG[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-      JLINK_SWD_ReadWriteBits(&_aData_JTAGtoSWD[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    }
-    v = 0;
-    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, _ACC_DP, &v);
-    if ((v & _DP_IDCODE_MSK) == _DP_IDCODE_VAL) { // DAP is responsive if we can read IDCODE (0x6BA02477 for SWD or 0x6BA00477 for JTAG)
-      status = _STATUS_OK;
-      break;
-    }
-    tDelta = JLINK_GetTime() - _aStartTime;
-  } while (tDelta < _TIMEOUT_HANDSHAKE); // Timeout reached?
-
-  // clear any previous errors in advance
-  if (status == _STATUS_OK)
-  {
-    status = _ClearStickyErrors();
-  }
-  return status;
-}
-
-/*********************************************************************
-*  Initialize the Debug Port for programing operations.
-*  Accepts Access Port number as input: 0 – System AP; 1 – CM0+ AP; 2 – CM4 AP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _InitDAP(U8 apNum, U8 doPowerUp) {
-  int status;
-
-  status = _ClearStickyErrors();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  if (doPowerUp != 0) {
-    // Power up DAP using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _ACC_DP, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ); // 0x50000000
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-  }
-
-  // Select desired Access Port and set bank 0 in APACC space
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACC_DP, (apNum << _AP_SELECT_APSEL_RSH) ); // DP->SELECT.APSEL <- apNum
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Set CSW (DbgSwEnable=0, Prot=0x23, SPIDEN=0, Mode=0x0, TrInProg=0, DeviceEn=0, AddrInc=Auto-increment off, Size=Word (32 bits))
-  // Note: Set Prot bits in DAP CSW register, because of no access to CPU registers via M4 AP without these bits
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACC_AP, _DP_CSW_PROT_VAL | _DP_CSW_SIZE_WORD); // 0x23000002
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs hardware reset by toggling XRES pin
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _HardReset(void) {
-  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
-  JLINK_SYS_Sleep(50);      // Make sure that device recognizes the reset
-  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Performs software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-*  DAP communication must be established before this method call (e.g. use _Handshake + _InitDAP function)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _SoftReset() {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _AIRCR_ADDR); // AP.TAR <- @AIRCR (0xE000ED0C)
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Note: do not check OK/WAIT/FAULT ACKs for the data write phase since the target immediately reboots
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_AP_REG_DATA, (_AIRCR_VECTKEY_VAL | _AIRCR_SYSRESETREQ) ); // AP.DRW <- 0x05FA0004
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs either of:
-*    a. Hardware reset (XRES)
-*    b. Software reset (AIRCR.SYSRESETREQ)
-*    c. Software reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_Reset(U8 doXRES) {
-  int status;
-
-  if (doXRES != 0) {
-    status = _HardReset();
-  } else {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) == _STATUS_OK) {
-      // Initialize the Debug Port and select CM0+ Access Port (AP[1])
-      status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-      if (_CheckStatus(status) == _STATUS_OK) {
-       status = _SoftReset(); // AIRCR.SYSRESETREQ
-      }
-
-      // In worst case, if standard software reset via SYSRESETREQ failed, it may mean that the firmware did
-      // very bad things disabling the debug pins or AHB_AP access (anything behind the DAP).
-      // However, if we still can access DAP registers, the last thing we could try is to reset the target
-      // via DP->CTRL/STAT.CDBGRSTREQ. In MXS40, setting the CDBGRSTREQ bit will result in a System wide Debug
-      // DeepSleep reset, what resets both (CM0+ and CM4) cores.
-      // Note that CDBGRSTREQ will reset the target only at first attempt after the hardware reset (XRES or Power Cycle).
-      // You need to do the additional hardware reset manually before the acquisition sequence execution if the target
-      // stucked in 'bad' state and you already used the CDBGRSTREQ bit since the previous hardware reset.
-      // If such case happens and we managed to reset the target using CDBGRSTREQ,
-      // the next thing would be to halt the CPU as quickly as possible to prevent firmware to do the bad things again.
-      if (_CheckStatus(status) != _STATUS_OK) {
-        status = _Handshake();
-        if (_CheckStatus(status) == _STATUS_OK) {
-          JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_CDBGRSTREQ); // 0x54000000
-        }
-      }
-
-    }
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Enables debug and halts or resumes the CPU using the DHCSR register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _HaltResumeCPU(U8 haltNresume) {
-  int status;
-  U32 v;
-  int t;
-  int tDelta;
-  U32 dhcsrVal;
-  U32 shaltExpectedVal;
-
-  if (haltNresume == 0) { // Resume
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_DEBUGEN; // 0xA05F0001
-    shaltExpectedVal = 0;
-  } else { // Halt
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN; // 0xA05F0003
-    shaltExpectedVal = _DHCSR_S_HALT;
-  }
-
-  // Enable debug, and halt the CPU using the DHCSR register
-  status = _WriteMem(_DHCSR_ADDR, dhcsrVal); // _DHCSR_ADDR (0xE000EDF0) <- dhcsrVal
-
-  if (_CheckStatus(status) == _STATUS_OK) {
-    // Poll for S_HALT bit [17] in DHCSR register (@0xE000EDF0)
-    status = _PollMem(_DHCSR_ADDR, _DHCSR_S_HALT, 0, shaltExpectedVal, _TIMEOUT_HALT_CPU, 0);
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Obtain device family from ROM-table and select proper magic number address
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-
-int _DAP_AP_GetFamilyID(void) {
-  int status;
-  U32 v;
-  U32 i;
-  U32 romBaseAddr;
-  U32 pidr_0_3;
-  U32 pidr_4_7;
-
-  if (_familyID != _PSOC64_UNKNOWN_FAMILY) {
-    // divice family already determined
-    status = _STATUS_OK;
-  } else {
-    // select bank 15
-    v = (_AP_MYCORE << _AP_SELECT_APSEL_RSH) | 0xF0; // Current core AP, Bank 15
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_DP, v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_AP, &romBaseAddr); // Get Debug ROM Address
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    // check format of BASE register
-    if ((romBaseAddr & _BASE_FORMAT_MASK) == _BASE_FORMAT_MASK) {
-      romBaseAddr &= _BASE_ADDR_MASK;
-    } else {
-      status = _STATUS_ERR;
-      return status;
-    }
-    // Select bank 0
-    v = (_AP_MYCORE << _AP_SELECT_APSEL_RSH); // Current core AP, Bank 0
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_DP, v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-
-    // Read peripheral ID registers 0-3
-    pidr_0_3 = 0;
-    i = 0;
-    do {
-      status = _ReadMem(romBaseAddr + _PIDR0_ADDR + (i * 4), &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-        return status;
-      }
-      pidr_0_3 |= (v & 0x000000FF) << (i * 8);
-      i += 1;
-    } while (i < 4);
-
-    // Read peripheral ID registers 4-7
-    pidr_4_7 = 0;
-    i = 0;
-    do {
-      status = _ReadMem(romBaseAddr + _PIDR4_ADDR + (i * 4), &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-        return status;
-      }
-      pidr_4_7 |= (v & 0x000000FF) << (i * 8);
-      i += 1;
-    } while (i < 4);
-
-    // validate PIDR values and extract family ID
-    if (((pidr_0_3 & _PIDR_0_3_VALID_MASK) == _PIDR_0_3_VALID_VAL) && (pidr_4_7 == 0)) {
-      _familyID = pidr_0_3 & _FAMILY_ID_MASK;
-      if (_familyID == _PSOC64_2M_FAMILY) {
-        _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_2M_FAMILY;
-        return status;
-      }
-      if (_familyID == _PSOC64_512K_FAMILY) {
-        _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_512K_FAMILY;
-        return status;
-      }
-      _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_1M_FAMILY;
-    } else {
-      status = _STATUS_ERR;
-    }
-  }
-  return status;
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition in test mode:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Set TEST_MODE bit in TST_MODE SRSS register
-*    4. Wait for magic acknowledge
-*
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*    (2) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int _PSoC6_AcquireTestMode(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 OrgTIFSpeed;
-
-  // Make sure that J-Link is using a high target interface speed, so we can meet the timing requirements as per programming specifications
-  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
-  OrgTIFSpeed = JLINK_JTAG_Speed;
-  JLINK_JTAG_Speed = _TEST_MODE_SWD_SPEED;
-
-  // Preconfigure some CoreSight settings as time is not critical at this point
-  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP.
-  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call.
-  // Additionally, suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0");
-
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset
-  // It is critical for Test Mode acquisition, so stop and in case of failure
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Store time point after reset
-  _aStartTime = JLINK_GetTime();
-
-  // - 2 ----------------------------------------------------------------------
-  // Set TEST_MODE bit loop
-  do {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    // Initialize the Debug Port and select CM0-AP (AP[1])
-    status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-
-    // - 3 ----------------------------------------------------------------------
-    // Enter CPU into Test Mode, so it does not start the user application
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR); // Set TEST_MODE bit in TST_MODE SRSS register
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, _SRSS_TST_MODE_TEST_MODE);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    // Read RDBUFF to make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACC_DP, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-  } while ((_CheckStatus(status) != _STATUS_OK) && ((JLINK_GetTime() - _aStartTime) < _TIMEOUT_HANDSHAKE)); // Timeout reached?
-
-    // The steps above are time critical and must be executed without delays immediately after reset.
-    // No hurry for further steps - target already acquired in Test Mode
-
-    // Restore CORESIGHT settings (See beginning of this function call for more info) and restore original TIF speed
-    JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0");
-    JLINK_JTAG_Speed = OrgTIFSpeed;
-
-  // - 4 ----------------------------------------------------------------------
-  // Poll for magic acknowledge
-  do {
-    // do handshake if something went wrong
-    if (_CheckStatus(status) != _STATUS_OK) {
-      status = _Handshake();
-      if (_CheckStatus(status) != _STATUS_OK) {
-        continue;
-      }
-    }
-
-    // Get device family and select proper magic number address
-    status = _DAP_AP_GetFamilyID();
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-
-    // poll secure acquire magic acknowledge
-    status = _PollMem(_sramMagicNumberAddr, _SRAM_MAGIC_NUMBER_MSK, 0, _SRAM_MAGIC_NUMBER_VAL, _TIMEOUT_HANDSHAKE - (JLINK_GetTime() - _aStartTime), 1);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-  } while ((_CheckStatus(status) != _STATUS_OK) && ((JLINK_GetTime() - _aStartTime) < _TIMEOUT_HANDSHAKE)); // Timeout reached?
-
-  // Even magic number is not provided due to cyloader corruption
-  // CPU must be halted
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Clear TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0);
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs variety of PSoC 6 chip acquisition attempts:
-*    1. Acquire in Test Mode so the boot code will not start the application
-*    1.a. Using hardware pre-reset (XRES).
-*         This is recommended and the only 100% reliable method.
-*
-*    If above step failed, Test Mode acquisition is not possible because of
-*    Listen window is turned off or the debugger cannot meet timing requirements.
-*
-* ! Note that XRES connection is strongly required for the hardware reset.
-*   Otherwise, neither of above methods will work if the firmware does really "bad" things such as:
-*   - Repurposes the debug pins (intentionally or unintentionally)
-*   - Disables/Protects access ports and the Listen window is turned off or too short
-*   - Intentionally or unintentionally corrupts values in MMIO registers and the Listen window is turned off or too short
-*   In this case, there is no way for debugger to establish even basic communication with target
-*
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-
-int _PSoC6_Acquire(U32 resumeCPU) {
-  int status;
-  status = _STATUS_ERR;
-
-  // 1. Acquire PSoC 6 in Test Mode:
-  //   1.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-  //   1.2. Handshake + Init DAP
-  //   1.3. Set TEST_MODE bit in TST_MODE SRSS register
-  //   1.4. Wait for magic acknowledge
-  // Items 1.1 to 1.3 are time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_AcquireTestMode(1 /* "1" - do hardware pre-reset (XRES) */);
-
-  // Resume CPU that was halted above if it is required for caller
-  if ((_CheckStatus(status) == _STATUS_OK) && (resumeCPU != 0)) {
-    status = _HaltResumeCPU(0 /* "0" - resume */);
-  }
-
-  return _CheckStatus(status);
-}
-/*********************************************************************
-*       Global functions
-*********************************************************************/
-
-/*********************************************************************
-*  Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
-*  For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
-*  that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
-*  May also be used to specify the device name in case debugger does not pass it to the DLL.
-*
-*  Notes
-*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
-*    (2) Should only set some global DLL variables
-*/
-int ConfigTargetSettings(void) {
-  Report("*****************************************************************");
-  Report("JLinkScript: Start 'ConfigTargetSettings' for Cortex-M0+ of CYxx64xx");
-
-  JLINK_CORESIGHT_AddAP(_AP_SYS, CORESIGHT_CUSTOM_AP); // AP[0]  SYS-AP (used for chip acquisition sequence)
-  JLINK_CORESIGHT_AddAP(_AP_CM0, CORESIGHT_AHB_AP);    // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-  JLINK_CORESIGHT_AddAP(_AP_CM4, CORESIGHT_AHB_AP);    // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-  JLINK_CORESIGHT_IndexAHBAPToUse = _AP_MYCORE;        // AP-Index of AHB-AP to use for communication with core
-  CPU=CORTEX_M0;
-  // Clear family ID value
-  _familyID = _PSOC64_UNKNOWN_FAMILY;
-  Report("*****************************************************************");
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Replaces reset strategies of DLL.
-*  No matter what reset type is selected in the DLL, if this function is present, it will be called instead of the DLL internal reset.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int ResetTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode or using Alternate Method
-  // Note: Test Mode acquisition is time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition since DLL expects target CPU to be halted / in debug mode, when leaving ResetTarget function
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Enable DWT, ITM, TPIU, and ETM units by setting TRCENA bit in DEMCR register
-  status = _WriteMem(_DEMCR_ADDR, _DEMCR_TRCENA); // DEMCR (0xE000EDFC) <- TRCENA
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Replaces the target-CPU-auto-find procedure of the J-Link DLL.
-*  Useful for target CPUs that are not accessible by default and need some special steps
-*  to be executed before the normal debug probe connect procedure can be executed successfully.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) If target interface JTAG is used: JTAG chain has to be specified manually before leaving this function
-*        (meaning all devices and their TAP IDs have to be specified by the user).
-*        Also appropriate JTAG TAP number to communicate with during the debug session has to be manually specified in this function.
-*    (2) MUST NOT use any MEM_ API functions
-*    (3) Global DLL variable “CPU” MUST be set when implementing this function, so the DLL knows which CPU module to use internally.
-*/
-int InitTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode (a. ToggleXRES; b. Handshake; c. Init DAP; d. Set TEST_MODE bit in TST_MODE SRSS register)
-  // Sequence is time critical, so executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition to avoid further FW execution
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  JLINK_ExecCommand("SetETBIsPresent = 1"); // ETB is available
-
-  return status;
-}
-
-/*********************************************************************
-*  Called right after flash programming Usually used to restore initialized peripherals
-*  which have been used during the flash download like for example clocks or port pins
-*  (e.g. QSPI alternate function)
-*
-*  Notes / Limitations
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int HandleAfterFlashProg(void) {
-  int status;
-
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset.
-  // Otherwise, device remains acquired because the reset command sent by IDE after programming,
-  // calls ResetTarget function, which will acquire target again.
-  // This is required to start the application for normal execution and for "Attach" actions after programming.
-  status = _PSoC6_Reset(1); // "1" do XRES
-  return status;
-}
-
-/*************************** end of file ****************************/

Devices/Cypress/PSoC6/CYxx64xx_CM4.JLinkScript

@@ -1,30 +0,0 @@
-int ConfigTargetSettings(void) {
-  //
-  // Mark a specific memory region as memory type illegal
-  // in order to make sure that the software is not allowed to access these regions
-  // 
-  // Note: This does not work for J-Flash tool
-  //
-
-  // Exclude SFLASH regions
-  JLINK_ExecCommand("map region 0x16000000-0x160007FF XI"); // [SFLASH Start - User Data Start]
-  JLINK_ExecCommand("map region 0x16001000-0x160019FF XI"); // [User Data End - NAR Start]
-  JLINK_ExecCommand("map region 0x16001C00-0x160059FF XI"); // [NAR End - Public Key Start]
-  JLINK_ExecCommand("map region 0x16006600-0x16007BFF XI"); // [Public Key End - TOC2 Start]
-
-  // Exclude Cy Metadata
-  JLINK_ExecCommand("map region 0x90300000-0x903FFFFF XI"); // Cy Checksum
-  JLINK_ExecCommand("map region 0x90500000-0x905FFFFF XI"); // Cy Metadata
-}
-
-void InitTarget(void) {
-  Report("********************************************");
-  Report("JLinkScript: InitTarget for PSoC64 Cortex-M4");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);  // SYSAP
-  CORESIGHT_AddAP(1, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M0+ core
-  CORESIGHT_AddAP(2, CORESIGHT_AHB_AP);  // AHB-AP used to connect to M4 core
-  CORESIGHT_IndexAHBAPToUse = 2;
-  CPU=CORTEX_M4;
-  JLINK_ExecCommand("SetETBIsPresent = 1");
-  Report("********************************************");
-}

Devices/Cypress/PSoC6/CYxx64xx_CM4_tm.JLinkScript

@@ -1,839 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : CYxx64xx_CM4_tm.JLinkScript
-Purpose : J-Link script file for Cypress PSoC64-2M/1M/512K devices (CYB064xA, CYS064xA, CYB064x7 and CYB064x5)
-Literature:
-  [1] J-Link User Guide
-  [2] PSoC® 64 MCU Programming Specifications (Document Number: 002-31353)
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*       Constants (similar to defines)
-*********************************************************************/
-
-/* --- Misc. --- */
-__constant int _STATUS_OK                   = 0;  // Function return status: O.K.
-__constant int _STATUS_ERR                  = -1; // Function return status: Error
-__constant U32 _TIMEOUT_HANDSHAKE           = 30000; // For 30 seconds for secure device
-__constant U32 _TIMEOUT_HALT_CPU            = 300;
-__constant U32 _TEST_MODE_SWD_SPEED         = 4000;
-
-/* PSoC® 6 MCU definitions */
-__constant U32 _AP_SYS                      = 0; // AP[0]  SYS-AP (used for chip acquisition sequence)
-__constant U32 _AP_CM0                      = 1; // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-__constant U32 _AP_CM4                      = 2; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _AP_MYCORE                   = 2; // AP[2]  CM4 Core is used as the default for this script
-__constant U32 _DP_IDCODE_MSK               = 0xFFF00FFF; // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-__constant U32 _DP_IDCODE_VAL               = 0x6BA00477; // AP[2]  0x6BA02477 for SWD or 0x6BA00477 for JTAG
-__constant U32 _SRSS_TST_MODE_ADDR          = 0x40260100; // SRSS_TST_MODE: Test Mode Control Register
-__constant U32 _SRSS_TST_MODE_TEST_MODE     = (1 << 31);  // SRSS_TST_MODE.TEST_MODE (bit[31], 0x80000000): 1 - Indicates the chip is in test mode. 0 - Normal operation mode
-__constant U32 _SRAM_ERROR_ADDR             = 0x080002FC; // Address in SRAM for error code
-
-/* --- AP/DP registers --- */
-__constant U32 _ACC_DP                      = 0; // APnDP for DP access
-__constant U32 _ACC_AP                      = 1; // APnDP for AP access
-__constant U32 _AP_ABORT_ORUNERRCLR         = (1 << 4);   // AP->ABORT.ORUNERRCLR (bit[4], 0x00000010): Clears CTRL/STAT.STICKYORUN
-__constant U32 _AP_ABORT_WDERRCLR           = (1 << 3);   // AP->ABORT.WDERRCLR   (bit[3], 0x00000008): Clears CTRL/STAT.WDATAERR
-__constant U32 _AP_ABORT_STKERRCLR          = (1 << 2);   // AP->ABORT.STKERRCLR  (bit[2], 0x00000004): Clears CTRL/STAT.STICKYERR
-__constant U32 _AP_ABORT_STKCMPCLR          = (1 << 1);   // AP->ABORT.STKCMPCLR  (bit[1], 0x00000002): Clears CTRL/STAT.STICKYERR
-                                                          //                      (     |= 0x0000001E)
-__constant U32 _AP_SELECT_APSEL_RSH         = 24;         // AP->SELECT.APSEL (bits[31:24], 0xFF000000): Selects an AP
-__constant U32 _DP_CTRL_STAT_CSYSPWRUPREQ   = (1 << 30);  // DP->CTRL/STAT.CSYSPWRUPREQ (bit[30], 0x40000000): System powerup request
-__constant U32 _DP_CTRL_STAT_CDBGPRWUPREQ   = (1 << 28);  // DP->CTRL/STAT.CDBGPRWUPREQ (bit[28], 0x10000000): Debug powerup request
-__constant U32 _DP_CTRL_STAT_CDBGRSTREQ     = (1 << 26);  // DP->CTRL/STAT.CDBGRSTREQ   (bit[26], 0x04000000): Debug reset request
-__constant U32 _DP_CTRL_STAT_STICKYERR      = (1 << 5);   // DP->CTRL/STAT.STICKYERR    ( bit[5], 0x00000020): Error in AP transaction
-__constant U32 _DP_CTRL_STAT_STICKYCMP      = (1 << 4);   // DP->CTRL/STAT.STICKYCMP    ( bit[4], 0x00000010): Match on a pushed operations
-__constant U32 _DP_CTRL_STAT_STICKYORUN     = (1 << 1);   // DP->CTRL/STAT.STICKYORUN   ( bit[1], 0x00000002): Overrun detection
-                                                          //                                   |= 0x50000032
-__constant U32 _DP_CSW_PROT_VAL             = (0x23 << 24); // DP->CSW.Prot (bits[30:24], 0x23000000): Bus access protection control
-                                                            // Set to 0x23, otherwise no access to CPU registers via M4 AP
-__constant U32 _DP_CSW_SIZE_WORD            = (2 << 0);     // DP->CSW.Size (  bits[2:0], 0x00000002): Size of access <- Word (32-bits)
-                                                            //                         |= 0x23000002
-/* --- ARMv6-M & ARMv7-M --- */
-__constant U32 _AIRCR_ADDR                  = 0xE000ED0C;     // AIRCR: Application Interrupt and Reset Control Register
-__constant U32 _AIRCR_VECTKEY_VAL           = (0x05FA << 16); // AIRCR.VECTKEY       (bits[31:16], 0x05FA0000): Vector Key. The value 0x05FA must be written to this register
-__constant U32 _AIRCR_SYSRESETREQ           = (1 << 2);       // AIRCR.SYSRESETREQ   (     bit[2], 0x00000004): System Reset Request
-__constant U32 _DHCSR_ADDR                  = 0xE000EDF0;     // DHCSR: Debug Halting Control and Status Register
-__constant U32 _DHCSR_DBGKEY_VAL            = (0xA05F << 16); // DHCSR.DBGKEY    (bits[31:16], 0xA05F0000): Must write 0xA05F to DBGKEY to enable write accesses to bits[15:0]
-__constant U32 _DHCSR_S_HALT                = (1 << 17);      // DHCSR.S_HALT    (    bit[17], 0x00020000): Indicates whether the processor is in Debug state
-__constant U32 _DHCSR_C_HALT                = (1 << 1);       // DHCSR.C_HALT    (     bit[1], 0x00000002): Processor halt bit
-__constant U32 _DHCSR_C_DEBUGEN             = (1 << 0);       // DHCSR.C_DEBUGEN (     bit[0], 0x00000001): Halting debug enable bit
-                                                              //                 (DBGKEY|C_HALT|C_DEBUGEN = 0xA05F0003)
-__constant U32 _DEMCR_ADDR                  = 0xE000EDFC; // DEMCR: Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_TRCENA                = (1 << 24);  // DEMCR.TRCENA (bit[24], 0x01000000): Global enable for all DWT and ITM features
-
-// Secure magic
-__constant U32 _SRAM_MAGIC_NUMBER_VAL       = 0x12344321;  // Magic Number value
-__constant U32 _SRAM_MAGIC_NUMBER_MSK       = 0xFFFFFFFF;  // Magic Number mask
-
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_512K_FAMILY = 0x0803E004;
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_1M_FAMILY   = 0x08044804;
-__constant U32 _SRAM_MAGIC_NUMBER_ADDR_2M_FAMILY   = 0x080FE004;
-
-// Device family defines
-__constant U16 _PSOC64_UNKNOWN_FAMILY       = 0;
-__constant U16 _PSOC64_2M_FAMILY            = 0x102;
-__constant U16 _PSOC64_1M_FAMILY            = 0x100;
-__constant U16 _PSOC64_512K_FAMILY          = 0x105;
-
-// ROM table defines
-__constant U32 _BASE_ADDR_MASK               = 0xFFFFF000;
-__constant U32 _BASE_FORMAT_MASK             = 0x00000003;
-__constant U32 _PIDR0_ADDR                   = 0x00000FE0;
-__constant U32 _PIDR4_ADDR                   = 0x00000FD0;
-__constant U32 _PIDR_0_3_VALID_MASK          = 0x000FF000;
-__constant U32 _PIDR_0_3_VALID_VAL           = 0x000B4000;
-__constant U32 _FAMILY_ID_MASK               = 0x00000FFF;
-
-
-/*********************************************************************
-*       Static data
-*********************************************************************/
-
-// Standard ARM command to switch SWJ-DP from JTAG to SWD operations:
-const U8 _aData_JTAGtoSWD[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The JTAG interface detects only the 16-bit JTAG-to-SWD sequence starting from the test-logic-reset state.
-  0x9E, 0xE7,                                    // Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS: 0b0111 1001 1110 0111, most significant bit (MSb) first.
-                                                 // This can be represented as 0x79E7, transmitted MSB first or 0xE79E, transmitted least significant bit (LSb) first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in SWD operation
-                                                 // before sending the select sequence, the SWD interface enters line reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Standard ARM command to switch SWJ-DP from SWD to JTAG operations
-const U8 _aData_SWDtoJTAG[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least 50 SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that the current interface is in its reset state.
-                                                 // The SWD interface detects the 16-bit SWD-to-JTAG sequence only when it is in reset state.
-  0x3C, 0xE7,                                    // Send the 16-bit SWD-to-JTAG select sequence on SWDIOTMS: 0b0011 1100 1110 0111, MSb first.
-                                                 // This can be represented as 0x3CE7, transmitted MSb first or 0xE73C, transmitted LSb first.
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,      // Send at least five SWCLKTCK cycles with SWDIOTMS HIGH. This ensures that if SWJ-DP was already in JTAG
-                                                 // operation before sending the select sequence, the JTAG TAP enters the test-logic-reset state.
-  0x00, 0x00                                     // Make sure SWD is ready for a start bit (min. 2 clocks with SWDIO == LOW)
-};
-
-// Direction buffer
-const U8 _aDir_SWJDPSwitch[] = {
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF,
-  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
-  0xFF, 0xFF
-};
-
-// Buffer for receiving data from target. Needs to be big enough to hold data for above sequences
-U8 _aDataOut[18];
-// Acquiring stat time mark
-int _aStartTime;
-// Si Family ID value
-U16 _familyID;
-// Acquisition acknowledge location (magic number address)
-U32 _sramMagicNumberAddr;
-
-/*********************************************************************
-*       Local functions
-*********************************************************************/
-
-/*********************************************************************
-*  Checks function result
-*
-*  Return value
-*    true   O.K.
-*    false  Error
-*/
-int _CheckStatus(int status) {
-  if (status >= _STATUS_OK) {
-    return _STATUS_OK;
-  } else {
-    // Push error code to SWD that is it easier to debug the issues
-    //JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRAM_ERROR_ADDR);
-    //JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0xDEADBEEF);
-    return _STATUS_ERR;
-  }
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_ReadU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _ReadMem(U32 address, U32* value) {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value);  // AP.DRW -> value
-  }
-
-  return status;
-}
-
-/*********************************************************************
-*  Writes U32 value to provided memory address.
-*  Used instead of JLINK_MEM_WriteU32 to validate transaction status
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _WriteMem(U32 address, U32 value) {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, address); // AP.TAR <- address
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, value); // AP.DRW <- value
-  }
-
-  return status;
-}
-
-/*********************************************************************
-*  Polls for the expected bit-field value in given register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error/Timeout
-*/
-int _PollMem(U32 regAddr, U32 fieldMsk, U32 rsh, U32 expectedValue, U32 timeout, U32 sleepBetweenPolling) {
-  int status;
-  int t;
-  int tDelta;
-  U32 v;
-  tDelta = -1;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, regAddr); // AP.ADDR <- regAddr
-  if (_CheckStatus(status) == _STATUS_OK) {
-    status = _STATUS_ERR;
-    t = JLINK_GetTime();
-    do {
-      // Sleep some time between polling: let CPU do its job and avoid too much garbage on SWD
-      if ((sleepBetweenPolling > 0) && (tDelta >= 0 /* not first iteration*/)) {
-        JLINK_SYS_Sleep(sleepBetweenPolling);
-      }
-      v = 0;
-      status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-      break;
-      }
-      if (((v & fieldMsk) >> rsh) == expectedValue) {
-        status = _STATUS_OK;
-        break;
-      }
-      tDelta = JLINK_GetTime() - t;
-    } while (tDelta < timeout);
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Clears any sticky errors which could be left from previous sessions.
-*  Otherwise only power-down-up cycle helps to restore DAP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _ClearStickyErrors() {
-  int status;
-  U32 abort_reg;
-  U32 abort_val;
-
-  if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-    // Power up DAP and clear sticky errors using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ, [5]:STICKYERR, [4]:STICKYCMP, [1]:STICKYORUN
-    // Note: for JTAG, sticky error bits are read-write enabled and writing ‘1’ to these bits clears associated sticky errors.
-    // For SWD, these bits are read-only and to clean the sticky errors, you should write to appropriate bits of DP.ABORT register
-    abort_reg = JLINK_CORESIGHT_DP_REG_CTRL_STAT;
-    abort_val = _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_STICKYERR | _DP_CTRL_STAT_STICKYCMP | _DP_CTRL_STAT_STICKYORUN; // 0x50000032
-  } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-    abort_reg = JLINK_CORESIGHT_DP_REG_ABORT;
-    abort_val = _AP_ABORT_ORUNERRCLR | _AP_ABORT_WDERRCLR | _AP_ABORT_STKERRCLR | _AP_ABORT_STKCMPCLR; // 0x0000001E
-  }
-
-  status = JLINK_CORESIGHT_WriteDAP(abort_reg, _ACC_DP, abort_val);
-
-  return status;
-}
-
-/*********************************************************************
-*  Handshake: wait for debug interface becomes enabled after device reset (tboot).
-*  In worst case, when the boot code performs application HASH verification,
-*  tboot is around 600ms and depends on CPU clock used by boot code.
-*  For PowerCycle, timeout depends on the design schematic and must be longer.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _Handshake(void) {
-  U32 v;
-  int tDelta;
-  int status;
-
-  status = _STATUS_ERR;
-  do {
-    if (JLINK_ActiveTIF == JLINK_TIF_JTAG) {
-      JLINK_SWD_ReadWriteBits(&_aData_SWDtoJTAG[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    } else { // JLINK_ActiveTIF == JLINK_TIF_SWD
-      JLINK_SWD_ReadWriteBits(&_aData_JTAGtoSWD[0], &_aDir_SWJDPSwitch[0], &_aDataOut[0], 18 * 8);
-    }
-    v = 0;
-    JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_IDCODE, _ACC_DP, &v);
-    if ((v & _DP_IDCODE_MSK) == _DP_IDCODE_VAL) { // DAP is responsive if we can read IDCODE (0x6BA02477 for SWD or 0x6BA00477 for JTAG)
-      status = _STATUS_OK;
-      break;
-    }
-    tDelta = JLINK_GetTime() - _aStartTime;
-  } while (tDelta < _TIMEOUT_HANDSHAKE); // Timeout reached?
-
-  // clear any previous errors in advance
-  if (status == _STATUS_OK)
-  {
-    status = _ClearStickyErrors();
-  }
-  return status;
-}
-
-/*********************************************************************
-*  Initialize the Debug Port for programing operations.
-*  Accepts Access Port number as input: 0 – System AP; 1 – CM0+ AP; 2 – CM4 AP.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _InitDAP(U8 apNum, U8 doPowerUp) {
-  int status;
-
-  status = _ClearStickyErrors();
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  if (doPowerUp != 0) {
-    // Power up DAP using DP.CTRL/STAT: [30]:CSYSPWRUPREQ, [28]:CDBGPWRUPREQ
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _ACC_DP, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ); // 0x50000000
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-  }
-
-  // Select desired Access Port and set bank 0 in APACC space
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, _ACC_DP, (apNum << _AP_SELECT_APSEL_RSH) ); // DP->SELECT.APSEL <- apNum
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Set CSW (DbgSwEnable=0, Prot=0x23, SPIDEN=0, Mode=0x0, TrInProg=0, DeviceEn=0, AddrInc=Auto-increment off, Size=Word (32 bits))
-  // Note: Set Prot bits in DAP CSW register, because of no access to CPU registers via M4 AP without these bits
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_CTRL, _ACC_AP, _DP_CSW_PROT_VAL | _DP_CSW_SIZE_WORD); // 0x23000002
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs hardware reset by toggling XRES pin
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-int _HardReset(void) {
-  JLINK_JTAG_ResetPin = 0;  // nRESET == LOW
-  JLINK_SYS_Sleep(50);      // Make sure that device recognizes the reset
-  JLINK_JTAG_ResetPin = 1;  // nRESET == HIGH
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Performs software reset using SYSRESETREQ bit in the AIRCR (Application Interrupt and Reset Control Register)
-*  DAP communication must be established before this method call (e.g. use _Handshake + _InitDAP function)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _SoftReset() {
-  int status;
-
-  status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _AIRCR_ADDR); // AP.TAR <- @AIRCR (0xE000ED0C)
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Note: do not check OK/WAIT/FAULT ACKs for the data write phase since the target immediately reboots
-  JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_AP_REG_DATA, (_AIRCR_VECTKEY_VAL | _AIRCR_SYSRESETREQ) ); // AP.DRW <- 0x05FA0004
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs either of:
-*    a. Hardware reset (XRES)
-*    b. Software reset (AIRCR.SYSRESETREQ)
-*    c. Software reset (DP->CTRL/STAT.CDBGRSTREQ)
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _PSoC6_Reset(U8 doXRES) {
-  int status;
-
-  if (doXRES != 0) {
-    status = _HardReset();
-  } else {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) == _STATUS_OK) {
-      // Initialize the Debug Port and select CM4 Access Port (AP[2])
-      status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-      if (_CheckStatus(status) == _STATUS_OK) {
-       status = _SoftReset(); // AIRCR.SYSRESETREQ
-      }
-
-      // In worst case, if standard software reset via SYSRESETREQ failed, it may mean that the firmware did
-      // very bad things disabling the debug pins or AHB_AP access (anything behind the DAP).
-      // However, if we still can access DAP registers, the last thing we could try is to reset the target
-      // via DP->CTRL/STAT.CDBGRSTREQ. In MXS40, setting the CDBGRSTREQ bit will result in a System wide Debug
-      // DeepSleep reset, what resets both (CM0+ and CM4) cores.
-      // Note that CDBGRSTREQ will reset the target only at first attempt after the hardware reset (XRES or Power Cycle).
-      // You need to do the additional hardware reset manually before the acquisition sequence execution if the target
-      // stucked in 'bad' state and you already used the CDBGRSTREQ bit since the previous hardware reset.
-      // If such case happens and we managed to reset the target using CDBGRSTREQ,
-      // the next thing would be to halt the CPU as quickly as possible to prevent firmware to do the bad things again.
-      if (_CheckStatus(status) != _STATUS_OK) {
-        status = _Handshake();
-        if (_CheckStatus(status) == _STATUS_OK) {
-          JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_CTRL_STAT, _DP_CTRL_STAT_CSYSPWRUPREQ | _DP_CTRL_STAT_CDBGPRWUPREQ | _DP_CTRL_STAT_CDBGRSTREQ); // 0x54000000
-        }
-      }
-
-    }
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Enables debug and halts or resumes the CPU using the DHCSR register
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-int _HaltResumeCPU(U8 haltNresume) {
-  int status;
-  U32 v;
-  int t;
-  int tDelta;
-  U32 dhcsrVal;
-  U32 shaltExpectedVal;
-
-  if (haltNresume == 0) { // Resume
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_DEBUGEN; // 0xA05F0001
-    shaltExpectedVal = 0;
-  } else { // Halt
-    dhcsrVal = _DHCSR_DBGKEY_VAL | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN; // 0xA05F0003
-    shaltExpectedVal = _DHCSR_S_HALT;
-  }
-
-  // Enable debug, and halt the CPU using the DHCSR register
-  status = _WriteMem(_DHCSR_ADDR, dhcsrVal); // _DHCSR_ADDR (0xE000EDF0) <- dhcsrVal
-
-  if (_CheckStatus(status) == _STATUS_OK) {
-    // Poll for S_HALT bit [17] in DHCSR register (@0xE000EDF0)
-    status = _PollMem(_DHCSR_ADDR, _DHCSR_S_HALT, 0, shaltExpectedVal, _TIMEOUT_HALT_CPU, 0);
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Obtain device family from ROM-table and select proper magic number address
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*/
-
-int _DAP_AP_GetFamilyID(void) {
-  int status;
-  U32 v;
-  U32 i;
-  U32 romBaseAddr;
-  U32 pidr_0_3;
-  U32 pidr_4_7;
-
-  if (_familyID != _PSOC64_UNKNOWN_FAMILY) {
-    // divice family already determined
-    status = _STATUS_OK;
-  } else {
-    // select bank 15
-    v = (_AP_MYCORE << _AP_SELECT_APSEL_RSH) | 0xF0; // Current core AP, Bank 15
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_DP, v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_AP, &romBaseAddr); // Get Debug ROM Address
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-    // check format of BASE register
-    if ((romBaseAddr & _BASE_FORMAT_MASK) == _BASE_FORMAT_MASK) {
-      romBaseAddr &= _BASE_ADDR_MASK;
-    } else {
-      status = _STATUS_ERR;
-      return status;
-    }
-    // Select bank 0
-    v = (_AP_MYCORE << _AP_SELECT_APSEL_RSH); // Current core AP, Bank 0
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ROM, _ACC_DP, v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      return status;
-    }
-
-    // Read peripheral ID registers 0-3
-    pidr_0_3 = 0;
-    i = 0;
-    do {
-      status = _ReadMem(romBaseAddr + _PIDR0_ADDR + (i * 4), &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-        return status;
-      }
-      pidr_0_3 |= (v & 0x000000FF) << (i * 8);
-      i += 1;
-    } while (i < 4);
-
-    // Read peripheral ID registers 4-7
-    pidr_4_7 = 0;
-    i = 0;
-    do {
-      status = _ReadMem(romBaseAddr + _PIDR4_ADDR + (i * 4), &v);
-      if (_CheckStatus(status) != _STATUS_OK) {
-        return status;
-      }
-      pidr_4_7 |= (v & 0x000000FF) << (i * 8);
-      i += 1;
-    } while (i < 4);
-
-    // validate PIDR values and extract family ID
-    if (((pidr_0_3 & _PIDR_0_3_VALID_MASK) == _PIDR_0_3_VALID_VAL) && (pidr_4_7 == 0)) {
-      _familyID = pidr_0_3 & _FAMILY_ID_MASK;
-      if (_familyID == _PSOC64_2M_FAMILY) {
-        _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_2M_FAMILY;
-        return status;
-      }
-      if (_familyID == _PSOC64_512K_FAMILY) {
-        _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_512K_FAMILY;
-        return status;
-      }
-      _sramMagicNumberAddr = _SRAM_MAGIC_NUMBER_ADDR_1M_FAMILY;
-    } else {
-      status = _STATUS_ERR;
-    }
-  }
-  return status;
-}
-
-/*********************************************************************
-*  Performs PSoC 6 chip acquisition in test mode:
-*    1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-*    2. Handshake + Init DAP
-*    3. Set TEST_MODE bit in TST_MODE SRSS register
-*    4. Wait for magic acknowledge
-*
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*    (2) __probe attribute specifies that this function is executed in the J-Link firmware rather than on the PC side,
-*        so changes to global variables may only be temporarily valid inside this function (not guaranteed to be valid later)
-*/
-__probe int _PSoC6_AcquireTestMode(U8 doXRES) {
-  int status;
-  U32 v;
-  U32 OrgTIFSpeed;
-
-  // Make sure that J-Link is using a high target interface speed, so we can meet the timing requirements as per programming specifications
-  // Might be necessary for some IDEs that select a very slow interface speed by default and do not allow to change this
-  OrgTIFSpeed = JLINK_JTAG_Speed;
-  JLINK_JTAG_Speed = _TEST_MODE_SWD_SPEED;
-
-  // Preconfigure some CoreSight settings as time is not critical at this point
-  // E.g. by default, when executing DAP API calls from within the firmware, J-Link will do a retry of the DAP transfer for some interfaces, if we got an invalid response from the DAP.
-  // As this costs valuable time here, we temporarily disable this behavior and restore it at the end of the call.
-  // Additionally, suppress output of the JTAG/SWD switching sequence init at the end of the CORESIGHT_Configure() call, as we do not need it and it only costs time
-  JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=0;PerformTIFInit=0");
-
-  // - 1 ----------------------------------------------------------------------
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) pre-reset
-  // It is critical for Test Mode acquisition, so stop and in case of failure
-  status = _PSoC6_Reset(doXRES);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-  // Store time point after reset
-  _aStartTime = JLINK_GetTime();
-
-  // - 2 ----------------------------------------------------------------------
-  // Set TEST_MODE bit loop
-  do {
-    // Handshake: wait for debug interface becomes enabled after device reset
-    status = _Handshake();
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    // Initialize the Debug Port and select CM0-AP (AP[1])
-    status = _InitDAP(_AP_MYCORE, 1 /* "1" - do power up request */);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-
-    // - 3 ----------------------------------------------------------------------
-    // Enter CPU into Test Mode, so it does not start the user application
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR); // Set TEST_MODE bit in TST_MODE SRSS register
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    status = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, _SRSS_TST_MODE_TEST_MODE);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-    // Read RDBUFF to make sure that the last AP write actually happens as SW-DP may buffer/delay it until next DAP access
-    status = JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_DP_REG_RDBUF, _ACC_DP, &v);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-  } while ((_CheckStatus(status) != _STATUS_OK) && ((JLINK_GetTime() - _aStartTime) < _TIMEOUT_HANDSHAKE)); // Timeout reached?
-
-    // The steps above are time critical and must be executed without delays immediately after reset.
-    // No hurry for further steps - target already acquired in Test Mode
-
-    // Restore CORESIGHT settings (See beginning of this function call for more info) and restore original TIF speed
-    JLINK_CORESIGHT_Configure("RetryOnInvalDAPResp=1;PerformTIFInit=0");
-    JLINK_JTAG_Speed = OrgTIFSpeed;
-
-  // - 4 ----------------------------------------------------------------------
-  // Poll for magic acknowledge
-  do {
-    // do handshake if something went wrong
-    if (_CheckStatus(status) != _STATUS_OK) {
-      status = _Handshake();
-      if (_CheckStatus(status) != _STATUS_OK) {
-        continue;
-      }
-    }
-
-    // Get device family and select proper magic number address
-    status = _DAP_AP_GetFamilyID();
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-
-    // poll secure acquire magic acknowledge
-    status = _PollMem(_sramMagicNumberAddr, _SRAM_MAGIC_NUMBER_MSK, 0, _SRAM_MAGIC_NUMBER_VAL, _TIMEOUT_HANDSHAKE - (JLINK_GetTime() - _aStartTime), 1);
-    if (_CheckStatus(status) != _STATUS_OK) {
-      continue;
-    }
-  } while ((_CheckStatus(status) != _STATUS_OK) && ((JLINK_GetTime() - _aStartTime) < _TIMEOUT_HANDSHAKE)); // Timeout reached?
-
-  // Even magic number is not provided due to cyloader corruption
-  // CPU must be halted
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Clear TEST_MODE bit in TST_MODE SRSS register
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACC_AP, _SRSS_TST_MODE_ADDR);
-  JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACC_AP, 0);
-  // Halt CPU again afler clear TEST_MODE bit
-  status = _HaltResumeCPU(1 /* "1" - halt */);
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Performs variety of PSoC 6 chip acquisition attempts:
-*    1. Acquire in Test Mode so the boot code will not start the application
-*    1.a. Using hardware pre-reset (XRES).
-*         This is recommended and the only 100% reliable method.
-*
-*    If above step failed, Test Mode acquisition is not possible because of
-*    Listen window is turned off or the debugger cannot meet timing requirements.
-*
-* ! Note that XRES connection is strongly required for the hardware reset.
-*   Otherwise, neither of above methods will work if the firmware does really "bad" things such as:
-*   - Repurposes the debug pins (intentionally or unintentionally)
-*   - Disables/Protects access ports and the Listen window is turned off or too short
-*   - Intentionally or unintentionally corrupts values in MMIO registers and the Listen window is turned off or too short
-*   In this case, there is no way for debugger to establish even basic communication with target
-*
-*  Refer PSoC 6 MCU Programming Specifications: 002-15554 http://www.cypress.com/file/385671/download
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) Must not use any high-level functions as it is also called from InitTarget() and uses non-standard APs etc.
-*/
-
-int _PSoC6_Acquire(U32 resumeCPU) {
-  int status;
-  status = _STATUS_ERR;
-
-  // 1. Acquire PSoC 6 in Test Mode:
-  //   1.1. Do hardware (XRES) or one of the software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset
-  //   1.2. Handshake + Init DAP
-  //   1.3. Set TEST_MODE bit in TST_MODE SRSS register
-  //   1.4. Wait for magic acknowledge
-  // Items 1.1 to 1.3 are time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_AcquireTestMode(1 /* "1" - do hardware pre-reset (XRES) */);
-
-  // Resume CPU that was halted above if it is required for caller
-  if ((_CheckStatus(status) == _STATUS_OK) && (resumeCPU != 0)) {
-    status = _HaltResumeCPU(0 /* "0" - resume */);
-  }
-
-  return _CheckStatus(status);
-}
-/*********************************************************************
-*       Global functions
-*********************************************************************/
-
-/*********************************************************************
-*  Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
-*  For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
-*  that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
-*  May also be used to specify the device name in case debugger does not pass it to the DLL.
-*
-*  Notes
-*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
-*    (2) Should only set some global DLL variables
-*/
-int ConfigTargetSettings(void) {
-  Report("*****************************************************************");
-  Report("JLinkScript: Start 'ConfigTargetSettings' for Cortex-M4 of CYxx64xx");
-
-  JLINK_CORESIGHT_AddAP(_AP_SYS, CORESIGHT_CUSTOM_AP); // AP[0]  SYS-AP (used for chip acquisition sequence)
-  JLINK_CORESIGHT_AddAP(_AP_CM0, CORESIGHT_AHB_AP);    // AP[1]  CM0-AP (used for J-Link communication with Cortex-M0 core)
-  JLINK_CORESIGHT_AddAP(_AP_CM4, CORESIGHT_AHB_AP);    // AP[2]  CM4-AP (used for J-Link communication with Cortex-M4 core)
-  JLINK_CORESIGHT_IndexAHBAPToUse = _AP_MYCORE;        // AP-Index of AHB-AP to use for communication with core
-  CPU=CORTEX_M4;
-  // Clear family ID value
-  _familyID = _PSOC64_UNKNOWN_FAMILY;
-  Report("*****************************************************************");
-  return _STATUS_OK;
-}
-
-/*********************************************************************
-*  Replaces reset strategies of DLL.
-*  No matter what reset type is selected in the DLL, if this function is present, it will be called instead of the DLL internal reset.
-*
-*  Return value
-*    >= 0  O.K.
-*    <  0  Error
-*
-*  Notes
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int ResetTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode or using Alternate Method
-  // Note: Test Mode acquisition is time critical, so entire function executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition since DLL expects target CPU to be halted / in debug mode, when leaving ResetTarget function
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  // Enable DWT, ITM, TPIU, and ETM units by setting TRCENA bit in DEMCR register
-  status = _WriteMem(_DEMCR_ADDR, _DEMCR_TRCENA); // DEMCR (0xE000EDFC) <- TRCENA
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  return _CheckStatus(status);
-}
-
-/*********************************************************************
-*  Replaces the target-CPU-auto-find procedure of the J-Link DLL.
-*  Useful for target CPUs that are not accessible by default and need some special steps
-*  to be executed before the normal debug probe connect procedure can be executed successfully.
-*
-*  Return value
-*    >= 0:  O.K.
-*     < 0:  Error
-*
-*  Notes
-*    (1) If target interface JTAG is used: JTAG chain has to be specified manually before leaving this function
-*        (meaning all devices and their TAP IDs have to be specified by the user).
-*        Also appropriate JTAG TAP number to communicate with during the debug session has to be manually specified in this function.
-*    (2) MUST NOT use any MEM_ API functions
-*    (3) Global DLL variable “CPU” MUST be set when implementing this function, so the DLL knows which CPU module to use internally.
-*/
-int InitTarget(void) {
-  int status;
-
-  // Acquire PSoC 6 in Test Mode (a. ToggleXRES; b. Handshake; c. Init DAP; d. Set TEST_MODE bit in TST_MODE SRSS register)
-  // Sequence is time critical, so executed in J-Link firmware and requires __probe attribute for caller
-  status = _PSoC6_Acquire(0); // "0" - Do not resume CPU that is halted during acquisition to avoid further FW execution
-  if (_CheckStatus(status) != _STATUS_OK) {
-    return status;
-  }
-
-  JLINK_ExecCommand("SetETBIsPresent = 1"); // ETB is available
-
-  return status;
-}
-
-/*********************************************************************
-*  Called right after flash programming Usually used to restore initialized peripherals
-*  which have been used during the flash download like for example clocks or port pins
-*  (e.g. QSPI alternate function)
-*
-*  Notes / Limitations
-*    (1) DLL expects target CPU to be halted / in debug mode, when leaving this function
-*    (2) May use MEM_ API functions
-*/
-int HandleAfterFlashProg(void) {
-  int status;
-
-  // Do hardware (XRES) of software (AIRCR.SYSRESETREQ or DP->CTRL/STAT.CDBGRSTREQ) reset.
-  // Otherwise, device remains acquired because the reset command sent by IDE after programming,
-  // calls ResetTarget function, which will acquire target again.
-  // This is required to start the application for normal execution and for "Attach" actions after programming.
-  status = _PSoC6_Reset(1); // "1" do XRES
-  return status;
-}
-
-/*************************** end of file ****************************/

Devices/Cypress/PSoC6/Readme_Cypress.txt

@@ -1,2 +0,0 @@
-The Cypress devices support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Cypress only.
-For support, please contact: cytechsupport@cypress.com

Devices/Cypress/PSoC6/known_issues.txt

@@ -1,14 +0,0 @@
----Known issues for Cypress Segger DFP-------
-
-ID:PROGTOOLS-98
-Issue: Segger J-Link Commander and J-Flash Lite tools cannot read and do not write eFuse bits correctly. These tools do not fill in gaps in the hex file with the correct values for eFuse bits, and use a different read technique than the Segger J-Flash tool.
-Workaround: Use the Segger J-Flash tool. To program eFuse bits with J-Link Commander and J-Flash Lite tools, manually edit the hex file so that the eFuse region (0x90700000-0x907003FF) is filled in with data. Fuses, which must not be touched, should be filled with the 0xFF (ignore) value in that hex file.
-
-ID:PROGTOOLS-2274
-Issue: Incorrect behaviour (invalid RAM size, erase operation failures) might be observed in J-Flash tool while using PSoC 64 MCU devices after changing a target device from CM0+ to CM4. It is caused by the fact that J-Flash continues to work via CM0+ core but uses RAM region which is dedicated to CM4 core. No reconnection happens automatically after the changing of core.
-Workaround: Perform a disconnecting before changing the MCU core.
-
----Known limitations for Cypress Segger DFP-------
-
-ID:None
-The recommended targets (aliases) for PSoC 6 devices in SEGGER tools have '_tm' suffix (for example CY8C6xA_CM0P_tm) and uses Cypress Test Mode connection method. Please use them for programming to avoid potential issues with the device connection by debugger when using SEGGER's default acquisition method (aliases without '_tm' suffix).

Devices/Cypress/PSoC6/version.dat

@@ -1 +0,0 @@
-2.2.0.87

Devices/Infineon/Readme.txt

@@ -1,2 +0,0 @@
-Infineon Technologies TLE98xy series support comes without any warranty and support from SEGGER Microcontroller GmbH. Support is provided via Infineon Technologies only.
-For support, please contact: kay.claussen@infineon.com

Devices/NXP/iMX6SX/iMX6SX_CortexA9.JLinkScript

@@ -1,53 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*        Solutions for real time microcontroller applications        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                                                                    *
-* Internet: www.segger.com Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-----------------------------------------------------------------------
-Purpose : 
----------------------------END-OF-HEADER------------------------------
-*/
-
-/*********************************************************************
-*
-*       ResetTarget
-*/
-void ResetTarget(void) {
-  // In case cores 1-3 are reset, we do nothing, 
-  //  as we would lose connection to these cores, when resetting the device
-  //  as a reset disables the clock to them.
-}
-
-/*********************************************************************
-*
-*       InitTarget
-*/
-void InitTarget(void) {
-  int WordAcc;
-  int v;
-  
-  JTAG_Reset();                                                                 // Perform TAP reset and J-Link JTAG auto-detection
-  if (JTAG_TotalIRLen == 5) {                                                   // Freescale System JTAG Controller (SJC) in MOD 1 detected?
-    JTAG_TRSTPin = 0;                                                           // Set JTAG_MOD to 0 in order to set Freescale System JTAG Controller (SJC) MOD to 0 ("Daisy chain ALL")
-    SYS_Sleep(10);                                                              // Give pin some time to get low
-  }
-  Report("******************************************************");
-  Report("J-Link script: iMX6 SoloX Cortex-A9 core J-Link script");
-  Report("******************************************************");
-  JLINK_CORESIGHT_Configure("IRPre=4;DRPre=1;IRPost=9;DRPost=2;IRLenDevice=4");
-  CPU = CORTEX_A9;                                                              // Pre-select that we have a Cortex-A9 connected
-  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
-  CORESIGHT_CoreBaseAddr = 0x02150000;
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
-  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
-  CORESIGHT_IndexAPBAPToUse = 1;
-  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
-  JTAG_SetDeviceId(1, 0x4BA00477);  // 4-bits IRLen
-  JTAG_SetDeviceId(2, 0x00000001);  // 5-bits IRLen
-  JTAG_SetDeviceId(3, 0x0891C01D);  // 4-bits IRLen
-}

Devices/NXP/iMX6SX/iMX6SX_CortexM4.JLinkScript

@@ -1,47 +0,0 @@
-/*********************************************************************
-*                    SEGGER Microcontroller GmbH                     *
-*        Solutions for real time microcontroller applications        *
-**********************************************************************
-*                                                                    *
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                                                                    *
-* Internet: www.segger.com Support: support@segger.com               *
-*                                                                    *
-**********************************************************************
-----------------------------------------------------------------------
-Purpose : 
----------------------------END-OF-HEADER------------------------------
-*/
-
-/*********************************************************************
-*
-*       ResetTarget
-*/
-void ResetTarget(void) {
-  // In case cores 1-3 are reset, we do nothing, 
-  //  as we would lose connection to these cores, when resetting the device
-  //  as a reset disables the clock to them.
-}
-
-/*********************************************************************
-*
-*       InitTarget
-*/
-void InitTarget(void) {
-  int WordAcc;
-  int v;
-
-  Report("******************************************************");
-  Report("J-Link script: iMX6 SoloX Cortex-M4 core J-Link script");
-  Report("******************************************************");
-  JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=13;DRPost=3;IRLenDevice=4");
-  CPU = CORTEX_M4;                                                              // Pre-select that we have a Cortex-A5 connected
-  JTAG_AllowTAPReset = 1;                                                       // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
-  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
-  CORESIGHT_IndexAHBAPToUse = 0;
-  JTAG_SetDeviceId(0, 0x4BA00477);  // 4-bits IRLen
-  JTAG_SetDeviceId(1, 0x4BA00477);  // 4-bits IRLen
-  JTAG_SetDeviceId(2, 0x00000001);  // 5-bits IRLen
-  JTAG_SetDeviceId(3, 0x0891C01D);  // 4-bits IRLen
-}

Devices/NXP/iMX6UL/NXP_iMX6ULL.JLinkScript

@@ -1,35 +0,0 @@
-/*********************************************************************
-*            (c) 1995 - 2018 SEGGER Microcontroller GmbH             *
-*                        The Embedded Experts                        *
-*                           www.segger.com                           *
-**********************************************************************
-
--------------------------- END-OF-HEADER -----------------------------
-
-File    : NXP_iMX6ULL.JLinkScript
-Purpose : Script file for iMX6 ULL series devices
-Literature:
-  [1]  J-Link User Guide
-
-Additional information:
-  For more information about public functions that can be implemented in order to customize J-Link actions, please refer to [1]
-*/
-
-/*********************************************************************
-*
-*       ConfigTargetSettings
-*/
-int ConfigTargetSettings(void) {
-  //
-  // The i.MX6ULL series does not like scanning the AP map because accessing
-  // a non-existing AP causes the whole DAP to crash and hang until power cycle
-  // Therefore, we manually setup the AP map so the J-Link SW skips the scanning
-  //
-  Report("J-Link script: Setting up AP map");
-  CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
-  CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
-  CORESIGHT_IndexAPBAPToUse = 1;
-  return 0;
-}
-
-/*************************** end of file ****************************/