iMX6SX_CortexA9.JLinkScript 2.7 KB

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  1. /*********************************************************************
  2. * SEGGER Microcontroller GmbH *
  3. * Solutions for real time microcontroller applications *
  4. **********************************************************************
  5. * *
  6. * (c) 1995 - 2018 SEGGER Microcontroller GmbH *
  7. * *
  8. * Internet: www.segger.com Support: support@segger.com *
  9. * *
  10. **********************************************************************
  11. ----------------------------------------------------------------------
  12. Purpose :
  13. ---------------------------END-OF-HEADER------------------------------
  14. */
  15. /*********************************************************************
  16. *
  17. * ResetTarget
  18. */
  19. void ResetTarget(void) {
  20. // In case cores 1-3 are reset, we do nothing,
  21. // as we would lose connection to these cores, when resetting the device
  22. // as a reset disables the clock to them.
  23. }
  24. /*********************************************************************
  25. *
  26. * InitTarget
  27. */
  28. void InitTarget(void) {
  29. int WordAcc;
  30. int v;
  31. JTAG_Reset(); // Perform TAP reset and J-Link JTAG auto-detection
  32. if (JTAG_TotalIRLen == 5) { // Freescale System JTAG Controller (SJC) in MOD 1 detected?
  33. JTAG_TRSTPin = 0; // Set JTAG_MOD to 0 in order to set Freescale System JTAG Controller (SJC) MOD to 0 ("Daisy chain ALL")
  34. SYS_Sleep(10); // Give pin some time to get low
  35. }
  36. Report("******************************************************");
  37. Report("J-Link script: iMX6 SoloX Cortex-A9 core J-Link script");
  38. Report("******************************************************");
  39. JLINK_CORESIGHT_Configure("IRPre=4;DRPre=1;IRPost=9;DRPost=2;IRLenDevice=4");
  40. CPU = CORTEX_A9; // Pre-select that we have a Cortex-A9 connected
  41. JTAG_AllowTAPReset = 1; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
  42. CORESIGHT_CoreBaseAddr = 0x02150000;
  43. CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
  44. CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
  45. CORESIGHT_IndexAPBAPToUse = 1;
  46. JTAG_SetDeviceId(0, 0x4BA00477); // 4-bits IRLen
  47. JTAG_SetDeviceId(1, 0x4BA00477); // 4-bits IRLen
  48. JTAG_SetDeviceId(2, 0x00000001); // 5-bits IRLen
  49. JTAG_SetDeviceId(3, 0x0891C01D); // 4-bits IRLen
  50. }