NXP_iMX7ULP_CortexM4.JLinkScript 2.4 KB

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  1. /*********************************************************************
  2. * (c) 1995 - 2018 SEGGER Microcontroller GmbH *
  3. * The Embedded Experts *
  4. * www.segger.com *
  5. **********************************************************************
  6. -------------------------- END-OF-HEADER -----------------------------
  7. */
  8. /*********************************************************************
  9. *
  10. * ResetTarget
  11. */
  12. void ResetTarget(void) {
  13. //
  14. // This device requires a special reset as default reset does not work for this device.
  15. // TBD
  16. //
  17. JLINK_TARGET_Halt(); // Make sure that the CPU is halted when reset is called
  18. }
  19. /*********************************************************************
  20. *
  21. * InitTarget
  22. */
  23. void InitTarget(void) {
  24. JLINK_SYS_Report("***************************************************");
  25. JLINK_SYS_Report("J-Link script: iMX7ULP Cortex-M4 core J-Link script");
  26. JLINK_SYS_Report("***************************************************");
  27. JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
  28. CPU = CORTEX_M4; // Pre-select that we have a Cortex-M4 connected
  29. JTAG_AllowTAPReset = 0; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection
  30. //
  31. // Manually configure which APs are present on the CoreSight device
  32. //
  33. JTAG_SetDeviceId(0, 0x4BA00477); // 4-bits IRLen
  34. CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
  35. CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
  36. CORESIGHT_AddAP(2, CORESIGHT_CUSTOM_AP);
  37. CORESIGHT_AddAP(3, CORESIGHT_AHB_AP);
  38. CORESIGHT_AddAP(4, CORESIGHT_CUSTOM_AP);
  39. CORESIGHT_AddAP(5, CORESIGHT_CUSTOM_AP);
  40. CORESIGHT_IndexAHBAPToUse = 3;
  41. JTAG_SetDeviceId(0, 0x6BA00477); // 4-bits IRLen
  42. }
  43. /*********************************************************************
  44. *
  45. * SetupTarget
  46. */
  47. void SetupTarget(void) {
  48. //
  49. // Map alias area of M4 core for flash to 0x04000000 instead of 0xC0000000 as in certain circumstances the 0xC0000000 is not initialized
  50. //
  51. JLINK_ExecCommand("map add 0xC0000000-0xC7FFFFFF A FLASH 0x04000000 0x07FFFFFF");
  52. //
  53. // The MPU causes problems during flash download
  54. // This fix has been requested by NXP
  55. //
  56. JLINK_SYS_Report("Disabling Cortex-M4 MPU ...");
  57. MEM_WriteU32(0xE000ED94, 0x00000000);
  58. }