LPC_SysControl.h 3.7 KB

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  1. #ifndef __LPC_SYSCONTROL_H
  2. #define __LPC_SYSCONTROL_H
  3. /*************************************************************************
  4. *
  5. * Used with ICCARM and AARM.
  6. *
  7. * (c) Copyright IAR Systems 2003
  8. *
  9. * File name : LPC_SysControl.h
  10. * Description :
  11. *
  12. * History :
  13. * 1. Data: August 17, 2004
  14. * Author: Shawn Zhang
  15. * Description: Create the basic function
  16. *
  17. * 2. Data : Oct 7, 2004
  18. * Author : Stanimir Bonev
  19. * Description : Modify some function and interface
  20. *
  21. * $Revision: 1.1 $
  22. **************************************************************************/
  23. #include <includes.h>
  24. /* Fosc range: 10MHz ~ 25MHz */
  25. #define Fosc_MIN 10000000L
  26. #define Fosc_MAX 25000000L
  27. /* Fcclk range: 10MHz ~ MCU allowed frequency */
  28. #define Fcclk_MIN 10000000L
  29. #define Fcclk_MAX 60000000L
  30. /* Fcco range: 156MHz ~ 320MHz */
  31. #define Fcco_MIN 156000000L
  32. #define Fcco_MAX 320000000L
  33. #define PLLFEED_DATA1 0xAA
  34. #define PLLFEED_DATA2 0x55
  35. /* PLL PLLCON register bit descriptions */
  36. #define PLLCON_ENABLE_BIT 0
  37. #define PLLCON_CONNECT_BIT 1
  38. /* PLL PLLSTAT register bit descriptions */
  39. #define PLLSTAT_ENABLE_BIT 8
  40. #define PLLSTAT_CONNECT_BIT 9
  41. #define PLLSTAT_LOCK_BIT 10
  42. /* PM Peripheral Type */
  43. #define PC_TIMER0 0x2
  44. #define PC_TIMER1 0x4
  45. #define PC_UART0 0x8
  46. #define PC_UART1 0x10
  47. #define PC_PWM0 0x20
  48. #define PC_I2C 0x80
  49. #define PC_SPI0 0x100
  50. #define PC_RTC 0x200
  51. // External interrupt
  52. typedef enum {
  53. EXTINT0 = 0,
  54. EXTINT1,
  55. EXTINT2
  56. } LPC_SysControl_ExtInt_Chanel_t;
  57. // Memory Mapping Control Mode
  58. typedef enum {
  59. BOOT_LOADER = 0,
  60. USER_FLASH,
  61. USER_RAM
  62. } LPC_SysControl_RemapMode_t;
  63. // Memory Accelerator Module Operating Mode
  64. typedef enum {
  65. VPBDIV4 = 0, // Pclk = 1/4 Pcclk
  66. VPBDIV1, // Pclk = Pcclk
  67. VPBDIV2 // Pclk = 1/2 Pcclk
  68. } LPC_SysControl_VPBDiv_t;
  69. // Memory Accelerator Module Operating Mode
  70. typedef enum {
  71. MAM_PARTIALLY = 1,
  72. MAM_FULL
  73. } LPC_SysControl_MAMMode_t;
  74. // Power Manager Mode
  75. typedef enum {
  76. PM_STANDARD = 0,
  77. PM_IDLE,
  78. PM_POWERDOWN
  79. } LPC_SysControl_PMMode_t;
  80. // External interrupt trigger type
  81. typedef enum {
  82. LEVEL_LOW = 0,
  83. LEVEL_HIGH,
  84. EDGE_RISING,
  85. EDGE_FALLING
  86. } LPC_SysControl_EXTINTTriggerType_t;
  87. // MAM fetch cycles
  88. // SysClock<20MHz: MAMTIM can be 001
  89. // 20MHz<SysClock<40MHz: suggest 2 cycle
  90. // 40MHz<SysClock: suggest 3 cycle
  91. typedef enum {
  92. MAMCycle1 = 1,
  93. MAMCycle2,
  94. MAMCycle3,
  95. MAMCycle4,
  96. MAMCycle5,
  97. MAMCycle6,
  98. MAMCycle7
  99. } LPC_SysControl_MAMCycle_t;
  100. typedef struct {
  101. LPC_SysControl_MAMMode_t Mode;
  102. LPC_SysControl_MAMCycle_t Cycle;
  103. } LPC_SysControl_MAMConfig_t;
  104. typedef struct {
  105. unsigned long Fosc; // Crystal Oscillator Frequency
  106. unsigned long Fcclk; // PLL output frequency (also processor clock frequency)
  107. unsigned long Fpclk; // Peripheral frequency
  108. LPC_SysControl_RemapMode_t RemapMode;
  109. LPC_SysControl_VPBDiv_t VPBDivider;
  110. bool MAMEnable;
  111. LPC_SysControl_MAMConfig_t MAMConfig;
  112. } LPC_Syscontrol_Config_t;
  113. // Declare API functions
  114. int SYS_Init (unsigned long Fosc, unsigned long Fcclk,
  115. LPC_SysControl_VPBDiv_t VPBDivider,
  116. LPC_SysControl_RemapMode_t RemapMode,
  117. unsigned long PortDir0, unsigned long Port0,
  118. unsigned long PortDir1, unsigned long Port1);
  119. unsigned int SYS_GetFpclk (void);
  120. int PM_SetMode (LPC_SysControl_PMMode_t Mode);
  121. int PM_OpenPeripheral (unsigned int DevType);
  122. int PM_ClosePeripheral (unsigned int DevType);
  123. int EXTINT_Init (LPC_SysControl_ExtInt_Chanel_t ExtIntNum,
  124. bool WakeupEnable);
  125. #endif //__LPC_SYSCONTROL_H