0x484 STMicroelectronics MCU Cortex-M33 STM32H5xx STM32H5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0xFF RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x10 Dual 0x10 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Dual 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Product state PRODUCT_STATE Life state code. 0x8 0x8 R ST-VIRGIN ST-OPEN ST-SFI-READY ST-ROT-READY OEM-provisioning OEM-provisioned TZ-OEM-Closed OEM-Closed OEM-Locked OEM-Unconstrained-Debug OEM-NS-Unconstrained-Debug PRODUCT_STATE Life state code. 0x8 0x8 W ST-VIRGIN ST-OPEN ST-SFI-READY ST-ROT-READY OEM-provisioning OEM-provisioned TZ-OEM-Closed OEM-Closed OEM-Locked OEM-Unconstrained-Debug OEM-NS-Unconstrained-Debug BOR Level BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration VDDIO_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x4 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed VDDIO_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x4 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 R OEM-iRoT (system flash) selected ST-iRoT (user flash) selected BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 W OEM-iRoT (system flash) selected ST-iRoT (user flash) selected SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW IWDG control mode option status bit. 0x4 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW IWDG control mode option status bit. 0x4 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_SHDWN Core domain Shutdown entry reset option status bit. 0x5 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_SHDWN Core domain Shutdown entry reset option status bit. 0x5 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP Core domain DStop entry reset option status bit. 0x6 0x1 R a reset is generated when entering DStop or DStop2 mode on core domain no reset generated when entering DStop or DStop2 mode on core domain NRST_STOP Core domain DStop entry reset option status bit. 0x6 0x1 W a reset is generated when entering DStop or DStop2 mode on core domain no reset generated when entering DStop or DStop2 mode on core domain NRST_STDY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain USB_EN USB peripheral enable bit 0xE 0x1 R USB communication disabled USB communication enabled HASH_EN HASH SHA IP enable bit. 0xD 0x1 R HASH feature disabled HASH feature enabled RNG_EN random number generator IP enable bit 0xC 0x1 R HASH feature disabled HASH feature enabled PKA_EN public key cryptography IP enable bit 0xB 0x1 R HASH feature disabled HASH feature enabled AES_EN 0xA 0x1 R HASH feature disabled HASH feature enabled RSS_OPT 0x7 0x3 R FLASH_SIZE 0x4 0x3 R 512kB product 1MB product 2MB product GFX_EN GFX module option status bit 0x3 0x1 R GFX disabled GFX enabled OTFDEC_EN OTFDEC option status bit. Controls on the fly decryption of external memory 0x2 0x1 R OTFDEC disabled OTFDEC enbled SAES_EN Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage 0x1 0x1 R SAES disabled SAES enabled CAN_EN CAN module control bit 0x0 0x1 R CAN disabled CAN enabled USB_EN USB peripheral enable bit. 0xE 0x1 W USB communication disabled USB communication enabled HASH_EN HASH SHA IP enable bit. 0xD 0x1 W HASH feature disabled HASH feature enabled RNG_EN random number generator IP enable bit 0xC 0x1 W HASH feature disabled HASH feature enabled PKA_EN public key cryptography IP enable bit 0xB 0x1 W HASH feature disabled HASH feature enabled AES_EN 0xA 0x1 W HASH feature disabled HASH feature enabled RSS_OPT 0x7 0x3 W FLASH_SIZE 0x4 0x3 W 512kB product 1MB product 2MB product GFX_EN GFX module option status bit 0x3 0x1 W GFX disabled GFX enabled OTFDEC_EN OTFDEC option status bit. Controls on the fly decryption of external memory 0x2 0x1 W OTFDEC disabled OTFDEC enbled SAES_EN Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage 0x1 0x1 W SAES disabled SAES enabled CAN_EN CAN module control bit 0x0 0x1 W CAN disabled CAN enabled User Configuration 2 TZEN Trust Zone Enable configuration bits 0x18 0x8 R Trust zone disabled Trust zone enabled HUK_PUF This bit configures the nature and use of the unique key 0xF 0x1 R The key is treated as HUK The key is treated as PUF USBPD_DB_DIS USB power delivery configuration option bit 0x8 0x1 R Disabled Enabled SRAM2_PAR Parity in SRAM2 region configuration bit 0x7 0x1 R The key is treated as HUK The key is treated as PUF SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R Disabled Enabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 R Disabled Enabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R Disabled Enabled SRAM2_RST 0x3 0x1 R Disabled Enabled SRAM1_3_RST 0x2 0x1 R Disabled Enabled TZEN Trust Zone Enable configuration bits 0x18 0x8 W Trust zone disabled Trust zone enabled HUK_PUF This bit configures the nature and use of the unique key 0xF 0x1 W The key is treated as HUK The key is treated as PUF USBPD_DB_DIS USB power delivery configuration option bit 0x8 0x1 W Disabled Enabled SRAM2_PAR Parity in SRAM2 region configuration bit 0x7 0x1 W The key is treated as HUK The key is treated as PUF SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W Disabled Enabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 W Disabled Enabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W Disabled Enabled SRAM2_RST 0x3 0x1 W Disabled Enabled SRAM1_3_RST 0x2 0x1 W Disabled Enabled Boot Configuration BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 0x10 R BOOT_LOCK_NS A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings 0x0 0x8 R BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 0x10 W BOOT_LOCK_NS A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings 0x0 0x8 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash data sectors DATA_EN Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_1 DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 R DATA_EN Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_1 DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 W Flash data sectors DATA_EN_2 Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_2 DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 R DATA_EN_2 Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_2 DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 W Flash EPOCH NS_EPOCH Non Volatile Non Secure EPOCH counter 0x0 0x18 R NS_EPOCH Non Volatile Non Secure EPOCH counter 0x0 0x18 W SEC_EPOCH Non Volatile Secure EPOCH counter 0x0 0x18 R SEC_EPOCH Non Volatile Secure EPOCH counter 0x0 0x18 W Flash HDP bank 1 HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 R HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x7 R HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 W HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x7 W Flash HDP bank 2 HDP2_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 R HDP2_END TIL barrier end set in number of 8kb sectors 0x10 0x7 R HDP2_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 W HDP2_END TIL barrier end set in number of 8kb sectors 0x10 0x7 W Product state PRODUCT_STATE Life state code. 0x8 0x8 R ST-VIRGIN ST-OPEN ST-SFI-READY ST-ROT-READY OEM-provisioning OEM-provisioned TZ-OEM-Closed OEM-Closed OEM-Locked OEM-Unconstrained-Debug OEM-NS-Unconstrained-Debug PRODUCT_STATE Life state code. 0x8 0x8 W ST-VIRGIN ST-OPEN ST-SFI-READY ST-ROT-READY OEM-provisioning OEM-provisioned TZ-OEM-Closed OEM-Closed OEM-Locked OEM-Unconstrained-Debug OEM-NS-Unconstrained-Debug BOR Level BOR_LEV Brownout level option status bit. 0x0 0x2 R BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) BOR_LEV Brownout level option status bit. 0x0 0x2 W BOR OFF, POR/PDR reset threshold level is applied BOR Level 1, the threshold level is low (around 2.1 V) BOR Level 2, the threshold level is medium (around 2.4 V) BOR Level 3, the threshold level is high (around 2.7 V) User Configuration VDDIO_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x4 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed VDDIO_HSLV VDD I/O high-speed at low-voltage status bit. 0x10 0x4 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled VDD I/O below 2.5 V, I/O speed optimization at low-voltage feature allowed IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 R Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. IWDG_STOP Stop mode freeze option status bit. 0x14 0x1 W Independent watchdog frozen in system Stop mode Independent watchdog keep running in system Stop mode. BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 R OEM-iRoT (system flash) selected ST-iRoT (user flash) selected BOOT_UBE Unique boot entry control, selects either ST or OEM iRoT for secure boot. 0x16 0x8 W OEM-iRoT (system flash) selected ST-iRoT (user flash) selected SWAP_BANK Bank swapping option status bit. 0x1F 0x1 R bank 1 and bank 2 not swapped bank 1 and bank 2 swapped SWAP_BANK Bank swapping option status bit. 0x1F 0x1 W bank 1 and bank 2 not swapped bank 1 and bank 2 swapped IWDG_SW IWDG control mode option status bit. 0x3 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software IWDG_SW IWDG control mode option status bit. 0x3 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW IWDG control mode option status bit. 0x4 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software WWDG_SW IWDG control mode option status bit. 0x4 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_SHDWN Core domain Shutdown entry reset option status bit. 0x5 0x1 R IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_SHDWN Core domain Shutdown entry reset option status bit. 0x5 0x1 W IWDG watchdog is controlled by hardware IWDG watchdog is controlled by software NRST_STOP Core domain DStop entry reset option status bit. 0x6 0x1 R a reset is generated when entering DStop or DStop2 mode on core domain no reset generated when entering DStop or DStop2 mode on core domain NRST_STOP Core domain DStop entry reset option status bit. 0x6 0x1 W a reset is generated when entering DStop or DStop2 mode on core domain no reset generated when entering DStop or DStop2 mode on core domain NRST_STDY Core domain Standby entry reset option status bit. 0x7 0x1 R a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain NRST_STDY Core domain Standby entry reset option status bit. 0x7 0x1 W a reset is generated when entering Standby mode on core domain no reset generated when entering Standby mode on core domain USB_EN USB peripheral enable bit 0xE 0x1 R USB communication disabled USB communication enabled HASH_EN HASH SHA IP enable bit. 0xD 0x1 R HASH feature disabled HASH feature enabled RNG_EN random number generator IP enable bit 0xC 0x1 R HASH feature disabled HASH feature enabled PKA_EN public key cryptography IP enable bit 0xB 0x1 R HASH feature disabled HASH feature enabled AES_EN 0xA 0x1 R HASH feature disabled HASH feature enabled RSS_OPT 0x7 0x3 R FLASH_SIZE 0x4 0x3 R 512kB product 1MB product 2MB product GFX_EN GFX module option status bit 0x3 0x1 R GFX disabled GFX enabled OTFDEC_EN OTFDEC option status bit. Controls on the fly decryption of external memory 0x2 0x1 R OTFDEC disabled OTFDEC enbled SAES_EN Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage 0x1 0x1 R SAES disabled SAES enabled CAN_EN CAN module control bit 0x0 0x1 R CAN disabled CAN enabled USB_EN USB peripheral enable bit. 0xE 0x1 W USB communication disabled USB communication enabled HASH_EN HASH SHA IP enable bit. 0xD 0x1 W HASH feature disabled HASH feature enabled RNG_EN random number generator IP enable bit 0xC 0x1 W HASH feature disabled HASH feature enabled PKA_EN public key cryptography IP enable bit 0xB 0x1 W HASH feature disabled HASH feature enabled AES_EN 0xA 0x1 W HASH feature disabled HASH feature enabled RSS_OPT 0x7 0x3 W FLASH_SIZE 0x4 0x3 W 512kB product 1MB product 2MB product GFX_EN GFX module option status bit 0x3 0x1 W GFX disabled GFX enabled OTFDEC_EN OTFDEC option status bit. Controls on the fly decryption of external memory 0x2 0x1 W OTFDEC disabled OTFDEC enbled SAES_EN Secure AES module control bit. SAES is symmetric cryptography module with close ties to OBKey storage 0x1 0x1 W SAES disabled SAES enabled CAN_EN CAN module control bit 0x0 0x1 W CAN disabled CAN enabled User Configuration 2 TZEN Trust Zone Enable configuration bits 0x18 0x8 R Trust zone disabled Trust zone enabled HUK_PUF This bit configures the nature and use of the unique key 0xF 0x1 R The key is treated as HUK The key is treated as PUF USBPD_DB_DIS USB power delivery configuration option bit 0x8 0x1 R Disabled Enabled SRAM2_PAR Parity in SRAM2 region configuration bit 0x7 0x1 R The key is treated as HUK The key is treated as PUF SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 R Disabled Enabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 R Disabled Enabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 R Disabled Enabled SRAM2_RST 0x3 0x1 R Disabled Enabled SRAM1_3_RST 0x2 0x1 R Disabled Enabled TZEN Trust Zone Enable configuration bits 0x18 0x8 W Trust zone disabled Trust zone enabled HUK_PUF This bit configures the nature and use of the unique key 0xF 0x1 W The key is treated as HUK The key is treated as PUF USBPD_DB_DIS USB power delivery configuration option bit 0x8 0x1 W Disabled Enabled SRAM2_PAR Parity in SRAM2 region configuration bit 0x7 0x1 W The key is treated as HUK The key is treated as PUF SRAM2_ECC ECC in SRAM2 region configuration bit 0x6 0x1 W Disabled Enabled SRAM3_ECC ECC in SRAM3 region configuration bit 0x5 0x1 W Disabled Enabled BKPRAM_ECC ECC in BKPRAM region configuration bit 0x4 0x1 W Disabled Enabled SRAM2_RST 0x3 0x1 W Disabled Enabled SRAM1_3_RST 0x2 0x1 W Disabled Enabled Boot Configuration BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 0x10 R BOOT_LOCK_NS A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings 0x0 0x8 R BOOT_ADDR_NS Unique Boot Entry Secure Address 0x8 0x10 W BOOT_LOCK_NS A field locking the values of UBE, SWAP, and BOOT_ADDR_SEC settings 0x0 0x8 W Write sector group protection 1 WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 R WRPSGn1 Bank 1 sector group protection option status byte 0x0 0x20 W Write sector group protection 2 WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 R WRPSGn2 Bank 2 sector group protection option status byte 0x0 0x20 W OTP write protection LOCKBL OTP Block Lock 0x0 0x20 R LOCKBL OTP Block Lock 0x0 0x20 W Flash data sectors DATA_EN Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_1 DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 R DATA_EN Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_1 DATA_SECTOR_START_1 contains the start sectors of the Flash high-cycle data area in Bank1. 0x0 0x3 W Flash data sectors DATA_EN_2 Bank1 Flash high-cycle data enable 0xF 0x1 R No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_2 DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 R DATA_EN_2 Bank1 Flash high-cycle data enable 0xF 0x1 W No Flash high-cycle data area Flash high-cycle data is used DATA_SECTOR_START_2 DATA_SECTOR_START_2 contains the start sectors of the Flash high-cycle data area in Bank2. 0x0 0x3 W Flash EPOCH NS_EPOCH Non Volatile Non Secure EPOCH counter 0x0 0x18 R NS_EPOCH Non Volatile Non Secure EPOCH counter 0x0 0x18 W SEC_EPOCH Non Volatile Secure EPOCH counter 0x0 0x18 R SEC_EPOCH Non Volatile Secure EPOCH counter 0x0 0x18 W Flash HDP bank 1 HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 R HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x7 R HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 W HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x7 W Flash HDP bank 2 HDP2_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 R HDP2_END TIL barrier end set in number of 8kb sectors 0x10 0x7 R HDP2_STRT TIL barrier start set in number of 8kb sectors 0x0 0x7 W HDP2_END TIL barrier end set in number of 8kb sectors 0x10 0x7 W