0x483 STMicroelectronics MCU Cortex-M7 STM32H723xx/STM32H725xx STM32H7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 R BOR OFF BOR level1: 2.1V BOR level2: 2.4 V BOR level3: 2.7 V BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 W reset level is set to 0.0 V reset level is set to 2.1 V reset level is set to 2.4 V reset level is set to 2.7 V User Configuration IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 R Security feature disabled Security feature enabled IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 W Security feature disabled Security feature enabled SWAP_BANK_OPT 0x1F 0x1 W after boot loading, no swap for user sectors after boot loading, user sectors swapped Boot address Option Bytes BOOT_CM7_ADD0 Define the boot address for Cortex-M7 when BOOT0=0 0x0 0x10 R BOOT_CM7_ADD1 Define the boot address for Cortex-M7 when BOOT0=1 0x10 0x10 R BOOT_CM7_ADD0 0x0 0x10 W BOOT_CM7_ADD1 0x10 0x10 W PCROP Protection PROT_AREA_START Flash Bank PCROP start address 0x0 0xC R PROT_AREA_END Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. 0x10 0xC R DMEP 0x1F 0x1 R Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START Flash Bank PCROP start address 0x0 0xC W PROT_AREA_END Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP 0x1F 0x1 W Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs Secure Protection SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC R SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC R DMES1 0x1F 0x1 R Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC W SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC W DMES1 0x1F 0x1 W Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC R SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC R DMES2 0x1F 0x1 R Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC W SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC W DMES2 0x1F 0x1 W Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs DTCM RAM Protection ST_RAM_SIZE 0x13 0x2 R 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code ST_RAM_SIZE 0x13 0x2 W 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code Write Protection nWRP0 0x0 0x8 R Write protection active Write protection not active nWRP0 0x0 0x8 W Write protection active Write protection not active TCM_AXI Shared Configuration TCM_AXI_SHARED_CFG 0x0 0x2 R 64 KB ITCM : 320KB system AXI 128KB ITCM : 256KB system AXI 192KB ITCM : 192KB system AXI 256KB ITCM : 128KB system AXI CPU_FREQ_BOOST 0x2 0x1 R Feature disabled CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) TCM_AXI_SHARED_CFG 0x0 0x2 W 64KB ITCM : 320KB system AXI 128KB ITCM : 256KB system AXI 192KB ITCM : 192KB system AXI 256KB ITCM : 128KB system AXI CPU_FREQ_BOOST 0x2 0x1 W Feature disabled CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM) 0x496 STMicroelectronics MCU Cortex-M0+/M4 STM32WB35xx STM32WB ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise system Flash Boot from code area if BOOT0=0 otherwise embedded SRAM nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 R Security disabled Security enabled SFSA Secure Flash start address 0x0 0x7 RW FSD 0x7 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1 : SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x11 RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area. 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area. 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area. 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area. 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise system Flash Boot from code area if BOOT0=0 otherwise embedded SRAM nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 R Security disabled Security enabled SFSA Secure Flash start address 0x0 0x8 RW FSD 0x8 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1: SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x12 RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area. 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area. 0x10 0x8 RW 0x469 STMicroelectronics MCU Cortex-M4 STM32G47x/G48x STM32G4 Category 3 devices, ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DBANK 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xF RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xF RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0xF RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0xF RW PCROP2_END Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP2_END Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW Secure Protection (Bank 1) SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x8 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. the boot will be done from user flash only, whatever the RDP level Secure Protection (Bank 2) SEC_SIZE2 sets the number of pages used in the bank 2 securable area 0x0 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DBANK 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xF RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xF RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x8 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. the boot will be done from user flash only, whatever the RDP level PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0xF RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0xF RW PCROP2_END Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW PCROP2_END Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xF RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW Secure Protection SEC_SIZE2 sets the number of pages used in the bank 2 securable area 0x0 0x8 RW 0x468 STMicroelectronics MCU Cortex-M4 STM32G43x/G44x STM32G4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xE RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xE RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW Secure Protection SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x8 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. the boot will be done from user flash only, whatever the RDP level Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, no debug BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM_PE SRAM1 and CCM SRAM parity check enable 0x18 0x1 RW SRAM1 and CCM SRAM parity check enable SRAM1 and CCM SRAM parity check disable CCMSRAM_RST CCM SRAM Erase when system reset 0x19 0x1 RW CCM SRAM erased when a system reset occurs CCM SRAM is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PB8/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 NRST_MODE 0x1C 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1E 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0xE RW PCROP1_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0xE RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW Secure Protection SEC_SIZE1 sets the number of pages used in the bank 1 securable area 0x0 0x8 RW BOOT_LOCK Unique boot entry point 0x10 0x1 RW This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash. the boot will be done from user flash only, whatever the RDP level 0x497 STMicroelectronics MCU Cortex-M0+/M4 STM32WLxx STM32WL ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x40 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise system Flash Boot from code area if BOOT0=0 otherwise embedded SRAM nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog C1BOOTLOCK 0x1E 0x1 RW CPU1 CM4 Unique Boot entry lock disabled CPU1 CM4 Unique Boot entry lock enabled C2BOOTLOCK 0x1F 0x1 RW CPU2 CM0+ Unique Boot entry lock disabled CPU2 CM0+ Unique Boot entry lock enabled IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 RW Security disabled Security enabled SFSA This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area. 0x0 0x7 RW FSD 0x7 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled SHDPSA SHDPSA[6:0] contain the start address of the first 2 kB page of the User Flash Sticky hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash Sticky hide protection area enabled. 0x10 0x7 RW HDPAD User Flash Sticky hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0 0x17 0x1 RW SPI3SD SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled 0x1F 0x1 RW FSD=0 and SPI3SD=0: SPI3 security enabled FSD=0 and SPI3SD=1: SPI3 security disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD 0x1E 0x1 RW SRAM2b is secure if FSD=0 and non-secure otherwise SRAM2b is non-secure if FSD=0 and secure otherwise SNBRSA 0x19 0x5 RW BRSD 0x17 0x1 RW SRAM2a is secure if FSD=0 and non-secure otherwise SRAM2b is non-secure if FSD=0 and secure otherwise SBRSA 0x12 0x5 RW SBRV 0x0 0x10 RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x8 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x8 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 nBOOT0=1 nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise system Flash Boot from code area if BOOT0=0 otherwise embedded SRAM nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog C1BOOTLOCK 0x1E 0x1 RW CPU1 CM4 Unique Boot entry lock disabled CPU1 CM4 Unique Boot entry lock enabled C2BOOTLOCK 0x1F 0x1 RW CPU2 CM0+ Unique Boot entry lock disabled CPU2 CM0+ Unique Boot entry lock enabled IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x8 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x8 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW 0x495 STMicroelectronics MCU Cortex-M0+/M4 STM32WB55xx STM32WB ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 Boot selected based on nBOOT1 nBOOT0=1 Boot from main Flash nBOOT1 0x17 0x1 RW Boot from code area if BOOT0=0 otherwise embedded SRAM Boot from code area if BOOT0=0 otherwise system Flash nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 R Security disabled Security enabled SFSA Secure Flash start address 0x0 0x8 RW FSD 0x8 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1 : SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x12 RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x3 RW BOR Level 0 reset level threshold is around 1.7 V BOR Level 1 reset level threshold is around 2.0 V BOR Level 2 reset level threshold is around 2.2 V BOR Level 3 reset level threshold is around 2.5 V BOR Level 4 reset level threshold is around 2.8 V User Configuration nBOOT0 0x1B 0x1 RW nBOOT0=0 Boot selected based on nBOOT1 nBOOT0=1 Boot from main Flash nBOOT1 0x17 0x1 RW Boot from Flash if nBoot0=0 otherwise embedded SRAM Boot from Flash if nBoot0=0 otherwise system memory nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin SRAM2RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs SRAM2PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nRST_STOP 0xC 0x1 RW Reset generated when entering the Stop mode No reset generated when entering the Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering the Standby mode No reset generated when entering the Standby mode nRSTSHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode WWDGSW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWGDSTDBY 0x12 0x1 RW Independent watchdog counter frozen in Standby mode Independent watchdog counter running in Standby mode IWDGSTOP 0x11 0x1 RW Independent watchdog counter frozen in Stop mode Independent watchdog counter running in Stop mode IWDGSW 0x10 0x1 RW Hardware independent watchdog Software independent watchdog IPCCDBA IPCC mailbox data buffer base address 0x0 0xE RW Security Configuration Option bytes ESE 0x8 0x1 R Security disabled Security enabled SFSA Secure Flash start address 0x0 0x8 RW FSD 0x8 0x1 RW System and Flash secure System and Flash non-secure DDS 0xC 0x1 RW CPU2 debug access enabled CPU2 debug access disabled C2OPT 0x1F 0x1 RW SBRV will address SRAM2 SBRV will address Flash NBRSD If FSD=1 : SRAM2b is non-secure. If FSD=0 : 0x1E 0x1 RW SRAM2b is secure SRAM2b is non-secure SNBRSA SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area. 0x19 0x5 RW BRSD If FSD=1: SRAM2a is non-secure. If FSD=0 : 0x17 0x1 RW SRAM2a is secure SRAM2a is non-secure SBRSA SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area. 0x12 0x5 RW SBRV Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT. 0x0 0x12 RW PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 2 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0. 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW 0x413 STMicroelectronics MCU Cortex-M4 STM32F405xx/F407xx/F415xx/F417xx STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0xC RW Write protection active Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0xC RW Write protection active Write protection not active 0x419 STMicroelectronics MCU Cortex-M4 STM32F42xxx/F43xxx STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x4 Dual 0x4 Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration BFB2 0x4 0x1 RW Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) Dual-bank boot enabled. Boot is always performed from system memory. WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated DB1M Dual-bank on 1 Mbyte Flash memory devices 0x1E 0x1 RW 1 Mbyte single bank Flash memory (contiguous addresses in bank1) 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each Write Protection nWRP0 0x10 0xC RW Write protection active Write protection not active nWRP0 0x10 0xC RW PCROP protection not active on sector i PCROP protection active on sector i nWRP12 0x10 0xC RW Write protection active Write protection not active nWRP12 0x10 0xC RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration BFB2 0x4 0x1 RW Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) Dual-bank boot enabled. Boot is always performed from system memory. WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated DB1M Dual-bank on 1 Mbyte Flash memory devices 0x1E 0x1 RW 1 Mbyte single bank Flash memory (contiguous addresses in bank1) 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each Write Protection (Bank 1) WRP0 0x0 0xC RW Write protection active Write protection not active WRP0 0x0 0xC RW PCROP protection not active on sector i PCROP protection active on sector i Write Protection (Bank 2) WRP12 0x0 0xC RW Write protection active Write protection not active WRP12 0x0 0xC RW PCROP protection not active on sector i PCROP protection active on sector i 0x423 STMicroelectronics MCU Cortex-M4 STM32F401xB/C STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x6 RW Write protection active Write protection not active WRP0 0x10 0x6 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x6 RW Write protection active Write protection not active WRP0 0x0 0x6 RW PCROP protection not active on sector i PCROP protection active on sector i 0x433 STMicroelectronics MCU Cortex-M4 STM32F401xD/E STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x8 RW Write protection active Write protection not active WRP0 0x10 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x8 RW Write protection active Write protection not active WRP0 0x0 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i 0x431 STMicroelectronics MCU Cortex-M4 STM32F411xC/E STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x8 RW Write protection active Write protection not active WRP0 0x10 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x8 RW Write protection active Write protection not active WRP0 0x0 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i 0x421 STMicroelectronics MCU Cortex-M4 STM32F446xx STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x8 RW Write protection active Write protection not active WRP0 0x10 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x8 RW Write protection active Write protection not active WRP0 0x0 0x8 RW PCROP protection not active on sector i PCROP protection active on sector i 0x441 STMicroelectronics MCU Cortex-M4 STM32F412 STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0xC RW Write protection active Write protection not active WRP0 0x10 0xC RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0xC RW Write protection active Write protection not active WRP0 0x0 0xC RW PCROP protection not active on sector i PCROP protection active on sector i 0x458 STMicroelectronics MCU Cortex-M4 STM32F410 STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0x5 RW Write protection active Write protection not active WRP0 0x10 0x5 RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x5 RW Write protection active Write protection not active WRP0 0x0 0x5 RW PCROP protection not active on sector i PCROP protection active on sector i 0x463 STMicroelectronics MCU Cortex-M4 STM32F413/F423 STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0xF RW Write protection active Write protection not active WRP0 0x10 0xF RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0xF RW Write protection active Write protection not active WRP0 0x0 0xF RW PCROP protection not active on sector i PCROP protection active on sector i 0x434 STMicroelectronics MCU Cortex-M4 STM32F469xx/F467xx STM32F4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x4 Dual 0x4 Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0x1F 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration BFB2 0x4 0x1 RW Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) Dual-bank boot enabled. Boot is always performed from system memory. WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated DB1M Dual-bank on 1 Mbyte Flash memory devices 0x1E 0x1 RW 1 Mbyte single bank Flash memory (contiguous addresses in bank1) 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each Write Protection nWRP0 0x10 0xC RW Write protection active Write protection not active nWRP0 0x10 0xC RW PCROP protection not active on sector i PCROP protection active on sector i nWRP12 0x10 0xC RW Write protection active Write protection not active nWRP12 0x10 0xC RW PCROP protection not active on sector i PCROP protection active on sector i Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Selection of protection mode for nWPRi bits. 0xF 0x1 RW PCROP disabled. nWPRi bits used for Write protection on sector i PCROP enabled. nWPRi bits used for PCROP protection on sector i BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration BFB2 0x4 0x1 RW Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default) Dual-bank boot enabled. Boot is always performed from system memory. WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated DB1M Dual-bank on 1 Mbyte Flash memory devices 0x1E 0x1 RW 1 Mbyte single bank Flash memory (contiguous addresses in bank1) 1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each Write Protection nWRP0 0x0 0xC RW Write protection active Write protection not active nWRP0 0x0 0xC RW PCROP protection not active on sector i PCROP protection active on sector i Write Protection nWRP12 0x0 0xC RW Write protection active Write protection not active nWRP12 0x0 0xC RW PCROP protection not active on sector i PCROP protection active on sector i 0x411 STMicroelectronics MCU Cortex-M3 STM32F2xx STM32F2 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x10 0xC RW Write protection active Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 reset threshold level from 2.70 to 3.60 V BOR Level 2 reset threshold level from 2.40 to 2.70 V BOR Level 1 reset threshold level from 2.10 to 2.40 V BOR OFF reset threshold level from 1.80 to 2.10 V User Configuration WDG_SW 0x5 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0xC RW Write protection active Write protection not active 0x437 STMicroelectronics MCU Cortex-M3 STM32L15xxE/STM32L162xE STM32L1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Dual 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Dual 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBFB2 0x17 0x1 R If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x20 R Write protection not active Write protection active WRP32 0x0 0x20 R Write protection not active Write protection active WRP64 0x0 0x20 R Write protection not active Write protection active WRP64 0x0 0x20 R Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBFB2 0x7 0x1 W If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x10 W Write protection not active Write protection active WRP16 0x0 0x10 W Write protection not active Write protection active WRP32 0x0 0x10 W Write protection not active Write protection active WRP48 0x0 0x10 W Write protection not active Write protection active WRP64 0x0 0x10 W Write protection not active Write protection active WRP80 0x0 0x10 W Write protection not active Write protection active WRP96 0x0 0x10 W Write protection not active Write protection active WRP112 0x0 0x10 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBFB2 0x7 0x1 RW If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x10 RW Write protection not active Write protection active WRP16 0x0 0x10 RW Write protection not active Write protection active WRP32 0x0 0x10 RW Write protection not active Write protection active WRP48 0x0 0x10 RW Write protection not active Write protection active WRP64 0x0 0x10 RW Write protection not active Write protection active WRP80 0x0 0x10 RW Write protection not active Write protection active WRP96 0x0 0x10 RW Write protection not active Write protection active WRP112 0x0 0x10 RW Write protection not active Write protection active 0x436 STMicroelectronics MCU Cortex-M3 STM32L15xxD/STM32L162xD STM32L1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Dual 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Dual 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBFB2 0x17 0x1 R If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x20 R Write protection not active Write protection active WRP32 0x0 0x20 R Write protection not active Write protection active WRP64 0x0 0x20 R Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBFB2 0x7 0x1 W If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x10 W Write protection not active Write protection active WRP16 0x0 0x10 W Write protection not active Write protection active WRP32 0x0 0x10 W Write protection not active Write protection active WRP48 0x0 0x10 W Write protection not active Write protection active WRP64 0x0 0x10 W Write protection not active Write protection active WRP80 0x0 0x10 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBFB2 0x7 0x1 RW If boot from Flash then boot from bank 2 If boot from Flash then boot from bank 1 Write Protection WRP0 0x0 0x10 RW Write protection not active Write protection active WRP16 0x0 0x10 RW Write protection not active Write protection active WRP32 0x0 0x10 RW Write protection not active Write protection active WRP48 0x0 0x10 RW Write protection not active Write protection active WRP64 0x0 0x10 RW Write protection not active Write protection active WRP80 0x0 0x10 RW Write protection not active Write protection active 0x429 STMicroelectronics MCU Cortex-M3 STM32L100x6xxA/STM32L100x8xxA/STM32L100xBxxA/STM32L15xx6xxA/STM32L15xx8xxA/STM32L15xxBxxA STM32L1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x20 R Write protection not active Write protection active WRP0 0x0 0x20 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector write/read (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 W Write protection not active Write protection active WRP0 0x0 0x10 W read/Write protection active read/Write protection active WRP16 0x0 0x10 W Write protection not active Write protection active WRP16 0x0 0x10 W read/Write protection active read/Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector write/read (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 RW Write protection not active Write protection active WRP0 0x0 0x10 RW read/Write protection active read/Write protection active WRP16 0x0 0x10 RW Write protection not active Write protection active WRP16 0x0 0x10 RW read/Write protection active read/Write protection active 0x427 STMicroelectronics MCU Cortex-M3 STM32L100xC/STM32L15xxC/STM32L162xC STM32L1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x20 R Write protection not active Write protection active WRP0 0x0 0x20 R read/Write protection active read/Write protection not active WRP32 0x0 0x20 R Write protection not active Write protection active WRP32 0x0 0x20 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector write/read (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 W Write protection not active Write protection active WRP0 0x0 0x10 W read/Write protection active read/Write protection active WRP16 0x0 0x10 W Write protection not active Write protection active WRP16 0x0 0x10 W read/Write protection active read/Write protection active WRP32 0x0 0x10 W Write protection not active Write protection active WRP32 0x0 0x10 W read/Write protection active read/Write protection not active WRP48 0x0 0x10 W Write protection not active Write protection active WRP48 0x0 0x10 W read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection SPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector write/read (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 RW Write protection not active Write protection active WRP0 0x0 0x10 RW read/Write protection active read/Write protection active WRP16 0x0 0x10 RW Write protection not active Write protection active WRP16 0x0 0x10 RW read/Write protection active read/Write protection active WRP32 0x0 0x10 RW Write protection not active Write protection active WRP32 0x0 0x10 RW read/Write protection active read/Write protection not active WRP48 0x0 0x10 RW Write protection not active Write protection active WRP48 0x0 0x10 RW read/Write protection active read/Write protection not active 0x416 STMicroelectronics MCU Cortex-M3 STM32L100x8/STM32L100xB/STM32L15xx6/STM32L15xx8/STM32L15xxB STM32L1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x20 R Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 W Write protection not active Write protection active WRP16 0x0 0x10 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated Write Protection WRP0 0x0 0x10 RW Write protection not active Write protection active WRP16 0x0 0x10 RW Write protection not active Write protection active 0x435 STMicroelectronics MCU Cortex-M4 STM32L43xxx/STM32L44xxx STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW 0x464 STMicroelectronics MCU Cortex-M4 STM32L41x STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x6 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x6 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x6 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x6 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x6 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x6 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x6 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x6 RW 0x462 STMicroelectronics MCU Cortex-M4 STM32L45x/L46x STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW 0x422 STMicroelectronics MCU Cortex-M4 STM32F302xB-xC/STM32F303xB-xC/F358xx STM32F3 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled SRAM_PE 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x439 STMicroelectronics MCU Cortex-M4 STM32F301x4-x6-x8/STM32F302x4-x6-x8/F318xx STM32F3 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled SRAM_PE 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x461 STMicroelectronics MCU Cortex-M4 STM32L496xx/STM32L4A6xx STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW 0x438 STMicroelectronics MCU Cortex-M4 STM32F303x4-x6-x8/F328xx/F334xx STM32F3 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled SRAM_PE 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x432 STMicroelectronics MCU Cortex-M4 STM32F37xx STM32F3 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled SDADC12_VDD 0x17 0x1 RW SDADC12_VDD power supply supervisor disabled. SDADC12_VDD power supply supervisor enabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x415 STMicroelectronics MCU Cortex-M4 STM32L4x1/STM32L475xx/STM32L476xx/STM32L486xx STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW 0x446 STMicroelectronics MCU Cortex-M4 STM32F302xE/F303xE/F398xx STM32F3 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT0 0x13 0x1 RW Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from Embedded SRAM when BOOT0=1 Boot from System flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled BOOT_SEL 0x17 0x1 RW BOOT0 signal is defined by nBOOT0 option bit BOOT0 signal is defined by BOOT0 pin value User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x445 STMicroelectronics MCU Cortex-M0 STM32F04x/F070x6 STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x13 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system memory when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled BOOT_SEL 0x17 0x1 RW BOOT0 signal is defined by nBOOT0 option bit BOOT0 signal is defined by BOOT0 pin value User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector 0x444 STMicroelectronics MCU Cortex-M0 STM32F03x STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector 0x442 STMicroelectronics MCU Cortex-M0 STM32F09x/F030xC STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x13 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. 0x14 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled BOOT_SEL 0x17 0x1 RW BOOT0 signal is defined by nBOOT0 option bit BOOT0 signal is defined by BOOT0 pin value User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x451 STMicroelectronics MCU Cortex-M7 STM32F76x/STM32F77x STM32F7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Dual 0x10 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x20 Dual 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0x1F 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x1E 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode nDBANK 0x1D 0x1 RW Flash in dual bank with 128 bits read access Flash in single bank with 256 bits read access nDBOOT 0x1C 0x1 RW Dual Boot enabled Dual Boot disabled WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x10 0x10 RW Write Protection nWRP0 0x10 0xC RW Write protection active on this sector Write protection not active on this sector nWRP0 0x10 0x6 RW Write protection active on bank1 sector 2i and 2i+1 Write protection not active on bank1 sector 2i, 2i+1 nWRP6 0x16 0x6 RW Write protection active on bank2 sector 2i and 2i+1 Write protection not active on bank2 sector 2i, 2i+1 Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0xF 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0xE 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode nDBANK 0xD 0x1 RW Flash in dual bank with 128 bits read access Flash in single bank with 256 bits read access nDBOOT 0xC 0x1 RW Dual Boot enabled Dual Boot disabled WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x0 0x10 RW Write Protection nWRP0 0x0 0xC RW Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x6 RW Write protection active on bank1 sector 2i and 2i+1 Write protection not active on bank1 sector 2i, 2i+1 nWRP6 0x6 0x6 RW Write protection active on bank2 sector 2i and 2i+1 Write protection not active on bank2 sector 2i, 2i+1 0x449 STMicroelectronics MCU Cortex-M7 STM32F74x/STM32F75x STM32F7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Single 0x10 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Single 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0x1F 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x1E 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x10 0x10 RW Write Protection nWRP0 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP0 0x10 0x2 RW Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0xF 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0xE 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x0 0x10 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector 0x440 STMicroelectronics MCU Cortex-M0 STM32F05x/F030x8 STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. 0x14 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x448 STMicroelectronics MCU Cortex-M0 STM32F07x STM32F0 ARM 32-bit Cortex-M0 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. 0x14 0x1 RW Boot from embedded SRAM when BOOT0=1 Boot from system flash when BOOT0=1 VDDA_MONITOR 0x15 0x1 RW VDDA power supply supervisor disabled VDDA power supply supervisor enabled RAM_PARITY 0x16 0x1 RW RAM parity check enabled RAM parity check disabled User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x452 STMicroelectronics MCU Cortex-M7 STM32F72x/STM32F73x STM32F7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Single 0x10 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Single 0x10 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0x1F 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x1E 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x10 0x10 RW Write Protection nWRP0 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector nWRP0 0x10 0x4 RW Write protection active on this sector Write protection not active on this sector Read/Write Protection PCROP0 0x0 0x8 RW PCROP protection not active on this sector PCROP protection active on this sector PCROP0 0x0 0x4 RW PCROP protection not active on this sector PCROP protection active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 RW BOR Level 3 (VBOR3), brownout threshold level 3 BOR Level 2 (VBOR2), brownout threshold level 2 BOR Level 1 (VBOR1), brownout threshold level 1 BOR off, POR/PDR reset threshold level is applied User Configuration IWDG_STOP 0xF 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0xE 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x4 0x1 RW Hardware window watchdog Software window watchdog IWDG_SW 0x5 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x6 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x7 0x1 RW Reset generated when entering Standby mode No reset generated PCROP_RDP 0xF 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Boot address Option Bytes BOOT_ADD0 Define the boot address when BOOT0=0 0x0 0x10 RW BOOT_ADD1 Define the boot address when BOOT0=1 0x0 0x10 RW Write Protection nWRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector Read/Write Protection PCROP0 0x0 0x8 RW PCROP protection not active on this sector PCROP protection active on this sector 0x450 STMicroelectronics MCU Cortex-M7 STM32H7xx STM32H7 ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x20 Single 0x20 ITCM Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x20 Single 0x20 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RSS RSS1 0x1A 0x1 R No SFI process on going SFI process started RSS1 0x1A 0x1 W No SFI process on going SFI process started BOR Level BOR_LEV These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. 0x2 0x2 R reset level is set to VBOR0 reset level is set to VBOR1 reset level is set to VBOR2 reset level is set to VBOR3 BOR_LEV These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds. 0x2 0x2 W reset level is set to VBOR0 reset level is set to VBOR1 reset level is set to VBOR2 reset level is set to VBOR3 User Configuration IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software IWDG2_SW 0x5 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP_D1 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY_D1 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 R Security feature disabled Security feature enabled BCM4 0x16 0x1 R CM4 boot disabled CM4 boot enabled BCM7 0x17 0x1 R CM7 boot disabled CM7 boot enabled NRST_STOP_D2 0x18 0x1 R STOP mode on Domain 2 is entering with reset STOP mode on Domain 2 is entering without reset NRST_STBY_D2 0x19 0x1 R STANDBY mode on Domain 2 is entering with reset STANDBY mode on Domain 2 is entering without reset SWAP_BANK 0x1F 0x1 R after boot loading, no swap for user sectors after boot loading, user sectors swapped IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software IWDG2_SW 0x5 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP_D1 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY_D1 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 W Security feature disabled Security feature enabled BCM4 0x16 0x1 W CM4 boot disabled CM4 boot enabled BCM7 0x17 0x1 W CM7 boot disabled CM7 boot enabled NRST_STOP_D2 0x18 0x1 W STOP mode on Domain 2 is entering with reset STOP mode on Domain 2 is entering without reset NRST_STBY_D2 0x19 0x1 W STANDBY mode on Domain 2 is entering with reset STANDBY mode on Domain 2 is entering without reset SWAP_BANK 0x1F 0x1 W after boot loading, no swap for user sectors after boot loading, user sectors swapped Boot address Option Bytes BOOT_CM7_ADD0 Define the boot address for Cortex-M7 when BOOT0=0 0x0 0x10 R BOOT_CM7_ADD1 Define the boot address for Cortex-M7 when BOOT0=1 0x10 0x10 R BOOT_CM4_ADD0 Define the boot address for Cortex-M4 when BOOT0=0 0x0 0x10 R BOOT_CM4_ADD1 Define the boot address for Cortex-M4 when BOOT0=1 0x10 0x10 R BOOT_CM7_ADD0 0x0 0x10 W BOOT_CM7_ADD1 0x10 0x10 W BOOT_CM4_ADD0 0x0 0x10 W BOOT_CM4_ADD1 0x10 0x10 W PCROP Protection PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC R PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. 0x10 0xC R DMEP1 0x1F 0x1 R Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC W PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP1 0x1F 0x1 W Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC R PROT_AREA_END2 Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC R DMEP2 0x1F 0x1 R Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC W PROT_AREA_END2 Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP2 0x1F 0x1 W Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs Secure Protection SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC R SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC R DMES1 0x1F 0x1 R Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC W SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC W DMES1 0x1F 0x1 W Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC R SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC R DMES2 0x1F 0x1 R Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC W SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC W DMES2 0x1F 0x1 W Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs DTCM RAM Protection ST_RAM_SIZE 0x13 0x2 R 2 KB 4 KB 8 KB 16 KB ST_RAM_SIZE 0x13 0x2 W 2 KB 4 KB 8 KB 16 KB Write Protection nWRP0 0x0 0x8 R Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x1 R Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector nWRP0 0x0 0x1 W Write protection active on this sector Write protection not active on this sector nWRP8 0x0 0x8 R Write protection active on this sector Write protection not active on this sector nWRP8 0x0 0x8 W Write protection active on this sector Write protection not active on this sector 0x480 STMicroelectronics MCU Cortex-M7 STM32H7A/B STM32H7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x20 Dual 0x20 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x20 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x8 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 R reset level OFF reset level is set to 2.1 V reset level is set to 2.4 V reset level is set to 2.7 V BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 W reset level OFF reset level is set to 2.1 V reset level is set to 2.4 V reset level is set to 2.7 V User Configuration IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset VDDMMC_HSLV 0x10 0x1 R I/O speed optimization at low-voltage disabled VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 R Security feature disabled Security feature enabled SWAP_BANK_OPT 0x1F 0x1 R after boot loading, no swap for user sectors after boot loading, user sectors swapped IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset VDDMMC_HSLV 0x10 0x1 W I/O speed optimization at low-voltage disabled VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode SECURITY 0x15 0x1 W Security feature disabled Security feature enabled SWAP_BANK_OPT 0x1F 0x1 W after boot loading, no swap for user sectors after boot loading, user sectors swapped Boot address Option Bytes BOOT_CM7_ADD0 Define the boot address for Cortex-M7 when BOOT0=0 0x0 0x10 R BOOT_CM7_ADD1 Define the boot address for Cortex-M7 when BOOT0=1 0x10 0x10 R BOOT_CM7_ADD0 0x0 0x10 W BOOT_CM7_ADD1 0x10 0x10 W PCROP Protection PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC R PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address. 0x10 0xC R DMEP1 0x1F 0x1 R Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START1 Flash Bank 1 PCROP start address 0x0 0xC W PROT_AREA_END1 Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP1 0x1F 0x1 W Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC R PROT_AREA_END2 Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC R DMEP2 0x1F 0x1 R Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs PROT_AREA_START2 Flash Bank 2 PCROP start address 0x0 0xC W PROT_AREA_END2 Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address 0x10 0xC W DMEP2 0x1F 0x1 W Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs Secure Protection SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC R SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC R DMES1 0x1F 0x1 R Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START1 Flash Bank 1 secure area start address 0x0 0xC W SEC_AREA_END1 Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1. 0x10 0xC W DMES1 0x1F 0x1 W Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC R SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC R DMES2 0x1F 0x1 R Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs SEC_AREA_START2 Flash Bank 2 secure area start address 0x0 0xC W SEC_AREA_END2 Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2. 0x10 0xC W DMES2 0x1F 0x1 W Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs DTCM RAM Protection ST_RAM_SIZE 0x13 0x2 R 2 KB 4 KB 8 KB 16 KB ST_RAM_SIZE 0x13 0x2 W 2 KB 4 KB 8 KB 16 KB Write Protection nWRP0 0x0 0x20 R Write protection active Write protection not active nWRP0 0x0 0x20 W Write protection active Write protection not active nWRP32 0x0 0x20 R Write protection active Write protection not active nWRP32 0x0 0x20 W Write protection active Write protection not active 0x417 STMicroelectronics MCU Cortex-M0+ STM32L05x/L06x/L010 STM32L0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBOOT1 0x1F 0x1 R Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT1 0x0 0x10 R Write protection not active Write protection active WRPOT1 0x0 0x10 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBOOT1 0x0F 0x1 W Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT1 0x0 0x10 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 0x0F 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT1 0x0 0x10 RW Write protection not active Write protection active 0x447 STMicroelectronics MCU Cortex-M0+ STM32L07x/L08x/L010 STM32L0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated BFB2 0x17 0x1 R Boot from flash bank 1 boot from flash bank 2 nBOOT1 0x1F 0x1 R Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x20 R Write protection not active Write protection active WRPOT0 0x0 0x20 R read/Write protection active read/Write protection not active WRPOT32 0x0 0x10 R Write protection not active Write protection active WRPOT32 0x0 0x10 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated BFB2 0x7 0x1 W Boot from flash bank 1 boot from flash bank 2 nBOOT1 0x0F 0x1 W Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x10 W Write protection not active Write protection active WRPOT0 0x0 0x10 W read/Write protection active read/Write protection not active WRPOT16 0x0 0x10 W Write protection not active Write protection active WRPOT16 0x0 0x10 W read/Write protection active read/Write protection not active WRPOT32 0x0 0x10 W Write protection not active Write protection active WRPOT32 0x0 0x10 W read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated BFB2 0x7 0x1 RW Boot from flash bank 1 boot from flash bank 2 nBOOT1 0x0F 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x10 RW Write protection not active Write protection active WRPOT0 0x0 0x10 RW read/Write protection active read/Write protection not active WRPOT16 0x0 0x10 RW Write protection not active Write protection active WRPOT16 0x0 0x10 RW read/Write protection active read/Write protection not active WRPOT32 0x0 0x10 RW Write protection not active Write protection active WRPOT32 0x0 0x10 RW read/Write protection active read/Write protection not active 0x430 STMicroelectronics MCU Cortex-M3 STM32F101/F103 XL-density STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Dual 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated BFB2 0x5 0x1 R The device will boot from Flash memory bank 2 when boot pins are set in user Flash position The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated BFB2 0x13 0x1 W The device will boot from Flash memory bank 2 when boot pins are set in user Flash position The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated BFB2 0x13 0x1 RW The device will boot from Flash memory bank 2 when boot pins are set in user Flash position The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default) User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x410 STMicroelectronics MCU Cortex-M3 STM32F101/F102/F103 Medium-density STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x414 STMicroelectronics MCU Cortex-M3 STM32F101/F103 High-density STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x412 STMicroelectronics MCU Cortex-M3 STM32F101/F102/F103 Low-density STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x8 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector 0x418 STMicroelectronics MCU Cortex-M3 STM32F105/F107 Connectivity Line STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x428 STMicroelectronics MCU Cortex-M3 STM32F100 High-density Value Line STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x420 STMicroelectronics MCU Cortex-M3 STM32F100 Low/Medium density Value Line STM32F1 ARM 32-bit Cortex-M3 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x1 0x1 R Flash memory is not read-protected. Flash memory is read-protected. User Configuration WDG_SW 0x2 0x1 R Hardware watchdog Software watchdog nRST_STOP 0x3 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x4 0x1 R Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0xA 0x8 R Data1 User data 1 (8-bit) 0x12 0x8 R Write Protection WRP0 0x0 0x20 R Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 W Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 W Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 W Data1 User data 1 (8-bit) 0x10 0x8 W Write Protection WRP0 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 W Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 W Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 W Write protection active on this sector Write protection not active on this sector Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection User Configuration WDG_SW 0x10 0x1 RW Hardware watchdog Software watchdog nRST_STOP 0x11 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x12 0x1 RW Reset generated when entering Standby mode No reset generated User Data Data0 User data 0 (8-bit) 0x0 0x8 RW Data1 User data 1 (8-bit) 0x10 0x8 RW Write Protection WRP0 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP8 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector WRP16 0x0 0x8 RW Write protection active on this sector Write protection not active on this sector WRP24 0x10 0x8 RW Write protection active on this sector Write protection not active on this sector 0x470 STMicroelectronics MCU Cortex-M4 STM32L4Rxxx/STM32L4Sxxx STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Dual 0x8 Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DB1M Dual-Bank on 1 MB Flash or 512 KB Flash memory devices 0x15 0x1 RW 1 MB or 512 Kb single Flash: contiguous address in bank1 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. DBANK This bit can only be written when PCROPA/B is disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x11 RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x11 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_STRT The address of the last page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DB1M Dual-Bank on 1 MB Flash or 512 KB Flash memory devices 0x15 0x1 RW 1 MB or 512 Kb single Flash: contiguous address in bank1 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. DBANK This bit can only be written when PCROPA/B is disabled. 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x11 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x8 RW 0x471 STMicroelectronics MCU Cortex-M4 STM32L4Pxxx/STM32L4Qxxx STM32L4 ARM 32-bit Cortex-M4 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Dual 0x8 Dual 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DB1M Dual-Bank on 1 MB Flash or 512 KB Flash memory devices 0x15 0x1 RW 1 MB or 512 Kb single Flash: contiguous address in bank1 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. DBANK This bit can only be written when PCROPA/B is disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. 0x17 0x1 RW Boot from embedded SRAM1 when BOOT0=1 Boot from system memory when BOOT0=1 SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_STRT The address of the last page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x11 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog BFB2 0x14 0x1 RW Dual-bank boot disable Dual-bank boot enable DB1M Dual-Bank on 1 MB Flash or 512 KB Flash memory devices 0x15 0x1 RW 1 MB or 512 Kb single Flash: contiguous address in bank1 1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb. DBANK This bit can only be written when PCROPA/B is disabled. 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data nBOOT1 0x17 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory SRAM2_PE 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 This option bit sets the BOOT0 value only when nSWBOOT0=0 0x1B 0x1 RW BOOT0 = 1, boot memory depends on nBOOT1 value BOOT0 = 0, boot from main flash memory PCROP Protection (Bank 1) PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_STRT Flash Bank 1 PCROP start address 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP1_END Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection (Bank 1) WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x7 RW PCROP Protection (Bank 2) PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_STRT Flash Bank 2 PCROP start address 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW PCROP2_END Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x10 RW Write Protection (Bank 2) WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_STRT The address of first page of the Bank 2 WRP first area 0x0 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2A_END The address of last page of the Bank 2 WRP first area 0x10 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_STRT The address of first page of the Bank 2 WRP second area 0x0 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW WRP2B_END The address of last page of the Bank 2 WRP second area 0x10 0x7 RW 0x472 STMicroelectronics MCU Cortex-M33 STM32L5xx STM32L5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0x00 RWE Single Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 Single 0x8 Dual 0x8 Dual 0x8 Single 0x8 Single 0x8 Dual 0x8 Dual 0x8 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0xFF RWE Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK This bit can only be written when all protection (secure, PCROP, HDP) are disabled 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW Secure area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW 0x482 STMicroelectronics MCU Cortex-M33 STM32U5xx STM32U5 ARM 32-bit Cortex-M33 based device Embedded SRAM Storage 0x00 RWE Single Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x10 Dual 0x10 Single 0x10 Dual 0x10 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 Single 0x4 Single 0x4 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode SRAM134_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 0xF 0x1 RW SRAM1, SRAM3 and SRAM4 erased when a system reset occurs SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x15 0x1 RW Single bank Flash with contiguous address in bank 1 Dual-bank Flash with contiguous addresses BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit 0x1D 0x1 RW High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x1E 0x1 RW High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK Bank 1 WPR first area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK Bank 2 WPR first area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the VDD supply level threshold that activates/releases the reset. 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode SRAM134_RST SRAM1, SRAM3 and SRAM4 erase upon system reset 0xF 0x1 RW SRAM1, SRAM3 and SRAM4 erased when a system reset occurs SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x15 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated BKPRAM_ECC SRAM2 parity check enable 0x16 0x1 RW Backup RAM ECC check enabled Backup RAM ECC check disabled SRAM3_ECC SRAM3 ECC detection and correction enable 0x17 0x1 RW SRAM3 ECC check enabled SRAM3 ECC check disabled SRAM2_ECC SRAM2 ECC detection and correction enable 0x18 0x1 RW SRAM2 ECC check enabled SRAM2 ECC check disabled IO_VDD_HSLV High-speed IO at low VDD voltage configuration bit 0x1D 0x1 RW High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V) High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V) IO_VDDIO2_HSLV High-speed IO at low VDDIO2 voltage configuration bit 0x1E 0x1 RW High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V) High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V) TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW BOOT_LOCK The boot is always forced to base address value programmed in SECBOOTADD0 0x0 0x1 RW Boot based on the pad/option bit configuration Boot forced from base address memory Secure Area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW UNLOCK Bank 1 WPR first area A unlock 0x1F 0x1 RW WRP1A start and end pages locked WRP1A start and end pages unlocked WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW UNLOCK Bank 1 WPR first area B unlock 0x1F 0x1 RW WRP1B start and end pages locked WRP1B start and end pages unlocked Secure Area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW UNLOCK Bank 2 WPR first area A unlock 0x1F 0x1 RW WRP2A start and end pages locked WRP2A start and end pages unlocked WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW UNLOCK Bank 2 WPR first area B unlock 0x1F 0x1 RW WRP2B start and end pages locked WRP2B start and end pages unlocked Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1) Level 1, read protection of memories Level 2, chip protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x8 0x3 RW BOR Level 0, reset level threshold is around 1.7 V BOR Level 1, reset level threshold is around 2.0 V BOR Level 2, reset level threshold is around 2.2 V BOR Level 3, reset level threshold is around 2.5 V BOR Level 4, reset level threshold is around 2.8 V User Configuration nRST_STOP 0xC 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xD 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xE 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog SWAP_BANK 0x14 0x1 RW Bank 1 and bank 2 address are not swapped Bank 1 and bank 2 address are swapped DB256 Dual-Bank on 256 Kb Flash memory devices 0x15 0x1 RW 256Kb single Flash: contiguous address in bank1 256Kb dual-bank Flash with contiguous addresses DBANK Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices 0x16 0x1 RW Single bank mode with 128 bits data read width Dual bank mode with 64 bits data SRAM2_PE SRAM2 parity check enable 0x18 0x1 RW SRAM2 parity check enable SRAM2 parity check disable SRAM2_RST SRAM2 Erase when system reset 0x19 0x1 RW SRAM2 erased when a system reset occurs SRAM2 is not erased when a system reset occurs nSWBOOT0 Software BOOT0 0x1A 0x1 RW BOOT0 taken from the option bit nBOOT0 BOOT0 taken from PH3/BOOT0 pin nBOOT0 nBOOT0 option bit 0x1B 0x1 RW nBOOT0 = 0 nBOOT0 = 1 PA15_PUPEN PA15 pull-up enable 0x1C 0x1 RW USB power delivery dead-battery enabled/ TDI pull-up deactivated USB power delivery dead-battery disabled/ TDI pull-up activated TZEN Global TrustZone security enable 0x1F 0x1 RW Global TrustZone security disabled Global TrustZone security enabled HDP1EN Hide protection first area enable 0x1F 0x1 RW No HDP area 1 HDP first area is enabled HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP1_PEND End page of first hide protection area 0x10 0x7 RW HDP2EN Hide protection second area enable 0x1F 0x1 RW No HDP area 2 HDP second area is enabled HDP2_PEND End page of second hide protection area 0x10 0x7 RW HDP2_PEND End page of second hide protection area 0x10 0x7 RW NSBOOTADD0 Non-secure Boot base address 0 0x7 0x19 RW NSBOOTADD1 Non-secure Boot base address 1 0x7 0x19 RW SECBOOTADD0 Secure boot base address 0 0x7 0x19 RW Secure area 1 SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PSTRT Start page of first secure area 0x0 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW SECWM1_PEND End page of first secure area 0x10 0x7 RW Write Protection 1 WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PSTRT Bank 1 WPR first area "A" start page 0x0 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1A_PEND Bank 1 WPR first area "A" end page 0x10 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PSTRT Bank 1 WPR first area "B" start page 0x0 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW WRP1B_PEND Bank 1 WPR first area "B" end page 0x10 0x7 RW Secure area 2 SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PSTRT Start page of second secure area 0x0 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW SECWM2_PEND End page of second secure area 0x10 0x7 RW Write Protection 2 WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PSTRT Bank 2 WPR first area "A" start page 0x0 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2A_PEND Bank 2 WPR first area "A" end page 0x10 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PSTRT Bank 2 WPR first area "B" start page 0x0 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW WRP2B_PEND Bank 2 WPR first area "B" end page 0x10 0x7 RW 0x425 STMicroelectronics MCU Cortex-M0+ STM32L03x/L04x/L010 STM32L0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBOOT1 0x1F 0x1 R Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x8 R Write protection not active Write protection active WRPOT0 0x0 0x8 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBOOT1 0x0F 0x1 W Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x8 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT1 0x0F 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x8 RW Write protection not active Write protection active WRPOT0 0x0 0x8 RW read/Write protection active read/Write protection not active 0x457 STMicroelectronics MCU Cortex-M0+ STM32L01x/L02x STM32L0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0x00 RWE Single 0x4 Data EEPROM Storage The Data EEPROM memory block. It contains user data. 0x00 RWE Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 R Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 R WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x10 0x4 R BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x14 0x1 R Hardware independant watchdog Software independant watchdog nRST_STOP 0x15 0x1 R Reset generated when entering Stop mode No reset generated nRST_STDBY 0x16 0x1 R Reset generated when entering Standby mode No reset generated nBOOT_SEL 0x1D 0x1 R BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0x1E 0x1 R Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 0x1F 0x1 R Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 R Write protection not active Write protection active WRPOT0 0x0 0x4 R read/Write protection active read/Write protection not active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 W Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 W WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 W BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 W Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 W Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 W Reset generated when entering Standby mode No reset generated nBOOT_SEL 0xD 0x1 W BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0xE 0x1 W Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 0x0F 0x1 W Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 W Write protection not active Write protection active Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection PCROP Protection WPRMOD Sector protection mode selection option byte. 0x8 0x1 RW WRPx bit defines sector write protection WRPx bit defines sector read/write (PCROP) protection BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x0 0x4 RW BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold the 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level OFF, reset level threshold for 1.45 V-1.55 V BOR Level 1, reset level threshold for 1.69 V-1.8 V BOR Level 2, reset level threshold for 1.94 V-2.1 V BOR Level 3, reset level threshold for 2.3 V-2.49 V BOR Level 4, reset level threshold for 2.54 V-2.74 V BOR Level 5, reset level threshold for 2.77 V-3.0 V User Configuration IWDG_SW 0x4 0x1 RW Hardware independant watchdog Software independant watchdog nRST_STOP 0x5 0x1 RW Reset generated when entering Stop mode No reset generated nRST_STDBY 0x6 0x1 RW Reset generated when entering Standby mode No reset generated nBOOT_SEL 0x0D 0x1 RW BOOT0 signal is defined by BOOT0 pin value (default mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT0 When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode 0x0E 0x1 RW Main Flash memory is selected as boot area nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area nBOOT1 0x0F 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory Write Protection WRPOT0 0x0 0x4 RW Write protection not active Write protection active WRPOT0 0x0 0x4 RW read/Write protection active read/Write protection not active 0x466 STMicroelectronics MCU Cortex-M0+ STM32G03x/STM32G04x STM32G0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 MirrorOptionBytes Storage Mirror Option Bytes contains the extra area. 0xFF RW Dual 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_HDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x8 RW PCROP1A_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 1 PCROP start address 0x0 0x8 RW PCROP1B_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x8 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x8 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x8 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x8 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x8 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x6 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x6 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x6 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x6 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x6 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x7 RW 0x460 STMicroelectronics MCU Cortex-M0+ STM32G07x/STM32G08x STM32G0 ARM 32-bit Cortex-M0+ based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x8 OTP Storage The Data OTP memory block. It contains the one time programmable bits. 0xFF RW Single 0x4 Option Bytes Configuration RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased PCROP1B_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1B_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x6 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x6 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x6 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x6 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x7 RW Read Out Protection RDP Read protection option byte. The read protection is used to protect the software code stored in Flash memory. 0x0 0x8 RW Level 0, no protection or any value other than 0xAA and 0xCC: Level 1, read protection Level 2, chip protection BOR Level BOR_EN 0x8 0x1 RW Configurable brown out reset disabled, power-on reset defined by POR/PDR levels Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account BORF_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x9 0x2 RW BOR falling level 1 with threshold around 2.0 V BOR falling level 2 with threshold around 2.2 V BOR falling level 3 with threshold around 2.5 V BOR falling level 4 with threshold around 2.8 V BORR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0xB 0x2 RW BOR rising level 1 with threshold around 2.1 V BOR rising level 2 with threshold around 2.3 V BOR rising level 3 with threshold around 2.6 V BOR rising level 4 with threshold around 2.9 V User Configuration nRST_STOP 0xD 0x1 RW Reset generated when entering Stop mode No reset generated when entering Stop mode nRST_STDBY 0xE 0x1 RW Reset generated when entering Standby mode No reset generated when entering Standby mode nRST_SHDW 0xF 0x1 RW Reset generated when entering the Shutdown mode No reset generated when entering the Shutdown mode IWDG_SW 0x10 0x1 RW Hardware independant watchdog Software independant watchdog IWDG_STOP 0x11 0x1 RW Freeze IWDG counter in stop mode IWDG counter active in stop mode IWDG_STDBY 0x12 0x1 RW Freeze IWDG counter in standby mode IWDG counter active in standby mode WWDG_SW 0x13 0x1 RW Hardware window watchdog Software window watchdog RAM_PARITY_CHECK 0x16 0x1 RW SRAM2 parity check enable SRAM2 parity check disable nBOOT_SEL 0x18 0x1 RW BOOT0 signal is defined by BOOT0 pin value (legacy mode) BOOT0 signal is defined by nBOOT0 option bit nBOOT1 0x19 0x1 RW Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1 Boot from Flash if BOOT0 = 0, otherwise system memory nBOOT0 0x1A 0x1 RW nBOOT0=0 nBOOT0=1 NRST_MODE 0x1B 0x2 RW Reserved Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin GPIO: standard GPIO pad functionality, only internal RESET possible Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode) IRHEN Internal reset holder enable bit 0x1D 0x1 RW Internal resets are propagated as simple pulse on NRST pin Internal resets drives NRST pin low until it is seen as low level PCROP Protection PCROP1A_STRT Flash Bank 1 PCROP start address 0x0 0x9 RW PCROP1A_END Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0 0x0 0x9 RW PCROP_RDP 0x1F 0x1 RW PCROP zone is kept when RDP is decreased PCROP zone is erased when RDP is decreased Write Protection WRP1A_STRT The address of the first page of the Bank 1 WRP first area 0x0 0x6 RW WRP1A_END The address of the last page of the Bank 1 WRP first area 0x10 0x6 RW WRP1B_STRT The address of the first page of the Bank 1 WRP second area 0x0 0x6 RW WRP1B_END The address of the last page of the Bank 1 WRP second area 0x10 0x6 RW FLASH security BOOT_LOCK used to force boot from user area 0x10 0x1 RW Boot based on the pad/option bit configuration Boot forced from Main Flash memory SEC_SIZE Securable memory area size 0x0 0x7 RW 0x500 STMicroelectronics MPU Cortex-A7 STM32MPxxx STM32MP ARM 32-bit Cortex-A7 and ARM 32-bit Cortex-M4 dualprocessor based device, CPU clock up to 600MHz OTP Memory Configuration RW OTP none none 0x0 0x20 R TR set SAFMEM Ring current level, default value = 0b00 0x7 0x2 RW PRGWIDTH SAFMEM Programming Pulse Width, default value = 0b0001 0x3 0x4 RW FRC SAFMEM CLOCK frequency range selection, default value = 0b11 0x1 0x2 RW PWRUP SAFMEM Power up control 0x0 0x1 RW BIST2LOCK 0: BIST2 is not locked, 1: BIST2 is locked. 0x7 0x1 R BIST1LOCK 0: BIST1 is not locked, 1: BIST1 is locked. 0x6 0x1 R PWRON 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. 0x5 0x1 R PROGFAIL 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. 0x4 0x1 R BUSY 0: SAFMEM is Idle, 1: SAFMEM operation is on going. 0x3 0x1 R INVALID 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. 0x2 0x1 R FULLDBG 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. 0x1 0x1 R SECURE 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. 0x0 0x1 R GPLOCK 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. 0x4 0x1 RW FENREG 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. 0x3 0x1 RW DENREG 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. 0x2 0x1 RW OTP 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. 0x0 0x1 RW DBGSWENABLE Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. 0xA 0x1 RW CFGSDISABLE Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. 0x9 0x1 RW CP15SDISABLE Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. 0x7 0x2 RW SPNIDEN Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. 0x6 0x1 RW SPIDEN Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. 0x5 0x1 RW HDPEN Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. 0x4 0x1 RW DEVICEEN Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. 0x3 0x1 RW NIDEN Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. 0x2 0x1 RW DBGEN Debug enable with signal dbgen. 0: Disabled, 1: Enabled. 0x1 0x1 RW DFTEN DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. 0x0 0x1 RW CAN_disable 0: CAN interface is enabled, 1: CAN interface is disabled. 0x3 0x1 RW GPU_disable 0: GPU enabled, 1: GPU disabled. 0x2 0x1 RW Dual_A7_disable 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. 0x1 0x1 RW Crypto_disable 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. 0x0 0x1 RW W_R conf This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM 0x0 0x1 RW BSEC_OTP_DISTURBED0 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_DISTURBED1 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_DISTURBED2 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_ERROR0 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_ERROR1 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_ERROR2 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_WRLOCK0 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_WRLOCK1 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_WRLOCK2 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_SPLOCK0 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SPLOCK1 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SPLOCK2 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK0 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK1 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK2 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SRLOCK0 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW BSEC_OTP_SRLOCK1 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW BSEC_OTP_SRLOCK2 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW CFG0 These bits determins the OTP mode encoding 0x0 0x7 RW fdis3 Disable CAN 0x3 0x1 RW fdis2 Disable GPU 0x2 0x1 RW fdis1 Disable CPU1 0x1 0x1 RW fdis0 Disable Crypto (license export) 0x0 0x1 RW rma_force RMA force Bit 0x0 0x1 RW rma_relock RMA relock Bit 0x1 0x1 RW CFG3 These bits determins the BOOT source definition 0x0 0x20 RW CFG4 These bits determins the BOOT monotonic counter 0x0 0x20 RW CFG5 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG6 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG7 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG8 BOOT/Device configuration. 0x2 0x1E RW rma_relock RMA relock Bit 0x1 0x1 RW rma_lock RMA lock Bit 0x0 0x1 RW CFG9 These bits determin the device configuration. 0x0 0x20 RW CFG10 These bits determin the device configuration. 0x0 0x20 RW CFG11 These bits determin the device configuration. 0x0 0x20 RW CFG12 These bits determin the device configuration. 0x0 0x20 RW ID0 Lot ID on 42bit (11LSB's) 0x15 0xB RW ID0 Wafer ID 0x10 0x5 RW ID0 Wafer Y coordinates 0x8 0x8 RW ID0 Wafer X coordinates 0x0 0x8 RW ID1 Lot ID on 42bit (31MSB's) 0x0 0x20 RW ID2 Test program flow T[12],F[12],Q[12] 0x14 0xC RW ID2 FT program revision 0xA 0xA RW ID2 EWS program revision 0x0 0xA RW HW0 Analog TRIM 0x0 0x20 RW HW1 Analog TRIM 0x0 0x20 RW HW2 Analog TRIM and hardware options 0x0 0x20 RW HW3 Analog TRIM 0x0 0x20 RW HW4 not used yet 0x0 0x20 RW HW5 memory repair bits 0x0 0x20 RW HW6 memory repair bits 0x0 0x20 RW HW7 reserved 0x0 0x20 RW PKH0 Public Key Hash 0x0 0x20 RW PKH1 Public Key Hash 0x0 0x20 RW PKH2 Public Key Hash 0x0 0x20 RW PKH3 Public Key Hash 0x0 0x20 RW PKH4 Public Key Hash 0x0 0x20 RW PKH5 Public Key Hash 0x0 0x20 RW PKH6 Public Key Hash 0x0 0x20 RW PKH7 Public Key Hash 0x0 0x20 RW XK0 ST ECDSA Private Key for SSP 0x0 0x20 RW XK1 ST ECDSA Private Key for SSP 0x0 0x20 RW XK2 ST ECDSA Private Key for SSP 0x0 0x20 RW XK3 ST ECDSA Private Key for SSP 0x0 0x20 RW XK4 ST ECDSA Private Key for SSP 0x0 0x20 RW XK5 ST ECDSA Private Key for SSP 0x0 0x20 RW XK6 ST ECDSA Private Key for SSP 0x0 0x20 RW XK7 ST ECDSA Private Key for SSP 0x0 0x20 RW XK8 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK9 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK10 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK11 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK12 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK13 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK14 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK15 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK16 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK17 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK18 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK19 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK20 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK21 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK22 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK23 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK24 RMA lock and relock passwords 0x0 0x20 RW XK25 OEM OTP secret word 0x0 0x20 RW XK26 OEM OTP secret word 0x0 0x20 RW XK27 OEM OTP secret word 0x0 0x20 RW XK28 OEM OTP secret word 0x0 0x20 RW XK29 OEM OTP secret word 0x0 0x20 RW XK30 OEM OTP secret word 0x0 0x20 RW XK31 OEM OTP secret word 0x0 0x20 RW XK32 OEM OTP secret word 0x0 0x20 RW XK33 OEM OTP secret word 0x0 0x20 RW XK34 OEM OTP secret word 0x0 0x20 RW XK35 OEM OTP secret word 0x0 0x20 RW XK36 OEM OTP secret word 0x0 0x20 RW XK37 OEM OTP secret word 0x0 0x20 RW XK38 OEM OTP secret word 0x0 0x20 RW XK39 OEM OTP secret word 0x0 0x20 RW XK40 OEM OTP secret word 0x0 0x20 RW XK41 OEM OTP secret word 0x0 0x20 RW XK42 OEM OTP secret word 0x0 0x20 RW XK43 OEM OTP secret word 0x0 0x20 RW XK44 OEM OTP secret word 0x0 0x20 RW XK45 OEM OTP secret word 0x0 0x20 RW XK46 OEM OTP secret word 0x0 0x20 RW XK47 OEM OTP secret word 0x0 0x20 RW XK48 OEM OTP secret word 0x0 0x20 RW XK49 OEM OTP secret word 0x0 0x20 RW XK50 OEM OTP secret word 0x0 0x20 RW XK51 OEM OTP secret word 0x0 0x20 RW XK52 OEM OTP secret word 0x0 0x20 RW XK53 OEM OTP secret word 0x0 0x20 RW XK54 OEM OTP secret word 0x0 0x20 RW XK55 OEM OTP secret word 0x0 0x20 RW XK56 OEM OTP secret word 0x0 0x20 RW XK57 OEM OTP secret word 0x0 0x20 RW XK58 OEM OTP secret word 0x0 0x20 RW XK59 OEM OTP secret word 0x0 0x20 RW XK60 OEM OTP secret word 0x0 0x20 RW XK61 OEM OTP secret word 0x0 0x20 RW XK62 OEM OTP secret word 0x0 0x20 RW XK63 OEM OTP secret word 0x0 0x20 RW ECC_USE SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. 0x4 0x4 R SAFMEM_SIZE SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. 0x0 0x4 R MAJREV IP Version major revision information. 0x4 0x4 R MINREV IP Version minor revision information. 0x0 0x4 R ID IP Identification. 0x0 0x20 R ID IP Magic Identification. 0x0 0x20 R