0x485 STMicroelectronics MCU Cortex-M7 STM32H7Rxx STM32H7 ARM 32-bit Cortex-M7 based device Embedded SRAM Storage 0x00 RWE Single Embedded Flash Storage The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms 0xFF RWE Single 0x80 Option Bytes Configuration RW Flash Non Volatile State FLASH_NVSR FLASH security status register programming. 0x0 0x8 R OPEN device CLOSED device FLASH_NVSR FLASH security status register programming. 0x0 0x8 W OPEN device CLOSED device BOR Level BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 R BOR OFF BOR level1: 2.1V BOR level2: 2.4 V BOR level3: 2.7 V BOR_LEV These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory 0x2 0x2 W reset level is set to 0.0 V reset level is set to 2.1 V reset level is set to 2.4 V reset level is set to 2.7 V User Configuration1 IWDG1_SW 0x4 0x1 R Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 R STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 R STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 R Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 R Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 R Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode OCTO1_HSLV 0x8 0x1 R I/O Octo1 High-Speed option disabled I/O Octo1 High-Speed option enabled OCTO2_HSLV 0x9 0x1 R I/O Octo2 High-Speed option disabled I/O Octo2 High-Speed option enabled IWDG1_SW 0x4 0x1 W Independent watchdog is controlled by hardware Independent watchdog is controlled by software NRST_STOP 0x6 0x1 W STOP mode on Domain 1 is entering with reset STOP mode on Domain 1 is entering without reset NRST_STBY 0x7 0x1 W STANDBY mode on Domain 1 is entering with reset STANDBY mode on Domain 1 is entering without reset IO_HSLV 0x1D 0x1 W Product working in the full voltage range, I/O speed optimization at low-voltage disabled Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed FZ_IWDG_STOP 0x11 0x1 W Independent watchdog is freezed in STOP mode Independent watchdog is running in STOP mode FZ_IWDG_SDBY 0x12 0x1 W Independent watchdog is freezed in STANDBY mode Independent watchdog is running in STANDBY mode OCTO1_HSLV 0x8 0x1 W I/O Octo1 High-Speed option disabled I/O Octo1 High-Speed option enabled OCTO2_HSLV 0x9 0x1 W I/O Octo2 High-Speed option disabled I/O Octo2 High-Speed option enabled User Configuration 2 I2c_NI3C 0x9 0x1 R I3C is selected I2C is delected ECC_ON_SRAM 0x8 0x1 R ECC_ON_SRAM disabled ECC_ON_SRAM enabled I2c_NI3C 0x9 0x1 W I3C is selected I2C is delected ECC_ON_SRAM 0x8 0x1 W ECC_ON_SRAM disabled ECC_ON_SRAM enabled DTCM RAM Protection DTCM_AXI_SHARE 0x4 0x3 R 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code DTCM_AXI_SHARE 0x4 0x3 W 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code ITCM RAM Protection ITCM_AXI_SHARE 0x0 0x3 R 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code ITCM_AXI_SHARE 0x0 0x3 W 2 KB reserved to ST code 4 KB reserved to ST code 8 KB reserved to ST code 16 KB reserved to ST code Write Protection nWRP0 0x0 0x8 R Write protection active Write protection not active nWRP0 0x0 0x8 W Write protection active Write protection not active Flash HDP bank HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x9 R HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x9 R HDP1_STRT TIL barrier start set in number of 8kb sectors 0x0 0x9 W HDP1_END TIL barrier end set in number of 8kb sectors 0x10 0x9 W Flash EPOCH EPOCH Non Volatile Non Secure EPOCH counter 0x0 0x18 R EPOCH Non Volatile Secure EPOCH counter 0x0 0x18 W OTP write protection LOCKBL OTP Lock 0x0 0x10 R LOCKBL OTP Lock 0x0 0x10 W FLASH ROT programming OEM_PROV OEM provisioned device 0x0 0x8 R IROT_SELECT OEM provisioned device 0x18 0x8 R DBG_AUTH Debug authentication method 0x8 0x8 R IROT_SELECT OEM provisioned device 0x18 0x8 W DBG_AUTH Debug authentication method 0x8 0x8 W OEM_PROV OEM provisioned device 0x0 0x8 W FLASH fixed bank NUM_FIXED_SECT Number of fixed sectors 0x1 0x3 R EN_SWAP_BANK enable swap bank 0x10 0x1 R swap bank disable swap bank enable LOCK_FIXED lock fixed 0x14 0x1 R lock disable lock enable NUM_FIXED_SECT Number of fixed sectors 0x1 0x3 W EN_SWAP_BANK enable swap bank 0x10 0x1 W swap bank disable swap bank enable LOCK_FIXED lock fixed 0x14 0x1 W lock disable lock enable