0x500 STMicroelectronics MPU Cortex-A7 STM32MP1 STM32MP ARM 32-bit Cortex-A7 and ARM 32-bit Cortex-M4 dualprocessor based device, CPU clock up to 600MHz Embedded SRAM Storage 0xFF RWE Single OTP Memory Configuration RW OTP none none 0x0 0x20 R TR set SAFMEM Ring current level, default value = 0b00 0x7 0x2 RW PRGWIDTH SAFMEM Programming Pulse Width, default value = 0b0001 0x3 0x4 RW FRC SAFMEM CLOCK frequency range selection, default value = 0b11 0x1 0x2 RW PWRUP SAFMEM Power up control 0x0 0x1 RW BIST2LOCK 0: BIST2 is not locked, 1: BIST2 is locked. 0x7 0x1 R BIST1LOCK 0: BIST1 is not locked, 1: BIST1 is locked. 0x6 0x1 R PWRON 0: SAFMEM is in Power Off, 1: SAFMEM is in Power On. 0x5 0x1 R PROGFAIL 0: SAFMEM last programming was successful, 1: SAFMEM last programming failed. 0x4 0x1 R BUSY 0: SAFMEM is Idle, 1: SAFMEM operation is on going. 0x3 0x1 R INVALID 0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID. 0x2 0x1 R FULLDBG 0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2. 0x1 0x1 R SECURE 0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED. 0x0 0x1 R GPLOCK 0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste. 0x4 0x1 RW FENREG 0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset. 0x3 0x1 RW DENREG 0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset. 0x2 0x1 RW OTP 0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM. 0x0 0x1 RW DBGSWENABLE Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses. 0xA 0x1 RW CFGSDISABLE Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers. 0x9 0x1 RW CP15SDISABLE Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU. 0x7 0x2 RW SPNIDEN Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled. 0x6 0x1 RW SPIDEN Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled. 0x5 0x1 RW HDPEN Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled. 0x4 0x1 RW DEVICEEN Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled. 0x3 0x1 RW NIDEN Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled. 0x2 0x1 RW DBGEN Debug enable with signal dbgen. 0: Disabled, 1: Enabled. 0x1 0x1 RW DFTEN DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled. 0x0 0x1 RW CAN_disable 0: CAN interface is enabled, 1: CAN interface is disabled. 0x3 0x1 RW GPU_disable 0: GPU enabled, 1: GPU disabled. 0x2 0x1 RW Dual_A7_disable 0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU. 0x1 0x1 RW Crypto_disable 0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control. 0x0 0x1 RW W_R conf This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM 0x0 0x1 RW BSEC_OTP_DISTURBED0 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_DISTURBED1 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_DISTURBED2 If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected 0x0 0x20 R BSEC_OTP_ERROR0 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_ERROR1 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_ERROR2 If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error. 0x0 0x20 R BSEC_OTP_WRLOCK0 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_WRLOCK1 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_WRLOCK2 If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock. 0x0 0x20 RW BSEC_OTP_SPLOCK0 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SPLOCK1 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SPLOCK2 If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK0 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK1 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SWLOCK2 If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset 0x0 0x20 RW BSEC_OTP_SRLOCK0 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW BSEC_OTP_SRLOCK1 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW BSEC_OTP_SRLOCK2 If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register 0x0 0x20 RW CFG0 These bits determins the OTP mode encoding 0x0 0x7 RW fdis3 Disable CAN 0x3 0x1 RW fdis2 Disable GPU 0x2 0x1 RW fdis1 Disable CPU1 0x1 0x1 RW fdis0 Disable Crypto (license export) 0x0 0x1 RW rma_force RMA force Bit 0x0 0x1 RW rma_relock RMA relock Bit 0x1 0x1 RW CFG3 These bits determins the BOOT source definition 0x0 0x20 RW CFG4 These bits determins the BOOT monotonic counter 0x0 0x20 RW CFG5 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG6 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG7 These bits determins the BOOT AFmux configuration 0x0 0x20 RW CFG8 BOOT/Device configuration. 0x2 0x1E RW rma_relock RMA relock Bit 0x1 0x1 RW rma_lock RMA lock Bit 0x0 0x1 RW CFG9 These bits determin the device configuration. 0x0 0x20 RW CFG10 These bits determin the device configuration. 0x0 0x20 RW CFG11 These bits determin the device configuration. 0x0 0x20 RW CFG12 These bits determin the device configuration. 0x0 0x20 RW ID0 Lot ID on 42bit (11LSB's) 0x15 0xB RW ID0 Wafer ID 0x10 0x5 RW ID0 Wafer Y coordinates 0x8 0x8 RW ID0 Wafer X coordinates 0x0 0x8 RW ID1 Lot ID on 42bit (31MSB's) 0x0 0x20 RW ID2 Test program flow T[12],F[12],Q[12] 0x14 0xC RW ID2 FT program revision 0xA 0xA RW ID2 EWS program revision 0x0 0xA RW HW0 Analog TRIM 0x0 0x20 RW HW1 Analog TRIM 0x0 0x20 RW HW2 Analog TRIM and hardware options 0x0 0x20 RW HW3 Analog TRIM 0x0 0x20 RW HW4 not used yet 0x0 0x20 RW HW5 memory repair bits 0x0 0x20 RW HW6 memory repair bits 0x0 0x20 RW HW7 reserved 0x0 0x20 RW PKH0 Public Key Hash 0x0 0x20 RW PKH1 Public Key Hash 0x0 0x20 RW PKH2 Public Key Hash 0x0 0x20 RW PKH3 Public Key Hash 0x0 0x20 RW PKH4 Public Key Hash 0x0 0x20 RW PKH5 Public Key Hash 0x0 0x20 RW PKH6 Public Key Hash 0x0 0x20 RW PKH7 Public Key Hash 0x0 0x20 RW XK0 ST ECDSA Private Key for SSP 0x0 0x20 RW XK1 ST ECDSA Private Key for SSP 0x0 0x20 RW XK2 ST ECDSA Private Key for SSP 0x0 0x20 RW XK3 ST ECDSA Private Key for SSP 0x0 0x20 RW XK4 ST ECDSA Private Key for SSP 0x0 0x20 RW XK5 ST ECDSA Private Key for SSP 0x0 0x20 RW XK6 ST ECDSA Private Key for SSP 0x0 0x20 RW XK7 ST ECDSA Private Key for SSP 0x0 0x20 RW XK8 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK9 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK10 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK11 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK12 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK13 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK14 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK15 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK16 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK17 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK18 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK19 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK20 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK21 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK22 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK23 ST Public ECDSA Chip Certificate for SSP 0x0 0x20 RW XK24 RMA lock and relock passwords 0x0 0x20 RW XK25 OEM OTP secret word 0x0 0x20 RW XK26 OEM OTP secret word 0x0 0x20 RW XK27 OEM OTP secret word 0x0 0x20 RW XK28 OEM OTP secret word 0x0 0x20 RW XK29 OEM OTP secret word 0x0 0x20 RW XK30 OEM OTP secret word 0x0 0x20 RW XK31 OEM OTP secret word 0x0 0x20 RW XK32 OEM OTP secret word 0x0 0x20 RW XK33 OEM OTP secret word 0x0 0x20 RW XK34 OEM OTP secret word 0x0 0x20 RW XK35 OEM OTP secret word 0x0 0x20 RW XK36 OEM OTP secret word 0x0 0x20 RW XK37 OEM OTP secret word 0x0 0x20 RW XK38 OEM OTP secret word 0x0 0x20 RW XK39 OEM OTP secret word 0x0 0x20 RW XK40 OEM OTP secret word 0x0 0x20 RW XK41 OEM OTP secret word 0x0 0x20 RW XK42 OEM OTP secret word 0x0 0x20 RW XK43 OEM OTP secret word 0x0 0x20 RW XK44 OEM OTP secret word 0x0 0x20 RW XK45 OEM OTP secret word 0x0 0x20 RW XK46 OEM OTP secret word 0x0 0x20 RW XK47 OEM OTP secret word 0x0 0x20 RW XK48 OEM OTP secret word 0x0 0x20 RW XK49 OEM OTP secret word 0x0 0x20 RW XK50 OEM OTP secret word 0x0 0x20 RW XK51 OEM OTP secret word 0x0 0x20 RW XK52 OEM OTP secret word 0x0 0x20 RW XK53 OEM OTP secret word 0x0 0x20 RW XK54 OEM OTP secret word 0x0 0x20 RW XK55 OEM OTP secret word 0x0 0x20 RW XK56 OEM OTP secret word 0x0 0x20 RW XK57 OEM OTP secret word 0x0 0x20 RW XK58 OEM OTP secret word 0x0 0x20 RW XK59 OEM OTP secret word 0x0 0x20 RW XK60 OEM OTP secret word 0x0 0x20 RW XK61 OEM OTP secret word 0x0 0x20 RW XK62 OEM OTP secret word 0x0 0x20 RW XK63 OEM OTP secret word 0x0 0x20 RW ECC_USE SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved. 0x4 0x4 R SAFMEM_SIZE SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved. 0x0 0x4 R MAJREV IP Version major revision information. 0x4 0x4 R MINREV IP Version minor revision information. 0x0 0x4 R ID IP Identification. 0x0 0x20 R ID IP Magic Identification. 0x0 0x20 R