STM32_Prog_DB_0x451.xml 22 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x451</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32F76x/STM32F77x</Name>
  9. <Series>STM32F7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- 2MB Single Bank-->
  15. <DualBank reference="0x1">
  16. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x20000000"/>
  17. </DualBank>
  18. </Configuration>
  19. <Configuration number="0x1"> <!-- 2MB Dual Bank-->
  20. <DualBank reference="0x0">
  21. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x0"/>
  22. </DualBank>
  23. </Configuration>
  24. </Interface>
  25. <!-- Bootloader Interface -->
  26. <Interface name="Bootloader">
  27. <Configuration number="0x0"> <!-- 2MB Single Bank-->
  28. <DualBank reference="0x1">
  29. <ReadRegister address="0x1FFF0008" mask="0x2000" value="0x2000"/>
  30. </DualBank>
  31. </Configuration>
  32. <Configuration number="0x1"> <!-- 2MB Dual Bank-->
  33. <DualBank reference="0x0">
  34. <ReadRegister address="0x1FFF0008" mask="0x2000" value="0x0"/>
  35. </DualBank>
  36. </Configuration>
  37. </Interface>
  38. </Configurations>
  39. <!-- Peripherals -->
  40. <Peripherals>
  41. <!-- Embedded SRAM -->
  42. <Peripheral>
  43. <Name>Embedded SRAM</Name>
  44. <Type>Storage</Type>
  45. <Description/>
  46. <ErasedValue>0x00</ErasedValue>
  47. <Access>RWE</Access>
  48. <!-- 512 KB -->
  49. <Configuration>
  50. <Parameters address="0x20000000" name="SRAM" size="0x80000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Bank name="Bank 1">
  54. <Field>
  55. <Parameters address="0x20000000" name="SRAM1" occurence="0x1" size="0x80000"/>
  56. </Field>
  57. </Bank>
  58. </Configuration>
  59. </Peripheral>
  60. <!-- Embedded Flash -->
  61. <Peripheral>
  62. <Name>Embedded Flash</Name>
  63. <Type>Storage</Type>
  64. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  65. <ErasedValue>0xFF</ErasedValue>
  66. <Access>RWE</Access>
  67. <FlashSize address="0x1FF0F442" default="0x200000"/>
  68. <!-- 2MB Single Bank -->
  69. <Configuration config="0">
  70. <Parameters address="0x08000000" name=" 2 Mbytes single bank Embedded Flash" size="0x200000"/>
  71. <Description/>
  72. <Organization>Single</Organization>
  73. <Allignement>0x20</Allignement>
  74. <Bank name="Bank 1">
  75. <Field>
  76. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x8000"/>
  77. </Field>
  78. <Field>
  79. <Parameters address="0x08020000" name="sector4" occurence="0x1" size="0x20000"/>
  80. </Field>
  81. <Field>
  82. <Parameters address="0x08040000" name="sector5" occurence="0x7" size="0x40000"/>
  83. </Field>
  84. </Bank>
  85. </Configuration>
  86. <!-- 2MB Dual Bank -->
  87. <Configuration config="1">
  88. <Parameters address="0x08000000" name=" 2 Mbytes dual bank Embedded Flash" size="0x200000"/>
  89. <Description/>
  90. <Organization>Dual</Organization>
  91. <Allignement>0x10</Allignement>
  92. <Bank name="Bank 1">
  93. <Field>
  94. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  95. </Field>
  96. <Field>
  97. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  98. </Field>
  99. <Field>
  100. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  101. </Field>
  102. </Bank>
  103. <Bank name="Bank 2">
  104. <Field>
  105. <Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
  106. </Field>
  107. <Field>
  108. <Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
  109. </Field>
  110. <Field>
  111. <Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
  112. </Field>
  113. </Bank>
  114. </Configuration>
  115. </Peripheral>
  116. <!-- ITCM FLASH -->
  117. <Peripheral>
  118. <Name>ITCM Flash</Name>
  119. <Type>Storage</Type>
  120. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  121. <ErasedValue>0xFF</ErasedValue>
  122. <Access>RWE</Access>
  123. <!-- 2MB Single Bank -->
  124. <Configuration config="0">
  125. <Parameters address="0x00200000" name=" 2 Mbytes single bank Embedded Flash" size="0x200000"/>
  126. <Description/>
  127. <Organization>Single</Organization>
  128. <Allignement>0x20</Allignement>
  129. <Bank name="Bank 1">
  130. <Field>
  131. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x8000"/>
  132. </Field>
  133. <Field>
  134. <Parameters address="0x00220000" name="sector4" occurence="0x1" size="0x20000"/>
  135. </Field>
  136. <Field>
  137. <Parameters address="0x00240000" name="sector5" occurence="0x7" size="0x40000"/>
  138. </Field>
  139. </Bank>
  140. </Configuration>
  141. <!-- 2MB Dual Bank -->
  142. <Configuration config="1">
  143. <Parameters address="0x00200000" name=" 2 Mbytes dual bank Embedded Flash" size="0x200000"/>
  144. <Description/>
  145. <Organization>Dual</Organization>
  146. <Allignement>0x10</Allignement>
  147. <Bank name="Bank 1">
  148. <Field>
  149. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
  150. </Field>
  151. <Field>
  152. <Parameters address="0x00210000" name="sector4" occurence="0x1" size="0x10000"/>
  153. </Field>
  154. <Field>
  155. <Parameters address="0x00220000" name="sector5" occurence="0x7" size="0x20000"/>
  156. </Field>
  157. </Bank>
  158. <Bank name="Bank 2">
  159. <Field>
  160. <Parameters address="0x00300000" name="sector12" occurence="0x4" size="0x4000"/>
  161. </Field>
  162. <Field>
  163. <Parameters address="0x00310000" name="sector16" occurence="0x1" size="0x10000"/>
  164. </Field>
  165. <Field>
  166. <Parameters address="0x00320000" name="sector17" occurence="0x7" size="0x20000"/>
  167. </Field>
  168. </Bank>
  169. </Configuration>
  170. </Peripheral>
  171. <!-- OTP -->
  172. <Peripheral>
  173. <Name>OTP</Name>
  174. <Type>Storage</Type>
  175. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  176. <ErasedValue>0xFF</ErasedValue>
  177. <Access>RW</Access>
  178. <!-- 1 KBytes single bank -->
  179. <Configuration>
  180. <Parameters address="0x1FF0F000" name=" 1 KBytes Data OTP" size="0x400"/>
  181. <Description/>
  182. <Organization>Single</Organization>
  183. <Allignement>0x4</Allignement>
  184. <Bank name="OTP">
  185. <Field>
  186. <Parameters address="0x1FF0F000" name="OTP" occurence="0x1" size="0x400"/>
  187. </Field>
  188. </Bank>
  189. </Configuration>
  190. </Peripheral>
  191. <!-- Mirror Option Bytes -->
  192. <Peripheral>
  193. <Name>MirrorOptionBytes</Name>
  194. <Type>Storage</Type>
  195. <Description>Mirror Option Bytes contains the extra area.</Description>
  196. <ErasedValue>0xFF</ErasedValue>
  197. <Access>RW</Access>
  198. <!-- 44 Bytes single bank -->
  199. <Configuration>
  200. <Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
  201. <Description/>
  202. <Organization>Single</Organization>
  203. <Allignement>0x4</Allignement>
  204. <Bank name="MirrorOptionBytes">
  205. <Field>
  206. <Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurence="0x1" size="0x2C"/>
  207. </Field>
  208. </Bank>
  209. </Configuration>
  210. </Peripheral>
  211. <!-- Option Bytes -->
  212. <Peripheral>
  213. <Name>Option Bytes</Name>
  214. <Type>Configuration</Type>
  215. <Description/>
  216. <Access>RW</Access>
  217. <Bank interface="JTAG_SWD">
  218. <Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
  219. <Category>
  220. <Name>Read Out Protection</Name>
  221. <Field>
  222. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  223. <AssignedBits>
  224. <Bit>
  225. <Name>RDP</Name>
  226. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  227. <BitOffset>0x8</BitOffset>
  228. <BitWidth>0x8</BitWidth>
  229. <Access>RW</Access>
  230. <Values>
  231. <Val value="0xAA">Level 0, no protection</Val>
  232. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  233. <Val value="0xCC">Level 2, chip protection</Val>
  234. </Values>
  235. </Bit>
  236. </AssignedBits>
  237. </Field>
  238. </Category>
  239. <Category>
  240. <Name>BOR Level</Name>
  241. <Field>
  242. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  243. <AssignedBits>
  244. <Bit>
  245. <Name>BOR_LEV</Name>
  246. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  247. <BitOffset>0x2</BitOffset>
  248. <BitWidth>0x2</BitWidth>
  249. <Access>RW</Access>
  250. <Values>
  251. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  252. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  253. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  254. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  255. </Values>
  256. </Bit>
  257. </AssignedBits>
  258. </Field>
  259. </Category>
  260. <Category>
  261. <Name>User Configuration</Name>
  262. <Field>
  263. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  264. <AssignedBits>
  265. <Bit>
  266. <Name>IWDG_STOP</Name>
  267. <Description/>
  268. <BitOffset>0x1F</BitOffset>
  269. <BitWidth>0x1</BitWidth>
  270. <Access>RW</Access>
  271. <Values>
  272. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  273. <Val value="0x1">IWDG counter active in stop mode</Val>
  274. </Values>
  275. </Bit>
  276. <Bit>
  277. <Name>IWDG_STDBY</Name>
  278. <Description/>
  279. <BitOffset>0x1E</BitOffset>
  280. <BitWidth>0x1</BitWidth>
  281. <Access>RW</Access>
  282. <Values>
  283. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  284. <Val value="0x1">IWDG counter active in standby mode</Val>
  285. </Values>
  286. </Bit>
  287. <Bit reference="DualBank">
  288. <Name>nDBANK</Name>
  289. <Description/>
  290. <BitOffset>0x1D</BitOffset>
  291. <BitWidth>0x1</BitWidth>
  292. <Access>RW</Access>
  293. <Values>
  294. <Val value="0x0">Flash in dual bank with 128 bits read access</Val>
  295. <Val value="0x1">Flash in single bank with 256 bits read access</Val>
  296. </Values>
  297. </Bit>
  298. <Bit config="1">
  299. <Name>nDBOOT</Name>
  300. <Description/>
  301. <BitOffset>0x1C</BitOffset>
  302. <BitWidth>0x1</BitWidth>
  303. <Access>RW</Access>
  304. <Values>
  305. <Val value="0x0">Dual Boot enabled</Val>
  306. <Val value="0x1">Dual Boot disabled</Val>
  307. </Values>
  308. </Bit>
  309. <Bit>
  310. <Name>WWDG_SW</Name>
  311. <Description/>
  312. <BitOffset>0x4</BitOffset>
  313. <BitWidth>0x1</BitWidth>
  314. <Access>RW</Access>
  315. <Values>
  316. <Val value="0x0">Hardware window watchdog</Val>
  317. <Val value="0x1">Software window watchdog</Val>
  318. </Values>
  319. </Bit>
  320. <Bit>
  321. <Name>IWDG_SW</Name>
  322. <Description/>
  323. <BitOffset>0x5</BitOffset>
  324. <BitWidth>0x1</BitWidth>
  325. <Access>RW</Access>
  326. <Values>
  327. <Val value="0x0">Hardware independant watchdog</Val>
  328. <Val value="0x1">Software independant watchdog</Val>
  329. </Values>
  330. </Bit>
  331. <Bit>
  332. <Name>nRST_STOP</Name>
  333. <Description/>
  334. <BitOffset>0x6</BitOffset>
  335. <BitWidth>0x1</BitWidth>
  336. <Access>RW</Access>
  337. <Values>
  338. <Val value="0x0">Reset generated when entering Stop mode</Val>
  339. <Val value="0x1">No reset generated</Val>
  340. </Values>
  341. </Bit>
  342. <Bit>
  343. <Name>nRST_STDBY</Name>
  344. <Description/>
  345. <BitOffset>0x7</BitOffset>
  346. <BitWidth>0x1</BitWidth>
  347. <Access>RW</Access>
  348. <Values>
  349. <Val value="0x0">Reset generated when entering Standby mode</Val>
  350. <Val value="0x1">No reset generated</Val>
  351. </Values>
  352. </Bit>
  353. </AssignedBits>
  354. </Field>
  355. </Category>
  356. <Category>
  357. <Name>Boot address Option Bytes</Name>
  358. <Field>
  359. <Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
  360. <AssignedBits>
  361. <Bit>
  362. <Name>BOOT_ADD0</Name>
  363. <Description>Define the boot address when BOOT0=0</Description>
  364. <BitOffset>0x0</BitOffset>
  365. <BitWidth>0x10</BitWidth>
  366. <Access>RW</Access>
  367. <Equation multiplier="0x4000" offset="0x0"/>
  368. </Bit>
  369. <Bit>
  370. <Name>BOOT_ADD1</Name>
  371. <Description>Define the boot address when BOOT0=1</Description>
  372. <BitOffset>0x10</BitOffset>
  373. <BitWidth>0x10</BitWidth>
  374. <Access>RW</Access>
  375. <Equation multiplier="0x4000" offset="0x0"/>
  376. </Bit>
  377. </AssignedBits>
  378. </Field>
  379. </Category>
  380. <Category>
  381. <Name>Write Protection</Name>
  382. <Field>
  383. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  384. <AssignedBits>
  385. <Bit config="0">
  386. <Name>nWRP0</Name>
  387. <Description/>
  388. <BitOffset>0x10</BitOffset>
  389. <BitWidth>0xC</BitWidth>
  390. <Access>RW</Access>
  391. <Values ByBit="true">
  392. <Val value="0x0">Write protection active on this sector</Val>
  393. <Val value="0x1">Write protection not active on this sector</Val>
  394. </Values>
  395. </Bit>
  396. <Bit config="1">
  397. <Name>nWRP0</Name>
  398. <Description/>
  399. <BitOffset>0x10</BitOffset>
  400. <BitWidth>0x6</BitWidth>
  401. <Access>RW</Access>
  402. <Values ByBit="true">
  403. <Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
  404. <Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
  405. </Values>
  406. </Bit>
  407. <Bit config="1">
  408. <Name>nWRP6</Name>
  409. <Description/>
  410. <BitOffset>0x16</BitOffset>
  411. <BitWidth>0x6</BitWidth>
  412. <Access>RW</Access>
  413. <Values ByBit="true">
  414. <Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
  415. <Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
  416. </Values>
  417. </Bit>
  418. </AssignedBits>
  419. </Field>
  420. </Category>
  421. </Bank>
  422. <Bank interface="Bootloader">
  423. <Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
  424. <Category>
  425. <Name>Read Out Protection</Name>
  426. <Field>
  427. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  428. <AssignedBits>
  429. <Bit>
  430. <Name>RDP</Name>
  431. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  432. <BitOffset>0x8</BitOffset>
  433. <BitWidth>0x8</BitWidth>
  434. <Access>RW</Access>
  435. <Values>
  436. <Val value="0xAA">Level 0, no protection</Val>
  437. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  438. <Val value="0xCC">Level 2, chip protection</Val>
  439. </Values>
  440. </Bit>
  441. </AssignedBits>
  442. </Field>
  443. </Category>
  444. <Category>
  445. <Name>BOR Level</Name>
  446. <Field>
  447. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  448. <AssignedBits>
  449. <Bit>
  450. <Name>BOR_LEV</Name>
  451. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  452. <BitOffset>0x2</BitOffset>
  453. <BitWidth>0x2</BitWidth>
  454. <Access>RW</Access>
  455. <Values>
  456. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  457. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  458. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  459. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  460. </Values>
  461. </Bit>
  462. </AssignedBits>
  463. </Field>
  464. </Category>
  465. <Category>
  466. <Name>User Configuration</Name>
  467. <Field>
  468. <Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
  469. <AssignedBits>
  470. <Bit>
  471. <Name>IWDG_STOP</Name>
  472. <Description/>
  473. <BitOffset>0xF</BitOffset>
  474. <BitWidth>0x1</BitWidth>
  475. <Access>RW</Access>
  476. <Values>
  477. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  478. <Val value="0x1">IWDG counter active in stop mode</Val>
  479. </Values>
  480. </Bit>
  481. <Bit>
  482. <Name>IWDG_STDBY</Name>
  483. <Description/>
  484. <BitOffset>0xE</BitOffset>
  485. <BitWidth>0x1</BitWidth>
  486. <Access>RW</Access>
  487. <Values>
  488. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  489. <Val value="0x1">IWDG counter active in standby mode</Val>
  490. </Values>
  491. </Bit>
  492. <Bit reference="DualBank">
  493. <Name>nDBANK</Name>
  494. <Description/>
  495. <BitOffset>0xD</BitOffset>
  496. <BitWidth>0x1</BitWidth>
  497. <Access>RW</Access>
  498. <Values>
  499. <Val value="0x0">Flash in dual bank with 128 bits read access</Val>
  500. <Val value="0x1">Flash in single bank with 256 bits read access</Val>
  501. </Values>
  502. </Bit>
  503. <Bit config="1">
  504. <Name>nDBOOT</Name>
  505. <Description/>
  506. <BitOffset>0xC</BitOffset>
  507. <BitWidth>0x1</BitWidth>
  508. <Access>RW</Access>
  509. <Values>
  510. <Val value="0x0">Dual Boot enabled</Val>
  511. <Val value="0x1">Dual Boot disabled</Val>
  512. </Values>
  513. </Bit>
  514. </AssignedBits>
  515. </Field>
  516. <Field>
  517. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  518. <AssignedBits>
  519. <Bit>
  520. <Name>WWDG_SW</Name>
  521. <Description/>
  522. <BitOffset>0x4</BitOffset>
  523. <BitWidth>0x1</BitWidth>
  524. <Access>RW</Access>
  525. <Values>
  526. <Val value="0x0">Hardware window watchdog</Val>
  527. <Val value="0x1">Software window watchdog</Val>
  528. </Values>
  529. </Bit>
  530. <Bit>
  531. <Name>IWDG_SW</Name>
  532. <Description/>
  533. <BitOffset>0x5</BitOffset>
  534. <BitWidth>0x1</BitWidth>
  535. <Access>RW</Access>
  536. <Values>
  537. <Val value="0x0">Hardware independant watchdog</Val>
  538. <Val value="0x1">Software independant watchdog</Val>
  539. </Values>
  540. </Bit>
  541. <Bit>
  542. <Name>nRST_STOP</Name>
  543. <Description/>
  544. <BitOffset>0x6</BitOffset>
  545. <BitWidth>0x1</BitWidth>
  546. <Access>RW</Access>
  547. <Values>
  548. <Val value="0x0">Reset generated when entering Stop mode</Val>
  549. <Val value="0x1">No reset generated</Val>
  550. </Values>
  551. </Bit>
  552. <Bit>
  553. <Name>nRST_STDBY</Name>
  554. <Description/>
  555. <BitOffset>0x7</BitOffset>
  556. <BitWidth>0x1</BitWidth>
  557. <Access>RW</Access>
  558. <Values>
  559. <Val value="0x0">Reset generated when entering Standby mode</Val>
  560. <Val value="0x1">No reset generated</Val>
  561. </Values>
  562. </Bit>
  563. </AssignedBits>
  564. </Field>
  565. </Category>
  566. <Category>
  567. <Name>Boot address Option Bytes</Name>
  568. <Field>
  569. <Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
  570. <AssignedBits>
  571. <Bit>
  572. <Name>BOOT_ADD0</Name>
  573. <Description>Define the boot address when BOOT0=0</Description>
  574. <BitOffset>0x0</BitOffset>
  575. <BitWidth>0x10</BitWidth>
  576. <Access>RW</Access>
  577. <Equation multiplier="0x4000" offset="0x0"/>
  578. </Bit>
  579. </AssignedBits>
  580. </Field>
  581. <Field>
  582. <Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
  583. <AssignedBits>
  584. <Bit>
  585. <Name>BOOT_ADD1</Name>
  586. <Description>Define the boot address when BOOT0=1</Description>
  587. <BitOffset>0x0</BitOffset>
  588. <BitWidth>0x10</BitWidth>
  589. <Access>RW</Access>
  590. <Equation multiplier="0x4000" offset="0x0"/>
  591. </Bit>
  592. </AssignedBits>
  593. </Field>
  594. </Category>
  595. <Category>
  596. <Name>Write Protection</Name>
  597. <Field>
  598. <Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
  599. <AssignedBits>
  600. <Bit config="0">
  601. <Name>nWRP0</Name>
  602. <Description/>
  603. <BitOffset>0x0</BitOffset>
  604. <BitWidth>0xC</BitWidth>
  605. <Access>RW</Access>
  606. <Values ByBit="true">
  607. <Val value="0x0">Write protection active on this sector</Val>
  608. <Val value="0x1">Write protection not active on this sector</Val>
  609. </Values>
  610. </Bit>
  611. <Bit config="1">
  612. <Name>nWRP0</Name>
  613. <Description/>
  614. <BitOffset>0x0</BitOffset>
  615. <BitWidth>0x6</BitWidth>
  616. <Access>RW</Access>
  617. <Values ByBit="true">
  618. <Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
  619. <Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
  620. </Values>
  621. </Bit>
  622. <Bit config="1">
  623. <Name>nWRP6</Name>
  624. <Description/>
  625. <BitOffset>0x6</BitOffset>
  626. <BitWidth>0x6</BitWidth>
  627. <Access>RW</Access>
  628. <Values ByBit="true">
  629. <Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
  630. <Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
  631. </Values>
  632. </Bit>
  633. </AssignedBits>
  634. </Field>
  635. </Category>
  636. </Bank>
  637. </Peripheral>
  638. </Peripherals>
  639. </Device>
  640. </Root>