STM32_Prog_DB_0x482.xml 108 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x482</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32U5xx</Name>
  9. <Series>STM32U5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Single Bank non secure -->
  15. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  16. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  17. </Configuration>
  18. <Configuration number="0x1"> <!-- Dual Bank non secure -->
  19. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  20. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  21. </Configuration>
  22. <Configuration number="0x2"> <!-- Single Bank secure + RDP=0xAA -->
  23. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  25. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  26. </Configuration>
  27. <Configuration number="0x3"> <!-- Dual Bank secure + RDP=0xAA -->
  28. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  29. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  30. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  31. </Configuration>
  32. <Configuration number="0x4"> <!-- Single Bank secure -->
  33. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  34. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  35. </Configuration>
  36. <Configuration number="0x5"> <!-- Dual Bank secure -->
  37. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  38. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  39. </Configuration>
  40. </Interface>
  41. <!-- Bootloader Interface -->
  42. <Interface name="Bootloader">
  43. <Configuration number="0x6"> <!-- Single Bank Secure-->
  44. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  45. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  46. </Configuration>
  47. <Configuration number="0x7"> <!-- Dual Bank Secure-->
  48. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  49. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  50. </Configuration>
  51. <Configuration number="0x8"> <!-- Single Bank non Secure-->
  52. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  53. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  54. </Configuration>
  55. <Configuration number="0x9"> <!-- Dual Bank non Secure-->
  56. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  57. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  58. </Configuration>
  59. </Interface>
  60. </Configurations>
  61. <!-- Peripherals -->
  62. <Peripherals>
  63. <!-- Embedded SRAM -->
  64. <Peripheral>
  65. <Name>Embedded SRAM</Name>
  66. <Type>Storage</Type>
  67. <Description/>
  68. <ErasedValue>0xFF</ErasedValue>
  69. <Access>RWE</Access>
  70. <!-- 96 KB -->
  71. <Configuration config="0,1,6,7,8,9">
  72. <Parameters address="0x20000000" name="SRAM" size="0x8000"/>
  73. <Description/>
  74. <Organization>Single</Organization>
  75. <Bank name="Bank 1">
  76. <Field>
  77. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
  78. </Field>
  79. </Bank>
  80. </Configuration>
  81. <Configuration config="2,3,4,5">
  82. <Parameters address="0x30000000" name="SRAM" size="0x8000"/>
  83. <Description/>
  84. <Organization>Single</Organization>
  85. <Bank name="Bank 1">
  86. <Field>
  87. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x8000"/>
  88. </Field>
  89. </Bank>
  90. </Configuration>
  91. </Peripheral>
  92. <!-- Embedded Flash -->
  93. <Peripheral>
  94. <Name>Embedded Flash</Name>
  95. <Type>Storage</Type>
  96. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  97. <ErasedValue>0xFF</ErasedValue>
  98. <Access>RWE</Access>
  99. <FlashSize address="0x0BFA0764" default="0x200000"/>
  100. <Configuration config="0"> <!-- Single Bank -->
  101. <Parameters address="0x08000000" name=" 2048 Kbyte Embedded Flash" size="0x200000"/>
  102. <Description/>
  103. <Organization>Single</Organization>
  104. <Allignement>0x10</Allignement>
  105. <Bank name="Bank 1">
  106. <Field>
  107. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  108. </Field>
  109. </Bank>
  110. </Configuration>
  111. <Configuration config="1"> <!-- dual Bank -->
  112. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  113. <Description/>
  114. <Organization>Dual</Organization>
  115. <Allignement>0x10</Allignement>
  116. <Bank name="Bank 1">
  117. <Field>
  118. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  119. </Field>
  120. </Bank>
  121. <Bank name="Bank 2">
  122. <Field>
  123. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  124. </Field>
  125. </Bank>
  126. </Configuration>
  127. <Configuration config="2,4"> <!-- Single Bank secure -->
  128. <Parameters address="0x0C000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  129. <Description/>
  130. <Organization>Single</Organization>
  131. <Allignement>0x10</Allignement>
  132. <Bank name="Bank 1">
  133. <Field>
  134. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x4000"/>
  135. </Field>
  136. </Bank>
  137. </Configuration>
  138. <Configuration config="3,5"> <!-- dual Bank secure -->
  139. <Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  140. <Description/>
  141. <Organization>Dual</Organization>
  142. <Allignement>0x10</Allignement>
  143. <Bank name="Bank 1">
  144. <Field>
  145. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  146. </Field>
  147. </Bank>
  148. <Bank name="Bank 2">
  149. <Field>
  150. <Parameters address="0x0c100000" name="sector128" occurence="0x80" size="0x2000"/>
  151. </Field>
  152. </Bank>
  153. </Configuration>
  154. </Peripheral>
  155. <!-- Data EEPROM -->
  156. <Peripheral>
  157. <Name>Data EEPROM</Name>
  158. <Type>Storage</Type>
  159. <Description>The Data EEPROM memory block. It contains user data.</Description>
  160. <ErasedValue>0xFF</ErasedValue>
  161. <Access>RWE</Access>
  162. <Configuration config="2,4">
  163. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  164. <Description/>
  165. <Organization>Single</Organization>
  166. <Allignement>0x4</Allignement>
  167. <Bank name="Bank 1">
  168. <Field>
  169. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  170. </Field>
  171. </Bank>
  172. </Configuration>
  173. <Configuration config="3,5">
  174. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  175. <Description/>
  176. <Organization>Single</Organization>
  177. <Allignement>0x4</Allignement>
  178. <Bank name="Bank 1">
  179. <Field>
  180. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  181. </Field>
  182. </Bank>
  183. <Bank name="Bank 2">
  184. <Field>
  185. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  186. </Field>
  187. </Bank>
  188. </Configuration>
  189. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  190. <Configuration config="1">
  191. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  192. <Description/>
  193. <Organization>Single</Organization>
  194. <Allignement>0x4</Allignement>
  195. <Bank name="Bank 1">
  196. <Field>
  197. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  198. </Field>
  199. </Bank>
  200. <Bank name="Bank 2">
  201. <Field>
  202. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  203. </Field>
  204. </Bank>
  205. </Configuration>
  206. </Peripheral>
  207. <!-- OTP -->
  208. <Peripheral>
  209. <Name>OTP</Name>
  210. <Type>Storage</Type>
  211. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  212. <ErasedValue>0xFF</ErasedValue>
  213. <Access>RW</Access>
  214. <!-- 512 Bytes single bank -->
  215. <Configuration>
  216. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  217. <Description/>
  218. <Organization>Single</Organization>
  219. <Allignement>0x4</Allignement>
  220. <Bank name="OTP">
  221. <Field>
  222. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  223. </Field>
  224. </Bank>
  225. </Configuration>
  226. </Peripheral>
  227. <!-- Option Bytes -->
  228. <Peripheral>
  229. <Name>Option Bytes</Name>
  230. <Type>Configuration</Type>
  231. <Description/>
  232. <Access>RW</Access>
  233. <Configuration config="0,1">
  234. <Bank interface="JTAG_SWD">
  235. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  236. <Category>
  237. <Name>Read Out Protection</Name>
  238. <Field>
  239. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  240. <AssignedBits>
  241. <Bit>
  242. <Name>RDP</Name>
  243. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  244. <BitOffset>0x0</BitOffset>
  245. <BitWidth>0x8</BitWidth>
  246. <Access>RW</Access>
  247. <Values>
  248. <Val value="0xAA">Level 0, no protection</Val>
  249. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  250. <Val value="0xDC">Level 1, read protection of memories</Val>
  251. <Val value="0xCC">Level 2, chip protection</Val>
  252. </Values>
  253. </Bit>
  254. </AssignedBits>
  255. </Field>
  256. </Category>
  257. <Category>
  258. <Name>BOR Level</Name>
  259. <Field>
  260. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  261. <AssignedBits>
  262. <Bit>
  263. <Name>BOR_LEV</Name>
  264. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  265. <BitOffset>0x8</BitOffset>
  266. <BitWidth>0x3</BitWidth>
  267. <Access>RW</Access>
  268. <Values>
  269. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  270. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  271. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  272. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  273. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  274. </Values>
  275. </Bit>
  276. </AssignedBits>
  277. </Field>
  278. </Category>
  279. <Category>
  280. <Name>User Configuration</Name>
  281. <Field>
  282. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  283. <AssignedBits>
  284. <Bit>
  285. <Name>nRST_STOP</Name>
  286. <Description/>
  287. <BitOffset>0xC</BitOffset>
  288. <BitWidth>0x1</BitWidth>
  289. <Access>RW</Access>
  290. <Values>
  291. <Val value="0x0">Reset generated when entering Stop mode</Val>
  292. <Val value="0x1">No reset generated when entering Stop mode</Val>
  293. </Values>
  294. </Bit>
  295. <Bit>
  296. <Name>nRST_STDBY</Name>
  297. <Description/>
  298. <BitOffset>0xD</BitOffset>
  299. <BitWidth>0x1</BitWidth>
  300. <Access>RW</Access>
  301. <Values>
  302. <Val value="0x0">Reset generated when entering Standby mode</Val>
  303. <Val value="0x1">No reset generated when entering Standby mode</Val>
  304. </Values>
  305. </Bit>
  306. <Bit>
  307. <Name>nRST_SHDW</Name>
  308. <Description/>
  309. <BitOffset>0xE</BitOffset>
  310. <BitWidth>0x1</BitWidth>
  311. <Access>RW</Access>
  312. <Values>
  313. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  314. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  315. </Values>
  316. </Bit>
  317. <Bit>
  318. <Name>SRAM134_RST</Name>
  319. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  320. <BitOffset>0xF</BitOffset>
  321. <BitWidth>0x1</BitWidth>
  322. <Access>RW</Access>
  323. <Values>
  324. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  325. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  326. </Values>
  327. </Bit>
  328. <Bit>
  329. <Name>IWDG_SW</Name>
  330. <Description/>
  331. <BitOffset>0x10</BitOffset>
  332. <BitWidth>0x1</BitWidth>
  333. <Access>RW</Access>
  334. <Values>
  335. <Val value="0x0">Hardware independant watchdog</Val>
  336. <Val value="0x1">Software independant watchdog</Val>
  337. </Values>
  338. </Bit>
  339. <Bit>
  340. <Name>IWDG_STOP</Name>
  341. <Description/>
  342. <BitOffset>0x11</BitOffset>
  343. <BitWidth>0x1</BitWidth>
  344. <Access>RW</Access>
  345. <Values>
  346. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  347. <Val value="0x1">IWDG counter active in stop mode</Val>
  348. </Values>
  349. </Bit>
  350. <Bit>
  351. <Name>IWDG_STDBY</Name>
  352. <Description/>
  353. <BitOffset>0x12</BitOffset>
  354. <BitWidth>0x1</BitWidth>
  355. <Access>RW</Access>
  356. <Values>
  357. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  358. <Val value="0x1">IWDG counter active in standby mode</Val>
  359. </Values>
  360. </Bit>
  361. <Bit>
  362. <Name>WWDG_SW</Name>
  363. <Description/>
  364. <BitOffset>0x13</BitOffset>
  365. <BitWidth>0x1</BitWidth>
  366. <Access>RW</Access>
  367. <Values>
  368. <Val value="0x0">Hardware window watchdog</Val>
  369. <Val value="0x1">Software window watchdog</Val>
  370. </Values>
  371. </Bit>
  372. <Bit>
  373. <Name>SWAP_BANK</Name>
  374. <Description/>
  375. <BitOffset>0x14</BitOffset>
  376. <BitWidth>0x1</BitWidth>
  377. <Access>RW</Access>
  378. <Values>
  379. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  380. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  381. </Values>
  382. </Bit>
  383. <Bit>
  384. <Name>DBANK</Name>
  385. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  386. <BitOffset>0x15</BitOffset>
  387. <BitWidth>0x1</BitWidth>
  388. <Access>RW</Access>
  389. <Values>
  390. <Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
  391. <Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
  392. </Values>
  393. </Bit>
  394. <Bit>
  395. <Name>BKPRAM_ECC</Name>
  396. <Description>SRAM2 parity check enable</Description>
  397. <BitOffset>0x16</BitOffset>
  398. <BitWidth>0x1</BitWidth>
  399. <Access>RW</Access>
  400. <Values>
  401. <Val value="0x0">Backup RAM ECC check enabled</Val>
  402. <Val value="0x1">Backup RAM ECC check disabled</Val>
  403. </Values>
  404. </Bit>
  405. <Bit>
  406. <Name>SRAM3_ECC</Name>
  407. <Description>SRAM3 ECC detection and correction enable</Description>
  408. <BitOffset>0x17</BitOffset>
  409. <BitWidth>0x1</BitWidth>
  410. <Access>RW</Access>
  411. <Values>
  412. <Val value="0x0">SRAM3 ECC check enabled</Val>
  413. <Val value="0x1">SRAM3 ECC check disabled</Val>
  414. </Values>
  415. </Bit>
  416. <Bit>
  417. <Name>SRAM2_ECC</Name>
  418. <Description>SRAM2 ECC detection and correction enable</Description>
  419. <BitOffset>0x18</BitOffset>
  420. <BitWidth>0x1</BitWidth>
  421. <Access>RW</Access>
  422. <Values>
  423. <Val value="0x0">SRAM2 ECC check enabled</Val>
  424. <Val value="0x1">SRAM2 ECC check disabled</Val>
  425. </Values>
  426. </Bit>
  427. <Bit>
  428. <Name>SRAM2_RST</Name>
  429. <Description>SRAM2 Erase when system reset</Description>
  430. <BitOffset>0x19</BitOffset>
  431. <BitWidth>0x1</BitWidth>
  432. <Access>RW</Access>
  433. <Values>
  434. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  435. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  436. </Values>
  437. </Bit>
  438. <Bit>
  439. <Name>nSWBOOT0</Name>
  440. <Description>Software BOOT0</Description>
  441. <BitOffset>0x1A</BitOffset>
  442. <BitWidth>0x1</BitWidth>
  443. <Access>RW</Access>
  444. <Values>
  445. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  446. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  447. </Values>
  448. </Bit>
  449. <Bit>
  450. <Name>nBOOT0</Name>
  451. <Description>nBOOT0 option bit</Description>
  452. <BitOffset>0x1B</BitOffset>
  453. <BitWidth>0x1</BitWidth>
  454. <Access>RW</Access>
  455. <Values>
  456. <Val value="0x0">nBOOT0 = 0</Val>
  457. <Val value="0x1">nBOOT0 = 1</Val>
  458. </Values>
  459. </Bit>
  460. <Bit>
  461. <Name>PA15_PUPEN</Name>
  462. <Description>PA15 pull-up enable</Description>
  463. <BitOffset>0x1C</BitOffset>
  464. <BitWidth>0x1</BitWidth>
  465. <Access>RW</Access>
  466. <Values>
  467. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  468. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  469. </Values>
  470. </Bit>
  471. <Bit>
  472. <Name>IO_VDD_HSLV</Name>
  473. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  474. <BitOffset>0x1D</BitOffset>
  475. <BitWidth>0x1</BitWidth>
  476. <Access>RW</Access>
  477. <Values>
  478. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  479. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  480. </Values>
  481. </Bit>
  482. <Bit>
  483. <Name>IO_VDDIO2_HSLV</Name>
  484. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  485. <BitOffset>0x1E</BitOffset>
  486. <BitWidth>0x1</BitWidth>
  487. <Access>RW</Access>
  488. <Values>
  489. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  490. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  491. </Values>
  492. </Bit>
  493. <Bit>
  494. <Name>TZEN</Name>
  495. <Description>Global TrustZone security enable</Description>
  496. <BitOffset>0x1F</BitOffset>
  497. <BitWidth>0x1</BitWidth>
  498. <Access>RW</Access>
  499. <Values>
  500. <Val value="0x0">Global TrustZone security disabled</Val>
  501. <Val value="0x1">Global TrustZone security enabled</Val>
  502. </Values>
  503. </Bit>
  504. </AssignedBits>
  505. </Field>
  506. </Category>
  507. <Category>
  508. <Name>Write Protection 1</Name>
  509. <Field>
  510. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  511. <AssignedBits>
  512. <Bit config="0">
  513. <Name>WRP1A_PSTRT</Name>
  514. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  515. <BitOffset>0x0</BitOffset>
  516. <BitWidth>0x7</BitWidth>
  517. <Access>RW</Access>
  518. <Equation multiplier="0x4000" offset="0x08000000"/>
  519. </Bit>
  520. <Bit config="1">
  521. <Name>WRP1A_PSTRT</Name>
  522. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  523. <BitOffset>0x0</BitOffset>
  524. <BitWidth>0x7</BitWidth>
  525. <Access>RW</Access>
  526. <Equation multiplier="0x2000" offset="0x08000000"/>
  527. </Bit>
  528. <Bit config="0">
  529. <Name>WRP1A_PEND</Name>
  530. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  531. <BitOffset>0x10</BitOffset>
  532. <BitWidth>0x7</BitWidth>
  533. <Access>RW</Access>
  534. <Equation multiplier="0x4000" offset="0x08000000"/>
  535. </Bit>
  536. <Bit config="1">
  537. <Name>WRP1A_PEND</Name>
  538. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  539. <BitOffset>0x10</BitOffset>
  540. <BitWidth>0x7</BitWidth>
  541. <Access>RW</Access>
  542. <Equation multiplier="0x2000" offset="0x08000000"/>
  543. </Bit>
  544. <Bit>
  545. <Name>UNLOCK_1A</Name>
  546. <Description>Bank 1 WPR first area A unlock</Description>
  547. <BitOffset>0x1F</BitOffset>
  548. <BitWidth>0x1</BitWidth>
  549. <Access>RW</Access>
  550. <Values>
  551. <Val value="0x0">WRP1A start and end pages locked</Val>
  552. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  553. </Values>
  554. </Bit>
  555. </AssignedBits>
  556. </Field>
  557. <Field>
  558. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  559. <AssignedBits>
  560. <Bit config="0">
  561. <Name>WRP1B_PSTRT</Name>
  562. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  563. <BitOffset>0x0</BitOffset>
  564. <BitWidth>0x7</BitWidth>
  565. <Access>RW</Access>
  566. <Equation multiplier="0x4000" offset="0x08000000"/>
  567. </Bit>
  568. <Bit config="1">
  569. <Name>WRP1B_PSTRT</Name>
  570. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  571. <BitOffset>0x0</BitOffset>
  572. <BitWidth>0x7</BitWidth>
  573. <Access>RW</Access>
  574. <Equation multiplier="0x2000" offset="0x08000000"/>
  575. </Bit>
  576. <Bit config="0">
  577. <Name>WRP1B_PEND</Name>
  578. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  579. <BitOffset>0x10</BitOffset>
  580. <BitWidth>0x7</BitWidth>
  581. <Access>RW</Access>
  582. <Equation multiplier="0x4000" offset="0x08000000"/>
  583. </Bit>
  584. <Bit config="1">
  585. <Name>WRP1B_PEND</Name>
  586. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  587. <BitOffset>0x10</BitOffset>
  588. <BitWidth>0x7</BitWidth>
  589. <Access>RW</Access>
  590. <Equation multiplier="0x2000" offset="0x08000000"/>
  591. </Bit>
  592. <Bit>
  593. <Name>UNLOCK_1B</Name>
  594. <Description>Bank 1 WPR first area B unlock</Description>
  595. <BitOffset>0x1F</BitOffset>
  596. <BitWidth>0x1</BitWidth>
  597. <Access>RW</Access>
  598. <Values>
  599. <Val value="0x0">WRP1B start and end pages locked</Val>
  600. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  601. </Values>
  602. </Bit>
  603. </AssignedBits>
  604. </Field>
  605. </Category>
  606. </Bank>
  607. <Bank interface="JTAG_SWD">
  608. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  609. <Category>
  610. <Name>Write Protection 2</Name>
  611. <Field>
  612. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  613. <AssignedBits>
  614. <Bit config="0">
  615. <Name>WRP2A_PSTRT</Name>
  616. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  617. <BitOffset>0x0</BitOffset>
  618. <BitWidth>0x7</BitWidth>
  619. <Access>RW</Access>
  620. <Equation multiplier="0x4000" offset="0x08000000"/>
  621. </Bit>
  622. <Bit config="1">
  623. <Name>WRP2A_PSTRT</Name>
  624. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  625. <BitOffset>0x0</BitOffset>
  626. <BitWidth>0x7</BitWidth>
  627. <Access>RW</Access>
  628. <Equation multiplier="0x2000" offset="0x08100000"/>
  629. </Bit>
  630. <Bit config="0">
  631. <Name>WRP2A_PEND</Name>
  632. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  633. <BitOffset>0x10</BitOffset>
  634. <BitWidth>0x7</BitWidth>
  635. <Access>RW</Access>
  636. <Equation multiplier="0x4000" offset="0x08000000"/>
  637. </Bit>
  638. <Bit config="1">
  639. <Name>WRP2A_PEND</Name>
  640. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  641. <BitOffset>0x10</BitOffset>
  642. <BitWidth>0x7</BitWidth>
  643. <Access>RW</Access>
  644. <Equation multiplier="0x2000" offset="0x08100000"/>
  645. </Bit>
  646. <Bit>
  647. <Name>UNLOCK_2A</Name>
  648. <Description>Bank 2 WPR first area A unlock</Description>
  649. <BitOffset>0x1F</BitOffset>
  650. <BitWidth>0x1</BitWidth>
  651. <Access>RW</Access>
  652. <Values>
  653. <Val value="0x0">WRP2A start and end pages locked</Val>
  654. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  655. </Values>
  656. </Bit>
  657. </AssignedBits>
  658. </Field>
  659. <Field>
  660. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  661. <AssignedBits>
  662. <Bit config="0">
  663. <Name>WRP2B_PSTRT</Name>
  664. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  665. <BitOffset>0x0</BitOffset>
  666. <BitWidth>0x7</BitWidth>
  667. <Access>RW</Access>
  668. <Equation multiplier="0x4000" offset="0x08000000"/>
  669. </Bit>
  670. <Bit config="1">
  671. <Name>WRP2B_PSTRT</Name>
  672. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  673. <BitOffset>0x0</BitOffset>
  674. <BitWidth>0x7</BitWidth>
  675. <Access>RW</Access>
  676. <Equation multiplier="0x2000" offset="0x08100000"/>
  677. </Bit>
  678. <Bit config="0">
  679. <Name>WRP2B_PEND</Name>
  680. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  681. <BitOffset>0x10</BitOffset>
  682. <BitWidth>0x7</BitWidth>
  683. <Access>RW</Access>
  684. <Equation multiplier="0x4000" offset="0x08000000"/>
  685. </Bit>
  686. <Bit config="1">
  687. <Name>WRP2B_PEND</Name>
  688. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  689. <BitOffset>0x10</BitOffset>
  690. <BitWidth>0x7</BitWidth>
  691. <Access>RW</Access>
  692. <Equation multiplier="0x2000" offset="0x08100000"/>
  693. </Bit>
  694. <Bit>
  695. <Name>UNLOCK_2B</Name>
  696. <Description>Bank 2 WPR first area B unlock</Description>
  697. <BitOffset>0x1F</BitOffset>
  698. <BitWidth>0x1</BitWidth>
  699. <Access>RW</Access>
  700. <Values>
  701. <Val value="0x0">WRP2B start and end pages locked</Val>
  702. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  703. </Values>
  704. </Bit>
  705. </AssignedBits>
  706. </Field>
  707. </Category>
  708. </Bank>
  709. <!--Bank interface="JTAG_SWD">
  710. <Parameters name="Bank 3" size="0x10" address="0x40022070"/>
  711. <Category>
  712. <Name>OEMxKEY</Name>
  713. <Field>
  714. <Parameters name="FLASH_OEM1KEYR1" size="0x4" address="0x40022070"/>
  715. <AssignedBits>
  716. <Bit>
  717. <Name>OEM1KEY_31_0</Name>
  718. <Description>OEM1 least significant bytes key</Description>
  719. <BitOffset>0x0</BitOffset>
  720. <BitWidth>0x20</BitWidth>
  721. <Access>RW</Access>
  722. <Equation multiplier="0x1" offset="0x0"/>
  723. </Bit>
  724. </AssignedBits>
  725. </Field>
  726. <Field>
  727. <Parameters name="FLASH_OEM1KEYR2" size="0x4" address="0x40022074"/>
  728. <AssignedBits>
  729. <Bit>
  730. <Name>OEM1KEY_63_32</Name>
  731. <Description>OEM1 most significant bytes key</Description>
  732. <BitOffset>0x0</BitOffset>
  733. <BitWidth>0x20</BitWidth>
  734. <Access>RW</Access>
  735. <Equation multiplier="0x1" offset="0x0"/>
  736. </Bit>
  737. </AssignedBits>
  738. </Field>
  739. <Field>
  740. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x40022078"/>
  741. <AssignedBits>
  742. <Bit>
  743. <Name>OEM2KEY_31_0</Name>
  744. <Description>OEM2 least significant bytes key</Description>
  745. <BitOffset>0x0</BitOffset>
  746. <BitWidth>0x20</BitWidth>
  747. <Access>RW</Access>
  748. <Equation multiplier="0x1" offset="0x0"/>
  749. </Bit>
  750. </AssignedBits>
  751. </Field>
  752. <Field>
  753. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x4002207C"/>
  754. <AssignedBits>
  755. <Bit>
  756. <Name>OEM2KEY_63_32</Name>
  757. <Description>OEM2 most significant bytes key</Description>
  758. <BitOffset>0x0</BitOffset>
  759. <BitWidth>0x20</BitWidth>
  760. <Access>RW</Access>
  761. <Equation multiplier="0x1" offset="0x0"/>
  762. </Bit>
  763. </AssignedBits>
  764. </Field>
  765. </Category>
  766. </Bank-->
  767. </Configuration>
  768. <Configuration config="2,3">
  769. <Bank interface="JTAG_SWD">
  770. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  771. <Category>
  772. <Name>Read Out Protection</Name>
  773. <Field>
  774. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  775. <AssignedBits>
  776. <Bit>
  777. <Name>RDP</Name>
  778. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  779. <BitOffset>0x0</BitOffset>
  780. <BitWidth>0x8</BitWidth>
  781. <Access>RW</Access>
  782. <Values>
  783. <Val value="0xAA">Level 0, no protection</Val>
  784. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  785. <Val value="0xDC">Level 1, read protection of memories</Val>
  786. <Val value="0xCC">Level 2, chip protection</Val>
  787. </Values>
  788. </Bit>
  789. </AssignedBits>
  790. </Field>
  791. </Category>
  792. <Category>
  793. <Name>BOR Level</Name>
  794. <Field>
  795. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  796. <AssignedBits>
  797. <Bit>
  798. <Name>BOR_LEV</Name>
  799. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  800. <BitOffset>0x8</BitOffset>
  801. <BitWidth>0x3</BitWidth>
  802. <Access>RW</Access>
  803. <Values>
  804. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  805. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  806. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  807. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  808. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  809. </Values>
  810. </Bit>
  811. </AssignedBits>
  812. </Field>
  813. </Category>
  814. <Category>
  815. <Name>User Configuration</Name>
  816. <Field>
  817. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  818. <AssignedBits>
  819. <Bit>
  820. <Name>nRST_STOP</Name>
  821. <Description/>
  822. <BitOffset>0xC</BitOffset>
  823. <BitWidth>0x1</BitWidth>
  824. <Access>RW</Access>
  825. <Values>
  826. <Val value="0x0">Reset generated when entering Stop mode</Val>
  827. <Val value="0x1">No reset generated when entering Stop mode</Val>
  828. </Values>
  829. </Bit>
  830. <Bit>
  831. <Name>nRST_STDBY</Name>
  832. <Description/>
  833. <BitOffset>0xD</BitOffset>
  834. <BitWidth>0x1</BitWidth>
  835. <Access>RW</Access>
  836. <Values>
  837. <Val value="0x0">Reset generated when entering Standby mode</Val>
  838. <Val value="0x1">No reset generated when entering Standby mode</Val>
  839. </Values>
  840. </Bit>
  841. <Bit>
  842. <Name>nRST_SHDW</Name>
  843. <Description/>
  844. <BitOffset>0xE</BitOffset>
  845. <BitWidth>0x1</BitWidth>
  846. <Access>RW</Access>
  847. <Values>
  848. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  849. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  850. </Values>
  851. </Bit>
  852. <Bit>
  853. <Name>SRAM134_RST</Name>
  854. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  855. <BitOffset>0xF</BitOffset>
  856. <BitWidth>0x1</BitWidth>
  857. <Access>RW</Access>
  858. <Values>
  859. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  860. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  861. </Values>
  862. </Bit>
  863. <Bit>
  864. <Name>IWDG_SW</Name>
  865. <Description/>
  866. <BitOffset>0x10</BitOffset>
  867. <BitWidth>0x1</BitWidth>
  868. <Access>RW</Access>
  869. <Values>
  870. <Val value="0x0">Hardware independant watchdog</Val>
  871. <Val value="0x1">Software independant watchdog</Val>
  872. </Values>
  873. </Bit>
  874. <Bit>
  875. <Name>IWDG_STOP</Name>
  876. <Description/>
  877. <BitOffset>0x11</BitOffset>
  878. <BitWidth>0x1</BitWidth>
  879. <Access>RW</Access>
  880. <Values>
  881. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  882. <Val value="0x1">IWDG counter active in stop mode</Val>
  883. </Values>
  884. </Bit>
  885. <Bit>
  886. <Name>IWDG_STDBY</Name>
  887. <Description/>
  888. <BitOffset>0x12</BitOffset>
  889. <BitWidth>0x1</BitWidth>
  890. <Access>RW</Access>
  891. <Values>
  892. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  893. <Val value="0x1">IWDG counter active in standby mode</Val>
  894. </Values>
  895. </Bit>
  896. <Bit>
  897. <Name>WWDG_SW</Name>
  898. <Description/>
  899. <BitOffset>0x13</BitOffset>
  900. <BitWidth>0x1</BitWidth>
  901. <Access>RW</Access>
  902. <Values>
  903. <Val value="0x0">Hardware window watchdog</Val>
  904. <Val value="0x1">Software window watchdog</Val>
  905. </Values>
  906. </Bit>
  907. <Bit>
  908. <Name>SWAP_BANK</Name>
  909. <Description/>
  910. <BitOffset>0x14</BitOffset>
  911. <BitWidth>0x1</BitWidth>
  912. <Access>RW</Access>
  913. <Values>
  914. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  915. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  916. </Values>
  917. </Bit>
  918. <Bit>
  919. <Name>DBANK</Name>
  920. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  921. <BitOffset>0x15</BitOffset>
  922. <BitWidth>0x1</BitWidth>
  923. <Access>RW</Access>
  924. <Values>
  925. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  926. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  927. </Values>
  928. </Bit>
  929. <Bit>
  930. <Name>SRAM2_PE</Name>
  931. <Description>SRAM2 parity check enable</Description>
  932. <BitOffset>0x18</BitOffset>
  933. <BitWidth>0x1</BitWidth>
  934. <Access>RW</Access>
  935. <Values>
  936. <Val value="0x0">SRAM2 parity check enable</Val>
  937. <Val value="0x1">SRAM2 parity check disable</Val>
  938. </Values>
  939. </Bit>
  940. <Bit>
  941. <Name>SRAM2_RST</Name>
  942. <Description>SRAM2 Erase when system reset</Description>
  943. <BitOffset>0x19</BitOffset>
  944. <BitWidth>0x1</BitWidth>
  945. <Access>RW</Access>
  946. <Values>
  947. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  948. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  949. </Values>
  950. </Bit>
  951. <Bit>
  952. <Name>nSWBOOT0</Name>
  953. <Description>Software BOOT0</Description>
  954. <BitOffset>0x1A</BitOffset>
  955. <BitWidth>0x1</BitWidth>
  956. <Access>RW</Access>
  957. <Values>
  958. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  959. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  960. </Values>
  961. </Bit>
  962. <Bit>
  963. <Name>nBOOT0</Name>
  964. <Description>nBOOT0 option bit</Description>
  965. <BitOffset>0x1B</BitOffset>
  966. <BitWidth>0x1</BitWidth>
  967. <Access>RW</Access>
  968. <Values>
  969. <Val value="0x0">nBOOT0 = 0</Val>
  970. <Val value="0x1">nBOOT0 = 1</Val>
  971. </Values>
  972. </Bit>
  973. <Bit>
  974. <Name>PA15_PUPEN</Name>
  975. <Description>PA15 pull-up enable</Description>
  976. <BitOffset>0x1C</BitOffset>
  977. <BitWidth>0x1</BitWidth>
  978. <Access>RW</Access>
  979. <Values>
  980. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  981. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  982. </Values>
  983. </Bit>
  984. <Bit>
  985. <Name>BKPRAM_ECC</Name>
  986. <Description>SRAM2 parity check enable</Description>
  987. <BitOffset>0x16</BitOffset>
  988. <BitWidth>0x1</BitWidth>
  989. <Access>RW</Access>
  990. <Values>
  991. <Val value="0x0">Backup RAM ECC check enabled</Val>
  992. <Val value="0x1">Backup RAM ECC check disabled</Val>
  993. </Values>
  994. </Bit>
  995. <Bit>
  996. <Name>SRAM3_ECC</Name>
  997. <Description>SRAM3 ECC detection and correction enable</Description>
  998. <BitOffset>0x17</BitOffset>
  999. <BitWidth>0x1</BitWidth>
  1000. <Access>RW</Access>
  1001. <Values>
  1002. <Val value="0x0">SRAM3 ECC check enabled</Val>
  1003. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1004. </Values>
  1005. </Bit>
  1006. <Bit>
  1007. <Name>SRAM2_ECC</Name>
  1008. <Description>SRAM2 ECC detection and correction enable</Description>
  1009. <BitOffset>0x18</BitOffset>
  1010. <BitWidth>0x1</BitWidth>
  1011. <Access>RW</Access>
  1012. <Values>
  1013. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1014. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1015. </Values>
  1016. </Bit>
  1017. <Bit>
  1018. <Name>IO_VDD_HSLV</Name>
  1019. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1020. <BitOffset>0x1D</BitOffset>
  1021. <BitWidth>0x1</BitWidth>
  1022. <Access>RW</Access>
  1023. <Values>
  1024. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1025. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1026. </Values>
  1027. </Bit>
  1028. <Bit>
  1029. <Name>IO_VDDIO2_HSLV</Name>
  1030. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1031. <BitOffset>0x1E</BitOffset>
  1032. <BitWidth>0x1</BitWidth>
  1033. <Access>RW</Access>
  1034. <Values>
  1035. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1036. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1037. </Values>
  1038. </Bit>
  1039. <Bit>
  1040. <Name>TZEN</Name>
  1041. <Description>Global TrustZone security enable</Description>
  1042. <BitOffset>0x1F</BitOffset>
  1043. <BitWidth>0x1</BitWidth>
  1044. <Access>RW</Access>
  1045. <Values>
  1046. <Val value="0x0">Global TrustZone security disabled</Val>
  1047. <Val value="0x1">Global TrustZone security enabled</Val>
  1048. </Values>
  1049. </Bit>
  1050. </AssignedBits>
  1051. </Field>
  1052. </Category>
  1053. <Category>
  1054. <Name>Boot Configuration</Name>
  1055. <Field>
  1056. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1057. <AssignedBits>
  1058. <Bit>
  1059. <Name>NSBOOTADD0</Name>
  1060. <Description>Non-secure Boot base address 0</Description>
  1061. <BitOffset>0x7</BitOffset>
  1062. <BitWidth>0x19</BitWidth>
  1063. <Access>RW</Access>
  1064. <Equation multiplier="0x80" offset="0x0000000"/>
  1065. </Bit>
  1066. </AssignedBits>
  1067. </Field>
  1068. <Field>
  1069. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1070. <AssignedBits>
  1071. <Bit>
  1072. <Name>NSBOOTADD1</Name>
  1073. <Description>Non-secure Boot base address 1</Description>
  1074. <BitOffset>0x7</BitOffset>
  1075. <BitWidth>0x19</BitWidth>
  1076. <Access>RW</Access>
  1077. <Equation multiplier="0x80" offset="0x0000000"/>
  1078. </Bit>
  1079. </AssignedBits>
  1080. </Field>
  1081. <Field>
  1082. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1083. <AssignedBits>
  1084. <Bit>
  1085. <Name>SECBOOTADD0</Name>
  1086. <Description>Secure boot base address 0</Description>
  1087. <BitOffset>0x7</BitOffset>
  1088. <BitWidth>0x19</BitWidth>
  1089. <Access>RW</Access>
  1090. <Equation multiplier="0x80" offset="0x0000000"/>
  1091. </Bit>
  1092. </AssignedBits>
  1093. </Field>
  1094. <Field>
  1095. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  1096. <AssignedBits>
  1097. <Bit>
  1098. <Name>BOOT_LOCK</Name>
  1099. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1100. <BitOffset>0x0</BitOffset>
  1101. <BitWidth>0x1</BitWidth>
  1102. <Access>RW</Access>
  1103. <Values>
  1104. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1105. <Val value="0x1">Boot forced from base address memory</Val>
  1106. </Values>
  1107. </Bit>
  1108. </AssignedBits>
  1109. </Field>
  1110. </Category>
  1111. <Category>
  1112. <Name>Secure Area 1</Name>
  1113. <Field>
  1114. <Parameters address="0x50022050" name="FLASH_SECWM1R1" size="0x4"/>
  1115. <AssignedBits>
  1116. <Bit config="2">
  1117. <Name>SECWM1_PSTRT</Name>
  1118. <Description>Start page of first secure area</Description>
  1119. <BitOffset>0x0</BitOffset>
  1120. <BitWidth>0x7</BitWidth>
  1121. <Access>RW</Access>
  1122. <Equation multiplier="0x4000" offset="0x08000000"/>
  1123. </Bit>
  1124. <Bit config="3">
  1125. <Name>SECWM1_PSTRT</Name>
  1126. <Description>Start page of first secure area</Description>
  1127. <BitOffset>0x0</BitOffset>
  1128. <BitWidth>0x7</BitWidth>
  1129. <Access>RW</Access>
  1130. <Equation multiplier="0x2000" offset="0x08000000"/>
  1131. </Bit>
  1132. <Bit config="2">
  1133. <Name>SECWM1_PEND</Name>
  1134. <Description>End page of first secure area</Description>
  1135. <BitOffset>0x10</BitOffset>
  1136. <BitWidth>0x7</BitWidth>
  1137. <Access>RW</Access>
  1138. <Equation multiplier="0x4000" offset="0x08000000"/>
  1139. </Bit>
  1140. <Bit config="3">
  1141. <Name>SECWM1_PEND</Name>
  1142. <Description>End page of first secure area</Description>
  1143. <BitOffset>0x10</BitOffset>
  1144. <BitWidth>0x7</BitWidth>
  1145. <Access>RW</Access>
  1146. <Equation multiplier="0x2000" offset="0x08000000"/>
  1147. </Bit>
  1148. </AssignedBits>
  1149. </Field>
  1150. <Field>
  1151. <Parameters address="0x50022054" name="FLASH_PCROP1SR" size="0x4"/>
  1152. <AssignedBits>
  1153. <Bit config="2">
  1154. <Name>PCROP1_PSTRT</Name>
  1155. <Description>This field contains the first page of the PCROP area in bank 1</Description>
  1156. <BitOffset>0x0</BitOffset>
  1157. <BitWidth>0x7</BitWidth>
  1158. <Access>RW</Access>
  1159. <Equation multiplier="0x4000" offset="0xC000000"/>
  1160. </Bit>
  1161. <Bit config="3">
  1162. <Name>PCROP1_PSTRT</Name>
  1163. <Description>This field contains the first page of the PCROP area in bank 1</Description>
  1164. <BitOffset>0x0</BitOffset>
  1165. <BitWidth>0x7</BitWidth>
  1166. <Access>RW</Access>
  1167. <Equation multiplier="0x2000" offset="0xC000000"/>
  1168. </Bit>
  1169. <Bit>
  1170. <Name>PCROP1EN</Name>
  1171. <Description>PCROP1 area enable</Description>
  1172. <BitOffset>0xF</BitOffset>
  1173. <BitWidth>0x1</BitWidth>
  1174. <Access>RW</Access>
  1175. <Values>
  1176. <Val value="0x0">PCROP1 area is disabled</Val>
  1177. <Val value="0x1">PCROP1 area is enabled</Val>
  1178. </Values>
  1179. </Bit>
  1180. </AssignedBits>
  1181. </Field>
  1182. <Field>
  1183. <Parameters address="0x50022054" name="FLASH_SECWM2R1" size="0x4"/>
  1184. <AssignedBits>
  1185. <Bit config="2">
  1186. <Name>HDP1_PEND</Name>
  1187. <Description>End page of first hide protection area</Description>
  1188. <BitOffset>0x10</BitOffset>
  1189. <BitWidth>0x7</BitWidth>
  1190. <Access>RW</Access>
  1191. <Equation multiplier="0x4000" offset="0xC000000"/>
  1192. </Bit>
  1193. <Bit config="3">
  1194. <Name>HDP1_PEND</Name>
  1195. <Description>End page of first hide protection area</Description>
  1196. <BitOffset>0x10</BitOffset>
  1197. <BitWidth>0x7</BitWidth>
  1198. <Access>RW</Access>
  1199. <Equation multiplier="0x2000" offset="0xC000000"/>
  1200. </Bit>
  1201. <Bit>
  1202. <Name>HDP1EN</Name>
  1203. <Description>Hide protection first area enable</Description>
  1204. <BitOffset>0x1F</BitOffset>
  1205. <BitWidth>0x1</BitWidth>
  1206. <Access>RW</Access>
  1207. <Values>
  1208. <Val value="0x0">No HDP area 1</Val>
  1209. <Val value="0x1">HDP first area is enabled</Val>
  1210. </Values>
  1211. </Bit>
  1212. </AssignedBits>
  1213. </Field>
  1214. </Category>
  1215. <Category>
  1216. <Name>Write Protection 1</Name>
  1217. <Field>
  1218. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  1219. <AssignedBits>
  1220. <Bit config="2">
  1221. <Name>WRP1A_PSTRT</Name>
  1222. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1223. <BitOffset>0x0</BitOffset>
  1224. <BitWidth>0x7</BitWidth>
  1225. <Access>RW</Access>
  1226. <Equation multiplier="0x4000" offset="0x08000000"/>
  1227. </Bit>
  1228. <Bit config="3">
  1229. <Name>WRP1A_PSTRT</Name>
  1230. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1231. <BitOffset>0x0</BitOffset>
  1232. <BitWidth>0x7</BitWidth>
  1233. <Access>RW</Access>
  1234. <Equation multiplier="0x2000" offset="0x08000000"/>
  1235. </Bit>
  1236. <Bit config="2">
  1237. <Name>WRP1A_PEND</Name>
  1238. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1239. <BitOffset>0x10</BitOffset>
  1240. <BitWidth>0x7</BitWidth>
  1241. <Access>RW</Access>
  1242. <Equation multiplier="0x4000" offset="0x08000000"/>
  1243. </Bit>
  1244. <Bit config="3">
  1245. <Name>WRP1A_PEND</Name>
  1246. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1247. <BitOffset>0x10</BitOffset>
  1248. <BitWidth>0x7</BitWidth>
  1249. <Access>RW</Access>
  1250. <Equation multiplier="0x2000" offset="0x08000000"/>
  1251. </Bit>
  1252. <Bit>
  1253. <Name>UNLOCK_1A</Name>
  1254. <Description>Bank 1 WPR first area A unlock</Description>
  1255. <BitOffset>0x1F</BitOffset>
  1256. <BitWidth>0x1</BitWidth>
  1257. <Access>RW</Access>
  1258. <Values>
  1259. <Val value="0x0">WRP1A start and end pages locked</Val>
  1260. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1261. </Values>
  1262. </Bit>
  1263. </AssignedBits>
  1264. </Field>
  1265. <Field>
  1266. <Parameters address="0x5002205C" name="FLASH_WRP1BR" size="0x4"/>
  1267. <AssignedBits>
  1268. <Bit config="2">
  1269. <Name>WRP1B_PSTRT</Name>
  1270. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1271. <BitOffset>0x0</BitOffset>
  1272. <BitWidth>0x7</BitWidth>
  1273. <Access>RW</Access>
  1274. <Equation multiplier="0x4000" offset="0x08000000"/>
  1275. </Bit>
  1276. <Bit config="3">
  1277. <Name>WRP1B_PSTRT</Name>
  1278. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1279. <BitOffset>0x0</BitOffset>
  1280. <BitWidth>0x7</BitWidth>
  1281. <Access>RW</Access>
  1282. <Equation multiplier="0x2000" offset="0x08000000"/>
  1283. </Bit>
  1284. <Bit config="2">
  1285. <Name>WRP1B_PEND</Name>
  1286. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1287. <BitOffset>0x10</BitOffset>
  1288. <BitWidth>0x7</BitWidth>
  1289. <Access>RW</Access>
  1290. <Equation multiplier="0x4000" offset="0x08000000"/>
  1291. </Bit>
  1292. <Bit config="3">
  1293. <Name>WRP1B_PEND</Name>
  1294. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1295. <BitOffset>0x10</BitOffset>
  1296. <BitWidth>0x7</BitWidth>
  1297. <Access>RW</Access>
  1298. <Equation multiplier="0x2000" offset="0x08000000"/>
  1299. </Bit>
  1300. <Bit>
  1301. <Name>UNLOCK_1B</Name>
  1302. <Description>Bank 1 WPR first area B unlock</Description>
  1303. <BitOffset>0x1F</BitOffset>
  1304. <BitWidth>0x1</BitWidth>
  1305. <Access>RW</Access>
  1306. <Values>
  1307. <Val value="0x0">WRP1B start and end pages locked</Val>
  1308. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1309. </Values>
  1310. </Bit>
  1311. </AssignedBits>
  1312. </Field>
  1313. </Category>
  1314. </Bank>
  1315. <Bank interface="JTAG_SWD">
  1316. <Parameters address="0x50022060" name="Bank 2" size="0x10"/>
  1317. <Category>
  1318. <Name>Secure Area 2</Name>
  1319. <Field>
  1320. <Parameters address="0x50022060" name="FLASH_SECWM2R1" size="0x4"/>
  1321. <AssignedBits>
  1322. <Bit config="2">
  1323. <Name>SECWM2_PSTRT</Name>
  1324. <Description>Start page of second secure area</Description>
  1325. <BitOffset>0x0</BitOffset>
  1326. <BitWidth>0x7</BitWidth>
  1327. <Access>RW</Access>
  1328. <Equation multiplier="0x4000" offset="0x08000000"/>
  1329. </Bit>
  1330. <Bit config="3">
  1331. <Name>SECWM2_PSTRT</Name>
  1332. <Description>Start page of second secure area</Description>
  1333. <BitOffset>0x0</BitOffset>
  1334. <BitWidth>0x7</BitWidth>
  1335. <Access>RW</Access>
  1336. <Equation multiplier="0x2000" offset="0x08100000"/>
  1337. </Bit>
  1338. <Bit config="2">
  1339. <Name>SECWM2_PEND</Name>
  1340. <Description>End page of second secure area</Description>
  1341. <BitOffset>0x10</BitOffset>
  1342. <BitWidth>0x7</BitWidth>
  1343. <Access>RW</Access>
  1344. <Equation multiplier="0x4000" offset="0x08000000"/>
  1345. </Bit>
  1346. <Bit config="3">
  1347. <Name>SECWM2_PEND</Name>
  1348. <Description>End page of second secure area</Description>
  1349. <BitOffset>0x10</BitOffset>
  1350. <BitWidth>0x7</BitWidth>
  1351. <Access>RW</Access>
  1352. <Equation multiplier="0x2000" offset="0x08100000"/>
  1353. </Bit>
  1354. </AssignedBits>
  1355. </Field>
  1356. <Field>
  1357. <Parameters address="0x50022064" name="FLASH_SECWM2R2" size="0x4"/>
  1358. <AssignedBits>
  1359. <Bit config="2">
  1360. <Name>PCROP2_PSTRT</Name>
  1361. <Description>PRCROP2_PSTRT contains the first page of the PCROP area in bank 2.</Description>
  1362. <BitOffset>0x0</BitOffset>
  1363. <BitWidth>0x7</BitWidth>
  1364. <Access>RW</Access>
  1365. <Equation multiplier="0x4000" offset="0xC100000"/>
  1366. </Bit>
  1367. <Bit config="3">
  1368. <Name>PCROP2_PSTRT</Name>
  1369. <Description>PRCROP2_PSTRT contains the first page of the PCROP area in bank 2.</Description>
  1370. <BitOffset>0x0</BitOffset>
  1371. <BitWidth>0x7</BitWidth>
  1372. <Access>RW</Access>
  1373. <Equation multiplier="0x2000" offset="0xC100000"/>
  1374. </Bit>
  1375. <Bit>
  1376. <Name>PCROP2EN</Name>
  1377. <Description>PCROP2 area enable</Description>
  1378. <BitOffset>0xF</BitOffset>
  1379. <BitWidth>0x1</BitWidth>
  1380. <Access>RW</Access>
  1381. <Values>
  1382. <Val value="0x0">PCROP2 area is disabled</Val>
  1383. <Val value="0x1">PCROP2 area is enabled</Val>
  1384. </Values>
  1385. </Bit>
  1386. </AssignedBits>
  1387. </Field>
  1388. <Field>
  1389. <Parameters address="0x50022064" name="FLASH_SECWM2R2" size="0x4"/>
  1390. <AssignedBits>
  1391. <Bit config="2">
  1392. <Name>HDP2_PEND</Name>
  1393. <Description>End page of second hide protection area</Description>
  1394. <BitOffset>0x10</BitOffset>
  1395. <BitWidth>0x7</BitWidth>
  1396. <Access>RW</Access>
  1397. <Equation multiplier="0x4000" offset="0xC100000"/>
  1398. </Bit>
  1399. <Bit config="3">
  1400. <Name>HDP2_PEND</Name>
  1401. <Description>End page of second hide protection area</Description>
  1402. <BitOffset>0x10</BitOffset>
  1403. <BitWidth>0x7</BitWidth>
  1404. <Access>RW</Access>
  1405. <Equation multiplier="0x2000" offset="0xC100000"/>
  1406. </Bit>
  1407. <Bit>
  1408. <Name>HDP2EN</Name>
  1409. <Description>Hide protection second area enable</Description>
  1410. <BitOffset>0x1F</BitOffset>
  1411. <BitWidth>0x1</BitWidth>
  1412. <Access>RW</Access>
  1413. <Values>
  1414. <Val value="0x0">No HDP area 2</Val>
  1415. <Val value="0x1">HDP second area is enabled</Val>
  1416. </Values>
  1417. </Bit>
  1418. </AssignedBits>
  1419. </Field>
  1420. </Category>
  1421. <Category>
  1422. <Name>Write Protection 2</Name>
  1423. <Field>
  1424. <Parameters address="0x50022068" name="FLASH_WRP2AR" size="0x4"/>
  1425. <AssignedBits>
  1426. <Bit config="2">
  1427. <Name>WRP2A_PSTRT</Name>
  1428. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1429. <BitOffset>0x0</BitOffset>
  1430. <BitWidth>0x7</BitWidth>
  1431. <Access>RW</Access>
  1432. <Equation multiplier="0x4000" offset="0x08100000"/>
  1433. </Bit>
  1434. <Bit config="3">
  1435. <Name>WRP2A_PSTRT</Name>
  1436. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1437. <BitOffset>0x0</BitOffset>
  1438. <BitWidth>0x7</BitWidth>
  1439. <Access>RW</Access>
  1440. <Equation multiplier="0x2000" offset="0x08100000"/>
  1441. </Bit>
  1442. <Bit config="2">
  1443. <Name>WRP2A_PEND</Name>
  1444. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1445. <BitOffset>0x10</BitOffset>
  1446. <BitWidth>0x7</BitWidth>
  1447. <Access>RW</Access>
  1448. <Equation multiplier="0x4000" offset="0x08100000"/>
  1449. </Bit>
  1450. <Bit config="3">
  1451. <Name>WRP2A_PEND</Name>
  1452. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1453. <BitOffset>0x10</BitOffset>
  1454. <BitWidth>0x7</BitWidth>
  1455. <Access>RW</Access>
  1456. <Equation multiplier="0x2000" offset="0x08100000"/>
  1457. </Bit>
  1458. <Bit>
  1459. <Name>UNLOCK_2A</Name>
  1460. <Description>Bank 2 WPR first area A unlock</Description>
  1461. <BitOffset>0x1F</BitOffset>
  1462. <BitWidth>0x1</BitWidth>
  1463. <Access>RW</Access>
  1464. <Values>
  1465. <Val value="0x0">WRP2A start and end pages locked</Val>
  1466. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1467. </Values>
  1468. </Bit>
  1469. </AssignedBits>
  1470. </Field>
  1471. <Field>
  1472. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  1473. <AssignedBits>
  1474. <Bit config="2">
  1475. <Name>WRP2B_PSTRT</Name>
  1476. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1477. <BitOffset>0x0</BitOffset>
  1478. <BitWidth>0x7</BitWidth>
  1479. <Access>RW</Access>
  1480. <Equation multiplier="0x4000" offset="0x08100000"/>
  1481. </Bit>
  1482. <Bit config="3">
  1483. <Name>WRP2B_PSTRT</Name>
  1484. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1485. <BitOffset>0x0</BitOffset>
  1486. <BitWidth>0x7</BitWidth>
  1487. <Access>RW</Access>
  1488. <Equation multiplier="0x2000" offset="0x08100000"/>
  1489. </Bit>
  1490. <Bit config="2">
  1491. <Name>WRP2B_PEND</Name>
  1492. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1493. <BitOffset>0x10</BitOffset>
  1494. <BitWidth>0x7</BitWidth>
  1495. <Access>RW</Access>
  1496. <Equation multiplier="0x4000" offset="0x08100000"/>
  1497. </Bit>
  1498. <Bit config="3">
  1499. <Name>WRP2B_PEND</Name>
  1500. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1501. <BitOffset>0x10</BitOffset>
  1502. <BitWidth>0x7</BitWidth>
  1503. <Access>RW</Access>
  1504. <Equation multiplier="0x2000" offset="0x08100000"/>
  1505. </Bit>
  1506. <Bit>
  1507. <Name>UNLOCK_2B</Name>
  1508. <Description>Bank 2 WPR first area B unlock</Description>
  1509. <BitOffset>0x1F</BitOffset>
  1510. <BitWidth>0x1</BitWidth>
  1511. <Access>RW</Access>
  1512. <Values>
  1513. <Val value="0x0">WRP2B start and end pages locked</Val>
  1514. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1515. </Values>
  1516. </Bit>
  1517. </AssignedBits>
  1518. </Field>
  1519. </Category>
  1520. </Bank>
  1521. <!--Bank interface="JTAG_SWD">
  1522. <Parameters name="Bank 3" size="0x10" address="0x40022070"/>
  1523. <Category>
  1524. <Name>OEMxKEY</Name>
  1525. <Field>
  1526. <Parameters name="FLASH_OEM1KEYR1" size="0x4" address="0x40022070"/>
  1527. <AssignedBits>
  1528. <Bit>
  1529. <Name>OEM1KEY_31_0</Name>
  1530. <Description>OEM1 least significant bytes key</Description>
  1531. <BitOffset>0x0</BitOffset>
  1532. <BitWidth>0x20</BitWidth>
  1533. <Access>RW</Access>
  1534. <Equation multiplier="0x1" offset="0x0"/>
  1535. </Bit>
  1536. </AssignedBits>
  1537. </Field>
  1538. <Field>
  1539. <Parameters name="FLASH_OEM1KEYR2" size="0x4" address="0x40022074"/>
  1540. <AssignedBits>
  1541. <Bit>
  1542. <Name>OEM1KEY_63_32</Name>
  1543. <Description>OEM1 most significant bytes key</Description>
  1544. <BitOffset>0x0</BitOffset>
  1545. <BitWidth>0x20</BitWidth>
  1546. <Access>RW</Access>
  1547. <Equation multiplier="0x1" offset="0x0"/>
  1548. </Bit>
  1549. </AssignedBits>
  1550. </Field>
  1551. <Field>
  1552. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x40022078"/>
  1553. <AssignedBits>
  1554. <Bit>
  1555. <Name>OEM2KEY_31_0</Name>
  1556. <Description>OEM2 least significant bytes key</Description>
  1557. <BitOffset>0x0</BitOffset>
  1558. <BitWidth>0x20</BitWidth>
  1559. <Access>RW</Access>
  1560. <Equation multiplier="0x1" offset="0x0"/>
  1561. </Bit>
  1562. </AssignedBits>
  1563. </Field>
  1564. <Field>
  1565. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x4002207C"/>
  1566. <AssignedBits>
  1567. <Bit>
  1568. <Name>OEM2KEY_63_32</Name>
  1569. <Description>OEM2 most significant bytes key</Description>
  1570. <BitOffset>0x0</BitOffset>
  1571. <BitWidth>0x20</BitWidth>
  1572. <Access>RW</Access>
  1573. <Equation multiplier="0x1" offset="0x0"/>
  1574. </Bit>
  1575. </AssignedBits>
  1576. </Field>
  1577. </Category>
  1578. </Bank-->
  1579. </Configuration>
  1580. <Configuration config="4,5">
  1581. <Bank interface="JTAG_SWD">
  1582. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  1583. <Category>
  1584. <Name>Read Out Protection</Name>
  1585. <Field>
  1586. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1587. <AssignedBits>
  1588. <Bit>
  1589. <Name>RDP</Name>
  1590. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1591. <BitOffset>0x0</BitOffset>
  1592. <BitWidth>0x8</BitWidth>
  1593. <Access>RW</Access>
  1594. <Values>
  1595. <Val value="0xAA">Level 0, no protection</Val>
  1596. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1597. <Val value="0xDC">Level 1, read protection of memories</Val>
  1598. <Val value="0xCC">Level 2, chip protection</Val>
  1599. </Values>
  1600. </Bit>
  1601. </AssignedBits>
  1602. </Field>
  1603. </Category>
  1604. <Category>
  1605. <Name>BOR Level</Name>
  1606. <Field>
  1607. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1608. <AssignedBits>
  1609. <Bit>
  1610. <Name>BOR_LEV</Name>
  1611. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  1612. <BitOffset>0x8</BitOffset>
  1613. <BitWidth>0x3</BitWidth>
  1614. <Access>RW</Access>
  1615. <Values>
  1616. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1617. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1618. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1619. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1620. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1621. </Values>
  1622. </Bit>
  1623. </AssignedBits>
  1624. </Field>
  1625. </Category>
  1626. <Category>
  1627. <Name>User Configuration</Name>
  1628. <Field>
  1629. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1630. <AssignedBits>
  1631. <Bit>
  1632. <Name>nRST_STOP</Name>
  1633. <Description/>
  1634. <BitOffset>0xC</BitOffset>
  1635. <BitWidth>0x1</BitWidth>
  1636. <Access>RW</Access>
  1637. <Values>
  1638. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1639. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1640. </Values>
  1641. </Bit>
  1642. <Bit>
  1643. <Name>nRST_STDBY</Name>
  1644. <Description/>
  1645. <BitOffset>0xD</BitOffset>
  1646. <BitWidth>0x1</BitWidth>
  1647. <Access>RW</Access>
  1648. <Values>
  1649. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1650. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1651. </Values>
  1652. </Bit>
  1653. <Bit>
  1654. <Name>nRST_SHDW</Name>
  1655. <Description/>
  1656. <BitOffset>0xE</BitOffset>
  1657. <BitWidth>0x1</BitWidth>
  1658. <Access>RW</Access>
  1659. <Values>
  1660. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1661. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1662. </Values>
  1663. </Bit>
  1664. <Bit>
  1665. <Name>SRAM134_RST</Name>
  1666. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  1667. <BitOffset>0xF</BitOffset>
  1668. <BitWidth>0x1</BitWidth>
  1669. <Access>RW</Access>
  1670. <Values>
  1671. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  1672. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  1673. </Values>
  1674. </Bit>
  1675. <Bit>
  1676. <Name>IWDG_SW</Name>
  1677. <Description/>
  1678. <BitOffset>0x10</BitOffset>
  1679. <BitWidth>0x1</BitWidth>
  1680. <Access>RW</Access>
  1681. <Values>
  1682. <Val value="0x0">Hardware independant watchdog</Val>
  1683. <Val value="0x1">Software independant watchdog</Val>
  1684. </Values>
  1685. </Bit>
  1686. <Bit>
  1687. <Name>IWDG_STOP</Name>
  1688. <Description/>
  1689. <BitOffset>0x11</BitOffset>
  1690. <BitWidth>0x1</BitWidth>
  1691. <Access>RW</Access>
  1692. <Values>
  1693. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1694. <Val value="0x1">IWDG counter active in stop mode</Val>
  1695. </Values>
  1696. </Bit>
  1697. <Bit>
  1698. <Name>IWDG_STDBY</Name>
  1699. <Description/>
  1700. <BitOffset>0x12</BitOffset>
  1701. <BitWidth>0x1</BitWidth>
  1702. <Access>RW</Access>
  1703. <Values>
  1704. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1705. <Val value="0x1">IWDG counter active in standby mode</Val>
  1706. </Values>
  1707. </Bit>
  1708. <Bit>
  1709. <Name>WWDG_SW</Name>
  1710. <Description/>
  1711. <BitOffset>0x13</BitOffset>
  1712. <BitWidth>0x1</BitWidth>
  1713. <Access>RW</Access>
  1714. <Values>
  1715. <Val value="0x0">Hardware window watchdog</Val>
  1716. <Val value="0x1">Software window watchdog</Val>
  1717. </Values>
  1718. </Bit>
  1719. <Bit>
  1720. <Name>SWAP_BANK</Name>
  1721. <Description/>
  1722. <BitOffset>0x14</BitOffset>
  1723. <BitWidth>0x1</BitWidth>
  1724. <Access>RW</Access>
  1725. <Values>
  1726. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1727. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1728. </Values>
  1729. </Bit>
  1730. <Bit>
  1731. <Name>DBANK</Name>
  1732. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  1733. <BitOffset>0x15</BitOffset>
  1734. <BitWidth>0x1</BitWidth>
  1735. <Access>RW</Access>
  1736. <Values>
  1737. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1738. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1739. </Values>
  1740. </Bit>
  1741. <Bit>
  1742. <Name>SRAM2_PE</Name>
  1743. <Description>SRAM2 parity check enable</Description>
  1744. <BitOffset>0x18</BitOffset>
  1745. <BitWidth>0x1</BitWidth>
  1746. <Access>RW</Access>
  1747. <Values>
  1748. <Val value="0x0">SRAM2 parity check enable</Val>
  1749. <Val value="0x1">SRAM2 parity check disable</Val>
  1750. </Values>
  1751. </Bit>
  1752. <Bit>
  1753. <Name>SRAM2_RST</Name>
  1754. <Description>SRAM2 Erase when system reset</Description>
  1755. <BitOffset>0x19</BitOffset>
  1756. <BitWidth>0x1</BitWidth>
  1757. <Access>RW</Access>
  1758. <Values>
  1759. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1760. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1761. </Values>
  1762. </Bit>
  1763. <Bit>
  1764. <Name>nSWBOOT0</Name>
  1765. <Description>Software BOOT0</Description>
  1766. <BitOffset>0x1A</BitOffset>
  1767. <BitWidth>0x1</BitWidth>
  1768. <Access>RW</Access>
  1769. <Values>
  1770. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1771. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1772. </Values>
  1773. </Bit>
  1774. <Bit>
  1775. <Name>nBOOT0</Name>
  1776. <Description>nBOOT0 option bit</Description>
  1777. <BitOffset>0x1B</BitOffset>
  1778. <BitWidth>0x1</BitWidth>
  1779. <Access>RW</Access>
  1780. <Values>
  1781. <Val value="0x0">nBOOT0 = 0</Val>
  1782. <Val value="0x1">nBOOT0 = 1</Val>
  1783. </Values>
  1784. </Bit>
  1785. <Bit>
  1786. <Name>PA15_PUPEN</Name>
  1787. <Description>PA15 pull-up enable</Description>
  1788. <BitOffset>0x1C</BitOffset>
  1789. <BitWidth>0x1</BitWidth>
  1790. <Access>RW</Access>
  1791. <Values>
  1792. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1793. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1794. </Values>
  1795. </Bit>
  1796. <Bit>
  1797. <Name>BKPRAM_ECC</Name>
  1798. <Description>SRAM2 parity check enable</Description>
  1799. <BitOffset>0x16</BitOffset>
  1800. <BitWidth>0x1</BitWidth>
  1801. <Access>RW</Access>
  1802. <Values>
  1803. <Val value="0x0">Backup RAM ECC check enabled</Val>
  1804. <Val value="0x1">Backup RAM ECC check disabled</Val>
  1805. </Values>
  1806. </Bit>
  1807. <Bit>
  1808. <Name>SRAM3_ECC</Name>
  1809. <Description>SRAM3 ECC detection and correction enable</Description>
  1810. <BitOffset>0x17</BitOffset>
  1811. <BitWidth>0x1</BitWidth>
  1812. <Access>RW</Access>
  1813. <Values>
  1814. <Val value="0x0">SRAM3 ECC check enabled</Val>
  1815. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1816. </Values>
  1817. </Bit>
  1818. <Bit>
  1819. <Name>SRAM2_ECC</Name>
  1820. <Description>SRAM2 ECC detection and correction enable</Description>
  1821. <BitOffset>0x18</BitOffset>
  1822. <BitWidth>0x1</BitWidth>
  1823. <Access>RW</Access>
  1824. <Values>
  1825. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1826. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1827. </Values>
  1828. </Bit>
  1829. <Bit>
  1830. <Name>IO_VDD_HSLV</Name>
  1831. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1832. <BitOffset>0x1D</BitOffset>
  1833. <BitWidth>0x1</BitWidth>
  1834. <Access>RW</Access>
  1835. <Values>
  1836. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1837. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1838. </Values>
  1839. </Bit>
  1840. <Bit>
  1841. <Name>IO_VDDIO2_HSLV</Name>
  1842. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1843. <BitOffset>0x1E</BitOffset>
  1844. <BitWidth>0x1</BitWidth>
  1845. <Access>RW</Access>
  1846. <Values>
  1847. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1848. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1849. </Values>
  1850. </Bit>
  1851. <Bit>
  1852. <Name>TZEN</Name>
  1853. <Description>Global TrustZone security enable</Description>
  1854. <BitOffset>0x1F</BitOffset>
  1855. <BitWidth>0x1</BitWidth>
  1856. <Access>RW</Access>
  1857. <Values>
  1858. <Val value="0x0">Global TrustZone security disabled</Val>
  1859. <Val value="0x1">Global TrustZone security enabled</Val>
  1860. </Values>
  1861. </Bit>
  1862. </AssignedBits>
  1863. </Field>
  1864. </Category>
  1865. <Category>
  1866. <Name>Boot Configuration</Name>
  1867. <Field>
  1868. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1869. <AssignedBits>
  1870. <Bit>
  1871. <Name>NSBOOTADD0</Name>
  1872. <Description>Non-secure Boot base address 0</Description>
  1873. <BitOffset>0x7</BitOffset>
  1874. <BitWidth>0x19</BitWidth>
  1875. <Access>RW</Access>
  1876. <Equation multiplier="0x80" offset="0x0000000"/>
  1877. </Bit>
  1878. </AssignedBits>
  1879. </Field>
  1880. <Field>
  1881. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1882. <AssignedBits>
  1883. <Bit>
  1884. <Name>NSBOOTADD1</Name>
  1885. <Description>Non-secure Boot base address 1</Description>
  1886. <BitOffset>0x7</BitOffset>
  1887. <BitWidth>0x19</BitWidth>
  1888. <Access>RW</Access>
  1889. <Equation multiplier="0x80" offset="0x0000000"/>
  1890. </Bit>
  1891. </AssignedBits>
  1892. </Field>
  1893. <Field>
  1894. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1895. <AssignedBits>
  1896. <Bit>
  1897. <Name>SECBOOTADD0</Name>
  1898. <Description>Secure boot base address 0</Description>
  1899. <BitOffset>0x7</BitOffset>
  1900. <BitWidth>0x19</BitWidth>
  1901. <Access>RW</Access>
  1902. <Equation multiplier="0x80" offset="0x0000000"/>
  1903. </Bit>
  1904. </AssignedBits>
  1905. </Field>
  1906. <Field>
  1907. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1908. <AssignedBits>
  1909. <Bit>
  1910. <Name>BOOT_LOCK</Name>
  1911. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1912. <BitOffset>0x0</BitOffset>
  1913. <BitWidth>0x1</BitWidth>
  1914. <Access>RW</Access>
  1915. <Values>
  1916. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1917. <Val value="0x1">Boot forced from base address memory</Val>
  1918. </Values>
  1919. </Bit>
  1920. </AssignedBits>
  1921. </Field>
  1922. </Category>
  1923. <Category>
  1924. <Name>Secure Area 1</Name>
  1925. <Field>
  1926. <Parameters address="0x40022054" name="FLASH_SECWM1R2" size="0x4"/>
  1927. <AssignedBits>
  1928. <Bit config="4">
  1929. <Name>PCROP1_PSTRT</Name>
  1930. <Description>This field contains the first page of the PCROP area in bank 1</Description>
  1931. <BitOffset>0x0</BitOffset>
  1932. <BitWidth>0x7</BitWidth>
  1933. <Access>RW</Access>
  1934. <Equation multiplier="0x4000" offset="0xC000000"/>
  1935. </Bit>
  1936. <Bit config="5">
  1937. <Name>PCROP1_PSTRT</Name>
  1938. <Description>This field contains the first page of the PCROP area in bank 1</Description>
  1939. <BitOffset>0x0</BitOffset>
  1940. <BitWidth>0x7</BitWidth>
  1941. <Access>RW</Access>
  1942. <Equation multiplier="0x2000" offset="0xC000000"/>
  1943. </Bit>
  1944. <Bit>
  1945. <Name>PCROP1EN</Name>
  1946. <Description>PCROP1 area enable</Description>
  1947. <BitOffset>0xF</BitOffset>
  1948. <BitWidth>0x1</BitWidth>
  1949. <Access>RW</Access>
  1950. <Values>
  1951. <Val value="0x0">PCROP1 area is disabled</Val>
  1952. <Val value="0x1">PCROP1 area is enabled</Val>
  1953. </Values>
  1954. </Bit>
  1955. </AssignedBits>
  1956. </Field>
  1957. <Field>
  1958. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  1959. <AssignedBits>
  1960. <Bit config="4">
  1961. <Name>HDP1_PEND</Name>
  1962. <Description>End page of first hide protection area</Description>
  1963. <BitOffset>0x10</BitOffset>
  1964. <BitWidth>0x7</BitWidth>
  1965. <Access>RW</Access>
  1966. <Equation multiplier="0x4000" offset="0xC000000"/>
  1967. </Bit>
  1968. <Bit config="5">
  1969. <Name>HDP1_PEND</Name>
  1970. <Description>End page of first hide protection area</Description>
  1971. <BitOffset>0x10</BitOffset>
  1972. <BitWidth>0x7</BitWidth>
  1973. <Access>RW</Access>
  1974. <Equation multiplier="0x2000" offset="0xC000000"/>
  1975. </Bit>
  1976. <Bit>
  1977. <Name>HDP1EN</Name>
  1978. <Description>Hide protection first area enable</Description>
  1979. <BitOffset>0x1F</BitOffset>
  1980. <BitWidth>0x1</BitWidth>
  1981. <Access>RW</Access>
  1982. <Values>
  1983. <Val value="0x0">No HDP area 1</Val>
  1984. <Val value="0x1">HDP first area is enabled</Val>
  1985. </Values>
  1986. </Bit>
  1987. </AssignedBits>
  1988. </Field>
  1989. <Field>
  1990. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  1991. <AssignedBits>
  1992. <Bit config="4">
  1993. <Name>SECWM1_PSTRT</Name>
  1994. <Description>Start page of first secure area</Description>
  1995. <BitOffset>0x0</BitOffset>
  1996. <BitWidth>0x7</BitWidth>
  1997. <Access>RW</Access>
  1998. <Equation multiplier="0x4000" offset="0x08000000"/>
  1999. </Bit>
  2000. <Bit config="5">
  2001. <Name>SECWM1_PSTRT</Name>
  2002. <Description>Start page of first secure area</Description>
  2003. <BitOffset>0x0</BitOffset>
  2004. <BitWidth>0x7</BitWidth>
  2005. <Access>RW</Access>
  2006. <Equation multiplier="0x2000" offset="0x08000000"/>
  2007. </Bit>
  2008. <Bit config="4">
  2009. <Name>SECWM1_PEND</Name>
  2010. <Description>End page of first secure area</Description>
  2011. <BitOffset>0x10</BitOffset>
  2012. <BitWidth>0x7</BitWidth>
  2013. <Access>RW</Access>
  2014. <Equation multiplier="0x4000" offset="0x08000000"/>
  2015. </Bit>
  2016. <Bit config="5">
  2017. <Name>SECWM1_PEND</Name>
  2018. <Description>End page of first secure area</Description>
  2019. <BitOffset>0x10</BitOffset>
  2020. <BitWidth>0x7</BitWidth>
  2021. <Access>RW</Access>
  2022. <Equation multiplier="0x2000" offset="0x08000000"/>
  2023. </Bit>
  2024. </AssignedBits>
  2025. </Field>
  2026. </Category>
  2027. <Category>
  2028. <Name>Write Protection 1</Name>
  2029. <Field>
  2030. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2031. <AssignedBits>
  2032. <Bit config="4">
  2033. <Name>WRP1A_PSTRT</Name>
  2034. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2035. <BitOffset>0x0</BitOffset>
  2036. <BitWidth>0x7</BitWidth>
  2037. <Access>RW</Access>
  2038. <Equation multiplier="0x4000" offset="0x08000000"/>
  2039. </Bit>
  2040. <Bit config="5">
  2041. <Name>WRP1A_PSTRT</Name>
  2042. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2043. <BitOffset>0x0</BitOffset>
  2044. <BitWidth>0x7</BitWidth>
  2045. <Access>RW</Access>
  2046. <Equation multiplier="0x2000" offset="0x08000000"/>
  2047. </Bit>
  2048. <Bit config="4">
  2049. <Name>WRP1A_PEND</Name>
  2050. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2051. <BitOffset>0x10</BitOffset>
  2052. <BitWidth>0x7</BitWidth>
  2053. <Access>RW</Access>
  2054. <Equation multiplier="0x4000" offset="0x08000000"/>
  2055. </Bit>
  2056. <Bit config="5">
  2057. <Name>WRP1A_PEND</Name>
  2058. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2059. <BitOffset>0x10</BitOffset>
  2060. <BitWidth>0x7</BitWidth>
  2061. <Access>RW</Access>
  2062. <Equation multiplier="0x2000" offset="0x08000000"/>
  2063. </Bit>
  2064. <Bit>
  2065. <Name>UNLOCK_1A</Name>
  2066. <Description>Bank 1 WPR first area A unlock</Description>
  2067. <BitOffset>0x1F</BitOffset>
  2068. <BitWidth>0x1</BitWidth>
  2069. <Access>RW</Access>
  2070. <Values>
  2071. <Val value="0x0">WRP1A start and end pages locked</Val>
  2072. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  2073. </Values>
  2074. </Bit>
  2075. </AssignedBits>
  2076. </Field>
  2077. <Field>
  2078. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  2079. <AssignedBits>
  2080. <Bit config="4">
  2081. <Name>WRP1B_PSTRT</Name>
  2082. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2083. <BitOffset>0x0</BitOffset>
  2084. <BitWidth>0x7</BitWidth>
  2085. <Access>RW</Access>
  2086. <Equation multiplier="0x4000" offset="0x08000000"/>
  2087. </Bit>
  2088. <Bit config="5">
  2089. <Name>WRP1B_PSTRT</Name>
  2090. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2091. <BitOffset>0x0</BitOffset>
  2092. <BitWidth>0x7</BitWidth>
  2093. <Access>RW</Access>
  2094. <Equation multiplier="0x2000" offset="0x08000000"/>
  2095. </Bit>
  2096. <Bit config="4">
  2097. <Name>WRP1B_PEND</Name>
  2098. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2099. <BitOffset>0x10</BitOffset>
  2100. <BitWidth>0x7</BitWidth>
  2101. <Access>RW</Access>
  2102. <Equation multiplier="0x4000" offset="0x08000000"/>
  2103. </Bit>
  2104. <Bit config="5">
  2105. <Name>WRP1B_PEND</Name>
  2106. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2107. <BitOffset>0x10</BitOffset>
  2108. <BitWidth>0x7</BitWidth>
  2109. <Access>RW</Access>
  2110. <Equation multiplier="0x2000" offset="0x08000000"/>
  2111. </Bit>
  2112. <Bit>
  2113. <Name>UNLOCK_1B</Name>
  2114. <Description>Bank 1 WPR first area B unlock</Description>
  2115. <BitOffset>0x1F</BitOffset>
  2116. <BitWidth>0x1</BitWidth>
  2117. <Access>RW</Access>
  2118. <Values>
  2119. <Val value="0x0">WRP1B start and end pages locked</Val>
  2120. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  2121. </Values>
  2122. </Bit>
  2123. </AssignedBits>
  2124. </Field>
  2125. </Category>
  2126. </Bank>
  2127. <Bank interface="JTAG_SWD">
  2128. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  2129. <Category>
  2130. <Name>Secure Area 2</Name>
  2131. <Field>
  2132. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  2133. <AssignedBits>
  2134. <Bit config="4">
  2135. <Name>SECWM2_PSTRT</Name>
  2136. <Description>Start page of second secure area</Description>
  2137. <BitOffset>0x0</BitOffset>
  2138. <BitWidth>0x7</BitWidth>
  2139. <Access>RW</Access>
  2140. <Equation multiplier="0x4000" offset="0x08000000"/>
  2141. </Bit>
  2142. <Bit config="5">
  2143. <Name>SECWM2_PSTRT</Name>
  2144. <Description>Start page of second secure area</Description>
  2145. <BitOffset>0x0</BitOffset>
  2146. <BitWidth>0x7</BitWidth>
  2147. <Access>RW</Access>
  2148. <Equation multiplier="0x2000" offset="0x08100000"/>
  2149. </Bit>
  2150. <Bit config="4">
  2151. <Name>SECWM2_PEND</Name>
  2152. <Description>End page of second secure area</Description>
  2153. <BitOffset>0x10</BitOffset>
  2154. <BitWidth>0x7</BitWidth>
  2155. <Access>RW</Access>
  2156. <Equation multiplier="0x4000" offset="0x08000000"/>
  2157. </Bit>
  2158. <Bit config="5">
  2159. <Name>SECWM2_PEND</Name>
  2160. <Description>End page of second secure area</Description>
  2161. <BitOffset>0x10</BitOffset>
  2162. <BitWidth>0x7</BitWidth>
  2163. <Access>RW</Access>
  2164. <Equation multiplier="0x2000" offset="0x08100000"/>
  2165. </Bit>
  2166. </AssignedBits>
  2167. </Field>
  2168. <Field>
  2169. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2170. <AssignedBits>
  2171. <Bit config="4">
  2172. <Name>PCROP2_PSTRT</Name>
  2173. <Description>PRCROP2_PSTRT contains the first page of the PCROP area in bank 2.</Description>
  2174. <BitOffset>0x0</BitOffset>
  2175. <BitWidth>0x7</BitWidth>
  2176. <Access>RW</Access>
  2177. <Equation multiplier="0x4000" offset="0xC100000"/>
  2178. </Bit>
  2179. <Bit config="5">
  2180. <Name>PCROP2_PSTRT</Name>
  2181. <Description>PRCROP2_PSTRT contains the first page of the PCROP area in bank 2.</Description>
  2182. <BitOffset>0x0</BitOffset>
  2183. <BitWidth>0x7</BitWidth>
  2184. <Access>RW</Access>
  2185. <Equation multiplier="0x2000" offset="0xC100000"/>
  2186. </Bit>
  2187. <Bit>
  2188. <Name>PCROP2EN</Name>
  2189. <Description>PCROP2 area enable</Description>
  2190. <BitOffset>0xF</BitOffset>
  2191. <BitWidth>0x1</BitWidth>
  2192. <Access>RW</Access>
  2193. <Values>
  2194. <Val value="0x0">PCROP2 area is disabled</Val>
  2195. <Val value="0x1">PCROP2 area is enabled</Val>
  2196. </Values>
  2197. </Bit>
  2198. </AssignedBits>
  2199. </Field>
  2200. <Field>
  2201. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2202. <AssignedBits>
  2203. <Bit config="4">
  2204. <Name>HDP2_PEND</Name>
  2205. <Description>End page of second hide protection area</Description>
  2206. <BitOffset>0x10</BitOffset>
  2207. <BitWidth>0x7</BitWidth>
  2208. <Access>RW</Access>
  2209. <Equation multiplier="0x4000" offset="0xC100000"/>
  2210. </Bit>
  2211. <Bit config="5">
  2212. <Name>HDP2_PEND</Name>
  2213. <Description>End page of second hide protection area</Description>
  2214. <BitOffset>0x10</BitOffset>
  2215. <BitWidth>0x7</BitWidth>
  2216. <Access>RW</Access>
  2217. <Equation multiplier="0x2000" offset="0xC100000"/>
  2218. </Bit>
  2219. <Bit>
  2220. <Name>HDP2EN</Name>
  2221. <Description>Hide protection second area enable</Description>
  2222. <BitOffset>0x1F</BitOffset>
  2223. <BitWidth>0x1</BitWidth>
  2224. <Access>RW</Access>
  2225. <Values>
  2226. <Val value="0x0">No HDP area 2</Val>
  2227. <Val value="0x1">HDP second area is enabled</Val>
  2228. </Values>
  2229. </Bit>
  2230. </AssignedBits>
  2231. </Field>
  2232. </Category>
  2233. <Category>
  2234. <Name>Write Protection 2</Name>
  2235. <Field>
  2236. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2237. <AssignedBits>
  2238. <Bit config="4">
  2239. <Name>WRP2A_PSTRT</Name>
  2240. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2241. <BitOffset>0x0</BitOffset>
  2242. <BitWidth>0x7</BitWidth>
  2243. <Access>RW</Access>
  2244. <Equation multiplier="0x4000" offset="0x08100000"/>
  2245. </Bit>
  2246. <Bit config="5">
  2247. <Name>WRP2A_PSTRT</Name>
  2248. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2249. <BitOffset>0x0</BitOffset>
  2250. <BitWidth>0x7</BitWidth>
  2251. <Access>RW</Access>
  2252. <Equation multiplier="0x2000" offset="0x08100000"/>
  2253. </Bit>
  2254. <Bit config="4">
  2255. <Name>WRP2A_PEND</Name>
  2256. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2257. <BitOffset>0x10</BitOffset>
  2258. <BitWidth>0x7</BitWidth>
  2259. <Access>RW</Access>
  2260. <Equation multiplier="0x4000" offset="0x08100000"/>
  2261. </Bit>
  2262. <Bit config="5">
  2263. <Name>WRP2A_PEND</Name>
  2264. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2265. <BitOffset>0x10</BitOffset>
  2266. <BitWidth>0x7</BitWidth>
  2267. <Access>RW</Access>
  2268. <Equation multiplier="0x2000" offset="0x08100000"/>
  2269. </Bit>
  2270. <Bit>
  2271. <Name>UNLOCK_2A</Name>
  2272. <Description>Bank 2 WPR first area A unlock</Description>
  2273. <BitOffset>0x1F</BitOffset>
  2274. <BitWidth>0x1</BitWidth>
  2275. <Access>RW</Access>
  2276. <Values>
  2277. <Val value="0x0">WRP2A start and end pages locked</Val>
  2278. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2279. </Values>
  2280. </Bit>
  2281. </AssignedBits>
  2282. </Field>
  2283. <Field>
  2284. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2285. <AssignedBits>
  2286. <Bit config="4">
  2287. <Name>WRP2B_PSTRT</Name>
  2288. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2289. <BitOffset>0x0</BitOffset>
  2290. <BitWidth>0x7</BitWidth>
  2291. <Access>RW</Access>
  2292. <Equation multiplier="0x4000" offset="0x08100000"/>
  2293. </Bit>
  2294. <Bit config="5">
  2295. <Name>WRP2B_PSTRT</Name>
  2296. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2297. <BitOffset>0x0</BitOffset>
  2298. <BitWidth>0x7</BitWidth>
  2299. <Access>RW</Access>
  2300. <Equation multiplier="0x2000" offset="0x08100000"/>
  2301. </Bit>
  2302. <Bit config="4">
  2303. <Name>WRP2B_PEND</Name>
  2304. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2305. <BitOffset>0x10</BitOffset>
  2306. <BitWidth>0x7</BitWidth>
  2307. <Access>RW</Access>
  2308. <Equation multiplier="0x4000" offset="0x08100000"/>
  2309. </Bit>
  2310. <Bit config="5">
  2311. <Name>WRP2B_PEND</Name>
  2312. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2313. <BitOffset>0x10</BitOffset>
  2314. <BitWidth>0x7</BitWidth>
  2315. <Access>RW</Access>
  2316. <Equation multiplier="0x2000" offset="0x08100000"/>
  2317. </Bit>
  2318. <Bit>
  2319. <Name>UNLOCK_2B</Name>
  2320. <Description>Bank 2 WPR first area B unlock</Description>
  2321. <BitOffset>0x1F</BitOffset>
  2322. <BitWidth>0x1</BitWidth>
  2323. <Access>RW</Access>
  2324. <Values>
  2325. <Val value="0x0">WRP2B start and end pages locked</Val>
  2326. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2327. </Values>
  2328. </Bit>
  2329. </AssignedBits>
  2330. </Field>
  2331. </Category>
  2332. </Bank>
  2333. <!--Bank interface="JTAG_SWD">
  2334. <Parameters name="Bank 3" size="0x10" address="0x40022070"/>
  2335. <Category>
  2336. <Name>OEMxKEY</Name>
  2337. <Field>
  2338. <Parameters name="FLASH_OEM1KEYR1" size="0x4" address="0x40022070"/>
  2339. <AssignedBits>
  2340. <Bit>
  2341. <Name>OEM1KEY_31_0</Name>
  2342. <Description>OEM1 least significant bytes key</Description>
  2343. <BitOffset>0x0</BitOffset>
  2344. <BitWidth>0x20</BitWidth>
  2345. <Access>RW</Access>
  2346. <Equation multiplier="0x1" offset="0x0"/>
  2347. </Bit>
  2348. </AssignedBits>
  2349. </Field>
  2350. <Field>
  2351. <Parameters name="FLASH_OEM1KEYR2" size="0x4" address="0x40022074"/>
  2352. <AssignedBits>
  2353. <Bit>
  2354. <Name>OEM1KEY_63_32</Name>
  2355. <Description>OEM1 most significant bytes key</Description>
  2356. <BitOffset>0x0</BitOffset>
  2357. <BitWidth>0x20</BitWidth>
  2358. <Access>RW</Access>
  2359. <Equation multiplier="0x1" offset="0x0"/>
  2360. </Bit>
  2361. </AssignedBits>
  2362. </Field>
  2363. <Field>
  2364. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x40022078"/>
  2365. <AssignedBits>
  2366. <Bit>
  2367. <Name>OEM2KEY_31_0</Name>
  2368. <Description>OEM2 least significant bytes key</Description>
  2369. <BitOffset>0x0</BitOffset>
  2370. <BitWidth>0x20</BitWidth>
  2371. <Access>RW</Access>
  2372. <Equation multiplier="0x1" offset="0x0"/>
  2373. </Bit>
  2374. </AssignedBits>
  2375. </Field>
  2376. <Field>
  2377. <Parameters name="FLASH_OEM2KEYR1" size="0x4" address="0x4002207C"/>
  2378. <AssignedBits>
  2379. <Bit>
  2380. <Name>OEM2KEY_63_32</Name>
  2381. <Description>OEM2 most significant bytes key</Description>
  2382. <BitOffset>0x0</BitOffset>
  2383. <BitWidth>0x20</BitWidth>
  2384. <Access>RW</Access>
  2385. <Equation multiplier="0x1" offset="0x0"/>
  2386. </Bit>
  2387. </AssignedBits>
  2388. </Field>
  2389. </Category>
  2390. </Bank-->
  2391. </Configuration>
  2392. <Bank interface="Bootloader">
  2393. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  2394. <Category>
  2395. <Name>Read Out Protection</Name>
  2396. <Field>
  2397. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2398. <AssignedBits>
  2399. <Bit>
  2400. <Name>RDP</Name>
  2401. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  2402. <BitOffset>0x0</BitOffset>
  2403. <BitWidth>0x8</BitWidth>
  2404. <Access>RW</Access>
  2405. <Values>
  2406. <Val value="0xAA">Level 0, no protection</Val>
  2407. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  2408. <Val value="0xDC">Level 1, read protection of memories</Val>
  2409. <Val value="0xCC">Level 2, chip protection</Val>
  2410. </Values>
  2411. </Bit>
  2412. </AssignedBits>
  2413. </Field>
  2414. </Category>
  2415. <Category>
  2416. <Name>BOR Level</Name>
  2417. <Field>
  2418. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2419. <AssignedBits>
  2420. <Bit>
  2421. <Name>BOR_LEV</Name>
  2422. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  2423. <BitOffset>0x8</BitOffset>
  2424. <BitWidth>0x3</BitWidth>
  2425. <Access>RW</Access>
  2426. <Values>
  2427. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  2428. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  2429. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  2430. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  2431. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  2432. </Values>
  2433. </Bit>
  2434. </AssignedBits>
  2435. </Field>
  2436. </Category>
  2437. <Category>
  2438. <Name>User Configuration</Name>
  2439. <Field>
  2440. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2441. <AssignedBits>
  2442. <Bit>
  2443. <Name>nRST_STOP</Name>
  2444. <Description/>
  2445. <BitOffset>0xC</BitOffset>
  2446. <BitWidth>0x1</BitWidth>
  2447. <Access>RW</Access>
  2448. <Values>
  2449. <Val value="0x0">Reset generated when entering Stop mode</Val>
  2450. <Val value="0x1">No reset generated when entering Stop mode</Val>
  2451. </Values>
  2452. </Bit>
  2453. <Bit>
  2454. <Name>nRST_STDBY</Name>
  2455. <Description/>
  2456. <BitOffset>0xD</BitOffset>
  2457. <BitWidth>0x1</BitWidth>
  2458. <Access>RW</Access>
  2459. <Values>
  2460. <Val value="0x0">Reset generated when entering Standby mode</Val>
  2461. <Val value="0x1">No reset generated when entering Standby mode</Val>
  2462. </Values>
  2463. </Bit>
  2464. <Bit>
  2465. <Name>nRST_SHDW</Name>
  2466. <Description/>
  2467. <BitOffset>0xE</BitOffset>
  2468. <BitWidth>0x1</BitWidth>
  2469. <Access>RW</Access>
  2470. <Values>
  2471. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  2472. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  2473. </Values>
  2474. </Bit>
  2475. <Bit>
  2476. <Name>IWDG_SW</Name>
  2477. <Description/>
  2478. <BitOffset>0x10</BitOffset>
  2479. <BitWidth>0x1</BitWidth>
  2480. <Access>RW</Access>
  2481. <Values>
  2482. <Val value="0x0">Hardware independant watchdog</Val>
  2483. <Val value="0x1">Software independant watchdog</Val>
  2484. </Values>
  2485. </Bit>
  2486. <Bit>
  2487. <Name>IWDG_STOP</Name>
  2488. <Description/>
  2489. <BitOffset>0x11</BitOffset>
  2490. <BitWidth>0x1</BitWidth>
  2491. <Access>RW</Access>
  2492. <Values>
  2493. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  2494. <Val value="0x1">IWDG counter active in stop mode</Val>
  2495. </Values>
  2496. </Bit>
  2497. <Bit>
  2498. <Name>IWDG_STDBY</Name>
  2499. <Description/>
  2500. <BitOffset>0x12</BitOffset>
  2501. <BitWidth>0x1</BitWidth>
  2502. <Access>RW</Access>
  2503. <Values>
  2504. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  2505. <Val value="0x1">IWDG counter active in standby mode</Val>
  2506. </Values>
  2507. </Bit>
  2508. <Bit>
  2509. <Name>WWDG_SW</Name>
  2510. <Description/>
  2511. <BitOffset>0x13</BitOffset>
  2512. <BitWidth>0x1</BitWidth>
  2513. <Access>RW</Access>
  2514. <Values>
  2515. <Val value="0x0">Hardware window watchdog</Val>
  2516. <Val value="0x1">Software window watchdog</Val>
  2517. </Values>
  2518. </Bit>
  2519. <Bit>
  2520. <Name>SWAP_BANK</Name>
  2521. <Description/>
  2522. <BitOffset>0x14</BitOffset>
  2523. <BitWidth>0x1</BitWidth>
  2524. <Access>RW</Access>
  2525. <Values>
  2526. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  2527. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  2528. </Values>
  2529. </Bit>
  2530. <Bit>
  2531. <Name>DB256</Name>
  2532. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  2533. <BitOffset>0x15</BitOffset>
  2534. <BitWidth>0x1</BitWidth>
  2535. <Access>RW</Access>
  2536. <Values>
  2537. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  2538. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  2539. </Values>
  2540. </Bit>
  2541. <Bit>
  2542. <Name>DBANK</Name>
  2543. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  2544. <BitOffset>0x16</BitOffset>
  2545. <BitWidth>0x1</BitWidth>
  2546. <Access>RW</Access>
  2547. <Values>
  2548. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  2549. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  2550. </Values>
  2551. </Bit>
  2552. <Bit>
  2553. <Name>SRAM2_PE</Name>
  2554. <Description>SRAM2 parity check enable</Description>
  2555. <BitOffset>0x18</BitOffset>
  2556. <BitWidth>0x1</BitWidth>
  2557. <Access>RW</Access>
  2558. <Values>
  2559. <Val value="0x0">SRAM2 parity check enable</Val>
  2560. <Val value="0x1">SRAM2 parity check disable</Val>
  2561. </Values>
  2562. </Bit>
  2563. <Bit>
  2564. <Name>SRAM2_RST</Name>
  2565. <Description>SRAM2 Erase when system reset</Description>
  2566. <BitOffset>0x19</BitOffset>
  2567. <BitWidth>0x1</BitWidth>
  2568. <Access>RW</Access>
  2569. <Values>
  2570. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  2571. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  2572. </Values>
  2573. </Bit>
  2574. <Bit>
  2575. <Name>nSWBOOT0</Name>
  2576. <Description>Software BOOT0</Description>
  2577. <BitOffset>0x1A</BitOffset>
  2578. <BitWidth>0x1</BitWidth>
  2579. <Access>RW</Access>
  2580. <Values>
  2581. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  2582. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  2583. </Values>
  2584. </Bit>
  2585. <Bit>
  2586. <Name>nBOOT0</Name>
  2587. <Description>nBOOT0 option bit</Description>
  2588. <BitOffset>0x1B</BitOffset>
  2589. <BitWidth>0x1</BitWidth>
  2590. <Access>RW</Access>
  2591. <Values>
  2592. <Val value="0x0">nBOOT0 = 0</Val>
  2593. <Val value="0x1">nBOOT0 = 1</Val>
  2594. </Values>
  2595. </Bit>
  2596. <Bit>
  2597. <Name>PA15_PUPEN</Name>
  2598. <Description>PA15 pull-up enable</Description>
  2599. <BitOffset>0x1C</BitOffset>
  2600. <BitWidth>0x1</BitWidth>
  2601. <Access>RW</Access>
  2602. <Values>
  2603. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  2604. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  2605. </Values>
  2606. </Bit>
  2607. <Bit>
  2608. <Name>TZEN</Name>
  2609. <Description>Global TrustZone security enable</Description>
  2610. <BitOffset>0x1F</BitOffset>
  2611. <BitWidth>0x1</BitWidth>
  2612. <Access>RW</Access>
  2613. <Values>
  2614. <Val value="0x0">Global TrustZone security disabled</Val>
  2615. <Val value="0x1">Global TrustZone security enabled</Val>
  2616. </Values>
  2617. </Bit>
  2618. </AssignedBits>
  2619. </Field>
  2620. <Field>
  2621. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  2622. <AssignedBits>
  2623. <Bit config="6,7,8,9">
  2624. <Name>HDP1EN</Name>
  2625. <Description>Hide protection first area enable</Description>
  2626. <BitOffset>0x1F</BitOffset>
  2627. <BitWidth>0x1</BitWidth>
  2628. <Access>RW</Access>
  2629. <Values>
  2630. <Val value="0x0">No HDP area 1</Val>
  2631. <Val value="0x1">HDP first area is enabled</Val>
  2632. </Values>
  2633. </Bit>
  2634. <Bit config="6,8">
  2635. <Name>HDP1_PEND</Name>
  2636. <Description>End page of first hide protection area</Description>
  2637. <BitOffset>0x10</BitOffset>
  2638. <BitWidth>0x7</BitWidth>
  2639. <Access>RW</Access>
  2640. <Equation multiplier="0x4" offset="0x08000000"/>
  2641. </Bit>
  2642. <Bit config="7,9">
  2643. <Name>HDP1_PEND</Name>
  2644. <Description>End page of first hide protection area</Description>
  2645. <BitOffset>0x10</BitOffset>
  2646. <BitWidth>0x7</BitWidth>
  2647. <Access>RW</Access>
  2648. <Equation multiplier="0x2" offset="0x08000000"/>
  2649. </Bit>
  2650. </AssignedBits>
  2651. </Field>
  2652. <Field>
  2653. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2654. <AssignedBits>
  2655. <Bit config="6,7,8,9">
  2656. <Name>HDP2EN</Name>
  2657. <Description>Hide protection second area enable</Description>
  2658. <BitOffset>0x1F</BitOffset>
  2659. <BitWidth>0x1</BitWidth>
  2660. <Access>RW</Access>
  2661. <Values>
  2662. <Val value="0x0">No HDP area 2</Val>
  2663. <Val value="0x1">HDP second area is enabled</Val>
  2664. </Values>
  2665. </Bit>
  2666. <Bit config="6,8">
  2667. <Name>HDP2_PEND</Name>
  2668. <Description>End page of second hide protection area</Description>
  2669. <BitOffset>0x10</BitOffset>
  2670. <BitWidth>0x7</BitWidth>
  2671. <Access>RW</Access>
  2672. <Equation multiplier="0x4" offset="0x08000000"/>
  2673. </Bit>
  2674. <Bit config="7,9">
  2675. <Name>HDP2_PEND</Name>
  2676. <Description>End page of second hide protection area</Description>
  2677. <BitOffset>0x10</BitOffset>
  2678. <BitWidth>0x7</BitWidth>
  2679. <Access>RW</Access>
  2680. <Equation multiplier="0x2" offset="0x08000000"/>
  2681. </Bit>
  2682. </AssignedBits>
  2683. </Field>
  2684. <Field>
  2685. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2686. <AssignedBits>
  2687. <Bit>
  2688. <Name>NSBOOTADD0</Name>
  2689. <Description>Non-secure Boot base address 0</Description>
  2690. <BitOffset>0x7</BitOffset>
  2691. <BitWidth>0x19</BitWidth>
  2692. <Access>RW</Access>
  2693. <Equation multiplier="0x80" offset="0x0000000"/>
  2694. </Bit>
  2695. </AssignedBits>
  2696. </Field>
  2697. <Field>
  2698. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2699. <AssignedBits>
  2700. <Bit>
  2701. <Name>NSBOOTADD1</Name>
  2702. <Description>Non-secure Boot base address 1</Description>
  2703. <BitOffset>0x7</BitOffset>
  2704. <BitWidth>0x19</BitWidth>
  2705. <Access>RW</Access>
  2706. <Equation multiplier="0x80" offset="0x0000000"/>
  2707. </Bit>
  2708. </AssignedBits>
  2709. </Field>
  2710. <Field>
  2711. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  2712. <AssignedBits>
  2713. <Bit>
  2714. <Name>SECBOOTADD0</Name>
  2715. <Description>Secure boot base address 0</Description>
  2716. <BitOffset>0x7</BitOffset>
  2717. <BitWidth>0x19</BitWidth>
  2718. <Access>RW</Access>
  2719. <Equation multiplier="0x80" offset="0x0000000"/>
  2720. </Bit>
  2721. </AssignedBits>
  2722. </Field>
  2723. </Category>
  2724. <Category>
  2725. <Name>Secure area 1</Name>
  2726. <Field>
  2727. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  2728. <AssignedBits>
  2729. <Bit config="6,8">
  2730. <Name>SECWM1_PSTRT</Name>
  2731. <Description>Start page of first secure area</Description>
  2732. <BitOffset>0x0</BitOffset>
  2733. <BitWidth>0x7</BitWidth>
  2734. <Access>RW</Access>
  2735. <Equation multiplier="0x1000" offset="0x08000000"/>
  2736. </Bit>
  2737. <Bit config="7,9">
  2738. <Name>SECWM1_PSTRT</Name>
  2739. <Description>Start page of first secure area</Description>
  2740. <BitOffset>0x0</BitOffset>
  2741. <BitWidth>0x7</BitWidth>
  2742. <Access>RW</Access>
  2743. <Equation multiplier="0x800" offset="0x08000000"/>
  2744. </Bit>
  2745. <Bit config="6,8">
  2746. <Name>SECWM1_PEND</Name>
  2747. <Description>End page of first secure area</Description>
  2748. <BitOffset>0x10</BitOffset>
  2749. <BitWidth>0x7</BitWidth>
  2750. <Access>RW</Access>
  2751. <Equation multiplier="0x1000" offset="0x08000000"/>
  2752. </Bit>
  2753. <Bit config="7,9">
  2754. <Name>SECWM1_PEND</Name>
  2755. <Description>End page of first secure area</Description>
  2756. <BitOffset>0x10</BitOffset>
  2757. <BitWidth>0x7</BitWidth>
  2758. <Access>RW</Access>
  2759. <Equation multiplier="0x800" offset="0x08000000"/>
  2760. </Bit>
  2761. </AssignedBits>
  2762. </Field>
  2763. </Category>
  2764. <Category>
  2765. <Name>Write Protection 1</Name>
  2766. <Field>
  2767. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2768. <AssignedBits>
  2769. <Bit config="6,8">
  2770. <Name>WRP1A_PSTRT</Name>
  2771. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2772. <BitOffset>0x0</BitOffset>
  2773. <BitWidth>0x7</BitWidth>
  2774. <Access>RW</Access>
  2775. <Equation multiplier="0x1000" offset="0x08000000"/>
  2776. </Bit>
  2777. <Bit config="7,9">
  2778. <Name>WRP1A_PSTRT</Name>
  2779. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2780. <BitOffset>0x0</BitOffset>
  2781. <BitWidth>0x7</BitWidth>
  2782. <Access>RW</Access>
  2783. <Equation multiplier="0x800" offset="0x08000000"/>
  2784. </Bit>
  2785. <Bit config="6,8">
  2786. <Name>WRP1A_PEND</Name>
  2787. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2788. <BitOffset>0x10</BitOffset>
  2789. <BitWidth>0x7</BitWidth>
  2790. <Access>RW</Access>
  2791. <Equation multiplier="0x1000" offset="0x08000000"/>
  2792. </Bit>
  2793. <Bit config="7,9">
  2794. <Name>WRP1A_PEND</Name>
  2795. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2796. <BitOffset>0x10</BitOffset>
  2797. <BitWidth>0x7</BitWidth>
  2798. <Access>RW</Access>
  2799. <Equation multiplier="0x800" offset="0x08000000"/>
  2800. </Bit>
  2801. </AssignedBits>
  2802. </Field>
  2803. <Field>
  2804. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  2805. <AssignedBits>
  2806. <Bit config="6,8">
  2807. <Name>WRP1B_PSTRT</Name>
  2808. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2809. <BitOffset>0x0</BitOffset>
  2810. <BitWidth>0x7</BitWidth>
  2811. <Access>RW</Access>
  2812. <Equation multiplier="0x1000" offset="0x08000000"/>
  2813. </Bit>
  2814. <Bit config="7,9">
  2815. <Name>WRP1B_PSTRT</Name>
  2816. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2817. <BitOffset>0x0</BitOffset>
  2818. <BitWidth>0x7</BitWidth>
  2819. <Access>RW</Access>
  2820. <Equation multiplier="0x800" offset="0x08000000"/>
  2821. </Bit>
  2822. <Bit config="6,8">
  2823. <Name>WRP1B_PEND</Name>
  2824. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2825. <BitOffset>0x10</BitOffset>
  2826. <BitWidth>0x7</BitWidth>
  2827. <Access>RW</Access>
  2828. <Equation multiplier="0x1000" offset="0x08000000"/>
  2829. </Bit>
  2830. <Bit config="7,9">
  2831. <Name>WRP1B_PEND</Name>
  2832. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2833. <BitOffset>0x10</BitOffset>
  2834. <BitWidth>0x7</BitWidth>
  2835. <Access>RW</Access>
  2836. <Equation multiplier="0x800" offset="0x08000000"/>
  2837. </Bit>
  2838. </AssignedBits>
  2839. </Field>
  2840. </Category>
  2841. <Category>
  2842. <Name>Secure area 2</Name>
  2843. <Field>
  2844. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  2845. <AssignedBits>
  2846. <Bit config="6,8">
  2847. <Name>SECWM2_PSTRT</Name>
  2848. <Description>Start page of second secure area</Description>
  2849. <BitOffset>0x0</BitOffset>
  2850. <BitWidth>0x7</BitWidth>
  2851. <Access>RW</Access>
  2852. <Equation multiplier="0x1000" offset="0x08000000"/>
  2853. </Bit>
  2854. <Bit config="7,9">
  2855. <Name>SECWM2_PSTRT</Name>
  2856. <Description>Start page of second secure area</Description>
  2857. <BitOffset>0x0</BitOffset>
  2858. <BitWidth>0x7</BitWidth>
  2859. <Access>RW</Access>
  2860. <Equation multiplier="0x800" offset="0x08040000"/>
  2861. </Bit>
  2862. <Bit config="6,8">
  2863. <Name>SECWM2_PEND</Name>
  2864. <Description>End page of second secure area</Description>
  2865. <BitOffset>0x10</BitOffset>
  2866. <BitWidth>0x7</BitWidth>
  2867. <Access>RW</Access>
  2868. <Equation multiplier="0x1000" offset="0x08000000"/>
  2869. </Bit>
  2870. <Bit config="7,9">
  2871. <Name>SECWM2_PEND</Name>
  2872. <Description>End page of second secure area</Description>
  2873. <BitOffset>0x10</BitOffset>
  2874. <BitWidth>0x7</BitWidth>
  2875. <Access>RW</Access>
  2876. <Equation multiplier="0x800" offset="0x08040000"/>
  2877. </Bit>
  2878. </AssignedBits>
  2879. </Field>
  2880. </Category>
  2881. <Category>
  2882. <Name>Write Protection 2</Name>
  2883. <Field>
  2884. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2885. <AssignedBits>
  2886. <Bit config="6,8">
  2887. <Name>WRP2A_PSTRT</Name>
  2888. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2889. <BitOffset>0x0</BitOffset>
  2890. <BitWidth>0x7</BitWidth>
  2891. <Access>RW</Access>
  2892. <Equation multiplier="0x1000" offset="0x08000000"/>
  2893. </Bit>
  2894. <Bit config="7,9">
  2895. <Name>WRP2A_PSTRT</Name>
  2896. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2897. <BitOffset>0x0</BitOffset>
  2898. <BitWidth>0x7</BitWidth>
  2899. <Access>RW</Access>
  2900. <Equation multiplier="0x800" offset="0x08040000"/>
  2901. </Bit>
  2902. <Bit config="6,8">
  2903. <Name>WRP2A_PEND</Name>
  2904. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2905. <BitOffset>0x10</BitOffset>
  2906. <BitWidth>0x7</BitWidth>
  2907. <Access>RW</Access>
  2908. <Equation multiplier="0x1000" offset="0x08000000"/>
  2909. </Bit>
  2910. <Bit config="7,9">
  2911. <Name>WRP2A_PEND</Name>
  2912. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2913. <BitOffset>0x10</BitOffset>
  2914. <BitWidth>0x7</BitWidth>
  2915. <Access>RW</Access>
  2916. <Equation multiplier="0x800" offset="0x08040000"/>
  2917. </Bit>
  2918. </AssignedBits>
  2919. </Field>
  2920. <Field>
  2921. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2922. <AssignedBits>
  2923. <Bit config="6,8">
  2924. <Name>WRP2B_PSTRT</Name>
  2925. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2926. <BitOffset>0x0</BitOffset>
  2927. <BitWidth>0x7</BitWidth>
  2928. <Access>RW</Access>
  2929. <Equation multiplier="0x1000" offset="0x08000000"/>
  2930. </Bit>
  2931. <Bit config="7,9">
  2932. <Name>WRP2B_PSTRT</Name>
  2933. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2934. <BitOffset>0x0</BitOffset>
  2935. <BitWidth>0x7</BitWidth>
  2936. <Access>RW</Access>
  2937. <Equation multiplier="0x800" offset="0x08040000"/>
  2938. </Bit>
  2939. <Bit config="6,8">
  2940. <Name>WRP2B_PEND</Name>
  2941. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2942. <BitOffset>0x10</BitOffset>
  2943. <BitWidth>0x7</BitWidth>
  2944. <Access>RW</Access>
  2945. <Equation multiplier="0x1000" offset="0x08000000"/>
  2946. </Bit>
  2947. <Bit config="7,9">
  2948. <Name>WRP2B_PEND</Name>
  2949. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2950. <BitOffset>0x10</BitOffset>
  2951. <BitWidth>0x7</BitWidth>
  2952. <Access>RW</Access>
  2953. <Equation multiplier="0x800" offset="0x08040000"/>
  2954. </Bit>
  2955. </AssignedBits>
  2956. </Field>
  2957. </Category>
  2958. </Bank>
  2959. </Peripheral>
  2960. </Peripherals>
  2961. </Device>
  2962. </Root>