STM32_Prog_DB_0x450.xml 40 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x450</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32H7xx</Name>
  9. <Series>STM32H7</Series>
  10. <Description>ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Security extension available && multi-core-->
  15. <SecurityEx>
  16. <WriteRegister address="0x580244F4" value="0x2"/>
  17. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  18. </SecurityEx>
  19. <MultiCore>
  20. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  21. </MultiCore>
  22. <!--<RomLess>
  23. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  24. </RomLess>-->
  25. </Configuration>
  26. <Configuration number="0x1"> <!-- Security extension not available && multi-core -->
  27. <SecurityEx>
  28. <WriteRegister address="0x580244F4" value="0x2"/>
  29. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  30. </SecurityEx>
  31. <MultiCore>
  32. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  33. </MultiCore>
  34. <!-- <RomLess>
  35. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  36. </RomLess> -->
  37. </Configuration>
  38. <Configuration number="0x2"> <!-- Security extension available && single core -->
  39. <SecurityEx>
  40. <WriteRegister address="0x580244F4" value="0x2"/>
  41. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  42. </SecurityEx>
  43. <MultiCore>
  44. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  45. </MultiCore>
  46. <RomLess>
  47. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  48. </RomLess>
  49. </Configuration>
  50. <Configuration number="0x3"> <!-- Security extension not available && single core -->
  51. <SecurityEx>
  52. <WriteRegister address="0x580244F4" value="0x2"/>
  53. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  54. </SecurityEx>
  55. <MultiCore>
  56. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  57. </MultiCore>
  58. <RomLess>
  59. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x00"/>
  60. </RomLess>
  61. </Configuration>
  62. <!-- ROMLESS Configurations -->
  63. <Configuration number="0x4"> <!-- Security extension available && multi-core-->
  64. <SecurityEx>
  65. <WriteRegister address="0x580244F4" value="0x2"/>
  66. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  67. </SecurityEx>
  68. <MultiCore>
  69. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  70. </MultiCore>
  71. <RomLess>
  72. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  73. </RomLess>
  74. </Configuration>
  75. <Configuration number="0x5"> <!-- Security extension not available && multi-core -->
  76. <SecurityEx>
  77. <WriteRegister address="0x580244F4" value="0x2"/>
  78. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  79. </SecurityEx>
  80. <MultiCore>
  81. <ReadRegister address="0x0" mask="0x0" value="0x4"/>
  82. </MultiCore>
  83. <RomLess>
  84. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  85. </RomLess>
  86. </Configuration>
  87. <Configuration number="0x6"> <!-- Security extension available && single core -->
  88. <SecurityEx>
  89. <WriteRegister address="0x580244F4" value="0x2"/>
  90. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  91. </SecurityEx>
  92. <MultiCore>
  93. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  94. </MultiCore>
  95. <RomLess>
  96. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  97. </RomLess>
  98. </Configuration>
  99. <Configuration number="0x7"> <!-- Security extension not available && single core -->
  100. <RomLess>
  101. <ReadRegister address="0x1FF1E880" mask="0x80" value="0x80"/>
  102. </RomLess>
  103. <SecurityEx>
  104. <WriteRegister address="0x580244F4" value="0x2"/>
  105. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  106. </SecurityEx>
  107. <MultiCore>
  108. <ReadRegister address="0x0" mask="0x0" value="0x3"/>
  109. </MultiCore>
  110. </Configuration>
  111. </Interface>
  112. <!-- Bootloader Interface -->
  113. <Interface name="Bootloader">
  114. <Configuration number="0x0"> <!-- Security extension availabe && multicore--> <!-- dummy always true -->
  115. <Dummy>
  116. <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
  117. </Dummy>
  118. </Configuration>
  119. </Interface>
  120. </Configurations>
  121. <!-- Peripherals -->
  122. <Peripherals>
  123. <!-- Embedded SRAM -->
  124. <Peripheral>
  125. <Name>Embedded SRAM</Name>
  126. <Type>Storage</Type>
  127. <Description/>
  128. <ErasedValue>0x00</ErasedValue>
  129. <Access>RWE</Access>
  130. <!-- 512 KB -->
  131. <Configuration>
  132. <Parameters address="0x24000000" name="SRAM" size="0x80000"/>
  133. <Description/>
  134. <Organization>Single</Organization>
  135. <Bank name="Bank 1">
  136. <Field>
  137. <Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x80000"/>
  138. </Field>
  139. </Bank>
  140. </Configuration>
  141. </Peripheral>
  142. <!-- Embedded Flash -->
  143. <Peripheral>
  144. <Name>Embedded Flash</Name>
  145. <Type>Storage</Type>
  146. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  147. <ErasedValue>0xFF</ErasedValue>
  148. <Access>RWE</Access>
  149. <FlashSize address="0x1FF1E880" default="0x200000"/>
  150. <!-- 2MB Dual Bank -->
  151. <Configuration config="0,1,2,3">
  152. <Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  153. <Description/>
  154. <Organization>Dual</Organization>
  155. <Allignement>0x20</Allignement>
  156. <Bank name="Bank 1">
  157. <Field>
  158. <Parameters address="0x08000000" name="sector0" occurence="0x8" size="0x20000"/>
  159. </Field>
  160. </Bank>
  161. <Bank name="Bank 2">
  162. <Field>
  163. <Parameters address="0x08100000" name="sector8" occurence="0x8" size="0x20000"/>
  164. </Field>
  165. </Bank>
  166. </Configuration>
  167. <!-- RomLess 128KB -->
  168. <Configuration config="4,5,6,7">
  169. <Parameters address="0x08000000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
  170. <Description/>
  171. <Organization>Single</Organization>
  172. <Allignement>0x20</Allignement>
  173. <Bank name="Bank 1">
  174. <Field>
  175. <Parameters address="0x08000000" name="sector0" occurence="0x1" size="0x20000"/>
  176. </Field>
  177. </Bank>
  178. </Configuration>
  179. </Peripheral>
  180. <!-- ITCM Flash -->
  181. <Peripheral>
  182. <Name>ITCM Flash</Name>
  183. <Type>Storage</Type>
  184. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  185. <ErasedValue>0xFF</ErasedValue>
  186. <Access>RWE</Access>
  187. <!-- 2MB Dual Bank -->
  188. <Configuration config="0,1,2,3">
  189. <Parameters address="0x00200000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  190. <Description/>
  191. <Organization>Dual</Organization>
  192. <Allignement>0x20</Allignement>
  193. <Bank name="Bank 1">
  194. <Field>
  195. <Parameters address="0x00200000" name="sector0" occurence="0x8" size="0x20000"/>
  196. </Field>
  197. </Bank>
  198. <Bank name="Bank 2">
  199. <Field>
  200. <Parameters address="0x00300000" name="sector8" occurence="0x8" size="0x20000"/>
  201. </Field>
  202. </Bank>
  203. </Configuration>
  204. <!-- RomLess 128KB -->
  205. <Configuration config="4,5,6,7">
  206. <Parameters address="0x00200000" name="RomLess 128 KB Embedded Flash" size="0x20000"/>
  207. <Description/>
  208. <Organization>Single</Organization>
  209. <Allignement>0x20</Allignement>
  210. <Bank name="Bank 1">
  211. <Field>
  212. <Parameters address="0x00200000" name="sector0" occurence="0x1" size="0x20000"/>
  213. </Field>
  214. </Bank>
  215. </Configuration>
  216. </Peripheral>
  217. <!-- Option Bytes -->
  218. <Peripheral>
  219. <Name>Option Bytes</Name>
  220. <Type>Configuration</Type>
  221. <Description/>
  222. <Access>RW</Access>
  223. <Bank>
  224. <Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
  225. <Category>
  226. <Name>Read Out Protection</Name>
  227. <Field>
  228. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  229. <AssignedBits>
  230. <Bit>
  231. <Name>RDP</Name>
  232. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  233. <BitOffset>0x8</BitOffset>
  234. <BitWidth>0x8</BitWidth>
  235. <Access>R</Access>
  236. <Values>
  237. <Val value="0xAA">Level 0, no protection</Val>
  238. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  239. <Val value="0xCC">Level 2, chip protection</Val>
  240. </Values>
  241. </Bit>
  242. </AssignedBits>
  243. </Field>
  244. <Field>
  245. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  246. <AssignedBits>
  247. <Bit>
  248. <Name>RDP</Name>
  249. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  250. <BitOffset>0x8</BitOffset>
  251. <BitWidth>0x8</BitWidth>
  252. <Access>W</Access>
  253. <Values>
  254. <Val value="0xAA">Level 0, no protection</Val>
  255. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  256. <Val value="0xCC">Level 2, chip protection</Val>
  257. </Values>
  258. </Bit>
  259. </AssignedBits>
  260. </Field>
  261. </Category>
  262. <Category>
  263. <Name>RSS</Name>
  264. <Field>
  265. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  266. <AssignedBits>
  267. <Bit>
  268. <Name>RSS1</Name>
  269. <Description/>
  270. <BitOffset>0x1A</BitOffset>
  271. <BitWidth>0x1</BitWidth>
  272. <Access>R</Access>
  273. <Values>
  274. <Val value="0x0">No SFI process on going</Val>
  275. <Val value="0x1">SFI process started</Val>
  276. </Values>
  277. </Bit>
  278. </AssignedBits>
  279. </Field>
  280. <Field>
  281. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  282. <AssignedBits>
  283. <Bit>
  284. <Name>RSS1</Name>
  285. <Description/>
  286. <BitOffset>0x1A</BitOffset>
  287. <BitWidth>0x1</BitWidth>
  288. <Access>W</Access>
  289. <Values>
  290. <Val value="0x0">No SFI process on going</Val>
  291. <Val value="0x1">SFI process started</Val>
  292. </Values>
  293. </Bit>
  294. </AssignedBits>
  295. </Field>
  296. </Category>
  297. <Category>
  298. <Name>BOR Level</Name>
  299. <Field>
  300. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  301. <AssignedBits>
  302. <Bit>
  303. <Name>BOR_LEV</Name>
  304. <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
  305. <BitOffset>0x2</BitOffset>
  306. <BitWidth>0x2</BitWidth>
  307. <Access>R</Access>
  308. <Values>
  309. <Val value="0x0">reset level is set to VBOR0</Val>
  310. <Val value="0x1">reset level is set to VBOR1</Val>
  311. <Val value="0x2">reset level is set to VBOR2</Val>
  312. <Val value="0x3">reset level is set to VBOR3</Val>
  313. </Values>
  314. </Bit>
  315. </AssignedBits>
  316. </Field>
  317. <Field>
  318. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  319. <AssignedBits>
  320. <Bit>
  321. <Name>BOR_LEV</Name>
  322. <Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
  323. <BitOffset>0x2</BitOffset>
  324. <BitWidth>0x2</BitWidth>
  325. <Access>W</Access>
  326. <Values>
  327. <Val value="0x0">reset level is set to VBOR0</Val>
  328. <Val value="0x1">reset level is set to VBOR1</Val>
  329. <Val value="0x2">reset level is set to VBOR2</Val>
  330. <Val value="0x3">reset level is set to VBOR3</Val>
  331. </Values>
  332. </Bit>
  333. </AssignedBits>
  334. </Field>
  335. </Category>
  336. <Category>
  337. <Name>User Configuration</Name>
  338. <Field>
  339. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  340. <AssignedBits>
  341. <Bit>
  342. <Name>IWDG1_SW</Name>
  343. <Description/>
  344. <BitOffset>0x4</BitOffset>
  345. <BitWidth>0x1</BitWidth>
  346. <Access>R</Access>
  347. <Values>
  348. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  349. <Val value="0x1">Independent watchdog is controlled by software</Val>
  350. </Values>
  351. </Bit>
  352. <Bit config="0,1,4,5">
  353. <Name>IWDG2_SW</Name>
  354. <Description/>
  355. <BitOffset>0x5</BitOffset>
  356. <BitWidth>0x1</BitWidth>
  357. <Access>R</Access>
  358. <Values>
  359. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  360. <Val value="0x1">Independent watchdog is controlled by software</Val>
  361. </Values>
  362. </Bit>
  363. <Bit>
  364. <Name>NRST_STOP_D1</Name>
  365. <Description/>
  366. <BitOffset>0x6</BitOffset>
  367. <BitWidth>0x1</BitWidth>
  368. <Access>R</Access>
  369. <Values>
  370. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  371. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  372. </Values>
  373. </Bit>
  374. <Bit>
  375. <Name>NRST_STBY_D1</Name>
  376. <Description/>
  377. <BitOffset>0x7</BitOffset>
  378. <BitWidth>0x1</BitWidth>
  379. <Access>R</Access>
  380. <Values>
  381. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  382. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  383. </Values>
  384. </Bit>
  385. <Bit>
  386. <Name>FZ_IWDG_STOP</Name>
  387. <Description/>
  388. <BitOffset>0x11</BitOffset>
  389. <BitWidth>0x1</BitWidth>
  390. <Access>R</Access>
  391. <Values>
  392. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  393. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  394. </Values>
  395. </Bit>
  396. <Bit>
  397. <Name>FZ_IWDG_SDBY</Name>
  398. <Description/>
  399. <BitOffset>0x12</BitOffset>
  400. <BitWidth>0x1</BitWidth>
  401. <Access>R</Access>
  402. <Values>
  403. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  404. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  405. </Values>
  406. </Bit>
  407. <Bit config="0,2">
  408. <Name>SECURITY</Name>
  409. <Description/>
  410. <BitOffset>0x15</BitOffset>
  411. <BitWidth>0x1</BitWidth>
  412. <Access>R</Access>
  413. <Values>
  414. <Val value="0x0">Security feature disabled</Val>
  415. <Val value="0x1">Security feature enabled</Val>
  416. </Values>
  417. </Bit>
  418. <Bit config="0,1">
  419. <Name>BCM4</Name>
  420. <Description/>
  421. <BitOffset>0x16</BitOffset>
  422. <BitWidth>0x1</BitWidth>
  423. <Access>R</Access>
  424. <Values>
  425. <Val value="0x0">CM4 boot disabled</Val>
  426. <Val value="0x1">CM4 boot enabled</Val>
  427. </Values>
  428. </Bit>
  429. <Bit>
  430. <Name>BCM7</Name>
  431. <Description/>
  432. <BitOffset>0x17</BitOffset>
  433. <BitWidth>0x1</BitWidth>
  434. <Access>R</Access>
  435. <Values>
  436. <Val value="0x0">CM7 boot disabled</Val>
  437. <Val value="0x1">CM7 boot enabled</Val>
  438. </Values>
  439. </Bit>
  440. <Bit>
  441. <Name>NRST_STOP_D2</Name>
  442. <Description/>
  443. <BitOffset>0x18</BitOffset>
  444. <BitWidth>0x1</BitWidth>
  445. <Access>R</Access>
  446. <Values>
  447. <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
  448. <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
  449. </Values>
  450. </Bit>
  451. <Bit>
  452. <Name>NRST_STBY_D2</Name>
  453. <Description/>
  454. <BitOffset>0x19</BitOffset>
  455. <BitWidth>0x1</BitWidth>
  456. <Access>R</Access>
  457. <Values>
  458. <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
  459. <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
  460. </Values>
  461. </Bit>
  462. <Bit config="0,1,2,3">
  463. <Name>SWAP_BANK</Name>
  464. <Description/>
  465. <BitOffset>0x1F</BitOffset>
  466. <BitWidth>0x1</BitWidth>
  467. <Access>R</Access>
  468. <Values>
  469. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  470. <Val value="0x1">after boot loading, user sectors swapped</Val>
  471. </Values>
  472. </Bit>
  473. <Bit>
  474. <Name>IO_HSLV</Name>
  475. <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
  476. <BitOffset>0x1D</BitOffset>
  477. <BitWidth>0x1</BitWidth>
  478. <Access>R</Access>
  479. <Values>
  480. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  481. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  482. </Values>
  483. </Bit>
  484. </AssignedBits>
  485. </Field>
  486. <Field>
  487. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  488. <AssignedBits>
  489. <Bit>
  490. <Name>IWDG1_SW</Name>
  491. <Description/>
  492. <BitOffset>0x4</BitOffset>
  493. <BitWidth>0x1</BitWidth>
  494. <Access>W</Access>
  495. <Values>
  496. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  497. <Val value="0x1">Independent watchdog is controlled by software</Val>
  498. </Values>
  499. </Bit>
  500. <Bit config="0,1,4,5">
  501. <Name>IWDG2_SW</Name>
  502. <Description/>
  503. <BitOffset>0x5</BitOffset>
  504. <BitWidth>0x1</BitWidth>
  505. <Access>W</Access>
  506. <Values>
  507. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  508. <Val value="0x1">Independent watchdog is controlled by software</Val>
  509. </Values>
  510. </Bit>
  511. <Bit>
  512. <Name>NRST_STOP_D1</Name>
  513. <Description/>
  514. <BitOffset>0x6</BitOffset>
  515. <BitWidth>0x1</BitWidth>
  516. <Access>W</Access>
  517. <Values>
  518. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  519. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  520. </Values>
  521. </Bit>
  522. <Bit>
  523. <Name>NRST_STBY_D1</Name>
  524. <Description/>
  525. <BitOffset>0x7</BitOffset>
  526. <BitWidth>0x1</BitWidth>
  527. <Access>W</Access>
  528. <Values>
  529. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  530. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  531. </Values>
  532. </Bit>
  533. <Bit>
  534. <Name>FZ_IWDG_STOP</Name>
  535. <Description/>
  536. <BitOffset>0x11</BitOffset>
  537. <BitWidth>0x1</BitWidth>
  538. <Access>W</Access>
  539. <Values>
  540. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  541. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  542. </Values>
  543. </Bit>
  544. <Bit>
  545. <Name>FZ_IWDG_SDBY</Name>
  546. <Description/>
  547. <BitOffset>0x12</BitOffset>
  548. <BitWidth>0x1</BitWidth>
  549. <Access>W</Access>
  550. <Values>
  551. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  552. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  553. </Values>
  554. </Bit>
  555. <Bit config="0,2,4,6">
  556. <Name>SECURITY</Name>
  557. <Description/>
  558. <BitOffset>0x15</BitOffset>
  559. <BitWidth>0x1</BitWidth>
  560. <Access>W</Access>
  561. <Values>
  562. <Val value="0x0">Security feature disabled</Val>
  563. <Val value="0x1">Security feature enabled</Val>
  564. </Values>
  565. </Bit>
  566. <Bit>
  567. <Name>IO_HSLV</Name>
  568. <Description> I/O high-speed at low-voltage configuration bit. This bit indicates that the product operates below 2.5 V</Description>
  569. <BitOffset>0x1D</BitOffset>
  570. <BitWidth>0x1</BitWidth>
  571. <Access>W</Access>
  572. <Values>
  573. <Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
  574. <Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  575. </Values>
  576. </Bit>
  577. <Bit config="0,1,4,5">
  578. <Name>BCM4</Name>
  579. <Description/>
  580. <BitOffset>0x16</BitOffset>
  581. <BitWidth>0x1</BitWidth>
  582. <Access>W</Access>
  583. <Values>
  584. <Val value="0x0">CM4 boot disabled</Val>
  585. <Val value="0x1">CM4 boot enabled</Val>
  586. </Values>
  587. </Bit>
  588. <Bit>
  589. <Name>BCM7</Name>
  590. <Description/>
  591. <BitOffset>0x17</BitOffset>
  592. <BitWidth>0x1</BitWidth>
  593. <Access>W</Access>
  594. <Values>
  595. <Val value="0x0">CM7 boot disabled</Val>
  596. <Val value="0x1">CM7 boot enabled</Val>
  597. </Values>
  598. </Bit>
  599. <Bit>
  600. <Name>NRST_STOP_D2</Name>
  601. <Description/>
  602. <BitOffset>0x18</BitOffset>
  603. <BitWidth>0x1</BitWidth>
  604. <Access>W</Access>
  605. <Values>
  606. <Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
  607. <Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
  608. </Values>
  609. </Bit>
  610. <Bit>
  611. <Name>NRST_STBY_D2</Name>
  612. <Description/>
  613. <BitOffset>0x19</BitOffset>
  614. <BitWidth>0x1</BitWidth>
  615. <Access>W</Access>
  616. <Values>
  617. <Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
  618. <Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
  619. </Values>
  620. </Bit>
  621. <Bit config="0,1,2,3">
  622. <Name>SWAP_BANK</Name>
  623. <Description/>
  624. <BitOffset>0x1F</BitOffset>
  625. <BitWidth>0x1</BitWidth>
  626. <Access>W</Access>
  627. <Values>
  628. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  629. <Val value="0x1">after boot loading, user sectors swapped</Val>
  630. </Values>
  631. </Bit>
  632. </AssignedBits>
  633. </Field>
  634. </Category>
  635. <Category>
  636. <Name>Boot address Option Bytes</Name>
  637. <Field>
  638. <Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
  639. <AssignedBits>
  640. <Bit>
  641. <Name>BOOT_CM7_ADD0</Name>
  642. <Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
  643. <BitOffset>0x0</BitOffset>
  644. <BitWidth>0x10</BitWidth>
  645. <Access>R</Access>
  646. <Equation multiplier="0x10000" offset="0x0"/>
  647. </Bit>
  648. <Bit>
  649. <Name>BOOT_CM7_ADD1</Name>
  650. <Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
  651. <BitOffset>0x10</BitOffset>
  652. <BitWidth>0x10</BitWidth>
  653. <Access>R</Access>
  654. <Equation multiplier="0x10000" offset="0x0"/>
  655. </Bit>
  656. </AssignedBits>
  657. </Field>
  658. <Field>
  659. <Parameters address="0x52002048" name="FBOOT4_CUR" size="0x4"/>
  660. <AssignedBits>
  661. <Bit config="0,1,4,5">
  662. <Name>BOOT_CM4_ADD0</Name>
  663. <Description>Define the boot address for Cortex-M4 when BOOT0=0</Description>
  664. <BitOffset>0x0</BitOffset>
  665. <BitWidth>0x10</BitWidth>
  666. <Access>R</Access>
  667. <Equation multiplier="0x10000" offset="0x0"/>
  668. </Bit>
  669. <Bit config="0,1,4,5">
  670. <Name>BOOT_CM4_ADD1</Name>
  671. <Description>Define the boot address for Cortex-M4 when BOOT0=1</Description>
  672. <BitOffset>0x10</BitOffset>
  673. <BitWidth>0x10</BitWidth>
  674. <Access>R</Access>
  675. <Equation multiplier="0x10000" offset="0x0"/>
  676. </Bit>
  677. </AssignedBits>
  678. </Field>
  679. <Field>
  680. <Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
  681. <AssignedBits>
  682. <Bit>
  683. <Name>BOOT_CM7_ADD0</Name>
  684. <Description/>
  685. <BitOffset>0x0</BitOffset>
  686. <BitWidth>0x10</BitWidth>
  687. <Access>W</Access>
  688. <Equation multiplier="0x10000" offset="0x0"/>
  689. </Bit>
  690. <Bit>
  691. <Name>BOOT_CM7_ADD1</Name>
  692. <Description/>
  693. <BitOffset>0x10</BitOffset>
  694. <BitWidth>0x10</BitWidth>
  695. <Access>W</Access>
  696. <Equation multiplier="0x10000" offset="0x0"/>
  697. </Bit>
  698. </AssignedBits>
  699. </Field>
  700. <Field>
  701. <Parameters address="0x5200204C" name="FBOOT4_PRG" size="0x4"/>
  702. <AssignedBits>
  703. <Bit config="0,1,4,5">
  704. <Name>BOOT_CM4_ADD0</Name>
  705. <Description/>
  706. <BitOffset>0x0</BitOffset>
  707. <BitWidth>0x10</BitWidth>
  708. <Access>W</Access>
  709. <Equation multiplier="0x10000" offset="0x0"/>
  710. </Bit>
  711. <Bit config="0,1,4,5">
  712. <Name>BOOT_CM4_ADD1</Name>
  713. <Description/>
  714. <BitOffset>0x10</BitOffset>
  715. <BitWidth>0x10</BitWidth>
  716. <Access>W</Access>
  717. <Equation multiplier="0x10000" offset="0x0"/>
  718. </Bit>
  719. </AssignedBits>
  720. </Field>
  721. </Category>
  722. <Category>
  723. <Name>PCROP Protection</Name>
  724. <Field>
  725. <Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
  726. <AssignedBits>
  727. <Bit>
  728. <Name>PROT_AREA_START1</Name>
  729. <Description>Flash Bank 1 PCROP start address</Description>
  730. <BitOffset>0x0</BitOffset>
  731. <BitWidth>0xC</BitWidth>
  732. <Access>R</Access>
  733. <Equation multiplier="0x100" offset="0x08000000"/>
  734. </Bit>
  735. <Bit>
  736. <Name>PROT_AREA_END1</Name>
  737. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
  738. <BitOffset>0x10</BitOffset>
  739. <BitWidth>0xC</BitWidth>
  740. <Access>R</Access>
  741. <Equation multiplier="0x100" offset="0x080000FF"/>
  742. </Bit>
  743. <Bit>
  744. <Name>DMEP1</Name>
  745. <Description/>
  746. <BitOffset>0x1F</BitOffset>
  747. <BitWidth>0x1</BitWidth>
  748. <Access>R</Access>
  749. <Values>
  750. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  751. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  752. </Values>
  753. </Bit>
  754. </AssignedBits>
  755. </Field>
  756. <Field>
  757. <Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
  758. <AssignedBits>
  759. <Bit>
  760. <Name>PROT_AREA_START1</Name>
  761. <Description>Flash Bank 1 PCROP start address</Description>
  762. <BitOffset>0x0</BitOffset>
  763. <BitWidth>0xC</BitWidth>
  764. <Access>W</Access>
  765. <Equation multiplier="0x100" offset="0x08000000"/>
  766. </Bit>
  767. <Bit>
  768. <Name>PROT_AREA_END1</Name>
  769. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  770. <BitOffset>0x10</BitOffset>
  771. <BitWidth>0xC</BitWidth>
  772. <Access>W</Access>
  773. <Equation multiplier="0x100" offset="0x080000FF"/>
  774. </Bit>
  775. <Bit>
  776. <Name>DMEP1</Name>
  777. <Description/>
  778. <BitOffset>0x1F</BitOffset>
  779. <BitWidth>0x1</BitWidth>
  780. <Access>W</Access>
  781. <Values>
  782. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  783. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  784. </Values>
  785. </Bit>
  786. </AssignedBits>
  787. </Field>
  788. <Field>
  789. <Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
  790. <AssignedBits>
  791. <Bit config="0,1,2,3">
  792. <Name>PROT_AREA_START2</Name>
  793. <Description>Flash Bank 2 PCROP start address</Description>
  794. <BitOffset>0x0</BitOffset>
  795. <BitWidth>0xC</BitWidth>
  796. <Access>R</Access>
  797. <Equation multiplier="0x100" offset="0x08100000"/>
  798. </Bit>
  799. <Bit config="0,1,2,3">
  800. <Name>PROT_AREA_END2</Name>
  801. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  802. <BitOffset>0x10</BitOffset>
  803. <BitWidth>0xC</BitWidth>
  804. <Access>R</Access>
  805. <Equation multiplier="0x100" offset="0x081000FF"/>
  806. </Bit>
  807. <Bit config="0,1,2,3">
  808. <Name>DMEP2</Name>
  809. <Description/>
  810. <BitOffset>0x1F</BitOffset>
  811. <BitWidth>0x1</BitWidth>
  812. <Access>R</Access>
  813. <Values>
  814. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  815. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  816. </Values>
  817. </Bit>
  818. </AssignedBits>
  819. </Field>
  820. <Field>
  821. <Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
  822. <AssignedBits>
  823. <Bit config="0,1,2,3">
  824. <Name>PROT_AREA_START2</Name>
  825. <Description>Flash Bank 2 PCROP start address</Description>
  826. <BitOffset>0x0</BitOffset>
  827. <BitWidth>0xC</BitWidth>
  828. <Access>W</Access>
  829. <Equation multiplier="0x100" offset="0x08100000"/>
  830. </Bit>
  831. <Bit config="0,1,2,3">
  832. <Name>PROT_AREA_END2</Name>
  833. <Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  834. <BitOffset>0x10</BitOffset>
  835. <BitWidth>0xC</BitWidth>
  836. <Access>W</Access>
  837. <Equation multiplier="0x100" offset="0x081000FF"/>
  838. </Bit>
  839. <Bit config="0,1,2,3">
  840. <Name>DMEP2</Name>
  841. <Description/>
  842. <BitOffset>0x1F</BitOffset>
  843. <BitWidth>0x1</BitWidth>
  844. <Access>W</Access>
  845. <Values>
  846. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  847. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  848. </Values>
  849. </Bit>
  850. </AssignedBits>
  851. </Field>
  852. </Category>
  853. <Category>
  854. <Name>Secure Protection</Name>
  855. <Field>
  856. <Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
  857. <AssignedBits>
  858. <Bit config="0,2,4,6">
  859. <Name>SEC_AREA_START1</Name>
  860. <Description>Flash Bank 1 secure area start address</Description>
  861. <BitOffset>0x0</BitOffset>
  862. <BitWidth>0xC</BitWidth>
  863. <Access>R</Access>
  864. <Equation multiplier="0x100" offset="0x08000000"/>
  865. </Bit>
  866. <Bit config="0,2,4,6">
  867. <Name>SEC_AREA_END1</Name>
  868. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  869. <BitOffset>0x10</BitOffset>
  870. <BitWidth>0xC</BitWidth>
  871. <Access>R</Access>
  872. <Equation multiplier="0x100" offset="0x080000FF"/>
  873. </Bit>
  874. <Bit config="0,2,4,6">
  875. <Name>DMES1</Name>
  876. <Description/>
  877. <BitOffset>0x1F</BitOffset>
  878. <BitWidth>0x1</BitWidth>
  879. <Access>R</Access>
  880. <Values>
  881. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  882. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  883. </Values>
  884. </Bit>
  885. </AssignedBits>
  886. </Field>
  887. <Field>
  888. <Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
  889. <AssignedBits>
  890. <Bit config="0,2,4,6">
  891. <Name>SEC_AREA_START1</Name>
  892. <Description>Flash Bank 1 secure area start address</Description>
  893. <BitOffset>0x0</BitOffset>
  894. <BitWidth>0xC</BitWidth>
  895. <Access>W</Access>
  896. <Equation multiplier="0x100" offset="0x08000000"/>
  897. </Bit>
  898. <Bit config="0,2,4,6">
  899. <Name>SEC_AREA_END1</Name>
  900. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  901. <BitOffset>0x10</BitOffset>
  902. <BitWidth>0xC</BitWidth>
  903. <Access>W</Access>
  904. <Equation multiplier="0x100" offset="0x080000FF"/>
  905. </Bit>
  906. <Bit config="0,2,4,6">
  907. <Name>DMES1</Name>
  908. <Description/>
  909. <BitOffset>0x1F</BitOffset>
  910. <BitWidth>0x1</BitWidth>
  911. <Access>W</Access>
  912. <Values>
  913. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  914. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  915. </Values>
  916. </Bit>
  917. </AssignedBits>
  918. </Field>
  919. <Field>
  920. <Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
  921. <AssignedBits>
  922. <Bit config="0,2">
  923. <Name>SEC_AREA_START2</Name>
  924. <Description>Flash Bank 2 secure area start address</Description>
  925. <BitOffset>0x0</BitOffset>
  926. <BitWidth>0xC</BitWidth>
  927. <Access>R</Access>
  928. <Equation multiplier="0x100" offset="0x08100000"/>
  929. </Bit>
  930. <Bit config="0,2">
  931. <Name>SEC_AREA_END2</Name>
  932. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  933. <BitOffset>0x10</BitOffset>
  934. <BitWidth>0xC</BitWidth>
  935. <Access>R</Access>
  936. <Equation multiplier="0x100" offset="0x081000FF"/>
  937. </Bit>
  938. <Bit config="0,2">
  939. <Name>DMES2</Name>
  940. <Description/>
  941. <BitOffset>0x1F</BitOffset>
  942. <BitWidth>0x1</BitWidth>
  943. <Access>R</Access>
  944. <Values>
  945. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  946. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  947. </Values>
  948. </Bit>
  949. </AssignedBits>
  950. </Field>
  951. <Field>
  952. <Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
  953. <AssignedBits>
  954. <Bit config="0,2">
  955. <Name>SEC_AREA_START2</Name>
  956. <Description>Flash Bank 2 secure area start address</Description>
  957. <BitOffset>0x0</BitOffset>
  958. <BitWidth>0xC</BitWidth>
  959. <Access>W</Access>
  960. <Equation multiplier="0x100" offset="0x08100000"/>
  961. </Bit>
  962. <Bit config="0,2">
  963. <Name>SEC_AREA_END2</Name>
  964. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  965. <BitOffset>0x10</BitOffset>
  966. <BitWidth>0xC</BitWidth>
  967. <Access>W</Access>
  968. <Equation multiplier="0x100" offset="0x081000FF"/>
  969. </Bit>
  970. <Bit config="0,2">
  971. <Name>DMES2</Name>
  972. <Description/>
  973. <BitOffset>0x1F</BitOffset>
  974. <BitWidth>0x1</BitWidth>
  975. <Access>W</Access>
  976. <Values>
  977. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  978. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  979. </Values>
  980. </Bit>
  981. </AssignedBits>
  982. </Field>
  983. </Category>
  984. <Category>
  985. <Name>DTCM RAM Protection</Name>
  986. <Field>
  987. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  988. <AssignedBits>
  989. <Bit>
  990. <Name>ST_RAM_SIZE</Name>
  991. <Description/>
  992. <BitOffset>0x13</BitOffset>
  993. <BitWidth>0x2</BitWidth>
  994. <Access>R</Access>
  995. <Values>
  996. <Val value="0x0">2 KB</Val>
  997. <Val value="0x1">4 KB</Val>
  998. <Val value="0x2">8 KB</Val>
  999. <Val value="0x3">16 KB</Val>
  1000. </Values>
  1001. </Bit>
  1002. </AssignedBits>
  1003. </Field>
  1004. <Field>
  1005. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  1006. <AssignedBits>
  1007. <Bit>
  1008. <Name>ST_RAM_SIZE</Name>
  1009. <Description/>
  1010. <BitOffset>0x13</BitOffset>
  1011. <BitWidth>0x2</BitWidth>
  1012. <Access>W</Access>
  1013. <Values>
  1014. <Val value="0x0">2 KB</Val>
  1015. <Val value="0x1">4 KB</Val>
  1016. <Val value="0x2">8 KB</Val>
  1017. <Val value="0x3">16 KB</Val>
  1018. </Values>
  1019. </Bit>
  1020. </AssignedBits>
  1021. </Field>
  1022. </Category>
  1023. <Category>
  1024. <Name>Write Protection</Name>
  1025. <Field>
  1026. <Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
  1027. <AssignedBits>
  1028. <Bit config="0,1,2,3">
  1029. <Name>nWRP0</Name>
  1030. <Description/>
  1031. <BitOffset>0x0</BitOffset>
  1032. <BitWidth>0x8</BitWidth>
  1033. <Access>R</Access>
  1034. <Values ByBit="true">
  1035. <Val value="0x0">Write protection active on this sector</Val>
  1036. <Val value="0x1">Write protection not active on this sector</Val>
  1037. </Values>
  1038. </Bit>
  1039. <Bit config="4,5,6,7">
  1040. <Name>nWRP0</Name>
  1041. <Description/>
  1042. <BitOffset>0x0</BitOffset>
  1043. <BitWidth>0x1</BitWidth>
  1044. <Access>R</Access>
  1045. <Values ByBit="true">
  1046. <Val value="0x0">Write protection active on this sector</Val>
  1047. <Val value="0x1">Write protection not active on this sector</Val>
  1048. </Values>
  1049. </Bit>
  1050. </AssignedBits>
  1051. </Field>
  1052. <Field>
  1053. <Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
  1054. <AssignedBits>
  1055. <Bit config="0,1,2,3">
  1056. <Name>nWRP0</Name>
  1057. <Description/>
  1058. <BitOffset>0x0</BitOffset>
  1059. <BitWidth>0x8</BitWidth>
  1060. <Access>W</Access>
  1061. <Values ByBit="true">
  1062. <Val value="0x0">Write protection active on this sector</Val>
  1063. <Val value="0x1">Write protection not active on this sector</Val>
  1064. </Values>
  1065. </Bit>
  1066. <Bit config="4,5,6,7">
  1067. <Name>nWRP0</Name>
  1068. <Description/>
  1069. <BitOffset>0x0</BitOffset>
  1070. <BitWidth>0x1</BitWidth>
  1071. <Access>W</Access>
  1072. <Values ByBit="true">
  1073. <Val value="0x0">Write protection active on this sector</Val>
  1074. <Val value="0x1">Write protection not active on this sector</Val>
  1075. </Values>
  1076. </Bit>
  1077. </AssignedBits>
  1078. </Field>
  1079. <Field>
  1080. <Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
  1081. <AssignedBits>
  1082. <Bit config="0,1,2,3">
  1083. <Name>nWRP8</Name>
  1084. <Description/>
  1085. <BitOffset>0x0</BitOffset>
  1086. <BitWidth>0x8</BitWidth>
  1087. <Access>R</Access>
  1088. <Values ByBit="true">
  1089. <Val value="0x0">Write protection active on this sector</Val>
  1090. <Val value="0x1">Write protection not active on this sector</Val>
  1091. </Values>
  1092. </Bit>
  1093. </AssignedBits>
  1094. </Field>
  1095. <Field>
  1096. <Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
  1097. <AssignedBits>
  1098. <Bit config="0,1,2,3">
  1099. <Name>nWRP8</Name>
  1100. <Description/>
  1101. <BitOffset>0x0</BitOffset>
  1102. <BitWidth>0x8</BitWidth>
  1103. <Access>W</Access>
  1104. <Values ByBit="true">
  1105. <Val value="0x0">Write protection active on this sector</Val>
  1106. <Val value="0x1">Write protection not active on this sector</Val>
  1107. </Values>
  1108. </Bit>
  1109. </AssignedBits>
  1110. </Field>
  1111. </Category>
  1112. </Bank>
  1113. </Peripheral>
  1114. </Peripherals>
  1115. </Device>
  1116. </Root>