STM32_Prog_DB_0x471.xml 52 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x471</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M4</CPU>
  8. <Name>STM32L4Pxxx/STM32L4Qxxx</Name>
  9. <Series>STM32L4</Series>
  10. <Description>ARM 32-bit Cortex-M4 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0">
  15. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x800"/> </flashSize>
  16. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  17. </Configuration>
  18. <Configuration number="0x1">
  19. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x800"/> </flashSize>
  20. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  21. </Configuration>
  22. <Configuration number="0x2">
  23. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  24. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  25. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  26. </Configuration>
  27. <Configuration number="0x3">
  28. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  29. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  30. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  31. </Configuration>
  32. <Configuration number="0x4">
  33. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  34. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  35. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  36. </Configuration>
  37. <Configuration number="0x5">
  38. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x400"/> </flashSize>
  39. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  40. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  41. </Configuration>
  42. <Configuration number="0x6">
  43. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x200"/> </flashSize>
  44. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  45. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  46. </Configuration>
  47. <Configuration number="0x7">
  48. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x200"/> </flashSize>
  49. <DB1M reference="0x0"> <ReadRegister address="0x40022020" mask="0x200000" value="0x0"/> </DB1M>
  50. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  51. </Configuration>
  52. <Configuration number="0x8">
  53. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x200"/> </flashSize>
  54. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  55. <DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
  56. </Configuration>
  57. <Configuration number="0x9">
  58. <flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0" mask="0xFFFF" value="0x200"/> </flashSize>
  59. <DB1M reference="0x1"> <ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/> </DB1M>
  60. <DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
  61. </Configuration>
  62. <Configuration number="0xA">
  63. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF0000" mask="0xFFFFFFFF" value="0XFFFFFFFF"/> </flashSize>
  64. </Configuration>
  65. </Interface>
  66. <!-- Bootloader Interface -->
  67. <Interface name="Bootloader">
  68. <Configuration number="0x0">
  69. <DBANK reference="0x0"> <ReadRegister address="0x1FF00000" mask="0x400000" value="0x0"/> </DBANK>
  70. </Configuration>
  71. <Configuration number="0x1">
  72. <DBANK reference="0x1"> <ReadRegister address="0x1FF00000" mask="0x400000" value="0x400000"/> </DBANK>
  73. </Configuration>
  74. <Configuration number="0xA">
  75. <dummy> <ReadRegister address="0x1FF00000" mask="0" value="0"/> </dummy>
  76. </Configuration>
  77. </Interface>
  78. </Configurations>
  79. <!-- Peripherals -->
  80. <Peripherals>
  81. <!-- Embedded SRAM -->
  82. <Peripheral>
  83. <Name>Embedded SRAM</Name>
  84. <Type>Storage</Type>
  85. <Description/>
  86. <ErasedValue>0x00</ErasedValue>
  87. <Access>RWE</Access>
  88. <!-- 96 KB -->
  89. <Configuration>
  90. <Parameters address="0x20000000" name="SRAM" size="0x30000"/>
  91. <Description/>
  92. <Organization>Single</Organization>
  93. <Bank name="Bank 1">
  94. <Field>
  95. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x30000"/>
  96. </Field>
  97. </Bank>
  98. </Configuration>
  99. </Peripheral>
  100. <!-- Embedded Flash -->
  101. <Peripheral>
  102. <Name>Embedded Flash</Name>
  103. <Type>Storage</Type>
  104. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  105. <ErasedValue>0xFF</ErasedValue>
  106. <Access>RWE</Access>
  107. <FlashSize address="0x1FFF75E0" default="0x100000"/>
  108. <Configuration config="0,2,3,6,9"> <!-- 2MB Single Bank -->
  109. <Parameters address="0x08000000" name=" 1 Mbyte Embedded Flash" size="0x100000"/>
  110. <Description/>
  111. <Organization>Single</Organization>
  112. <Allignement>0x8</Allignement>
  113. <Bank name="Bank 1">
  114. <Field>
  115. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  116. </Field>
  117. </Bank>
  118. </Configuration>
  119. <Configuration config="1,4,5,7,8"> <!-- 1MB dual Bank -->
  120. <Parameters address="0x08000000" name=" 1 Mbyte Embedded Flash" size="0x100000"/>
  121. <Description/>
  122. <Organization>Dual</Organization>
  123. <Allignement>0x8</Allignement>
  124. <Bank name="Bank 1">
  125. <Field>
  126. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x1000"/>
  127. </Field>
  128. </Bank>
  129. <Bank name="Bank 2">
  130. <Field>
  131. <Parameters address="0x08080000" name="sector128" occurence="0x80" size="0x1000"/>
  132. </Field>
  133. </Bank>
  134. </Configuration>
  135. <Configuration config="2"> <!-- 2MB dual Bank -->
  136. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  137. <Description/>
  138. <Organization>Dual</Organization>
  139. <Allignement>0x8</Allignement>
  140. <Bank name="Bank 1">
  141. <Field>
  142. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x2000"/>
  143. </Field>
  144. </Bank>
  145. <Bank name="Bank 2">
  146. <Field>
  147. <Parameters address="0x08100000" name="sector256" occurence="0x100" size="0x2000"/>
  148. </Field>
  149. </Bank>
  150. </Configuration>
  151. </Peripheral>
  152. <!-- OTP -->
  153. <Peripheral>
  154. <Name>OTP</Name>
  155. <Type>Storage</Type>
  156. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  157. <ErasedValue>0xFF</ErasedValue>
  158. <Access>RW</Access>
  159. <!-- 1 KBytes single bank -->
  160. <Configuration>
  161. <Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
  162. <Description/>
  163. <Organization>Single</Organization>
  164. <Allignement>0x4</Allignement>
  165. <Bank name="OTP">
  166. <Field>
  167. <Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
  168. </Field>
  169. </Bank>
  170. </Configuration>
  171. </Peripheral>
  172. <!-- Mirror Option Bytes -->
  173. <Peripheral>
  174. <Name>MirrorOptionBytes</Name>
  175. <Type>Storage</Type>
  176. <Description>Mirror Option Bytes contains the extra area.</Description>
  177. <ErasedValue>0xFF</ErasedValue>
  178. <Access>RW</Access>
  179. <!-- 64 Bytes Dual bank -->
  180. <Configuration>
  181. <Parameters address="0x1FFF7800" name=" 64 Bytes Data MirrorOptionBytes" size="0x40"/>
  182. <Description/>
  183. <Organization>Dual</Organization>
  184. <Allignement>0x4</Allignement>
  185. <Bank name="Bank 1">
  186. <Field>
  187. <Parameters address="0x1FF00000" name="Bank1" occurence="0x1" size="0x24"/>
  188. </Field>
  189. </Bank>
  190. <Bank name="Bank 2">
  191. <Field>
  192. <Parameters address="0x1FF01008" name="Bank2" occurence="0x1" size="0x1C"/>
  193. </Field>
  194. </Bank>
  195. </Configuration>
  196. </Peripheral>
  197. <!-- Option Bytes -->
  198. <Peripheral>
  199. <Name>Option Bytes</Name>
  200. <Type>Configuration</Type>
  201. <Description/>
  202. <Access>RW</Access>
  203. <Bank interface="JTAG_SWD">
  204. <Parameters address="0x40022020" name="Bank 1" size="0x30"/>
  205. <Category>
  206. <Name>Read Out Protection</Name>
  207. <Field>
  208. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  209. <AssignedBits>
  210. <Bit>
  211. <Name>RDP</Name>
  212. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  213. <BitOffset>0x0</BitOffset>
  214. <BitWidth>0x8</BitWidth>
  215. <Access>RW</Access>
  216. <Values>
  217. <Val value="0xAA">Level 0, no protection</Val>
  218. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  219. <Val value="0xCC">Level 2, chip protection</Val>
  220. </Values>
  221. </Bit>
  222. </AssignedBits>
  223. </Field>
  224. </Category>
  225. <Category>
  226. <Name>BOR Level</Name>
  227. <Field>
  228. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  229. <AssignedBits>
  230. <Bit>
  231. <Name>BOR_LEV</Name>
  232. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  233. <BitOffset>0x8</BitOffset>
  234. <BitWidth>0x3</BitWidth>
  235. <Access>RW</Access>
  236. <Values>
  237. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  238. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  239. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  240. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  241. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  242. </Values>
  243. </Bit>
  244. </AssignedBits>
  245. </Field>
  246. </Category>
  247. <Category>
  248. <Name>User Configuration</Name>
  249. <Field>
  250. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  251. <AssignedBits>
  252. <Bit>
  253. <Name>nRST_STOP</Name>
  254. <Description/>
  255. <BitOffset>0xC</BitOffset>
  256. <BitWidth>0x1</BitWidth>
  257. <Access>RW</Access>
  258. <Values>
  259. <Val value="0x0">Reset generated when entering Stop mode</Val>
  260. <Val value="0x1">No reset generated when entering Stop mode</Val>
  261. </Values>
  262. </Bit>
  263. <Bit>
  264. <Name>nRST_STDBY</Name>
  265. <Description/>
  266. <BitOffset>0xD</BitOffset>
  267. <BitWidth>0x1</BitWidth>
  268. <Access>RW</Access>
  269. <Values>
  270. <Val value="0x0">Reset generated when entering Standby mode</Val>
  271. <Val value="0x1">No reset generated when entering Standby mode</Val>
  272. </Values>
  273. </Bit>
  274. <Bit>
  275. <Name>nRST_SHDW</Name>
  276. <Description/>
  277. <BitOffset>0xE</BitOffset>
  278. <BitWidth>0x1</BitWidth>
  279. <Access>RW</Access>
  280. <Values>
  281. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  282. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  283. </Values>
  284. </Bit>
  285. <Bit>
  286. <Name>IWDG_SW</Name>
  287. <Description/>
  288. <BitOffset>0x10</BitOffset>
  289. <BitWidth>0x1</BitWidth>
  290. <Access>RW</Access>
  291. <Values>
  292. <Val value="0x0">Hardware independant watchdog</Val>
  293. <Val value="0x1">Software independant watchdog</Val>
  294. </Values>
  295. </Bit>
  296. <Bit>
  297. <Name>IWDG_STOP</Name>
  298. <Description/>
  299. <BitOffset>0x11</BitOffset>
  300. <BitWidth>0x1</BitWidth>
  301. <Access>RW</Access>
  302. <Values>
  303. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  304. <Val value="0x1">IWDG counter active in stop mode</Val>
  305. </Values>
  306. </Bit>
  307. <Bit>
  308. <Name>IWDG_STDBY</Name>
  309. <Description/>
  310. <BitOffset>0x12</BitOffset>
  311. <BitWidth>0x1</BitWidth>
  312. <Access>RW</Access>
  313. <Values>
  314. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  315. <Val value="0x1">IWDG counter active in standby mode</Val>
  316. </Values>
  317. </Bit>
  318. <Bit>
  319. <Name>WWDG_SW</Name>
  320. <Description/>
  321. <BitOffset>0x13</BitOffset>
  322. <BitWidth>0x1</BitWidth>
  323. <Access>RW</Access>
  324. <Values>
  325. <Val value="0x0">Hardware window watchdog</Val>
  326. <Val value="0x1">Software window watchdog</Val>
  327. </Values>
  328. </Bit>
  329. <Bit>
  330. <Name>BFB2</Name>
  331. <Description/>
  332. <BitOffset>0x14</BitOffset>
  333. <BitWidth>0x1</BitWidth>
  334. <Access>RW</Access>
  335. <Values>
  336. <Val value="0x0">Dual-bank boot disable</Val>
  337. <Val value="0x1">Dual-bank boot enable</Val>
  338. </Values>
  339. </Bit>
  340. <Bit config="2,3,4,5,6,7,8,9,10">
  341. <Name>DB1M</Name>
  342. <Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
  343. <BitOffset>0x15</BitOffset>
  344. <BitWidth>0x1</BitWidth>
  345. <Access>RW</Access>
  346. <Values>
  347. <Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
  348. <Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
  349. </Values>
  350. </Bit>
  351. <Bit>
  352. <Name>DBANK</Name>
  353. <Description>This bit can only be written when PCROPA/B is disabled</Description>
  354. <BitOffset>0x16</BitOffset>
  355. <BitWidth>0x1</BitWidth>
  356. <Access>RW</Access>
  357. <Values>
  358. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  359. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  360. </Values>
  361. </Bit>
  362. <Bit>
  363. <Name>nBOOT1</Name>
  364. <Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory.</Description>
  365. <BitOffset>0x17</BitOffset>
  366. <BitWidth>0x1</BitWidth>
  367. <Access>RW</Access>
  368. <Values>
  369. <Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
  370. <Val value="0x1">Boot from system memory when BOOT0=1</Val>
  371. </Values>
  372. </Bit>
  373. <Bit>
  374. <Name>SRAM2_PE</Name>
  375. <Description>SRAM2 parity check enable</Description>
  376. <BitOffset>0x18</BitOffset>
  377. <BitWidth>0x1</BitWidth>
  378. <Access>RW</Access>
  379. <Values>
  380. <Val value="0x0">SRAM2 parity check enable</Val>
  381. <Val value="0x1">SRAM2 parity check disable</Val>
  382. </Values>
  383. </Bit>
  384. <Bit>
  385. <Name>SRAM2_RST</Name>
  386. <Description>SRAM2 Erase when system reset</Description>
  387. <BitOffset>0x19</BitOffset>
  388. <BitWidth>0x1</BitWidth>
  389. <Access>RW</Access>
  390. <Values>
  391. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  392. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  393. </Values>
  394. </Bit>
  395. <Bit>
  396. <Name>nSWBOOT0</Name>
  397. <Description>Software BOOT0</Description>
  398. <BitOffset>0x1A</BitOffset>
  399. <BitWidth>0x1</BitWidth>
  400. <Access>RW</Access>
  401. <Values>
  402. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  403. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  404. </Values>
  405. </Bit>
  406. <Bit>
  407. <Name>nBOOT0</Name>
  408. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  409. <BitOffset>0x1B</BitOffset>
  410. <BitWidth>0x1</BitWidth>
  411. <Access>RW</Access>
  412. <Values>
  413. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  414. <Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
  415. </Values>
  416. </Bit>
  417. </AssignedBits>
  418. </Field>
  419. </Category>
  420. <Category>
  421. <Name>PCROP Protection (Bank 1)</Name>
  422. <Field>
  423. <Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
  424. <AssignedBits>
  425. <Bit config="0,2,3,6,9,10">
  426. <Name>PCROP1_STRT</Name>
  427. <Description>Flash Bank 1 PCROP start address</Description>
  428. <BitOffset>0x0</BitOffset>
  429. <BitWidth>0x10</BitWidth>
  430. <Access>RW</Access>
  431. <Equation multiplier="0x10" offset="0x08000000"/>
  432. </Bit>
  433. <Bit config="1,4,5,7,8">
  434. <Name>PCROP1_STRT</Name>
  435. <Description>Flash Bank 1 PCROP start address</Description>
  436. <BitOffset>0x0</BitOffset>
  437. <BitWidth>0x10</BitWidth>
  438. <Access>RW</Access>
  439. <Equation multiplier="0x8" offset="0x08000000"/>
  440. </Bit>
  441. </AssignedBits>
  442. </Field>
  443. <Field>
  444. <Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
  445. <AssignedBits>
  446. <Bit config="0,2,3,6,9,10">
  447. <Name>PCROP1_END</Name>
  448. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  449. <BitOffset>0x0</BitOffset>
  450. <BitWidth>0x10</BitWidth>
  451. <Access>RW</Access>
  452. <Equation multiplier="0x10" offset="0x08000000"/>
  453. </Bit>
  454. <Bit config="1,4,5,7,8">
  455. <Name>PCROP1_END</Name>
  456. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  457. <BitOffset>0x0</BitOffset>
  458. <BitWidth>0x10</BitWidth>
  459. <Access>RW</Access>
  460. <Equation multiplier="0x8" offset="0x08000000"/>
  461. </Bit>
  462. <Bit>
  463. <Name>PCROP_RDP</Name>
  464. <Description/>
  465. <BitOffset>0x1F</BitOffset>
  466. <BitWidth>0x1</BitWidth>
  467. <Access>RW</Access>
  468. <Values>
  469. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  470. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  471. </Values>
  472. </Bit>
  473. </AssignedBits>
  474. </Field>
  475. </Category>
  476. <Category>
  477. <Name>Write Protection (Bank 1)</Name>
  478. <Field>
  479. <Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
  480. <AssignedBits>
  481. <Bit config="0,2,3,6,9,10">
  482. <Name>WRP1A_STRT</Name>
  483. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  484. <BitOffset>0x0</BitOffset>
  485. <BitWidth>0x7</BitWidth>
  486. <Access>RW</Access>
  487. <Equation multiplier="0x2000" offset="0x08000000"/>
  488. </Bit>
  489. <Bit config="1,4,5,7,8">
  490. <Name>WRP1A_STRT</Name>
  491. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  492. <BitOffset>0x0</BitOffset>
  493. <BitWidth>0x7</BitWidth>
  494. <Access>RW</Access>
  495. <Equation multiplier="0x1000" offset="0x08000000"/>
  496. </Bit>
  497. <Bit config="0,2,3,6,9,10">
  498. <Name>WRP1A_END</Name>
  499. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  500. <BitOffset>0x10</BitOffset>
  501. <BitWidth>0x7</BitWidth>
  502. <Access>RW</Access>
  503. <Equation multiplier="0x2000" offset="0x08000000"/>
  504. </Bit>
  505. <Bit config="1,4,5,7,8">
  506. <Name>WRP1A_END</Name>
  507. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  508. <BitOffset>0x10</BitOffset>
  509. <BitWidth>0x7</BitWidth>
  510. <Access>RW</Access>
  511. <Equation multiplier="0x1000" offset="0x08000000"/>
  512. </Bit>
  513. </AssignedBits>
  514. </Field>
  515. <Field>
  516. <Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
  517. <AssignedBits>
  518. <Bit config="0,2,3,6,9,10">
  519. <Name>WRP1B_STRT</Name>
  520. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  521. <BitOffset>0x0</BitOffset>
  522. <BitWidth>0x7</BitWidth>
  523. <Access>RW</Access>
  524. <Equation multiplier="0x2000" offset="0x08000000"/>
  525. </Bit>
  526. <Bit config="1,4,5,7,8">
  527. <Name>WRP1B_STRT</Name>
  528. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  529. <BitOffset>0x0</BitOffset>
  530. <BitWidth>0x7</BitWidth>
  531. <Access>RW</Access>
  532. <Equation multiplier="0x1000" offset="0x08000000"/>
  533. </Bit>
  534. <Bit config="0,2,3,6,9,10">
  535. <Name>WRP1B_END</Name>
  536. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  537. <BitOffset>0x10</BitOffset>
  538. <BitWidth>0x7</BitWidth>
  539. <Access>RW</Access>
  540. <Equation multiplier="0x2000" offset="0x08000000"/>
  541. </Bit>
  542. <Bit config="1,4,5,7,8">
  543. <Name>WRP1B_END</Name>
  544. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  545. <BitOffset>0x10</BitOffset>
  546. <BitWidth>0x7</BitWidth>
  547. <Access>RW</Access>
  548. <Equation multiplier="0x1000" offset="0x08000000"/>
  549. </Bit>
  550. </AssignedBits>
  551. </Field>
  552. </Category>
  553. </Bank>
  554. <Bank interface="JTAG_SWD">
  555. <Parameters address="0x40022030" name="Bank 2" size="0x24"/>
  556. <Category>
  557. <Name>PCROP Protection (Bank 2)</Name>
  558. <Field>
  559. <Parameters address="0x40022044" name="FLASH_PCROP2SR" size="0x4"/>
  560. <AssignedBits>
  561. <Bit config="0,10"> <!-- 2M whith offset 1M></!-->
  562. <Name>PCROP2_STRT</Name>
  563. <Description>Flash Bank 2 PCROP start address</Description>
  564. <BitOffset>0x0</BitOffset>
  565. <BitWidth>0x11</BitWidth>
  566. <Access>RW</Access>
  567. <Equation multiplier="0x16" offset="0x08100000"/>
  568. </Bit>
  569. <Bit config="2,3"> <!-- 1M whith offset 512K></!-->
  570. <Name>PCROP2_STRT</Name>
  571. <Description>Flash Bank 2 PCROP start address</Description>
  572. <BitOffset>0x0</BitOffset>
  573. <BitWidth>0x10</BitWidth>
  574. <Access>RW</Access>
  575. <Equation multiplier="0x10" offset="0x08000000"/>
  576. </Bit>
  577. <Bit config="6,9"> <!-- 512K whith offset 256K></!-->
  578. <Name>PCROP2_STRT</Name>
  579. <Description>Flash Bank 2 PCROP start address</Description>
  580. <BitOffset>0x0</BitOffset>
  581. <BitWidth>0x11</BitWidth>
  582. <Access>RW</Access>
  583. <Equation multiplier="0x16" offset="0x08040000"/>
  584. </Bit>
  585. <Bit config="1">
  586. <Name>PCROP2_STRT</Name>
  587. <Description>Flash Bank 2 PCROP start address</Description>
  588. <BitOffset>0x0</BitOffset>
  589. <BitWidth>0x11</BitWidth>
  590. <Access>RW</Access>
  591. <Equation multiplier="0x8" offset="0x08100000"/>
  592. </Bit>
  593. <Bit config="4,5">
  594. <Name>PCROP2_STRT</Name>
  595. <Description>Flash Bank 2 PCROP start address</Description>
  596. <BitOffset>0x0</BitOffset>
  597. <BitWidth>0x10</BitWidth>
  598. <Access>RW</Access>
  599. <Equation multiplier="0x8" offset="0x08080000"/>
  600. </Bit>
  601. <Bit config="7,8">
  602. <Name>PCROP2_STRT</Name>
  603. <Description>Flash Bank 2 PCROP start address</Description>
  604. <BitOffset>0x0</BitOffset>
  605. <BitWidth>0x11</BitWidth>
  606. <Access>RW</Access>
  607. <Equation multiplier="0x8" offset="0x08040000"/>
  608. </Bit>
  609. </AssignedBits>
  610. </Field>
  611. <Field>
  612. <Parameters address="0x40022048" name="FLASH_PCROP2ER" size="0x4"/>
  613. <AssignedBits>
  614. <Bit config="0,10">
  615. <Name>PCROP2_END</Name>
  616. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  617. <BitOffset>0x0</BitOffset>
  618. <BitWidth>0x11</BitWidth>
  619. <Access>RW</Access>
  620. <Equation multiplier="0x16" offset="0x08100000"/>
  621. </Bit>
  622. <Bit config="2,3">
  623. <Name>PCROP2_END</Name>
  624. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  625. <BitOffset>0x0</BitOffset>
  626. <BitWidth>0x10</BitWidth>
  627. <Access>RW</Access>
  628. <Equation multiplier="0x10" offset="0x08000000"/>
  629. </Bit>
  630. <Bit config="6,9">
  631. <Name>PCROP2_END</Name>
  632. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  633. <BitOffset>0x0</BitOffset>
  634. <BitWidth>0x11</BitWidth>
  635. <Access>RW</Access>
  636. <Equation multiplier="0x16" offset="0x08040000"/>
  637. </Bit>
  638. <Bit config="1">
  639. <Name>PCROP2_END</Name>
  640. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  641. <BitOffset>0x0</BitOffset>
  642. <BitWidth>0x11</BitWidth>
  643. <Access>RW</Access>
  644. <Equation multiplier="0x8" offset="0x08100000"/>
  645. </Bit>
  646. <Bit config="4,5">
  647. <Name>PCROP2_END</Name>
  648. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  649. <BitOffset>0x0</BitOffset>
  650. <BitWidth>0x10</BitWidth>
  651. <Access>RW</Access>
  652. <Equation multiplier="0x8" offset="0x08080000"/>
  653. </Bit>
  654. <Bit config="7,8">
  655. <Name>PCROP2_END</Name>
  656. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  657. <BitOffset>0x0</BitOffset>
  658. <BitWidth>0x11</BitWidth>
  659. <Access>RW</Access>
  660. <Equation multiplier="0x8" offset="0x08040000"/>
  661. </Bit>
  662. </AssignedBits>
  663. </Field>
  664. </Category>
  665. <Category>
  666. <Name>Write Protection (Bank 2)</Name>
  667. <Field>
  668. <Parameters address="0x4002204C" name="FLASH_WRP2AR" size="0x4"/>
  669. <AssignedBits>
  670. <Bit config="0,10">
  671. <Name>WRP2A_STRT</Name>
  672. <Description>The address of first page of the Bank 2 WRP first area</Description>
  673. <BitOffset>0x0</BitOffset>
  674. <BitWidth>0x7</BitWidth>
  675. <Access>RW</Access>
  676. <Equation multiplier="0x2000" offset="0x08100000"/>
  677. </Bit>
  678. <Bit config="2,3">
  679. <Name>WRP2A_STRT</Name>
  680. <Description>The address of first page of the Bank 2 WRP first area</Description>
  681. <BitOffset>0x0</BitOffset>
  682. <BitWidth>0x7</BitWidth>
  683. <Access>RW</Access>
  684. <Equation multiplier="0x2000" offset="0x08000000"/>
  685. </Bit>
  686. <Bit config="6,9">
  687. <Name>WRP2A_STRT</Name>
  688. <Description>The address of first page of the Bank 2 WRP first area</Description>
  689. <BitOffset>0x0</BitOffset>
  690. <BitWidth>0x7</BitWidth>
  691. <Access>RW</Access>
  692. <Equation multiplier="0x2000" offset="0x08040000"/>
  693. </Bit>
  694. <Bit config="1">
  695. <Name>WRP2A_STRT</Name>
  696. <Description>The address of first page of the Bank 2 WRP first area</Description>
  697. <BitOffset>0x0</BitOffset>
  698. <BitWidth>0x7</BitWidth>
  699. <Access>RW</Access>
  700. <Equation multiplier="0x1000" offset="0x08100000"/>
  701. </Bit>
  702. <Bit config="4,5">
  703. <Name>WRP2A_STRT</Name>
  704. <Description>The address of first page of the Bank 2 WRP first area</Description>
  705. <BitOffset>0x0</BitOffset>
  706. <BitWidth>0x7</BitWidth>
  707. <Access>RW</Access>
  708. <Equation multiplier="0x1000" offset="0x08080000"/>
  709. </Bit>
  710. <Bit config="7,8">
  711. <Name>WRP2A_STRT</Name>
  712. <Description>The address of first page of the Bank 2 WRP first area</Description>
  713. <BitOffset>0x0</BitOffset>
  714. <BitWidth>0x7</BitWidth>
  715. <Access>RW</Access>
  716. <Equation multiplier="0x1000" offset="0x08040000"/>
  717. </Bit>
  718. <Bit config="0,10">
  719. <Name>WRP2A_END</Name>
  720. <Description>The address of last page of the Bank 2 WRP first area</Description>
  721. <BitOffset>0x10</BitOffset>
  722. <BitWidth>0x7</BitWidth>
  723. <Access>RW</Access>
  724. <Equation multiplier="0x2000" offset="0x08100000"/>
  725. </Bit>
  726. <Bit config="2,3">
  727. <Name>WRP2A_END</Name>
  728. <Description>The address of last page of the Bank 2 WRP first area</Description>
  729. <BitOffset>0x10</BitOffset>
  730. <BitWidth>0x7</BitWidth>
  731. <Access>RW</Access>
  732. <Equation multiplier="0x2000" offset="0x08000000"/>
  733. </Bit>
  734. <Bit config="6,9">
  735. <Name>WRP2A_END</Name>
  736. <Description>The address of last page of the Bank 2 WRP first area</Description>
  737. <BitOffset>0x10</BitOffset>
  738. <BitWidth>0x7</BitWidth>
  739. <Access>RW</Access>
  740. <Equation multiplier="0x2000" offset="0x08040000"/>
  741. </Bit>
  742. <Bit config="1">
  743. <Name>WRP2A_END</Name>
  744. <Description>The address of last page of the Bank 2 WRP first area</Description>
  745. <BitOffset>0x10</BitOffset>
  746. <BitWidth>0x7</BitWidth>
  747. <Access>RW</Access>
  748. <Equation multiplier="0x1000" offset="0x08100000"/>
  749. </Bit>
  750. <Bit config="4,5">
  751. <Name>WRP2A_END</Name>
  752. <Description>The address of last page of the Bank 2 WRP first area</Description>
  753. <BitOffset>0x10</BitOffset>
  754. <BitWidth>0x7</BitWidth>
  755. <Access>RW</Access>
  756. <Equation multiplier="0x1000" offset="0x08080000"/>
  757. </Bit>
  758. <Bit config="7,8">
  759. <Name>WRP2A_END</Name>
  760. <Description>The address of last page of the Bank 2 WRP first area</Description>
  761. <BitOffset>0x10</BitOffset>
  762. <BitWidth>0x7</BitWidth>
  763. <Access>RW</Access>
  764. <Equation multiplier="0x1000" offset="0x08040000"/>
  765. </Bit>
  766. </AssignedBits>
  767. </Field>
  768. <Field>
  769. <Parameters address="0x40022050" name="FLASH_WRP2BR" size="0x4"/>
  770. <AssignedBits>
  771. <Bit config="0,10">
  772. <Name>WRP2B_STRT</Name>
  773. <Description>The address of first page of the Bank 2 WRP second area</Description>
  774. <BitOffset>0x0</BitOffset>
  775. <BitWidth>0x7</BitWidth>
  776. <Access>RW</Access>
  777. <Equation multiplier="0x2000" offset="0x08100000"/>
  778. </Bit>
  779. <Bit config="2,3">
  780. <Name>WRP2B_STRT</Name>
  781. <Description>The address of first page of the Bank 2 WRP second area</Description>
  782. <BitOffset>0x0</BitOffset>
  783. <BitWidth>0x7</BitWidth>
  784. <Access>RW</Access>
  785. <Equation multiplier="0x2000" offset="0x08000000"/>
  786. </Bit>
  787. <Bit config="6,9">
  788. <Name>WRP2B_STRT</Name>
  789. <Description>The address of first page of the Bank 2 WRP second area</Description>
  790. <BitOffset>0x0</BitOffset>
  791. <BitWidth>0x7</BitWidth>
  792. <Access>RW</Access>
  793. <Equation multiplier="0x2000" offset="0x08040000"/>
  794. </Bit>
  795. <Bit config="1">
  796. <Name>WRP2B_STRT</Name>
  797. <Description>The address of first page of the Bank 2 WRP second area</Description>
  798. <BitOffset>0x0</BitOffset>
  799. <BitWidth>0x7</BitWidth>
  800. <Access>RW</Access>
  801. <Equation multiplier="0x1000" offset="0x08100000"/>
  802. </Bit>
  803. <Bit config="4,5">
  804. <Name>WRP2B_STRT</Name>
  805. <Description>The address of first page of the Bank 2 WRP second area</Description>
  806. <BitOffset>0x0</BitOffset>
  807. <BitWidth>0x7</BitWidth>
  808. <Access>RW</Access>
  809. <Equation multiplier="0x1000" offset="0x08080000"/>
  810. </Bit>
  811. <Bit config="7,8">
  812. <Name>WRP2B_STRT</Name>
  813. <Description>The address of first page of the Bank 2 WRP second area</Description>
  814. <BitOffset>0x0</BitOffset>
  815. <BitWidth>0x7</BitWidth>
  816. <Access>RW</Access>
  817. <Equation multiplier="0x1000" offset="0x08040000"/>
  818. </Bit>
  819. <Bit config="0,10">
  820. <Name>WRP2B_END</Name>
  821. <Description>The address of last page of the Bank 2 WRP second area</Description>
  822. <BitOffset>0x10</BitOffset>
  823. <BitWidth>0x7</BitWidth>
  824. <Access>RW</Access>
  825. <Equation multiplier="0x2000" offset="0x08100000"/>
  826. </Bit>
  827. <Bit config="2,3">
  828. <Name>WRP2B_END</Name>
  829. <Description>The address of last page of the Bank 2 WRP second area</Description>
  830. <BitOffset>0x10</BitOffset>
  831. <BitWidth>0x7</BitWidth>
  832. <Access>RW</Access>
  833. <Equation multiplier="0x2000" offset="0x08000000"/>
  834. </Bit>
  835. <Bit config="6,9">
  836. <Name>WRP2B_END</Name>
  837. <Description>The address of last page of the Bank 2 WRP second area</Description>
  838. <BitOffset>0x10</BitOffset>
  839. <BitWidth>0x7</BitWidth>
  840. <Access>RW</Access>
  841. <Equation multiplier="0x2000" offset="0x08040000"/>
  842. </Bit>
  843. <Bit config="1">
  844. <Name>WRP2B_END</Name>
  845. <Description>The address of last page of the Bank 2 WRP second area</Description>
  846. <BitOffset>0x10</BitOffset>
  847. <BitWidth>0x7</BitWidth>
  848. <Access>RW</Access>
  849. <Equation multiplier="0x1000" offset="0x08100000"/>
  850. </Bit>
  851. <Bit config="4,5">
  852. <Name>WRP2B_END</Name>
  853. <Description>The address of last page of the Bank 2 WRP second area</Description>
  854. <BitOffset>0x10</BitOffset>
  855. <BitWidth>0x7</BitWidth>
  856. <Access>RW</Access>
  857. <Equation multiplier="0x1000" offset="0x08080000"/>
  858. </Bit>
  859. <Bit config="7,8">
  860. <Name>WRP2B_END</Name>
  861. <Description>The address of last page of the Bank 2 WRP second area</Description>
  862. <BitOffset>0x10</BitOffset>
  863. <BitWidth>0x7</BitWidth>
  864. <Access>RW</Access>
  865. <Equation multiplier="0x1000" offset="0x08040000"/>
  866. </Bit>
  867. </AssignedBits>
  868. </Field>
  869. </Category>
  870. </Bank>
  871. <Bank interface="Bootloader">
  872. <Parameters address="0x1FF00000" name="Bank 1" size="0x24"/>
  873. <Category>
  874. <Name>Read Out Protection</Name>
  875. <Field>
  876. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  877. <AssignedBits>
  878. <Bit>
  879. <Name>RDP</Name>
  880. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  881. <BitOffset>0x0</BitOffset>
  882. <BitWidth>0x8</BitWidth>
  883. <Access>RW</Access>
  884. <Values>
  885. <Val value="0xAA">Level 0, no protection</Val>
  886. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  887. <Val value="0xCC">Level 2, chip protection</Val>
  888. </Values>
  889. </Bit>
  890. </AssignedBits>
  891. </Field>
  892. </Category>
  893. <Category>
  894. <Name>BOR Level</Name>
  895. <Field>
  896. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  897. <AssignedBits>
  898. <Bit>
  899. <Name>BOR_LEV</Name>
  900. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  901. <BitOffset>0x8</BitOffset>
  902. <BitWidth>0x3</BitWidth>
  903. <Access>RW</Access>
  904. <Values>
  905. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  906. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  907. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  908. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  909. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  910. </Values>
  911. </Bit>
  912. </AssignedBits>
  913. </Field>
  914. </Category>
  915. <Category>
  916. <Name>User Configuration</Name>
  917. <Field>
  918. <Parameters address="0x1FF00000" name="FLASH_OPTR" size="0x4"/>
  919. <AssignedBits>
  920. <Bit>
  921. <Name>nRST_STOP</Name>
  922. <Description/>
  923. <BitOffset>0xC</BitOffset>
  924. <BitWidth>0x1</BitWidth>
  925. <Access>RW</Access>
  926. <Values>
  927. <Val value="0x0">Reset generated when entering Stop mode</Val>
  928. <Val value="0x1">No reset generated</Val>
  929. </Values>
  930. </Bit>
  931. <Bit>
  932. <Name>nRST_STDBY</Name>
  933. <Description/>
  934. <BitOffset>0xD</BitOffset>
  935. <BitWidth>0x1</BitWidth>
  936. <Access>RW</Access>
  937. <Values>
  938. <Val value="0x0">Reset generated when entering Standby mode</Val>
  939. <Val value="0x1">No reset generated</Val>
  940. </Values>
  941. </Bit>
  942. <Bit>
  943. <Name>nRST_SHDW</Name>
  944. <Description/>
  945. <BitOffset>0xE</BitOffset>
  946. <BitWidth>0x1</BitWidth>
  947. <Access>RW</Access>
  948. <Values>
  949. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  950. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  951. </Values>
  952. </Bit>
  953. <Bit>
  954. <Name>IWDG_SW</Name>
  955. <Description/>
  956. <BitOffset>0x10</BitOffset>
  957. <BitWidth>0x1</BitWidth>
  958. <Access>RW</Access>
  959. <Values>
  960. <Val value="0x0">Hardware independant watchdog</Val>
  961. <Val value="0x1">Software independant watchdog</Val>
  962. </Values>
  963. </Bit>
  964. <Bit>
  965. <Name>IWDG_STOP</Name>
  966. <Description/>
  967. <BitOffset>0x11</BitOffset>
  968. <BitWidth>0x1</BitWidth>
  969. <Access>RW</Access>
  970. <Values>
  971. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  972. <Val value="0x1">IWDG counter active in stop mode</Val>
  973. </Values>
  974. </Bit>
  975. <Bit>
  976. <Name>IWDG_STDBY</Name>
  977. <Description/>
  978. <BitOffset>0x12</BitOffset>
  979. <BitWidth>0x1</BitWidth>
  980. <Access>RW</Access>
  981. <Values>
  982. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  983. <Val value="0x1">IWDG counter active in standby mode</Val>
  984. </Values>
  985. </Bit>
  986. <Bit>
  987. <Name>WWDG_SW</Name>
  988. <Description/>
  989. <BitOffset>0x13</BitOffset>
  990. <BitWidth>0x1</BitWidth>
  991. <Access>RW</Access>
  992. <Values>
  993. <Val value="0x0">Hardware window watchdog</Val>
  994. <Val value="0x1">Software window watchdog</Val>
  995. </Values>
  996. </Bit>
  997. <Bit>
  998. <Name>BFB2</Name>
  999. <Description/>
  1000. <BitOffset>0x14</BitOffset>
  1001. <BitWidth>0x1</BitWidth>
  1002. <Access>RW</Access>
  1003. <Values>
  1004. <Val value="0x0">Dual-bank boot disable</Val>
  1005. <Val value="0x1">Dual-bank boot enable</Val>
  1006. </Values>
  1007. </Bit>
  1008. <Bit config="10">
  1009. <Name>DB1M</Name>
  1010. <Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
  1011. <BitOffset>0x15</BitOffset>
  1012. <BitWidth>0x1</BitWidth>
  1013. <Access>RW</Access>
  1014. <Values>
  1015. <Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
  1016. <Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
  1017. </Values>
  1018. </Bit>
  1019. <Bit>
  1020. <Name>DBANK</Name>
  1021. <Description>This bit can only be written when PCROPA/B is disabled.</Description>
  1022. <BitOffset>0x16</BitOffset>
  1023. <BitWidth>0x1</BitWidth>
  1024. <Access>RW</Access>
  1025. <Values>
  1026. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1027. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1028. </Values>
  1029. </Bit>
  1030. <Bit>
  1031. <Name>nBOOT1</Name>
  1032. <Description/>
  1033. <BitOffset>0x17</BitOffset>
  1034. <BitWidth>0x1</BitWidth>
  1035. <Access>RW</Access>
  1036. <Values>
  1037. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  1038. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  1039. </Values>
  1040. </Bit>
  1041. <Bit>
  1042. <Name>SRAM2_PE</Name>
  1043. <Description/>
  1044. <BitOffset>0x18</BitOffset>
  1045. <BitWidth>0x1</BitWidth>
  1046. <Access>RW</Access>
  1047. <Values>
  1048. <Val value="0x0">SRAM2 parity check enable</Val>
  1049. <Val value="0x1">SRAM2 parity check disable</Val>
  1050. </Values>
  1051. </Bit>
  1052. <Bit>
  1053. <Name>SRAM2_RST</Name>
  1054. <Description/>
  1055. <BitOffset>0x19</BitOffset>
  1056. <BitWidth>0x1</BitWidth>
  1057. <Access>RW</Access>
  1058. <Values>
  1059. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1060. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1061. </Values>
  1062. </Bit>
  1063. <Bit>
  1064. <Name>nSWBOOT0</Name>
  1065. <Description>Software BOOT0</Description>
  1066. <BitOffset>0x1A</BitOffset>
  1067. <BitWidth>0x1</BitWidth>
  1068. <Access>RW</Access>
  1069. <Values>
  1070. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1071. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1072. </Values>
  1073. </Bit>
  1074. <Bit>
  1075. <Name>nBOOT0</Name>
  1076. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  1077. <BitOffset>0x1B</BitOffset>
  1078. <BitWidth>0x1</BitWidth>
  1079. <Access>RW</Access>
  1080. <Values>
  1081. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  1082. <Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
  1083. </Values>
  1084. </Bit>
  1085. </AssignedBits>
  1086. </Field>
  1087. </Category>
  1088. <Category>
  1089. <Name>PCROP Protection (Bank 1)</Name>
  1090. <Field>
  1091. <Parameters address="0x1FF00008" name="FLASH_PCROP1SR" size="0x4"/>
  1092. <AssignedBits>
  1093. <Bit config="0,10">
  1094. <Name>PCROP1_STRT</Name>
  1095. <Description>Flash Bank 1 PCROP start address</Description>
  1096. <BitOffset>0x0</BitOffset>
  1097. <BitWidth>0x10</BitWidth>
  1098. <Access>RW</Access>
  1099. <Equation multiplier="0x10" offset="0x08000000"/>
  1100. </Bit>
  1101. <Bit config="1">
  1102. <Name>PCROP1_STRT</Name>
  1103. <Description>Flash Bank 1 PCROP start address</Description>
  1104. <BitOffset>0x0</BitOffset>
  1105. <BitWidth>0x10</BitWidth>
  1106. <Access>RW</Access>
  1107. <Equation multiplier="0x8" offset="0x08000000"/>
  1108. </Bit>
  1109. </AssignedBits>
  1110. </Field>
  1111. <Field>
  1112. <Parameters address="0x1FF00010" name="FLASH_PCROP1ER" size="0x4"/>
  1113. <AssignedBits>
  1114. <Bit config="0,10">
  1115. <Name>PCROP1_END</Name>
  1116. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1117. <BitOffset>0x0</BitOffset>
  1118. <BitWidth>0x10</BitWidth>
  1119. <Access>RW</Access>
  1120. <Equation multiplier="0x10" offset="0x08000000"/>
  1121. </Bit>
  1122. <Bit config="1">
  1123. <Name>PCROP1_END</Name>
  1124. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1125. <BitOffset>0x0</BitOffset>
  1126. <BitWidth>0x10</BitWidth>
  1127. <Access>RW</Access>
  1128. <Equation multiplier="0x8" offset="0x08000000"/>
  1129. </Bit>
  1130. <Bit>
  1131. <Name>PCROP_RDP</Name>
  1132. <Description/>
  1133. <BitOffset>0x1F</BitOffset>
  1134. <BitWidth>0x1</BitWidth>
  1135. <Access>RW</Access>
  1136. <Values>
  1137. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  1138. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  1139. </Values>
  1140. </Bit>
  1141. </AssignedBits>
  1142. </Field>
  1143. </Category>
  1144. <Category>
  1145. <Name>Write Protection (Bank 1)</Name>
  1146. <Field>
  1147. <Parameters address="0x1FF00018" name="FLASH_WRP1AR" size="0x4"/>
  1148. <AssignedBits>
  1149. <Bit config="0,10">
  1150. <Name>WRP1A_STRT</Name>
  1151. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  1152. <BitOffset>0x0</BitOffset>
  1153. <BitWidth>0x7</BitWidth>
  1154. <Access>RW</Access>
  1155. <Equation multiplier="0x2000" offset="0x08000000"/>
  1156. </Bit>
  1157. <Bit config="1">
  1158. <Name>WRP1A_STRT</Name>
  1159. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  1160. <BitOffset>0x0</BitOffset>
  1161. <BitWidth>0x7</BitWidth>
  1162. <Access>RW</Access>
  1163. <Equation multiplier="0x1000" offset="0x08000000"/>
  1164. </Bit>
  1165. <Bit config="0,10">
  1166. <Name>WRP1A_END</Name>
  1167. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  1168. <BitOffset>0x10</BitOffset>
  1169. <BitWidth>0x7</BitWidth>
  1170. <Access>RW</Access>
  1171. <Equation multiplier="0x2000" offset="0x08000000"/>
  1172. </Bit>
  1173. <Bit config="1">
  1174. <Name>WRP1A_END</Name>
  1175. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  1176. <BitOffset>0x10</BitOffset>
  1177. <BitWidth>0x7</BitWidth>
  1178. <Access>RW</Access>
  1179. <Equation multiplier="0x1000" offset="0x08000000"/>
  1180. </Bit>
  1181. </AssignedBits>
  1182. </Field>
  1183. <Field>
  1184. <Parameters address="0x1FF00020" name="FLASH_WRP1BR" size="0x4"/>
  1185. <AssignedBits>
  1186. <Bit config="0,10">
  1187. <Name>WRP1B_STRT</Name>
  1188. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  1189. <BitOffset>0x0</BitOffset>
  1190. <BitWidth>0x7</BitWidth>
  1191. <Access>RW</Access>
  1192. <Equation multiplier="0x2000" offset="0x08000000"/>
  1193. </Bit>
  1194. <Bit config="1">
  1195. <Name>WRP1B_STRT</Name>
  1196. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  1197. <BitOffset>0x0</BitOffset>
  1198. <BitWidth>0x7</BitWidth>
  1199. <Access>RW</Access>
  1200. <Equation multiplier="0x1000" offset="0x08000000"/>
  1201. </Bit>
  1202. <Bit config="0,10">
  1203. <Name>WRP1B_END</Name>
  1204. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  1205. <BitOffset>0x10</BitOffset>
  1206. <BitWidth>0x7</BitWidth>
  1207. <Access>RW</Access>
  1208. <Equation multiplier="0x2000" offset="0x08000000"/>
  1209. </Bit>
  1210. <Bit config="1">
  1211. <Name>WRP1B_END</Name>
  1212. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  1213. <BitOffset>0x10</BitOffset>
  1214. <BitWidth>0x7</BitWidth>
  1215. <Access>RW</Access>
  1216. <Equation multiplier="0x1000" offset="0x08000000"/>
  1217. </Bit>
  1218. </AssignedBits>
  1219. </Field>
  1220. </Category>
  1221. </Bank>
  1222. <Bank interface="Bootloader">
  1223. <Parameters address="0x1FF01000" name="Bank 2" size="0x24"/>
  1224. <Category>
  1225. <Name>PCROP Protection (Bank 2)</Name>
  1226. <Field>
  1227. <Parameters address="0x1FF01008" name="FLASH_PCROP2SR" size="0x4"/>
  1228. <AssignedBits>
  1229. <Bit config="0,10">
  1230. <Name>PCROP2_STRT</Name>
  1231. <Description>Flash Bank 2 PCROP start address</Description>
  1232. <BitOffset>0x0</BitOffset>
  1233. <BitWidth>0x10</BitWidth>
  1234. <Access>RW</Access>
  1235. <Equation multiplier="0x10" offset="0x08000000"/>
  1236. </Bit>
  1237. <Bit config="1">
  1238. <Name>PCROP2_STRT</Name>
  1239. <Description>Flash Bank 2 PCROP start address</Description>
  1240. <BitOffset>0x0</BitOffset>
  1241. <BitWidth>0x10</BitWidth>
  1242. <Access>RW</Access>
  1243. <Equation multiplier="0x8" offset="0x08080000"/>
  1244. </Bit>
  1245. </AssignedBits>
  1246. </Field>
  1247. <Field>
  1248. <Parameters address="0x1FF01010" name="FLASH_PCROP2ER" size="0x4"/>
  1249. <AssignedBits>
  1250. <Bit config="0,10">
  1251. <Name>PCROP2_END</Name>
  1252. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1253. <BitOffset>0x0</BitOffset>
  1254. <BitWidth>0x10</BitWidth>
  1255. <Access>RW</Access>
  1256. <Equation multiplier="0x10" offset="0x08000000"/>
  1257. </Bit>
  1258. <Bit config="1">
  1259. <Name>PCROP2_END</Name>
  1260. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  1261. <BitOffset>0x0</BitOffset>
  1262. <BitWidth>0x10</BitWidth>
  1263. <Access>RW</Access>
  1264. <Equation multiplier="0x8" offset="0x08080000"/>
  1265. </Bit>
  1266. </AssignedBits>
  1267. </Field>
  1268. </Category>
  1269. <Category>
  1270. <Name>Write Protection (Bank 2)</Name>
  1271. <Field>
  1272. <Parameters address="0x1FF01018" name="FLASH_WRP2AR" size="0x4"/>
  1273. <AssignedBits>
  1274. <Bit config="0,10">
  1275. <Name>WRP2A_STRT</Name>
  1276. <Description>The address of first page of the Bank 2 WRP first area</Description>
  1277. <BitOffset>0x0</BitOffset>
  1278. <BitWidth>0x7</BitWidth>
  1279. <Access>RW</Access>
  1280. <Equation multiplier="0x2000" offset="0x08000000"/>
  1281. </Bit>
  1282. <Bit config="1">
  1283. <Name>WRP2A_STRT</Name>
  1284. <Description>The address of first page of the Bank 2 WRP first area</Description>
  1285. <BitOffset>0x0</BitOffset>
  1286. <BitWidth>0x7</BitWidth>
  1287. <Access>RW</Access>
  1288. <Equation multiplier="0x1000" offset="0x08080000"/>
  1289. </Bit>
  1290. <Bit config="0,10">
  1291. <Name>WRP2A_END</Name>
  1292. <Description>The address of last page of the Bank 2 WRP first area</Description>
  1293. <BitOffset>0x10</BitOffset>
  1294. <BitWidth>0x7</BitWidth>
  1295. <Access>RW</Access>
  1296. <Equation multiplier="0x2000" offset="0x08000000"/>
  1297. </Bit>
  1298. <Bit config="1">
  1299. <Name>WRP2A_END</Name>
  1300. <Description>The address of last page of the Bank 2 WRP first area</Description>
  1301. <BitOffset>0x10</BitOffset>
  1302. <BitWidth>0x7</BitWidth>
  1303. <Access>RW</Access>
  1304. <Equation multiplier="0x1000" offset="0x08080000"/>
  1305. </Bit>
  1306. </AssignedBits>
  1307. </Field>
  1308. <Field>
  1309. <Parameters address="0x1FF01020" name="FLASH_WRP2BR" size="0x4"/>
  1310. <AssignedBits>
  1311. <Bit config="0,10">
  1312. <Name>WRP2B_STRT</Name>
  1313. <Description>The address of first page of the Bank 2 WRP second area</Description>
  1314. <BitOffset>0x0</BitOffset>
  1315. <BitWidth>0x7</BitWidth>
  1316. <Access>RW</Access>
  1317. <Equation multiplier="0x2000" offset="0x08000000"/>
  1318. </Bit>
  1319. <Bit config="1">
  1320. <Name>WRP2B_STRT</Name>
  1321. <Description>The address of first page of the Bank 2 WRP second area</Description>
  1322. <BitOffset>0x0</BitOffset>
  1323. <BitWidth>0x7</BitWidth>
  1324. <Access>RW</Access>
  1325. <Equation multiplier="0x1000" offset="0x08080000"/>
  1326. </Bit>
  1327. <Bit config="0,10">
  1328. <Name>WRP2B_END</Name>
  1329. <Description>The address of last page of the Bank 2 WRP second area</Description>
  1330. <BitOffset>0x10</BitOffset>
  1331. <BitWidth>0x7</BitWidth>
  1332. <Access>RW</Access>
  1333. <Equation multiplier="0x2000" offset="0x08000000"/>
  1334. </Bit>
  1335. <Bit config="1">
  1336. <Name>WRP2B_END</Name>
  1337. <Description>The address of last page of the Bank 2 WRP second area</Description>
  1338. <BitOffset>0x10</BitOffset>
  1339. <BitWidth>0x7</BitWidth>
  1340. <Access>RW</Access>
  1341. <Equation multiplier="0x1000" offset="0x08080000"/>
  1342. </Bit>
  1343. </AssignedBits>
  1344. </Field>
  1345. </Category>
  1346. </Bank>
  1347. </Peripheral>
  1348. </Peripherals>
  1349. </Device>
  1350. </Root>