STM32_Prog_DB_0x480.xml 31 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x480</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32H7A/B</Name>
  9. <Series>STM32H7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0xA">
  15. <SecurityEx>
  16. <WriteRegister address="0x580244F4" value="0x2"/>
  17. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  18. <ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
  19. </SecurityEx>
  20. </Configuration>
  21. <Configuration number="0xB">
  22. <SecurityEx>
  23. <WriteRegister address="0x580244F4" value="0x2"/>
  24. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  25. <ReadRegister address="0x08fff80c" mask="0x00000FFF" value="0x400"/>
  26. </SecurityEx>
  27. </Configuration>
  28. <Configuration number="0x0"> <!-- Security extension available -->
  29. <SecurityEx>
  30. <WriteRegister address="0x580244F4" value="0x2"/>
  31. <ReadRegister address="0x58000528" mask="0x1" value="0x0"/>
  32. </SecurityEx>
  33. </Configuration>
  34. <Configuration number="0x1"> <!-- Security extension not available -->
  35. <SecurityEx>
  36. <WriteRegister address="0x580244F4" value="0x2"/>
  37. <ReadRegister address="0x58000528" mask="0x1" value="0x1"/>
  38. </SecurityEx>
  39. </Configuration>
  40. </Interface>
  41. <!-- Bootloader Interface -->
  42. <Interface name="Bootloader">
  43. <Configuration number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
  44. <Dummy>
  45. <ReadRegister address="0x08000000" mask="0x0" value="0x0"/>
  46. </Dummy>
  47. </Configuration>
  48. </Interface>
  49. </Configurations>
  50. <!-- Peripherals -->
  51. <Peripherals>
  52. <!-- Embedded SRAM -->
  53. <Peripheral>
  54. <Name>Embedded SRAM</Name>
  55. <Type>Storage</Type>
  56. <Description/>
  57. <ErasedValue>0x00</ErasedValue>
  58. <Access>RWE</Access>
  59. <!-- 1024 KB -->
  60. <Configuration>
  61. <Parameters address="0x24000000" name="SRAM" size="0x100000"/>
  62. <Description/>
  63. <Organization>Single</Organization>
  64. <Bank name="Bank 1">
  65. <Field>
  66. <Parameters address="0x24000000" name="SRAM" occurence="0x1" size="0x100000"/>
  67. </Field>
  68. </Bank>
  69. </Configuration>
  70. </Peripheral>
  71. <!-- Embedded Flash -->
  72. <Peripheral>
  73. <Name>Embedded Flash</Name>
  74. <Type>Storage</Type>
  75. <Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  76. <ErasedValue>0xFF</ErasedValue>
  77. <Access>RWE</Access>
  78. <FlashSize address="0x08fff80c" default="0x200000"/>
  79. <!-- 2MB Dual Bank -->
  80. <Configuration config="0,1">
  81. <Parameters address="0x08000000" name="2 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  82. <Description/>
  83. <Organization>Dual</Organization>
  84. <Allignement>0x20</Allignement>
  85. <Bank name="Bank 1">
  86. <Field>
  87. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  88. </Field>
  89. </Bank>
  90. <Bank name="Bank 2">
  91. <Field>
  92. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  93. </Field>
  94. </Bank>
  95. </Configuration>
  96. <!-- 1MB Dual Bank -->
  97. <Configuration config="10,11">
  98. <Parameters address="0x08000000" name="1 MBytes Dual Bank Embedded Flash" size="0x200000"/>
  99. <Description/>
  100. <Organization>Dual</Organization>
  101. <Allignement>0x20</Allignement>
  102. <Bank name="Bank 1">
  103. <Field>
  104. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  105. </Field>
  106. </Bank>
  107. <Bank name="Bank 2">
  108. <Field>
  109. <Parameters address="0x08080000" name="sector64" occurence="0x80" size="0x2000"/>
  110. </Field>
  111. </Bank>
  112. </Configuration>
  113. </Peripheral>
  114. <!-- OTP -->
  115. <Peripheral>
  116. <Name>OTP</Name>
  117. <Type>Storage</Type>
  118. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  119. <ErasedValue>0xFF</ErasedValue>
  120. <Access>RW</Access>
  121. <!-- 1 KBytes single bank -->
  122. <Configuration>
  123. <Parameters address="0x08FFF000" name=" 1 KBytes Data OTP" size="0x400"/>
  124. <Description/>
  125. <Organization>Single</Organization>
  126. <Allignement>0x20</Allignement>
  127. <Bank name="OTP">
  128. <Field>
  129. <Parameters address="0x08FFF000" name="OTP" occurence="0x1" size="0x400"/>
  130. </Field>
  131. </Bank>
  132. </Configuration>
  133. </Peripheral>
  134. <!-- Option Bytes -->
  135. <Peripheral>
  136. <Name>Option Bytes</Name>
  137. <Type>Configuration</Type>
  138. <Description/>
  139. <Access>RW</Access>
  140. <Bank>
  141. <Parameters address="0x5200201C" name="Bank 1" size="0x134"/>
  142. <Category>
  143. <Name>Read Out Protection</Name>
  144. <Field>
  145. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  146. <AssignedBits>
  147. <Bit>
  148. <Name>RDP</Name>
  149. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  150. <BitOffset>0x8</BitOffset>
  151. <BitWidth>0x8</BitWidth>
  152. <Access>R</Access>
  153. <Values>
  154. <Val value="0xAA">Level 0, no protection</Val>
  155. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  156. <Val value="0xCC">Level 2, chip protection</Val>
  157. </Values>
  158. </Bit>
  159. </AssignedBits>
  160. </Field>
  161. <Field>
  162. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  163. <AssignedBits>
  164. <Bit>
  165. <Name>RDP</Name>
  166. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  167. <BitOffset>0x8</BitOffset>
  168. <BitWidth>0x8</BitWidth>
  169. <Access>W</Access>
  170. <Values>
  171. <Val value="0xAA">Level 0, no protection</Val>
  172. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  173. <Val value="0xCC">Level 2, chip protection</Val>
  174. </Values>
  175. </Bit>
  176. </AssignedBits>
  177. </Field>
  178. </Category>
  179. <Category>
  180. <Name>BOR Level</Name>
  181. <Field>
  182. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  183. <AssignedBits>
  184. <Bit>
  185. <Name>BOR_LEV</Name>
  186. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  187. <BitOffset>0x2</BitOffset>
  188. <BitWidth>0x2</BitWidth>
  189. <Access>R</Access>
  190. <Values>
  191. <Val value="0x0">reset level OFF</Val>
  192. <Val value="0x1">reset level is set to 2.1 V</Val>
  193. <Val value="0x2">reset level is set to 2.4 V</Val>
  194. <Val value="0x3">reset level is set to 2.7 V</Val>
  195. </Values>
  196. </Bit>
  197. </AssignedBits>
  198. </Field>
  199. <Field>
  200. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  201. <AssignedBits>
  202. <Bit>
  203. <Name>BOR_LEV</Name>
  204. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  205. <BitOffset>0x2</BitOffset>
  206. <BitWidth>0x2</BitWidth>
  207. <Access>W</Access>
  208. <Values>
  209. <Val value="0x0">reset level OFF</Val>
  210. <Val value="0x1">reset level is set to 2.1 V</Val>
  211. <Val value="0x2">reset level is set to 2.4 V</Val>
  212. <Val value="0x3">reset level is set to 2.7 V</Val>
  213. </Values>
  214. </Bit>
  215. </AssignedBits>
  216. </Field>
  217. </Category>
  218. <Category>
  219. <Name>User Configuration</Name>
  220. <Field>
  221. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  222. <AssignedBits>
  223. <Bit>
  224. <Name>IWDG1_SW</Name>
  225. <Description/>
  226. <BitOffset>0x4</BitOffset>
  227. <BitWidth>0x1</BitWidth>
  228. <Access>R</Access>
  229. <Values>
  230. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  231. <Val value="0x1">Independent watchdog is controlled by software</Val>
  232. </Values>
  233. </Bit>
  234. <Bit>
  235. <Name>NRST_STOP</Name>
  236. <Description/>
  237. <BitOffset>0x6</BitOffset>
  238. <BitWidth>0x1</BitWidth>
  239. <Access>R</Access>
  240. <Values>
  241. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  242. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  243. </Values>
  244. </Bit>
  245. <Bit>
  246. <Name>NRST_STBY</Name>
  247. <Description/>
  248. <BitOffset>0x7</BitOffset>
  249. <BitWidth>0x1</BitWidth>
  250. <Access>R</Access>
  251. <Values>
  252. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  253. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  254. </Values>
  255. </Bit>
  256. <Bit>
  257. <Name>VDDMMC_HSLV</Name>
  258. <Description/>
  259. <BitOffset>0x10</BitOffset>
  260. <BitWidth>0x1</BitWidth>
  261. <Access>R</Access>
  262. <Values>
  263. <Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
  264. <Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  265. </Values>
  266. </Bit>
  267. <Bit>
  268. <Name>IWDG_FZ_STOP</Name>
  269. <Description/>
  270. <BitOffset>0x11</BitOffset>
  271. <BitWidth>0x1</BitWidth>
  272. <Access>R</Access>
  273. <Values>
  274. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  275. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  276. </Values>
  277. </Bit>
  278. <Bit>
  279. <Name>IWDG_FZ_SDBY</Name>
  280. <Description/>
  281. <BitOffset>0x12</BitOffset>
  282. <BitWidth>0x1</BitWidth>
  283. <Access>R</Access>
  284. <Values>
  285. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  286. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  287. </Values>
  288. </Bit>
  289. <Bit config="0,10">
  290. <Name>SECURITY</Name>
  291. <Description/>
  292. <BitOffset>0x15</BitOffset>
  293. <BitWidth>0x1</BitWidth>
  294. <Access>R</Access>
  295. <Values>
  296. <Val value="0x0">Security feature disabled</Val>
  297. <Val value="0x1">Security feature enabled</Val>
  298. </Values>
  299. </Bit>
  300. <Bit>
  301. <Name>VDDIO_HSLV</Name>
  302. <Description/>
  303. <BitOffset>0x1D</BitOffset>
  304. <BitWidth>0x1</BitWidth>
  305. <Access>R</Access>
  306. <Values>
  307. <Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
  308. <Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
  309. </Values>
  310. </Bit>
  311. <Bit>
  312. <Name>SWAP_BANK_OPT</Name>
  313. <Description/>
  314. <BitOffset>0x1F</BitOffset>
  315. <BitWidth>0x1</BitWidth>
  316. <Access>R</Access>
  317. <Values>
  318. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  319. <Val value="0x1">after boot loading, user sectors swapped</Val>
  320. </Values>
  321. </Bit>
  322. </AssignedBits>
  323. </Field>
  324. <Field>
  325. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  326. <AssignedBits>
  327. <Bit>
  328. <Name>IWDG1_SW</Name>
  329. <Description/>
  330. <BitOffset>0x4</BitOffset>
  331. <BitWidth>0x1</BitWidth>
  332. <Access>W</Access>
  333. <Values>
  334. <Val value="0x0">Independent watchdog is controlled by hardware</Val>
  335. <Val value="0x1">Independent watchdog is controlled by software</Val>
  336. </Values>
  337. </Bit>
  338. <Bit>
  339. <Name>NRST_STOP</Name>
  340. <Description/>
  341. <BitOffset>0x6</BitOffset>
  342. <BitWidth>0x1</BitWidth>
  343. <Access>W</Access>
  344. <Values>
  345. <Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
  346. <Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
  347. </Values>
  348. </Bit>
  349. <Bit>
  350. <Name>NRST_STBY</Name>
  351. <Description/>
  352. <BitOffset>0x7</BitOffset>
  353. <BitWidth>0x1</BitWidth>
  354. <Access>W</Access>
  355. <Values>
  356. <Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
  357. <Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
  358. </Values>
  359. </Bit>
  360. <Bit>
  361. <Name>VDDMMC_HSLV</Name>
  362. <Description/>
  363. <BitOffset>0x10</BitOffset>
  364. <BitWidth>0x1</BitWidth>
  365. <Access>W</Access>
  366. <Values>
  367. <Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
  368. <Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
  369. </Values>
  370. </Bit>
  371. <Bit>
  372. <Name>IWDG_FZ_STOP</Name>
  373. <Description/>
  374. <BitOffset>0x11</BitOffset>
  375. <BitWidth>0x1</BitWidth>
  376. <Access>W</Access>
  377. <Values>
  378. <Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
  379. <Val value="0x1">Independent watchdog is running in STOP mode</Val>
  380. </Values>
  381. </Bit>
  382. <Bit>
  383. <Name>IWDG_FZ_SDBY</Name>
  384. <Description/>
  385. <BitOffset>0x12</BitOffset>
  386. <BitWidth>0x1</BitWidth>
  387. <Access>W</Access>
  388. <Values>
  389. <Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
  390. <Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
  391. </Values>
  392. </Bit>
  393. <Bit config="0,10">
  394. <Name>SECURITY</Name>
  395. <Description/>
  396. <BitOffset>0x15</BitOffset>
  397. <BitWidth>0x1</BitWidth>
  398. <Access>W</Access>
  399. <Values>
  400. <Val value="0x0">Security feature disabled</Val>
  401. <Val value="0x1">Security feature enabled</Val>
  402. </Values>
  403. </Bit>
  404. <Bit>
  405. <Name>VDDIO_HSLV</Name>
  406. <Description/>
  407. <BitOffset>0x1D</BitOffset>
  408. <BitWidth>0x1</BitWidth>
  409. <Access>W</Access>
  410. <Values>
  411. <Val value="0x0">Product working in the full voltage range,I/O speed optimization at low-voltage disabled</Val>
  412. <Val value="0x1">VDD I/O below 2.5 V,I/O speed optimization at low-voltage feature allowed</Val>
  413. </Values>
  414. </Bit>
  415. <Bit>
  416. <Name>SWAP_BANK_OPT</Name>
  417. <Description/>
  418. <BitOffset>0x1F</BitOffset>
  419. <BitWidth>0x1</BitWidth>
  420. <Access>W</Access>
  421. <Values>
  422. <Val value="0x0">after boot loading, no swap for user sectors</Val>
  423. <Val value="0x1">after boot loading, user sectors swapped</Val>
  424. </Values>
  425. </Bit>
  426. </AssignedBits>
  427. </Field>
  428. </Category>
  429. <Category>
  430. <Name>Boot address Option Bytes</Name>
  431. <Field>
  432. <Parameters address="0x52002040" name="FBOOT7_CUR" size="0x4"/>
  433. <AssignedBits>
  434. <Bit>
  435. <Name>BOOT_CM7_ADD0</Name>
  436. <Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
  437. <BitOffset>0x0</BitOffset>
  438. <BitWidth>0x10</BitWidth>
  439. <Access>R</Access>
  440. <Equation multiplier="0x10000" offset="0x0"/>
  441. </Bit>
  442. <Bit>
  443. <Name>BOOT_CM7_ADD1</Name>
  444. <Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
  445. <BitOffset>0x10</BitOffset>
  446. <BitWidth>0x10</BitWidth>
  447. <Access>R</Access>
  448. <Equation multiplier="0x10000" offset="0x0"/>
  449. </Bit>
  450. </AssignedBits>
  451. </Field>
  452. <Field>
  453. <Parameters address="0x52002044" name="FBOOT7_PRG" size="0x4"/>
  454. <AssignedBits>
  455. <Bit>
  456. <Name>BOOT_CM7_ADD0</Name>
  457. <Description/>
  458. <BitOffset>0x0</BitOffset>
  459. <BitWidth>0x10</BitWidth>
  460. <Access>W</Access>
  461. <Equation multiplier="0x10000" offset="0x0"/>
  462. </Bit>
  463. <Bit>
  464. <Name>BOOT_CM7_ADD1</Name>
  465. <Description/>
  466. <BitOffset>0x10</BitOffset>
  467. <BitWidth>0x10</BitWidth>
  468. <Access>W</Access>
  469. <Equation multiplier="0x10000" offset="0x0"/>
  470. </Bit>
  471. </AssignedBits>
  472. </Field>
  473. </Category>
  474. <Category>
  475. <Name>PCROP Protection</Name>
  476. <Field>
  477. <Parameters address="0x52002028" name="FPRAR_CUR_A" size="0x4"/>
  478. <AssignedBits>
  479. <Bit>
  480. <Name>PROT_AREA_START1</Name>
  481. <Description>Flash Bank 1 PCROP start address</Description>
  482. <BitOffset>0x0</BitOffset>
  483. <BitWidth>0xC</BitWidth>
  484. <Access>R</Access>
  485. <Equation multiplier="0x100" offset="0x08000000"/>
  486. </Bit>
  487. <Bit>
  488. <Name>PROT_AREA_END1</Name>
  489. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
  490. <BitOffset>0x10</BitOffset>
  491. <BitWidth>0xC</BitWidth>
  492. <Access>R</Access>
  493. <Equation multiplier="0x100" offset="0x080000FF"/>
  494. </Bit>
  495. <Bit>
  496. <Name>DMEP1</Name>
  497. <Description/>
  498. <BitOffset>0x1F</BitOffset>
  499. <BitWidth>0x1</BitWidth>
  500. <Access>R</Access>
  501. <Values>
  502. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  503. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  504. </Values>
  505. </Bit>
  506. </AssignedBits>
  507. </Field>
  508. <Field>
  509. <Parameters address="0x5200202C" name="FPRAR_PRG_A" size="0x4"/>
  510. <AssignedBits>
  511. <Bit>
  512. <Name>PROT_AREA_START1</Name>
  513. <Description>Flash Bank 1 PCROP start address</Description>
  514. <BitOffset>0x0</BitOffset>
  515. <BitWidth>0xC</BitWidth>
  516. <Access>W</Access>
  517. <Equation multiplier="0x100" offset="0x08000000"/>
  518. </Bit>
  519. <Bit>
  520. <Name>PROT_AREA_END1</Name>
  521. <Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  522. <BitOffset>0x10</BitOffset>
  523. <BitWidth>0xC</BitWidth>
  524. <Access>W</Access>
  525. <Equation multiplier="0x100" offset="0x080000FF"/>
  526. </Bit>
  527. <Bit>
  528. <Name>DMEP1</Name>
  529. <Description/>
  530. <BitOffset>0x1F</BitOffset>
  531. <BitWidth>0x1</BitWidth>
  532. <Access>W</Access>
  533. <Values>
  534. <Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  535. <Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  536. </Values>
  537. </Bit>
  538. </AssignedBits>
  539. </Field>
  540. <Field>
  541. <Parameters address="0x52002128" name="FPRAR_CUR_B" size="0x4"/>
  542. <AssignedBits>
  543. <Bit>
  544. <Name>PROT_AREA_START2</Name>
  545. <Description>Flash Bank 2 PCROP start address</Description>
  546. <BitOffset>0x0</BitOffset>
  547. <BitWidth>0xC</BitWidth>
  548. <Access>R</Access>
  549. <Equation multiplier="0x100" offset="0x08100000"/>
  550. </Bit>
  551. <Bit>
  552. <Name>PROT_AREA_END2</Name>
  553. <Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  554. <BitOffset>0x10</BitOffset>
  555. <BitWidth>0xC</BitWidth>
  556. <Access>R</Access>
  557. <Equation multiplier="0x100" offset="0x081000FF"/>
  558. </Bit>
  559. <Bit>
  560. <Name>DMEP2</Name>
  561. <Description/>
  562. <BitOffset>0x1F</BitOffset>
  563. <BitWidth>0x1</BitWidth>
  564. <Access>R</Access>
  565. <Values>
  566. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  567. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  568. </Values>
  569. </Bit>
  570. </AssignedBits>
  571. </Field>
  572. <Field>
  573. <Parameters address="0x5200212C" name="FPRAR_PRG_B" size="0x4"/>
  574. <AssignedBits>
  575. <Bit>
  576. <Name>PROT_AREA_START2</Name>
  577. <Description>Flash Bank 2 PCROP start address</Description>
  578. <BitOffset>0x0</BitOffset>
  579. <BitWidth>0xC</BitWidth>
  580. <Access>W</Access>
  581. <Equation multiplier="0x100" offset="0x08100000"/>
  582. </Bit>
  583. <Bit>
  584. <Name>PROT_AREA_END2</Name>
  585. <Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
  586. <BitOffset>0x10</BitOffset>
  587. <BitWidth>0xC</BitWidth>
  588. <Access>W</Access>
  589. <Equation multiplier="0x100" offset="0x081000FF"/>
  590. </Bit>
  591. <Bit>
  592. <Name>DMEP2</Name>
  593. <Description/>
  594. <BitOffset>0x1F</BitOffset>
  595. <BitWidth>0x1</BitWidth>
  596. <Access>W</Access>
  597. <Values>
  598. <Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  599. <Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  600. </Values>
  601. </Bit>
  602. </AssignedBits>
  603. </Field>
  604. </Category>
  605. <Category>
  606. <Name>Secure Protection</Name>
  607. <Field>
  608. <Parameters address="0x52002030" name="FSCAR_CUR_A" size="0x4"/>
  609. <AssignedBits>
  610. <Bit config="0,10">
  611. <Name>SEC_AREA_START1</Name>
  612. <Description>Flash Bank 1 secure area start address</Description>
  613. <BitOffset>0x0</BitOffset>
  614. <BitWidth>0xC</BitWidth>
  615. <Access>R</Access>
  616. <Equation multiplier="0x100" offset="0x08000000"/>
  617. </Bit>
  618. <Bit config="0,10">
  619. <Name>SEC_AREA_END1</Name>
  620. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  621. <BitOffset>0x10</BitOffset>
  622. <BitWidth>0xC</BitWidth>
  623. <Access>R</Access>
  624. <Equation multiplier="0x100" offset="0x080000FF"/>
  625. </Bit>
  626. <Bit config="0,10">
  627. <Name>DMES1</Name>
  628. <Description/>
  629. <BitOffset>0x1F</BitOffset>
  630. <BitWidth>0x1</BitWidth>
  631. <Access>R</Access>
  632. <Values>
  633. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  634. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  635. </Values>
  636. </Bit>
  637. </AssignedBits>
  638. </Field>
  639. <Field>
  640. <Parameters address="0x52002034" name="FSCAR_PRG_A" size="0x4"/>
  641. <AssignedBits>
  642. <Bit config="0,10">
  643. <Name>SEC_AREA_START1</Name>
  644. <Description>Flash Bank 1 secure area start address</Description>
  645. <BitOffset>0x0</BitOffset>
  646. <BitWidth>0xC</BitWidth>
  647. <Access>W</Access>
  648. <Equation multiplier="0x100" offset="0x08000000"/>
  649. </Bit>
  650. <Bit config="0,10">
  651. <Name>SEC_AREA_END1</Name>
  652. <Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
  653. <BitOffset>0x10</BitOffset>
  654. <BitWidth>0xC</BitWidth>
  655. <Access>W</Access>
  656. <Equation multiplier="0x100" offset="0x080000FF"/>
  657. </Bit>
  658. <Bit config="0,10">
  659. <Name>DMES1</Name>
  660. <Description/>
  661. <BitOffset>0x1F</BitOffset>
  662. <BitWidth>0x1</BitWidth>
  663. <Access>W</Access>
  664. <Values>
  665. <Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  666. <Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  667. </Values>
  668. </Bit>
  669. </AssignedBits>
  670. </Field>
  671. <Field>
  672. <Parameters address="0x52002130" name="FSCAR_CUR_B" size="0x4"/>
  673. <AssignedBits>
  674. <Bit config="0,10">
  675. <Name>SEC_AREA_START2</Name>
  676. <Description>Flash Bank 2 secure area start address</Description>
  677. <BitOffset>0x0</BitOffset>
  678. <BitWidth>0xC</BitWidth>
  679. <Access>R</Access>
  680. <Equation multiplier="0x100" offset="0x08100000"/>
  681. </Bit>
  682. <Bit config="0,10">
  683. <Name>SEC_AREA_END2</Name>
  684. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  685. <BitOffset>0x10</BitOffset>
  686. <BitWidth>0xC</BitWidth>
  687. <Access>R</Access>
  688. <Equation multiplier="0x100" offset="0x081000FF"/>
  689. </Bit>
  690. <Bit config="0,10">
  691. <Name>DMES2</Name>
  692. <Description/>
  693. <BitOffset>0x1F</BitOffset>
  694. <BitWidth>0x1</BitWidth>
  695. <Access>R</Access>
  696. <Values>
  697. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  698. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  699. </Values>
  700. </Bit>
  701. </AssignedBits>
  702. </Field>
  703. <Field>
  704. <Parameters address="0x52002134" name="FSCAR_PRG_B" size="0x4"/>
  705. <AssignedBits>
  706. <Bit config="0,10">
  707. <Name>SEC_AREA_START2</Name>
  708. <Description>Flash Bank 2 secure area start address</Description>
  709. <BitOffset>0x0</BitOffset>
  710. <BitWidth>0xC</BitWidth>
  711. <Access>W</Access>
  712. <Equation multiplier="0x100" offset="0x08100000"/>
  713. </Bit>
  714. <Bit config="0,10">
  715. <Name>SEC_AREA_END2</Name>
  716. <Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
  717. <BitOffset>0x10</BitOffset>
  718. <BitWidth>0xC</BitWidth>
  719. <Access>W</Access>
  720. <Equation multiplier="0x100" offset="0x081000FF"/>
  721. </Bit>
  722. <Bit config="0,10">
  723. <Name>DMES2</Name>
  724. <Description/>
  725. <BitOffset>0x1F</BitOffset>
  726. <BitWidth>0x1</BitWidth>
  727. <Access>W</Access>
  728. <Values>
  729. <Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
  730. <Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
  731. </Values>
  732. </Bit>
  733. </AssignedBits>
  734. </Field>
  735. </Category>
  736. <Category>
  737. <Name>DTCM RAM Protection</Name>
  738. <Field>
  739. <Parameters address="0x5200201C" name="FOPTSR_CUR" size="0x4"/>
  740. <AssignedBits>
  741. <Bit>
  742. <Name>ST_RAM_SIZE</Name>
  743. <Description/>
  744. <BitOffset>0x13</BitOffset>
  745. <BitWidth>0x2</BitWidth>
  746. <Access>R</Access>
  747. <Values>
  748. <Val value="0x0">2 KB</Val>
  749. <Val value="0x1">4 KB</Val>
  750. <Val value="0x2">8 KB</Val>
  751. <Val value="0x3">16 KB</Val>
  752. </Values>
  753. </Bit>
  754. </AssignedBits>
  755. </Field>
  756. <Field>
  757. <Parameters address="0x52002020" name="FOPTSR_PRG" size="0x4"/>
  758. <AssignedBits>
  759. <Bit>
  760. <Name>ST_RAM_SIZE</Name>
  761. <Description/>
  762. <BitOffset>0x13</BitOffset>
  763. <BitWidth>0x2</BitWidth>
  764. <Access>W</Access>
  765. <Values>
  766. <Val value="0x0">2 KB</Val>
  767. <Val value="0x1">4 KB</Val>
  768. <Val value="0x2">8 KB</Val>
  769. <Val value="0x3">16 KB</Val>
  770. </Values>
  771. </Bit>
  772. </AssignedBits>
  773. </Field>
  774. </Category>
  775. <Category>
  776. <Name>Write Protection</Name>
  777. <Field>
  778. <Parameters address="0x52002038" name="FWPSN_CUR_A" size="0x4"/>
  779. <AssignedBits>
  780. <Bit>
  781. <Name>nWRP0</Name>
  782. <Description/>
  783. <BitOffset>0x0</BitOffset>
  784. <BitWidth>0x20</BitWidth>
  785. <Access>R</Access>
  786. <Values ByBit="true">
  787. <Val value="0x0">Write protection active</Val>
  788. <Val value="0x1">Write protection not active</Val>
  789. </Values>
  790. </Bit>
  791. </AssignedBits>
  792. </Field>
  793. <Field>
  794. <Parameters address="0x5200203C" name="FWPSN_PRG_A" size="0x4"/>
  795. <AssignedBits>
  796. <Bit>
  797. <Name>nWRP0</Name>
  798. <Description/>
  799. <BitOffset>0x0</BitOffset>
  800. <BitWidth>0x20</BitWidth>
  801. <Access>W</Access>
  802. <Values ByBit="true">
  803. <Val value="0x0">Write protection active</Val>
  804. <Val value="0x1">Write protection not active</Val>
  805. </Values>
  806. </Bit>
  807. </AssignedBits>
  808. </Field>
  809. <Field>
  810. <Parameters address="0x52002138" name="FWPSN_CUR_B" size="0x4"/>
  811. <AssignedBits>
  812. <Bit>
  813. <Name>nWRP32</Name>
  814. <Description/>
  815. <BitOffset>0x0</BitOffset>
  816. <BitWidth>0x20</BitWidth>
  817. <Access>R</Access>
  818. <Values ByBit="true">
  819. <Val value="0x0">Write protection active</Val>
  820. <Val value="0x1">Write protection not active</Val>
  821. </Values>
  822. </Bit>
  823. </AssignedBits>
  824. </Field>
  825. <Field>
  826. <Parameters address="0x5200213C" name="FWPSN_PRG_B" size="0x4"/>
  827. <AssignedBits>
  828. <Bit>
  829. <Name>nWRP32</Name>
  830. <Description/>
  831. <BitOffset>0x0</BitOffset>
  832. <BitWidth>0x20</BitWidth>
  833. <Access>W</Access>
  834. <Values ByBit="true">
  835. <Val value="0x0">Write protection active</Val>
  836. <Val value="0x1">Write protection not active</Val>
  837. </Values>
  838. </Bit>
  839. </AssignedBits>
  840. </Field>
  841. </Category>
  842. </Bank>
  843. </Peripheral>
  844. </Peripherals>
  845. </Device>
  846. </Root>