STM32_Prog_DB_0x482.xml 91 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x482</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32U5xx</Name>
  9. <Series>STM32U5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Single Bank non secure -->
  15. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  16. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  17. </Configuration>
  18. <Configuration number="0x1"> <!-- Dual Bank non secure -->
  19. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  20. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  21. </Configuration>
  22. <Configuration number="0x2"> <!-- Single Bank secure + RDP=0xAA -->
  23. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  25. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  26. </Configuration>
  27. <Configuration number="0x3"> <!-- Dual Bank secure + RDP=0xAA -->
  28. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  29. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  30. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  31. </Configuration>
  32. <Configuration number="0x4"> <!-- Single Bank secure -->
  33. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  34. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  35. </Configuration>
  36. <Configuration number="0x5"> <!-- Dual Bank secure -->
  37. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  38. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  39. </Configuration>
  40. </Interface>
  41. <!-- Bootloader Interface -->
  42. <Interface name="Bootloader">
  43. <Configuration number="0x6"> <!-- Single Bank Secure-->
  44. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  45. </Configuration>
  46. <Configuration number="0x7"> <!-- Dual Bank Secure-->
  47. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  48. </Configuration>
  49. </Interface>
  50. </Configurations>
  51. <!-- Peripherals -->
  52. <Peripherals>
  53. <!-- Embedded SRAM -->
  54. <Peripheral>
  55. <Name>Embedded SRAM</Name>
  56. <Type>Storage</Type>
  57. <Description/>
  58. <ErasedValue>0xFF</ErasedValue>
  59. <Access>RWE</Access>
  60. <!-- 96 KB -->
  61. <Configuration config="0,1,6,7,8,9">
  62. <Parameters address="0x20000000" name="SRAM" size="0xC0000"/>
  63. <Description/>
  64. <Organization>Single</Organization>
  65. <Bank name="Bank 1">
  66. <Field>
  67. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
  68. </Field>
  69. </Bank>
  70. </Configuration>
  71. <Configuration config="2,3,4,5">
  72. <Parameters address="0x30000000" name="SRAM" size="0xC0000"/>
  73. <Description/>
  74. <Organization>Single</Organization>
  75. <Bank name="Bank 1">
  76. <Field>
  77. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x8000"/>
  78. </Field>
  79. </Bank>
  80. </Configuration>
  81. </Peripheral>
  82. <!-- Embedded Flash -->
  83. <Peripheral>
  84. <Name>Embedded Flash</Name>
  85. <Type>Storage</Type>
  86. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  87. <ErasedValue>0xFF</ErasedValue>
  88. <Access>RWE</Access>
  89. <FlashSize address="0x0BFA07A0" default="0x200000"/>
  90. <Configuration config="0"> <!-- Single Bank -->
  91. <Parameters address="0x08000000" name=" 2048 Kbyte Embedded Flash" size="0x200000"/>
  92. <Description/>
  93. <Organization>Single</Organization>
  94. <Allignement>0x10</Allignement>
  95. <Bank name="Bank 1">
  96. <Field>
  97. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  98. </Field>
  99. </Bank>
  100. </Configuration>
  101. <Configuration config="1"> <!-- dual Bank -->
  102. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  103. <Description/>
  104. <Organization>Dual</Organization>
  105. <Allignement>0x10</Allignement>
  106. <Bank name="Bank 1">
  107. <Field>
  108. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  109. </Field>
  110. </Bank>
  111. <Bank name="Bank 2">
  112. <Field>
  113. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  114. </Field>
  115. </Bank>
  116. </Configuration>
  117. <Configuration config="2,4"> <!-- Single Bank secure -->
  118. <Parameters address="0x0C000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  119. <Description/>
  120. <Organization>Single</Organization>
  121. <Allignement>0x10</Allignement>
  122. <Bank name="Bank 1">
  123. <Field>
  124. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x4000"/>
  125. </Field>
  126. </Bank>
  127. </Configuration>
  128. <Configuration config="3,5"> <!-- dual Bank secure -->
  129. <Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  130. <Description/>
  131. <Organization>Dual</Organization>
  132. <Allignement>0x10</Allignement>
  133. <Bank name="Bank 1">
  134. <Field>
  135. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  136. </Field>
  137. </Bank>
  138. <Bank name="Bank 2">
  139. <Field>
  140. <Parameters address="0x0c100000" name="sector128" occurence="0x80" size="0x2000"/>
  141. </Field>
  142. </Bank>
  143. </Configuration>
  144. </Peripheral>
  145. <!-- Data EEPROM -->
  146. <Peripheral>
  147. <Name>Data EEPROM</Name>
  148. <Type>Storage</Type>
  149. <Description>The Data EEPROM memory block. It contains user data.</Description>
  150. <ErasedValue>0xFF</ErasedValue>
  151. <Access>RWE</Access>
  152. <Configuration config="2,4">
  153. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  154. <Description/>
  155. <Organization>Single</Organization>
  156. <Allignement>0x4</Allignement>
  157. <Bank name="Bank 1">
  158. <Field>
  159. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  160. </Field>
  161. </Bank>
  162. </Configuration>
  163. <Configuration config="3,5">
  164. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  165. <Description/>
  166. <Organization>Single</Organization>
  167. <Allignement>0x4</Allignement>
  168. <Bank name="Bank 1">
  169. <Field>
  170. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  171. </Field>
  172. </Bank>
  173. <Bank name="Bank 2">
  174. <Field>
  175. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  176. </Field>
  177. </Bank>
  178. </Configuration>
  179. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  180. <Configuration config="1">
  181. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  182. <Description/>
  183. <Organization>Single</Organization>
  184. <Allignement>0x4</Allignement>
  185. <Bank name="Bank 1">
  186. <Field>
  187. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  188. </Field>
  189. </Bank>
  190. <Bank name="Bank 2">
  191. <Field>
  192. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  193. </Field>
  194. </Bank>
  195. </Configuration>
  196. </Peripheral>
  197. <!-- OTP -->
  198. <Peripheral>
  199. <Name>OTP</Name>
  200. <Type>Storage</Type>
  201. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  202. <ErasedValue>0xFF</ErasedValue>
  203. <Access>RW</Access>
  204. <!-- 512 Bytes single bank -->
  205. <Configuration>
  206. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  207. <Description/>
  208. <Organization>Single</Organization>
  209. <Allignement>0x4</Allignement>
  210. <Bank name="OTP">
  211. <Field>
  212. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  213. </Field>
  214. </Bank>
  215. </Configuration>
  216. </Peripheral>
  217. <!-- Option Bytes -->
  218. <Peripheral>
  219. <Name>Option Bytes</Name>
  220. <Type>Configuration</Type>
  221. <Description/>
  222. <Access>RW</Access>
  223. <Configuration config="0,1">
  224. <Bank interface="JTAG_SWD">
  225. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  226. <Category>
  227. <Name>Read Out Protection</Name>
  228. <Field>
  229. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  230. <AssignedBits>
  231. <Bit>
  232. <Name>RDP</Name>
  233. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  234. <BitOffset>0x0</BitOffset>
  235. <BitWidth>0x8</BitWidth>
  236. <Access>RW</Access>
  237. <Values>
  238. <Val value="0xAA">Level 0, no protection</Val>
  239. <Val value="0xDC">Level 1, read protection of memories</Val>
  240. <Val value="0xCC">Level 2, chip protection</Val>
  241. </Values>
  242. </Bit>
  243. </AssignedBits>
  244. </Field>
  245. </Category>
  246. <Category>
  247. <Name>BOR Level</Name>
  248. <Field>
  249. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  250. <AssignedBits>
  251. <Bit>
  252. <Name>BOR_LEV</Name>
  253. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  254. <BitOffset>0x8</BitOffset>
  255. <BitWidth>0x3</BitWidth>
  256. <Access>RW</Access>
  257. <Values>
  258. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  259. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  260. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  261. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  262. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  263. </Values>
  264. </Bit>
  265. </AssignedBits>
  266. </Field>
  267. </Category>
  268. <Category>
  269. <Name>User Configuration</Name>
  270. <Field>
  271. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  272. <AssignedBits>
  273. <Bit>
  274. <Name>nRST_STOP</Name>
  275. <Description/>
  276. <BitOffset>0xC</BitOffset>
  277. <BitWidth>0x1</BitWidth>
  278. <Access>RW</Access>
  279. <Values>
  280. <Val value="0x0">Reset generated when entering Stop mode</Val>
  281. <Val value="0x1">No reset generated when entering Stop mode</Val>
  282. </Values>
  283. </Bit>
  284. <Bit>
  285. <Name>nRST_STDBY</Name>
  286. <Description/>
  287. <BitOffset>0xD</BitOffset>
  288. <BitWidth>0x1</BitWidth>
  289. <Access>RW</Access>
  290. <Values>
  291. <Val value="0x0">Reset generated when entering Standby mode</Val>
  292. <Val value="0x1">No reset generated when entering Standby mode</Val>
  293. </Values>
  294. </Bit>
  295. <Bit>
  296. <Name>nRST_SHDW</Name>
  297. <Description/>
  298. <BitOffset>0xE</BitOffset>
  299. <BitWidth>0x1</BitWidth>
  300. <Access>RW</Access>
  301. <Values>
  302. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  303. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  304. </Values>
  305. </Bit>
  306. <Bit>
  307. <Name>SRAM134_RST</Name>
  308. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  309. <BitOffset>0xF</BitOffset>
  310. <BitWidth>0x1</BitWidth>
  311. <Access>RW</Access>
  312. <Values>
  313. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  314. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  315. </Values>
  316. </Bit>
  317. <Bit>
  318. <Name>IWDG_SW</Name>
  319. <Description/>
  320. <BitOffset>0x10</BitOffset>
  321. <BitWidth>0x1</BitWidth>
  322. <Access>RW</Access>
  323. <Values>
  324. <Val value="0x0">Hardware independant watchdog</Val>
  325. <Val value="0x1">Software independant watchdog</Val>
  326. </Values>
  327. </Bit>
  328. <Bit>
  329. <Name>IWDG_STOP</Name>
  330. <Description/>
  331. <BitOffset>0x11</BitOffset>
  332. <BitWidth>0x1</BitWidth>
  333. <Access>RW</Access>
  334. <Values>
  335. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  336. <Val value="0x1">IWDG counter active in stop mode</Val>
  337. </Values>
  338. </Bit>
  339. <Bit>
  340. <Name>IWDG_STDBY</Name>
  341. <Description/>
  342. <BitOffset>0x12</BitOffset>
  343. <BitWidth>0x1</BitWidth>
  344. <Access>RW</Access>
  345. <Values>
  346. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  347. <Val value="0x1">IWDG counter active in standby mode</Val>
  348. </Values>
  349. </Bit>
  350. <Bit>
  351. <Name>WWDG_SW</Name>
  352. <Description/>
  353. <BitOffset>0x13</BitOffset>
  354. <BitWidth>0x1</BitWidth>
  355. <Access>RW</Access>
  356. <Values>
  357. <Val value="0x0">Hardware window watchdog</Val>
  358. <Val value="0x1">Software window watchdog</Val>
  359. </Values>
  360. </Bit>
  361. <Bit>
  362. <Name>SWAP_BANK</Name>
  363. <Description/>
  364. <BitOffset>0x14</BitOffset>
  365. <BitWidth>0x1</BitWidth>
  366. <Access>RW</Access>
  367. <Values>
  368. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  369. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  370. </Values>
  371. </Bit>
  372. <Bit>
  373. <Name>DBANK</Name>
  374. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  375. <BitOffset>0x15</BitOffset>
  376. <BitWidth>0x1</BitWidth>
  377. <Access>RW</Access>
  378. <Values>
  379. <Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
  380. <Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
  381. </Values>
  382. </Bit>
  383. <Bit>
  384. <Name>BKPRAM_ECC</Name>
  385. <Description>SRAM2 parity check enable</Description>
  386. <BitOffset>0x16</BitOffset>
  387. <BitWidth>0x1</BitWidth>
  388. <Access>RW</Access>
  389. <Values>
  390. <Val value="0x0">Backup RAM ECC check enabled</Val>
  391. <Val value="0x1">Backup RAM ECC check disabled</Val>
  392. </Values>
  393. </Bit>
  394. <Bit>
  395. <Name>SRAM3_ECC</Name>
  396. <Description>SRAM3 ECC detection and correction enable</Description>
  397. <BitOffset>0x17</BitOffset>
  398. <BitWidth>0x1</BitWidth>
  399. <Access>RW</Access>
  400. <Values>
  401. <Val value="0x0">SRAM3 ECC check enabled</Val>
  402. <Val value="0x1">SRAM3 ECC check disabled</Val>
  403. </Values>
  404. </Bit>
  405. <Bit>
  406. <Name>SRAM2_ECC</Name>
  407. <Description>SRAM2 ECC detection and correction enable</Description>
  408. <BitOffset>0x18</BitOffset>
  409. <BitWidth>0x1</BitWidth>
  410. <Access>RW</Access>
  411. <Values>
  412. <Val value="0x0">SRAM2 ECC check enabled</Val>
  413. <Val value="0x1">SRAM2 ECC check disabled</Val>
  414. </Values>
  415. </Bit>
  416. <Bit>
  417. <Name>SRAM2_RST</Name>
  418. <Description>SRAM2 Erase when system reset</Description>
  419. <BitOffset>0x19</BitOffset>
  420. <BitWidth>0x1</BitWidth>
  421. <Access>RW</Access>
  422. <Values>
  423. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  424. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  425. </Values>
  426. </Bit>
  427. <Bit>
  428. <Name>nSWBOOT0</Name>
  429. <Description>Software BOOT0</Description>
  430. <BitOffset>0x1A</BitOffset>
  431. <BitWidth>0x1</BitWidth>
  432. <Access>RW</Access>
  433. <Values>
  434. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  435. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  436. </Values>
  437. </Bit>
  438. <Bit>
  439. <Name>nBOOT0</Name>
  440. <Description>nBOOT0 option bit</Description>
  441. <BitOffset>0x1B</BitOffset>
  442. <BitWidth>0x1</BitWidth>
  443. <Access>RW</Access>
  444. <Values>
  445. <Val value="0x0">nBOOT0 = 0</Val>
  446. <Val value="0x1">nBOOT0 = 1</Val>
  447. </Values>
  448. </Bit>
  449. <Bit>
  450. <Name>PA15_PUPEN</Name>
  451. <Description>PA15 pull-up enable</Description>
  452. <BitOffset>0x1C</BitOffset>
  453. <BitWidth>0x1</BitWidth>
  454. <Access>RW</Access>
  455. <Values>
  456. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  457. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  458. </Values>
  459. </Bit>
  460. <Bit>
  461. <Name>IO_VDD_HSLV</Name>
  462. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  463. <BitOffset>0x1D</BitOffset>
  464. <BitWidth>0x1</BitWidth>
  465. <Access>RW</Access>
  466. <Values>
  467. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  468. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  469. </Values>
  470. </Bit>
  471. <Bit>
  472. <Name>IO_VDDIO2_HSLV</Name>
  473. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  474. <BitOffset>0x1E</BitOffset>
  475. <BitWidth>0x1</BitWidth>
  476. <Access>RW</Access>
  477. <Values>
  478. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  479. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  480. </Values>
  481. </Bit>
  482. <Bit>
  483. <Name>TZEN</Name>
  484. <Description>Global TrustZone security enable</Description>
  485. <BitOffset>0x1F</BitOffset>
  486. <BitWidth>0x1</BitWidth>
  487. <Access>RW</Access>
  488. <Values>
  489. <Val value="0x0">Global TrustZone security disabled</Val>
  490. <Val value="0x1">Global TrustZone security enabled</Val>
  491. </Values>
  492. </Bit>
  493. </AssignedBits>
  494. </Field>
  495. </Category>
  496. <Category>
  497. <Name>Boot Configuration</Name>
  498. <Field>
  499. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  500. <AssignedBits>
  501. <Bit>
  502. <Name>NSBOOTADD0</Name>
  503. <Description>Non-secure Boot base address 0</Description>
  504. <BitOffset>0x7</BitOffset>
  505. <BitWidth>0x19</BitWidth>
  506. <Access>RW</Access>
  507. <Equation multiplier="0x80" offset="0x0000000"/>
  508. </Bit>
  509. </AssignedBits>
  510. </Field>
  511. <Field>
  512. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  513. <AssignedBits>
  514. <Bit>
  515. <Name>NSBOOTADD1</Name>
  516. <Description>Non-secure Boot base address 1</Description>
  517. <BitOffset>0x7</BitOffset>
  518. <BitWidth>0x19</BitWidth>
  519. <Access>RW</Access>
  520. <Equation multiplier="0x80" offset="0x0000000"/>
  521. </Bit>
  522. </AssignedBits>
  523. </Field>
  524. </Category>
  525. <Category>
  526. <Name>Write Protection 1</Name>
  527. <Field>
  528. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  529. <AssignedBits>
  530. <Bit config="0">
  531. <Name>WRP1A_PSTRT</Name>
  532. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  533. <BitOffset>0x0</BitOffset>
  534. <BitWidth>0x7</BitWidth>
  535. <Access>RW</Access>
  536. <Equation multiplier="0x4000" offset="0x08000000"/>
  537. </Bit>
  538. <Bit config="1">
  539. <Name>WRP1A_PSTRT</Name>
  540. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  541. <BitOffset>0x0</BitOffset>
  542. <BitWidth>0x7</BitWidth>
  543. <Access>RW</Access>
  544. <Equation multiplier="0x2000" offset="0x08000000"/>
  545. </Bit>
  546. <Bit config="0">
  547. <Name>WRP1A_PEND</Name>
  548. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  549. <BitOffset>0x10</BitOffset>
  550. <BitWidth>0x7</BitWidth>
  551. <Access>RW</Access>
  552. <Equation multiplier="0x4000" offset="0x08000000"/>
  553. </Bit>
  554. <Bit config="1">
  555. <Name>WRP1A_PEND</Name>
  556. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  557. <BitOffset>0x10</BitOffset>
  558. <BitWidth>0x7</BitWidth>
  559. <Access>RW</Access>
  560. <Equation multiplier="0x2000" offset="0x08000000"/>
  561. </Bit>
  562. <Bit>
  563. <Name>UNLOCK_1A</Name>
  564. <Description>Bank 1 WPR first area A unlock</Description>
  565. <BitOffset>0x1F</BitOffset>
  566. <BitWidth>0x1</BitWidth>
  567. <Access>RW</Access>
  568. <Values>
  569. <Val value="0x0">WRP1A start and end pages locked</Val>
  570. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  571. </Values>
  572. </Bit>
  573. </AssignedBits>
  574. </Field>
  575. <Field>
  576. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  577. <AssignedBits>
  578. <Bit config="0">
  579. <Name>WRP1B_PSTRT</Name>
  580. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  581. <BitOffset>0x0</BitOffset>
  582. <BitWidth>0x7</BitWidth>
  583. <Access>RW</Access>
  584. <Equation multiplier="0x4000" offset="0x08000000"/>
  585. </Bit>
  586. <Bit config="1">
  587. <Name>WRP1B_PSTRT</Name>
  588. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  589. <BitOffset>0x0</BitOffset>
  590. <BitWidth>0x7</BitWidth>
  591. <Access>RW</Access>
  592. <Equation multiplier="0x2000" offset="0x08000000"/>
  593. </Bit>
  594. <Bit config="0">
  595. <Name>WRP1B_PEND</Name>
  596. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  597. <BitOffset>0x10</BitOffset>
  598. <BitWidth>0x7</BitWidth>
  599. <Access>RW</Access>
  600. <Equation multiplier="0x4000" offset="0x08000000"/>
  601. </Bit>
  602. <Bit config="1">
  603. <Name>WRP1B_PEND</Name>
  604. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  605. <BitOffset>0x10</BitOffset>
  606. <BitWidth>0x7</BitWidth>
  607. <Access>RW</Access>
  608. <Equation multiplier="0x2000" offset="0x08000000"/>
  609. </Bit>
  610. <Bit>
  611. <Name>UNLOCK_1B</Name>
  612. <Description>Bank 1 WPR first area B unlock</Description>
  613. <BitOffset>0x1F</BitOffset>
  614. <BitWidth>0x1</BitWidth>
  615. <Access>RW</Access>
  616. <Values>
  617. <Val value="0x0">WRP1B start and end pages locked</Val>
  618. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  619. </Values>
  620. </Bit>
  621. </AssignedBits>
  622. </Field>
  623. </Category>
  624. </Bank>
  625. <Bank interface="JTAG_SWD">
  626. <Parameters address="0x40022068" name="Bank 2" size="0x10"/>
  627. <Category>
  628. <Name>Write Protection 2</Name>
  629. <Field>
  630. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  631. <AssignedBits>
  632. <Bit config="0">
  633. <Name>WRP2A_PSTRT</Name>
  634. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  635. <BitOffset>0x0</BitOffset>
  636. <BitWidth>0x7</BitWidth>
  637. <Access>RW</Access>
  638. <Equation multiplier="0x4000" offset="0x08000000"/>
  639. </Bit>
  640. <Bit config="1">
  641. <Name>WRP2A_PSTRT</Name>
  642. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  643. <BitOffset>0x0</BitOffset>
  644. <BitWidth>0x7</BitWidth>
  645. <Access>RW</Access>
  646. <Equation multiplier="0x2000" offset="0x08100000"/>
  647. </Bit>
  648. <Bit config="0">
  649. <Name>WRP2A_PEND</Name>
  650. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  651. <BitOffset>0x10</BitOffset>
  652. <BitWidth>0x7</BitWidth>
  653. <Access>RW</Access>
  654. <Equation multiplier="0x4000" offset="0x08000000"/>
  655. </Bit>
  656. <Bit config="1">
  657. <Name>WRP2A_PEND</Name>
  658. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  659. <BitOffset>0x10</BitOffset>
  660. <BitWidth>0x7</BitWidth>
  661. <Access>RW</Access>
  662. <Equation multiplier="0x2000" offset="0x08100000"/>
  663. </Bit>
  664. <Bit>
  665. <Name>UNLOCK_2A</Name>
  666. <Description>Bank 2 WPR first area A unlock</Description>
  667. <BitOffset>0x1F</BitOffset>
  668. <BitWidth>0x1</BitWidth>
  669. <Access>RW</Access>
  670. <Values>
  671. <Val value="0x0">WRP2A start and end pages locked</Val>
  672. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  673. </Values>
  674. </Bit>
  675. </AssignedBits>
  676. </Field>
  677. <Field>
  678. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  679. <AssignedBits>
  680. <Bit config="0">
  681. <Name>WRP2B_PSTRT</Name>
  682. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  683. <BitOffset>0x0</BitOffset>
  684. <BitWidth>0x7</BitWidth>
  685. <Access>RW</Access>
  686. <Equation multiplier="0x4000" offset="0x08000000"/>
  687. </Bit>
  688. <Bit config="1">
  689. <Name>WRP2B_PSTRT</Name>
  690. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  691. <BitOffset>0x0</BitOffset>
  692. <BitWidth>0x7</BitWidth>
  693. <Access>RW</Access>
  694. <Equation multiplier="0x2000" offset="0x08100000"/>
  695. </Bit>
  696. <Bit config="0">
  697. <Name>WRP2B_PEND</Name>
  698. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  699. <BitOffset>0x10</BitOffset>
  700. <BitWidth>0x7</BitWidth>
  701. <Access>RW</Access>
  702. <Equation multiplier="0x4000" offset="0x08000000"/>
  703. </Bit>
  704. <Bit config="1">
  705. <Name>WRP2B_PEND</Name>
  706. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  707. <BitOffset>0x10</BitOffset>
  708. <BitWidth>0x7</BitWidth>
  709. <Access>RW</Access>
  710. <Equation multiplier="0x2000" offset="0x08100000"/>
  711. </Bit>
  712. <Bit>
  713. <Name>UNLOCK_2B</Name>
  714. <Description>Bank 2 WPR first area B unlock</Description>
  715. <BitOffset>0x1F</BitOffset>
  716. <BitWidth>0x1</BitWidth>
  717. <Access>RW</Access>
  718. <Values>
  719. <Val value="0x0">WRP2B start and end pages locked</Val>
  720. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  721. </Values>
  722. </Bit>
  723. </AssignedBits>
  724. </Field>
  725. </Category>
  726. </Bank>
  727. </Configuration>
  728. <Configuration config="2,3">
  729. <Bank interface="JTAG_SWD">
  730. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  731. <Category>
  732. <Name>Read Out Protection</Name>
  733. <Field>
  734. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  735. <AssignedBits>
  736. <Bit>
  737. <Name>RDP</Name>
  738. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  739. <BitOffset>0x0</BitOffset>
  740. <BitWidth>0x8</BitWidth>
  741. <Access>RW</Access>
  742. <Values>
  743. <Val value="0xAA">Level 0, no protection</Val>
  744. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  745. <Val value="0xDC">Level 1, read protection of memories</Val>
  746. <Val value="0xCC">Level 2, chip protection</Val>
  747. </Values>
  748. </Bit>
  749. </AssignedBits>
  750. </Field>
  751. </Category>
  752. <Category>
  753. <Name>BOR Level</Name>
  754. <Field>
  755. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  756. <AssignedBits>
  757. <Bit>
  758. <Name>BOR_LEV</Name>
  759. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  760. <BitOffset>0x8</BitOffset>
  761. <BitWidth>0x3</BitWidth>
  762. <Access>RW</Access>
  763. <Values>
  764. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  765. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  766. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  767. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  768. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  769. </Values>
  770. </Bit>
  771. </AssignedBits>
  772. </Field>
  773. </Category>
  774. <Category>
  775. <Name>User Configuration</Name>
  776. <Field>
  777. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  778. <AssignedBits>
  779. <Bit>
  780. <Name>nRST_STOP</Name>
  781. <Description/>
  782. <BitOffset>0xC</BitOffset>
  783. <BitWidth>0x1</BitWidth>
  784. <Access>RW</Access>
  785. <Values>
  786. <Val value="0x0">Reset generated when entering Stop mode</Val>
  787. <Val value="0x1">No reset generated when entering Stop mode</Val>
  788. </Values>
  789. </Bit>
  790. <Bit>
  791. <Name>nRST_STDBY</Name>
  792. <Description/>
  793. <BitOffset>0xD</BitOffset>
  794. <BitWidth>0x1</BitWidth>
  795. <Access>RW</Access>
  796. <Values>
  797. <Val value="0x0">Reset generated when entering Standby mode</Val>
  798. <Val value="0x1">No reset generated when entering Standby mode</Val>
  799. </Values>
  800. </Bit>
  801. <Bit>
  802. <Name>nRST_SHDW</Name>
  803. <Description/>
  804. <BitOffset>0xE</BitOffset>
  805. <BitWidth>0x1</BitWidth>
  806. <Access>RW</Access>
  807. <Values>
  808. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  809. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  810. </Values>
  811. </Bit>
  812. <Bit>
  813. <Name>SRAM134_RST</Name>
  814. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  815. <BitOffset>0xF</BitOffset>
  816. <BitWidth>0x1</BitWidth>
  817. <Access>RW</Access>
  818. <Values>
  819. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  820. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  821. </Values>
  822. </Bit>
  823. <Bit>
  824. <Name>IWDG_SW</Name>
  825. <Description/>
  826. <BitOffset>0x10</BitOffset>
  827. <BitWidth>0x1</BitWidth>
  828. <Access>RW</Access>
  829. <Values>
  830. <Val value="0x0">Hardware independant watchdog</Val>
  831. <Val value="0x1">Software independant watchdog</Val>
  832. </Values>
  833. </Bit>
  834. <Bit>
  835. <Name>IWDG_STOP</Name>
  836. <Description/>
  837. <BitOffset>0x11</BitOffset>
  838. <BitWidth>0x1</BitWidth>
  839. <Access>RW</Access>
  840. <Values>
  841. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  842. <Val value="0x1">IWDG counter active in stop mode</Val>
  843. </Values>
  844. </Bit>
  845. <Bit>
  846. <Name>IWDG_STDBY</Name>
  847. <Description/>
  848. <BitOffset>0x12</BitOffset>
  849. <BitWidth>0x1</BitWidth>
  850. <Access>RW</Access>
  851. <Values>
  852. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  853. <Val value="0x1">IWDG counter active in standby mode</Val>
  854. </Values>
  855. </Bit>
  856. <Bit>
  857. <Name>WWDG_SW</Name>
  858. <Description/>
  859. <BitOffset>0x13</BitOffset>
  860. <BitWidth>0x1</BitWidth>
  861. <Access>RW</Access>
  862. <Values>
  863. <Val value="0x0">Hardware window watchdog</Val>
  864. <Val value="0x1">Software window watchdog</Val>
  865. </Values>
  866. </Bit>
  867. <Bit>
  868. <Name>SWAP_BANK</Name>
  869. <Description/>
  870. <BitOffset>0x14</BitOffset>
  871. <BitWidth>0x1</BitWidth>
  872. <Access>RW</Access>
  873. <Values>
  874. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  875. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  876. </Values>
  877. </Bit>
  878. <Bit>
  879. <Name>DBANK</Name>
  880. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  881. <BitOffset>0x15</BitOffset>
  882. <BitWidth>0x1</BitWidth>
  883. <Access>RW</Access>
  884. <Values>
  885. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  886. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  887. </Values>
  888. </Bit>
  889. <Bit>
  890. <Name>SRAM2_PE</Name>
  891. <Description>SRAM2 parity check enable</Description>
  892. <BitOffset>0x18</BitOffset>
  893. <BitWidth>0x1</BitWidth>
  894. <Access>RW</Access>
  895. <Values>
  896. <Val value="0x0">SRAM2 parity check enable</Val>
  897. <Val value="0x1">SRAM2 parity check disable</Val>
  898. </Values>
  899. </Bit>
  900. <Bit>
  901. <Name>SRAM2_RST</Name>
  902. <Description>SRAM2 Erase when system reset</Description>
  903. <BitOffset>0x19</BitOffset>
  904. <BitWidth>0x1</BitWidth>
  905. <Access>RW</Access>
  906. <Values>
  907. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  908. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  909. </Values>
  910. </Bit>
  911. <Bit>
  912. <Name>nSWBOOT0</Name>
  913. <Description>Software BOOT0</Description>
  914. <BitOffset>0x1A</BitOffset>
  915. <BitWidth>0x1</BitWidth>
  916. <Access>RW</Access>
  917. <Values>
  918. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  919. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  920. </Values>
  921. </Bit>
  922. <Bit>
  923. <Name>nBOOT0</Name>
  924. <Description>nBOOT0 option bit</Description>
  925. <BitOffset>0x1B</BitOffset>
  926. <BitWidth>0x1</BitWidth>
  927. <Access>RW</Access>
  928. <Values>
  929. <Val value="0x0">nBOOT0 = 0</Val>
  930. <Val value="0x1">nBOOT0 = 1</Val>
  931. </Values>
  932. </Bit>
  933. <Bit>
  934. <Name>PA15_PUPEN</Name>
  935. <Description>PA15 pull-up enable</Description>
  936. <BitOffset>0x1C</BitOffset>
  937. <BitWidth>0x1</BitWidth>
  938. <Access>RW</Access>
  939. <Values>
  940. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  941. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  942. </Values>
  943. </Bit>
  944. <Bit>
  945. <Name>BKPRAM_ECC</Name>
  946. <Description>SRAM2 parity check enable</Description>
  947. <BitOffset>0x16</BitOffset>
  948. <BitWidth>0x1</BitWidth>
  949. <Access>RW</Access>
  950. <Values>
  951. <Val value="0x0">Backup RAM ECC check enabled</Val>
  952. <Val value="0x1">Backup RAM ECC check disabled</Val>
  953. </Values>
  954. </Bit>
  955. <Bit>
  956. <Name>SRAM3_ECC</Name>
  957. <Description>SRAM3 ECC detection and correction enable</Description>
  958. <BitOffset>0x17</BitOffset>
  959. <BitWidth>0x1</BitWidth>
  960. <Access>RW</Access>
  961. <Values>
  962. <Val value="0x0">SRAM3 ECC check enabled</Val>
  963. <Val value="0x1">SRAM3 ECC check disabled</Val>
  964. </Values>
  965. </Bit>
  966. <Bit>
  967. <Name>SRAM2_ECC</Name>
  968. <Description>SRAM2 ECC detection and correction enable</Description>
  969. <BitOffset>0x18</BitOffset>
  970. <BitWidth>0x1</BitWidth>
  971. <Access>RW</Access>
  972. <Values>
  973. <Val value="0x0">SRAM2 ECC check enabled</Val>
  974. <Val value="0x1">SRAM2 ECC check disabled</Val>
  975. </Values>
  976. </Bit>
  977. <Bit>
  978. <Name>IO_VDD_HSLV</Name>
  979. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  980. <BitOffset>0x1D</BitOffset>
  981. <BitWidth>0x1</BitWidth>
  982. <Access>RW</Access>
  983. <Values>
  984. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  985. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  986. </Values>
  987. </Bit>
  988. <Bit>
  989. <Name>IO_VDDIO2_HSLV</Name>
  990. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  991. <BitOffset>0x1E</BitOffset>
  992. <BitWidth>0x1</BitWidth>
  993. <Access>RW</Access>
  994. <Values>
  995. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  996. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  997. </Values>
  998. </Bit>
  999. <Bit>
  1000. <Name>TZEN</Name>
  1001. <Description>Global TrustZone security enable</Description>
  1002. <BitOffset>0x1F</BitOffset>
  1003. <BitWidth>0x1</BitWidth>
  1004. <Access>RW</Access>
  1005. <Values>
  1006. <Val value="0x0">Global TrustZone security disabled</Val>
  1007. <Val value="0x1">Global TrustZone security enabled</Val>
  1008. </Values>
  1009. </Bit>
  1010. </AssignedBits>
  1011. </Field>
  1012. </Category>
  1013. <Category>
  1014. <Name>Boot Configuration</Name>
  1015. <Field>
  1016. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1017. <AssignedBits>
  1018. <Bit>
  1019. <Name>NSBOOTADD0</Name>
  1020. <Description>Non-secure Boot base address 0</Description>
  1021. <BitOffset>0x7</BitOffset>
  1022. <BitWidth>0x19</BitWidth>
  1023. <Access>RW</Access>
  1024. <Equation multiplier="0x80" offset="0x0000000"/>
  1025. </Bit>
  1026. </AssignedBits>
  1027. </Field>
  1028. <Field>
  1029. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1030. <AssignedBits>
  1031. <Bit>
  1032. <Name>NSBOOTADD1</Name>
  1033. <Description>Non-secure Boot base address 1</Description>
  1034. <BitOffset>0x7</BitOffset>
  1035. <BitWidth>0x19</BitWidth>
  1036. <Access>RW</Access>
  1037. <Equation multiplier="0x80" offset="0x0000000"/>
  1038. </Bit>
  1039. </AssignedBits>
  1040. </Field>
  1041. <Field>
  1042. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1043. <AssignedBits>
  1044. <Bit>
  1045. <Name>SECBOOTADD0</Name>
  1046. <Description>Secure boot base address 0</Description>
  1047. <BitOffset>0x7</BitOffset>
  1048. <BitWidth>0x19</BitWidth>
  1049. <Access>RW</Access>
  1050. <Equation multiplier="0x80" offset="0x0000000"/>
  1051. </Bit>
  1052. </AssignedBits>
  1053. </Field>
  1054. <Field>
  1055. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  1056. <AssignedBits>
  1057. <Bit>
  1058. <Name>BOOT_LOCK</Name>
  1059. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1060. <BitOffset>0x0</BitOffset>
  1061. <BitWidth>0x1</BitWidth>
  1062. <Access>RW</Access>
  1063. <Values>
  1064. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1065. <Val value="0x1">Boot forced from base address memory</Val>
  1066. </Values>
  1067. </Bit>
  1068. </AssignedBits>
  1069. </Field>
  1070. </Category>
  1071. <Category>
  1072. <Name>Secure Area 1</Name>
  1073. <Field>
  1074. <Parameters address="0x50022050" name="FLASH_SECWM1R1" size="0x4"/>
  1075. <AssignedBits>
  1076. <Bit config="2">
  1077. <Name>SECWM1_PSTRT</Name>
  1078. <Description>Start page of first secure area</Description>
  1079. <BitOffset>0x0</BitOffset>
  1080. <BitWidth>0x7</BitWidth>
  1081. <Access>RW</Access>
  1082. <Equation multiplier="0x4000" offset="0x08000000"/>
  1083. </Bit>
  1084. <Bit config="3">
  1085. <Name>SECWM1_PSTRT</Name>
  1086. <Description>Start page of first secure area</Description>
  1087. <BitOffset>0x0</BitOffset>
  1088. <BitWidth>0x7</BitWidth>
  1089. <Access>RW</Access>
  1090. <Equation multiplier="0x2000" offset="0x08000000"/>
  1091. </Bit>
  1092. <Bit config="2">
  1093. <Name>SECWM1_PEND</Name>
  1094. <Description>End page of first secure area</Description>
  1095. <BitOffset>0x10</BitOffset>
  1096. <BitWidth>0x7</BitWidth>
  1097. <Access>RW</Access>
  1098. <Equation multiplier="0x4000" offset="0x08000000"/>
  1099. </Bit>
  1100. <Bit config="3">
  1101. <Name>SECWM1_PEND</Name>
  1102. <Description>End page of first secure area</Description>
  1103. <BitOffset>0x10</BitOffset>
  1104. <BitWidth>0x7</BitWidth>
  1105. <Access>RW</Access>
  1106. <Equation multiplier="0x2000" offset="0x08000000"/>
  1107. </Bit>
  1108. </AssignedBits>
  1109. </Field>
  1110. </Category>
  1111. <Category>
  1112. <Name>Write Protection 1</Name>
  1113. <Field>
  1114. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  1115. <AssignedBits>
  1116. <Bit config="2">
  1117. <Name>WRP1A_PSTRT</Name>
  1118. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1119. <BitOffset>0x0</BitOffset>
  1120. <BitWidth>0x7</BitWidth>
  1121. <Access>RW</Access>
  1122. <Equation multiplier="0x4000" offset="0x08000000"/>
  1123. </Bit>
  1124. <Bit config="3">
  1125. <Name>WRP1A_PSTRT</Name>
  1126. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1127. <BitOffset>0x0</BitOffset>
  1128. <BitWidth>0x7</BitWidth>
  1129. <Access>RW</Access>
  1130. <Equation multiplier="0x2000" offset="0x08000000"/>
  1131. </Bit>
  1132. <Bit config="2">
  1133. <Name>WRP1A_PEND</Name>
  1134. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1135. <BitOffset>0x10</BitOffset>
  1136. <BitWidth>0x7</BitWidth>
  1137. <Access>RW</Access>
  1138. <Equation multiplier="0x4000" offset="0x08000000"/>
  1139. </Bit>
  1140. <Bit config="3">
  1141. <Name>WRP1A_PEND</Name>
  1142. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1143. <BitOffset>0x10</BitOffset>
  1144. <BitWidth>0x7</BitWidth>
  1145. <Access>RW</Access>
  1146. <Equation multiplier="0x2000" offset="0x08000000"/>
  1147. </Bit>
  1148. <Bit>
  1149. <Name>UNLOCK_1A</Name>
  1150. <Description>Bank 1 WPR first area A unlock</Description>
  1151. <BitOffset>0x1F</BitOffset>
  1152. <BitWidth>0x1</BitWidth>
  1153. <Access>RW</Access>
  1154. <Values>
  1155. <Val value="0x0">WRP1A start and end pages locked</Val>
  1156. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1157. </Values>
  1158. </Bit>
  1159. </AssignedBits>
  1160. </Field>
  1161. <Field>
  1162. <Parameters address="0x5002205C" name="FLASH_WRP1BR" size="0x4"/>
  1163. <AssignedBits>
  1164. <Bit config="2">
  1165. <Name>WRP1B_PSTRT</Name>
  1166. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1167. <BitOffset>0x0</BitOffset>
  1168. <BitWidth>0x7</BitWidth>
  1169. <Access>RW</Access>
  1170. <Equation multiplier="0x4000" offset="0x08000000"/>
  1171. </Bit>
  1172. <Bit config="3">
  1173. <Name>WRP1B_PSTRT</Name>
  1174. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1175. <BitOffset>0x0</BitOffset>
  1176. <BitWidth>0x7</BitWidth>
  1177. <Access>RW</Access>
  1178. <Equation multiplier="0x2000" offset="0x08000000"/>
  1179. </Bit>
  1180. <Bit config="2">
  1181. <Name>WRP1B_PEND</Name>
  1182. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1183. <BitOffset>0x10</BitOffset>
  1184. <BitWidth>0x7</BitWidth>
  1185. <Access>RW</Access>
  1186. <Equation multiplier="0x4000" offset="0x08000000"/>
  1187. </Bit>
  1188. <Bit config="3">
  1189. <Name>WRP1B_PEND</Name>
  1190. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1191. <BitOffset>0x10</BitOffset>
  1192. <BitWidth>0x7</BitWidth>
  1193. <Access>RW</Access>
  1194. <Equation multiplier="0x2000" offset="0x08000000"/>
  1195. </Bit>
  1196. <Bit>
  1197. <Name>UNLOCK_1B</Name>
  1198. <Description>Bank 1 WPR first area B unlock</Description>
  1199. <BitOffset>0x1F</BitOffset>
  1200. <BitWidth>0x1</BitWidth>
  1201. <Access>RW</Access>
  1202. <Values>
  1203. <Val value="0x0">WRP1B start and end pages locked</Val>
  1204. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1205. </Values>
  1206. </Bit>
  1207. </AssignedBits>
  1208. </Field>
  1209. </Category>
  1210. </Bank>
  1211. <Bank interface="JTAG_SWD">
  1212. <Parameters address="0x50022060" name="Bank 2" size="0x10"/>
  1213. <Category>
  1214. <Name>Secure Area 2</Name>
  1215. <Field>
  1216. <Parameters address="0x50022060" name="FLASH_SECWM2R1" size="0x4"/>
  1217. <AssignedBits>
  1218. <Bit config="2">
  1219. <Name>SECWM2_PSTRT</Name>
  1220. <Description>Start page of second secure area</Description>
  1221. <BitOffset>0x0</BitOffset>
  1222. <BitWidth>0x7</BitWidth>
  1223. <Access>RW</Access>
  1224. <Equation multiplier="0x4000" offset="0x08000000"/>
  1225. </Bit>
  1226. <Bit config="3">
  1227. <Name>SECWM2_PSTRT</Name>
  1228. <Description>Start page of second secure area</Description>
  1229. <BitOffset>0x0</BitOffset>
  1230. <BitWidth>0x7</BitWidth>
  1231. <Access>RW</Access>
  1232. <Equation multiplier="0x2000" offset="0x08100000"/>
  1233. </Bit>
  1234. <Bit config="2">
  1235. <Name>SECWM2_PEND</Name>
  1236. <Description>End page of second secure area</Description>
  1237. <BitOffset>0x10</BitOffset>
  1238. <BitWidth>0x7</BitWidth>
  1239. <Access>RW</Access>
  1240. <Equation multiplier="0x4000" offset="0x08000000"/>
  1241. </Bit>
  1242. <Bit config="3">
  1243. <Name>SECWM2_PEND</Name>
  1244. <Description>End page of second secure area</Description>
  1245. <BitOffset>0x10</BitOffset>
  1246. <BitWidth>0x7</BitWidth>
  1247. <Access>RW</Access>
  1248. <Equation multiplier="0x2000" offset="0x08100000"/>
  1249. </Bit>
  1250. </AssignedBits>
  1251. </Field>
  1252. </Category>
  1253. <Category>
  1254. <Name>Write Protection 2</Name>
  1255. <Field>
  1256. <Parameters address="0x50022068" name="FLASH_WRP2AR" size="0x4"/>
  1257. <AssignedBits>
  1258. <Bit config="2">
  1259. <Name>WRP2A_PSTRT</Name>
  1260. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1261. <BitOffset>0x0</BitOffset>
  1262. <BitWidth>0x7</BitWidth>
  1263. <Access>RW</Access>
  1264. <Equation multiplier="0x4000" offset="0x08100000"/>
  1265. </Bit>
  1266. <Bit config="3">
  1267. <Name>WRP2A_PSTRT</Name>
  1268. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1269. <BitOffset>0x0</BitOffset>
  1270. <BitWidth>0x7</BitWidth>
  1271. <Access>RW</Access>
  1272. <Equation multiplier="0x2000" offset="0x08100000"/>
  1273. </Bit>
  1274. <Bit config="2">
  1275. <Name>WRP2A_PEND</Name>
  1276. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1277. <BitOffset>0x10</BitOffset>
  1278. <BitWidth>0x7</BitWidth>
  1279. <Access>RW</Access>
  1280. <Equation multiplier="0x4000" offset="0x08100000"/>
  1281. </Bit>
  1282. <Bit config="3">
  1283. <Name>WRP2A_PEND</Name>
  1284. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1285. <BitOffset>0x10</BitOffset>
  1286. <BitWidth>0x7</BitWidth>
  1287. <Access>RW</Access>
  1288. <Equation multiplier="0x2000" offset="0x08100000"/>
  1289. </Bit>
  1290. <Bit>
  1291. <Name>UNLOCK_2A</Name>
  1292. <Description>Bank 2 WPR first area A unlock</Description>
  1293. <BitOffset>0x1F</BitOffset>
  1294. <BitWidth>0x1</BitWidth>
  1295. <Access>RW</Access>
  1296. <Values>
  1297. <Val value="0x0">WRP2A start and end pages locked</Val>
  1298. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1299. </Values>
  1300. </Bit>
  1301. </AssignedBits>
  1302. </Field>
  1303. <Field>
  1304. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  1305. <AssignedBits>
  1306. <Bit config="2">
  1307. <Name>WRP2B_PSTRT</Name>
  1308. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1309. <BitOffset>0x0</BitOffset>
  1310. <BitWidth>0x7</BitWidth>
  1311. <Access>RW</Access>
  1312. <Equation multiplier="0x4000" offset="0x08100000"/>
  1313. </Bit>
  1314. <Bit config="3">
  1315. <Name>WRP2B_PSTRT</Name>
  1316. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1317. <BitOffset>0x0</BitOffset>
  1318. <BitWidth>0x7</BitWidth>
  1319. <Access>RW</Access>
  1320. <Equation multiplier="0x2000" offset="0x08100000"/>
  1321. </Bit>
  1322. <Bit config="2">
  1323. <Name>WRP2B_PEND</Name>
  1324. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1325. <BitOffset>0x10</BitOffset>
  1326. <BitWidth>0x7</BitWidth>
  1327. <Access>RW</Access>
  1328. <Equation multiplier="0x4000" offset="0x08100000"/>
  1329. </Bit>
  1330. <Bit config="3">
  1331. <Name>WRP2B_PEND</Name>
  1332. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1333. <BitOffset>0x10</BitOffset>
  1334. <BitWidth>0x7</BitWidth>
  1335. <Access>RW</Access>
  1336. <Equation multiplier="0x2000" offset="0x08100000"/>
  1337. </Bit>
  1338. <Bit>
  1339. <Name>UNLOCK_2B</Name>
  1340. <Description>Bank 2 WPR first area B unlock</Description>
  1341. <BitOffset>0x1F</BitOffset>
  1342. <BitWidth>0x1</BitWidth>
  1343. <Access>RW</Access>
  1344. <Values>
  1345. <Val value="0x0">WRP2B start and end pages locked</Val>
  1346. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1347. </Values>
  1348. </Bit>
  1349. </AssignedBits>
  1350. </Field>
  1351. </Category>
  1352. </Bank>
  1353. </Configuration>
  1354. <Configuration config="4,5">
  1355. <Bank interface="JTAG_SWD">
  1356. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  1357. <Category>
  1358. <Name>Read Out Protection</Name>
  1359. <Field>
  1360. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1361. <AssignedBits>
  1362. <Bit>
  1363. <Name>RDP</Name>
  1364. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1365. <BitOffset>0x0</BitOffset>
  1366. <BitWidth>0x8</BitWidth>
  1367. <Access>RW</Access>
  1368. <Values>
  1369. <Val value="0xAA">Level 0, no protection</Val>
  1370. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1371. <Val value="0xDC">Level 1, read protection of memories</Val>
  1372. <Val value="0xCC">Level 2, chip protection</Val>
  1373. </Values>
  1374. </Bit>
  1375. </AssignedBits>
  1376. </Field>
  1377. </Category>
  1378. <Category>
  1379. <Name>BOR Level</Name>
  1380. <Field>
  1381. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1382. <AssignedBits>
  1383. <Bit>
  1384. <Name>BOR_LEV</Name>
  1385. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  1386. <BitOffset>0x8</BitOffset>
  1387. <BitWidth>0x3</BitWidth>
  1388. <Access>RW</Access>
  1389. <Values>
  1390. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1391. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1392. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1393. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1394. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1395. </Values>
  1396. </Bit>
  1397. </AssignedBits>
  1398. </Field>
  1399. </Category>
  1400. <Category>
  1401. <Name>User Configuration</Name>
  1402. <Field>
  1403. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1404. <AssignedBits>
  1405. <Bit>
  1406. <Name>nRST_STOP</Name>
  1407. <Description/>
  1408. <BitOffset>0xC</BitOffset>
  1409. <BitWidth>0x1</BitWidth>
  1410. <Access>RW</Access>
  1411. <Values>
  1412. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1413. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1414. </Values>
  1415. </Bit>
  1416. <Bit>
  1417. <Name>nRST_STDBY</Name>
  1418. <Description/>
  1419. <BitOffset>0xD</BitOffset>
  1420. <BitWidth>0x1</BitWidth>
  1421. <Access>RW</Access>
  1422. <Values>
  1423. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1424. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1425. </Values>
  1426. </Bit>
  1427. <Bit>
  1428. <Name>nRST_SHDW</Name>
  1429. <Description/>
  1430. <BitOffset>0xE</BitOffset>
  1431. <BitWidth>0x1</BitWidth>
  1432. <Access>RW</Access>
  1433. <Values>
  1434. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1435. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1436. </Values>
  1437. </Bit>
  1438. <Bit>
  1439. <Name>SRAM134_RST</Name>
  1440. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  1441. <BitOffset>0xF</BitOffset>
  1442. <BitWidth>0x1</BitWidth>
  1443. <Access>RW</Access>
  1444. <Values>
  1445. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  1446. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  1447. </Values>
  1448. </Bit>
  1449. <Bit>
  1450. <Name>IWDG_SW</Name>
  1451. <Description/>
  1452. <BitOffset>0x10</BitOffset>
  1453. <BitWidth>0x1</BitWidth>
  1454. <Access>RW</Access>
  1455. <Values>
  1456. <Val value="0x0">Hardware independant watchdog</Val>
  1457. <Val value="0x1">Software independant watchdog</Val>
  1458. </Values>
  1459. </Bit>
  1460. <Bit>
  1461. <Name>IWDG_STOP</Name>
  1462. <Description/>
  1463. <BitOffset>0x11</BitOffset>
  1464. <BitWidth>0x1</BitWidth>
  1465. <Access>RW</Access>
  1466. <Values>
  1467. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1468. <Val value="0x1">IWDG counter active in stop mode</Val>
  1469. </Values>
  1470. </Bit>
  1471. <Bit>
  1472. <Name>IWDG_STDBY</Name>
  1473. <Description/>
  1474. <BitOffset>0x12</BitOffset>
  1475. <BitWidth>0x1</BitWidth>
  1476. <Access>RW</Access>
  1477. <Values>
  1478. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1479. <Val value="0x1">IWDG counter active in standby mode</Val>
  1480. </Values>
  1481. </Bit>
  1482. <Bit>
  1483. <Name>WWDG_SW</Name>
  1484. <Description/>
  1485. <BitOffset>0x13</BitOffset>
  1486. <BitWidth>0x1</BitWidth>
  1487. <Access>RW</Access>
  1488. <Values>
  1489. <Val value="0x0">Hardware window watchdog</Val>
  1490. <Val value="0x1">Software window watchdog</Val>
  1491. </Values>
  1492. </Bit>
  1493. <Bit>
  1494. <Name>SWAP_BANK</Name>
  1495. <Description/>
  1496. <BitOffset>0x14</BitOffset>
  1497. <BitWidth>0x1</BitWidth>
  1498. <Access>RW</Access>
  1499. <Values>
  1500. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1501. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1502. </Values>
  1503. </Bit>
  1504. <Bit>
  1505. <Name>DBANK</Name>
  1506. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  1507. <BitOffset>0x15</BitOffset>
  1508. <BitWidth>0x1</BitWidth>
  1509. <Access>RW</Access>
  1510. <Values>
  1511. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1512. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1513. </Values>
  1514. </Bit>
  1515. <Bit>
  1516. <Name>SRAM2_PE</Name>
  1517. <Description>SRAM2 parity check enable</Description>
  1518. <BitOffset>0x18</BitOffset>
  1519. <BitWidth>0x1</BitWidth>
  1520. <Access>RW</Access>
  1521. <Values>
  1522. <Val value="0x0">SRAM2 parity check enable</Val>
  1523. <Val value="0x1">SRAM2 parity check disable</Val>
  1524. </Values>
  1525. </Bit>
  1526. <Bit>
  1527. <Name>SRAM2_RST</Name>
  1528. <Description>SRAM2 Erase when system reset</Description>
  1529. <BitOffset>0x19</BitOffset>
  1530. <BitWidth>0x1</BitWidth>
  1531. <Access>RW</Access>
  1532. <Values>
  1533. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1534. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1535. </Values>
  1536. </Bit>
  1537. <Bit>
  1538. <Name>nSWBOOT0</Name>
  1539. <Description>Software BOOT0</Description>
  1540. <BitOffset>0x1A</BitOffset>
  1541. <BitWidth>0x1</BitWidth>
  1542. <Access>RW</Access>
  1543. <Values>
  1544. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1545. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1546. </Values>
  1547. </Bit>
  1548. <Bit>
  1549. <Name>nBOOT0</Name>
  1550. <Description>nBOOT0 option bit</Description>
  1551. <BitOffset>0x1B</BitOffset>
  1552. <BitWidth>0x1</BitWidth>
  1553. <Access>RW</Access>
  1554. <Values>
  1555. <Val value="0x0">nBOOT0 = 0</Val>
  1556. <Val value="0x1">nBOOT0 = 1</Val>
  1557. </Values>
  1558. </Bit>
  1559. <Bit>
  1560. <Name>PA15_PUPEN</Name>
  1561. <Description>PA15 pull-up enable</Description>
  1562. <BitOffset>0x1C</BitOffset>
  1563. <BitWidth>0x1</BitWidth>
  1564. <Access>RW</Access>
  1565. <Values>
  1566. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1567. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1568. </Values>
  1569. </Bit>
  1570. <Bit>
  1571. <Name>BKPRAM_ECC</Name>
  1572. <Description>SRAM2 parity check enable</Description>
  1573. <BitOffset>0x16</BitOffset>
  1574. <BitWidth>0x1</BitWidth>
  1575. <Access>RW</Access>
  1576. <Values>
  1577. <Val value="0x0">Backup RAM ECC check enabled</Val>
  1578. <Val value="0x1">Backup RAM ECC check disabled</Val>
  1579. </Values>
  1580. </Bit>
  1581. <Bit>
  1582. <Name>SRAM3_ECC</Name>
  1583. <Description>SRAM3 ECC detection and correction enable</Description>
  1584. <BitOffset>0x17</BitOffset>
  1585. <BitWidth>0x1</BitWidth>
  1586. <Access>RW</Access>
  1587. <Values>
  1588. <Val value="0x0">SRAM3 ECC check enabled</Val>
  1589. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1590. </Values>
  1591. </Bit>
  1592. <Bit>
  1593. <Name>SRAM2_ECC</Name>
  1594. <Description>SRAM2 ECC detection and correction enable</Description>
  1595. <BitOffset>0x18</BitOffset>
  1596. <BitWidth>0x1</BitWidth>
  1597. <Access>RW</Access>
  1598. <Values>
  1599. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1600. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1601. </Values>
  1602. </Bit>
  1603. <Bit>
  1604. <Name>IO_VDD_HSLV</Name>
  1605. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1606. <BitOffset>0x1D</BitOffset>
  1607. <BitWidth>0x1</BitWidth>
  1608. <Access>RW</Access>
  1609. <Values>
  1610. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1611. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1612. </Values>
  1613. </Bit>
  1614. <Bit>
  1615. <Name>IO_VDDIO2_HSLV</Name>
  1616. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1617. <BitOffset>0x1E</BitOffset>
  1618. <BitWidth>0x1</BitWidth>
  1619. <Access>RW</Access>
  1620. <Values>
  1621. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1622. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1623. </Values>
  1624. </Bit>
  1625. <Bit>
  1626. <Name>TZEN</Name>
  1627. <Description>Global TrustZone security enable</Description>
  1628. <BitOffset>0x1F</BitOffset>
  1629. <BitWidth>0x1</BitWidth>
  1630. <Access>RW</Access>
  1631. <Values>
  1632. <Val value="0x0">Global TrustZone security disabled</Val>
  1633. <Val value="0x1">Global TrustZone security enabled</Val>
  1634. </Values>
  1635. </Bit>
  1636. </AssignedBits>
  1637. </Field>
  1638. </Category>
  1639. <Category>
  1640. <Name>Boot Configuration</Name>
  1641. <Field>
  1642. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1643. <AssignedBits>
  1644. <Bit>
  1645. <Name>NSBOOTADD0</Name>
  1646. <Description>Non-secure Boot base address 0</Description>
  1647. <BitOffset>0x7</BitOffset>
  1648. <BitWidth>0x19</BitWidth>
  1649. <Access>RW</Access>
  1650. <Equation multiplier="0x80" offset="0x0000000"/>
  1651. </Bit>
  1652. </AssignedBits>
  1653. </Field>
  1654. <Field>
  1655. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1656. <AssignedBits>
  1657. <Bit>
  1658. <Name>NSBOOTADD1</Name>
  1659. <Description>Non-secure Boot base address 1</Description>
  1660. <BitOffset>0x7</BitOffset>
  1661. <BitWidth>0x19</BitWidth>
  1662. <Access>RW</Access>
  1663. <Equation multiplier="0x80" offset="0x0000000"/>
  1664. </Bit>
  1665. </AssignedBits>
  1666. </Field>
  1667. <Field>
  1668. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1669. <AssignedBits>
  1670. <Bit>
  1671. <Name>SECBOOTADD0</Name>
  1672. <Description>Secure boot base address 0</Description>
  1673. <BitOffset>0x7</BitOffset>
  1674. <BitWidth>0x19</BitWidth>
  1675. <Access>RW</Access>
  1676. <Equation multiplier="0x80" offset="0x0000000"/>
  1677. </Bit>
  1678. </AssignedBits>
  1679. </Field>
  1680. <Field>
  1681. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1682. <AssignedBits>
  1683. <Bit>
  1684. <Name>BOOT_LOCK</Name>
  1685. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1686. <BitOffset>0x0</BitOffset>
  1687. <BitWidth>0x1</BitWidth>
  1688. <Access>RW</Access>
  1689. <Values>
  1690. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1691. <Val value="0x1">Boot forced from base address memory</Val>
  1692. </Values>
  1693. </Bit>
  1694. </AssignedBits>
  1695. </Field>
  1696. </Category>
  1697. <Category>
  1698. <Name>Secure Area 1</Name>
  1699. <Field>
  1700. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  1701. <AssignedBits>
  1702. <Bit config="4">
  1703. <Name>SECWM1_PSTRT</Name>
  1704. <Description>Start page of first secure area</Description>
  1705. <BitOffset>0x0</BitOffset>
  1706. <BitWidth>0x7</BitWidth>
  1707. <Access>RW</Access>
  1708. <Equation multiplier="0x4000" offset="0x08000000"/>
  1709. </Bit>
  1710. <Bit config="5">
  1711. <Name>SECWM1_PSTRT</Name>
  1712. <Description>Start page of first secure area</Description>
  1713. <BitOffset>0x0</BitOffset>
  1714. <BitWidth>0x7</BitWidth>
  1715. <Access>RW</Access>
  1716. <Equation multiplier="0x2000" offset="0x08000000"/>
  1717. </Bit>
  1718. <Bit config="4">
  1719. <Name>SECWM1_PEND</Name>
  1720. <Description>End page of first secure area</Description>
  1721. <BitOffset>0x10</BitOffset>
  1722. <BitWidth>0x7</BitWidth>
  1723. <Access>RW</Access>
  1724. <Equation multiplier="0x4000" offset="0x08000000"/>
  1725. </Bit>
  1726. <Bit config="5">
  1727. <Name>SECWM1_PEND</Name>
  1728. <Description>End page of first secure area</Description>
  1729. <BitOffset>0x10</BitOffset>
  1730. <BitWidth>0x7</BitWidth>
  1731. <Access>RW</Access>
  1732. <Equation multiplier="0x2000" offset="0x08000000"/>
  1733. </Bit>
  1734. </AssignedBits>
  1735. </Field>
  1736. </Category>
  1737. <Category>
  1738. <Name>Write Protection 1</Name>
  1739. <Field>
  1740. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  1741. <AssignedBits>
  1742. <Bit config="4">
  1743. <Name>WRP1A_PSTRT</Name>
  1744. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1745. <BitOffset>0x0</BitOffset>
  1746. <BitWidth>0x7</BitWidth>
  1747. <Access>RW</Access>
  1748. <Equation multiplier="0x4000" offset="0x08000000"/>
  1749. </Bit>
  1750. <Bit config="5">
  1751. <Name>WRP1A_PSTRT</Name>
  1752. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1753. <BitOffset>0x0</BitOffset>
  1754. <BitWidth>0x7</BitWidth>
  1755. <Access>RW</Access>
  1756. <Equation multiplier="0x2000" offset="0x08000000"/>
  1757. </Bit>
  1758. <Bit config="4">
  1759. <Name>WRP1A_PEND</Name>
  1760. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1761. <BitOffset>0x10</BitOffset>
  1762. <BitWidth>0x7</BitWidth>
  1763. <Access>RW</Access>
  1764. <Equation multiplier="0x4000" offset="0x08000000"/>
  1765. </Bit>
  1766. <Bit config="5">
  1767. <Name>WRP1A_PEND</Name>
  1768. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1769. <BitOffset>0x10</BitOffset>
  1770. <BitWidth>0x7</BitWidth>
  1771. <Access>RW</Access>
  1772. <Equation multiplier="0x2000" offset="0x08000000"/>
  1773. </Bit>
  1774. <Bit>
  1775. <Name>UNLOCK_1A</Name>
  1776. <Description>Bank 1 WPR first area A unlock</Description>
  1777. <BitOffset>0x1F</BitOffset>
  1778. <BitWidth>0x1</BitWidth>
  1779. <Access>RW</Access>
  1780. <Values>
  1781. <Val value="0x0">WRP1A start and end pages locked</Val>
  1782. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1783. </Values>
  1784. </Bit>
  1785. </AssignedBits>
  1786. </Field>
  1787. <Field>
  1788. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  1789. <AssignedBits>
  1790. <Bit config="4">
  1791. <Name>WRP1B_PSTRT</Name>
  1792. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1793. <BitOffset>0x0</BitOffset>
  1794. <BitWidth>0x7</BitWidth>
  1795. <Access>RW</Access>
  1796. <Equation multiplier="0x4000" offset="0x08000000"/>
  1797. </Bit>
  1798. <Bit config="5">
  1799. <Name>WRP1B_PSTRT</Name>
  1800. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1801. <BitOffset>0x0</BitOffset>
  1802. <BitWidth>0x7</BitWidth>
  1803. <Access>RW</Access>
  1804. <Equation multiplier="0x2000" offset="0x08000000"/>
  1805. </Bit>
  1806. <Bit config="4">
  1807. <Name>WRP1B_PEND</Name>
  1808. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1809. <BitOffset>0x10</BitOffset>
  1810. <BitWidth>0x7</BitWidth>
  1811. <Access>RW</Access>
  1812. <Equation multiplier="0x4000" offset="0x08000000"/>
  1813. </Bit>
  1814. <Bit config="5">
  1815. <Name>WRP1B_PEND</Name>
  1816. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1817. <BitOffset>0x10</BitOffset>
  1818. <BitWidth>0x7</BitWidth>
  1819. <Access>RW</Access>
  1820. <Equation multiplier="0x2000" offset="0x08000000"/>
  1821. </Bit>
  1822. <Bit>
  1823. <Name>UNLOCK_1B</Name>
  1824. <Description>Bank 1 WPR first area B unlock</Description>
  1825. <BitOffset>0x1F</BitOffset>
  1826. <BitWidth>0x1</BitWidth>
  1827. <Access>RW</Access>
  1828. <Values>
  1829. <Val value="0x0">WRP1B start and end pages locked</Val>
  1830. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1831. </Values>
  1832. </Bit>
  1833. </AssignedBits>
  1834. </Field>
  1835. </Category>
  1836. </Bank>
  1837. <Bank interface="JTAG_SWD">
  1838. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  1839. <Category>
  1840. <Name>Secure Area 2</Name>
  1841. <Field>
  1842. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  1843. <AssignedBits>
  1844. <Bit config="4">
  1845. <Name>SECWM2_PSTRT</Name>
  1846. <Description>Start page of second secure area</Description>
  1847. <BitOffset>0x0</BitOffset>
  1848. <BitWidth>0x7</BitWidth>
  1849. <Access>RW</Access>
  1850. <Equation multiplier="0x4000" offset="0x08000000"/>
  1851. </Bit>
  1852. <Bit config="5">
  1853. <Name>SECWM2_PSTRT</Name>
  1854. <Description>Start page of second secure area</Description>
  1855. <BitOffset>0x0</BitOffset>
  1856. <BitWidth>0x7</BitWidth>
  1857. <Access>RW</Access>
  1858. <Equation multiplier="0x2000" offset="0x08100000"/>
  1859. </Bit>
  1860. <Bit config="4">
  1861. <Name>SECWM2_PEND</Name>
  1862. <Description>End page of second secure area</Description>
  1863. <BitOffset>0x10</BitOffset>
  1864. <BitWidth>0x7</BitWidth>
  1865. <Access>RW</Access>
  1866. <Equation multiplier="0x4000" offset="0x08000000"/>
  1867. </Bit>
  1868. <Bit config="5">
  1869. <Name>SECWM2_PEND</Name>
  1870. <Description>End page of second secure area</Description>
  1871. <BitOffset>0x10</BitOffset>
  1872. <BitWidth>0x7</BitWidth>
  1873. <Access>RW</Access>
  1874. <Equation multiplier="0x2000" offset="0x08100000"/>
  1875. </Bit>
  1876. </AssignedBits>
  1877. </Field>
  1878. </Category>
  1879. <Category>
  1880. <Name>Write Protection 2</Name>
  1881. <Field>
  1882. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  1883. <AssignedBits>
  1884. <Bit config="4">
  1885. <Name>WRP2A_PSTRT</Name>
  1886. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1887. <BitOffset>0x0</BitOffset>
  1888. <BitWidth>0x7</BitWidth>
  1889. <Access>RW</Access>
  1890. <Equation multiplier="0x4000" offset="0x08100000"/>
  1891. </Bit>
  1892. <Bit config="5">
  1893. <Name>WRP2A_PSTRT</Name>
  1894. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1895. <BitOffset>0x0</BitOffset>
  1896. <BitWidth>0x7</BitWidth>
  1897. <Access>RW</Access>
  1898. <Equation multiplier="0x2000" offset="0x08100000"/>
  1899. </Bit>
  1900. <Bit config="4">
  1901. <Name>WRP2A_PEND</Name>
  1902. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1903. <BitOffset>0x10</BitOffset>
  1904. <BitWidth>0x7</BitWidth>
  1905. <Access>RW</Access>
  1906. <Equation multiplier="0x4000" offset="0x08100000"/>
  1907. </Bit>
  1908. <Bit config="5">
  1909. <Name>WRP2A_PEND</Name>
  1910. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1911. <BitOffset>0x10</BitOffset>
  1912. <BitWidth>0x7</BitWidth>
  1913. <Access>RW</Access>
  1914. <Equation multiplier="0x2000" offset="0x08100000"/>
  1915. </Bit>
  1916. <Bit>
  1917. <Name>UNLOCK_2A</Name>
  1918. <Description>Bank 2 WPR first area A unlock</Description>
  1919. <BitOffset>0x1F</BitOffset>
  1920. <BitWidth>0x1</BitWidth>
  1921. <Access>RW</Access>
  1922. <Values>
  1923. <Val value="0x0">WRP2A start and end pages locked</Val>
  1924. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1925. </Values>
  1926. </Bit>
  1927. </AssignedBits>
  1928. </Field>
  1929. <Field>
  1930. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  1931. <AssignedBits>
  1932. <Bit config="4">
  1933. <Name>WRP2B_PSTRT</Name>
  1934. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1935. <BitOffset>0x0</BitOffset>
  1936. <BitWidth>0x7</BitWidth>
  1937. <Access>RW</Access>
  1938. <Equation multiplier="0x4000" offset="0x08100000"/>
  1939. </Bit>
  1940. <Bit config="5">
  1941. <Name>WRP2B_PSTRT</Name>
  1942. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1943. <BitOffset>0x0</BitOffset>
  1944. <BitWidth>0x7</BitWidth>
  1945. <Access>RW</Access>
  1946. <Equation multiplier="0x2000" offset="0x08100000"/>
  1947. </Bit>
  1948. <Bit config="4">
  1949. <Name>WRP2B_PEND</Name>
  1950. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1951. <BitOffset>0x10</BitOffset>
  1952. <BitWidth>0x7</BitWidth>
  1953. <Access>RW</Access>
  1954. <Equation multiplier="0x4000" offset="0x08100000"/>
  1955. </Bit>
  1956. <Bit config="5">
  1957. <Name>WRP2B_PEND</Name>
  1958. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1959. <BitOffset>0x10</BitOffset>
  1960. <BitWidth>0x7</BitWidth>
  1961. <Access>RW</Access>
  1962. <Equation multiplier="0x2000" offset="0x08100000"/>
  1963. </Bit>
  1964. <Bit>
  1965. <Name>UNLOCK_2B</Name>
  1966. <Description>Bank 2 WPR first area B unlock</Description>
  1967. <BitOffset>0x1F</BitOffset>
  1968. <BitWidth>0x1</BitWidth>
  1969. <Access>RW</Access>
  1970. <Values>
  1971. <Val value="0x0">WRP2B start and end pages locked</Val>
  1972. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1973. </Values>
  1974. </Bit>
  1975. </AssignedBits>
  1976. </Field>
  1977. </Category>
  1978. </Bank>
  1979. </Configuration>
  1980. <Bank interface="Bootloader">
  1981. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  1982. <Category>
  1983. <Name>Read Out Protection</Name>
  1984. <Field>
  1985. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1986. <AssignedBits>
  1987. <Bit>
  1988. <Name>RDP</Name>
  1989. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1990. <BitOffset>0x0</BitOffset>
  1991. <BitWidth>0x8</BitWidth>
  1992. <Access>RW</Access>
  1993. <Values>
  1994. <Val value="0xAA">Level 0, no protection</Val>
  1995. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1996. <Val value="0xDC">Level 1, read protection of memories</Val>
  1997. <Val value="0xCC">Level 2, chip protection</Val>
  1998. </Values>
  1999. </Bit>
  2000. </AssignedBits>
  2001. </Field>
  2002. </Category>
  2003. <Category>
  2004. <Name>BOR Level</Name>
  2005. <Field>
  2006. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2007. <AssignedBits>
  2008. <Bit>
  2009. <Name>BOR_LEV</Name>
  2010. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  2011. <BitOffset>0x8</BitOffset>
  2012. <BitWidth>0x3</BitWidth>
  2013. <Access>RW</Access>
  2014. <Values>
  2015. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  2016. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  2017. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  2018. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  2019. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  2020. </Values>
  2021. </Bit>
  2022. </AssignedBits>
  2023. </Field>
  2024. </Category>
  2025. <Category>
  2026. <Name>User Configuration</Name>
  2027. <Field>
  2028. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2029. <AssignedBits>
  2030. <Bit>
  2031. <Name>nRST_STOP</Name>
  2032. <Description/>
  2033. <BitOffset>0xC</BitOffset>
  2034. <BitWidth>0x1</BitWidth>
  2035. <Access>RW</Access>
  2036. <Values>
  2037. <Val value="0x0">Reset generated when entering Stop mode</Val>
  2038. <Val value="0x1">No reset generated when entering Stop mode</Val>
  2039. </Values>
  2040. </Bit>
  2041. <Bit>
  2042. <Name>nRST_STDBY</Name>
  2043. <Description/>
  2044. <BitOffset>0xD</BitOffset>
  2045. <BitWidth>0x1</BitWidth>
  2046. <Access>RW</Access>
  2047. <Values>
  2048. <Val value="0x0">Reset generated when entering Standby mode</Val>
  2049. <Val value="0x1">No reset generated when entering Standby mode</Val>
  2050. </Values>
  2051. </Bit>
  2052. <Bit>
  2053. <Name>nRST_SHDW</Name>
  2054. <Description/>
  2055. <BitOffset>0xE</BitOffset>
  2056. <BitWidth>0x1</BitWidth>
  2057. <Access>RW</Access>
  2058. <Values>
  2059. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  2060. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  2061. </Values>
  2062. </Bit>
  2063. <Bit>
  2064. <Name>IWDG_SW</Name>
  2065. <Description/>
  2066. <BitOffset>0x10</BitOffset>
  2067. <BitWidth>0x1</BitWidth>
  2068. <Access>RW</Access>
  2069. <Values>
  2070. <Val value="0x0">Hardware independant watchdog</Val>
  2071. <Val value="0x1">Software independant watchdog</Val>
  2072. </Values>
  2073. </Bit>
  2074. <Bit>
  2075. <Name>IWDG_STOP</Name>
  2076. <Description/>
  2077. <BitOffset>0x11</BitOffset>
  2078. <BitWidth>0x1</BitWidth>
  2079. <Access>RW</Access>
  2080. <Values>
  2081. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  2082. <Val value="0x1">IWDG counter active in stop mode</Val>
  2083. </Values>
  2084. </Bit>
  2085. <Bit>
  2086. <Name>IWDG_STDBY</Name>
  2087. <Description/>
  2088. <BitOffset>0x12</BitOffset>
  2089. <BitWidth>0x1</BitWidth>
  2090. <Access>RW</Access>
  2091. <Values>
  2092. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  2093. <Val value="0x1">IWDG counter active in standby mode</Val>
  2094. </Values>
  2095. </Bit>
  2096. <Bit>
  2097. <Name>WWDG_SW</Name>
  2098. <Description/>
  2099. <BitOffset>0x13</BitOffset>
  2100. <BitWidth>0x1</BitWidth>
  2101. <Access>RW</Access>
  2102. <Values>
  2103. <Val value="0x0">Hardware window watchdog</Val>
  2104. <Val value="0x1">Software window watchdog</Val>
  2105. </Values>
  2106. </Bit>
  2107. <Bit>
  2108. <Name>SWAP_BANK</Name>
  2109. <Description/>
  2110. <BitOffset>0x14</BitOffset>
  2111. <BitWidth>0x1</BitWidth>
  2112. <Access>RW</Access>
  2113. <Values>
  2114. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  2115. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  2116. </Values>
  2117. </Bit>
  2118. <Bit>
  2119. <Name>DB256</Name>
  2120. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  2121. <BitOffset>0x15</BitOffset>
  2122. <BitWidth>0x1</BitWidth>
  2123. <Access>RW</Access>
  2124. <Values>
  2125. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  2126. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  2127. </Values>
  2128. </Bit>
  2129. <Bit>
  2130. <Name>DBANK</Name>
  2131. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  2132. <BitOffset>0x16</BitOffset>
  2133. <BitWidth>0x1</BitWidth>
  2134. <Access>RW</Access>
  2135. <Values>
  2136. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  2137. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  2138. </Values>
  2139. </Bit>
  2140. <Bit>
  2141. <Name>SRAM2_PE</Name>
  2142. <Description>SRAM2 parity check enable</Description>
  2143. <BitOffset>0x18</BitOffset>
  2144. <BitWidth>0x1</BitWidth>
  2145. <Access>RW</Access>
  2146. <Values>
  2147. <Val value="0x0">SRAM2 parity check enable</Val>
  2148. <Val value="0x1">SRAM2 parity check disable</Val>
  2149. </Values>
  2150. </Bit>
  2151. <Bit>
  2152. <Name>SRAM2_RST</Name>
  2153. <Description>SRAM2 Erase when system reset</Description>
  2154. <BitOffset>0x19</BitOffset>
  2155. <BitWidth>0x1</BitWidth>
  2156. <Access>RW</Access>
  2157. <Values>
  2158. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  2159. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  2160. </Values>
  2161. </Bit>
  2162. <Bit>
  2163. <Name>nSWBOOT0</Name>
  2164. <Description>Software BOOT0</Description>
  2165. <BitOffset>0x1A</BitOffset>
  2166. <BitWidth>0x1</BitWidth>
  2167. <Access>RW</Access>
  2168. <Values>
  2169. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  2170. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  2171. </Values>
  2172. </Bit>
  2173. <Bit>
  2174. <Name>nBOOT0</Name>
  2175. <Description>nBOOT0 option bit</Description>
  2176. <BitOffset>0x1B</BitOffset>
  2177. <BitWidth>0x1</BitWidth>
  2178. <Access>RW</Access>
  2179. <Values>
  2180. <Val value="0x0">nBOOT0 = 0</Val>
  2181. <Val value="0x1">nBOOT0 = 1</Val>
  2182. </Values>
  2183. </Bit>
  2184. <Bit>
  2185. <Name>PA15_PUPEN</Name>
  2186. <Description>PA15 pull-up enable</Description>
  2187. <BitOffset>0x1C</BitOffset>
  2188. <BitWidth>0x1</BitWidth>
  2189. <Access>RW</Access>
  2190. <Values>
  2191. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  2192. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  2193. </Values>
  2194. </Bit>
  2195. <Bit>
  2196. <Name>TZEN</Name>
  2197. <Description>Global TrustZone security enable</Description>
  2198. <BitOffset>0x1F</BitOffset>
  2199. <BitWidth>0x1</BitWidth>
  2200. <Access>RW</Access>
  2201. <Values>
  2202. <Val value="0x0">Global TrustZone security disabled</Val>
  2203. <Val value="0x1">Global TrustZone security enabled</Val>
  2204. </Values>
  2205. </Bit>
  2206. </AssignedBits>
  2207. </Field>
  2208. <Field>
  2209. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  2210. <AssignedBits>
  2211. <Bit config="6,7,8,9">
  2212. <Name>HDP1EN</Name>
  2213. <Description>Hide protection first area enable</Description>
  2214. <BitOffset>0x1F</BitOffset>
  2215. <BitWidth>0x1</BitWidth>
  2216. <Access>RW</Access>
  2217. <Values>
  2218. <Val value="0x0">No HDP area 1</Val>
  2219. <Val value="0x1">HDP first area is enabled</Val>
  2220. </Values>
  2221. </Bit>
  2222. <Bit config="6,8">
  2223. <Name>HDP1_PEND</Name>
  2224. <Description>End page of first hide protection area</Description>
  2225. <BitOffset>0x10</BitOffset>
  2226. <BitWidth>0x7</BitWidth>
  2227. <Access>RW</Access>
  2228. <Equation multiplier="0x4" offset="0x08000000"/>
  2229. </Bit>
  2230. <Bit config="7,9">
  2231. <Name>HDP1_PEND</Name>
  2232. <Description>End page of first hide protection area</Description>
  2233. <BitOffset>0x10</BitOffset>
  2234. <BitWidth>0x7</BitWidth>
  2235. <Access>RW</Access>
  2236. <Equation multiplier="0x2" offset="0x08000000"/>
  2237. </Bit>
  2238. </AssignedBits>
  2239. </Field>
  2240. <Field>
  2241. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2242. <AssignedBits>
  2243. <Bit config="6,7,8,9">
  2244. <Name>HDP2EN</Name>
  2245. <Description>Hide protection second area enable</Description>
  2246. <BitOffset>0x1F</BitOffset>
  2247. <BitWidth>0x1</BitWidth>
  2248. <Access>RW</Access>
  2249. <Values>
  2250. <Val value="0x0">No HDP area 2</Val>
  2251. <Val value="0x1">HDP second area is enabled</Val>
  2252. </Values>
  2253. </Bit>
  2254. <Bit config="6,8">
  2255. <Name>HDP2_PEND</Name>
  2256. <Description>End page of second hide protection area</Description>
  2257. <BitOffset>0x10</BitOffset>
  2258. <BitWidth>0x7</BitWidth>
  2259. <Access>RW</Access>
  2260. <Equation multiplier="0x4" offset="0x08000000"/>
  2261. </Bit>
  2262. <Bit config="7,9">
  2263. <Name>HDP2_PEND</Name>
  2264. <Description>End page of second hide protection area</Description>
  2265. <BitOffset>0x10</BitOffset>
  2266. <BitWidth>0x7</BitWidth>
  2267. <Access>RW</Access>
  2268. <Equation multiplier="0x2" offset="0x08000000"/>
  2269. </Bit>
  2270. </AssignedBits>
  2271. </Field>
  2272. <Field>
  2273. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2274. <AssignedBits>
  2275. <Bit>
  2276. <Name>NSBOOTADD0</Name>
  2277. <Description>Non-secure Boot base address 0</Description>
  2278. <BitOffset>0x7</BitOffset>
  2279. <BitWidth>0x19</BitWidth>
  2280. <Access>RW</Access>
  2281. <Equation multiplier="0x80" offset="0x0000000"/>
  2282. </Bit>
  2283. </AssignedBits>
  2284. </Field>
  2285. <Field>
  2286. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2287. <AssignedBits>
  2288. <Bit>
  2289. <Name>NSBOOTADD1</Name>
  2290. <Description>Non-secure Boot base address 1</Description>
  2291. <BitOffset>0x7</BitOffset>
  2292. <BitWidth>0x19</BitWidth>
  2293. <Access>RW</Access>
  2294. <Equation multiplier="0x80" offset="0x0000000"/>
  2295. </Bit>
  2296. </AssignedBits>
  2297. </Field>
  2298. </Category>
  2299. <Category>
  2300. <Name>Write Protection 1</Name>
  2301. <Field>
  2302. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2303. <AssignedBits>
  2304. <Bit config="6">
  2305. <Name>WRP1A_PSTRT</Name>
  2306. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2307. <BitOffset>0x0</BitOffset>
  2308. <BitWidth>0x7</BitWidth>
  2309. <Access>RW</Access>
  2310. <Equation multiplier="0x4000" offset="0x08000000"/>
  2311. </Bit>
  2312. <Bit config="7">
  2313. <Name>WRP1A_PSTRT</Name>
  2314. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2315. <BitOffset>0x0</BitOffset>
  2316. <BitWidth>0x7</BitWidth>
  2317. <Access>RW</Access>
  2318. <Equation multiplier="0x2000" offset="0x08000000"/>
  2319. </Bit>
  2320. <Bit config="6">
  2321. <Name>WRP1A_PEND</Name>
  2322. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2323. <BitOffset>0x10</BitOffset>
  2324. <BitWidth>0x7</BitWidth>
  2325. <Access>RW</Access>
  2326. <Equation multiplier="0x4000" offset="0x08000000"/>
  2327. </Bit>
  2328. <Bit config="7">
  2329. <Name>WRP1A_PEND</Name>
  2330. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2331. <BitOffset>0x10</BitOffset>
  2332. <BitWidth>0x7</BitWidth>
  2333. <Access>RW</Access>
  2334. <Equation multiplier="0x2000" offset="0x08000000"/>
  2335. </Bit>
  2336. <Bit>
  2337. <Name>UNLOCK</Name>
  2338. <Description>Bank 1 WPR first area A unlock</Description>
  2339. <BitOffset>0x1F</BitOffset>
  2340. <BitWidth>0x1</BitWidth>
  2341. <Access>RW</Access>
  2342. <Values>
  2343. <Val value="0x0">WRP1A start and end pages locked</Val>
  2344. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  2345. </Values>
  2346. </Bit>
  2347. </AssignedBits>
  2348. </Field>
  2349. <Field>
  2350. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  2351. <AssignedBits>
  2352. <Bit config="6">
  2353. <Name>WRP1B_PSTRT</Name>
  2354. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2355. <BitOffset>0x0</BitOffset>
  2356. <BitWidth>0x7</BitWidth>
  2357. <Access>RW</Access>
  2358. <Equation multiplier="0x4000" offset="0x08000000"/>
  2359. </Bit>
  2360. <Bit config="7">
  2361. <Name>WRP1B_PSTRT</Name>
  2362. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2363. <BitOffset>0x0</BitOffset>
  2364. <BitWidth>0x7</BitWidth>
  2365. <Access>RW</Access>
  2366. <Equation multiplier="0x2000" offset="0x08000000"/>
  2367. </Bit>
  2368. <Bit config="6">
  2369. <Name>WRP1B_PEND</Name>
  2370. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2371. <BitOffset>0x10</BitOffset>
  2372. <BitWidth>0x7</BitWidth>
  2373. <Access>RW</Access>
  2374. <Equation multiplier="0x4000" offset="0x08000000"/>
  2375. </Bit>
  2376. <Bit config="7">
  2377. <Name>WRP1B_PEND</Name>
  2378. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2379. <BitOffset>0x10</BitOffset>
  2380. <BitWidth>0x7</BitWidth>
  2381. <Access>RW</Access>
  2382. <Equation multiplier="0x2000" offset="0x08000000"/>
  2383. </Bit>
  2384. <Bit>
  2385. <Name>UNLOCK</Name>
  2386. <Description>Bank 1 WPR first area B unlock</Description>
  2387. <BitOffset>0x1F</BitOffset>
  2388. <BitWidth>0x1</BitWidth>
  2389. <Access>RW</Access>
  2390. <Values>
  2391. <Val value="0x0">WRP1B start and end pages locked</Val>
  2392. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  2393. </Values>
  2394. </Bit>
  2395. </AssignedBits>
  2396. </Field>
  2397. </Category>
  2398. <Parameters address="0x40022068" name="Bank 2" size="0x8"/>
  2399. <Category>
  2400. <Name>Write Protection 2</Name>
  2401. <Field>
  2402. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2403. <AssignedBits>
  2404. <Bit config="6">
  2405. <Name>WRP2A_PSTRT</Name>
  2406. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2407. <BitOffset>0x0</BitOffset>
  2408. <BitWidth>0x7</BitWidth>
  2409. <Access>RW</Access>
  2410. <Equation multiplier="0x4000" offset="0x08000000"/>
  2411. </Bit>
  2412. <Bit config="7">
  2413. <Name>WRP2A_PSTRT</Name>
  2414. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2415. <BitOffset>0x0</BitOffset>
  2416. <BitWidth>0x7</BitWidth>
  2417. <Access>RW</Access>
  2418. <Equation multiplier="0x2000" offset="0x08200000"/>
  2419. </Bit>
  2420. <Bit config="6">
  2421. <Name>WRP2A_PEND</Name>
  2422. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2423. <BitOffset>0x10</BitOffset>
  2424. <BitWidth>0x7</BitWidth>
  2425. <Access>RW</Access>
  2426. <Equation multiplier="0x4000" offset="0x08000000"/>
  2427. </Bit>
  2428. <Bit config="7">
  2429. <Name>WRP2A_PEND</Name>
  2430. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2431. <BitOffset>0x10</BitOffset>
  2432. <BitWidth>0x7</BitWidth>
  2433. <Access>RW</Access>
  2434. <Equation multiplier="0x2000" offset="0x08200000"/>
  2435. </Bit>
  2436. <Bit>
  2437. <Name>UNLOCK</Name>
  2438. <Description>Bank 2 WPR first area A unlock</Description>
  2439. <BitOffset>0x1F</BitOffset>
  2440. <BitWidth>0x1</BitWidth>
  2441. <Access>RW</Access>
  2442. <Values>
  2443. <Val value="0x0">WRP2A start and end pages locked</Val>
  2444. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2445. </Values>
  2446. </Bit>
  2447. </AssignedBits>
  2448. </Field>
  2449. <Field>
  2450. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2451. <AssignedBits>
  2452. <Bit config="6">
  2453. <Name>WRP2B_PSTRT</Name>
  2454. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2455. <BitOffset>0x0</BitOffset>
  2456. <BitWidth>0x7</BitWidth>
  2457. <Access>RW</Access>
  2458. <Equation multiplier="0x4000" offset="0x08000000"/>
  2459. </Bit>
  2460. <Bit config="7">
  2461. <Name>WRP2B_PSTRT</Name>
  2462. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2463. <BitOffset>0x0</BitOffset>
  2464. <BitWidth>0x7</BitWidth>
  2465. <Access>RW</Access>
  2466. <Equation multiplier="0x2000" offset="0x08200000"/>
  2467. </Bit>
  2468. <Bit config="6">
  2469. <Name>WRP2B_PEND</Name>
  2470. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2471. <BitOffset>0x10</BitOffset>
  2472. <BitWidth>0x7</BitWidth>
  2473. <Access>RW</Access>
  2474. <Equation multiplier="0x4000" offset="0x08000000"/>
  2475. </Bit>
  2476. <Bit config="7">
  2477. <Name>WRP2B_PEND</Name>
  2478. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2479. <BitOffset>0x10</BitOffset>
  2480. <BitWidth>0x7</BitWidth>
  2481. <Access>RW</Access>
  2482. <Equation multiplier="0x2000" offset="0x08200000"/>
  2483. </Bit>
  2484. <Bit>
  2485. <Name>UNLOCK</Name>
  2486. <Description>Bank 2 WPR first area B unlock</Description>
  2487. <BitOffset>0x1F</BitOffset>
  2488. <BitWidth>0x1</BitWidth>
  2489. <Access>RW</Access>
  2490. <Values>
  2491. <Val value="0x0">WRP2B start and end pages locked</Val>
  2492. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2493. </Values>
  2494. </Bit>
  2495. </AssignedBits>
  2496. </Field>
  2497. </Category>
  2498. </Bank>
  2499. </Peripheral>
  2500. </Peripherals>
  2501. </Device>
  2502. </Root>