sdk-debuger-stlink/tools/Data_Base/STM32_Prog_DB_0x494.xml

<?xml version="1.0" encoding="UTF-8"?>
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
<Device>
		<DeviceID>0x494</DeviceID>
		<Vendor>STMicroelectronics</Vendor>
		<Type>MCU</Type>
		<CPU>Cortex-M0+/M4</CPU>
		<Name>STM32WB15xx</Name>
		<Series>STM32WB</Series>
		<Description>ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device</Description>
		<Configurations>
			<!-- JTAG_SWD Interface -->
			<Interface name="JTAG_SWD"/>
			<!-- Bootloader Interface -->
			<Interface name="Bootloader"/>
		</Configurations>
		<!-- Peripherals -->
		<Peripherals>
			<!-- Embedded SRAM -->
			<Peripheral>
				<Name>Embedded SRAM</Name>
				<Type>Storage</Type>
				<Description/>
				<ErasedValue>0x00</ErasedValue>
				<Access>RWE</Access>
				<!-- 12 KB SRAM1-->
				<Configuration>
					<Parameters address="0x20000000" name="SRAM" size="0x3000"/>
					<Description/>
					<Organization>Single</Organization>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x3000"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Embedded Flash -->
			<Peripheral>
				<Name>Embedded Flash</Name>
				<Type>Storage</Type>
				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
				<ErasedValue>0x00</ErasedValue>
				<Access>RWE</Access>
				<FlashSize address="0x1FFF75E0" default="0x50000"/>
				<!-- 320 KB Single Bank -->
				<Configuration>
					<Parameters address="0x08000000" name=" 320 Kbytes Embedded Flash" size="0x50000"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0xA0" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- OTP -->
			<Peripheral>
				<Name>OTP</Name>
				<Type>Storage</Type>
				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 1 KBytes -->
				<Configuration>
					<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="OTP">
						<Field>
							<Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Mirror Option Bytes -->
			<Peripheral>
				<Name>MirrorOptionBytes</Name>
				<Type>Storage</Type>
				<Description>Mirror Option Bytes contains the extra area.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 128 Bytes single bank -->
				<Configuration>
					<Parameters address="0x1FFF7800" name=" 128 Bytes Data MirrorOptionBytes" size="0x80"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="MirrorOptionBytes">
						<Field>
							<Parameters address="0x1FFF7800" name="MirrorOptionBytes" occurence="0x1" size="0x80"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Option Bytes -->
			<Peripheral> 
				<Name>Option Bytes</Name>
				<Type>Configuration</Type>
				<Description/>
				<Access>RW</Access>
				<Bank interface="JTAG_SWD">
				    <!-- Bank non secure -->
					<Parameters address="0x58004020" name="Bank 1" size="0x3C"/>
						<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x58004020" name="RDP" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters address="0x58004020" name="USER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x9</BitOffset>
									<BitWidth>0x3</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x58004020" name="USER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>nBOOT0</Name>
									<Description/>
									<BitOffset>0x1B</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">nBOOT0=0</Val>
										<Val value="0x1">nBOOT0=1</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from code area if BOOT0=0 otherwise embedded SRAM1</Val>
										<Val value="0x1">Boot from code area if BOOT0=0 otherwise system Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nSWBOOT0</Name>
									<Description/>
									<BitOffset>0x1A</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2RST</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2PE</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 parity check enable</Val>
										<Val value="0x1">SRAM2 parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Stop mode</Val>
										<Val value="0x1">No reset generated when entering the Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Standby mode</Val>
										<Val value="0x1">No reset generated when entering the Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRSTSHDW</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>WWDGSW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWGDSTDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDGSTOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDGSW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independent watchdog</Val>
										<Val value="0x1">Software independent watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>GPIO_MODE_PB11</Name>
									<Description>PB11 GPIO mode</Description>
									<BitOffset>0x1C</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">If RESET_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode, GPIO functionality is not available on PB11. If RESET_MODE_PB11 = 1: Reset Input only, a low level on the NRST pin generates system reset, internal RESET.</Val>
										<Val value="0x1">If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11.</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>RESET_MODE_PB11</Name>
									<Description>PB11 reset mode</Description>
									<BitOffset>0x16</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">If GPIO_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode. If GPIO_MODE_PB11 = 1: Standard GPIO pad functionality, only internal RESET possible.</Val>
										<Val value="0x1">If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode).</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IRH</Name>
									<Description>Internal reset holder enable bit</Description>
									<BitOffset>0xF</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin.</Val>
										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level.</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>ESE</Name>
						<Field>
							<Parameters address="0x58004020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>ESE</Name>
									<Description>System Security Enabled flag</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>R</Access>
									<Values>
										<Val value="0x0">Security disabled</Val>
										<Val value="0x1">Security enabled</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>				
					</Category>
					<Category>
						<Name>PCROP Protection</Name>
						<Field>
							<Parameters address="0x58004024" name="PCROP1ASR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_STRT</Name>
									<Description>Flash Area 1 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x58004028" name="PCROP1AER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_END</Name>
									<Description>Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x58004034" name="PCROP1BSR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_STRT</Name>
									<Description>Flash Area 2 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x58004038" name="PCROP1BER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_END</Name>
									<Description>Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection</Name>
						<Field>
							<Parameters address="0x5800402C" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the WRP first area.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the WRP first area.</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x58004030" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of WRP second area.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of WRP second area.</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="JTAG_SWD">
					<Parameters address="0x5800403C" name="Bank 2" size="0x4"/>
				    <Category>
					<Name>IPCCDBA-AA</Name>
						<Field>
							<Parameters address="0x5800403C" name="FLASH_IPCCBR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>IPCCDBA</Name>
									<Description>IPCC mailbox data buffer base address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0xE</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x1" offset="0x20010000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="JTAG_SWD">
				<Parameters address="0x58004080" name="Bank 3" size="0x8"/>
				<Category>
					<Name>Security Configuration Option bytes</Name>
						<Field>
							<Parameters address="0x58004080" name="FLASH_SFR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>SFSA</Name>
									<Description>Secure Flash Start Address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit> 
								<Bit>
									<Name>FSD</Name>
									<Description>Flash Security Disable</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">System and Flash secure</Val>
										<Val value="0x1">System and Flash non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>DDS</Name>
									<Description>Disable CPU2 Debug access</Description>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">CPU2 debug access enabled</Val>
										<Val value="0x1">CPU2 debug access disabled</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x58004084" name="FLASH_SRRVR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>C2OPT</Name>
									<Description>CPU2 boot reset vector memory selection</Description>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SBRV will address SRAM1 or SRAM2</Val>
										<Val value="0x1">SBRV will address Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>BRSD_B</Name>
									<Description>Backup SRAM2b security disable</Description>
									<BitOffset>0x1E</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2b is secure</Val>
										<Val value="0x1">SRAM2b is non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SBRSA_B</Name>
									<Description>SBRSA_B[1:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x2000BFFF"/>
								</Bit>
								<Bit>
									<Name>BRSD_A</Name>
									<Description>Backup SRAM2a security disable</Description>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2a is secure</Val>
										<Val value="0x1">SRAM2a is non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SBRSA_A</Name>
									<Description>SBRSA_A[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x5</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x2000B000"/>
								</Bit>
								<Bit>
									<Name>SBRV</Name>
									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x11</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>		
					</Category>	
				</Bank>
				<Bank interface="Bootloader">
					<Parameters address="0x1FFF7800" name="Bank 1" size="0x80"/>
					<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="RDP" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="USER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x9</BitOffset>
									<BitWidth>0x3</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="USER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>nBOOT0</Name>
									<Description/>
									<BitOffset>0x1B</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">nBOOT0=0</Val>
										<Val value="0x1">nBOOT0=1</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from code area if BOOT0=0 otherwise embedded SRAM1</Val>
										<Val value="0x1">Boot from code area if BOOT0=0 otherwise  system Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nSWBOOT0</Name>
									<Description/>
									<BitOffset>0x1A</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2RST</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2PE</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 parity check enable</Val>
										<Val value="0x1">SRAM2 parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Stop mode</Val>
										<Val value="0x1">No reset generated when entering the Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Standby mode</Val>
										<Val value="0x1">No reset generated when entering the Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRSTSHDW</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>WWDGSW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWGDSTDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDGSTOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDGSW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independent watchdog</Val>
										<Val value="0x1">Software independent watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>GPIO_MODE_PB11</Name>
									<Description>PB11 GPIO mode</Description>
									<BitOffset>0x1C</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">If RESET_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode, GPIO functionality is not available on PB11. If RESET_MODE_PB11 = 1: Reset Input only, a low level on the NRST pin generates system reset, internal RESET.</Val>
										<Val value="0x1">If RESET_MODE_PB11 = 0: Standard GPIO pad functionality, Only internal RESET possible. If RESET_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode), GPIO functionality is not available on PB11.</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>RESET_MODE_PB11</Name>
									<Description>PB11 reset mode</Description>
									<BitOffset>0x16</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">If GPIO_MODE_PB11 = 0: Bidirectional reset, NRST pin configured in reset input/output mode. If GPIO_MODE_PB11 = 1: Standard GPIO pad functionality, only internal RESET possible.</Val>
										<Val value="0x1">If GPIO_MODE_PB11 = 0: Reset input only, a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin. If GPIO_MODE_PB11 = 1: Bidirectional reset, NRST pin configured in reset input/output mode (default mode).</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IRH</Name>
									<Description>Internal reset holder enable bit</Description>
									<BitOffset>0xF</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin.</Val>
										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level.</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7868" name="FLASH_IPCCBR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>IPCCDBA</Name>
									<Description>IPCC mailbox data buffer base address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0xE</BitWidth>
									<Access>RW</Access>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Security Configuration</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>ESE</Name>
									<Description>System Security Enabled flag</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>R</Access>
									<Values>
										<Val value="0x0">Security disabled</Val>
										<Val value="0x1">Security enabled</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7870" name="FLASH_SFR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>SFSA</Name>
									<Description>Secure Flash Start Address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>FSD</Name>
									<Description>Flash Security Disable</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">System and Flash secure</Val>
										<Val value="0x1">System and Flash non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>DDS</Name>
									<Description>Disable CPU2 Debug access</Description>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">CPU2 debug access enabled</Val>
										<Val value="0x1">CPU2 debug access disabled</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7878" name="FLASH_SRRVR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>C2OPT</Name>
									<Description>CPU2 boot reset vector memory selection</Description>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SBRV will address SRAM1 or SRAM2</Val>
										<Val value="0x1">SBRV will address Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>BRSD_B</Name>
									<Description>Backup SRAM2b security disable</Description>
									<BitOffset>0x1E</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2b is secure</Val>
										<Val value="0x1">SRAM2b is non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SBRSA_B</Name>
									<Description>SBRSA_B[1:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>BRSD_A</Name>
									<Description>Backup SRAM2a security disable</Description>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2a is secure</Val>
										<Val value="0x1">SRAM2a is non-secure</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SBRSA_A</Name>
									<Description>SBRSA_A[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x5</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>SBRV</Name>
									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x11</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>PCROP Protection</Name>
						<Field>
							<Parameters address="0x1FFF7808" name="PCROP1ASR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_STRT</Name>
									<Description>Flash Area 1 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7810" name="PCROP1AER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_END</Name>
									<Description>Flash Area 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7828" name="PCROP1BSR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_STRT</Name>
									<Description>Flash Area 2 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7830" name="PCROP1BER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_END</Name>
									<Description>Flash Area 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x400" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection</Name>
						<Field>
							<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x1000" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of the WRP second area.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of the WRP second area.</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x0800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
			</Peripheral>
		</Peripherals>
	</Device>
</Root>