sdk-debuger-stlink/tools/Data_Base/STM32_Prog_DB_0x460.xml

<?xml version="1.0" encoding="UTF-8"?>
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
<Device>
		<DeviceID>0x460</DeviceID>
		<Vendor>STMicroelectronics</Vendor>
		<Type>MCU</Type>
		<CPU>Cortex-M0+</CPU>
		<Name>STM32G07x/STM32G08x</Name>
		<Series>STM32G0</Series>
		<Description>ARM 32-bit Cortex-M0+ based device</Description>
		<Configurations>
			<!-- JTAG_SWD Interface -->
			<Interface name="JTAG_SWD">
				<Configuration	number="0x0">
					<ValueLine> <ReadRegister address="0x1FFF77DD" mask="0xFF" value="0xFF"/> </ValueLine>
				</Configuration>
				<Configuration	number="0x1">
					<ValueLine> <ReadRegister address="0x1FFF77DD"	mask="0xFF"	value="0x30"/> </ValueLine>
				</Configuration>
				<Configuration	number="0x2">
					<ValueLine> <ReadRegister address="0x1FFF77DD" mask="0xFF" value="0x31"/> </ValueLine>
				</Configuration>
			</Interface>
			<!-- Bootloader Interface -->
			<Interface name="Bootloader">
			<Configurations>
				<Configuration	number="0x0">
					<ValueLine> <ReadRegister address="0x1FFF77DD" mask="0xFF" value="0xFF"/> </ValueLine>
				</Configuration>
				<Configuration	number="0x1">
					<ValueLine> <ReadRegister address="0x1FFF77DD"	mask="0xFF"	value="0x30"/> </ValueLine>
				</Configuration>
				<Configuration	number="0x2">
					<ValueLine> <ReadRegister address="0x1FFF77DD" mask="0xFF" value="0x31"/> </ValueLine>
				</Configuration>
				</Configurations>
			</Interface>
		</Configurations>
		<!-- Peripherals -->
		<Peripherals>
			<!-- Embedded SRAM -->
			<Peripheral>
				<Name>Embedded SRAM</Name>
				<Type>Storage</Type>
				<Description/>
				<ErasedValue>0x00</ErasedValue>
				<Access>RWE</Access>
				<!-- 96 KB -->
				<Configuration>
					<Parameters address="0x20000000" name="SRAM" size="0x8000"/>
					<Description/>
					<Organization>Single</Organization>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Embedded Flash -->
			<Peripheral>
				<Name>Embedded Flash</Name>
				<Type>Storage</Type>
				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RWE</Access>
				<FlashSize address="0x1FFF75E0" default="0x20000"/>
				<BootloaderVersion address="0x1FFF6FFE"/>
				<DBGMCU_CR address="0x40015804" mask="0x007"/>
				<DBGMCU_APB1_FZ address="0x40015808" mask="0x1800"/>
				<RCC_APB2ENR address="0x4002103C" mask="0x08000000"/>
				<!--<CR address="0x40002C04" mask="0x000001FF"/>-->
				<!-- Single Bank -->
				<Configuration>
					<Parameters address="0x08000000" name=" 128 KB Embedded Flash" size="0x20000"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- OTP -->
			<Peripheral>
				<Name>OTP</Name>
				<Type>Storage</Type>
				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 1 KBytes single bank -->
				<Configuration>
					<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="OTP">
						<Field>
							<Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Mirror Option Bytes -->
			<Peripheral>
				<Name>MirrorOptionBytes</Name>
				<Type>Storage</Type>
				<Description>Mirror Option Bytes contains the extra area.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 44 Bytes single bank -->
				<Configuration>
					<Parameters address="0x1FFF7800" name=" 56 Bytes Data MirrorOptionBytes" size="0x38"/>
					<Description/>
					<Organization>Dual</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x1FFF7800" name="Bank1" occurence="0x1" size="0x34"/>
						</Field>
					</Bank>
					<Bank name="Bank 2">
						<Field>
							<Parameters address="0x1FFF7870" name="Bank2" occurence="0x1" size="0x4"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Option Bytes -->
			<Peripheral>
				<Name>Option Bytes</Name>
				<Type>Configuration</Type>
				<Description/>
				<Access>RW</Access>
				<Bank interface="JTAG_SWD">
					<Parameters address="0x40022020" name="Bank 1" size="0x70"/>
					<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
							<AssignedBits>
								<Bit number="0x0,0x2">
									<Name>BOR_EN</Name>
									<Description/>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
									</Values>
								</Bit>
								<Bit number="0x0,0x2">
									<Name>BORR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x9</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
									</Values>
								</Bit>
								<Bit number="0x0,0x2">
									<Name>BORF_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0xB</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Stop mode</Val>
										<Val value="0x1">No reset generated when entering Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Standby mode</Val>
										<Val value="0x1">No reset generated when entering Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_SHDW</Name>
									<Description/>
									<BitOffset>0xF</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_SW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independant watchdog</Val>
										<Val value="0x1">Software independant watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
										<Val value="0x1">IWDG counter active in stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
										<Val value="0x1">IWDG counter active in standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>WWDG_SW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>RAM_PARITY_CHECK</Name>
									<Description/>
									<BitOffset>0x16</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM parity check enable</Val>
										<Val value="0x1">SRAM parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT_SEL</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT0</Name>
									<Description/>
									<BitOffset>0x1A</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">nBOOT0=0</Val>
										<Val value="0x1">nBOOT0=1</Val>
									</Values>
								</Bit>
								<Bit number="0x0,0x2">
									<Name>NRST_MODE</Name>
									<Description/>
									<BitOffset>0x1B</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reserved</Val>
										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
									</Values>
								</Bit>	
								<Bit number="0x0,0x2">
									<Name>IRHEN</Name>
									<Description>Internal reset holder enable bit</Description>
									<BitOffset>0x1D</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
									</Values>
								</Bit>									
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>PCROP Protection</Name>
						<Field>
							<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_STRT</Name>
									<Description>Flash Area A PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_END</Name>
									<Description>Flash Area A PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000200"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022034" name="FLASH_PCROP1BSR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_STRT</Name>
									<Description>Flash Area B PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022038" name="FLASH_PCROP1BER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1B_END</Name>
									<Description>Flash Area B PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000200"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection</Name>
						<Field>
							<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the Bank 1 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of the Bank 1 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>FLASH security</Name>
						<Field>
							<Parameters address="0x40022080" name="FLASH_SECR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOOT_LOCK</Name>
									<Description>used to force boot from user area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
										<Val value="0x1">Boot forced from Main Flash memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SEC_SIZE</Name>
									<Description>Securable memory area size</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x7</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="Bootloader">
					<Parameters address="0x1FFF7800" name="Bank 1" size="0x34"/>
					<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit number="0x0,0x2">
									<Name>BOR_EN</Name>
									<Description/>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
									</Values>
								</Bit>
								<Bit number="0x0,0x2">
									<Name>BORR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x9</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
									</Values>
								</Bit>
								<Bit number="0x0,0x2">
									<Name>BORF_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0xB</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Stop mode</Val>
										<Val value="0x1">No reset generated when entering Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Standby mode</Val>
										<Val value="0x1">No reset generated when entering Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_SHDW</Name>
									<Description/>
									<BitOffset>0xF</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_SW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independant watchdog</Val>
										<Val value="0x1">Software independant watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
										<Val value="0x1">IWDG counter active in stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
										<Val value="0x1">IWDG counter active in standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>WWDG_SW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>RAM_PARITY_CHECK</Name>
									<Description/>
									<BitOffset>0x16</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM parity check enable</Val>
										<Val value="0x1">SRAM parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT_SEL</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1</Val>
										<Val value="0x1">Boot from Flash if BOOT0 = 1, otherwise system memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT0</Name>
									<Description/>
									<BitOffset>0x1A</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">nBOOT0=0</Val>
										<Val value="0x1">nBOOT0=1</Val>
									</Values>
								</Bit>	
                                <Bit number="0x0,0x2">
									<Name>NRST_MODE</Name>
									<Description/>
									<BitOffset>0x1B</BitOffset>
									<BitWidth>0x2</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reserved</Val>
										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
									</Values>
								</Bit>									
								<Bit number="0x0,0x2">
									<Name>IRHEN</Name>
									<Description>Internal reset holder enable bit</Description>
									<BitOffset>0x1D</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
									</Values>
								</Bit>	
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>PCROP Protection</Name>
						<Field>
							<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_STRT</Name>
									<Description>Flash Bank 1 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1A_END</Name>
									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x9</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x200" offset="0x08000200"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection</Name>
						<Field>
							<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the Bank 1 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of the Bank 1 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x6</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="Bootloader">
					<Parameters address="0x1FFF7870" name="Bank 2" size="0x4"/>
					<Category>
						<Name>FLASH security</Name>
						<Field>
							<Parameters address="0x1FFF7870" name="FLASH_SECR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOOT_LOCK</Name>
									<Description>used to force boot from user area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
										<Val value="0x1">Boot forced from Main Flash memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SEC_SIZE</Name>
									<Description>Securable memory area size</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x7</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
			</Peripheral>
		</Peripherals>
	</Device>
</Root>