STM32_Prog_DB_0x464.xml 23 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x464</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M4</CPU>
  8. <Name>STM32L41x</Name>
  9. <Series>STM32L4</Series>
  10. <Description>ARM 32-bit Cortex-M4 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD"/>
  14. <!-- Bootloader Interface -->
  15. <Interface name="Bootloader"/>
  16. </Configurations>
  17. <!-- Peripherals -->
  18. <Peripherals>
  19. <!-- Embedded SRAM -->
  20. <Peripheral>
  21. <Name>Embedded SRAM</Name>
  22. <Type>Storage</Type>
  23. <Description/>
  24. <ErasedValue>0x00</ErasedValue>
  25. <Access>RWE</Access>
  26. <!-- 128 KB -->
  27. <Configuration>
  28. <Parameters address="0x20000000" name="SRAM" size="0xA000"/>
  29. <Description/>
  30. <Organization>Single</Organization>
  31. <Bank name="Bank 1">
  32. <Field>
  33. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0xA000"/>
  34. </Field>
  35. </Bank>
  36. </Configuration>
  37. </Peripheral>
  38. <!-- Embedded Flash -->
  39. <Peripheral>
  40. <Name>Embedded Flash</Name>
  41. <Type>Storage</Type>
  42. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  43. <ErasedValue>0xFF</ErasedValue>
  44. <Access>RWE</Access>
  45. <FlashSize address="0x1FFF75E0" default="0x80000"/>
  46. <DBGMCU_CR address="0xE0042004" mask="0x007"/>
  47. <DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
  48. <!-- 512KB single Bank -->
  49. <Configuration>
  50. <Parameters address="0x08000000" name=" 128 Kbytes Embedded Flash" size="0x20000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Allignement>0x8</Allignement>
  54. <Bank name="Bank 1">
  55. <Field>
  56. <Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
  57. </Field>
  58. </Bank>
  59. </Configuration>
  60. </Peripheral>
  61. <!-- OTP -->
  62. <Peripheral>
  63. <Name>OTP</Name>
  64. <Type>Storage</Type>
  65. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  66. <ErasedValue>0xFF</ErasedValue>
  67. <Access>RW</Access>
  68. <!-- 1 KBytes single bank -->
  69. <Configuration>
  70. <Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
  71. <Description/>
  72. <Organization>Single</Organization>
  73. <Allignement>0x4</Allignement>
  74. <Bank name="OTP">
  75. <Field>
  76. <Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
  77. </Field>
  78. </Bank>
  79. </Configuration>
  80. </Peripheral>
  81. <!-- Mirror Option Bytes -->
  82. <Peripheral>
  83. <Name>MirrorOptionBytes</Name>
  84. <Type>Storage</Type>
  85. <Description>Mirror Option Bytes contains the extra area.</Description>
  86. <ErasedValue>0xFF</ErasedValue>
  87. <Access>RW</Access>
  88. <!-- 36 Bytes single bank -->
  89. <Configuration>
  90. <Parameters address="0x1FFF7800" name=" 36 Bytes Data MirrorOptionBytes" size="0x24"/>
  91. <Description/>
  92. <Organization>Single</Organization>
  93. <Allignement>0x4</Allignement>
  94. <Bank name="MirrorOptionBytes">
  95. <Field>
  96. <Parameters address="0x1FFF7800" name="MirrorOptionBytes" occurence="0x1" size="0x24"/>
  97. </Field>
  98. </Bank>
  99. </Configuration>
  100. </Peripheral>
  101. <!-- Option Bytes -->
  102. <Peripheral>
  103. <Name>Option Bytes</Name>
  104. <Type>Configuration</Type>
  105. <Description/>
  106. <Access>RW</Access>
  107. <Bank interface="JTAG_SWD">
  108. <Parameters address="0x40022020" name="Bank 1" size="0x14"/>
  109. <Category>
  110. <Name>Read Out Protection</Name>
  111. <Field>
  112. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  113. <AssignedBits>
  114. <Bit>
  115. <Name>RDP</Name>
  116. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  117. <BitOffset>0x0</BitOffset>
  118. <BitWidth>0x8</BitWidth>
  119. <Access>RW</Access>
  120. <Values>
  121. <Val value="0xAA">Level 0, no protection</Val>
  122. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  123. <Val value="0xCC">Level 2, chip protection</Val>
  124. </Values>
  125. </Bit>
  126. </AssignedBits>
  127. </Field>
  128. </Category>
  129. <Category>
  130. <Name>BOR Level</Name>
  131. <Field>
  132. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  133. <AssignedBits>
  134. <Bit>
  135. <Name>BOR_LEV</Name>
  136. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  137. <BitOffset>0x8</BitOffset>
  138. <BitWidth>0x3</BitWidth>
  139. <Access>RW</Access>
  140. <Values>
  141. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  142. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  143. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  144. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  145. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  146. </Values>
  147. </Bit>
  148. </AssignedBits>
  149. </Field>
  150. </Category>
  151. <Category>
  152. <Name>User Configuration</Name>
  153. <Field>
  154. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  155. <AssignedBits>
  156. <Bit>
  157. <Name>nRST_STOP</Name>
  158. <Description/>
  159. <BitOffset>0xC</BitOffset>
  160. <BitWidth>0x1</BitWidth>
  161. <Access>RW</Access>
  162. <Values>
  163. <Val value="0x0">Reset generated when entering Stop mode</Val>
  164. <Val value="0x1">No reset generated when entering Stop mode</Val>
  165. </Values>
  166. </Bit>
  167. <Bit>
  168. <Name>nRST_STDBY</Name>
  169. <Description/>
  170. <BitOffset>0xD</BitOffset>
  171. <BitWidth>0x1</BitWidth>
  172. <Access>RW</Access>
  173. <Values>
  174. <Val value="0x0">Reset generated when entering Standby mode</Val>
  175. <Val value="0x1">No reset generated when entering Standby mode</Val>
  176. </Values>
  177. </Bit>
  178. <Bit>
  179. <Name>nRST_SHDW</Name>
  180. <Description/>
  181. <BitOffset>0xE</BitOffset>
  182. <BitWidth>0x1</BitWidth>
  183. <Access>RW</Access>
  184. <Values>
  185. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  186. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  187. </Values>
  188. </Bit>
  189. <Bit>
  190. <Name>IWDG_SW</Name>
  191. <Description/>
  192. <BitOffset>0x10</BitOffset>
  193. <BitWidth>0x1</BitWidth>
  194. <Access>RW</Access>
  195. <Values>
  196. <Val value="0x0">Hardware independant watchdog</Val>
  197. <Val value="0x1">Software independant watchdog</Val>
  198. </Values>
  199. </Bit>
  200. <Bit>
  201. <Name>IWDG_STOP</Name>
  202. <Description/>
  203. <BitOffset>0x11</BitOffset>
  204. <BitWidth>0x1</BitWidth>
  205. <Access>RW</Access>
  206. <Values>
  207. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  208. <Val value="0x1">IWDG counter active in stop mode</Val>
  209. </Values>
  210. </Bit>
  211. <Bit>
  212. <Name>IWDG_STDBY</Name>
  213. <Description/>
  214. <BitOffset>0x12</BitOffset>
  215. <BitWidth>0x1</BitWidth>
  216. <Access>RW</Access>
  217. <Values>
  218. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  219. <Val value="0x1">IWDG counter active in standby mode</Val>
  220. </Values>
  221. </Bit>
  222. <Bit>
  223. <Name>WWDG_SW</Name>
  224. <Description/>
  225. <BitOffset>0x13</BitOffset>
  226. <BitWidth>0x1</BitWidth>
  227. <Access>RW</Access>
  228. <Values>
  229. <Val value="0x0">Hardware window watchdog</Val>
  230. <Val value="0x1">Software window watchdog</Val>
  231. </Values>
  232. </Bit>
  233. <Bit>
  234. <Name>nBOOT1</Name>
  235. <Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
  236. <BitOffset>0x17</BitOffset>
  237. <BitWidth>0x1</BitWidth>
  238. <Access>RW</Access>
  239. <Values>
  240. <Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
  241. <Val value="0x1">Boot from system memory when BOOT0=1</Val>
  242. </Values>
  243. </Bit>
  244. <Bit>
  245. <Name>SRAM2_PE</Name>
  246. <Description/>
  247. <BitOffset>0x18</BitOffset>
  248. <BitWidth>0x1</BitWidth>
  249. <Access>RW</Access>
  250. <Values>
  251. <Val value="0x0">SRAM2 parity check enable</Val>
  252. <Val value="0x1">SRAM2 parity check disable</Val>
  253. </Values>
  254. </Bit>
  255. <Bit>
  256. <Name>SRAM2_RST</Name>
  257. <Description/>
  258. <BitOffset>0x19</BitOffset>
  259. <BitWidth>0x1</BitWidth>
  260. <Access>RW</Access>
  261. <Values>
  262. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  263. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  264. </Values>
  265. </Bit>
  266. <Bit>
  267. <Name>nSWBOOT0</Name>
  268. <Description/>
  269. <BitOffset>0x1A</BitOffset>
  270. <BitWidth>0x1</BitWidth>
  271. <Access>RW</Access>
  272. <Values>
  273. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  274. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  275. </Values>
  276. </Bit>
  277. <Bit>
  278. <Name>nBOOT0</Name>
  279. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  280. <BitOffset>0x1B</BitOffset>
  281. <BitWidth>0x1</BitWidth>
  282. <Access>RW</Access>
  283. <Values>
  284. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  285. <Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
  286. </Values>
  287. </Bit>
  288. </AssignedBits>
  289. </Field>
  290. </Category>
  291. <Category>
  292. <Name>PCROP Protection</Name>
  293. <Field>
  294. <Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
  295. <AssignedBits>
  296. <Bit>
  297. <Name>PCROP1_STRT</Name>
  298. <Description>Flash Bank 1 PCROP start address</Description>
  299. <BitOffset>0x0</BitOffset>
  300. <BitWidth>0x10</BitWidth>
  301. <Access>RW</Access>
  302. <Equation multiplier="0x8" offset="0x08000000"/>
  303. </Bit>
  304. </AssignedBits>
  305. </Field>
  306. <Field>
  307. <Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
  308. <AssignedBits>
  309. <Bit>
  310. <Name>PCROP1_END</Name>
  311. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  312. <BitOffset>0x0</BitOffset>
  313. <BitWidth>0x10</BitWidth>
  314. <Access>RW</Access>
  315. <Equation multiplier="0x8" offset="0x08000000"/>
  316. </Bit>
  317. <Bit>
  318. <Name>PCROP_RDP</Name>
  319. <Description/>
  320. <BitOffset>0x1F</BitOffset>
  321. <BitWidth>0x1</BitWidth>
  322. <Access>RW</Access>
  323. <Values>
  324. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  325. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  326. </Values>
  327. </Bit>
  328. </AssignedBits>
  329. </Field>
  330. </Category>
  331. <Category>
  332. <Name>Write Protection</Name>
  333. <Field>
  334. <Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
  335. <AssignedBits>
  336. <Bit>
  337. <Name>WRP1A_STRT</Name>
  338. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  339. <BitOffset>0x0</BitOffset>
  340. <BitWidth>0x6</BitWidth>
  341. <Access>RW</Access>
  342. <Equation multiplier="0x800" offset="0x08000000"/>
  343. </Bit>
  344. <Bit>
  345. <Name>WRP1A_END</Name>
  346. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  347. <BitOffset>0x10</BitOffset>
  348. <BitWidth>0x6</BitWidth>
  349. <Access>RW</Access>
  350. <Equation multiplier="0x800" offset="0x08000000"/>
  351. </Bit>
  352. </AssignedBits>
  353. </Field>
  354. <Field>
  355. <Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
  356. <AssignedBits>
  357. <Bit>
  358. <Name>WRP1B_STRT</Name>
  359. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  360. <BitOffset>0x0</BitOffset>
  361. <BitWidth>0x6</BitWidth>
  362. <Access>RW</Access>
  363. <Equation multiplier="0x800" offset="0x08000000"/>
  364. </Bit>
  365. <Bit>
  366. <Name>WRP1B_END</Name>
  367. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  368. <BitOffset>0x10</BitOffset>
  369. <BitWidth>0x6</BitWidth>
  370. <Access>RW</Access>
  371. <Equation multiplier="0x800" offset="0x08000000"/>
  372. </Bit>
  373. </AssignedBits>
  374. </Field>
  375. </Category>
  376. </Bank>
  377. <Bank interface="Bootloader">
  378. <Parameters address="0x1FFF7800" name="Bank 1" size="0x24"/>
  379. <Category>
  380. <Name>Read Out Protection</Name>
  381. <Field>
  382. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  383. <AssignedBits>
  384. <Bit>
  385. <Name>RDP</Name>
  386. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  387. <BitOffset>0x0</BitOffset>
  388. <BitWidth>0x8</BitWidth>
  389. <Access>RW</Access>
  390. <Values>
  391. <Val value="0xAA">Level 0, no protection</Val>
  392. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  393. <Val value="0xCC">Level 2, chip protection</Val>
  394. </Values>
  395. </Bit>
  396. </AssignedBits>
  397. </Field>
  398. </Category>
  399. <Category>
  400. <Name>BOR Level</Name>
  401. <Field>
  402. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  403. <AssignedBits>
  404. <Bit>
  405. <Name>BOR_LEV</Name>
  406. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  407. <BitOffset>0x8</BitOffset>
  408. <BitWidth>0x3</BitWidth>
  409. <Access>RW</Access>
  410. <Values>
  411. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  412. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  413. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  414. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  415. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  416. </Values>
  417. </Bit>
  418. </AssignedBits>
  419. </Field>
  420. </Category>
  421. <Category>
  422. <Name>User Configuration</Name>
  423. <Field>
  424. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  425. <AssignedBits>
  426. <Bit>
  427. <Name>IWDG_STOP</Name>
  428. <Description/>
  429. <BitOffset>0x11</BitOffset>
  430. <BitWidth>0x1</BitWidth>
  431. <Access>RW</Access>
  432. <Values>
  433. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  434. <Val value="0x1">IWDG counter active in stop mode</Val>
  435. </Values>
  436. </Bit>
  437. <Bit>
  438. <Name>IWDG_STDBY</Name>
  439. <Description/>
  440. <BitOffset>0x12</BitOffset>
  441. <BitWidth>0x1</BitWidth>
  442. <Access>RW</Access>
  443. <Values>
  444. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  445. <Val value="0x1">IWDG counter active in standby mode</Val>
  446. </Values>
  447. </Bit>
  448. </AssignedBits>
  449. </Field>
  450. <Field>
  451. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  452. <AssignedBits>
  453. <Bit>
  454. <Name>WWDG_SW</Name>
  455. <Description/>
  456. <BitOffset>0x13</BitOffset>
  457. <BitWidth>0x1</BitWidth>
  458. <Access>RW</Access>
  459. <Values>
  460. <Val value="0x0">Hardware window watchdog</Val>
  461. <Val value="0x1">Software window watchdog</Val>
  462. </Values>
  463. </Bit>
  464. <Bit>
  465. <Name>IWDG_SW</Name>
  466. <Description/>
  467. <BitOffset>0x10</BitOffset>
  468. <BitWidth>0x1</BitWidth>
  469. <Access>RW</Access>
  470. <Values>
  471. <Val value="0x0">Hardware independant watchdog</Val>
  472. <Val value="0x1">Software independant watchdog</Val>
  473. </Values>
  474. </Bit>
  475. <Bit>
  476. <Name>nRST_STOP</Name>
  477. <Description/>
  478. <BitOffset>0xC</BitOffset>
  479. <BitWidth>0x1</BitWidth>
  480. <Access>RW</Access>
  481. <Values>
  482. <Val value="0x0">Reset generated when entering Stop mode</Val>
  483. <Val value="0x1">No reset generated</Val>
  484. </Values>
  485. </Bit>
  486. <Bit>
  487. <Name>nRST_STDBY</Name>
  488. <Description/>
  489. <BitOffset>0xD</BitOffset>
  490. <BitWidth>0x1</BitWidth>
  491. <Access>RW</Access>
  492. <Values>
  493. <Val value="0x0">Reset generated when entering Standby mode</Val>
  494. <Val value="0x1">No reset generated</Val>
  495. </Values>
  496. </Bit>
  497. <Bit>
  498. <Name>nRST_SHDW</Name>
  499. <Description/>
  500. <BitOffset>0xE</BitOffset>
  501. <BitWidth>0x1</BitWidth>
  502. <Access>RW</Access>
  503. <Values>
  504. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  505. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  506. </Values>
  507. </Bit>
  508. <Bit>
  509. <Name>nBOOT1</Name>
  510. <Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
  511. <BitOffset>0x17</BitOffset>
  512. <BitWidth>0x1</BitWidth>
  513. <Access>RW</Access>
  514. <Values>
  515. <Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
  516. <Val value="0x1">Boot from system memory when BOOT0=1</Val>
  517. </Values>
  518. </Bit>
  519. <Bit>
  520. <Name>SRAM2_PE</Name>
  521. <Description/>
  522. <BitOffset>0x18</BitOffset>
  523. <BitWidth>0x1</BitWidth>
  524. <Access>RW</Access>
  525. <Values>
  526. <Val value="0x0">SRAM2 parity check enable</Val>
  527. <Val value="0x1">SRAM2 parity check disable</Val>
  528. </Values>
  529. </Bit>
  530. <Bit>
  531. <Name>SRAM2_RST</Name>
  532. <Description/>
  533. <BitOffset>0x19</BitOffset>
  534. <BitWidth>0x1</BitWidth>
  535. <Access>RW</Access>
  536. <Values>
  537. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  538. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  539. </Values>
  540. </Bit>
  541. <Bit>
  542. <Name>nSWBOOT0</Name>
  543. <Description/>
  544. <BitOffset>0x1A</BitOffset>
  545. <BitWidth>0x1</BitWidth>
  546. <Access>RW</Access>
  547. <Values>
  548. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  549. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  550. </Values>
  551. </Bit>
  552. <Bit>
  553. <Name>nBOOT0</Name>
  554. <Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
  555. <BitOffset>0x1B</BitOffset>
  556. <BitWidth>0x1</BitWidth>
  557. <Access>RW</Access>
  558. <Values>
  559. <Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
  560. <Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
  561. </Values>
  562. </Bit>
  563. </AssignedBits>
  564. </Field>
  565. </Category>
  566. <Category>
  567. <Name>PCROP Protection</Name>
  568. <Field>
  569. <Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
  570. <AssignedBits>
  571. <Bit>
  572. <Name>PCROP1_STRT</Name>
  573. <Description>Flash Bank 1 PCROP start address</Description>
  574. <BitOffset>0x0</BitOffset>
  575. <BitWidth>0x10</BitWidth>
  576. <Access>RW</Access>
  577. <Equation multiplier="0x8" offset="0x08000000"/>
  578. </Bit>
  579. </AssignedBits>
  580. </Field>
  581. <Field>
  582. <Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
  583. <AssignedBits>
  584. <Bit>
  585. <Name>PCROP1_END</Name>
  586. <Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
  587. <BitOffset>0x0</BitOffset>
  588. <BitWidth>0x10</BitWidth>
  589. <Access>RW</Access>
  590. <Equation multiplier="0x8" offset="0x08000000"/>
  591. </Bit>
  592. <Bit>
  593. <Name>PCROP_RDP</Name>
  594. <Description/>
  595. <BitOffset>0x1F</BitOffset>
  596. <BitWidth>0x1</BitWidth>
  597. <Access>RW</Access>
  598. <Values>
  599. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  600. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  601. </Values>
  602. </Bit>
  603. </AssignedBits>
  604. </Field>
  605. </Category>
  606. <Category>
  607. <Name>Write Protection</Name>
  608. <Field>
  609. <Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
  610. <AssignedBits>
  611. <Bit>
  612. <Name>WRP1A_STRT</Name>
  613. <Description>The address of the first page of the Bank 1 WRP first area</Description>
  614. <BitOffset>0x0</BitOffset>
  615. <BitWidth>0x6</BitWidth>
  616. <Access>RW</Access>
  617. <Equation multiplier="0x800" offset="0x08000000"/>
  618. </Bit>
  619. <Bit>
  620. <Name>WRP1A_END</Name>
  621. <Description>The address of the last page of the Bank 1 WRP first area</Description>
  622. <BitOffset>0x10</BitOffset>
  623. <BitWidth>0x6</BitWidth>
  624. <Access>RW</Access>
  625. <Equation multiplier="0x800" offset="0x08000000"/>
  626. </Bit>
  627. </AssignedBits>
  628. </Field>
  629. <Field>
  630. <Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
  631. <AssignedBits>
  632. <Bit>
  633. <Name>WRP1B_STRT</Name>
  634. <Description>The address of the first page of the Bank 1 WRP second area</Description>
  635. <BitOffset>0x0</BitOffset>
  636. <BitWidth>0x6</BitWidth>
  637. <Access>RW</Access>
  638. <Equation multiplier="0x800" offset="0x08000000"/>
  639. </Bit>
  640. <Bit>
  641. <Name>WRP1B_END</Name>
  642. <Description>The address of the last page of the Bank 1 WRP second area</Description>
  643. <BitOffset>0x10</BitOffset>
  644. <BitWidth>0x6</BitWidth>
  645. <Access>RW</Access>
  646. <Equation multiplier="0x800" offset="0x08000000"/>
  647. </Bit>
  648. </AssignedBits>
  649. </Field>
  650. </Category>
  651. </Bank>
  652. </Peripheral>
  653. </Peripherals>
  654. </Device>
  655. </Root>