STM32_Prog_DB_0x482.xml 102 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x482</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32U575/STM32U585</Name>
  9. <Series>STM32U5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- Single Bank non secure -->
  15. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  16. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  17. </Configuration>
  18. <Configuration number="0x1"> <!-- Dual Bank non secure -->
  19. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  20. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  21. </Configuration>
  22. <Configuration number="0x2"> <!-- Single Bank secure + RDP=0xAA -->
  23. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  24. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  25. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  26. </Configuration>
  27. <Configuration number="0x3"> <!-- Dual Bank secure + RDP=0xAA -->
  28. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  29. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  30. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  31. </Configuration>
  32. <Configuration number="0xA"> <!-- Single Bank + RDP=0x55 -->
  33. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  34. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x00000055"/> </RDP>
  35. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  36. </Configuration>
  37. <Configuration number="0xB"> <!-- Dual Bank + RDP=0x55 -->
  38. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  39. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x00000055"/> </RDP>
  40. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  41. </Configuration>
  42. <Configuration number="0x4"> <!-- Single Bank secure -->
  43. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x0"/> </DBANK>
  44. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  45. </Configuration>
  46. <Configuration number="0x5"> <!-- Dual Bank secure -->
  47. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x00200000" value="0x00200000"/> </DBANK>
  48. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  49. </Configuration>
  50. </Interface>
  51. <!-- Bootloader Interface -->
  52. <Interface name="Bootloader">
  53. <Configuration number="0x6"> <!-- Single Bank Secure-->
  54. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  55. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  56. </Configuration>
  57. <Configuration number="0x7"> <!-- Dual Bank Secure-->
  58. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  59. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  60. </Configuration>
  61. <Configuration number="0x8"> <!-- Single Bank non Secure-->
  62. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  63. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  64. </Configuration>
  65. <Configuration number="0x9"> <!-- Dual Bank non Secure-->
  66. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  67. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  68. </Configuration>
  69. </Interface>
  70. </Configurations>
  71. <!-- Peripherals -->
  72. <Peripherals>
  73. <!-- Embedded SRAM -->
  74. <Peripheral>
  75. <Name>Embedded SRAM</Name>
  76. <Type>Storage</Type>
  77. <Description/>
  78. <ErasedValue>0xFF</ErasedValue>
  79. <Access>RWE</Access>
  80. <!-- 96 KB -->
  81. <Configuration config="0,1,6,7,8,9,10,11">
  82. <Parameters address="0x20000000" name="SRAM" size="0xC0000"/>
  83. <Description/>
  84. <Organization>Single</Organization>
  85. <Bank name="Bank 1">
  86. <Field>
  87. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x8000"/>
  88. </Field>
  89. </Bank>
  90. </Configuration>
  91. <Configuration config="2,3,4,5">
  92. <Parameters address="0x30000000" name="SRAM" size="0xC0000"/>
  93. <Description/>
  94. <Organization>Single</Organization>
  95. <Bank name="Bank 1">
  96. <Field>
  97. <Parameters address="0x30000000" name="SRAM" occurence="0x1" size="0x8000"/>
  98. </Field>
  99. </Bank>
  100. </Configuration>
  101. </Peripheral>
  102. <!-- Embedded Flash -->
  103. <Peripheral>
  104. <Name>Embedded Flash</Name>
  105. <Type>Storage</Type>
  106. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  107. <ErasedValue>0xFF</ErasedValue>
  108. <Access>RWE</Access>
  109. <FlashSize address="0x0BFA07A0" default="0x200000"/>
  110. <BootloaderVersion address="0x0BF99EFE"/>
  111. <DBGMCU_CR address="0xE0044004" mask="0x06"/>
  112. <DBGMCU_APB1_FZ address="0xE0044008" mask="0x1800"/>
  113. <Configuration config="0,8,10"> <!-- Single Bank -->
  114. <Parameters address="0x08000000" name=" 2048 Kbyte Embedded Flash" size="0x200000"/>
  115. <Description/>
  116. <Organization>Single</Organization>
  117. <Allignement>0x10</Allignement>
  118. <Bank name="Bank 1">
  119. <Field>
  120. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  121. </Field>
  122. </Bank>
  123. </Configuration>
  124. <Configuration config="1,9,11"> <!-- dual Bank -->
  125. <Parameters address="0x08000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  126. <Description/>
  127. <Organization>Dual</Organization>
  128. <Allignement>0x10</Allignement>
  129. <Bank name="Bank 1">
  130. <Field>
  131. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  132. </Field>
  133. </Bank>
  134. <Bank name="Bank 2">
  135. <Field>
  136. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  137. </Field>
  138. </Bank>
  139. </Configuration>
  140. <Configuration config="2,4,6"> <!-- Single Bank secure -->
  141. <Parameters address="0x0C000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  142. <Description/>
  143. <Organization>Single</Organization>
  144. <Allignement>0x10</Allignement>
  145. <Bank name="Bank 1">
  146. <Field>
  147. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x4000"/>
  148. </Field>
  149. </Bank>
  150. </Configuration>
  151. <Configuration config="3,5,7"> <!-- dual Bank secure -->
  152. <Parameters address="0x0c000000" name=" 2 Mbyte Embedded Flash" size="0x200000"/>
  153. <Description/>
  154. <Organization>Dual</Organization>
  155. <Allignement>0x10</Allignement>
  156. <Bank name="Bank 1">
  157. <Field>
  158. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x2000"/>
  159. </Field>
  160. </Bank>
  161. <Bank name="Bank 2">
  162. <Field>
  163. <Parameters address="0x0c100000" name="sector128" occurence="0x80" size="0x2000"/>
  164. </Field>
  165. </Bank>
  166. </Configuration>
  167. </Peripheral>
  168. <!-- Data EEPROM -->
  169. <Peripheral>
  170. <Name>Data EEPROM</Name>
  171. <Type>Storage</Type>
  172. <Description>The Data EEPROM memory block. It contains user data.</Description>
  173. <ErasedValue>0xFF</ErasedValue>
  174. <Access>RWE</Access>
  175. <Configuration config="2,4,7,9,10">
  176. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  177. <Description/>
  178. <Organization>Single</Organization>
  179. <Allignement>0x4</Allignement>
  180. <Bank name="Bank 1">
  181. <Field>
  182. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x4000"/>
  183. </Field>
  184. </Bank>
  185. </Configuration>
  186. <Configuration config="3,5,6,8,11">
  187. <Parameters address="0x08000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  188. <Description/>
  189. <Organization>Single</Organization>
  190. <Allignement>0x4</Allignement>
  191. <Bank name="Bank 1">
  192. <Field>
  193. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x2000"/>
  194. </Field>
  195. </Bank>
  196. <Bank name="Bank 2">
  197. <Field>
  198. <Parameters address="0x08100000" name="sector128" occurence="0x80" size="0x2000"/>
  199. </Field>
  200. </Bank>
  201. </Configuration>
  202. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  203. <Configuration config="1">
  204. <Parameters address="0x0C000000" name=" 2 Mbyte Data EEPROM" size="0x200000"/>
  205. <Description/>
  206. <Organization>Single</Organization>
  207. <Allignement>0x4</Allignement>
  208. <Bank name="Bank 1">
  209. <Field>
  210. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x2000"/>
  211. </Field>
  212. </Bank>
  213. <Bank name="Bank 2">
  214. <Field>
  215. <Parameters address="0x0C100000" name="sector128" occurence="0x80" size="0x2000"/>
  216. </Field>
  217. </Bank>
  218. </Configuration>
  219. </Peripheral>
  220. <!-- OTP -->
  221. <Peripheral>
  222. <Name>OTP</Name>
  223. <Type>Storage</Type>
  224. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  225. <ErasedValue>0xFF</ErasedValue>
  226. <Access>RW</Access>
  227. <!-- 512 Bytes single bank -->
  228. <Configuration>
  229. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  230. <Description/>
  231. <Organization>Single</Organization>
  232. <Allignement>0x4</Allignement>
  233. <Bank name="OTP">
  234. <Field>
  235. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  236. </Field>
  237. </Bank>
  238. </Configuration>
  239. </Peripheral>
  240. <!-- Option Bytes -->
  241. <Peripheral>
  242. <Name>Option Bytes</Name>
  243. <Type>Configuration</Type>
  244. <Description/>
  245. <Access>RW</Access>
  246. <Configuration config="0,1,10,11">
  247. <Bank interface="JTAG_SWD">
  248. <Parameters address="0x40022040" name="Bank 1" size="0x24"/>
  249. <Category>
  250. <Name>Read Out Protection</Name>
  251. <Field>
  252. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  253. <AssignedBits>
  254. <Bit>
  255. <Name>RDP</Name>
  256. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  257. <BitOffset>0x0</BitOffset>
  258. <BitWidth>0x8</BitWidth>
  259. <Access>RW</Access>
  260. <Values>
  261. <Val value="0xAA">Level 0, no protection</Val>
  262. <Val value="0xDC">Level 1, read protection of memories</Val>
  263. <Val value="0xCC">Level 2, chip protection</Val>
  264. </Values>
  265. </Bit>
  266. </AssignedBits>
  267. </Field>
  268. </Category>
  269. <Category>
  270. <Name>BOR Level</Name>
  271. <Field>
  272. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  273. <AssignedBits>
  274. <Bit>
  275. <Name>BOR_LEV</Name>
  276. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  277. <BitOffset>0x8</BitOffset>
  278. <BitWidth>0x3</BitWidth>
  279. <Access>RW</Access>
  280. <Values>
  281. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  282. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  283. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  284. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  285. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  286. </Values>
  287. </Bit>
  288. </AssignedBits>
  289. </Field>
  290. </Category>
  291. <Category>
  292. <Name>User Configuration</Name>
  293. <Field>
  294. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  295. <AssignedBits>
  296. <Bit>
  297. <Name>TZEN</Name>
  298. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  299. <BitOffset>0x1F</BitOffset>
  300. <BitWidth>0x1</BitWidth>
  301. <Access>RW</Access>
  302. <Values>
  303. <Val value="0x0">Global TrustZone security disabled</Val>
  304. <Val value="0x1">Global TrustZone security enabled</Val>
  305. </Values>
  306. </Bit>
  307. <Bit>
  308. <Name>nRST_STOP</Name>
  309. <Description/>
  310. <BitOffset>0xC</BitOffset>
  311. <BitWidth>0x1</BitWidth>
  312. <Access>RW</Access>
  313. <Values>
  314. <Val value="0x0">Reset generated when entering Stop mode</Val>
  315. <Val value="0x1">No reset generated when entering Stop mode</Val>
  316. </Values>
  317. </Bit>
  318. <Bit>
  319. <Name>nRST_STDBY</Name>
  320. <Description/>
  321. <BitOffset>0xD</BitOffset>
  322. <BitWidth>0x1</BitWidth>
  323. <Access>RW</Access>
  324. <Values>
  325. <Val value="0x0">Reset generated when entering Standby mode</Val>
  326. <Val value="0x1">No reset generated when entering Standby mode</Val>
  327. </Values>
  328. </Bit>
  329. <Bit>
  330. <Name>nRST_SHDW</Name>
  331. <Description/>
  332. <BitOffset>0xE</BitOffset>
  333. <BitWidth>0x1</BitWidth>
  334. <Access>RW</Access>
  335. <Values>
  336. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  337. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  338. </Values>
  339. </Bit>
  340. <Bit>
  341. <Name>SRAM134_RST</Name>
  342. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  343. <BitOffset>0xF</BitOffset>
  344. <BitWidth>0x1</BitWidth>
  345. <Access>RW</Access>
  346. <Values>
  347. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  348. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  349. </Values>
  350. </Bit>
  351. <Bit>
  352. <Name>IWDG_SW</Name>
  353. <Description/>
  354. <BitOffset>0x10</BitOffset>
  355. <BitWidth>0x1</BitWidth>
  356. <Access>RW</Access>
  357. <Values>
  358. <Val value="0x0">Hardware independant watchdog</Val>
  359. <Val value="0x1">Software independant watchdog</Val>
  360. </Values>
  361. </Bit>
  362. <Bit>
  363. <Name>IWDG_STOP</Name>
  364. <Description/>
  365. <BitOffset>0x11</BitOffset>
  366. <BitWidth>0x1</BitWidth>
  367. <Access>RW</Access>
  368. <Values>
  369. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  370. <Val value="0x1">IWDG counter active in stop mode</Val>
  371. </Values>
  372. </Bit>
  373. <Bit>
  374. <Name>IWDG_STDBY</Name>
  375. <Description/>
  376. <BitOffset>0x12</BitOffset>
  377. <BitWidth>0x1</BitWidth>
  378. <Access>RW</Access>
  379. <Values>
  380. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  381. <Val value="0x1">IWDG counter active in standby mode</Val>
  382. </Values>
  383. </Bit>
  384. <Bit>
  385. <Name>WWDG_SW</Name>
  386. <Description/>
  387. <BitOffset>0x13</BitOffset>
  388. <BitWidth>0x1</BitWidth>
  389. <Access>RW</Access>
  390. <Values>
  391. <Val value="0x0">Hardware window watchdog</Val>
  392. <Val value="0x1">Software window watchdog</Val>
  393. </Values>
  394. </Bit>
  395. <Bit>
  396. <Name>SWAP_BANK</Name>
  397. <Description/>
  398. <BitOffset>0x14</BitOffset>
  399. <BitWidth>0x1</BitWidth>
  400. <Access>RW</Access>
  401. <Values>
  402. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  403. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  404. </Values>
  405. </Bit>
  406. <Bit>
  407. <Name>DBANK</Name>
  408. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  409. <BitOffset>0x15</BitOffset>
  410. <BitWidth>0x1</BitWidth>
  411. <Access>RW</Access>
  412. <Values>
  413. <Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
  414. <Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
  415. </Values>
  416. </Bit>
  417. <Bit>
  418. <Name>BKPRAM_ECC</Name>
  419. <Description>SRAM2 parity check enable</Description>
  420. <BitOffset>0x16</BitOffset>
  421. <BitWidth>0x1</BitWidth>
  422. <Access>RW</Access>
  423. <Values>
  424. <Val value="0x0">Backup RAM ECC check enabled</Val>
  425. <Val value="0x1">Backup RAM ECC check disabled</Val>
  426. </Values>
  427. </Bit>
  428. <Bit>
  429. <Name>SRAM3_ECC</Name>
  430. <Description>SRAM3 ECC detection and correction enable</Description>
  431. <BitOffset>0x17</BitOffset>
  432. <BitWidth>0x1</BitWidth>
  433. <Access>RW</Access>
  434. <Values>
  435. <Val value="0x0">SRAM3 ECC check enabled</Val>
  436. <Val value="0x1">SRAM3 ECC check disabled</Val>
  437. </Values>
  438. </Bit>
  439. <Bit>
  440. <Name>SRAM2_ECC</Name>
  441. <Description>SRAM2 ECC detection and correction enable</Description>
  442. <BitOffset>0x18</BitOffset>
  443. <BitWidth>0x1</BitWidth>
  444. <Access>RW</Access>
  445. <Values>
  446. <Val value="0x0">SRAM2 ECC check enabled</Val>
  447. <Val value="0x1">SRAM2 ECC check disabled</Val>
  448. </Values>
  449. </Bit>
  450. <Bit>
  451. <Name>SRAM2_RST</Name>
  452. <Description>SRAM2 Erase when system reset</Description>
  453. <BitOffset>0x19</BitOffset>
  454. <BitWidth>0x1</BitWidth>
  455. <Access>RW</Access>
  456. <Values>
  457. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  458. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  459. </Values>
  460. </Bit>
  461. <Bit>
  462. <Name>nSWBOOT0</Name>
  463. <Description>Software BOOT0</Description>
  464. <BitOffset>0x1A</BitOffset>
  465. <BitWidth>0x1</BitWidth>
  466. <Access>RW</Access>
  467. <Values>
  468. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  469. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  470. </Values>
  471. </Bit>
  472. <Bit>
  473. <Name>nBOOT0</Name>
  474. <Description>nBOOT0 option bit</Description>
  475. <BitOffset>0x1B</BitOffset>
  476. <BitWidth>0x1</BitWidth>
  477. <Access>RW</Access>
  478. <Values>
  479. <Val value="0x0">nBOOT0 = 0</Val>
  480. <Val value="0x1">nBOOT0 = 1</Val>
  481. </Values>
  482. </Bit>
  483. <Bit>
  484. <Name>PA15_PUPEN</Name>
  485. <Description>PA15 pull-up enable</Description>
  486. <BitOffset>0x1C</BitOffset>
  487. <BitWidth>0x1</BitWidth>
  488. <Access>RW</Access>
  489. <Values>
  490. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  491. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  492. </Values>
  493. </Bit>
  494. <Bit>
  495. <Name>IO_VDD_HSLV</Name>
  496. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  497. <BitOffset>0x1D</BitOffset>
  498. <BitWidth>0x1</BitWidth>
  499. <Access>RW</Access>
  500. <Values>
  501. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  502. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  503. </Values>
  504. </Bit>
  505. <Bit>
  506. <Name>IO_VDDIO2_HSLV</Name>
  507. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  508. <BitOffset>0x1E</BitOffset>
  509. <BitWidth>0x1</BitWidth>
  510. <Access>RW</Access>
  511. <Values>
  512. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  513. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  514. </Values>
  515. </Bit>
  516. </AssignedBits>
  517. </Field>
  518. </Category>
  519. <Category>
  520. <Name>Boot Configuration</Name>
  521. <Field>
  522. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  523. <AssignedBits>
  524. <Bit>
  525. <Name>NSBOOTADD0</Name>
  526. <Description>Non-secure Boot base address 0</Description>
  527. <BitOffset>0x7</BitOffset>
  528. <BitWidth>0x19</BitWidth>
  529. <Access>RW</Access>
  530. <Equation multiplier="0x80" offset="0x0000000"/>
  531. </Bit>
  532. </AssignedBits>
  533. </Field>
  534. <Field>
  535. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  536. <AssignedBits>
  537. <Bit>
  538. <Name>NSBOOTADD1</Name>
  539. <Description>Non-secure Boot base address 1</Description>
  540. <BitOffset>0x7</BitOffset>
  541. <BitWidth>0x19</BitWidth>
  542. <Access>RW</Access>
  543. <Equation multiplier="0x80" offset="0x0000000"/>
  544. </Bit>
  545. </AssignedBits>
  546. </Field>
  547. </Category>
  548. <Category>
  549. <Name>Write Protection 1</Name>
  550. <Field>
  551. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  552. <AssignedBits>
  553. <Bit config="0,10">
  554. <Name>WRP1A_PSTRT</Name>
  555. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  556. <BitOffset>0x0</BitOffset>
  557. <BitWidth>0x7</BitWidth>
  558. <Access>RW</Access>
  559. <Equation multiplier="0x4000" offset="0x08000000"/>
  560. </Bit>
  561. <Bit config="1,11">
  562. <Name>WRP1A_PSTRT</Name>
  563. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  564. <BitOffset>0x0</BitOffset>
  565. <BitWidth>0x7</BitWidth>
  566. <Access>RW</Access>
  567. <Equation multiplier="0x2000" offset="0x08000000"/>
  568. </Bit>
  569. <Bit config="0,10">
  570. <Name>WRP1A_PEND</Name>
  571. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  572. <BitOffset>0x10</BitOffset>
  573. <BitWidth>0x7</BitWidth>
  574. <Access>RW</Access>
  575. <Equation multiplier="0x4000" offset="0x08000000"/>
  576. </Bit>
  577. <Bit config="1,11">
  578. <Name>WRP1A_PEND</Name>
  579. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  580. <BitOffset>0x10</BitOffset>
  581. <BitWidth>0x7</BitWidth>
  582. <Access>RW</Access>
  583. <Equation multiplier="0x2000" offset="0x08000000"/>
  584. </Bit>
  585. <Bit>
  586. <Name>UNLOCK_1A</Name>
  587. <Description>Bank 1 WPR first area A unlock</Description>
  588. <BitOffset>0x1F</BitOffset>
  589. <BitWidth>0x1</BitWidth>
  590. <Access>RW</Access>
  591. <Values>
  592. <Val value="0x0">WRP1A start and end pages locked</Val>
  593. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  594. </Values>
  595. </Bit>
  596. </AssignedBits>
  597. </Field>
  598. <Field>
  599. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  600. <AssignedBits>
  601. <Bit config="0,10">
  602. <Name>WRP1B_PSTRT</Name>
  603. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  604. <BitOffset>0x0</BitOffset>
  605. <BitWidth>0x7</BitWidth>
  606. <Access>RW</Access>
  607. <Equation multiplier="0x4000" offset="0x08000000"/>
  608. </Bit>
  609. <Bit config="1,11">
  610. <Name>WRP1B_PSTRT</Name>
  611. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  612. <BitOffset>0x0</BitOffset>
  613. <BitWidth>0x7</BitWidth>
  614. <Access>RW</Access>
  615. <Equation multiplier="0x2000" offset="0x08000000"/>
  616. </Bit>
  617. <Bit config="0,10">
  618. <Name>WRP1B_PEND</Name>
  619. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  620. <BitOffset>0x10</BitOffset>
  621. <BitWidth>0x7</BitWidth>
  622. <Access>RW</Access>
  623. <Equation multiplier="0x4000" offset="0x08000000"/>
  624. </Bit>
  625. <Bit config="1,11">
  626. <Name>WRP1B_PEND</Name>
  627. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  628. <BitOffset>0x10</BitOffset>
  629. <BitWidth>0x7</BitWidth>
  630. <Access>RW</Access>
  631. <Equation multiplier="0x2000" offset="0x08000000"/>
  632. </Bit>
  633. <Bit>
  634. <Name>UNLOCK_1B</Name>
  635. <Description>Bank 1 WPR first area B unlock</Description>
  636. <BitOffset>0x1F</BitOffset>
  637. <BitWidth>0x1</BitWidth>
  638. <Access>RW</Access>
  639. <Values>
  640. <Val value="0x0">WRP1B start and end pages locked</Val>
  641. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  642. </Values>
  643. </Bit>
  644. </AssignedBits>
  645. </Field>
  646. </Category>
  647. </Bank>
  648. <Bank interface="JTAG_SWD">
  649. <Parameters address="0x40022068" name="Bank 2" size="0x8"/>
  650. <Category>
  651. <Name>Write Protection 2</Name>
  652. <Field>
  653. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  654. <AssignedBits>
  655. <Bit config="0,10">
  656. <Name>WRP2A_PSTRT</Name>
  657. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  658. <BitOffset>0x0</BitOffset>
  659. <BitWidth>0x7</BitWidth>
  660. <Access>RW</Access>
  661. <Equation multiplier="0x4000" offset="0x08000000"/>
  662. </Bit>
  663. <Bit config="1,11">
  664. <Name>WRP2A_PSTRT</Name>
  665. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  666. <BitOffset>0x0</BitOffset>
  667. <BitWidth>0x7</BitWidth>
  668. <Access>RW</Access>
  669. <Equation multiplier="0x2000" offset="0x08100000"/>
  670. </Bit>
  671. <Bit config="0,10">
  672. <Name>WRP2A_PEND</Name>
  673. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  674. <BitOffset>0x10</BitOffset>
  675. <BitWidth>0x7</BitWidth>
  676. <Access>RW</Access>
  677. <Equation multiplier="0x4000" offset="0x08000000"/>
  678. </Bit>
  679. <Bit config="1,11">
  680. <Name>WRP2A_PEND</Name>
  681. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  682. <BitOffset>0x10</BitOffset>
  683. <BitWidth>0x7</BitWidth>
  684. <Access>RW</Access>
  685. <Equation multiplier="0x2000" offset="0x08100000"/>
  686. </Bit>
  687. <Bit>
  688. <Name>UNLOCK_2A</Name>
  689. <Description>Bank 2 WPR first area A unlock</Description>
  690. <BitOffset>0x1F</BitOffset>
  691. <BitWidth>0x1</BitWidth>
  692. <Access>RW</Access>
  693. <Values>
  694. <Val value="0x0">WRP2A start and end pages locked</Val>
  695. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  696. </Values>
  697. </Bit>
  698. </AssignedBits>
  699. </Field>
  700. <Field>
  701. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  702. <AssignedBits>
  703. <Bit config="0,10">
  704. <Name>WRP2B_PSTRT</Name>
  705. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  706. <BitOffset>0x0</BitOffset>
  707. <BitWidth>0x7</BitWidth>
  708. <Access>RW</Access>
  709. <Equation multiplier="0x4000" offset="0x08000000"/>
  710. </Bit>
  711. <Bit config="1,11">
  712. <Name>WRP2B_PSTRT</Name>
  713. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  714. <BitOffset>0x0</BitOffset>
  715. <BitWidth>0x7</BitWidth>
  716. <Access>RW</Access>
  717. <Equation multiplier="0x2000" offset="0x08100000"/>
  718. </Bit>
  719. <Bit config="0,10">
  720. <Name>WRP2B_PEND</Name>
  721. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  722. <BitOffset>0x10</BitOffset>
  723. <BitWidth>0x7</BitWidth>
  724. <Access>RW</Access>
  725. <Equation multiplier="0x4000" offset="0x08000000"/>
  726. </Bit>
  727. <Bit config="1,11">
  728. <Name>WRP2B_PEND</Name>
  729. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  730. <BitOffset>0x10</BitOffset>
  731. <BitWidth>0x7</BitWidth>
  732. <Access>RW</Access>
  733. <Equation multiplier="0x2000" offset="0x08100000"/>
  734. </Bit>
  735. <Bit>
  736. <Name>UNLOCK_2B</Name>
  737. <Description>Bank 2 WPR first area B unlock</Description>
  738. <BitOffset>0x1F</BitOffset>
  739. <BitWidth>0x1</BitWidth>
  740. <Access>RW</Access>
  741. <Values>
  742. <Val value="0x0">WRP2B start and end pages locked</Val>
  743. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  744. </Values>
  745. </Bit>
  746. </AssignedBits>
  747. </Field>
  748. </Category>
  749. </Bank>
  750. </Configuration>
  751. <Configuration config="2,3">
  752. <Bank interface="JTAG_SWD">
  753. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  754. <Category>
  755. <Name>Read Out Protection</Name>
  756. <Field>
  757. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  758. <AssignedBits>
  759. <Bit>
  760. <Name>RDP</Name>
  761. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  762. <BitOffset>0x0</BitOffset>
  763. <BitWidth>0x8</BitWidth>
  764. <Access>RW</Access>
  765. <Values>
  766. <Val value="0xAA">Level 0, no protection</Val>
  767. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  768. <Val value="0xDC">Level 1, read protection of memories</Val>
  769. <Val value="0xCC">Level 2, chip protection</Val>
  770. </Values>
  771. </Bit>
  772. </AssignedBits>
  773. </Field>
  774. </Category>
  775. <Category>
  776. <Name>BOR Level</Name>
  777. <Field>
  778. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  779. <AssignedBits>
  780. <Bit>
  781. <Name>BOR_LEV</Name>
  782. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  783. <BitOffset>0x8</BitOffset>
  784. <BitWidth>0x3</BitWidth>
  785. <Access>RW</Access>
  786. <Values>
  787. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  788. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  789. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  790. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  791. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  792. </Values>
  793. </Bit>
  794. </AssignedBits>
  795. </Field>
  796. </Category>
  797. <Category>
  798. <Name>User Configuration</Name>
  799. <Field>
  800. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  801. <AssignedBits>
  802. <Bit>
  803. <Name>TZEN</Name>
  804. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  805. <BitOffset>0x1F</BitOffset>
  806. <BitWidth>0x1</BitWidth>
  807. <Access>RW</Access>
  808. <Values>
  809. <Val value="0x0">Global TrustZone security disabled</Val>
  810. <Val value="0x1">Global TrustZone security enabled</Val>
  811. </Values>
  812. </Bit>
  813. <Bit>
  814. <Name>nRST_STOP</Name>
  815. <Description/>
  816. <BitOffset>0xC</BitOffset>
  817. <BitWidth>0x1</BitWidth>
  818. <Access>RW</Access>
  819. <Values>
  820. <Val value="0x0">Reset generated when entering Stop mode</Val>
  821. <Val value="0x1">No reset generated when entering Stop mode</Val>
  822. </Values>
  823. </Bit>
  824. <Bit>
  825. <Name>nRST_STDBY</Name>
  826. <Description/>
  827. <BitOffset>0xD</BitOffset>
  828. <BitWidth>0x1</BitWidth>
  829. <Access>RW</Access>
  830. <Values>
  831. <Val value="0x0">Reset generated when entering Standby mode</Val>
  832. <Val value="0x1">No reset generated when entering Standby mode</Val>
  833. </Values>
  834. </Bit>
  835. <Bit>
  836. <Name>nRST_SHDW</Name>
  837. <Description/>
  838. <BitOffset>0xE</BitOffset>
  839. <BitWidth>0x1</BitWidth>
  840. <Access>RW</Access>
  841. <Values>
  842. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  843. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  844. </Values>
  845. </Bit>
  846. <Bit>
  847. <Name>SRAM134_RST</Name>
  848. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  849. <BitOffset>0xF</BitOffset>
  850. <BitWidth>0x1</BitWidth>
  851. <Access>RW</Access>
  852. <Values>
  853. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  854. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  855. </Values>
  856. </Bit>
  857. <Bit>
  858. <Name>IWDG_SW</Name>
  859. <Description/>
  860. <BitOffset>0x10</BitOffset>
  861. <BitWidth>0x1</BitWidth>
  862. <Access>RW</Access>
  863. <Values>
  864. <Val value="0x0">Hardware independant watchdog</Val>
  865. <Val value="0x1">Software independant watchdog</Val>
  866. </Values>
  867. </Bit>
  868. <Bit>
  869. <Name>IWDG_STOP</Name>
  870. <Description/>
  871. <BitOffset>0x11</BitOffset>
  872. <BitWidth>0x1</BitWidth>
  873. <Access>RW</Access>
  874. <Values>
  875. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  876. <Val value="0x1">IWDG counter active in stop mode</Val>
  877. </Values>
  878. </Bit>
  879. <Bit>
  880. <Name>IWDG_STDBY</Name>
  881. <Description/>
  882. <BitOffset>0x12</BitOffset>
  883. <BitWidth>0x1</BitWidth>
  884. <Access>RW</Access>
  885. <Values>
  886. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  887. <Val value="0x1">IWDG counter active in standby mode</Val>
  888. </Values>
  889. </Bit>
  890. <Bit>
  891. <Name>WWDG_SW</Name>
  892. <Description/>
  893. <BitOffset>0x13</BitOffset>
  894. <BitWidth>0x1</BitWidth>
  895. <Access>RW</Access>
  896. <Values>
  897. <Val value="0x0">Hardware window watchdog</Val>
  898. <Val value="0x1">Software window watchdog</Val>
  899. </Values>
  900. </Bit>
  901. <Bit>
  902. <Name>SWAP_BANK</Name>
  903. <Description/>
  904. <BitOffset>0x14</BitOffset>
  905. <BitWidth>0x1</BitWidth>
  906. <Access>RW</Access>
  907. <Values>
  908. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  909. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  910. </Values>
  911. </Bit>
  912. <Bit>
  913. <Name>DBANK</Name>
  914. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  915. <BitOffset>0x15</BitOffset>
  916. <BitWidth>0x1</BitWidth>
  917. <Access>RW</Access>
  918. <Values>
  919. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  920. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  921. </Values>
  922. </Bit>
  923. <Bit>
  924. <Name>SRAM2_PE</Name>
  925. <Description>SRAM2 parity check enable</Description>
  926. <BitOffset>0x18</BitOffset>
  927. <BitWidth>0x1</BitWidth>
  928. <Access>RW</Access>
  929. <Values>
  930. <Val value="0x0">SRAM2 parity check enable</Val>
  931. <Val value="0x1">SRAM2 parity check disable</Val>
  932. </Values>
  933. </Bit>
  934. <Bit>
  935. <Name>SRAM2_RST</Name>
  936. <Description>SRAM2 Erase when system reset</Description>
  937. <BitOffset>0x19</BitOffset>
  938. <BitWidth>0x1</BitWidth>
  939. <Access>RW</Access>
  940. <Values>
  941. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  942. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  943. </Values>
  944. </Bit>
  945. <Bit>
  946. <Name>nSWBOOT0</Name>
  947. <Description>Software BOOT0</Description>
  948. <BitOffset>0x1A</BitOffset>
  949. <BitWidth>0x1</BitWidth>
  950. <Access>RW</Access>
  951. <Values>
  952. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  953. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  954. </Values>
  955. </Bit>
  956. <Bit>
  957. <Name>nBOOT0</Name>
  958. <Description>nBOOT0 option bit</Description>
  959. <BitOffset>0x1B</BitOffset>
  960. <BitWidth>0x1</BitWidth>
  961. <Access>RW</Access>
  962. <Values>
  963. <Val value="0x0">nBOOT0 = 0</Val>
  964. <Val value="0x1">nBOOT0 = 1</Val>
  965. </Values>
  966. </Bit>
  967. <Bit>
  968. <Name>PA15_PUPEN</Name>
  969. <Description>PA15 pull-up enable</Description>
  970. <BitOffset>0x1C</BitOffset>
  971. <BitWidth>0x1</BitWidth>
  972. <Access>RW</Access>
  973. <Values>
  974. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  975. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  976. </Values>
  977. </Bit>
  978. <Bit>
  979. <Name>BKPRAM_ECC</Name>
  980. <Description>SRAM2 parity check enable</Description>
  981. <BitOffset>0x16</BitOffset>
  982. <BitWidth>0x1</BitWidth>
  983. <Access>RW</Access>
  984. <Values>
  985. <Val value="0x0">Backup RAM ECC check enabled</Val>
  986. <Val value="0x1">Backup RAM ECC check disabled</Val>
  987. </Values>
  988. </Bit>
  989. <Bit>
  990. <Name>SRAM3_ECC</Name>
  991. <Description>SRAM3 ECC detection and correction enable</Description>
  992. <BitOffset>0x17</BitOffset>
  993. <BitWidth>0x1</BitWidth>
  994. <Access>RW</Access>
  995. <Values>
  996. <Val value="0x0">SRAM3 ECC check enabled</Val>
  997. <Val value="0x1">SRAM3 ECC check disabled</Val>
  998. </Values>
  999. </Bit>
  1000. <Bit>
  1001. <Name>SRAM2_ECC</Name>
  1002. <Description>SRAM2 ECC detection and correction enable</Description>
  1003. <BitOffset>0x18</BitOffset>
  1004. <BitWidth>0x1</BitWidth>
  1005. <Access>RW</Access>
  1006. <Values>
  1007. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1008. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1009. </Values>
  1010. </Bit>
  1011. <Bit>
  1012. <Name>IO_VDD_HSLV</Name>
  1013. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1014. <BitOffset>0x1D</BitOffset>
  1015. <BitWidth>0x1</BitWidth>
  1016. <Access>RW</Access>
  1017. <Values>
  1018. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1019. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1020. </Values>
  1021. </Bit>
  1022. <Bit>
  1023. <Name>IO_VDDIO2_HSLV</Name>
  1024. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1025. <BitOffset>0x1E</BitOffset>
  1026. <BitWidth>0x1</BitWidth>
  1027. <Access>RW</Access>
  1028. <Values>
  1029. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1030. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1031. </Values>
  1032. </Bit>
  1033. </AssignedBits>
  1034. </Field>
  1035. </Category>
  1036. <Category>
  1037. <Name>Boot Configuration</Name>
  1038. <Field>
  1039. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1040. <AssignedBits>
  1041. <Bit>
  1042. <Name>NSBOOTADD0</Name>
  1043. <Description>Non-secure Boot base address 0</Description>
  1044. <BitOffset>0x7</BitOffset>
  1045. <BitWidth>0x19</BitWidth>
  1046. <Access>RW</Access>
  1047. <Equation multiplier="0x80" offset="0x0000000"/>
  1048. </Bit>
  1049. </AssignedBits>
  1050. </Field>
  1051. <Field>
  1052. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1053. <AssignedBits>
  1054. <Bit>
  1055. <Name>NSBOOTADD1</Name>
  1056. <Description>Non-secure Boot base address 1</Description>
  1057. <BitOffset>0x7</BitOffset>
  1058. <BitWidth>0x19</BitWidth>
  1059. <Access>RW</Access>
  1060. <Equation multiplier="0x80" offset="0x0000000"/>
  1061. </Bit>
  1062. </AssignedBits>
  1063. </Field>
  1064. <Field>
  1065. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1066. <AssignedBits>
  1067. <Bit>
  1068. <Name>SECBOOTADD0</Name>
  1069. <Description>Secure boot base address 0</Description>
  1070. <BitOffset>0x7</BitOffset>
  1071. <BitWidth>0x19</BitWidth>
  1072. <Access>RW</Access>
  1073. <Equation multiplier="0x80" offset="0x0000000"/>
  1074. </Bit>
  1075. </AssignedBits>
  1076. </Field>
  1077. <Field>
  1078. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  1079. <AssignedBits>
  1080. <Bit>
  1081. <Name>BOOT_LOCK</Name>
  1082. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1083. <BitOffset>0x0</BitOffset>
  1084. <BitWidth>0x1</BitWidth>
  1085. <Access>RW</Access>
  1086. <Values>
  1087. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1088. <Val value="0x1">Boot forced from base address memory</Val>
  1089. </Values>
  1090. </Bit>
  1091. </AssignedBits>
  1092. </Field>
  1093. </Category>
  1094. <Category>
  1095. <Name>Secure Area 1</Name>
  1096. <Field>
  1097. <Parameters address="0x50022050" name="FLASH_SECWM1R1" size="0x4"/>
  1098. <AssignedBits>
  1099. <Bit config="2">
  1100. <Name>SECWM1_PSTRT</Name>
  1101. <Description>Start page of first secure area</Description>
  1102. <BitOffset>0x0</BitOffset>
  1103. <BitWidth>0x7</BitWidth>
  1104. <Access>RW</Access>
  1105. <Equation multiplier="0x4000" offset="0x08000000"/>
  1106. </Bit>
  1107. <Bit config="3">
  1108. <Name>SECWM1_PSTRT</Name>
  1109. <Description>Start page of first secure area</Description>
  1110. <BitOffset>0x0</BitOffset>
  1111. <BitWidth>0x7</BitWidth>
  1112. <Access>RW</Access>
  1113. <Equation multiplier="0x2000" offset="0x08000000"/>
  1114. </Bit>
  1115. <Bit config="2">
  1116. <Name>SECWM1_PEND</Name>
  1117. <Description>End page of first secure area</Description>
  1118. <BitOffset>0x10</BitOffset>
  1119. <BitWidth>0x7</BitWidth>
  1120. <Access>RW</Access>
  1121. <Equation multiplier="0x4000" offset="0x08000000"/>
  1122. </Bit>
  1123. <Bit config="3">
  1124. <Name>SECWM1_PEND</Name>
  1125. <Description>End page of first secure area</Description>
  1126. <BitOffset>0x10</BitOffset>
  1127. <BitWidth>0x7</BitWidth>
  1128. <Access>RW</Access>
  1129. <Equation multiplier="0x2000" offset="0x08000000"/>
  1130. </Bit>
  1131. </AssignedBits>
  1132. </Field>
  1133. <Field>
  1134. <Parameters address="0x50022054" name="FLASH_SECWM2R1" size="0x4"/>
  1135. <AssignedBits>
  1136. <Bit config="2">
  1137. <Name>HDP1_PEND</Name>
  1138. <Description>End page of first hide protection area</Description>
  1139. <BitOffset>0x10</BitOffset>
  1140. <BitWidth>0x7</BitWidth>
  1141. <Access>RW</Access>
  1142. <Equation multiplier="0x4000" offset="0xC003fff"/>
  1143. </Bit>
  1144. <Bit config="3">
  1145. <Name>HDP1_PEND</Name>
  1146. <Description>End page of first hide protection area</Description>
  1147. <BitOffset>0x10</BitOffset>
  1148. <BitWidth>0x7</BitWidth>
  1149. <Access>RW</Access>
  1150. <Equation multiplier="0x2000" offset="0xC001FFF"/>
  1151. </Bit>
  1152. <Bit>
  1153. <Name>HDP1EN</Name>
  1154. <Description>Hide protection first area enable</Description>
  1155. <BitOffset>0x1F</BitOffset>
  1156. <BitWidth>0x1</BitWidth>
  1157. <Access>RW</Access>
  1158. <Values>
  1159. <Val value="0x0">No HDP area 1</Val>
  1160. <Val value="0x1">HDP first area is enabled</Val>
  1161. </Values>
  1162. </Bit>
  1163. </AssignedBits>
  1164. </Field>
  1165. </Category>
  1166. <Category>
  1167. <Name>Write Protection 1</Name>
  1168. <Field>
  1169. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  1170. <AssignedBits>
  1171. <Bit config="2">
  1172. <Name>WRP1A_PSTRT</Name>
  1173. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1174. <BitOffset>0x0</BitOffset>
  1175. <BitWidth>0x7</BitWidth>
  1176. <Access>RW</Access>
  1177. <Equation multiplier="0x4000" offset="0x08000000"/>
  1178. </Bit>
  1179. <Bit config="3">
  1180. <Name>WRP1A_PSTRT</Name>
  1181. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1182. <BitOffset>0x0</BitOffset>
  1183. <BitWidth>0x7</BitWidth>
  1184. <Access>RW</Access>
  1185. <Equation multiplier="0x2000" offset="0x08000000"/>
  1186. </Bit>
  1187. <Bit config="2">
  1188. <Name>WRP1A_PEND</Name>
  1189. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1190. <BitOffset>0x10</BitOffset>
  1191. <BitWidth>0x7</BitWidth>
  1192. <Access>RW</Access>
  1193. <Equation multiplier="0x4000" offset="0x08000000"/>
  1194. </Bit>
  1195. <Bit config="3">
  1196. <Name>WRP1A_PEND</Name>
  1197. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1198. <BitOffset>0x10</BitOffset>
  1199. <BitWidth>0x7</BitWidth>
  1200. <Access>RW</Access>
  1201. <Equation multiplier="0x2000" offset="0x08000000"/>
  1202. </Bit>
  1203. <Bit>
  1204. <Name>UNLOCK_1A</Name>
  1205. <Description>Bank 1 WPR first area A unlock</Description>
  1206. <BitOffset>0x1F</BitOffset>
  1207. <BitWidth>0x1</BitWidth>
  1208. <Access>RW</Access>
  1209. <Values>
  1210. <Val value="0x0">WRP1A start and end pages locked</Val>
  1211. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1212. </Values>
  1213. </Bit>
  1214. </AssignedBits>
  1215. </Field>
  1216. <Field>
  1217. <Parameters address="0x5002205C" name="FLASH_WRP1BR" size="0x4"/>
  1218. <AssignedBits>
  1219. <Bit config="2">
  1220. <Name>WRP1B_PSTRT</Name>
  1221. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1222. <BitOffset>0x0</BitOffset>
  1223. <BitWidth>0x7</BitWidth>
  1224. <Access>RW</Access>
  1225. <Equation multiplier="0x4000" offset="0x08000000"/>
  1226. </Bit>
  1227. <Bit config="3">
  1228. <Name>WRP1B_PSTRT</Name>
  1229. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1230. <BitOffset>0x0</BitOffset>
  1231. <BitWidth>0x7</BitWidth>
  1232. <Access>RW</Access>
  1233. <Equation multiplier="0x2000" offset="0x08000000"/>
  1234. </Bit>
  1235. <Bit config="2">
  1236. <Name>WRP1B_PEND</Name>
  1237. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1238. <BitOffset>0x10</BitOffset>
  1239. <BitWidth>0x7</BitWidth>
  1240. <Access>RW</Access>
  1241. <Equation multiplier="0x4000" offset="0x08000000"/>
  1242. </Bit>
  1243. <Bit config="3">
  1244. <Name>WRP1B_PEND</Name>
  1245. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1246. <BitOffset>0x10</BitOffset>
  1247. <BitWidth>0x7</BitWidth>
  1248. <Access>RW</Access>
  1249. <Equation multiplier="0x2000" offset="0x08000000"/>
  1250. </Bit>
  1251. <Bit>
  1252. <Name>UNLOCK_1B</Name>
  1253. <Description>Bank 1 WPR first area B unlock</Description>
  1254. <BitOffset>0x1F</BitOffset>
  1255. <BitWidth>0x1</BitWidth>
  1256. <Access>RW</Access>
  1257. <Values>
  1258. <Val value="0x0">WRP1B start and end pages locked</Val>
  1259. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1260. </Values>
  1261. </Bit>
  1262. </AssignedBits>
  1263. </Field>
  1264. </Category>
  1265. </Bank>
  1266. <Bank interface="JTAG_SWD">
  1267. <Parameters address="0x50022060" name="Bank 2" size="0x8"/>
  1268. <Category>
  1269. <Name>Secure Area 2</Name>
  1270. <Field>
  1271. <Parameters address="0x50022060" name="FLASH_SECWM2R1" size="0x4"/>
  1272. <AssignedBits>
  1273. <Bit config="2">
  1274. <Name>SECWM2_PSTRT</Name>
  1275. <Description>Start page of second secure area</Description>
  1276. <BitOffset>0x0</BitOffset>
  1277. <BitWidth>0x7</BitWidth>
  1278. <Access>RW</Access>
  1279. <Equation multiplier="0x4000" offset="0x08000000"/>
  1280. </Bit>
  1281. <Bit config="3">
  1282. <Name>SECWM2_PSTRT</Name>
  1283. <Description>Start page of second secure area</Description>
  1284. <BitOffset>0x0</BitOffset>
  1285. <BitWidth>0x7</BitWidth>
  1286. <Access>RW</Access>
  1287. <Equation multiplier="0x2000" offset="0x08100000"/>
  1288. </Bit>
  1289. <Bit config="2">
  1290. <Name>SECWM2_PEND</Name>
  1291. <Description>End page of second secure area</Description>
  1292. <BitOffset>0x10</BitOffset>
  1293. <BitWidth>0x7</BitWidth>
  1294. <Access>RW</Access>
  1295. <Equation multiplier="0x4000" offset="0x08000000"/>
  1296. </Bit>
  1297. <Bit config="3">
  1298. <Name>SECWM2_PEND</Name>
  1299. <Description>End page of second secure area</Description>
  1300. <BitOffset>0x10</BitOffset>
  1301. <BitWidth>0x7</BitWidth>
  1302. <Access>RW</Access>
  1303. <Equation multiplier="0x2000" offset="0x08100000"/>
  1304. </Bit>
  1305. </AssignedBits>
  1306. </Field>
  1307. <Field>
  1308. <Parameters address="0x50022064" name="FLASH_SECWM2R2" size="0x4"/>
  1309. <AssignedBits>
  1310. <Bit config="2">
  1311. <Name>HDP2_PEND</Name>
  1312. <Description>End page of second hide protection area</Description>
  1313. <BitOffset>0x10</BitOffset>
  1314. <BitWidth>0x7</BitWidth>
  1315. <Access>RW</Access>
  1316. <Equation multiplier="0x4000" offset="0xC103FFF"/>
  1317. </Bit>
  1318. <Bit config="3">
  1319. <Name>HDP2_PEND</Name>
  1320. <Description>End page of second hide protection area</Description>
  1321. <BitOffset>0x10</BitOffset>
  1322. <BitWidth>0x7</BitWidth>
  1323. <Access>RW</Access>
  1324. <Equation multiplier="0x2000" offset="0xC101FFF"/>
  1325. </Bit>
  1326. <Bit>
  1327. <Name>HDP2EN</Name>
  1328. <Description>Hide protection second area enable</Description>
  1329. <BitOffset>0x1F</BitOffset>
  1330. <BitWidth>0x1</BitWidth>
  1331. <Access>RW</Access>
  1332. <Values>
  1333. <Val value="0x0">No HDP area 2</Val>
  1334. <Val value="0x1">HDP second area is enabled</Val>
  1335. </Values>
  1336. </Bit>
  1337. </AssignedBits>
  1338. </Field>
  1339. </Category>
  1340. </Bank>
  1341. <Bank interface="JTAG_SWD">
  1342. <Parameters address="0x50022068" name="Bank 3" size="0x8"/>
  1343. <Category>
  1344. <Name>Write Protection 2</Name>
  1345. <Field>
  1346. <Parameters address="0x50022068" name="FLASH_WRP2AR" size="0x4"/>
  1347. <AssignedBits>
  1348. <Bit config="2">
  1349. <Name>WRP2A_PSTRT</Name>
  1350. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1351. <BitOffset>0x0</BitOffset>
  1352. <BitWidth>0x7</BitWidth>
  1353. <Access>RW</Access>
  1354. <Equation multiplier="0x4000" offset="0x08100000"/>
  1355. </Bit>
  1356. <Bit config="3">
  1357. <Name>WRP2A_PSTRT</Name>
  1358. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1359. <BitOffset>0x0</BitOffset>
  1360. <BitWidth>0x7</BitWidth>
  1361. <Access>RW</Access>
  1362. <Equation multiplier="0x2000" offset="0x08100000"/>
  1363. </Bit>
  1364. <Bit config="2">
  1365. <Name>WRP2A_PEND</Name>
  1366. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1367. <BitOffset>0x10</BitOffset>
  1368. <BitWidth>0x7</BitWidth>
  1369. <Access>RW</Access>
  1370. <Equation multiplier="0x4000" offset="0x08100000"/>
  1371. </Bit>
  1372. <Bit config="3">
  1373. <Name>WRP2A_PEND</Name>
  1374. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1375. <BitOffset>0x10</BitOffset>
  1376. <BitWidth>0x7</BitWidth>
  1377. <Access>RW</Access>
  1378. <Equation multiplier="0x2000" offset="0x08100000"/>
  1379. </Bit>
  1380. <Bit>
  1381. <Name>UNLOCK_2A</Name>
  1382. <Description>Bank 2 WPR first area A unlock</Description>
  1383. <BitOffset>0x1F</BitOffset>
  1384. <BitWidth>0x1</BitWidth>
  1385. <Access>RW</Access>
  1386. <Values>
  1387. <Val value="0x0">WRP2A start and end pages locked</Val>
  1388. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  1389. </Values>
  1390. </Bit>
  1391. </AssignedBits>
  1392. </Field>
  1393. <Field>
  1394. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  1395. <AssignedBits>
  1396. <Bit config="2">
  1397. <Name>WRP2B_PSTRT</Name>
  1398. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1399. <BitOffset>0x0</BitOffset>
  1400. <BitWidth>0x7</BitWidth>
  1401. <Access>RW</Access>
  1402. <Equation multiplier="0x4000" offset="0x08100000"/>
  1403. </Bit>
  1404. <Bit config="3">
  1405. <Name>WRP2B_PSTRT</Name>
  1406. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1407. <BitOffset>0x0</BitOffset>
  1408. <BitWidth>0x7</BitWidth>
  1409. <Access>RW</Access>
  1410. <Equation multiplier="0x2000" offset="0x08100000"/>
  1411. </Bit>
  1412. <Bit config="2">
  1413. <Name>WRP2B_PEND</Name>
  1414. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1415. <BitOffset>0x10</BitOffset>
  1416. <BitWidth>0x7</BitWidth>
  1417. <Access>RW</Access>
  1418. <Equation multiplier="0x4000" offset="0x08100000"/>
  1419. </Bit>
  1420. <Bit config="3">
  1421. <Name>WRP2B_PEND</Name>
  1422. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1423. <BitOffset>0x10</BitOffset>
  1424. <BitWidth>0x7</BitWidth>
  1425. <Access>RW</Access>
  1426. <Equation multiplier="0x2000" offset="0x08100000"/>
  1427. </Bit>
  1428. <Bit>
  1429. <Name>UNLOCK_2B</Name>
  1430. <Description>Bank 2 WPR first area B unlock</Description>
  1431. <BitOffset>0x1F</BitOffset>
  1432. <BitWidth>0x1</BitWidth>
  1433. <Access>RW</Access>
  1434. <Values>
  1435. <Val value="0x0">WRP2B start and end pages locked</Val>
  1436. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  1437. </Values>
  1438. </Bit>
  1439. </AssignedBits>
  1440. </Field>
  1441. </Category>
  1442. </Bank>
  1443. </Configuration>
  1444. <Configuration config="4,5">
  1445. <Bank interface="JTAG_SWD">
  1446. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  1447. <Category>
  1448. <Name>Read Out Protection</Name>
  1449. <Field>
  1450. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1451. <AssignedBits>
  1452. <Bit>
  1453. <Name>RDP</Name>
  1454. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1455. <BitOffset>0x0</BitOffset>
  1456. <BitWidth>0x8</BitWidth>
  1457. <Access>RW</Access>
  1458. <Values>
  1459. <Val value="0xAA">Level 0, no protection</Val>
  1460. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1461. <Val value="0xDC">Level 1, read protection of memories</Val>
  1462. <Val value="0xCC">Level 2, chip protection</Val>
  1463. </Values>
  1464. </Bit>
  1465. </AssignedBits>
  1466. </Field>
  1467. </Category>
  1468. <Category>
  1469. <Name>BOR Level</Name>
  1470. <Field>
  1471. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1472. <AssignedBits>
  1473. <Bit>
  1474. <Name>BOR_LEV</Name>
  1475. <Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
  1476. <BitOffset>0x8</BitOffset>
  1477. <BitWidth>0x3</BitWidth>
  1478. <Access>RW</Access>
  1479. <Values>
  1480. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1481. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1482. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1483. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1484. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1485. </Values>
  1486. </Bit>
  1487. </AssignedBits>
  1488. </Field>
  1489. </Category>
  1490. <Category>
  1491. <Name>User Configuration</Name>
  1492. <Field>
  1493. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1494. <AssignedBits>
  1495. <Bit>
  1496. <Name>TZEN</Name>
  1497. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  1498. <BitOffset>0x1F</BitOffset>
  1499. <BitWidth>0x1</BitWidth>
  1500. <Access>RW</Access>
  1501. <Values>
  1502. <Val value="0x0">Global TrustZone security disabled</Val>
  1503. <Val value="0x1">Global TrustZone security enabled</Val>
  1504. </Values>
  1505. </Bit>
  1506. <Bit>
  1507. <Name>nRST_STOP</Name>
  1508. <Description/>
  1509. <BitOffset>0xC</BitOffset>
  1510. <BitWidth>0x1</BitWidth>
  1511. <Access>RW</Access>
  1512. <Values>
  1513. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1514. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1515. </Values>
  1516. </Bit>
  1517. <Bit>
  1518. <Name>nRST_STDBY</Name>
  1519. <Description/>
  1520. <BitOffset>0xD</BitOffset>
  1521. <BitWidth>0x1</BitWidth>
  1522. <Access>RW</Access>
  1523. <Values>
  1524. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1525. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1526. </Values>
  1527. </Bit>
  1528. <Bit>
  1529. <Name>nRST_SHDW</Name>
  1530. <Description/>
  1531. <BitOffset>0xE</BitOffset>
  1532. <BitWidth>0x1</BitWidth>
  1533. <Access>RW</Access>
  1534. <Values>
  1535. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1536. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1537. </Values>
  1538. </Bit>
  1539. <Bit>
  1540. <Name>SRAM134_RST</Name>
  1541. <Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
  1542. <BitOffset>0xF</BitOffset>
  1543. <BitWidth>0x1</BitWidth>
  1544. <Access>RW</Access>
  1545. <Values>
  1546. <Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
  1547. <Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
  1548. </Values>
  1549. </Bit>
  1550. <Bit>
  1551. <Name>IWDG_SW</Name>
  1552. <Description/>
  1553. <BitOffset>0x10</BitOffset>
  1554. <BitWidth>0x1</BitWidth>
  1555. <Access>RW</Access>
  1556. <Values>
  1557. <Val value="0x0">Hardware independant watchdog</Val>
  1558. <Val value="0x1">Software independant watchdog</Val>
  1559. </Values>
  1560. </Bit>
  1561. <Bit>
  1562. <Name>IWDG_STOP</Name>
  1563. <Description/>
  1564. <BitOffset>0x11</BitOffset>
  1565. <BitWidth>0x1</BitWidth>
  1566. <Access>RW</Access>
  1567. <Values>
  1568. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1569. <Val value="0x1">IWDG counter active in stop mode</Val>
  1570. </Values>
  1571. </Bit>
  1572. <Bit>
  1573. <Name>IWDG_STDBY</Name>
  1574. <Description/>
  1575. <BitOffset>0x12</BitOffset>
  1576. <BitWidth>0x1</BitWidth>
  1577. <Access>RW</Access>
  1578. <Values>
  1579. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1580. <Val value="0x1">IWDG counter active in standby mode</Val>
  1581. </Values>
  1582. </Bit>
  1583. <Bit>
  1584. <Name>WWDG_SW</Name>
  1585. <Description/>
  1586. <BitOffset>0x13</BitOffset>
  1587. <BitWidth>0x1</BitWidth>
  1588. <Access>RW</Access>
  1589. <Values>
  1590. <Val value="0x0">Hardware window watchdog</Val>
  1591. <Val value="0x1">Software window watchdog</Val>
  1592. </Values>
  1593. </Bit>
  1594. <Bit>
  1595. <Name>SWAP_BANK</Name>
  1596. <Description/>
  1597. <BitOffset>0x14</BitOffset>
  1598. <BitWidth>0x1</BitWidth>
  1599. <Access>RW</Access>
  1600. <Values>
  1601. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1602. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1603. </Values>
  1604. </Bit>
  1605. <Bit>
  1606. <Name>DBANK</Name>
  1607. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  1608. <BitOffset>0x15</BitOffset>
  1609. <BitWidth>0x1</BitWidth>
  1610. <Access>RW</Access>
  1611. <Values>
  1612. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1613. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1614. </Values>
  1615. </Bit>
  1616. <Bit>
  1617. <Name>SRAM2_PE</Name>
  1618. <Description>SRAM2 parity check enable</Description>
  1619. <BitOffset>0x18</BitOffset>
  1620. <BitWidth>0x1</BitWidth>
  1621. <Access>RW</Access>
  1622. <Values>
  1623. <Val value="0x0">SRAM2 parity check enable</Val>
  1624. <Val value="0x1">SRAM2 parity check disable</Val>
  1625. </Values>
  1626. </Bit>
  1627. <Bit>
  1628. <Name>SRAM2_RST</Name>
  1629. <Description>SRAM2 Erase when system reset</Description>
  1630. <BitOffset>0x19</BitOffset>
  1631. <BitWidth>0x1</BitWidth>
  1632. <Access>RW</Access>
  1633. <Values>
  1634. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1635. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1636. </Values>
  1637. </Bit>
  1638. <Bit>
  1639. <Name>nSWBOOT0</Name>
  1640. <Description>Software BOOT0</Description>
  1641. <BitOffset>0x1A</BitOffset>
  1642. <BitWidth>0x1</BitWidth>
  1643. <Access>RW</Access>
  1644. <Values>
  1645. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1646. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1647. </Values>
  1648. </Bit>
  1649. <Bit>
  1650. <Name>nBOOT0</Name>
  1651. <Description>nBOOT0 option bit</Description>
  1652. <BitOffset>0x1B</BitOffset>
  1653. <BitWidth>0x1</BitWidth>
  1654. <Access>RW</Access>
  1655. <Values>
  1656. <Val value="0x0">nBOOT0 = 0</Val>
  1657. <Val value="0x1">nBOOT0 = 1</Val>
  1658. </Values>
  1659. </Bit>
  1660. <Bit>
  1661. <Name>PA15_PUPEN</Name>
  1662. <Description>PA15 pull-up enable</Description>
  1663. <BitOffset>0x1C</BitOffset>
  1664. <BitWidth>0x1</BitWidth>
  1665. <Access>RW</Access>
  1666. <Values>
  1667. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1668. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1669. </Values>
  1670. </Bit>
  1671. <Bit>
  1672. <Name>BKPRAM_ECC</Name>
  1673. <Description>SRAM2 parity check enable</Description>
  1674. <BitOffset>0x16</BitOffset>
  1675. <BitWidth>0x1</BitWidth>
  1676. <Access>RW</Access>
  1677. <Values>
  1678. <Val value="0x0">Backup RAM ECC check enabled</Val>
  1679. <Val value="0x1">Backup RAM ECC check disabled</Val>
  1680. </Values>
  1681. </Bit>
  1682. <Bit>
  1683. <Name>SRAM3_ECC</Name>
  1684. <Description>SRAM3 ECC detection and correction enable</Description>
  1685. <BitOffset>0x17</BitOffset>
  1686. <BitWidth>0x1</BitWidth>
  1687. <Access>RW</Access>
  1688. <Values>
  1689. <Val value="0x0">SRAM3 ECC check enabled</Val>
  1690. <Val value="0x1">SRAM3 ECC check disabled</Val>
  1691. </Values>
  1692. </Bit>
  1693. <Bit>
  1694. <Name>SRAM2_ECC</Name>
  1695. <Description>SRAM2 ECC detection and correction enable</Description>
  1696. <BitOffset>0x18</BitOffset>
  1697. <BitWidth>0x1</BitWidth>
  1698. <Access>RW</Access>
  1699. <Values>
  1700. <Val value="0x0">SRAM2 ECC check enabled</Val>
  1701. <Val value="0x1">SRAM2 ECC check disabled</Val>
  1702. </Values>
  1703. </Bit>
  1704. <Bit>
  1705. <Name>IO_VDD_HSLV</Name>
  1706. <Description>High-speed IO at low VDD voltage configuration bit</Description>
  1707. <BitOffset>0x1D</BitOffset>
  1708. <BitWidth>0x1</BitWidth>
  1709. <Access>RW</Access>
  1710. <Values>
  1711. <Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
  1712. <Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
  1713. </Values>
  1714. </Bit>
  1715. <Bit>
  1716. <Name>IO_VDDIO2_HSLV</Name>
  1717. <Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
  1718. <BitOffset>0x1E</BitOffset>
  1719. <BitWidth>0x1</BitWidth>
  1720. <Access>RW</Access>
  1721. <Values>
  1722. <Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
  1723. <Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
  1724. </Values>
  1725. </Bit>
  1726. </AssignedBits>
  1727. </Field>
  1728. </Category>
  1729. <Category>
  1730. <Name>Boot Configuration</Name>
  1731. <Field>
  1732. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1733. <AssignedBits>
  1734. <Bit>
  1735. <Name>NSBOOTADD0</Name>
  1736. <Description>Non-secure Boot base address 0</Description>
  1737. <BitOffset>0x7</BitOffset>
  1738. <BitWidth>0x19</BitWidth>
  1739. <Access>RW</Access>
  1740. <Equation multiplier="0x80" offset="0x0000000"/>
  1741. </Bit>
  1742. </AssignedBits>
  1743. </Field>
  1744. <Field>
  1745. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1746. <AssignedBits>
  1747. <Bit>
  1748. <Name>NSBOOTADD1</Name>
  1749. <Description>Non-secure Boot base address 1</Description>
  1750. <BitOffset>0x7</BitOffset>
  1751. <BitWidth>0x19</BitWidth>
  1752. <Access>RW</Access>
  1753. <Equation multiplier="0x80" offset="0x0000000"/>
  1754. </Bit>
  1755. </AssignedBits>
  1756. </Field>
  1757. <Field>
  1758. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  1759. <AssignedBits>
  1760. <Bit>
  1761. <Name>SECBOOTADD0</Name>
  1762. <Description>Secure boot base address 0</Description>
  1763. <BitOffset>0x7</BitOffset>
  1764. <BitWidth>0x19</BitWidth>
  1765. <Access>RW</Access>
  1766. <Equation multiplier="0x80" offset="0x0000000"/>
  1767. </Bit>
  1768. </AssignedBits>
  1769. </Field>
  1770. <Field>
  1771. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1772. <AssignedBits>
  1773. <Bit>
  1774. <Name>BOOT_LOCK</Name>
  1775. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1776. <BitOffset>0x0</BitOffset>
  1777. <BitWidth>0x1</BitWidth>
  1778. <Access>RW</Access>
  1779. <Values>
  1780. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1781. <Val value="0x1">Boot forced from base address memory</Val>
  1782. </Values>
  1783. </Bit>
  1784. </AssignedBits>
  1785. </Field>
  1786. </Category>
  1787. <Category>
  1788. <Name>Secure Area 1</Name>
  1789. <Field>
  1790. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  1791. <AssignedBits>
  1792. <Bit config="4">
  1793. <Name>SECWM1_PSTRT</Name>
  1794. <Description>Start page of first secure area</Description>
  1795. <BitOffset>0x0</BitOffset>
  1796. <BitWidth>0x7</BitWidth>
  1797. <Access>RW</Access>
  1798. <Equation multiplier="0x4000" offset="0x08000000"/>
  1799. </Bit>
  1800. <Bit config="5">
  1801. <Name>SECWM1_PSTRT</Name>
  1802. <Description>Start page of first secure area</Description>
  1803. <BitOffset>0x0</BitOffset>
  1804. <BitWidth>0x7</BitWidth>
  1805. <Access>RW</Access>
  1806. <Equation multiplier="0x2000" offset="0x08000000"/>
  1807. </Bit>
  1808. <Bit config="4">
  1809. <Name>SECWM1_PEND</Name>
  1810. <Description>End page of first secure area</Description>
  1811. <BitOffset>0x10</BitOffset>
  1812. <BitWidth>0x7</BitWidth>
  1813. <Access>RW</Access>
  1814. <Equation multiplier="0x4000" offset="0x08000000"/>
  1815. </Bit>
  1816. <Bit config="5">
  1817. <Name>SECWM1_PEND</Name>
  1818. <Description>End page of first secure area</Description>
  1819. <BitOffset>0x10</BitOffset>
  1820. <BitWidth>0x7</BitWidth>
  1821. <Access>RW</Access>
  1822. <Equation multiplier="0x2000" offset="0x08000000"/>
  1823. </Bit>
  1824. </AssignedBits>
  1825. </Field>
  1826. <Field>
  1827. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  1828. <AssignedBits>
  1829. <Bit config="4">
  1830. <Name>HDP1_PEND</Name>
  1831. <Description>End page of first hide protection area</Description>
  1832. <BitOffset>0x10</BitOffset>
  1833. <BitWidth>0x7</BitWidth>
  1834. <Access>RW</Access>
  1835. <Equation multiplier="0x4000" offset="0xC003fff"/>
  1836. </Bit>
  1837. <Bit config="5">
  1838. <Name>HDP1_PEND</Name>
  1839. <Description>End page of first hide protection area</Description>
  1840. <BitOffset>0x10</BitOffset>
  1841. <BitWidth>0x7</BitWidth>
  1842. <Access>RW</Access>
  1843. <Equation multiplier="0x2000" offset="0xC001fff"/>
  1844. </Bit>
  1845. <Bit>
  1846. <Name>HDP1EN</Name>
  1847. <Description>Hide protection first area enable</Description>
  1848. <BitOffset>0x1F</BitOffset>
  1849. <BitWidth>0x1</BitWidth>
  1850. <Access>RW</Access>
  1851. <Values>
  1852. <Val value="0x0">No HDP area 1</Val>
  1853. <Val value="0x1">HDP first area is enabled</Val>
  1854. </Values>
  1855. </Bit>
  1856. </AssignedBits>
  1857. </Field>
  1858. </Category>
  1859. <Category>
  1860. <Name>Write Protection 1</Name>
  1861. <Field>
  1862. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  1863. <AssignedBits>
  1864. <Bit config="4">
  1865. <Name>WRP1A_PSTRT</Name>
  1866. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1867. <BitOffset>0x0</BitOffset>
  1868. <BitWidth>0x7</BitWidth>
  1869. <Access>RW</Access>
  1870. <Equation multiplier="0x4000" offset="0x08000000"/>
  1871. </Bit>
  1872. <Bit config="5">
  1873. <Name>WRP1A_PSTRT</Name>
  1874. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1875. <BitOffset>0x0</BitOffset>
  1876. <BitWidth>0x7</BitWidth>
  1877. <Access>RW</Access>
  1878. <Equation multiplier="0x2000" offset="0x08000000"/>
  1879. </Bit>
  1880. <Bit config="4">
  1881. <Name>WRP1A_PEND</Name>
  1882. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1883. <BitOffset>0x10</BitOffset>
  1884. <BitWidth>0x7</BitWidth>
  1885. <Access>RW</Access>
  1886. <Equation multiplier="0x4000" offset="0x08000000"/>
  1887. </Bit>
  1888. <Bit config="5">
  1889. <Name>WRP1A_PEND</Name>
  1890. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1891. <BitOffset>0x10</BitOffset>
  1892. <BitWidth>0x7</BitWidth>
  1893. <Access>RW</Access>
  1894. <Equation multiplier="0x2000" offset="0x08000000"/>
  1895. </Bit>
  1896. <Bit>
  1897. <Name>UNLOCK_1A</Name>
  1898. <Description>Bank 1 WPR first area A unlock</Description>
  1899. <BitOffset>0x1F</BitOffset>
  1900. <BitWidth>0x1</BitWidth>
  1901. <Access>RW</Access>
  1902. <Values>
  1903. <Val value="0x0">WRP1A start and end pages locked</Val>
  1904. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  1905. </Values>
  1906. </Bit>
  1907. </AssignedBits>
  1908. </Field>
  1909. <Field>
  1910. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  1911. <AssignedBits>
  1912. <Bit config="4">
  1913. <Name>WRP1B_PSTRT</Name>
  1914. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1915. <BitOffset>0x0</BitOffset>
  1916. <BitWidth>0x7</BitWidth>
  1917. <Access>RW</Access>
  1918. <Equation multiplier="0x4000" offset="0x08000000"/>
  1919. </Bit>
  1920. <Bit config="5">
  1921. <Name>WRP1B_PSTRT</Name>
  1922. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1923. <BitOffset>0x0</BitOffset>
  1924. <BitWidth>0x7</BitWidth>
  1925. <Access>RW</Access>
  1926. <Equation multiplier="0x2000" offset="0x08000000"/>
  1927. </Bit>
  1928. <Bit config="4">
  1929. <Name>WRP1B_PEND</Name>
  1930. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1931. <BitOffset>0x10</BitOffset>
  1932. <BitWidth>0x7</BitWidth>
  1933. <Access>RW</Access>
  1934. <Equation multiplier="0x4000" offset="0x08000000"/>
  1935. </Bit>
  1936. <Bit config="5">
  1937. <Name>WRP1B_PEND</Name>
  1938. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1939. <BitOffset>0x10</BitOffset>
  1940. <BitWidth>0x7</BitWidth>
  1941. <Access>RW</Access>
  1942. <Equation multiplier="0x2000" offset="0x08000000"/>
  1943. </Bit>
  1944. <Bit>
  1945. <Name>UNLOCK_1B</Name>
  1946. <Description>Bank 1 WPR first area B unlock</Description>
  1947. <BitOffset>0x1F</BitOffset>
  1948. <BitWidth>0x1</BitWidth>
  1949. <Access>RW</Access>
  1950. <Values>
  1951. <Val value="0x0">WRP1B start and end pages locked</Val>
  1952. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  1953. </Values>
  1954. </Bit>
  1955. </AssignedBits>
  1956. </Field>
  1957. </Category>
  1958. </Bank>
  1959. <Bank interface="JTAG_SWD">
  1960. <Parameters address="0x40022060" name="Bank 2" size="0x8"/>
  1961. <Category>
  1962. <Name>Secure Area 2</Name>
  1963. <Field>
  1964. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  1965. <AssignedBits>
  1966. <Bit config="4">
  1967. <Name>SECWM2_PSTRT</Name>
  1968. <Description>Start page of second secure area</Description>
  1969. <BitOffset>0x0</BitOffset>
  1970. <BitWidth>0x7</BitWidth>
  1971. <Access>RW</Access>
  1972. <Equation multiplier="0x4000" offset="0x08000000"/>
  1973. </Bit>
  1974. <Bit config="5">
  1975. <Name>SECWM2_PSTRT</Name>
  1976. <Description>Start page of second secure area</Description>
  1977. <BitOffset>0x0</BitOffset>
  1978. <BitWidth>0x7</BitWidth>
  1979. <Access>RW</Access>
  1980. <Equation multiplier="0x2000" offset="0x08100000"/>
  1981. </Bit>
  1982. <Bit config="4">
  1983. <Name>SECWM2_PEND</Name>
  1984. <Description>End page of second secure area</Description>
  1985. <BitOffset>0x10</BitOffset>
  1986. <BitWidth>0x7</BitWidth>
  1987. <Access>RW</Access>
  1988. <Equation multiplier="0x4000" offset="0x08000000"/>
  1989. </Bit>
  1990. <Bit config="5">
  1991. <Name>SECWM2_PEND</Name>
  1992. <Description>End page of second secure area</Description>
  1993. <BitOffset>0x10</BitOffset>
  1994. <BitWidth>0x7</BitWidth>
  1995. <Access>RW</Access>
  1996. <Equation multiplier="0x2000" offset="0x08100000"/>
  1997. </Bit>
  1998. </AssignedBits>
  1999. </Field>
  2000. <Field>
  2001. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2002. <AssignedBits>
  2003. <Bit config="4">
  2004. <Name>HDP2_PEND</Name>
  2005. <Description>End page of second hide protection area</Description>
  2006. <BitOffset>0x10</BitOffset>
  2007. <BitWidth>0x7</BitWidth>
  2008. <Access>RW</Access>
  2009. <Equation multiplier="0x4000" offset="0xC103FFF"/>
  2010. </Bit>
  2011. <Bit config="5">
  2012. <Name>HDP2_PEND</Name>
  2013. <Description>End page of second hide protection area</Description>
  2014. <BitOffset>0x10</BitOffset>
  2015. <BitWidth>0x7</BitWidth>
  2016. <Access>RW</Access>
  2017. <Equation multiplier="0x2000" offset="0xC101FFF"/>
  2018. </Bit>
  2019. <Bit>
  2020. <Name>HDP2EN</Name>
  2021. <Description>Hide protection second area enable</Description>
  2022. <BitOffset>0x1F</BitOffset>
  2023. <BitWidth>0x1</BitWidth>
  2024. <Access>RW</Access>
  2025. <Values>
  2026. <Val value="0x0">No HDP area 2</Val>
  2027. <Val value="0x1">HDP second area is enabled</Val>
  2028. </Values>
  2029. </Bit>
  2030. </AssignedBits>
  2031. </Field>
  2032. </Category>
  2033. </Bank>
  2034. <Bank interface="JTAG_SWD">
  2035. <Parameters address="0x40022068" name="Bank 3" size="0x8"/>
  2036. <Category>
  2037. <Name>Write Protection 2</Name>
  2038. <Field>
  2039. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2040. <AssignedBits>
  2041. <Bit config="4">
  2042. <Name>WRP2A_PSTRT</Name>
  2043. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2044. <BitOffset>0x0</BitOffset>
  2045. <BitWidth>0x7</BitWidth>
  2046. <Access>RW</Access>
  2047. <Equation multiplier="0x4000" offset="0x08100000"/>
  2048. </Bit>
  2049. <Bit config="5">
  2050. <Name>WRP2A_PSTRT</Name>
  2051. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2052. <BitOffset>0x0</BitOffset>
  2053. <BitWidth>0x7</BitWidth>
  2054. <Access>RW</Access>
  2055. <Equation multiplier="0x2000" offset="0x08100000"/>
  2056. </Bit>
  2057. <Bit config="4">
  2058. <Name>WRP2A_PEND</Name>
  2059. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2060. <BitOffset>0x10</BitOffset>
  2061. <BitWidth>0x7</BitWidth>
  2062. <Access>RW</Access>
  2063. <Equation multiplier="0x4000" offset="0x08100000"/>
  2064. </Bit>
  2065. <Bit config="5">
  2066. <Name>WRP2A_PEND</Name>
  2067. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2068. <BitOffset>0x10</BitOffset>
  2069. <BitWidth>0x7</BitWidth>
  2070. <Access>RW</Access>
  2071. <Equation multiplier="0x2000" offset="0x08100000"/>
  2072. </Bit>
  2073. <Bit>
  2074. <Name>UNLOCK_2A</Name>
  2075. <Description>Bank 2 WPR first area A unlock</Description>
  2076. <BitOffset>0x1F</BitOffset>
  2077. <BitWidth>0x1</BitWidth>
  2078. <Access>RW</Access>
  2079. <Values>
  2080. <Val value="0x0">WRP2A start and end pages locked</Val>
  2081. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2082. </Values>
  2083. </Bit>
  2084. </AssignedBits>
  2085. </Field>
  2086. <Field>
  2087. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2088. <AssignedBits>
  2089. <Bit config="4">
  2090. <Name>WRP2B_PSTRT</Name>
  2091. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2092. <BitOffset>0x0</BitOffset>
  2093. <BitWidth>0x7</BitWidth>
  2094. <Access>RW</Access>
  2095. <Equation multiplier="0x4000" offset="0x08100000"/>
  2096. </Bit>
  2097. <Bit config="5">
  2098. <Name>WRP2B_PSTRT</Name>
  2099. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2100. <BitOffset>0x0</BitOffset>
  2101. <BitWidth>0x7</BitWidth>
  2102. <Access>RW</Access>
  2103. <Equation multiplier="0x2000" offset="0x08100000"/>
  2104. </Bit>
  2105. <Bit config="4">
  2106. <Name>WRP2B_PEND</Name>
  2107. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2108. <BitOffset>0x10</BitOffset>
  2109. <BitWidth>0x7</BitWidth>
  2110. <Access>RW</Access>
  2111. <Equation multiplier="0x4000" offset="0x08100000"/>
  2112. </Bit>
  2113. <Bit config="5">
  2114. <Name>WRP2B_PEND</Name>
  2115. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2116. <BitOffset>0x10</BitOffset>
  2117. <BitWidth>0x7</BitWidth>
  2118. <Access>RW</Access>
  2119. <Equation multiplier="0x2000" offset="0x08100000"/>
  2120. </Bit>
  2121. <Bit>
  2122. <Name>UNLOCK_2B</Name>
  2123. <Description>Bank 2 WPR first area B unlock</Description>
  2124. <BitOffset>0x1F</BitOffset>
  2125. <BitWidth>0x1</BitWidth>
  2126. <Access>RW</Access>
  2127. <Values>
  2128. <Val value="0x0">WRP2B start and end pages locked</Val>
  2129. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2130. </Values>
  2131. </Bit>
  2132. </AssignedBits>
  2133. </Field>
  2134. </Category>
  2135. </Bank>
  2136. </Configuration>
  2137. <Bank interface="Bootloader">
  2138. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  2139. <Category>
  2140. <Name>Read Out Protection</Name>
  2141. <Field>
  2142. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2143. <AssignedBits>
  2144. <Bit>
  2145. <Name>RDP</Name>
  2146. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  2147. <BitOffset>0x0</BitOffset>
  2148. <BitWidth>0x8</BitWidth>
  2149. <Access>RW</Access>
  2150. <Values>
  2151. <Val value="0xAA">Level 0, no protection</Val>
  2152. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  2153. <Val value="0xDC">Level 1, read protection of memories</Val>
  2154. <Val value="0xCC">Level 2, chip protection</Val>
  2155. </Values>
  2156. </Bit>
  2157. </AssignedBits>
  2158. </Field>
  2159. </Category>
  2160. <Category>
  2161. <Name>BOR Level</Name>
  2162. <Field>
  2163. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2164. <AssignedBits>
  2165. <Bit>
  2166. <Name>BOR_LEV</Name>
  2167. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  2168. <BitOffset>0x8</BitOffset>
  2169. <BitWidth>0x3</BitWidth>
  2170. <Access>RW</Access>
  2171. <Values>
  2172. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  2173. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  2174. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  2175. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  2176. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  2177. </Values>
  2178. </Bit>
  2179. </AssignedBits>
  2180. </Field>
  2181. </Category>
  2182. <Category>
  2183. <Name>User Configuration</Name>
  2184. <Field>
  2185. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2186. <AssignedBits>
  2187. <Bit>
  2188. <Name>TZEN</Name>
  2189. <Description>Global TrustZone security enable. disable this OB by Unchecking TZEN + RDP regression from level 1 to 0 simultaneously</Description>
  2190. <BitOffset>0x1F</BitOffset>
  2191. <BitWidth>0x1</BitWidth>
  2192. <Access>RW</Access>
  2193. <Values>
  2194. <Val value="0x0">Global TrustZone security disabled</Val>
  2195. <Val value="0x1">Global TrustZone security enabled</Val>
  2196. </Values>
  2197. </Bit>
  2198. <Bit>
  2199. <Name>nRST_STOP</Name>
  2200. <Description/>
  2201. <BitOffset>0xC</BitOffset>
  2202. <BitWidth>0x1</BitWidth>
  2203. <Access>RW</Access>
  2204. <Values>
  2205. <Val value="0x0">Reset generated when entering Stop mode</Val>
  2206. <Val value="0x1">No reset generated when entering Stop mode</Val>
  2207. </Values>
  2208. </Bit>
  2209. <Bit>
  2210. <Name>nRST_STDBY</Name>
  2211. <Description/>
  2212. <BitOffset>0xD</BitOffset>
  2213. <BitWidth>0x1</BitWidth>
  2214. <Access>RW</Access>
  2215. <Values>
  2216. <Val value="0x0">Reset generated when entering Standby mode</Val>
  2217. <Val value="0x1">No reset generated when entering Standby mode</Val>
  2218. </Values>
  2219. </Bit>
  2220. <Bit>
  2221. <Name>nRST_SHDW</Name>
  2222. <Description/>
  2223. <BitOffset>0xE</BitOffset>
  2224. <BitWidth>0x1</BitWidth>
  2225. <Access>RW</Access>
  2226. <Values>
  2227. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  2228. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  2229. </Values>
  2230. </Bit>
  2231. <Bit>
  2232. <Name>IWDG_SW</Name>
  2233. <Description/>
  2234. <BitOffset>0x10</BitOffset>
  2235. <BitWidth>0x1</BitWidth>
  2236. <Access>RW</Access>
  2237. <Values>
  2238. <Val value="0x0">Hardware independant watchdog</Val>
  2239. <Val value="0x1">Software independant watchdog</Val>
  2240. </Values>
  2241. </Bit>
  2242. <Bit>
  2243. <Name>IWDG_STOP</Name>
  2244. <Description/>
  2245. <BitOffset>0x11</BitOffset>
  2246. <BitWidth>0x1</BitWidth>
  2247. <Access>RW</Access>
  2248. <Values>
  2249. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  2250. <Val value="0x1">IWDG counter active in stop mode</Val>
  2251. </Values>
  2252. </Bit>
  2253. <Bit>
  2254. <Name>IWDG_STDBY</Name>
  2255. <Description/>
  2256. <BitOffset>0x12</BitOffset>
  2257. <BitWidth>0x1</BitWidth>
  2258. <Access>RW</Access>
  2259. <Values>
  2260. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  2261. <Val value="0x1">IWDG counter active in standby mode</Val>
  2262. </Values>
  2263. </Bit>
  2264. <Bit>
  2265. <Name>WWDG_SW</Name>
  2266. <Description/>
  2267. <BitOffset>0x13</BitOffset>
  2268. <BitWidth>0x1</BitWidth>
  2269. <Access>RW</Access>
  2270. <Values>
  2271. <Val value="0x0">Hardware window watchdog</Val>
  2272. <Val value="0x1">Software window watchdog</Val>
  2273. </Values>
  2274. </Bit>
  2275. <Bit>
  2276. <Name>SWAP_BANK</Name>
  2277. <Description/>
  2278. <BitOffset>0x14</BitOffset>
  2279. <BitWidth>0x1</BitWidth>
  2280. <Access>RW</Access>
  2281. <Values>
  2282. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  2283. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  2284. </Values>
  2285. </Bit>
  2286. <Bit>
  2287. <Name>DB256</Name>
  2288. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  2289. <BitOffset>0x15</BitOffset>
  2290. <BitWidth>0x1</BitWidth>
  2291. <Access>RW</Access>
  2292. <Values>
  2293. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  2294. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  2295. </Values>
  2296. </Bit>
  2297. <Bit>
  2298. <Name>DBANK</Name>
  2299. <Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
  2300. <BitOffset>0x16</BitOffset>
  2301. <BitWidth>0x1</BitWidth>
  2302. <Access>RW</Access>
  2303. <Values>
  2304. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  2305. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  2306. </Values>
  2307. </Bit>
  2308. <Bit>
  2309. <Name>SRAM2_PE</Name>
  2310. <Description>SRAM2 parity check enable</Description>
  2311. <BitOffset>0x18</BitOffset>
  2312. <BitWidth>0x1</BitWidth>
  2313. <Access>RW</Access>
  2314. <Values>
  2315. <Val value="0x0">SRAM2 parity check enable</Val>
  2316. <Val value="0x1">SRAM2 parity check disable</Val>
  2317. </Values>
  2318. </Bit>
  2319. <Bit>
  2320. <Name>SRAM2_RST</Name>
  2321. <Description>SRAM2 Erase when system reset</Description>
  2322. <BitOffset>0x19</BitOffset>
  2323. <BitWidth>0x1</BitWidth>
  2324. <Access>RW</Access>
  2325. <Values>
  2326. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  2327. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  2328. </Values>
  2329. </Bit>
  2330. <Bit>
  2331. <Name>nSWBOOT0</Name>
  2332. <Description>Software BOOT0</Description>
  2333. <BitOffset>0x1A</BitOffset>
  2334. <BitWidth>0x1</BitWidth>
  2335. <Access>RW</Access>
  2336. <Values>
  2337. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  2338. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  2339. </Values>
  2340. </Bit>
  2341. <Bit>
  2342. <Name>nBOOT0</Name>
  2343. <Description>nBOOT0 option bit</Description>
  2344. <BitOffset>0x1B</BitOffset>
  2345. <BitWidth>0x1</BitWidth>
  2346. <Access>RW</Access>
  2347. <Values>
  2348. <Val value="0x0">nBOOT0 = 0</Val>
  2349. <Val value="0x1">nBOOT0 = 1</Val>
  2350. </Values>
  2351. </Bit>
  2352. <Bit>
  2353. <Name>PA15_PUPEN</Name>
  2354. <Description>PA15 pull-up enable</Description>
  2355. <BitOffset>0x1C</BitOffset>
  2356. <BitWidth>0x1</BitWidth>
  2357. <Access>RW</Access>
  2358. <Values>
  2359. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  2360. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  2361. </Values>
  2362. </Bit>
  2363. </AssignedBits>
  2364. </Field>
  2365. </Category>
  2366. <Category>
  2367. <Name>Boot Configuration</Name>
  2368. <Field>
  2369. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2370. <AssignedBits>
  2371. <Bit>
  2372. <Name>NSBOOTADD0</Name>
  2373. <Description>Non-secure Boot base address 0</Description>
  2374. <BitOffset>0x7</BitOffset>
  2375. <BitWidth>0x19</BitWidth>
  2376. <Access>RW</Access>
  2377. <Equation multiplier="0x80" offset="0x0000000"/>
  2378. </Bit>
  2379. </AssignedBits>
  2380. </Field>
  2381. <Field>
  2382. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2383. <AssignedBits>
  2384. <Bit>
  2385. <Name>NSBOOTADD1</Name>
  2386. <Description>Non-secure Boot base address 1</Description>
  2387. <BitOffset>0x7</BitOffset>
  2388. <BitWidth>0x19</BitWidth>
  2389. <Access>RW</Access>
  2390. <Equation multiplier="0x80" offset="0x0000000"/>
  2391. </Bit>
  2392. </AssignedBits>
  2393. </Field>
  2394. <Field>
  2395. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  2396. <AssignedBits>
  2397. <Bit config="6,7">
  2398. <Name>SECBOOTADD0</Name>
  2399. <Description>Secure boot base address 0</Description>
  2400. <BitOffset>0x7</BitOffset>
  2401. <BitWidth>0x19</BitWidth>
  2402. <Access>RW</Access>
  2403. <Equation multiplier="0x80" offset="0x0000000"/>
  2404. </Bit>
  2405. </AssignedBits>
  2406. </Field>
  2407. <Field>
  2408. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  2409. <AssignedBits>
  2410. <Bit config="6,7">
  2411. <Name>BOOT_LOCK</Name>
  2412. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  2413. <BitOffset>0x0</BitOffset>
  2414. <BitWidth>0x1</BitWidth>
  2415. <Access>RW</Access>
  2416. <Values>
  2417. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  2418. <Val value="0x1">Boot forced from base address memory</Val>
  2419. </Values>
  2420. </Bit>
  2421. </AssignedBits>
  2422. </Field>
  2423. </Category>
  2424. <Category>
  2425. <Name>Secure area 1</Name>
  2426. <Field>
  2427. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  2428. <AssignedBits>
  2429. <Bit config="6">
  2430. <Name>SECWM1_PSTRT</Name>
  2431. <Description>Start page of first secure area</Description>
  2432. <BitOffset>0x0</BitOffset>
  2433. <BitWidth>0x7</BitWidth>
  2434. <Access>RW</Access>
  2435. <Equation multiplier="0x4000" offset="0x08000000"/>
  2436. </Bit>
  2437. <Bit config="7">
  2438. <Name>SECWM1_PSTRT</Name>
  2439. <Description>Start page of first secure area</Description>
  2440. <BitOffset>0x0</BitOffset>
  2441. <BitWidth>0x7</BitWidth>
  2442. <Access>RW</Access>
  2443. <Equation multiplier="0x2000" offset="0x08000000"/>
  2444. </Bit>
  2445. <Bit config="6">
  2446. <Name>SECWM1_PEND</Name>
  2447. <Description>End page of first secure area</Description>
  2448. <BitOffset>0x10</BitOffset>
  2449. <BitWidth>0x7</BitWidth>
  2450. <Access>RW</Access>
  2451. <Equation multiplier="0x4000" offset="0x08000000"/>
  2452. </Bit>
  2453. <Bit config="7">
  2454. <Name>SECWM1_PEND</Name>
  2455. <Description>End page of first secure area</Description>
  2456. <BitOffset>0x10</BitOffset>
  2457. <BitWidth>0x7</BitWidth>
  2458. <Access>RW</Access>
  2459. <Equation multiplier="0x2000" offset="0x08000000"/>
  2460. </Bit>
  2461. </AssignedBits>
  2462. </Field>
  2463. <Field>
  2464. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  2465. <AssignedBits>
  2466. <Bit config="6">
  2467. <Name>HDP1_PEND</Name>
  2468. <Description>End page of first hide protection area</Description>
  2469. <BitOffset>0x10</BitOffset>
  2470. <BitWidth>0x7</BitWidth>
  2471. <Access>RW</Access>
  2472. <Equation multiplier="0x400" offset="0x08000000"/>
  2473. </Bit>
  2474. <Bit config="7">
  2475. <Name>HDP1_PEND</Name>
  2476. <Description>End page of first hide protection area</Description>
  2477. <BitOffset>0x10</BitOffset>
  2478. <BitWidth>0x7</BitWidth>
  2479. <Access>RW</Access>
  2480. <Equation multiplier="0x200" offset="0x08000000"/>
  2481. </Bit>
  2482. <Bit config="6,7">
  2483. <Name>HDP1EN</Name>
  2484. <Description>Hide protection first area enable</Description>
  2485. <BitOffset>0x1F</BitOffset>
  2486. <BitWidth>0x1</BitWidth>
  2487. <Access>RW</Access>
  2488. <Values>
  2489. <Val value="0x0">No HDP area 1</Val>
  2490. <Val value="0x1">HDP first area is enabled</Val>
  2491. </Values>
  2492. </Bit>
  2493. </AssignedBits>
  2494. </Field>
  2495. </Category>
  2496. <Category>
  2497. <Name>Write Protection 1</Name>
  2498. <Field>
  2499. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2500. <AssignedBits>
  2501. <Bit config="6,8">
  2502. <Name>WRP1A_PSTRT</Name>
  2503. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2504. <BitOffset>0x0</BitOffset>
  2505. <BitWidth>0x7</BitWidth>
  2506. <Access>RW</Access>
  2507. <Equation multiplier="0x4000" offset="0x08000000"/>
  2508. </Bit>
  2509. <Bit config="7,9">
  2510. <Name>WRP1A_PSTRT</Name>
  2511. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2512. <BitOffset>0x0</BitOffset>
  2513. <BitWidth>0x7</BitWidth>
  2514. <Access>RW</Access>
  2515. <Equation multiplier="0x2000" offset="0x08000000"/>
  2516. </Bit>
  2517. <Bit config="6,8">
  2518. <Name>WRP1A_PEND</Name>
  2519. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2520. <BitOffset>0x10</BitOffset>
  2521. <BitWidth>0x7</BitWidth>
  2522. <Access>RW</Access>
  2523. <Equation multiplier="0x4000" offset="0x08000000"/>
  2524. </Bit>
  2525. <Bit config="7,9">
  2526. <Name>WRP1A_PEND</Name>
  2527. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2528. <BitOffset>0x10</BitOffset>
  2529. <BitWidth>0x7</BitWidth>
  2530. <Access>RW</Access>
  2531. <Equation multiplier="0x2000" offset="0x08000000"/>
  2532. </Bit>
  2533. <Bit>
  2534. <Name>UNLOCK_1A</Name>
  2535. <Description>Bank 1 WPR first area A unlock</Description>
  2536. <BitOffset>0x1F</BitOffset>
  2537. <BitWidth>0x1</BitWidth>
  2538. <Access>RW</Access>
  2539. <Values>
  2540. <Val value="0x0">WRP1A start and end pages locked</Val>
  2541. <Val value="0x1">WRP1A start and end pages unlocked</Val>
  2542. </Values>
  2543. </Bit>
  2544. </AssignedBits>
  2545. </Field>
  2546. <Field>
  2547. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  2548. <AssignedBits>
  2549. <Bit config="6,8">
  2550. <Name>WRP1B_PSTRT</Name>
  2551. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2552. <BitOffset>0x0</BitOffset>
  2553. <BitWidth>0x7</BitWidth>
  2554. <Access>RW</Access>
  2555. <Equation multiplier="0x4000" offset="0x08000000"/>
  2556. </Bit>
  2557. <Bit config="7,9">
  2558. <Name>WRP1B_PSTRT</Name>
  2559. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2560. <BitOffset>0x0</BitOffset>
  2561. <BitWidth>0x7</BitWidth>
  2562. <Access>RW</Access>
  2563. <Equation multiplier="0x2000" offset="0x08000000"/>
  2564. </Bit>
  2565. <Bit config="6,8">
  2566. <Name>WRP1B_PEND</Name>
  2567. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2568. <BitOffset>0x10</BitOffset>
  2569. <BitWidth>0x7</BitWidth>
  2570. <Access>RW</Access>
  2571. <Equation multiplier="0x4000" offset="0x08000000"/>
  2572. </Bit>
  2573. <Bit config="7,9">
  2574. <Name>WRP1B_PEND</Name>
  2575. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2576. <BitOffset>0x10</BitOffset>
  2577. <BitWidth>0x7</BitWidth>
  2578. <Access>RW</Access>
  2579. <Equation multiplier="0x2000" offset="0x08000000"/>
  2580. </Bit>
  2581. <Bit>
  2582. <Name>UNLOCK_1B</Name>
  2583. <Description>Bank 1 WPR second area B unlock</Description>
  2584. <BitOffset>0x1F</BitOffset>
  2585. <BitWidth>0x1</BitWidth>
  2586. <Access>RW</Access>
  2587. <Values>
  2588. <Val value="0x0">WRP1B start and end pages locked</Val>
  2589. <Val value="0x1">WRP1B start and end pages unlocked</Val>
  2590. </Values>
  2591. </Bit>
  2592. </AssignedBits>
  2593. </Field>
  2594. </Category>
  2595. <Category>
  2596. <Name>Secure area 2</Name>
  2597. <Field>
  2598. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  2599. <AssignedBits>
  2600. <Bit config="6">
  2601. <Name>SECWM2_PSTRT</Name>
  2602. <Description>Start page of second secure area</Description>
  2603. <BitOffset>0x0</BitOffset>
  2604. <BitWidth>0x7</BitWidth>
  2605. <Access>RW</Access>
  2606. <Equation multiplier="0x4000" offset="0x08000000"/>
  2607. </Bit>
  2608. <Bit config="7">
  2609. <Name>SECWM2_PSTRT</Name>
  2610. <Description>Start page of second secure area</Description>
  2611. <BitOffset>0x0</BitOffset>
  2612. <BitWidth>0x7</BitWidth>
  2613. <Access>RW</Access>
  2614. <Equation multiplier="0x2000" offset="0x08100000"/>
  2615. </Bit>
  2616. <Bit config="6">
  2617. <Name>SECWM2_PEND</Name>
  2618. <Description>End page of second secure area</Description>
  2619. <BitOffset>0x10</BitOffset>
  2620. <BitWidth>0x7</BitWidth>
  2621. <Access>RW</Access>
  2622. <Equation multiplier="0x4000" offset="0x08000000"/>
  2623. </Bit>
  2624. <Bit config="7">
  2625. <Name>SECWM2_PEND</Name>
  2626. <Description>End page of second secure area</Description>
  2627. <BitOffset>0x10</BitOffset>
  2628. <BitWidth>0x7</BitWidth>
  2629. <Access>RW</Access>
  2630. <Equation multiplier="0x2000" offset="0x08100000"/>
  2631. </Bit>
  2632. </AssignedBits>
  2633. </Field>
  2634. <Field>
  2635. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2636. <AssignedBits>
  2637. <Bit config="6">
  2638. <Name>HDP2_PEND</Name>
  2639. <Description>End page of second hide protection area</Description>
  2640. <BitOffset>0x10</BitOffset>
  2641. <BitWidth>0x7</BitWidth>
  2642. <Access>RW</Access>
  2643. <Equation multiplier="0x400" offset="0x08000000"/>
  2644. </Bit>
  2645. <Bit config="7">
  2646. <Name>HDP2_PEND</Name>
  2647. <Description>End page of second hide protection area</Description>
  2648. <BitOffset>0x10</BitOffset>
  2649. <BitWidth>0x7</BitWidth>
  2650. <Access>RW</Access>
  2651. <Equation multiplier="0x200" offset="0x08000000"/>
  2652. </Bit>
  2653. <Bit config="6,7">
  2654. <Name>HDP2EN</Name>
  2655. <Description>Hide protection second area enable</Description>
  2656. <BitOffset>0x1F</BitOffset>
  2657. <BitWidth>0x1</BitWidth>
  2658. <Access>RW</Access>
  2659. <Values>
  2660. <Val value="0x0">No HDP area 2</Val>
  2661. <Val value="0x1">HDP second area is enabled</Val>
  2662. </Values>
  2663. </Bit>
  2664. </AssignedBits>
  2665. </Field>
  2666. </Category>
  2667. <Category>
  2668. <Name>Write Protection 2</Name>
  2669. <Field>
  2670. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  2671. <AssignedBits>
  2672. <Bit config="6,8">
  2673. <Name>WRP2A_PSTRT</Name>
  2674. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2675. <BitOffset>0x0</BitOffset>
  2676. <BitWidth>0x7</BitWidth>
  2677. <Access>RW</Access>
  2678. <Equation multiplier="0x4000" offset="0x08000000"/>
  2679. </Bit>
  2680. <Bit config="7,9">
  2681. <Name>WRP2A_PSTRT</Name>
  2682. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2683. <BitOffset>0x0</BitOffset>
  2684. <BitWidth>0x7</BitWidth>
  2685. <Access>RW</Access>
  2686. <Equation multiplier="0x2000" offset="0x08100000"/>
  2687. </Bit>
  2688. <Bit config="6,8">
  2689. <Name>WRP2A_PEND</Name>
  2690. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2691. <BitOffset>0x10</BitOffset>
  2692. <BitWidth>0x7</BitWidth>
  2693. <Access>RW</Access>
  2694. <Equation multiplier="0x4000" offset="0x08000000"/>
  2695. </Bit>
  2696. <Bit config="7,9">
  2697. <Name>WRP2A_PEND</Name>
  2698. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2699. <BitOffset>0x10</BitOffset>
  2700. <BitWidth>0x7</BitWidth>
  2701. <Access>RW</Access>
  2702. <Equation multiplier="0x2000" offset="0x08100000"/>
  2703. </Bit>
  2704. <Bit>
  2705. <Name>UNLOCK_2A</Name>
  2706. <Description>Bank 2 WPR first area A unlock</Description>
  2707. <BitOffset>0x1F</BitOffset>
  2708. <BitWidth>0x1</BitWidth>
  2709. <Access>RW</Access>
  2710. <Values>
  2711. <Val value="0x0">WRP2A start and end pages locked</Val>
  2712. <Val value="0x1">WRP2A start and end pages unlocked</Val>
  2713. </Values>
  2714. </Bit>
  2715. </AssignedBits>
  2716. </Field>
  2717. <Field>
  2718. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  2719. <AssignedBits>
  2720. <Bit config="6,8">
  2721. <Name>WRP2B_PSTRT</Name>
  2722. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2723. <BitOffset>0x0</BitOffset>
  2724. <BitWidth>0x7</BitWidth>
  2725. <Access>RW</Access>
  2726. <Equation multiplier="0x4000" offset="0x08000000"/>
  2727. </Bit>
  2728. <Bit config="7,9">
  2729. <Name>WRP2B_PSTRT</Name>
  2730. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2731. <BitOffset>0x0</BitOffset>
  2732. <BitWidth>0x7</BitWidth>
  2733. <Access>RW</Access>
  2734. <Equation multiplier="0x2000" offset="0x08100000"/>
  2735. </Bit>
  2736. <Bit config="6,8">
  2737. <Name>WRP2B_PEND</Name>
  2738. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2739. <BitOffset>0x10</BitOffset>
  2740. <BitWidth>0x7</BitWidth>
  2741. <Access>RW</Access>
  2742. <Equation multiplier="0x4000" offset="0x08000000"/>
  2743. </Bit>
  2744. <Bit config="7,9">
  2745. <Name>WRP2B_PEND</Name>
  2746. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2747. <BitOffset>0x10</BitOffset>
  2748. <BitWidth>0x7</BitWidth>
  2749. <Access>RW</Access>
  2750. <Equation multiplier="0x2000" offset="0x08100000"/>
  2751. </Bit>
  2752. <Bit>
  2753. <Name>UNLOCK_2B</Name>
  2754. <Description>Bank 2 WPR second area B unlock</Description>
  2755. <BitOffset>0x1F</BitOffset>
  2756. <BitWidth>0x1</BitWidth>
  2757. <Access>RW</Access>
  2758. <Values>
  2759. <Val value="0x0">WRP2B start and end pages locked</Val>
  2760. <Val value="0x1">WRP2B start and end pages unlocked</Val>
  2761. </Values>
  2762. </Bit>
  2763. </AssignedBits>
  2764. </Field>
  2765. </Category>
  2766. </Bank>
  2767. </Peripheral>
  2768. </Peripherals>
  2769. </Device>
  2770. </Root>