STM32_Prog_DB_0x411.xml 14 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x411</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M3</CPU>
  8. <Name>STM32F2xx</Name>
  9. <Series>STM32F2</Series>
  10. <Description>ARM 32-bit Cortex-M3 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD"/>
  14. <!-- Bootloader Interface -->
  15. <Interface name="Bootloader"/>
  16. </Configurations>
  17. <!-- Peripherals -->
  18. <Peripherals>
  19. <!-- Embedded SRAM -->
  20. <Peripheral>
  21. <Name>Embedded SRAM</Name>
  22. <Type>Storage</Type>
  23. <Description/>
  24. <ErasedValue>0x00</ErasedValue>
  25. <Access>RWE</Access>
  26. <!-- 128 KB -->
  27. <Configuration>
  28. <Parameters address="0x20000000" name="SRAM" size="0x20000"/>
  29. <Description/>
  30. <Organization>Single</Organization>
  31. <Bank name="Bank 1">
  32. <Field>
  33. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x20000"/>
  34. </Field>
  35. </Bank>
  36. </Configuration>
  37. </Peripheral>
  38. <!-- Embedded Flash -->
  39. <Peripheral>
  40. <Name>Embedded Flash</Name>
  41. <Type>Storage</Type>
  42. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  43. <ErasedValue>0xFF</ErasedValue>
  44. <Access>RWE</Access>
  45. <FlashSize address="0x1FFF7A22" default="0x100000"/>
  46. <!-- 1024KB Single Bank -->
  47. <Configuration>
  48. <Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
  49. <Description/>
  50. <Organization>Single</Organization>
  51. <Allignement>0x4</Allignement>
  52. <Bank name="Bank 1">
  53. <Field>
  54. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  55. </Field>
  56. <Field>
  57. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  58. </Field>
  59. <Field>
  60. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  61. </Field>
  62. </Bank>
  63. </Configuration>
  64. </Peripheral>
  65. <!-- OTP -->
  66. <Peripheral>
  67. <Name>OTP</Name>
  68. <Type>Storage</Type>
  69. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  70. <ErasedValue>0xFF</ErasedValue>
  71. <Access>RW</Access>
  72. <!-- 512 Bytes single bank -->
  73. <Configuration>
  74. <Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x200"/>
  75. <Description/>
  76. <Organization>Single</Organization>
  77. <Allignement>0x4</Allignement>
  78. <Bank name="OTP">
  79. <Field>
  80. <Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x200"/>
  81. </Field>
  82. </Bank>
  83. </Configuration>
  84. </Peripheral>
  85. <!-- Option Bytes -->
  86. <Peripheral>
  87. <Name>Option Bytes</Name>
  88. <Type>Configuration</Type>
  89. <Description/>
  90. <Access>RW</Access>
  91. <Bank interface="JTAG_SWD">
  92. <Parameters address="0x40023c14" name="Bank 1" size="0xC"/>
  93. <Category>
  94. <Name>Read Out Protection</Name>
  95. <Field>
  96. <Parameters address="0x40023c14" name="RDP" size="0x1"/>
  97. <AssignedBits>
  98. <Bit>
  99. <Name>RDP</Name>
  100. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  101. <BitOffset>0x8</BitOffset>
  102. <BitWidth>0x8</BitWidth>
  103. <Access>RW</Access>
  104. <Values>
  105. <Val value="0xAA">Level 0, no protection</Val>
  106. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  107. <Val value="0xCC">Level 2, chip protection</Val>
  108. </Values>
  109. </Bit>
  110. </AssignedBits>
  111. </Field>
  112. </Category>
  113. <Category>
  114. <Name>BOR Level</Name>
  115. <Field>
  116. <Parameters address="0x40023c14" name="USER" size="0x1"/>
  117. <AssignedBits>
  118. <Bit>
  119. <Name>BOR_LEV</Name>
  120. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  121. <BitOffset>0x2</BitOffset>
  122. <BitWidth>0x2</BitWidth>
  123. <Access>RW</Access>
  124. <Values>
  125. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  126. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  127. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  128. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  129. </Values>
  130. </Bit>
  131. </AssignedBits>
  132. </Field>
  133. </Category>
  134. <Category>
  135. <Name>User Configuration</Name>
  136. <Field>
  137. <Parameters address="0x40023c14" name="USER" size="0x1"/>
  138. <AssignedBits>
  139. <Bit>
  140. <Name>WDG_SW</Name>
  141. <Description/>
  142. <BitOffset>0x5</BitOffset>
  143. <BitWidth>0x1</BitWidth>
  144. <Access>RW</Access>
  145. <Values>
  146. <Val value="0x0">Hardware watchdog</Val>
  147. <Val value="0x1">Software watchdog</Val>
  148. </Values>
  149. </Bit>
  150. <Bit>
  151. <Name>nRST_STOP</Name>
  152. <Description/>
  153. <BitOffset>0x6</BitOffset>
  154. <BitWidth>0x1</BitWidth>
  155. <Access>RW</Access>
  156. <Values>
  157. <Val value="0x0">Reset generated when entering Stop mode</Val>
  158. <Val value="0x1">No reset generated</Val>
  159. </Values>
  160. </Bit>
  161. <Bit>
  162. <Name>nRST_STDBY</Name>
  163. <Description/>
  164. <BitOffset>0x7</BitOffset>
  165. <BitWidth>0x1</BitWidth>
  166. <Access>RW</Access>
  167. <Values>
  168. <Val value="0x0">Reset generated when entering Standby mode</Val>
  169. <Val value="0x1">No reset generated</Val>
  170. </Values>
  171. </Bit>
  172. </AssignedBits>
  173. </Field>
  174. </Category>
  175. <Category>
  176. <Name>Write Protection</Name>
  177. <Field>
  178. <Parameters address="0x40023c14" name="WRP1" size="0x2"/>
  179. <AssignedBits>
  180. <Bit>
  181. <Name>WRP0</Name>
  182. <Description/>
  183. <BitOffset>0x10</BitOffset>
  184. <BitWidth>0xC</BitWidth>
  185. <Access>RW</Access>
  186. <Values ByBit="true">
  187. <Val value="0x0">Write protection active</Val>
  188. <Val value="0x1">Write protection not active</Val>
  189. </Values>
  190. </Bit>
  191. </AssignedBits>
  192. </Field>
  193. </Category>
  194. </Bank>
  195. <!--<Bank interface="JTAG_SWD">
  196. <Parameters name="Bank 1" size="0xC" address="0x1FFFC000"/>
  197. <Category>
  198. <Name>Read Out Protection</Name>
  199. <Field>
  200. <Parameters name="RDP" size="0x1" address="0x1FFFC000"/>
  201. <AssignedBits>
  202. <Bit>
  203. <Name>RDP</Name>
  204. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  205. <BitOffset>0x8</BitOffset>
  206. <BitWidth>0x8</BitWidth>
  207. <Access>W</Access>
  208. <Values>
  209. <Val value="0xAA">Level 0, no protection</Val>
  210. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  211. <Val value="0xCC">Level 2, chip protection</Val>
  212. </Values>
  213. </Bit>
  214. </AssignedBits>
  215. </Field>
  216. </Category>
  217. <Category>
  218. <Name>BOR Level</Name>
  219. <Field>
  220. <Parameters name="USER" size="0x1" address="0x1FFFC000"/>
  221. <AssignedBits>
  222. <Bit>
  223. <Name>BOR_LEV</Name>
  224. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  225. <BitOffset>0x2</BitOffset>
  226. <BitWidth>0x2</BitWidth>
  227. <Access>W</Access>
  228. <Values>
  229. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  230. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  231. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  232. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  233. </Values>
  234. </Bit>
  235. </AssignedBits>
  236. </Field>
  237. </Category>
  238. <Category>
  239. <Name>User Configuration</Name>
  240. <Field>
  241. <Parameters name="USER" size="0x1" address="0x1FFFC000"/>
  242. <AssignedBits>
  243. <Bit>
  244. <Name>WDG_SW</Name>
  245. <Description/>
  246. <BitOffset>0x5</BitOffset>
  247. <BitWidth>0x1</BitWidth>
  248. <Access>W</Access>
  249. <Values>
  250. <Val value="0x0">Hardware watchdog</Val>
  251. <Val value="0x1">Software watchdog</Val>
  252. </Values>
  253. </Bit>
  254. <Bit>
  255. <Name>nRST_STOP</Name>
  256. <Description/>
  257. <BitOffset>0x6</BitOffset>
  258. <BitWidth>0x1</BitWidth>
  259. <Access>W</Access>
  260. <Values>
  261. <Val value="0x0">Reset generated when entering Stop mode</Val>
  262. <Val value="0x1">No reset generated</Val>
  263. </Values>
  264. </Bit>
  265. <Bit>
  266. <Name>nRST_STDBY</Name>
  267. <Description/>
  268. <BitOffset>0x7</BitOffset>
  269. <BitWidth>0x1</BitWidth>
  270. <Access>W</Access>
  271. <Values>
  272. <Val value="0x0">Reset generated when entering Standby mode</Val>
  273. <Val value="0x1">No reset generated</Val>
  274. </Values>
  275. </Bit>
  276. </AssignedBits>
  277. </Field>
  278. </Category>
  279. <Category>
  280. <Name>Write Protection</Name>
  281. <Field>
  282. <Parameters name="WRP1" size="0x2" address="0x1FFFC008"/>
  283. <AssignedBits>
  284. <Bit>
  285. <Name>WRP0</Name>
  286. <Description/>
  287. <BitOffset>0x0</BitOffset>
  288. <BitWidth>0xC</BitWidth>
  289. <Access>W</Access>
  290. <Values ByBit="true">
  291. <Val value="0x0">Write protection active</Val>
  292. <Val value="0x1">Write protection not active</Val>
  293. </Values>
  294. </Bit>
  295. </AssignedBits>
  296. </Field>
  297. </Category>
  298. </Bank>-->
  299. <Bank interface="Bootloader">
  300. <Parameters address="0x1FFFC000" name="Bank 1" size="0xC"/>
  301. <Category>
  302. <Name>Read Out Protection</Name>
  303. <Field>
  304. <Parameters address="0x1FFFC000" name="RDP" size="0x1"/>
  305. <AssignedBits>
  306. <Bit>
  307. <Name>RDP</Name>
  308. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  309. <BitOffset>0x8</BitOffset>
  310. <BitWidth>0x8</BitWidth>
  311. <Access>RW</Access>
  312. <Values>
  313. <Val value="0xAA">Level 0, no protection</Val>
  314. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  315. <Val value="0xCC">Level 2, chip protection</Val>
  316. </Values>
  317. </Bit>
  318. </AssignedBits>
  319. </Field>
  320. </Category>
  321. <Category>
  322. <Name>BOR Level</Name>
  323. <Field>
  324. <Parameters address="0x1FFFC000" name="USER" size="0x1"/>
  325. <AssignedBits>
  326. <Bit>
  327. <Name>BOR_LEV</Name>
  328. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  329. <BitOffset>0x2</BitOffset>
  330. <BitWidth>0x2</BitWidth>
  331. <Access>RW</Access>
  332. <Values>
  333. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  334. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  335. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  336. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  337. </Values>
  338. </Bit>
  339. </AssignedBits>
  340. </Field>
  341. </Category>
  342. <Category>
  343. <Name>User Configuration</Name>
  344. <Field>
  345. <Parameters address="0x1FFFC000" name="USER" size="0x1"/>
  346. <AssignedBits>
  347. <Bit>
  348. <Name>WDG_SW</Name>
  349. <Description/>
  350. <BitOffset>0x5</BitOffset>
  351. <BitWidth>0x1</BitWidth>
  352. <Access>RW</Access>
  353. <Values>
  354. <Val value="0x0">Hardware watchdog</Val>
  355. <Val value="0x1">Software watchdog</Val>
  356. </Values>
  357. </Bit>
  358. <Bit>
  359. <Name>nRST_STOP</Name>
  360. <Description/>
  361. <BitOffset>0x6</BitOffset>
  362. <BitWidth>0x1</BitWidth>
  363. <Access>RW</Access>
  364. <Values>
  365. <Val value="0x0">Reset generated when entering Stop mode</Val>
  366. <Val value="0x1">No reset generated</Val>
  367. </Values>
  368. </Bit>
  369. <Bit>
  370. <Name>nRST_STDBY</Name>
  371. <Description/>
  372. <BitOffset>0x7</BitOffset>
  373. <BitWidth>0x1</BitWidth>
  374. <Access>RW</Access>
  375. <Values>
  376. <Val value="0x0">Reset generated when entering Standby mode</Val>
  377. <Val value="0x1">No reset generated</Val>
  378. </Values>
  379. </Bit>
  380. </AssignedBits>
  381. </Field>
  382. </Category>
  383. <Category>
  384. <Name>Write Protection</Name>
  385. <Field>
  386. <Parameters address="0x1FFFC008" name="WRP1" size="0x2"/>
  387. <AssignedBits>
  388. <Bit>
  389. <Name>WRP0</Name>
  390. <Description/>
  391. <BitOffset>0x0</BitOffset>
  392. <BitWidth>0xC</BitWidth>
  393. <Access>RW</Access>
  394. <Values ByBit="true">
  395. <Val value="0x0">Write protection active</Val>
  396. <Val value="0x1">Write protection not active</Val>
  397. </Values>
  398. </Bit>
  399. </AssignedBits>
  400. </Field>
  401. </Category>
  402. </Bank>
  403. </Peripheral>
  404. </Peripherals>
  405. </Device>
  406. </Root>