sdk-debuger-stlink/tools/Data_Base/STM32_Prog_DB_0x415.xml

<?xml version="1.0" encoding="UTF-8"?>
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
<Device>
		<DeviceID>0x415</DeviceID>
		<Vendor>STMicroelectronics</Vendor>
		<Type>MCU</Type>
		<CPU>Cortex-M4</CPU>
		<Name>STM32L4x1/STM32L475xx/STM32L476xx/STM32L486xx</Name>
		<Series>STM32L4</Series>
		<Description>ARM 32-bit Cortex-M4 based device</Description>
		<Configurations>
			<!-- JTAG_SWD Interface -->
			<Interface name="JTAG_SWD">
				<!-- 1MB Dual Bank-->
				<Configuration number="0x0">
					<FlashSize>
						<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="0x0400"/>
					</FlashSize>
				</Configuration>
				<!-- 512KB Dual Bank-->
				<Configuration number="0x1"> <!-- DBANK=0x1-->
					<DualBank>
						<ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/>
					</DualBank>
					<FlashSize>
						<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="0x0200"/>
					</FlashSize>
				</Configuration>
				<!-- 512KB Single Bank-->
				<Configuration number="0x2"> <!-- DBANK=0x0-->
					<DualBank>
						<ReadRegister address="0x40022020" mask="0x200000" value="0x0"/>
					</DualBank>
					<FlashSize>
						<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="0x0200"/>
					</FlashSize>
				</Configuration>
				<!-- 256KB Dual Bank-->
				<Configuration number="0x3"> <!-- DBANK=0x1-->
					<DualBank>
						<ReadRegister address="0x40022020" mask="0x200000" value="0x200000"/>
					</DualBank>
					<FlashSize>
						<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="0x0100"/>
					</FlashSize>
				</Configuration>
				<!-- 256KB Single Bank-->
				<Configuration number="0x4"> <!-- DBANK=0x0-->
					<DualBank>
						<ReadRegister address="0x40022020" mask="0x200000" value="0x0"/>
					</DualBank>
					<FlashSize>
						<ReadRegister address="0x1FFF75E0" mask="0x0000FFFF" value="0x0100"/>
					</FlashSize>
				</Configuration>								
			</Interface>
			<!-- Bootloader Interface -->
			<Interface name="Bootloader">
			<!-- 1MB Dual Bank-->
				<!-- 512KB Dual Bank-->
				<Configuration number="0x5"> <!-- DBANK=0x1-->
					<DualBank>
						<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x200000"/>
					</DualBank>
				</Configuration>
				<!-- 512KB Single Bank-->
				<Configuration number="0x6"> <!-- DBANK=0x0-->
					<DualBank>
						<ReadRegister address="0x1FFF7800" mask="0x200000" value="0x0"/>
					</DualBank>
				</Configuration>
			</Interface>
		</Configurations>
		<!-- Peripherals -->
		<Peripherals>
			<!-- Embedded SRAM -->
			<Peripheral>
				<Name>Embedded SRAM</Name>
				<Type>Storage</Type>
				<Description/>
				<ErasedValue>0x00</ErasedValue>
				<Access>RWE</Access>
				<!-- 96 KB -->
				<Configuration>
					<Parameters address="0x20000000" name="SRAM" size="0x18000"/>
					<Description/>
					<Organization>Single</Organization>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x18000"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Embedded Flash -->
			<Peripheral>
				<Name>Embedded Flash</Name>
				<Type>Storage</Type>
				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RWE</Access>
				<FlashSize address="0x1FFF75E0" default="0x100000"/>
				<DBGMCU_CR address="0xE0042004" mask="0x007"/>
				<DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
				<!-- 1MB dual Bank -->
				<Configuration config="0,5,6">
					<Parameters address="0x08000000" name=" 1 Mbyte Embedded Flash" size="0x100000"/>
					<Description/>
					<Organization>Dual</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x800"/>
						</Field>
					</Bank>
					<Bank name="Bank 2">
						<Field>
							<Parameters address="0x08080000" name="sector256" occurence="0x100" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
				<!-- 512KB dual Bank -->
				<Configuration config="1,5">
					<Parameters address="0x08000000" name=" 512 KBbyte Embedded Flash" size="0x80000"/>
					<Description/>
					<Organization>Dual</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x800"/>
						</Field>
					</Bank>
					<Bank name="Bank 2">
						<Field>
							<Parameters address="0x08040000 " name="sector128" occurence="0x80" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
				<!-- 512KB Single Bank -->
				<Configuration config="2,6">
					<Parameters address="0x08000000" name=" 512 KBbyte Embedded Flash" size="0x80000"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x1000"/>
						</Field>
					</Bank>
				</Configuration>
				<!-- 256KB dual Bank -->
				<Configuration config="3,5">
					<Parameters address="0x08000000" name=" 256 KBbyte Embedded Flash" size="0x40000"/>
					<Description/>
					<Organization>Dual</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
						</Field>
					</Bank>
					<Bank name="Bank 2">
						<Field>
							<Parameters address="0x08020000 " name="sector65" occurence="0x40" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
				<!-- 256KB Single Bank -->
				<Configuration config="4,6">
					<Parameters address="0x08000000" name=" 256 KBbyte Embedded Flash" size="0x40000"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x8</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x800"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- OTP -->
			<Peripheral>
				<Name>OTP</Name>
				<Type>Storage</Type>
				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 1 KBytes single bank -->
				<Configuration>
					<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
					<Description/>
					<Organization>Single</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="OTP">
						<Field>
							<Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Mirror Option Bytes -->
			<Peripheral>
				<Name>MirrorOptionBytes</Name>
				<Type>Storage</Type>
				<Description>Mirror Option Bytes contains the extra area.</Description>
				<ErasedValue>0xFF</ErasedValue>
				<Access>RW</Access>
				<!-- 64 Bytes Dual bank -->
				<Configuration>
					<Parameters address="0x1FFF7800" name=" 64 Bytes Data MirrorOptionBytes" size="0x40"/>
					<Description/>
					<Organization>Dual</Organization>
					<Allignement>0x4</Allignement>
					<Bank name="Bank 1">
						<Field>
							<Parameters address="0x1FFF7800" name="Bank1" occurence="0x1" size="0x28"/>
						</Field>
					</Bank>
					<Bank name="Bank 2">
						<Field>
							<Parameters address="0x1FFFF800" name="Bank2" occurence="0x1" size="0x28"/>
						</Field>
					</Bank>
				</Configuration>
			</Peripheral>
			<!-- Option Bytes -->
			<Peripheral>
				<Name>Option Bytes</Name>
				<Type>Configuration</Type>
				<Description/>
				<Access>RW</Access>
				<Bank interface="JTAG_SWD">
					<Parameters address="0x40022020" name="Bank 1" size="0x14"/>
					<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x3</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Stop mode</Val>
										<Val value="0x1">No reset generated when entering Stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Standby mode</Val>
										<Val value="0x1">No reset generated when entering Standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_SHDW</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_SW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independant watchdog</Val>
										<Val value="0x1">Software independant watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
										<Val value="0x1">IWDG counter active in stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
										<Val value="0x1">IWDG counter active in standby mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>WWDG_SW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>BFB2</Name>
									<Description/>
									<BitOffset>0x14</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Dual-bank boot disable</Val>
										<Val value="0x1">Dual-bank boot enable</Val>
									</Values>
								</Bit>
								<Bit config="1,2,3,4">
									<Name>DualBank</Name>
									<Description/>
									<BitOffset>0x15</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1</Val>
										<Val value="0x1">256 KB/512 KB Dual-bank Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2_PE</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 parity check enable</Val>
										<Val value="0x1">SRAM2 parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2_RST</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>PCROP Protection (Bank 1)</Name>
						<Field>
							<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1_STRT</Name>
									<Description>Flash Bank 1 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1_END</Name>
									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection (Bank 1)</Name>
						<Field>
							<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the Bank 1 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of the Bank 1 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="JTAG_SWD">
					<Parameters address="0x40022044" name="Bank 2" size="0x10"/>
					<Category>
						<Name>PCROP Protection (Bank 2)</Name>
						<Field>
							<Parameters address="0x40022044" name="FLASH_PCROP2SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP2_STRT</Name>
									<Description>Flash Bank 2 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022048" name="FLASH_PCROP2ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP2_END</Name>
									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection (Bank 2)</Name>
						<Field>
							<Parameters address="0x4002204C" name="FLASH_WRP2AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP2A_STRT</Name>
									<Description>The address of first page of the Bank 2 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
								<Bit>
									<Name>WRP2A_END</Name>
									<Description>The address of last page of the Bank 2 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x40022050" name="FLASH_WRP2BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP2B_STRT</Name>
									<Description>The address of first page of the Bank 2 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
								<Bit>
									<Name>WRP2B_END</Name>
									<Description>The address of last page of the Bank 2 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="Bootloader">
					<Parameters address="0x1FFF7800" name="Bank 1" size="0x28"/>
					<Category>
						<Name>Read Out Protection</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>RDP</Name>
									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0xAA">Level 0, no protection</Val>
										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
										<Val value="0xCC">Level 2, chip protection</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>BOR Level</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>BOR_LEV</Name>
									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
									<BitOffset>0x8</BitOffset>
									<BitWidth>0x3</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>User Configuration</Name>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>IWDG_STOP</Name>
									<Description/>
									<BitOffset>0x11</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
										<Val value="0x1">IWDG counter active in stop mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_STDBY</Name>
									<Description/>
									<BitOffset>0x12</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
										<Val value="0x1">IWDG counter active in standby mode</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WWDG_SW</Name>
									<Description/>
									<BitOffset>0x13</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware window watchdog</Val>
										<Val value="0x1">Software window watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>IWDG_SW</Name>
									<Description/>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Hardware independant watchdog</Val>
										<Val value="0x1">Software independant watchdog</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STOP</Name>
									<Description/>
									<BitOffset>0xC</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Stop mode</Val>
										<Val value="0x1">No reset generated</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_STDBY</Name>
									<Description/>
									<BitOffset>0xD</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering Standby mode</Val>
										<Val value="0x1">No reset generated</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nRST_SHDW</Name>
									<Description/>
									<BitOffset>0xE</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>BFB2</Name>
									<Description/>
									<BitOffset>0x14</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Dual-bank boot disable</Val>
										<Val value="0x1">Dual-bank boot enable</Val>
									</Values>
								</Bit>
								<Bit config="5">
									<Name>DualBank</Name>
									<Description/>
									<BitOffset>0x15</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">256 KB/512 KB Single-bank Flash: Contiguous addresses in Bank 1</Val>
										<Val value="0x1">256 KB/512 KB Dual-bank Flash</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>nBOOT1</Name>
									<Description/>
									<BitOffset>0x17</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2_PE</Name>
									<Description/>
									<BitOffset>0x18</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 parity check enable</Val>
										<Val value="0x1">SRAM2 parity check disable</Val>
									</Values>
								</Bit>
								<Bit>
									<Name>SRAM2_RST</Name>
									<Description/>
									<BitOffset>0x19</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>PCROP Protection (Bank 1)</Name>
						<Field>
							<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1_STRT</Name>
									<Description>Flash Bank 1 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP1_END</Name>
									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>PCROP_RDP</Name>
									<Description/>
									<BitOffset>0x1F</BitOffset>
									<BitWidth>0x1</BitWidth>
									<Access>RW</Access>
									<Values>
										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
									</Values>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection (Bank 1)</Name>
						<Field>
							<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1A_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1A_END</Name>
									<Description>The address of the last page of the Bank 1 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP1B_STRT</Name>
									<Description>The address of the first page of the Bank 1 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
								<Bit>
									<Name>WRP1B_END</Name>
									<Description>The address of the last page of the Bank 1 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08000000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
				<Bank interface="Bootloader">
					<Parameters address="0x1FFFF800" name="Bank 2" size="0x28"/>
					<Category>
						<Name>PCROP Protection (Bank 2)</Name>
						<Field>
							<Parameters address="0x1FFFF808" name="FLASH_PCROP2SR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP2_STRT</Name>
									<Description>Flash Bank 2 PCROP start address</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFFF810" name="FLASH_PCROP2ER" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>PCROP2_END</Name>
									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x10</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x8" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
					<Category>
						<Name>Write Protection (Bank 2)</Name>
						<Field>
							<Parameters address="0x1FFFF818" name="FLASH_WRP2AR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP2A_STRT</Name>
									<Description>The address of first page of the Bank 2 WRP first area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
								<Bit>
									<Name>WRP2A_END</Name>
									<Description>The address of last page of the Bank 2 WRP first area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
						<Field>
							<Parameters address="0x1FFFF820" name="FLASH_WRP2BR" size="0x4"/>
							<AssignedBits>
								<Bit>
									<Name>WRP2B_STRT</Name>
									<Description>The address of first page of the Bank 2 WRP second area</Description>
									<BitOffset>0x0</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x20" offset="0x08080000"/>
								</Bit>
								<Bit>
									<Name>WRP2B_END</Name>
									<Description>The address of last page of the Bank 2 WRP second area</Description>
									<BitOffset>0x10</BitOffset>
									<BitWidth>0x8</BitWidth>
									<Access>RW</Access>
									<Equation multiplier="0x800" offset="0x08080000"/>
								</Bit>
							</AssignedBits>
						</Field>
					</Category>
				</Bank>
			</Peripheral>
		</Peripherals>
	</Device>
</Root>