STM32_Prog_DB_0x417.xml 21 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x417</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M0+</CPU>
  8. <Name>STM32L05x/L06x/L010</Name>
  9. <Series>STM32L0</Series>
  10. <Description>ARM 32-bit Cortex-M0+ based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  15. <WPRMOD reference="0x1">
  16. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
  17. </WPRMOD>
  18. </Configuration>
  19. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  20. <WPRMOD reference="0x0">
  21. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
  22. </WPRMOD>
  23. </Configuration>
  24. </Interface>
  25. <!-- Bootloader Interface -->
  26. <Interface name="Bootloader">
  27. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  28. <WPRMOD reference="0x1">
  29. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
  30. </WPRMOD>
  31. </Configuration>
  32. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  33. <WPRMOD reference="0x0">
  34. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
  35. </WPRMOD>
  36. </Configuration>
  37. </Interface>
  38. </Configurations>
  39. <!-- Peripherals -->
  40. <Peripherals>
  41. <!-- Embedded SRAM -->
  42. <Peripheral>
  43. <Name>Embedded SRAM</Name>
  44. <Type>Storage</Type>
  45. <Description/>
  46. <ErasedValue>0x00</ErasedValue>
  47. <Access>RWE</Access>
  48. <!-- 16 KB -->
  49. <Configuration>
  50. <Parameters address="0x20000000" name="SRAM" size="0x2000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Bank name="Bank 1">
  54. <Field>
  55. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x2000"/>
  56. </Field>
  57. </Bank>
  58. </Configuration>
  59. </Peripheral>
  60. <!-- Embedded Flash -->
  61. <Peripheral>
  62. <Name>Embedded Flash</Name>
  63. <Type>Storage</Type>
  64. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  65. <ErasedValue>0x00</ErasedValue>
  66. <Access>RWE</Access>
  67. <FlashSize address="0x1FF8007C" default="0x10000"/>
  68. <!-- 128KB single Bank -->
  69. <Configuration>
  70. <Parameters address="0x08000000" name="64 Kbytes Embedded Flash" size="0x10000"/>
  71. <Description/>
  72. <Organization>Single</Organization>
  73. <Allignement>0x4</Allignement>
  74. <Bank name="Bank 1">
  75. <Field>
  76. <Parameters address="0x08000000" name="sector0" occurence="0x200" size="0x80"/>
  77. </Field>
  78. </Bank>
  79. <Bank name="EEPROM1">
  80. <Field>
  81. <Parameters address="0x08080000" name="sector65281" occurence="0x1" size="0x800"/>
  82. </Field>
  83. </Bank>
  84. </Configuration>
  85. </Peripheral>
  86. <!-- Data EEPROM -->
  87. <Peripheral>
  88. <Name>Data EEPROM</Name>
  89. <Type>Storage</Type>
  90. <Description>The Data EEPROM memory block. It contains user data.</Description>
  91. <ErasedValue>0x00</ErasedValue>
  92. <Access>RWE</Access>
  93. <!-- 1KB single Bank -->
  94. <Configuration>
  95. <Parameters address="0x08080000" name=" 2 Kbytes Data EEPROM" size="0x800"/>
  96. <Description/>
  97. <Organization>Single</Organization>
  98. <Allignement>0x4</Allignement>
  99. <Bank name="Bank 1">
  100. <Field>
  101. <Parameters address="0x08080000" name="EEPROM1" occurence="0x1" size="0x800"/>
  102. </Field>
  103. </Bank>
  104. </Configuration>
  105. </Peripheral>
  106. <!-- Mirror Option Bytes -->
  107. <Peripheral>
  108. <Name>MirrorOptionBytes</Name>
  109. <Type>Storage</Type>
  110. <Description>Mirror Option Bytes contains the extra area.</Description>
  111. <ErasedValue>0xFF</ErasedValue>
  112. <Access>RW</Access>
  113. <!-- 20 Bytes single bank -->
  114. <Configuration>
  115. <Parameters address="0x1FF80000" name=" 20 Bytes Data MirrorOptionBytes" size="0x14"/>
  116. <Description/>
  117. <Organization>Single</Organization>
  118. <Allignement>0x4</Allignement>
  119. <Bank name="MirrorOptionBytes">
  120. <Field>
  121. <Parameters address="0x1FF80000" name="MirrorOptionBytes" occurence="0x1" size="0x14"/>
  122. </Field>
  123. </Bank>
  124. </Configuration>
  125. </Peripheral>
  126. <!-- Option Bytes -->
  127. <Peripheral>
  128. <Name>Option Bytes</Name>
  129. <Type>Configuration</Type>
  130. <Description/>
  131. <Access>RW</Access>
  132. <Bank interface="JTAG_SWD">
  133. <Parameters address="0x4002201C" name="Bank 1" size="0x68"/>
  134. <Category>
  135. <Name>Read Out Protection</Name>
  136. <Field>
  137. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  138. <AssignedBits>
  139. <Bit>
  140. <Name>RDP</Name>
  141. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  142. <BitOffset>0x0</BitOffset>
  143. <BitWidth>0x8</BitWidth>
  144. <Access>R</Access>
  145. <Values>
  146. <Val value="0xAA">Level 0, no protection</Val>
  147. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  148. <Val value="0xCC">Level 2, chip protection</Val>
  149. </Values>
  150. </Bit>
  151. </AssignedBits>
  152. </Field>
  153. </Category>
  154. <Category>
  155. <Name>PCROP Protection</Name>
  156. <Field>
  157. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  158. <AssignedBits>
  159. <Bit reference="SPRMode">
  160. <Name>WPRMOD</Name>
  161. <Description>Sector protection mode selection option byte.</Description>
  162. <BitOffset>0x8</BitOffset>
  163. <BitWidth>0x1</BitWidth>
  164. <Access>R</Access>
  165. <Values>
  166. <Val value="0x0">WRPx bit defines sector write protection</Val>
  167. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  168. </Values>
  169. </Bit>
  170. </AssignedBits>
  171. </Field>
  172. </Category>
  173. <Category>
  174. <Name>BOR Level</Name>
  175. <Field>
  176. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  177. <AssignedBits>
  178. <Bit>
  179. <Name>BOR_LEV</Name>
  180. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  181. <BitOffset>0x10</BitOffset>
  182. <BitWidth>0x4</BitWidth>
  183. <Access>R</Access>
  184. <Values>
  185. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  186. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  187. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  188. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  189. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  190. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  191. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  192. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  193. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  194. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  195. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  196. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  197. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  198. </Values>
  199. </Bit>
  200. </AssignedBits>
  201. </Field>
  202. </Category>
  203. <Category>
  204. <Name>User Configuration</Name>
  205. <Field>
  206. <Parameters address="0x4002201C" nname="FLASH_OBR" size="0x4"/>
  207. <AssignedBits>
  208. <Bit>
  209. <Name>IWDG_SW</Name>
  210. <Description/>
  211. <BitOffset>0x14</BitOffset>
  212. <BitWidth>0x1</BitWidth>
  213. <Access>R</Access>
  214. <Values>
  215. <Val value="0x0">Hardware independant watchdog</Val>
  216. <Val value="0x1">Software independant watchdog</Val>
  217. </Values>
  218. </Bit>
  219. <Bit>
  220. <Name>nRST_STOP</Name>
  221. <Description/>
  222. <BitOffset>0x15</BitOffset>
  223. <BitWidth>0x1</BitWidth>
  224. <Access>R</Access>
  225. <Values>
  226. <Val value="0x0">Reset generated when entering Stop mode</Val>
  227. <Val value="0x1">No reset generated</Val>
  228. </Values>
  229. </Bit>
  230. <Bit>
  231. <Name>nRST_STDBY</Name>
  232. <Description/>
  233. <BitOffset>0x16</BitOffset>
  234. <BitWidth>0x1</BitWidth>
  235. <Access>R</Access>
  236. <Values>
  237. <Val value="0x0">Reset generated when entering Standby mode</Val>
  238. <Val value="0x1">No reset generated</Val>
  239. </Values>
  240. </Bit>
  241. <Bit>
  242. <Name>nBOOT1</Name>
  243. <Description/>
  244. <BitOffset>0x1F</BitOffset>
  245. <BitWidth>0x1</BitWidth>
  246. <Access>R</Access>
  247. <Values>
  248. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  249. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  250. </Values>
  251. </Bit>
  252. </AssignedBits>
  253. </Field>
  254. </Category>
  255. <Category>
  256. <Name>Write Protection</Name>
  257. <Field>
  258. <Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
  259. <AssignedBits>
  260. <Bit config="0">
  261. <Name>WRPOT1</Name>
  262. <Description/>
  263. <BitOffset>0x0</BitOffset>
  264. <BitWidth>0x10</BitWidth>
  265. <Access>R</Access>
  266. <Values ByBit="true">
  267. <Val value="0x0">Write protection not active</Val>
  268. <Val value="0x1">Write protection active</Val>
  269. </Values>
  270. </Bit>
  271. <Bit config="1">
  272. <Name>WRPOT1</Name>
  273. <Description/>
  274. <BitOffset>0x0</BitOffset>
  275. <BitWidth>0x10</BitWidth>
  276. <Access>R</Access>
  277. <Values ByBit="true">
  278. <Val value="0x0">read/Write protection active</Val>
  279. <Val value="0x1">read/Write protection not active</Val>
  280. </Values>
  281. </Bit>
  282. </AssignedBits>
  283. </Field>
  284. </Category>
  285. </Bank>
  286. <Bank interface="JTAG_SWD">
  287. <Parameters address="0x1FF80000" name="Bank 1" size="0x14"/>
  288. <Category>
  289. <Name>Read Out Protection</Name>
  290. <Field>
  291. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  292. <AssignedBits>
  293. <Bit>
  294. <Name>RDP</Name>
  295. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  296. <BitOffset>0x0</BitOffset>
  297. <BitWidth>0x8</BitWidth>
  298. <Access>W</Access>
  299. <Values>
  300. <Val value="0xAA">Level 0, no protection</Val>
  301. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  302. <Val value="0xCC">Level 2, chip protection</Val>
  303. </Values>
  304. </Bit>
  305. </AssignedBits>
  306. </Field>
  307. </Category>
  308. <Category>
  309. <Name>PCROP Protection</Name>
  310. <Field>
  311. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  312. <AssignedBits>
  313. <Bit reference="SPRMode">
  314. <Name>WPRMOD</Name>
  315. <Description>Sector protection mode selection option byte.</Description>
  316. <BitOffset>0x8</BitOffset>
  317. <BitWidth>0x1</BitWidth>
  318. <Access>W</Access>
  319. <Values>
  320. <Val value="0x0">WRPx bit defines sector write protection</Val>
  321. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  322. </Values>
  323. </Bit>
  324. </AssignedBits>
  325. </Field>
  326. </Category>
  327. <Category>
  328. <Name>BOR Level</Name>
  329. <Field>
  330. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  331. <AssignedBits>
  332. <Bit>
  333. <Name>BOR_LEV</Name>
  334. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  335. <BitOffset>0x0</BitOffset>
  336. <BitWidth>0x4</BitWidth>
  337. <Access>W</Access>
  338. <Values>
  339. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  340. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  341. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  342. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  343. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  344. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  345. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  346. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  347. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  348. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  349. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  350. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  351. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  352. </Values>
  353. </Bit>
  354. </AssignedBits>
  355. </Field>
  356. </Category>
  357. <Category>
  358. <Name>User Configuration</Name>
  359. <Field>
  360. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  361. <AssignedBits>
  362. <Bit>
  363. <Name>IWDG_SW</Name>
  364. <Description/>
  365. <BitOffset>0x4</BitOffset>
  366. <BitWidth>0x1</BitWidth>
  367. <Access>W</Access>
  368. <Values>
  369. <Val value="0x0">Hardware independant watchdog</Val>
  370. <Val value="0x1">Software independant watchdog</Val>
  371. </Values>
  372. </Bit>
  373. <Bit>
  374. <Name>nRST_STOP</Name>
  375. <Description/>
  376. <BitOffset>0x5</BitOffset>
  377. <BitWidth>0x1</BitWidth>
  378. <Access>W</Access>
  379. <Values>
  380. <Val value="0x0">Reset generated when entering Stop mode</Val>
  381. <Val value="0x1">No reset generated</Val>
  382. </Values>
  383. </Bit>
  384. <Bit>
  385. <Name>nRST_STDBY</Name>
  386. <Description/>
  387. <BitOffset>0x6</BitOffset>
  388. <BitWidth>0x1</BitWidth>
  389. <Access>W</Access>
  390. <Values>
  391. <Val value="0x0">Reset generated when entering Standby mode</Val>
  392. <Val value="0x1">No reset generated</Val>
  393. </Values>
  394. </Bit>
  395. <Bit>
  396. <Name>nBOOT1</Name>
  397. <Description/>
  398. <BitOffset>0x0F</BitOffset>
  399. <BitWidth>0x1</BitWidth>
  400. <Access>W</Access>
  401. <Values>
  402. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  403. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  404. </Values>
  405. </Bit>
  406. </AssignedBits>
  407. </Field>
  408. </Category>
  409. <Category>
  410. <Name>Write Protection</Name>
  411. <Field>
  412. <Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
  413. <AssignedBits>
  414. <Bit>
  415. <Name>WRPOT1</Name>
  416. <Description/>
  417. <BitOffset>0x0</BitOffset>
  418. <BitWidth>0x10</BitWidth>
  419. <Access>W</Access>
  420. <Values ByBit="true">
  421. <Val value="0x0">Write protection not active</Val>
  422. <Val value="0x1">Write protection active</Val>
  423. </Values>
  424. </Bit>
  425. </AssignedBits>
  426. </Field>
  427. </Category>
  428. </Bank>
  429. <Bank interface="Bootloader">
  430. <Parameters address="0x1FF80000" name="Bank 2" size="0x14"/>
  431. <Category>
  432. <Name>Read Out Protection</Name>
  433. <Field>
  434. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  435. <AssignedBits>
  436. <Bit>
  437. <Name>RDP</Name>
  438. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  439. <BitOffset>0x0</BitOffset>
  440. <BitWidth>0x8</BitWidth>
  441. <Access>RW</Access>
  442. <Values>
  443. <Val value="0xAA">Level 0, no protection</Val>
  444. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  445. <Val value="0xCC">Level 2, chip protection</Val>
  446. </Values>
  447. </Bit>
  448. </AssignedBits>
  449. </Field>
  450. </Category>
  451. <Category>
  452. <Name>PCROP Protection</Name>
  453. <Field>
  454. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  455. <AssignedBits>
  456. <Bit reference="SPRMode">
  457. <Name>WPRMOD</Name>
  458. <Description>Sector protection mode selection option byte.</Description>
  459. <BitOffset>0x8</BitOffset>
  460. <BitWidth>0x1</BitWidth>
  461. <Access>RW</Access>
  462. <Values>
  463. <Val value="0x0">WRPx bit defines sector write protection</Val>
  464. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  465. </Values>
  466. </Bit>
  467. </AssignedBits>
  468. </Field>
  469. </Category>
  470. <Category>
  471. <Name>BOR Level</Name>
  472. <Field>
  473. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  474. <AssignedBits>
  475. <Bit>
  476. <Name>BOR_LEV</Name>
  477. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  478. <BitOffset>0x0</BitOffset>
  479. <BitWidth>0x4</BitWidth>
  480. <Access>RW</Access>
  481. <Values>
  482. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  483. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  484. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  485. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  486. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  487. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  488. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  489. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  490. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  491. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  492. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  493. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  494. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  495. </Values>
  496. </Bit>
  497. </AssignedBits>
  498. </Field>
  499. </Category>
  500. <Category>
  501. <Name>User Configuration</Name>
  502. <Field>
  503. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  504. <AssignedBits>
  505. <Bit>
  506. <Name>IWDG_SW</Name>
  507. <Description/>
  508. <BitOffset>0x4</BitOffset>
  509. <BitWidth>0x1</BitWidth>
  510. <Access>RW</Access>
  511. <Values>
  512. <Val value="0x0">Hardware independant watchdog</Val>
  513. <Val value="0x1">Software independant watchdog</Val>
  514. </Values>
  515. </Bit>
  516. <Bit>
  517. <Name>nRST_STOP</Name>
  518. <Description/>
  519. <BitOffset>0x5</BitOffset>
  520. <BitWidth>0x1</BitWidth>
  521. <Access>RW</Access>
  522. <Values>
  523. <Val value="0x0">Reset generated when entering Stop mode</Val>
  524. <Val value="0x1">No reset generated</Val>
  525. </Values>
  526. </Bit>
  527. <Bit>
  528. <Name>nRST_STDBY</Name>
  529. <Description/>
  530. <BitOffset>0x6</BitOffset>
  531. <BitWidth>0x1</BitWidth>
  532. <Access>RW</Access>
  533. <Values>
  534. <Val value="0x0">Reset generated when entering Standby mode</Val>
  535. <Val value="0x1">No reset generated</Val>
  536. </Values>
  537. </Bit>
  538. <Bit>
  539. <Name>nBOOT1</Name>
  540. <Description/>
  541. <BitOffset>0x0F</BitOffset>
  542. <BitWidth>0x1</BitWidth>
  543. <Access>RW</Access>
  544. <Values>
  545. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  546. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  547. </Values>
  548. </Bit>
  549. </AssignedBits>
  550. </Field>
  551. </Category>
  552. <Category>
  553. <Name>Write Protection</Name>
  554. <Field>
  555. <Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
  556. <AssignedBits>
  557. <Bit>
  558. <Name>WRPOT1</Name>
  559. <Description/>
  560. <BitOffset>0x0</BitOffset>
  561. <BitWidth>0x10</BitWidth>
  562. <Access>RW</Access>
  563. <Values ByBit="true">
  564. <Val value="0x0">Write protection not active</Val>
  565. <Val value="0x1">Write protection active</Val>
  566. </Values>
  567. </Bit>
  568. </AssignedBits>
  569. </Field>
  570. </Category>
  571. </Bank>
  572. </Peripheral>
  573. </Peripherals>
  574. </Device>
  575. </Root>