STM32_Prog_DB_0x419.xml 22 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x419</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M4</CPU>
  8. <Name>STM32F42xxx/F43xxx</Name>
  9. <Series>STM32F4</Series>
  10. <Description>ARM 32-bit Cortex-M4 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0">
  15. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  16. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
  17. </Configuration>
  18. <Configuration number="0x1">
  19. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
  20. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0"/> </flashSize>
  21. </Configuration>
  22. <Configuration number="0x2">
  23. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  24. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  25. <DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
  26. </Configuration>
  27. <Configuration number="0x3">
  28. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
  29. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  30. <DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
  31. </Configuration>
  32. <Configuration number="0x4">
  33. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  34. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  35. <DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
  36. </Configuration>
  37. <Configuration number="0x5">
  38. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x80000000"/> </SPRMode>
  39. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  40. <DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
  41. </Configuration>
  42. <Configuration number="0x6"> <!-- dummy config ></!-->
  43. <dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
  44. </Configuration>
  45. </Interface>
  46. <!-- Bootloader Interface -->
  47. <Interface name="Bootloader">
  48. <Configuration number="0x0">
  49. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  50. </Configuration>
  51. <Configuration number="0x1">
  52. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  53. </Configuration>
  54. <Configuration number="0x2">
  55. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  56. <DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
  57. </Configuration>
  58. <Configuration number="0x3">
  59. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  60. <DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
  61. </Configuration>
  62. <Configuration number="0x4">
  63. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  64. <DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
  65. </Configuration>
  66. <Configuration number="0x5">
  67. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  68. <DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
  69. </Configuration>
  70. <Configuration number="0x6"> <!-- dummy config ></!-->
  71. <dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
  72. </Configuration>
  73. </Interface>
  74. </Configurations>
  75. <!-- Peripherals -->
  76. <Peripherals>
  77. <!-- Embedded SRAM -->
  78. <Peripheral>
  79. <Name>Embedded SRAM</Name>
  80. <Type>Storage</Type>
  81. <Description/>
  82. <ErasedValue>0x00</ErasedValue>
  83. <Access>RWE</Access>
  84. <!-- 112 KB 0x1c000-->
  85. <Configuration>
  86. <Parameters address="0x20000000" name="SRAM" size="0x30000"/>
  87. <Description/>
  88. <Organization>Single</Organization>
  89. <Bank name="Bank 1">
  90. <Field>
  91. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x30000"/>
  92. </Field>
  93. </Bank>
  94. </Configuration>
  95. </Peripheral>
  96. <!-- Embedded Flash -->
  97. <Peripheral>
  98. <Name>Embedded Flash</Name>
  99. <Type>Storage</Type>
  100. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  101. <ErasedValue>0xFF</ErasedValue>
  102. <Access>RWE</Access>
  103. <FlashSize address="0x1FFF7A22" default="0x200000"/>
  104. <BootloaderVersion address="0x1FFF76DE"/>
  105. <!-- 1024KB Single Bank -->
  106. <Configuration config="0,1,6">
  107. <Parameters address="0x08000000" name=" 2048 Kbytes Embedded Flash" size="0x200000"/>
  108. <Description/>
  109. <Organization>Dual</Organization>
  110. <Allignement>0x4</Allignement>
  111. <Bank name="Bank 1">
  112. <Field>
  113. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  114. </Field>
  115. <Field>
  116. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  117. </Field>
  118. <Field>
  119. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  120. </Field>
  121. </Bank>
  122. <Bank name="Bank 2">
  123. <Field>
  124. <Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
  125. </Field>
  126. <Field>
  127. <Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
  128. </Field>
  129. <Field>
  130. <Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
  131. </Field>
  132. </Bank>
  133. </Configuration>
  134. <Configuration config="4,5">
  135. <Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
  136. <Description/>
  137. <Organization>Dual</Organization>
  138. <Allignement>0x4</Allignement>
  139. <Bank name="Bank 1">
  140. <Field>
  141. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  142. </Field>
  143. <Field>
  144. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  145. </Field>
  146. <Field>
  147. <Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
  148. </Field>
  149. </Bank>
  150. <Bank name="Bank 2">
  151. <Field>
  152. <Parameters address="0x08080000" name="sector8" occurence="0x4" size="0x20000"/>
  153. </Field>
  154. </Bank>
  155. </Configuration>
  156. <Configuration config="2,3">
  157. <Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
  158. <Description/>
  159. <Organization>Single</Organization>
  160. <Allignement>0x4</Allignement>
  161. <Bank name="Bank 1">
  162. <Field>
  163. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  164. </Field>
  165. <Field>
  166. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  167. </Field>
  168. <Field>
  169. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  170. </Field>
  171. </Bank>
  172. </Configuration>
  173. </Peripheral>
  174. <!-- OTP -->
  175. <Peripheral>
  176. <Name>OTP</Name>
  177. <Type>Storage</Type>
  178. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  179. <ErasedValue>0xFF</ErasedValue>
  180. <Access>RW</Access>
  181. <!-- 512 Bytes single bank -->
  182. <Configuration>
  183. <Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x210"/>
  184. <Description/>
  185. <Organization>Single</Organization>
  186. <Allignement>0x4</Allignement>
  187. <Bank name="OTP">
  188. <Field>
  189. <Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x210"/>
  190. </Field>
  191. </Bank>
  192. </Configuration>
  193. </Peripheral>
  194. <!-- Mirror Option Bytes -->
  195. <Peripheral>
  196. <Name>MirrorOptionBytes</Name>
  197. <Type>Storage</Type>
  198. <Description>Mirror Option Bytes contains the extra area.</Description>
  199. <ErasedValue>0xFF</ErasedValue>
  200. <Access>RW</Access>
  201. <!-- 24 Bytes Dual bank -->
  202. <Configuration>
  203. <Parameters address="0x1FFF7800" name=" 24 Bytes Data MirrorOptionBytes" size="0x18"/>
  204. <Description/>
  205. <Organization>Dual</Organization>
  206. <Allignement>0x4</Allignement>
  207. <Bank name="Bank 1">
  208. <Field>
  209. <Parameters address="0x1FFFC000" name="Bank1" occurence="0x1" size="0x10"/>
  210. </Field>
  211. </Bank>
  212. <Bank name="Bank 2">
  213. <Field>
  214. <Parameters address="0x1FFEC008" name="Bank2" occurence="0x1" size="0x8"/>
  215. </Field>
  216. </Bank>
  217. </Configuration>
  218. </Peripheral>
  219. <!-- Option Bytes -->
  220. <Peripheral>
  221. <Name>Option Bytes</Name>
  222. <Type>Configuration</Type>
  223. <Description/>
  224. <Access>RW</Access>
  225. <Bank interface="JTAG_SWD">
  226. <Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
  227. <Category>
  228. <Name>Read Out Protection</Name>
  229. <Field>
  230. <Parameters address="0x40023C14" name="RDP" size="0x4"/>
  231. <AssignedBits>
  232. <Bit>
  233. <Name>RDP</Name>
  234. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  235. <BitOffset>0x8</BitOffset>
  236. <BitWidth>0x8</BitWidth>
  237. <Access>RW</Access>
  238. <Values>
  239. <Val value="0xAA">Level 0, no protection</Val>
  240. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  241. <Val value="0xCC">Level 2, chip protection</Val>
  242. </Values>
  243. </Bit>
  244. </AssignedBits>
  245. </Field>
  246. </Category>
  247. <Category>
  248. <Name>PCROP Protection</Name>
  249. <Field>
  250. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  251. <AssignedBits>
  252. <Bit reference="SPRMode">
  253. <Name>SPRMOD</Name>
  254. <Description>Selection of protection mode for nWPRi bits.</Description>
  255. <BitOffset>0x1F</BitOffset>
  256. <BitWidth>0x1</BitWidth>
  257. <Access>RW</Access>
  258. <Values>
  259. <Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
  260. <Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
  261. </Values>
  262. </Bit>
  263. </AssignedBits>
  264. </Field>
  265. </Category>
  266. <Category>
  267. <Name>BOR Level</Name>
  268. <Field>
  269. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  270. <AssignedBits>
  271. <Bit>
  272. <Name>BOR_LEV</Name>
  273. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  274. <BitOffset>0x2</BitOffset>
  275. <BitWidth>0x2</BitWidth>
  276. <Access>RW</Access>
  277. <Values>
  278. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  279. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  280. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  281. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  282. </Values>
  283. </Bit>
  284. </AssignedBits>
  285. </Field>
  286. </Category>
  287. <Category>
  288. <Name>User Configuration</Name>
  289. <Field>
  290. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  291. <AssignedBits>
  292. <Bit>
  293. <Name>BFB2</Name>
  294. <Description/>
  295. <BitOffset>0x4</BitOffset>
  296. <BitWidth>0x1</BitWidth>
  297. <Access>RW</Access>
  298. <Values>
  299. <Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
  300. <Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
  301. </Values>
  302. </Bit>
  303. <Bit>
  304. <Name>WDG_SW</Name>
  305. <Description/>
  306. <BitOffset>0x5</BitOffset>
  307. <BitWidth>0x1</BitWidth>
  308. <Access>RW</Access>
  309. <Values>
  310. <Val value="0x0">Hardware watchdog</Val>
  311. <Val value="0x1">Software watchdog</Val>
  312. </Values>
  313. </Bit>
  314. <Bit>
  315. <Name>nRST_STOP</Name>
  316. <Description/>
  317. <BitOffset>0x6</BitOffset>
  318. <BitWidth>0x1</BitWidth>
  319. <Access>RW</Access>
  320. <Values>
  321. <Val value="0x0">Reset generated when entering Stop mode</Val>
  322. <Val value="0x1">No reset generated</Val>
  323. </Values>
  324. </Bit>
  325. <Bit>
  326. <Name>nRST_STDBY</Name>
  327. <Description/>
  328. <BitOffset>0x7</BitOffset>
  329. <BitWidth>0x1</BitWidth>
  330. <Access>RW</Access>
  331. <Values>
  332. <Val value="0x0">Reset generated when entering Standby mode</Val>
  333. <Val value="0x1">No reset generated</Val>
  334. </Values>
  335. </Bit>
  336. <Bit config="2,3,4,5">
  337. <Name>DB1M</Name>
  338. <Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
  339. <BitOffset>0x1E</BitOffset>
  340. <BitWidth>0x1</BitWidth>
  341. <Access>RW</Access>
  342. <Values>
  343. <Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
  344. <Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
  345. </Values>
  346. </Bit>
  347. </AssignedBits>
  348. </Field>
  349. </Category>
  350. <Category>
  351. <Name>Write Protection</Name>
  352. <Field>
  353. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  354. <AssignedBits>
  355. <Bit config="0,2,4">
  356. <Name>nWRP0</Name>
  357. <Description/>
  358. <BitOffset>0x10</BitOffset>
  359. <BitWidth>0xC</BitWidth>
  360. <Access>RW</Access>
  361. <Values ByBit="true">
  362. <Val value="0x0">Write protection active</Val>
  363. <Val value="0x1">Write protection not active</Val>
  364. </Values>
  365. </Bit>
  366. <Bit config="1,3,5,6">
  367. <Name>nWRP0</Name>
  368. <Description/>
  369. <BitOffset>0x10</BitOffset>
  370. <BitWidth>0xC</BitWidth>
  371. <Access>RW</Access>
  372. <Values ByBit="true">
  373. <Val value="0x0">PCROP protection not active on sector i</Val>
  374. <Val value="0x1">PCROP protection active on sector i</Val>
  375. </Values>
  376. </Bit>
  377. </AssignedBits>
  378. </Field>
  379. <Field>
  380. <Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
  381. <AssignedBits>
  382. <Bit config="0,2,4">
  383. <Name>nWRP12</Name>
  384. <Description/>
  385. <BitOffset>0x10</BitOffset>
  386. <BitWidth>0xC</BitWidth>
  387. <Access>RW</Access>
  388. <Values ByBit="true">
  389. <Val value="0x0">Write protection active</Val>
  390. <Val value="0x1">Write protection not active</Val>
  391. </Values>
  392. </Bit>
  393. <Bit config="1,3,5,6">
  394. <Name>nWRP12</Name>
  395. <Description/>
  396. <BitOffset>0x10</BitOffset>
  397. <BitWidth>0xC</BitWidth>
  398. <Access>RW</Access>
  399. <Values ByBit="true">
  400. <Val value="0x0">PCROP protection not active on sector i</Val>
  401. <Val value="0x1">PCROP protection active on sector i</Val>
  402. </Values>
  403. </Bit>
  404. </AssignedBits>
  405. </Field>
  406. </Category>
  407. </Bank>
  408. <Bank interface="Bootloader">
  409. <Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
  410. <Category>
  411. <Name>Read Out Protection</Name>
  412. <Field>
  413. <Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
  414. <AssignedBits>
  415. <Bit>
  416. <Name>RDP</Name>
  417. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  418. <BitOffset>0x8</BitOffset>
  419. <BitWidth>0x8</BitWidth>
  420. <Access>RW</Access>
  421. <Values>
  422. <Val value="0xAA">Level 0, no protection</Val>
  423. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  424. <Val value="0xCC">Level 2, chip protection</Val>
  425. </Values>
  426. </Bit>
  427. </AssignedBits>
  428. </Field>
  429. </Category>
  430. <Category>
  431. <Name>PCROP Protection</Name>
  432. <Field>
  433. <Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
  434. <AssignedBits>
  435. <Bit reference="SPRMode">
  436. <Name>SPRMOD</Name>
  437. <Description>Selection of protection mode for nWPRi bits.</Description>
  438. <BitOffset>0xF</BitOffset>
  439. <BitWidth>0x1</BitWidth>
  440. <Access>RW</Access>
  441. <Values>
  442. <Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
  443. <Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
  444. </Values>
  445. </Bit>
  446. </AssignedBits>
  447. </Field>
  448. </Category>
  449. <Category>
  450. <Name>BOR Level</Name>
  451. <Field>
  452. <Parameters address="0x1FFFC000" name="USER" size="0x4"/>
  453. <AssignedBits>
  454. <Bit>
  455. <Name>BOR_LEV</Name>
  456. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  457. <BitOffset>0x2</BitOffset>
  458. <BitWidth>0x2</BitWidth>
  459. <Access>RW</Access>
  460. <Values>
  461. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  462. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  463. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  464. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  465. </Values>
  466. </Bit>
  467. </AssignedBits>
  468. </Field>
  469. </Category>
  470. <Category>
  471. <Name>User Configuration</Name>
  472. <Field>
  473. <Parameters address="0x1FFFC000" name="USER" size="0x4"/>
  474. <AssignedBits>
  475. <Bit>
  476. <Name>BFB2</Name>
  477. <Description/>
  478. <BitOffset>0x4</BitOffset>
  479. <BitWidth>0x1</BitWidth>
  480. <Access>RW</Access>
  481. <Values>
  482. <Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
  483. <Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
  484. </Values>
  485. </Bit>
  486. <Bit>
  487. <Name>WDG_SW</Name>
  488. <Description/>
  489. <BitOffset>0x5</BitOffset>
  490. <BitWidth>0x1</BitWidth>
  491. <Access>RW</Access>
  492. <Values>
  493. <Val value="0x0">Hardware watchdog</Val>
  494. <Val value="0x1">Software watchdog</Val>
  495. </Values>
  496. </Bit>
  497. <Bit>
  498. <Name>nRST_STOP</Name>
  499. <Description/>
  500. <BitOffset>0x6</BitOffset>
  501. <BitWidth>0x1</BitWidth>
  502. <Access>RW</Access>
  503. <Values>
  504. <Val value="0x0">Reset generated when entering Stop mode</Val>
  505. <Val value="0x1">No reset generated</Val>
  506. </Values>
  507. </Bit>
  508. <Bit>
  509. <Name>nRST_STDBY</Name>
  510. <Description/>
  511. <BitOffset>0x7</BitOffset>
  512. <BitWidth>0x1</BitWidth>
  513. <Access>RW</Access>
  514. <Values>
  515. <Val value="0x0">Reset generated when entering Standby mode</Val>
  516. <Val value="0x1">No reset generated</Val>
  517. </Values>
  518. </Bit>
  519. <Bit config="2,3,4,5">
  520. <Name>DB1M</Name>
  521. <Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
  522. <BitOffset>0x1E</BitOffset>
  523. <BitWidth>0x1</BitWidth>
  524. <Access>RW</Access>
  525. <Values>
  526. <Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
  527. <Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
  528. </Values>
  529. </Bit>
  530. </AssignedBits>
  531. </Field>
  532. </Category>
  533. <Category>
  534. <Name>Write Protection (Bank 1)</Name>
  535. <Field>
  536. <Parameters address="0x1FFFC008" name="WRP0" size="0x4"/>
  537. <AssignedBits>
  538. <Bit config="0,2,4">
  539. <Name>WRP0</Name>
  540. <Description/>
  541. <BitOffset>0x0</BitOffset>
  542. <BitWidth>0xC</BitWidth>
  543. <Access>RW</Access>
  544. <Values ByBit="true">
  545. <Val value="0x0">Write protection active</Val>
  546. <Val value="0x1">Write protection not active</Val>
  547. </Values>
  548. </Bit>
  549. <Bit config="1,3,5,6">
  550. <Name>WRP0</Name>
  551. <Description/>
  552. <BitOffset>0x0</BitOffset>
  553. <BitWidth>0xC</BitWidth>
  554. <Access>RW</Access>
  555. <Values ByBit="true">
  556. <Val value="0x0">PCROP protection not active on sector i</Val>
  557. <Val value="0x1">PCROP protection active on sector i</Val>
  558. </Values>
  559. </Bit>
  560. </AssignedBits>
  561. </Field>
  562. </Category>
  563. </Bank>
  564. <Bank interface="Bootloader">
  565. <Parameters address="0x1FFEC008" name="Bank 2" size="0x8"/>
  566. <Category>
  567. <Name>Write Protection (Bank 2)</Name>
  568. <Field>
  569. <Parameters address="0x1FFEC008" name="WRP1" size="0x4"/>
  570. <AssignedBits>
  571. <Bit config="0,2,4">
  572. <Name>WRP12</Name>
  573. <Description/>
  574. <BitOffset>0x0</BitOffset>
  575. <BitWidth>0xC</BitWidth>
  576. <Access>RW</Access>
  577. <Values ByBit="true">
  578. <Val value="0x0">Write protection active</Val>
  579. <Val value="0x1">Write protection not active</Val>
  580. </Values>
  581. </Bit>
  582. <Bit config="1,3,5,6">
  583. <Name>WRP12</Name>
  584. <Description/>
  585. <BitOffset>0x0</BitOffset>
  586. <BitWidth>0xC</BitWidth>
  587. <Access>RW</Access>
  588. <Values ByBit="true">
  589. <Val value="0x0">PCROP protection not active on sector i</Val>
  590. <Val value="0x1">PCROP protection active on sector i</Val>
  591. </Values>
  592. </Bit>
  593. </AssignedBits>
  594. </Field>
  595. </Category>
  596. </Bank>
  597. </Peripheral>
  598. </Peripherals>
  599. </Device>
  600. </Root>