STM32_Prog_DB_0x425.xml 21 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x425</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M0+</CPU>
  8. <Name>STM32L03x/L04x/L010</Name>
  9. <Series>STM32L0</Series>
  10. <Description>ARM 32-bit Cortex-M0+ based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  15. <WPRMOD reference="0x1">
  16. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
  17. </WPRMOD>
  18. </Configuration>
  19. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  20. <WPRMOD reference="0x0">
  21. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
  22. </WPRMOD>
  23. </Configuration>
  24. </Interface>
  25. <!-- Bootloader Interface -->
  26. <Interface name="Bootloader">
  27. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  28. <WPRMOD reference="0x1">
  29. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
  30. </WPRMOD>
  31. </Configuration>
  32. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  33. <WPRMOD reference="0x0">
  34. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
  35. </WPRMOD>
  36. </Configuration>
  37. </Interface>
  38. </Configurations>
  39. <!-- Peripherals -->
  40. <Peripherals>
  41. <!-- Embedded SRAM -->
  42. <Peripheral>
  43. <Name>Embedded SRAM</Name>
  44. <Type>Storage</Type>
  45. <Description/>
  46. <ErasedValue>0x00</ErasedValue>
  47. <Access>RWE</Access>
  48. <!-- 16 KB -->
  49. <Configuration>
  50. <Parameters address="0x20000000" name="SRAM" size="0x2000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Bank name="Bank 1">
  54. <Field>
  55. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x2000"/>
  56. </Field>
  57. </Bank>
  58. </Configuration>
  59. </Peripheral>
  60. <!-- Embedded Flash -->
  61. <Peripheral>
  62. <Name>Embedded Flash</Name>
  63. <Type>Storage</Type>
  64. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  65. <ErasedValue>0x00</ErasedValue>
  66. <Access>RWE</Access>
  67. <FlashSize address="0x1FF8007C" default="0x8000"/>
  68. <BootloaderVersion address="0x1FF00FFE"/>
  69. <!-- 128KB single Bank -->
  70. <Configuration>
  71. <Parameters address="0x08000000" name="32 Kbytes Embedded Flash" size="0x8000"/>
  72. <Description/>
  73. <Organization>Single</Organization>
  74. <Allignement>0x4</Allignement>
  75. <Bank name="Bank 1">
  76. <Field>
  77. <Parameters address="0x08000000" name="sector0" occurence="0x100" size="0x80"/>
  78. </Field>
  79. </Bank>
  80. <Bank name="EEPROM1">
  81. <Field>
  82. <Parameters address="0x08080000" name="sector65281" occurence="0x1" size="0x400"/>
  83. </Field>
  84. </Bank>
  85. </Configuration>
  86. </Peripheral>
  87. <!-- Data EEPROM -->
  88. <Peripheral>
  89. <Name>Data EEPROM</Name>
  90. <Type>Storage</Type>
  91. <Description>The Data EEPROM memory block. It contains user data.</Description>
  92. <ErasedValue>0x00</ErasedValue>
  93. <Access>RWE</Access>
  94. <!-- 1KB single Bank -->
  95. <Configuration>
  96. <Parameters address="0x08080000" name=" 1 Kbytes Data EEPROM" size="0x400"/>
  97. <Description/>
  98. <Organization>Single</Organization>
  99. <Allignement>0x4</Allignement>
  100. <Bank name="Bank 1">
  101. <Field>
  102. <Parameters address="0x08080000" name="EEPROM1" occurence="0x1" size="0x400"/>
  103. </Field>
  104. </Bank>
  105. </Configuration>
  106. </Peripheral>
  107. <!-- Option Bytes -->
  108. <Peripheral>
  109. <Name>Option Bytes</Name>
  110. <Type>Configuration</Type>
  111. <Description/>
  112. <Access>RW</Access>
  113. <Bank interface="JTAG_SWD">
  114. <Parameters address="0x4002201C" name="Bank 1" size="0x68"/>
  115. <Category>
  116. <Name>Read Out Protection</Name>
  117. <Field>
  118. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  119. <AssignedBits>
  120. <Bit>
  121. <Name>RDP</Name>
  122. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  123. <BitOffset>0x0</BitOffset>
  124. <BitWidth>0x8</BitWidth>
  125. <Access>R</Access>
  126. <Values>
  127. <Val value="0xAA">Level 0, no protection</Val>
  128. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  129. <Val value="0xCC">Level 2, chip protection</Val>
  130. </Values>
  131. </Bit>
  132. </AssignedBits>
  133. </Field>
  134. </Category>
  135. <Category>
  136. <Name>PCROP Protection</Name>
  137. <Field>
  138. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  139. <AssignedBits>
  140. <Bit reference="SPRMode">
  141. <Name>WPRMOD</Name>
  142. <Description>Sector protection mode selection option byte.</Description>
  143. <BitOffset>0x8</BitOffset>
  144. <BitWidth>0x1</BitWidth>
  145. <Access>R</Access>
  146. <Values>
  147. <Val value="0x0">WRPx bit defines sector write protection</Val>
  148. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  149. </Values>
  150. </Bit>
  151. </AssignedBits>
  152. </Field>
  153. </Category>
  154. <Category>
  155. <Name>BOR Level</Name>
  156. <Field>
  157. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  158. <AssignedBits>
  159. <Bit>
  160. <Name>BOR_LEV</Name>
  161. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  162. <BitOffset>0x10</BitOffset>
  163. <BitWidth>0x4</BitWidth>
  164. <Access>R</Access>
  165. <Values>
  166. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  167. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  168. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  169. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  170. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  171. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  172. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  173. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  174. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  175. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  176. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  177. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  178. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  179. </Values>
  180. </Bit>
  181. </AssignedBits>
  182. </Field>
  183. </Category>
  184. <Category>
  185. <Name>User Configuration</Name>
  186. <Field>
  187. <Parameters address="0x4002201C" nname="FLASH_OBR" size="0x4"/>
  188. <AssignedBits>
  189. <Bit>
  190. <Name>IWDG_SW</Name>
  191. <Description/>
  192. <BitOffset>0x14</BitOffset>
  193. <BitWidth>0x1</BitWidth>
  194. <Access>R</Access>
  195. <Values>
  196. <Val value="0x0">Hardware independant watchdog</Val>
  197. <Val value="0x1">Software independant watchdog</Val>
  198. </Values>
  199. </Bit>
  200. <Bit>
  201. <Name>nRST_STOP</Name>
  202. <Description/>
  203. <BitOffset>0x15</BitOffset>
  204. <BitWidth>0x1</BitWidth>
  205. <Access>R</Access>
  206. <Values>
  207. <Val value="0x0">Reset generated when entering Stop mode</Val>
  208. <Val value="0x1">No reset generated</Val>
  209. </Values>
  210. </Bit>
  211. <Bit>
  212. <Name>nRST_STDBY</Name>
  213. <Description/>
  214. <BitOffset>0x16</BitOffset>
  215. <BitWidth>0x1</BitWidth>
  216. <Access>R</Access>
  217. <Values>
  218. <Val value="0x0">Reset generated when entering Standby mode</Val>
  219. <Val value="0x1">No reset generated</Val>
  220. </Values>
  221. </Bit>
  222. <Bit>
  223. <Name>nBOOT1</Name>
  224. <Description/>
  225. <BitOffset>0x1F</BitOffset>
  226. <BitWidth>0x1</BitWidth>
  227. <Access>R</Access>
  228. <Values>
  229. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  230. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  231. </Values>
  232. </Bit>
  233. </AssignedBits>
  234. </Field>
  235. </Category>
  236. <Category>
  237. <Name>Write Protection</Name>
  238. <Field>
  239. <Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
  240. <AssignedBits>
  241. <Bit config="0">
  242. <Name>WRPOT0</Name>
  243. <Description/>
  244. <BitOffset>0x0</BitOffset>
  245. <BitWidth>0x8</BitWidth>
  246. <Access>R</Access>
  247. <Values ByBit="true">
  248. <Val value="0x0">Write protection not active</Val>
  249. <Val value="0x1">Write protection active</Val>
  250. </Values>
  251. </Bit>
  252. <Bit config="1">
  253. <Name>WRPOT0</Name>
  254. <Description/>
  255. <BitOffset>0x0</BitOffset>
  256. <BitWidth>0x8</BitWidth>
  257. <Access>R</Access>
  258. <Values ByBit="true">
  259. <Val value="0x0">read/Write protection active</Val>
  260. <Val value="0x1">read/Write protection not active</Val>
  261. </Values>
  262. </Bit>
  263. </AssignedBits>
  264. </Field>
  265. </Category>
  266. </Bank>
  267. <Bank interface="JTAG_SWD">
  268. <Parameters address="0x1FF80000" name="Bank 1" size="0x14"/>
  269. <Category>
  270. <Name>Read Out Protection</Name>
  271. <Field>
  272. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  273. <AssignedBits>
  274. <Bit>
  275. <Name>RDP</Name>
  276. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  277. <BitOffset>0x0</BitOffset>
  278. <BitWidth>0x8</BitWidth>
  279. <Access>W</Access>
  280. <Values>
  281. <Val value="0xAA">Level 0, no protection</Val>
  282. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  283. <Val value="0xCC">Level 2, chip protection</Val>
  284. </Values>
  285. </Bit>
  286. </AssignedBits>
  287. </Field>
  288. </Category>
  289. <Category>
  290. <Name>PCROP Protection</Name>
  291. <Field>
  292. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  293. <AssignedBits>
  294. <Bit reference="SPRMode">
  295. <Name>WPRMOD</Name>
  296. <Description>Sector protection mode selection option byte.</Description>
  297. <BitOffset>0x8</BitOffset>
  298. <BitWidth>0x1</BitWidth>
  299. <Access>W</Access>
  300. <Values>
  301. <Val value="0x0">WRPx bit defines sector write protection</Val>
  302. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  303. </Values>
  304. </Bit>
  305. </AssignedBits>
  306. </Field>
  307. </Category>
  308. <Category>
  309. <Name>BOR Level</Name>
  310. <Field>
  311. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  312. <AssignedBits>
  313. <Bit>
  314. <Name>BOR_LEV</Name>
  315. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  316. <BitOffset>0x0</BitOffset>
  317. <BitWidth>0x4</BitWidth>
  318. <Access>W</Access>
  319. <Values>
  320. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  321. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  322. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  323. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  324. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  325. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  326. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  327. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  328. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  329. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  330. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  331. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  332. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  333. </Values>
  334. </Bit>
  335. </AssignedBits>
  336. </Field>
  337. </Category>
  338. <Category>
  339. <Name>User Configuration</Name>
  340. <Field>
  341. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  342. <AssignedBits>
  343. <Bit>
  344. <Name>IWDG_SW</Name>
  345. <Description/>
  346. <BitOffset>0x4</BitOffset>
  347. <BitWidth>0x1</BitWidth>
  348. <Access>W</Access>
  349. <Values>
  350. <Val value="0x0">Hardware independant watchdog</Val>
  351. <Val value="0x1">Software independant watchdog</Val>
  352. </Values>
  353. </Bit>
  354. <Bit>
  355. <Name>nRST_STOP</Name>
  356. <Description/>
  357. <BitOffset>0x5</BitOffset>
  358. <BitWidth>0x1</BitWidth>
  359. <Access>W</Access>
  360. <Values>
  361. <Val value="0x0">Reset generated when entering Stop mode</Val>
  362. <Val value="0x1">No reset generated</Val>
  363. </Values>
  364. </Bit>
  365. <Bit>
  366. <Name>nRST_STDBY</Name>
  367. <Description/>
  368. <BitOffset>0x6</BitOffset>
  369. <BitWidth>0x1</BitWidth>
  370. <Access>W</Access>
  371. <Values>
  372. <Val value="0x0">Reset generated when entering Standby mode</Val>
  373. <Val value="0x1">No reset generated</Val>
  374. </Values>
  375. </Bit>
  376. <Bit>
  377. <Name>nBOOT1</Name>
  378. <Description/>
  379. <BitOffset>0x0F</BitOffset>
  380. <BitWidth>0x1</BitWidth>
  381. <Access>W</Access>
  382. <Values>
  383. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  384. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  385. </Values>
  386. </Bit>
  387. </AssignedBits>
  388. </Field>
  389. </Category>
  390. <Category>
  391. <Name>Write Protection</Name>
  392. <Field>
  393. <Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
  394. <AssignedBits>
  395. <Bit>
  396. <Name>WRPOT0</Name>
  397. <Description/>
  398. <BitOffset>0x0</BitOffset>
  399. <BitWidth>0x8</BitWidth>
  400. <Access>W</Access>
  401. <Values ByBit="true">
  402. <Val value="0x0">Write protection not active</Val>
  403. <Val value="0x1">Write protection active</Val>
  404. </Values>
  405. </Bit>
  406. </AssignedBits>
  407. </Field>
  408. </Category>
  409. </Bank>
  410. <Bank interface="Bootloader">
  411. <Parameters address="0x1FF80000" name="Bank 2" size="0x14"/>
  412. <Category>
  413. <Name>Read Out Protection</Name>
  414. <Field>
  415. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  416. <AssignedBits>
  417. <Bit>
  418. <Name>RDP</Name>
  419. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  420. <BitOffset>0x0</BitOffset>
  421. <BitWidth>0x8</BitWidth>
  422. <Access>RW</Access>
  423. <Values>
  424. <Val value="0xAA">Level 0, no protection</Val>
  425. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  426. <Val value="0xCC">Level 2, chip protection</Val>
  427. </Values>
  428. </Bit>
  429. </AssignedBits>
  430. </Field>
  431. </Category>
  432. <Category>
  433. <Name>PCROP Protection</Name>
  434. <Field>
  435. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  436. <AssignedBits>
  437. <Bit reference="SPRMode">
  438. <Name>WPRMOD</Name>
  439. <Description>Sector protection mode selection option byte.</Description>
  440. <BitOffset>0x8</BitOffset>
  441. <BitWidth>0x1</BitWidth>
  442. <Access>RW</Access>
  443. <Values>
  444. <Val value="0x0">WRPx bit defines sector write protection</Val>
  445. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  446. </Values>
  447. </Bit>
  448. </AssignedBits>
  449. </Field>
  450. </Category>
  451. <Category>
  452. <Name>BOR Level</Name>
  453. <Field>
  454. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  455. <AssignedBits>
  456. <Bit>
  457. <Name>BOR_LEV</Name>
  458. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  459. <BitOffset>0x0</BitOffset>
  460. <BitWidth>0x4</BitWidth>
  461. <Access>RW</Access>
  462. <Values>
  463. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  464. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  465. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  466. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  467. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  468. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  469. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  470. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  471. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  472. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  473. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  474. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  475. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  476. </Values>
  477. </Bit>
  478. </AssignedBits>
  479. </Field>
  480. </Category>
  481. <Category>
  482. <Name>User Configuration</Name>
  483. <Field>
  484. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  485. <AssignedBits>
  486. <Bit>
  487. <Name>IWDG_SW</Name>
  488. <Description/>
  489. <BitOffset>0x4</BitOffset>
  490. <BitWidth>0x1</BitWidth>
  491. <Access>RW</Access>
  492. <Values>
  493. <Val value="0x0">Hardware independant watchdog</Val>
  494. <Val value="0x1">Software independant watchdog</Val>
  495. </Values>
  496. </Bit>
  497. <Bit>
  498. <Name>nRST_STOP</Name>
  499. <Description/>
  500. <BitOffset>0x5</BitOffset>
  501. <BitWidth>0x1</BitWidth>
  502. <Access>RW</Access>
  503. <Values>
  504. <Val value="0x0">Reset generated when entering Stop mode</Val>
  505. <Val value="0x1">No reset generated</Val>
  506. </Values>
  507. </Bit>
  508. <Bit>
  509. <Name>nRST_STDBY</Name>
  510. <Description/>
  511. <BitOffset>0x6</BitOffset>
  512. <BitWidth>0x1</BitWidth>
  513. <Access>RW</Access>
  514. <Values>
  515. <Val value="0x0">Reset generated when entering Standby mode</Val>
  516. <Val value="0x1">No reset generated</Val>
  517. </Values>
  518. </Bit>
  519. <Bit>
  520. <Name>nBOOT1</Name>
  521. <Description/>
  522. <BitOffset>0x0F</BitOffset>
  523. <BitWidth>0x1</BitWidth>
  524. <Access>RW</Access>
  525. <Values>
  526. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  527. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  528. </Values>
  529. </Bit>
  530. </AssignedBits>
  531. </Field>
  532. </Category>
  533. <Category>
  534. <Name>Write Protection</Name>
  535. <Field>
  536. <Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
  537. <AssignedBits>
  538. <Bit config="0">
  539. <Name>WRPOT0</Name>
  540. <Description/>
  541. <BitOffset>0x0</BitOffset>
  542. <BitWidth>0x8</BitWidth>
  543. <Access>RW</Access>
  544. <Values ByBit="true">
  545. <Val value="0x0">Write protection not active</Val>
  546. <Val value="0x1">Write protection active</Val>
  547. </Values>
  548. </Bit>
  549. <Bit config="1">
  550. <Name>WRPOT0</Name>
  551. <Description/>
  552. <BitOffset>0x0</BitOffset>
  553. <BitWidth>0x8</BitWidth>
  554. <Access>RW</Access>
  555. <Values ByBit="true">
  556. <Val value="0x0">read/Write protection active</Val>
  557. <Val value="0x1">read/Write protection not active</Val>
  558. </Values>
  559. </Bit>
  560. </AssignedBits>
  561. </Field>
  562. </Category>
  563. </Bank>
  564. </Peripheral>
  565. </Peripherals>
  566. </Device>
  567. </Root>