STM32_Prog_DB_0x434.xml 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599
  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x434</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M4</CPU>
  8. <Name>STM32F469xx/F467xx</Name>
  9. <Series>STM32F4</Series>
  10. <Description>ARM 32-bit Cortex-M4 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0">
  15. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  16. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
  17. </Configuration>
  18. <Configuration number="0x1">
  19. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  20. <flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x800"/> </flashSize>
  21. </Configuration>
  22. <Configuration number="0x2">
  23. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  24. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  25. <DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
  26. </Configuration>
  27. <Configuration number="0x3">
  28. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  29. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  30. <DB1M reference="0x0"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x0"/> </DB1M>
  31. </Configuration>
  32. <Configuration number="0x4">
  33. <SPRMode reference="0x0"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  34. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  35. <DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
  36. </Configuration>
  37. <Configuration number="0x5">
  38. <SPRMode reference="0x1"> <ReadRegister address="0x40023C14" mask="0x80000000" value="0x0"/> </SPRMode>
  39. <flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22" mask="0xFFFF" value="0x400"/> </flashSize>
  40. <DB1M reference="0x1"> <ReadRegister address="0x40023C14" mask="0x40000000" value="0x40000000"/> </DB1M>
  41. </Configuration>
  42. <Configuration number="0x6">
  43. <dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
  44. </Configuration>
  45. </Interface>
  46. <!-- Bootloader Interface -->
  47. <Interface name="Bootloader">
  48. <Configuration number="0x0">
  49. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  50. </Configuration>
  51. <Configuration number="0x1">
  52. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  53. </Configuration>
  54. <Configuration number="0x2">
  55. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  56. <DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
  57. </Configuration>
  58. <Configuration number="0x3">
  59. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  60. <DB1M reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x0"/> </DB1M>
  61. </Configuration>
  62. <Configuration number="0x4">
  63. <SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x0"/> </SPRMode>
  64. <DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
  65. </Configuration>
  66. <Configuration number="0x5">
  67. <SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x8000" value="0x8000"/> </SPRMode>
  68. <DB1M reference="0x1"> <ReadRegister address="0x1FFFC008" mask="0x4000" value="0x4000"/> </DB1M>
  69. </Configuration>
  70. <Configuration number="0x6">
  71. <dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
  72. </Configuration>
  73. </Interface>
  74. </Configurations>
  75. <!-- Peripherals -->
  76. <Peripherals>
  77. <!-- Embedded SRAM -->
  78. <Peripheral>
  79. <Name>Embedded SRAM</Name>
  80. <Type>Storage</Type>
  81. <Description/>
  82. <ErasedValue>0x00</ErasedValue>
  83. <Access>RWE</Access>
  84. <!-- 320 KB 0x50000-->
  85. <Configuration>
  86. <Parameters address="0x20000000" name="SRAM" size="0x50000"/>
  87. <Description/>
  88. <Organization>Single</Organization>
  89. <Bank name="Bank 1">
  90. <Field>
  91. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x50000"/>
  92. </Field>
  93. </Bank>
  94. </Configuration>
  95. </Peripheral>
  96. <!-- Embedded Flash -->
  97. <Peripheral>
  98. <Name>Embedded Flash</Name>
  99. <Type>Storage</Type>
  100. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  101. <ErasedValue>0xFF</ErasedValue>
  102. <Access>RWE</Access>
  103. <FlashSize address="0x1FFF7A22" default="0x200000"/>
  104. <!-- 1024KB Single Bank -->
  105. <Configuration config="0,1,6">
  106. <Parameters address="0x08000000" name=" 2048 Kbytes Embedded Flash" size="0x200000"/>
  107. <Description/>
  108. <Organization>Dual</Organization>
  109. <Allignement>0x4</Allignement>
  110. <Bank name="Bank 1">
  111. <Field>
  112. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  113. </Field>
  114. <Field>
  115. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  116. </Field>
  117. <Field>
  118. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  119. </Field>
  120. </Bank>
  121. <Bank name="Bank 2">
  122. <Field>
  123. <Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
  124. </Field>
  125. <Field>
  126. <Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
  127. </Field>
  128. <Field>
  129. <Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
  130. </Field>
  131. </Bank>
  132. </Configuration>
  133. <Configuration config="4,5">
  134. <Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
  135. <Description/>
  136. <Organization>Dual</Organization>
  137. <Allignement>0x4</Allignement>
  138. <Bank name="Bank 1">
  139. <Field>
  140. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  141. </Field>
  142. <Field>
  143. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  144. </Field>
  145. <Field>
  146. <Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
  147. </Field>
  148. </Bank>
  149. <Bank name="Bank 2">
  150. <Field>
  151. <Parameters address="0x08080000" name="sector8" occurence="0x4" size="0x20000"/>
  152. </Field>
  153. </Bank>
  154. </Configuration>
  155. <Configuration config="2,3">
  156. <Parameters address="0x08000000" name=" 1024 Kbytes Embedded Flash" size="0x100000"/>
  157. <Description/>
  158. <Organization>Single</Organization>
  159. <Allignement>0x4</Allignement>
  160. <Bank name="Bank 1">
  161. <Field>
  162. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  163. </Field>
  164. <Field>
  165. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  166. </Field>
  167. <Field>
  168. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  169. </Field>
  170. </Bank>
  171. </Configuration>
  172. </Peripheral>
  173. <!-- OTP -->
  174. <Peripheral>
  175. <Name>OTP</Name>
  176. <Type>Storage</Type>
  177. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  178. <ErasedValue>0xFF</ErasedValue>
  179. <Access>RW</Access>
  180. <!-- 512 Bytes single bank -->
  181. <Configuration>
  182. <Parameters address="0x1FFF7800" name=" 512 Bytes Data OTP" size="0x210"/>
  183. <Description/>
  184. <Organization>Single</Organization>
  185. <Allignement>0x4</Allignement>
  186. <Bank name="OTP">
  187. <Field>
  188. <Parameters address="0x1FFF7800" name="OTP" occurence="0x1" size="0x210"/>
  189. </Field>
  190. </Bank>
  191. </Configuration>
  192. </Peripheral>
  193. <!-- Mirror Option Bytes -->
  194. <Peripheral>
  195. <Name>MirrorOptionBytes</Name>
  196. <Type>Storage</Type>
  197. <Description>Mirror Option Bytes contains the extra area.</Description>
  198. <ErasedValue>0xFF</ErasedValue>
  199. <Access>RW</Access>
  200. <!-- 20 Bytes Dual bank -->
  201. <Configuration>
  202. <Parameters address="0x1FFEC008" name=" 20 Bytes Data MirrorOptionBytes" size="0x14"/>
  203. <Description/>
  204. <Organization>Dual</Organization>
  205. <Allignement>0x4</Allignement>
  206. <Bank name="Bank 1">
  207. <Field>
  208. <Parameters address="0x1FFEC008" name="Bank1" occurence="0x1" size="0x4"/>
  209. </Field>
  210. </Bank>
  211. <Bank name="Bank 2">
  212. <Field>
  213. <Parameters address="0x1FFFC000" name="Bank2" occurence="0x1" size="0x10"/>
  214. </Field>
  215. </Bank>
  216. </Configuration>
  217. </Peripheral>
  218. <!-- Option Bytes -->
  219. <Peripheral>
  220. <Name>Option Bytes</Name>
  221. <Type>Configuration</Type>
  222. <Description/>
  223. <Access>RW</Access>
  224. <Bank interface="JTAG_SWD">
  225. <Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
  226. <Category>
  227. <Name>Read Out Protection</Name>
  228. <Field>
  229. <Parameters address="0x40023C14" name="RDP" size="0x4"/>
  230. <AssignedBits>
  231. <Bit>
  232. <Name>RDP</Name>
  233. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  234. <BitOffset>0x8</BitOffset>
  235. <BitWidth>0x8</BitWidth>
  236. <Access>RW</Access>
  237. <Values>
  238. <Val value="0xAA">Level 0, no protection</Val>
  239. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  240. <Val value="0xCC">Level 2, chip protection</Val>
  241. </Values>
  242. </Bit>
  243. </AssignedBits>
  244. </Field>
  245. </Category>
  246. <Category>
  247. <Name>PCROP Protection</Name>
  248. <Field>
  249. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  250. <AssignedBits>
  251. <Bit reference="SPRMode">
  252. <Name>SPRMOD</Name>
  253. <Description>Selection of protection mode for nWPRi bits.</Description>
  254. <BitOffset>0x1F</BitOffset>
  255. <BitWidth>0x1</BitWidth>
  256. <Access>RW</Access>
  257. <Values>
  258. <Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
  259. <Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
  260. </Values>
  261. </Bit>
  262. </AssignedBits>
  263. </Field>
  264. </Category>
  265. <Category>
  266. <Name>BOR Level</Name>
  267. <Field>
  268. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  269. <AssignedBits>
  270. <Bit>
  271. <Name>BOR_LEV</Name>
  272. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  273. <BitOffset>0x2</BitOffset>
  274. <BitWidth>0x2</BitWidth>
  275. <Access>RW</Access>
  276. <Values>
  277. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  278. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  279. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  280. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  281. </Values>
  282. </Bit>
  283. </AssignedBits>
  284. </Field>
  285. </Category>
  286. <Category>
  287. <Name>User Configuration</Name>
  288. <Field>
  289. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  290. <AssignedBits>
  291. <Bit>
  292. <Name>BFB2</Name>
  293. <Description/>
  294. <BitOffset>0x4</BitOffset>
  295. <BitWidth>0x1</BitWidth>
  296. <Access>RW</Access>
  297. <Values>
  298. <Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
  299. <Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
  300. </Values>
  301. </Bit>
  302. <Bit>
  303. <Name>WDG_SW</Name>
  304. <Description/>
  305. <BitOffset>0x5</BitOffset>
  306. <BitWidth>0x1</BitWidth>
  307. <Access>RW</Access>
  308. <Values>
  309. <Val value="0x0">Hardware watchdog</Val>
  310. <Val value="0x1">Software watchdog</Val>
  311. </Values>
  312. </Bit>
  313. <Bit>
  314. <Name>nRST_STOP</Name>
  315. <Description/>
  316. <BitOffset>0x6</BitOffset>
  317. <BitWidth>0x1</BitWidth>
  318. <Access>RW</Access>
  319. <Values>
  320. <Val value="0x0">Reset generated when entering Stop mode</Val>
  321. <Val value="0x1">No reset generated</Val>
  322. </Values>
  323. </Bit>
  324. <Bit>
  325. <Name>nRST_STDBY</Name>
  326. <Description/>
  327. <BitOffset>0x7</BitOffset>
  328. <BitWidth>0x1</BitWidth>
  329. <Access>RW</Access>
  330. <Values>
  331. <Val value="0x0">Reset generated when entering Standby mode</Val>
  332. <Val value="0x1">No reset generated</Val>
  333. </Values>
  334. </Bit>
  335. <Bit config="2,3,4,5">
  336. <Name>DB1M</Name>
  337. <Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
  338. <BitOffset>0x1E</BitOffset>
  339. <BitWidth>0x1</BitWidth>
  340. <Access>RW</Access>
  341. <Values>
  342. <Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
  343. <Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
  344. </Values>
  345. </Bit>
  346. </AssignedBits>
  347. </Field>
  348. </Category>
  349. <Category>
  350. <Name>Write Protection</Name>
  351. <Field>
  352. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  353. <AssignedBits>
  354. <Bit config="0,2,4">
  355. <Name>nWRP0</Name>
  356. <Description/>
  357. <BitOffset>0x10</BitOffset>
  358. <BitWidth>0xC</BitWidth>
  359. <Access>RW</Access>
  360. <Values ByBit="true">
  361. <Val value="0x0">Write protection active</Val>
  362. <Val value="0x1">Write protection not active</Val>
  363. </Values>
  364. </Bit>
  365. <Bit config="1,3,5,6">
  366. <Name>nWRP0</Name>
  367. <Description/>
  368. <BitOffset>0x10</BitOffset>
  369. <BitWidth>0xC</BitWidth>
  370. <Access>RW</Access>
  371. <Values ByBit="true">
  372. <Val value="0x0">PCROP protection not active on sector i</Val>
  373. <Val value="0x1">PCROP protection active on sector i</Val>
  374. </Values>
  375. </Bit>
  376. </AssignedBits>
  377. </Field>
  378. <Field>
  379. <Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
  380. <AssignedBits>
  381. <Bit config="0,2,4">
  382. <Name>nWRP12</Name>
  383. <Description/>
  384. <BitOffset>0x10</BitOffset>
  385. <BitWidth>0xC</BitWidth>
  386. <Access>RW</Access>
  387. <Values ByBit="true">
  388. <Val value="0x0">Write protection active</Val>
  389. <Val value="0x1">Write protection not active</Val>
  390. </Values>
  391. </Bit>
  392. <Bit config="1,3,5,6">
  393. <Name>nWRP12</Name>
  394. <Description/>
  395. <BitOffset>0x10</BitOffset>
  396. <BitWidth>0xC</BitWidth>
  397. <Access>RW</Access>
  398. <Values ByBit="true">
  399. <Val value="0x0">PCROP protection not active on sector i</Val>
  400. <Val value="0x1">PCROP protection active on sector i</Val>
  401. </Values>
  402. </Bit>
  403. </AssignedBits>
  404. </Field>
  405. </Category>
  406. </Bank>
  407. <Bank interface="Bootloader">
  408. <Parameters address="0x1FFFC000" name="Bank 1" size="0x10"/>
  409. <Category>
  410. <Name>Read Out Protection</Name>
  411. <Field>
  412. <Parameters address="0x1FFFC000" name="RDP" size="0x4"/>
  413. <AssignedBits>
  414. <Bit>
  415. <Name>RDP</Name>
  416. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  417. <BitOffset>0x8</BitOffset>
  418. <BitWidth>0x8</BitWidth>
  419. <Access>RW</Access>
  420. <Values>
  421. <Val value="0xAA">Level 0, no protection</Val>
  422. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  423. <Val value="0xCC">Level 2, chip protection</Val>
  424. </Values>
  425. </Bit>
  426. </AssignedBits>
  427. </Field>
  428. </Category>
  429. <Category>
  430. <Name>PCROP Protection</Name>
  431. <Field>
  432. <Parameters address="0x1FFFC008" name="FLASH_OPTCR" size="0x4"/>
  433. <AssignedBits>
  434. <Bit reference="SPRMode">
  435. <Name>SPRMOD</Name>
  436. <Description>Selection of protection mode for nWPRi bits.</Description>
  437. <BitOffset>0xF</BitOffset>
  438. <BitWidth>0x1</BitWidth>
  439. <Access>RW</Access>
  440. <Values>
  441. <Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
  442. <Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
  443. </Values>
  444. </Bit>
  445. </AssignedBits>
  446. </Field>
  447. </Category>
  448. <Category>
  449. <Name>BOR Level</Name>
  450. <Field>
  451. <Parameters address="0x1FFFC000" name="USER" size="0x4"/>
  452. <AssignedBits>
  453. <Bit>
  454. <Name>BOR_LEV</Name>
  455. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  456. <BitOffset>0x2</BitOffset>
  457. <BitWidth>0x2</BitWidth>
  458. <Access>RW</Access>
  459. <Values>
  460. <Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
  461. <Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
  462. <Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
  463. <Val value="0x3">BOR OFF reset threshold level from 1.80 to 2.10 V</Val>
  464. </Values>
  465. </Bit>
  466. </AssignedBits>
  467. </Field>
  468. </Category>
  469. <Category>
  470. <Name>User Configuration</Name>
  471. <Field>
  472. <Parameters address="0x1FFFC000" name="USER" size="0x4"/>
  473. <AssignedBits>
  474. <Bit>
  475. <Name>BFB2</Name>
  476. <Description/>
  477. <BitOffset>0x4</BitOffset>
  478. <BitWidth>0x1</BitWidth>
  479. <Access>RW</Access>
  480. <Values>
  481. <Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
  482. <Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
  483. </Values>
  484. </Bit>
  485. <Bit>
  486. <Name>WDG_SW</Name>
  487. <Description/>
  488. <BitOffset>0x5</BitOffset>
  489. <BitWidth>0x1</BitWidth>
  490. <Access>RW</Access>
  491. <Values>
  492. <Val value="0x0">Hardware watchdog</Val>
  493. <Val value="0x1">Software watchdog</Val>
  494. </Values>
  495. </Bit>
  496. <Bit>
  497. <Name>nRST_STOP</Name>
  498. <Description/>
  499. <BitOffset>0x6</BitOffset>
  500. <BitWidth>0x1</BitWidth>
  501. <Access>RW</Access>
  502. <Values>
  503. <Val value="0x0">Reset generated when entering Stop mode</Val>
  504. <Val value="0x1">No reset generated</Val>
  505. </Values>
  506. </Bit>
  507. <Bit>
  508. <Name>nRST_STDBY</Name>
  509. <Description/>
  510. <BitOffset>0x7</BitOffset>
  511. <BitWidth>0x1</BitWidth>
  512. <Access>RW</Access>
  513. <Values>
  514. <Val value="0x0">Reset generated when entering Standby mode</Val>
  515. <Val value="0x1">No reset generated</Val>
  516. </Values>
  517. </Bit>
  518. <Bit config="2,3,4,5">
  519. <Name>DB1M</Name>
  520. <Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
  521. <BitOffset>0x1E</BitOffset>
  522. <BitWidth>0x1</BitWidth>
  523. <Access>RW</Access>
  524. <Values>
  525. <Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
  526. <Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
  527. </Values>
  528. </Bit>
  529. </AssignedBits>
  530. </Field>
  531. </Category>
  532. <Category>
  533. <Name>Write Protection</Name>
  534. <Field>
  535. <Parameters address="0x1FFFC008" name="WRP0" size="0x4"/>
  536. <AssignedBits>
  537. <Bit config="0,2,4">
  538. <Name>nWRP0</Name>
  539. <Description/>
  540. <BitOffset>0x0</BitOffset>
  541. <BitWidth>0xC</BitWidth>
  542. <Access>RW</Access>
  543. <Values ByBit="true">
  544. <Val value="0x0">Write protection active</Val>
  545. <Val value="0x1">Write protection not active</Val>
  546. </Values>
  547. </Bit>
  548. <Bit config="1,3,5,6">
  549. <Name>nWRP0</Name>
  550. <Description/>
  551. <BitOffset>0x0</BitOffset>
  552. <BitWidth>0xC</BitWidth>
  553. <Access>RW</Access>
  554. <Values ByBit="true">
  555. <Val value="0x0">PCROP protection not active on sector i</Val>
  556. <Val value="0x1">PCROP protection active on sector i</Val>
  557. </Values>
  558. </Bit>
  559. </AssignedBits>
  560. </Field>
  561. </Category>
  562. </Bank>
  563. <Bank interface="Bootloader">
  564. <Parameters address="0x1FFEC008" name="Bank 2" size="0x4"/>
  565. <Category>
  566. <Name>Write Protection</Name>
  567. <Field>
  568. <Parameters address="0x1FFEC008" name="WRP1" size="0x4"/>
  569. <AssignedBits>
  570. <Bit config="0,2,4">
  571. <Name>nWRP12</Name>
  572. <Description/>
  573. <BitOffset>0x0</BitOffset>
  574. <BitWidth>0xC</BitWidth>
  575. <Access>RW</Access>
  576. <Values ByBit="true">
  577. <Val value="0x0">Write protection active</Val>
  578. <Val value="0x1">Write protection not active</Val>
  579. </Values>
  580. </Bit>
  581. <Bit config="1,3,5,6">
  582. <Name>nWRP12</Name>
  583. <Description/>
  584. <BitOffset>0x0</BitOffset>
  585. <BitWidth>0xC</BitWidth>
  586. <Access>RW</Access>
  587. <Values ByBit="true">
  588. <Val value="0x0">PCROP protection not active on sector i</Val>
  589. <Val value="0x1">PCROP protection active on sector i</Val>
  590. </Values>
  591. </Bit>
  592. </AssignedBits>
  593. </Field>
  594. </Category>
  595. </Bank>
  596. </Peripheral>
  597. </Peripherals>
  598. </Device>
  599. </Root>