STM32_Prog_DB_0x444.xml 6.5 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x444</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M0</CPU>
  8. <Name>STM32F03x</Name>
  9. <Series>STM32F0</Series>
  10. <Description>ARM 32-bit Cortex-M0 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD"/>
  14. <!-- Bootloader Interface -->
  15. <Interface name="Bootloader"/>
  16. </Configurations>
  17. <!-- Peripherals -->
  18. <Peripherals>
  19. <!-- Embedded SRAM -->
  20. <Peripheral>
  21. <Name>Embedded SRAM</Name>
  22. <Type>Storage</Type>
  23. <Description/>
  24. <ErasedValue>0x00</ErasedValue>
  25. <Access>RWE</Access>
  26. <!-- 4 KB -->
  27. <Configuration>
  28. <Parameters address="0x20000000" name="SRAM" size="0x1000"/>
  29. <Description/>
  30. <Organization>Single</Organization>
  31. <Bank name="Bank 1">
  32. <Field>
  33. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x1000"/>
  34. </Field>
  35. </Bank>
  36. </Configuration>
  37. </Peripheral>
  38. <!-- Embedded Flash -->
  39. <Peripheral>
  40. <Name>Embedded Flash</Name>
  41. <Type>Storage</Type>
  42. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  43. <ErasedValue>0xFF</ErasedValue>
  44. <Access>RWE</Access>
  45. <FlashSize address="0x1FFFF7CC" default="0x8000"/>
  46. <!-- 32KB single Bank -->
  47. <Configuration>
  48. <Parameters address="0x08000000" name=" 32 Kbytes Embedded Flash" size="0x8000"/>
  49. <Description/>
  50. <Organization>Single</Organization>
  51. <Allignement>0x4</Allignement>
  52. <Bank name="Bank 1">
  53. <Field>
  54. <Parameters address="0x08000000" name="sector0" occurence="0x20" size="0x400"/>
  55. </Field>
  56. </Bank>
  57. </Configuration>
  58. </Peripheral>
  59. <!-- Option Bytes -->
  60. <Peripheral>
  61. <Name>Option Bytes</Name>
  62. <Type>Configuration</Type>
  63. <Description/>
  64. <Access>RW</Access>
  65. <Bank>
  66. <Parameters address="0x1FFFF800" name="Bank 1" size="0x10"/>
  67. <Category>
  68. <Name>Read Out Protection</Name>
  69. <Field>
  70. <Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
  71. <AssignedBits>
  72. <Bit>
  73. <Name>RDP</Name>
  74. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  75. <BitOffset>0x0</BitOffset>
  76. <BitWidth>0x8</BitWidth>
  77. <Access>RW</Access>
  78. <Values>
  79. <Val value="0xAA">Level 0, no protection</Val>
  80. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  81. <Val value="0xCC">Level 2, chip protection</Val>
  82. </Values>
  83. </Bit>
  84. </AssignedBits>
  85. </Field>
  86. </Category>
  87. <Category>
  88. <Name>User Configuration</Name>
  89. <Field>
  90. <Parameters address="0x1FFFF800" name="USR_RDP" size="0x4"/>
  91. <AssignedBits>
  92. <Bit>
  93. <Name>WDG_SW</Name>
  94. <Description/>
  95. <BitOffset>0x10</BitOffset>
  96. <BitWidth>0x1</BitWidth>
  97. <Access>RW</Access>
  98. <Values>
  99. <Val value="0x0">Hardware watchdog</Val>
  100. <Val value="0x1">Software watchdog</Val>
  101. </Values>
  102. </Bit>
  103. <Bit>
  104. <Name>nRST_STOP</Name>
  105. <Description/>
  106. <BitOffset>0x11</BitOffset>
  107. <BitWidth>0x1</BitWidth>
  108. <Access>RW</Access>
  109. <Values>
  110. <Val value="0x0">Reset generated when entering Stop mode</Val>
  111. <Val value="0x1">No reset generated</Val>
  112. </Values>
  113. </Bit>
  114. <Bit>
  115. <Name>nRST_STDBY</Name>
  116. <Description/>
  117. <BitOffset>0x12</BitOffset>
  118. <BitWidth>0x1</BitWidth>
  119. <Access>RW</Access>
  120. <Values>
  121. <Val value="0x0">Reset generated when entering Standby mode</Val>
  122. <Val value="0x1">No reset generated</Val>
  123. </Values>
  124. </Bit>
  125. <Bit>
  126. <Name>nBOOT1</Name>
  127. <Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
  128. <BitOffset>0x14</BitOffset>
  129. <BitWidth>0x1</BitWidth>
  130. <Access>RW</Access>
  131. <Values>
  132. <Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
  133. <Val value="0x1">Boot from system flash when BOOT0=1</Val>
  134. </Values>
  135. </Bit>
  136. <Bit>
  137. <Name>VDDA_MONITOR</Name>
  138. <Description/>
  139. <BitOffset>0x15</BitOffset>
  140. <BitWidth>0x1</BitWidth>
  141. <Access>RW</Access>
  142. <Values>
  143. <Val value="0x0">VDDA power supply supervisor disabled</Val>
  144. <Val value="0x1">VDDA power supply supervisor enabled</Val>
  145. </Values>
  146. </Bit>
  147. <Bit>
  148. <Name>RAM_PARITY</Name>
  149. <Description/>
  150. <BitOffset>0x16</BitOffset>
  151. <BitWidth>0x1</BitWidth>
  152. <Access>RW</Access>
  153. <Values>
  154. <Val value="0x0">RAM parity check enabled</Val>
  155. <Val value="0x1">RAM parity check disabled</Val>
  156. </Values>
  157. </Bit>
  158. </AssignedBits>
  159. </Field>
  160. </Category>
  161. <Category>
  162. <Name>User Data</Name>
  163. <Field>
  164. <Parameters address="0x1FFFF804" name="USR_DATA" size="0x4"/>
  165. <AssignedBits>
  166. <Bit>
  167. <Name>Data0</Name>
  168. <Description>User data 0 (8-bit)</Description>
  169. <BitOffset>0x0</BitOffset>
  170. <BitWidth>0x8</BitWidth>
  171. <Access>RW</Access>
  172. </Bit>
  173. <Bit>
  174. <Name>Data1</Name>
  175. <Description>User data 1 (8-bit)</Description>
  176. <BitOffset>0x10</BitOffset>
  177. <BitWidth>0x8</BitWidth>
  178. <Access>RW</Access>
  179. </Bit>
  180. </AssignedBits>
  181. </Field>
  182. </Category>
  183. <Category>
  184. <Name>Write Protection</Name>
  185. <Field>
  186. <Parameters address="0x1FFFF808" name="WRP_0_1" size="0x4"/>
  187. <AssignedBits>
  188. <Bit>
  189. <Name>nWRP0</Name>
  190. <Description/>
  191. <BitOffset>0x0</BitOffset>
  192. <BitWidth>0x8</BitWidth>
  193. <Access>RW</Access>
  194. <Values ByBit="true">
  195. <Val value="0x0">Write protection active on this sector</Val>
  196. <Val value="0x1">Write protection not active on this sector</Val>
  197. </Values>
  198. </Bit>
  199. </AssignedBits>
  200. </Field>
  201. </Category>
  202. </Bank>
  203. </Peripheral>
  204. </Peripherals>
  205. </Device>
  206. </Root>