STM32_Prog_DB_0x447.xml 29 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x447</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M0+</CPU>
  8. <Name>STM32L07x/L08x/L010</Name>
  9. <Series>STM32L0</Series>
  10. <Description>ARM 32-bit Cortex-M0+ based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  15. <WPRMOD reference="0x1">
  16. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
  17. </WPRMOD>
  18. <ValueLine>
  19. <ReadRegister address="0x1FF8007C" mask="0x0000FFFF" value="0x0080"/>
  20. </ValueLine>
  21. </Configuration>
  22. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  23. <WPRMOD reference="0x0">
  24. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
  25. </WPRMOD>
  26. <ValueLine>
  27. <ReadRegister address="0x1FF8007C" mask="0x0000FFFF" value="0x0080"/>
  28. </ValueLine>
  29. </Configuration>
  30. <Configuration number="0x2"> <!-- WRPx control the write protection of user sector-->
  31. <WPRMOD reference="0x1">
  32. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
  33. </WPRMOD>
  34. </Configuration>
  35. <Configuration number="0x3"> <!-- WRPx control the read/write protection PcROP-->
  36. <WPRMOD reference="0x0">
  37. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
  38. </WPRMOD>
  39. </Configuration>
  40. </Interface>
  41. <!-- Bootloader Interface -->
  42. <Interface name="Bootloader">
  43. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  44. <WPRMOD reference="0x1">
  45. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
  46. </WPRMOD>
  47. <ValueLine>
  48. <ReadRegister address="0x1FF00000" mask="0xFFFFFFFF" value="0x20001290"/>
  49. </ValueLine>
  50. </Configuration>
  51. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  52. <WPRMOD reference="0x0">
  53. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
  54. </WPRMOD>
  55. <ValueLine>
  56. <ReadRegister address="0x1FF00000" mask="0xFFFFFFFF" value="0x20001290"/>
  57. </ValueLine>
  58. </Configuration>
  59. <Configuration number="0x2"> <!-- WRPx control the write protection of user sector-->
  60. <WPRMOD reference="0x1">
  61. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
  62. </WPRMOD>
  63. </Configuration>
  64. <Configuration number="0x3"> <!-- WRPx control the read/write protection PcROP-->
  65. <WPRMOD reference="0x0">
  66. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
  67. </WPRMOD>
  68. </Configuration>
  69. </Interface>
  70. </Configurations>
  71. <!-- Peripherals -->
  72. <Peripherals>
  73. <!-- Embedded SRAM -->
  74. <Peripheral>
  75. <Name>Embedded SRAM</Name>
  76. <Type>Storage</Type>
  77. <Description/>
  78. <ErasedValue>0x00</ErasedValue>
  79. <Access>RWE</Access>
  80. <!-- 20 KB -->
  81. <Configuration>
  82. <Parameters address="0x20000000" name="SRAM" size="0x5000"/>
  83. <Description/>
  84. <Organization>Single</Organization>
  85. <Bank name="Bank 1">
  86. <Field>
  87. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x5000"/>
  88. </Field>
  89. </Bank>
  90. </Configuration>
  91. </Peripheral>
  92. <!-- Embedded Flash -->
  93. <Peripheral>
  94. <Name>Embedded Flash</Name>
  95. <Type>Storage</Type>
  96. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  97. <ErasedValue>0x00</ErasedValue>
  98. <Access>RWE</Access>
  99. <FlashSize address="0x1FF8007C" default="0x30000"/>
  100. <!-- 128KB single Bank -->
  101. <Configuration config="0,1">
  102. <Parameters address="0x08000000" name="128 Kbytes Embedded Flash" size="0x20000"/>
  103. <Description/>
  104. <Organization>Single</Organization>
  105. <Allignement>0x4</Allignement>
  106. <Bank name="Bank 1">
  107. <Field>
  108. <Parameters address="0x08000000" name="sector0" occurence="0x400" size="0x80"/>
  109. </Field>
  110. </Bank>
  111. <Bank name="EEPROM1">
  112. <Field>
  113. <Parameters address="0x08080000" name="sector65281" occurence="0x1" size="0xC00"/>
  114. </Field>
  115. </Bank>
  116. <Bank name="EEPROM2">
  117. <Field>
  118. <Parameters address="0x08080C00" name="sector65282" occurence="0x1" size="0xC00"/>
  119. </Field>
  120. </Bank>
  121. </Configuration>
  122. <Configuration config="2,3">
  123. <Parameters address="0x08000000" name="192 Kbytes Embedded Flash" size="0x30000"/>
  124. <Description/>
  125. <Organization>Single</Organization>
  126. <Allignement>0x4</Allignement>
  127. <Bank name="Bank 1">
  128. <Field>
  129. <Parameters address="0x08000000" name="sector0" occurence="0x600" size="0x80"/>
  130. </Field>
  131. </Bank>
  132. <Bank name="EEPROM1">
  133. <Field>
  134. <Parameters address="0x08080000" name="sector65281" occurence="0x1" size="0xC00"/>
  135. </Field>
  136. </Bank>
  137. <Bank name="EEPROM2">
  138. <Field>
  139. <Parameters address="0x08080C00" name="sector65282" occurence="0x1" size="0xC00"/>
  140. </Field>
  141. </Bank>
  142. </Configuration>
  143. </Peripheral>
  144. <!-- Data EEPROM -->
  145. <Peripheral>
  146. <Name>Data EEPROM</Name>
  147. <Type>Storage</Type>
  148. <Description>The Data EEPROM memory block. It contains user data.</Description>
  149. <ErasedValue>0x00</ErasedValue>
  150. <Access>RWE</Access>
  151. <!-- 1KB single Bank -->
  152. <Configuration>
  153. <Parameters address="0x08080000" name=" 2 Kbytes Data EEPROM" size="0x1800"/>
  154. <Description/>
  155. <Organization>Single</Organization>
  156. <Allignement>0x4</Allignement>
  157. <Bank name="Bank 1">
  158. <Field>
  159. <Parameters address="0x08080000" name="EEPROM1" occurence="0x1" size="0xC00"/>
  160. </Field>
  161. </Bank>
  162. <Bank name="Bank 2">
  163. <Field>
  164. <Parameters address="0x08080C00" name="EEPROM2" occurence="0x1" size="0xC00"/>
  165. </Field>
  166. </Bank>
  167. </Configuration>
  168. </Peripheral>
  169. <!-- Mirror Option Bytes -->
  170. <Peripheral>
  171. <Name>MirrorOptionBytes</Name>
  172. <Type>Storage</Type>
  173. <Description>Mirror Option Bytes contains the extra area.</Description>
  174. <ErasedValue>0xFF</ErasedValue>
  175. <Access>RW</Access>
  176. <!-- 20 Bytes single bank -->
  177. <Configuration>
  178. <Parameters address="0x1FF80000" name=" 20 Bytes Data MirrorOptionBytes" size="0x14"/>
  179. <Description/>
  180. <Organization>Single</Organization>
  181. <Allignement>0x4</Allignement>
  182. <Bank name="MirrorOptionBytes">
  183. <Field>
  184. <Parameters address="0x1FF80000" name="MirrorOptionBytes" occurence="0x1" size="0x14"/>
  185. </Field>
  186. </Bank>
  187. </Configuration>
  188. </Peripheral>
  189. <!-- Option Bytes -->
  190. <Peripheral>
  191. <Name>Option Bytes</Name>
  192. <Type>Configuration</Type>
  193. <Description/>
  194. <Access>RW</Access>
  195. <Bank interface="JTAG_SWD">
  196. <Parameters address="0x4002201C" name="Bank 1" size="0x68"/>
  197. <Category>
  198. <Name>Read Out Protection</Name>
  199. <Field>
  200. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  201. <AssignedBits>
  202. <Bit>
  203. <Name>RDP</Name>
  204. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  205. <BitOffset>0x0</BitOffset>
  206. <BitWidth>0x8</BitWidth>
  207. <Access>R</Access>
  208. <Values>
  209. <Val value="0xAA">Level 0, no protection</Val>
  210. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  211. <Val value="0xCC">Level 2, chip protection</Val>
  212. </Values>
  213. </Bit>
  214. </AssignedBits>
  215. </Field>
  216. </Category>
  217. <Category>
  218. <Name>PCROP Protection</Name>
  219. <Field>
  220. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  221. <AssignedBits>
  222. <Bit reference="SPRMode">
  223. <Name>WPRMOD</Name>
  224. <Description>Sector protection mode selection option byte.</Description>
  225. <BitOffset>0x8</BitOffset>
  226. <BitWidth>0x1</BitWidth>
  227. <Access>R</Access>
  228. <Values>
  229. <Val value="0x0">WRPx bit defines sector write protection</Val>
  230. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  231. </Values>
  232. </Bit>
  233. </AssignedBits>
  234. </Field>
  235. </Category>
  236. <Category>
  237. <Name>BOR Level</Name>
  238. <Field>
  239. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  240. <AssignedBits>
  241. <Bit>
  242. <Name>BOR_LEV</Name>
  243. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  244. <BitOffset>0x10</BitOffset>
  245. <BitWidth>0x4</BitWidth>
  246. <Access>R</Access>
  247. <Values>
  248. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  249. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  250. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  251. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  252. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  253. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  254. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  255. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  256. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  257. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  258. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  259. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  260. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  261. </Values>
  262. </Bit>
  263. </AssignedBits>
  264. </Field>
  265. </Category>
  266. <Category>
  267. <Name>User Configuration</Name>
  268. <Field>
  269. <Parameters address="0x4002201C" nname="FLASH_OBR" size="0x4"/>
  270. <AssignedBits>
  271. <Bit>
  272. <Name>IWDG_SW</Name>
  273. <Description/>
  274. <BitOffset>0x14</BitOffset>
  275. <BitWidth>0x1</BitWidth>
  276. <Access>R</Access>
  277. <Values>
  278. <Val value="0x0">Hardware independant watchdog</Val>
  279. <Val value="0x1">Software independant watchdog</Val>
  280. </Values>
  281. </Bit>
  282. <Bit>
  283. <Name>nRST_STOP</Name>
  284. <Description/>
  285. <BitOffset>0x15</BitOffset>
  286. <BitWidth>0x1</BitWidth>
  287. <Access>R</Access>
  288. <Values>
  289. <Val value="0x0">Reset generated when entering Stop mode</Val>
  290. <Val value="0x1">No reset generated</Val>
  291. </Values>
  292. </Bit>
  293. <Bit>
  294. <Name>nRST_STDBY</Name>
  295. <Description/>
  296. <BitOffset>0x16</BitOffset>
  297. <BitWidth>0x1</BitWidth>
  298. <Access>R</Access>
  299. <Values>
  300. <Val value="0x0">Reset generated when entering Standby mode</Val>
  301. <Val value="0x1">No reset generated</Val>
  302. </Values>
  303. </Bit>
  304. <Bit>
  305. <Name>BFB2</Name>
  306. <Description/>
  307. <BitOffset>0x17</BitOffset>
  308. <BitWidth>0x1</BitWidth>
  309. <Access>R</Access>
  310. <Values>
  311. <Val value="0x0">Boot from flash bank 1</Val>
  312. <Val value="0x1">boot from flash bank 2</Val>
  313. </Values>
  314. </Bit>
  315. <Bit>
  316. <Name>nBOOT1</Name>
  317. <Description/>
  318. <BitOffset>0x1F</BitOffset>
  319. <BitWidth>0x1</BitWidth>
  320. <Access>R</Access>
  321. <Values>
  322. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  323. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  324. </Values>
  325. </Bit>
  326. </AssignedBits>
  327. </Field>
  328. </Category>
  329. <Category>
  330. <Name>Write Protection</Name>
  331. <Field>
  332. <Parameters address="0x40022020" name="FLASH_WRPROT1" size="0x4"/>
  333. <AssignedBits>
  334. <Bit config="0,2">
  335. <Name>WRPOT0</Name>
  336. <Description/>
  337. <BitOffset>0x0</BitOffset>
  338. <BitWidth>0x20</BitWidth>
  339. <Access>R</Access>
  340. <Values ByBit="true">
  341. <Val value="0x0">Write protection not active</Val>
  342. <Val value="0x1">Write protection active</Val>
  343. </Values>
  344. </Bit>
  345. <Bit config="1,3">
  346. <Name>WRPOT0</Name>
  347. <Description/>
  348. <BitOffset>0x0</BitOffset>
  349. <BitWidth>0x20</BitWidth>
  350. <Access>R</Access>
  351. <Values ByBit="true">
  352. <Val value="0x0">read/Write protection active</Val>
  353. <Val value="0x1">read/Write protection not active</Val>
  354. </Values>
  355. </Bit>
  356. </AssignedBits>
  357. </Field>
  358. <Field>
  359. <Parameters address="0x40022080" name="FLASH_WRPROT2" size="0x4"/>
  360. <AssignedBits>
  361. <Bit config="0,2">
  362. <Name>WRPOT32</Name>
  363. <Description/>
  364. <BitOffset>0x0</BitOffset>
  365. <BitWidth>0x10</BitWidth>
  366. <Access>R</Access>
  367. <Values ByBit="true">
  368. <Val value="0x0">Write protection not active</Val>
  369. <Val value="0x1">Write protection active</Val>
  370. </Values>
  371. </Bit>
  372. <Bit config="1,3">
  373. <Name>WRPOT32</Name>
  374. <Description/>
  375. <BitOffset>0x0</BitOffset>
  376. <BitWidth>0x10</BitWidth>
  377. <Access>R</Access>
  378. <Values ByBit="true">
  379. <Val value="0x0">read/Write protection active</Val>
  380. <Val value="0x1">read/Write protection not active</Val>
  381. </Values>
  382. </Bit>
  383. </AssignedBits>
  384. </Field>
  385. </Category>
  386. </Bank>
  387. <Bank interface="JTAG_SWD">
  388. <Parameters address="0x1FF80000" name="Bank 2" size="0x14"/>
  389. <Category>
  390. <Name>Read Out Protection</Name>
  391. <Field>
  392. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  393. <AssignedBits>
  394. <Bit>
  395. <Name>RDP</Name>
  396. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  397. <BitOffset>0x0</BitOffset>
  398. <BitWidth>0x8</BitWidth>
  399. <Access>W</Access>
  400. <Values>
  401. <Val value="0xAA">Level 0, no protection</Val>
  402. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  403. <Val value="0xCC">Level 2, chip protection</Val>
  404. </Values>
  405. </Bit>
  406. </AssignedBits>
  407. </Field>
  408. </Category>
  409. <Category>
  410. <Name>PCROP Protection</Name>
  411. <Field>
  412. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  413. <AssignedBits>
  414. <Bit reference="SPRMode">
  415. <Name>WPRMOD</Name>
  416. <Description>Sector protection mode selection option byte.</Description>
  417. <BitOffset>0x8</BitOffset>
  418. <BitWidth>0x1</BitWidth>
  419. <Access>W</Access>
  420. <Values>
  421. <Val value="0x0">WRPx bit defines sector write protection</Val>
  422. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  423. </Values>
  424. </Bit>
  425. </AssignedBits>
  426. </Field>
  427. </Category>
  428. <Category>
  429. <Name>BOR Level</Name>
  430. <Field>
  431. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  432. <AssignedBits>
  433. <Bit>
  434. <Name>BOR_LEV</Name>
  435. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  436. <BitOffset>0x0</BitOffset>
  437. <BitWidth>0x4</BitWidth>
  438. <Access>W</Access>
  439. <Values>
  440. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  441. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  442. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  443. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  444. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  445. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  446. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  447. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  448. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  449. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  450. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  451. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  452. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  453. </Values>
  454. </Bit>
  455. </AssignedBits>
  456. </Field>
  457. </Category>
  458. <Category>
  459. <Name>User Configuration</Name>
  460. <Field>
  461. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  462. <AssignedBits>
  463. <Bit>
  464. <Name>IWDG_SW</Name>
  465. <Description/>
  466. <BitOffset>0x4</BitOffset>
  467. <BitWidth>0x1</BitWidth>
  468. <Access>W</Access>
  469. <Values>
  470. <Val value="0x0">Hardware independant watchdog</Val>
  471. <Val value="0x1">Software independant watchdog</Val>
  472. </Values>
  473. </Bit>
  474. <Bit>
  475. <Name>nRST_STOP</Name>
  476. <Description/>
  477. <BitOffset>0x5</BitOffset>
  478. <BitWidth>0x1</BitWidth>
  479. <Access>W</Access>
  480. <Values>
  481. <Val value="0x0">Reset generated when entering Stop mode</Val>
  482. <Val value="0x1">No reset generated</Val>
  483. </Values>
  484. </Bit>
  485. <Bit>
  486. <Name>nRST_STDBY</Name>
  487. <Description/>
  488. <BitOffset>0x6</BitOffset>
  489. <BitWidth>0x1</BitWidth>
  490. <Access>W</Access>
  491. <Values>
  492. <Val value="0x0">Reset generated when entering Standby mode</Val>
  493. <Val value="0x1">No reset generated</Val>
  494. </Values>
  495. </Bit>
  496. <Bit>
  497. <Name>BFB2</Name>
  498. <Description/>
  499. <BitOffset>0x7</BitOffset>
  500. <BitWidth>0x1</BitWidth>
  501. <Access>W</Access>
  502. <Values>
  503. <Val value="0x0">Boot from flash bank 1</Val>
  504. <Val value="0x1">boot from flash bank 2</Val>
  505. </Values>
  506. </Bit>
  507. <Bit>
  508. <Name>nBOOT1</Name>
  509. <Description/>
  510. <BitOffset>0x0F</BitOffset>
  511. <BitWidth>0x1</BitWidth>
  512. <Access>W</Access>
  513. <Values>
  514. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  515. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  516. </Values>
  517. </Bit>
  518. </AssignedBits>
  519. </Field>
  520. </Category>
  521. <Category>
  522. <Name>Write Protection</Name>
  523. <Field>
  524. <Parameters address="0x1FF80008" name="FLASH_WRPROT11" size="0x4"/>
  525. <AssignedBits>
  526. <Bit config="0,2">
  527. <Name>WRPOT0</Name>
  528. <Description/>
  529. <BitOffset>0x0</BitOffset>
  530. <BitWidth>0x10</BitWidth>
  531. <Access>W</Access>
  532. <Values ByBit="true">
  533. <Val value="0x0">Write protection not active</Val>
  534. <Val value="0x1">Write protection active</Val>
  535. </Values>
  536. </Bit>
  537. <Bit config="1,3">
  538. <Name>WRPOT0</Name>
  539. <Description/>
  540. <BitOffset>0x0</BitOffset>
  541. <BitWidth>0x10</BitWidth>
  542. <Access>W</Access>
  543. <Values ByBit="true">
  544. <Val value="0x0">read/Write protection active</Val>
  545. <Val value="0x1">read/Write protection not active</Val>
  546. </Values>
  547. </Bit>
  548. </AssignedBits>
  549. </Field>
  550. <Field>
  551. <Parameters address="0x1FF8000C" name="FLASH_WRPROT12" size="0x4"/>
  552. <AssignedBits>
  553. <Bit config="0,2">
  554. <Name>WRPOT16</Name>
  555. <Description/>
  556. <BitOffset>0x0</BitOffset>
  557. <BitWidth>0x10</BitWidth>
  558. <Access>W</Access>
  559. <Values ByBit="true">
  560. <Val value="0x0">Write protection not active</Val>
  561. <Val value="0x1">Write protection active</Val>
  562. </Values>
  563. </Bit>
  564. <Bit config="1,3">
  565. <Name>WRPOT16</Name>
  566. <Description/>
  567. <BitOffset>0x0</BitOffset>
  568. <BitWidth>0x10</BitWidth>
  569. <Access>W</Access>
  570. <Values ByBit="true">
  571. <Val value="0x0">read/Write protection active</Val>
  572. <Val value="0x1">read/Write protection not active</Val>
  573. </Values>
  574. </Bit>
  575. </AssignedBits>
  576. </Field>
  577. <Field>
  578. <Parameters address="0x1FF80010" name="FLASH_WRPROT2" size="0x4"/>
  579. <AssignedBits>
  580. <Bit config="0,2">
  581. <Name>WRPOT32</Name>
  582. <Description/>
  583. <BitOffset>0x0</BitOffset>
  584. <BitWidth>0x10</BitWidth>
  585. <Access>W</Access>
  586. <Values ByBit="true">
  587. <Val value="0x0">Write protection not active</Val>
  588. <Val value="0x1">Write protection active</Val>
  589. </Values>
  590. </Bit>
  591. <Bit config="1,3">
  592. <Name>WRPOT32</Name>
  593. <Description/>
  594. <BitOffset>0x0</BitOffset>
  595. <BitWidth>0x10</BitWidth>
  596. <Access>W</Access>
  597. <Values ByBit="true">
  598. <Val value="0x0">read/Write protection active</Val>
  599. <Val value="0x1">read/Write protection not active</Val>
  600. </Values>
  601. </Bit>
  602. </AssignedBits>
  603. </Field>
  604. </Category>
  605. </Bank>
  606. <Bank interface="Bootloader">
  607. <Parameters address="0x1FF80000" name="Bank 1" size="0x14"/>
  608. <Category>
  609. <Name>Read Out Protection</Name>
  610. <Field>
  611. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  612. <AssignedBits>
  613. <Bit>
  614. <Name>RDP</Name>
  615. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  616. <BitOffset>0x0</BitOffset>
  617. <BitWidth>0x8</BitWidth>
  618. <Access>RW</Access>
  619. <Values>
  620. <Val value="0xAA">Level 0, no protection</Val>
  621. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  622. <Val value="0xCC">Level 2, chip protection</Val>
  623. </Values>
  624. </Bit>
  625. </AssignedBits>
  626. </Field>
  627. </Category>
  628. <Category>
  629. <Name>PCROP Protection</Name>
  630. <Field>
  631. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  632. <AssignedBits>
  633. <Bit reference="SPRMode">
  634. <Name>WPRMOD</Name>
  635. <Description>Sector protection mode selection option byte.</Description>
  636. <BitOffset>0x8</BitOffset>
  637. <BitWidth>0x1</BitWidth>
  638. <Access>RW</Access>
  639. <Values>
  640. <Val value="0x0">WRPx bit defines sector write protection</Val>
  641. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  642. </Values>
  643. </Bit>
  644. </AssignedBits>
  645. </Field>
  646. </Category>
  647. <Category>
  648. <Name>BOR Level</Name>
  649. <Field>
  650. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  651. <AssignedBits>
  652. <Bit>
  653. <Name>BOR_LEV</Name>
  654. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  655. <BitOffset>0x0</BitOffset>
  656. <BitWidth>0x4</BitWidth>
  657. <Access>RW</Access>
  658. <Values>
  659. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  660. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  661. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  662. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  663. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  664. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  665. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  666. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  667. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  668. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  669. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  670. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  671. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  672. </Values>
  673. </Bit>
  674. </AssignedBits>
  675. </Field>
  676. </Category>
  677. <Category>
  678. <Name>User Configuration</Name>
  679. <Field>
  680. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  681. <AssignedBits>
  682. <Bit>
  683. <Name>IWDG_SW</Name>
  684. <Description/>
  685. <BitOffset>0x4</BitOffset>
  686. <BitWidth>0x1</BitWidth>
  687. <Access>RW</Access>
  688. <Values>
  689. <Val value="0x0">Hardware independant watchdog</Val>
  690. <Val value="0x1">Software independant watchdog</Val>
  691. </Values>
  692. </Bit>
  693. <Bit>
  694. <Name>nRST_STOP</Name>
  695. <Description/>
  696. <BitOffset>0x5</BitOffset>
  697. <BitWidth>0x1</BitWidth>
  698. <Access>RW</Access>
  699. <Values>
  700. <Val value="0x0">Reset generated when entering Stop mode</Val>
  701. <Val value="0x1">No reset generated</Val>
  702. </Values>
  703. </Bit>
  704. <Bit>
  705. <Name>nRST_STDBY</Name>
  706. <Description/>
  707. <BitOffset>0x6</BitOffset>
  708. <BitWidth>0x1</BitWidth>
  709. <Access>RW</Access>
  710. <Values>
  711. <Val value="0x0">Reset generated when entering Standby mode</Val>
  712. <Val value="0x1">No reset generated</Val>
  713. </Values>
  714. </Bit>
  715. <Bit>
  716. <Name>BFB2</Name>
  717. <Description/>
  718. <BitOffset>0x7</BitOffset>
  719. <BitWidth>0x1</BitWidth>
  720. <Access>RW</Access>
  721. <Values>
  722. <Val value="0x0">Boot from flash bank 1</Val>
  723. <Val value="0x1">boot from flash bank 2</Val>
  724. </Values>
  725. </Bit>
  726. <Bit>
  727. <Name>nBOOT1</Name>
  728. <Description/>
  729. <BitOffset>0x0F</BitOffset>
  730. <BitWidth>0x1</BitWidth>
  731. <Access>RW</Access>
  732. <Values>
  733. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  734. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  735. </Values>
  736. </Bit>
  737. </AssignedBits>
  738. </Field>
  739. </Category>
  740. <Category>
  741. <Name>Write Protection</Name>
  742. <Field>
  743. <Parameters address="0x1FF80008" name="FLASH_WRPROT11" size="0x4"/>
  744. <AssignedBits>
  745. <Bit config="0,2">
  746. <Name>WRPOT0</Name>
  747. <Description/>
  748. <BitOffset>0x0</BitOffset>
  749. <BitWidth>0x10</BitWidth>
  750. <Access>RW</Access>
  751. <Values ByBit="true">
  752. <Val value="0x0">Write protection not active</Val>
  753. <Val value="0x1">Write protection active</Val>
  754. </Values>
  755. </Bit>
  756. <Bit config="1,3">
  757. <Name>WRPOT0</Name>
  758. <Description/>
  759. <BitOffset>0x0</BitOffset>
  760. <BitWidth>0x10</BitWidth>
  761. <Access>RW</Access>
  762. <Values ByBit="true">
  763. <Val value="0x0">read/Write protection active</Val>
  764. <Val value="0x1">read/Write protection not active</Val>
  765. </Values>
  766. </Bit>
  767. </AssignedBits>
  768. </Field>
  769. <Field>
  770. <Parameters address="0x1FF8000C" name="FLASH_WRPROT12" size="0x4"/>
  771. <AssignedBits>
  772. <Bit config="0,2">
  773. <Name>WRPOT16</Name>
  774. <Description/>
  775. <BitOffset>0x0</BitOffset>
  776. <BitWidth>0x10</BitWidth>
  777. <Access>RW</Access>
  778. <Values ByBit="true">
  779. <Val value="0x0">Write protection not active</Val>
  780. <Val value="0x1">Write protection active</Val>
  781. </Values>
  782. </Bit>
  783. <Bit config="1,3">
  784. <Name>WRPOT16</Name>
  785. <Description/>
  786. <BitOffset>0x0</BitOffset>
  787. <BitWidth>0x10</BitWidth>
  788. <Access>RW</Access>
  789. <Values ByBit="true">
  790. <Val value="0x0">read/Write protection active</Val>
  791. <Val value="0x1">read/Write protection not active</Val>
  792. </Values>
  793. </Bit>
  794. </AssignedBits>
  795. </Field>
  796. <Field>
  797. <Parameters address="0x1FF80010" name="FLASH_WRPROT2" size="0x4"/>
  798. <AssignedBits>
  799. <Bit config="0,2">
  800. <Name>WRPOT32</Name>
  801. <Description/>
  802. <BitOffset>0x0</BitOffset>
  803. <BitWidth>0x10</BitWidth>
  804. <Access>RW</Access>
  805. <Values ByBit="true">
  806. <Val value="0x0">Write protection not active</Val>
  807. <Val value="0x1">Write protection active</Val>
  808. </Values>
  809. </Bit>
  810. <Bit config="1,3">
  811. <Name>WRPOT32</Name>
  812. <Description/>
  813. <BitOffset>0x0</BitOffset>
  814. <BitWidth>0x10</BitWidth>
  815. <Access>RW</Access>
  816. <Values ByBit="true">
  817. <Val value="0x0">read/Write protection active</Val>
  818. <Val value="0x1">read/Write protection not active</Val>
  819. </Values>
  820. </Bit>
  821. </AssignedBits>
  822. </Field>
  823. </Category>
  824. </Bank>
  825. </Peripheral>
  826. </Peripherals>
  827. </Device>
  828. </Root>