STM32_Prog_DB_0x451.xml 25 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x451</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32F76x/STM32F77x</Name>
  9. <Series>STM32F7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <!-- 2MB Single Bank-->
  15. <Configuration number="0x0">
  16. <DualBank>
  17. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x20000000"/>
  18. </DualBank>
  19. <FlashSize>
  20. <ReadRegister address="0x1FF0F442" mask="0x0000FFFF" value="0x0800"/>
  21. </FlashSize>
  22. </Configuration>
  23. <!-- 2MB Dual Bank-->
  24. <Configuration number="0x1">
  25. <DualBank>
  26. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x0"/>
  27. </DualBank>
  28. <FlashSize>
  29. <ReadRegister address="0x1FF0F442" mask="0x0000FFFF" value="0x0800"/>
  30. </FlashSize>
  31. </Configuration>
  32. <!-- 1MB Single Bank-->
  33. <Configuration number="0x2">
  34. <DualBank>
  35. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x20000000"/>
  36. </DualBank>
  37. <FlashSize>
  38. <ReadRegister address="0x1FF0F442" mask="0x0000FFFF" value="0x0400"/>
  39. </FlashSize>
  40. </Configuration>
  41. <!-- 1MB Dual Bank-->
  42. <Configuration number="0x3">
  43. <DualBank>
  44. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x0"/>
  45. </DualBank>
  46. <FlashSize>
  47. <ReadRegister address="0x1FF0F442" mask="0x0000FFFF" value="0x0400"/>
  48. </FlashSize>
  49. </Configuration>
  50. <!-- Dummy Config Dual bank-->
  51. <Configuration number="0x4">
  52. <DualBank>
  53. <ReadRegister address="0x40023C14" mask="0x20000000" value="0x00000000"/>
  54. </DualBank>
  55. </Configuration>
  56. <!-- Dummy Config-->
  57. <Configuration number="0x5">
  58. <DualBank>
  59. <ReadRegister address="0x40023C14" mask="0x00000000" value="0x00000000"/>
  60. </DualBank>
  61. </Configuration>
  62. </Interface>
  63. <!-- Bootloader Interface -->
  64. <Interface name="Bootloader">
  65. <Configuration number="0x0"> <!-- 2MB Single Bank-->
  66. <DualBank reference="0x1">
  67. <ReadRegister address="0x1FFF0008" mask="0x2000" value="0x2000"/>
  68. </DualBank>
  69. </Configuration>
  70. <Configuration number="0x1"> <!-- 2MB Dual Bank-->
  71. <DualBank reference="0x0">
  72. <ReadRegister address="0x1FFF0008" mask="0x2000" value="0x0"/>
  73. </DualBank>
  74. </Configuration>
  75. </Interface>
  76. </Configurations>
  77. <!-- Peripherals -->
  78. <Peripherals>
  79. <!-- Embedded SRAM -->
  80. <Peripheral>
  81. <Name>Embedded SRAM</Name>
  82. <Type>Storage</Type>
  83. <Description/>
  84. <ErasedValue>0x00</ErasedValue>
  85. <Access>RWE</Access>
  86. <!-- 512 KB -->
  87. <Configuration>
  88. <Parameters address="0x20000000" name="SRAM" size="0x80000"/>
  89. <Description/>
  90. <Organization>Single</Organization>
  91. <Bank name="Bank 1">
  92. <Field>
  93. <Parameters address="0x20000000" name="SRAM1" occurence="0x1" size="0x80000"/>
  94. </Field>
  95. </Bank>
  96. </Configuration>
  97. </Peripheral>
  98. <!-- Embedded Flash -->
  99. <Peripheral>
  100. <Name>Embedded Flash</Name>
  101. <Type>Storage</Type>
  102. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  103. <ErasedValue>0xFF</ErasedValue>
  104. <Access>RWE</Access>
  105. <FlashSize address="0x1FF0F442" default="0x200000"/>
  106. <!-- 2MB Single Bank -->
  107. <Configuration config="0,5">
  108. <Parameters address="0x08000000" name=" 2 Mbytes single bank Embedded Flash" size="0x200000"/>
  109. <Description/>
  110. <Organization>Single</Organization>
  111. <Allignement>0x20</Allignement>
  112. <Bank name="Bank 1">
  113. <Field>
  114. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x8000"/>
  115. </Field>
  116. <Field>
  117. <Parameters address="0x08020000" name="sector4" occurence="0x1" size="0x20000"/>
  118. </Field>
  119. <Field>
  120. <Parameters address="0x08040000" name="sector5" occurence="0x7" size="0x40000"/>
  121. </Field>
  122. </Bank>
  123. </Configuration>
  124. <!-- 2MB Dual Bank -->
  125. <Configuration config="1,4">
  126. <Parameters address="0x08000000" name=" 2 Mbytes dual bank Embedded Flash" size="0x200000"/>
  127. <Description/>
  128. <Organization>Dual</Organization>
  129. <Allignement>0x10</Allignement>
  130. <Bank name="Bank 1">
  131. <Field>
  132. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  133. </Field>
  134. <Field>
  135. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  136. </Field>
  137. <Field>
  138. <Parameters address="0x08020000" name="sector5" occurence="0x7" size="0x20000"/>
  139. </Field>
  140. </Bank>
  141. <Bank name="Bank 2">
  142. <Field>
  143. <Parameters address="0x08100000" name="sector12" occurence="0x4" size="0x4000"/>
  144. </Field>
  145. <Field>
  146. <Parameters address="0x08110000" name="sector16" occurence="0x1" size="0x10000"/>
  147. </Field>
  148. <Field>
  149. <Parameters address="0x08120000" name="sector17" occurence="0x7" size="0x20000"/>
  150. </Field>
  151. </Bank>
  152. </Configuration>
  153. <!-- 1MB Single Bank -->
  154. <Configuration config="2">
  155. <Parameters address="0x08000000" name=" 1 Mbyte single bank Embedded Flash" size="0x100000"/>
  156. <Description/>
  157. <Organization>Single</Organization>
  158. <Allignement>0x20</Allignement>
  159. <Bank name="Bank 1">
  160. <Field>
  161. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x8000"/>
  162. </Field>
  163. <Field>
  164. <Parameters address="0x08020000" name="sector4" occurence="0x1" size="0x20000"/>
  165. </Field>
  166. <Field>
  167. <Parameters address="0x08040000" name="sector5" occurence="0x3" size="0x40000"/>
  168. </Field>
  169. </Bank>
  170. </Configuration>
  171. <!-- 1MB Dual Bank -->
  172. <Configuration config="3">
  173. <Parameters address="0x08000000" name=" 1 Mbyte dual bank Embedded Flash" size="0x100000"/>
  174. <Description/>
  175. <Organization>Dual</Organization>
  176. <Allignement>0x10</Allignement>
  177. <Bank name="Bank 1">
  178. <Field>
  179. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  180. </Field>
  181. <Field>
  182. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  183. </Field>
  184. <Field>
  185. <Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
  186. </Field>
  187. </Bank>
  188. <Bank name="Bank 2">
  189. <Field>
  190. <Parameters address="0x08080000 " name="sector12" occurence="0x4" size="0x4000"/>
  191. </Field>
  192. <Field>
  193. <Parameters address="0x08090000" name="sector16" occurence="0x1" size="0x10000"/>
  194. </Field>
  195. <Field>
  196. <Parameters address="0x080A0000" name="sector17" occurence="0x3" size="0x20000"/>
  197. </Field>
  198. </Bank>
  199. </Configuration>
  200. </Peripheral>
  201. <!-- ITCM FLASH -->
  202. <Peripheral>
  203. <Name>ITCM Flash</Name>
  204. <Type>Storage</Type>
  205. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  206. <ErasedValue>0xFF</ErasedValue>
  207. <Access>RWE</Access>
  208. <!-- 2MB Single Bank -->
  209. <Configuration config="0,5">
  210. <Parameters address="0x00200000" name=" 2 Mbytes single bank Embedded Flash" size="0x200000"/>
  211. <Description/>
  212. <Organization>Single</Organization>
  213. <Allignement>0x20</Allignement>
  214. <Bank name="Bank 1">
  215. <Field>
  216. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x8000"/>
  217. </Field>
  218. <Field>
  219. <Parameters address="0x00220000" name="sector4" occurence="0x1" size="0x20000"/>
  220. </Field>
  221. <Field>
  222. <Parameters address="0x00240000" name="sector5" occurence="0x7" size="0x40000"/>
  223. </Field>
  224. </Bank>
  225. </Configuration>
  226. <!-- 2MB Dual Bank -->
  227. <Configuration config="1,4">
  228. <Parameters address="0x00200000" name=" 2 Mbytes dual bank Embedded Flash" size="0x200000"/>
  229. <Description/>
  230. <Organization>Dual</Organization>
  231. <Allignement>0x10</Allignement>
  232. <Bank name="Bank 1">
  233. <Field>
  234. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
  235. </Field>
  236. <Field>
  237. <Parameters address="0x00210000" name="sector4" occurence="0x1" size="0x10000"/>
  238. </Field>
  239. <Field>
  240. <Parameters address="0x00220000" name="sector5" occurence="0x7" size="0x20000"/>
  241. </Field>
  242. </Bank>
  243. <Bank name="Bank 2">
  244. <Field>
  245. <Parameters address="0x00300000" name="sector12" occurence="0x4" size="0x4000"/>
  246. </Field>
  247. <Field>
  248. <Parameters address="0x00310000" name="sector16" occurence="0x1" size="0x10000"/>
  249. </Field>
  250. <Field>
  251. <Parameters address="0x00320000" name="sector17" occurence="0x7" size="0x20000"/>
  252. </Field>
  253. </Bank>
  254. </Configuration>
  255. </Peripheral>
  256. <!-- OTP -->
  257. <Peripheral>
  258. <Name>OTP</Name>
  259. <Type>Storage</Type>
  260. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  261. <ErasedValue>0xFF</ErasedValue>
  262. <Access>RW</Access>
  263. <!-- 1 KBytes single bank -->
  264. <Configuration>
  265. <Parameters address="0x1FF0F000" name=" 1 KBytes Data OTP" size="0x480"/>
  266. <Description/>
  267. <Organization>Single</Organization>
  268. <Allignement>0x4</Allignement>
  269. <Bank name="OTP">
  270. <Field>
  271. <Parameters address="0x1FF0F000" name="OTP" occurence="0x1" size="0x480"/>
  272. </Field>
  273. </Bank>
  274. </Configuration>
  275. </Peripheral>
  276. <!-- Mirror Option Bytes -->
  277. <Peripheral>
  278. <Name>MirrorOptionBytes</Name>
  279. <Type>Storage</Type>
  280. <Description>Mirror Option Bytes contains the extra area.</Description>
  281. <ErasedValue>0xFF</ErasedValue>
  282. <Access>RW</Access>
  283. <!-- 44 Bytes single bank -->
  284. <Configuration>
  285. <Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
  286. <Description/>
  287. <Organization>Single</Organization>
  288. <Allignement>0x4</Allignement>
  289. <Bank name="MirrorOptionBytes">
  290. <Field>
  291. <Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurence="0x1" size="0x2C"/>
  292. </Field>
  293. </Bank>
  294. </Configuration>
  295. </Peripheral>
  296. <!-- Option Bytes -->
  297. <Peripheral>
  298. <Name>Option Bytes</Name>
  299. <Type>Configuration</Type>
  300. <Description/>
  301. <Access>RW</Access>
  302. <Bank interface="JTAG_SWD">
  303. <Parameters address="0x40023C14" name="Bank 1" size="0x8"/>
  304. <Category>
  305. <Name>Read Out Protection</Name>
  306. <Field>
  307. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  308. <AssignedBits>
  309. <Bit>
  310. <Name>RDP</Name>
  311. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  312. <BitOffset>0x8</BitOffset>
  313. <BitWidth>0x8</BitWidth>
  314. <Access>RW</Access>
  315. <Values>
  316. <Val value="0xAA">Level 0, no protection</Val>
  317. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  318. <Val value="0xCC">Level 2, chip protection</Val>
  319. </Values>
  320. </Bit>
  321. </AssignedBits>
  322. </Field>
  323. </Category>
  324. <Category>
  325. <Name>BOR Level</Name>
  326. <Field>
  327. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  328. <AssignedBits>
  329. <Bit>
  330. <Name>BOR_LEV</Name>
  331. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  332. <BitOffset>0x2</BitOffset>
  333. <BitWidth>0x2</BitWidth>
  334. <Access>RW</Access>
  335. <Values>
  336. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  337. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  338. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  339. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  340. </Values>
  341. </Bit>
  342. </AssignedBits>
  343. </Field>
  344. </Category>
  345. <Category>
  346. <Name>User Configuration</Name>
  347. <Field>
  348. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  349. <AssignedBits>
  350. <Bit>
  351. <Name>IWDG_STOP</Name>
  352. <Description/>
  353. <BitOffset>0x1F</BitOffset>
  354. <BitWidth>0x1</BitWidth>
  355. <Access>RW</Access>
  356. <Values>
  357. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  358. <Val value="0x1">IWDG counter active in stop mode</Val>
  359. </Values>
  360. </Bit>
  361. <Bit>
  362. <Name>IWDG_STDBY</Name>
  363. <Description/>
  364. <BitOffset>0x1E</BitOffset>
  365. <BitWidth>0x1</BitWidth>
  366. <Access>RW</Access>
  367. <Values>
  368. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  369. <Val value="0x1">IWDG counter active in standby mode</Val>
  370. </Values>
  371. </Bit>
  372. <Bit reference="DualBank">
  373. <Name>nDBANK</Name>
  374. <Description/>
  375. <BitOffset>0x1D</BitOffset>
  376. <BitWidth>0x1</BitWidth>
  377. <Access>RW</Access>
  378. <Values>
  379. <Val value="0x0">Flash in dual bank with 128 bits read access</Val>
  380. <Val value="0x1">Flash in single bank with 256 bits read access</Val>
  381. </Values>
  382. </Bit>
  383. <Bit config="1,4">
  384. <Name>nDBOOT</Name>
  385. <Description/>
  386. <BitOffset>0x1C</BitOffset>
  387. <BitWidth>0x1</BitWidth>
  388. <Access>RW</Access>
  389. <Values>
  390. <Val value="0x0">Dual Boot enabled</Val>
  391. <Val value="0x1">Dual Boot disabled</Val>
  392. </Values>
  393. </Bit>
  394. <Bit>
  395. <Name>WWDG_SW</Name>
  396. <Description/>
  397. <BitOffset>0x4</BitOffset>
  398. <BitWidth>0x1</BitWidth>
  399. <Access>RW</Access>
  400. <Values>
  401. <Val value="0x0">Hardware window watchdog</Val>
  402. <Val value="0x1">Software window watchdog</Val>
  403. </Values>
  404. </Bit>
  405. <Bit>
  406. <Name>IWDG_SW</Name>
  407. <Description/>
  408. <BitOffset>0x5</BitOffset>
  409. <BitWidth>0x1</BitWidth>
  410. <Access>RW</Access>
  411. <Values>
  412. <Val value="0x0">Hardware independant watchdog</Val>
  413. <Val value="0x1">Software independant watchdog</Val>
  414. </Values>
  415. </Bit>
  416. <Bit>
  417. <Name>nRST_STOP</Name>
  418. <Description/>
  419. <BitOffset>0x6</BitOffset>
  420. <BitWidth>0x1</BitWidth>
  421. <Access>RW</Access>
  422. <Values>
  423. <Val value="0x0">Reset generated when entering Stop mode</Val>
  424. <Val value="0x1">No reset generated</Val>
  425. </Values>
  426. </Bit>
  427. <Bit>
  428. <Name>nRST_STDBY</Name>
  429. <Description/>
  430. <BitOffset>0x7</BitOffset>
  431. <BitWidth>0x1</BitWidth>
  432. <Access>RW</Access>
  433. <Values>
  434. <Val value="0x0">Reset generated when entering Standby mode</Val>
  435. <Val value="0x1">No reset generated</Val>
  436. </Values>
  437. </Bit>
  438. </AssignedBits>
  439. </Field>
  440. </Category>
  441. <Category>
  442. <Name>Boot address Option Bytes</Name>
  443. <Field>
  444. <Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
  445. <AssignedBits>
  446. <Bit>
  447. <Name>BOOT_ADD0</Name>
  448. <Description>Define the boot address when BOOT0=0</Description>
  449. <BitOffset>0x0</BitOffset>
  450. <BitWidth>0x10</BitWidth>
  451. <Access>RW</Access>
  452. <Equation multiplier="0x4000" offset="0x0"/>
  453. </Bit>
  454. <Bit>
  455. <Name>BOOT_ADD1</Name>
  456. <Description>Define the boot address when BOOT0=1</Description>
  457. <BitOffset>0x10</BitOffset>
  458. <BitWidth>0x10</BitWidth>
  459. <Access>RW</Access>
  460. <Equation multiplier="0x4000" offset="0x0"/>
  461. </Bit>
  462. </AssignedBits>
  463. </Field>
  464. </Category>
  465. <Category>
  466. <Name>Write Protection</Name>
  467. <Field>
  468. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  469. <AssignedBits>
  470. <Bit config="0,2,5">
  471. <Name>nWRP0</Name>
  472. <Description/>
  473. <BitOffset>0x10</BitOffset>
  474. <BitWidth>0xC</BitWidth>
  475. <Access>RW</Access>
  476. <Values ByBit="true">
  477. <Val value="0x0">Write protection active on this sector</Val>
  478. <Val value="0x1">Write protection not active on this sector</Val>
  479. </Values>
  480. </Bit>
  481. <Bit config="1,3,4">
  482. <Name>nWRP0</Name>
  483. <Description/>
  484. <BitOffset>0x10</BitOffset>
  485. <BitWidth>0x6</BitWidth>
  486. <Access>RW</Access>
  487. <Values ByBit="true">
  488. <Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
  489. <Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
  490. </Values>
  491. </Bit>
  492. <Bit config="1,3,4">
  493. <Name>nWRP6</Name>
  494. <Description/>
  495. <BitOffset>0x16</BitOffset>
  496. <BitWidth>0x6</BitWidth>
  497. <Access>RW</Access>
  498. <Values ByBit="true">
  499. <Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
  500. <Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
  501. </Values>
  502. </Bit>
  503. </AssignedBits>
  504. </Field>
  505. </Category>
  506. </Bank>
  507. <Bank interface="Bootloader">
  508. <Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
  509. <Category>
  510. <Name>Read Out Protection</Name>
  511. <Field>
  512. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  513. <AssignedBits>
  514. <Bit>
  515. <Name>RDP</Name>
  516. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  517. <BitOffset>0x8</BitOffset>
  518. <BitWidth>0x8</BitWidth>
  519. <Access>RW</Access>
  520. <Values>
  521. <Val value="0xAA">Level 0, no protection</Val>
  522. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  523. <Val value="0xCC">Level 2, chip protection</Val>
  524. </Values>
  525. </Bit>
  526. </AssignedBits>
  527. </Field>
  528. </Category>
  529. <Category>
  530. <Name>BOR Level</Name>
  531. <Field>
  532. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  533. <AssignedBits>
  534. <Bit>
  535. <Name>BOR_LEV</Name>
  536. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  537. <BitOffset>0x2</BitOffset>
  538. <BitWidth>0x2</BitWidth>
  539. <Access>RW</Access>
  540. <Values>
  541. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  542. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  543. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  544. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  545. </Values>
  546. </Bit>
  547. </AssignedBits>
  548. </Field>
  549. </Category>
  550. <Category>
  551. <Name>User Configuration</Name>
  552. <Field>
  553. <Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
  554. <AssignedBits>
  555. <Bit>
  556. <Name>IWDG_STOP</Name>
  557. <Description/>
  558. <BitOffset>0xF</BitOffset>
  559. <BitWidth>0x1</BitWidth>
  560. <Access>RW</Access>
  561. <Values>
  562. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  563. <Val value="0x1">IWDG counter active in stop mode</Val>
  564. </Values>
  565. </Bit>
  566. <Bit>
  567. <Name>IWDG_STDBY</Name>
  568. <Description/>
  569. <BitOffset>0xE</BitOffset>
  570. <BitWidth>0x1</BitWidth>
  571. <Access>RW</Access>
  572. <Values>
  573. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  574. <Val value="0x1">IWDG counter active in standby mode</Val>
  575. </Values>
  576. </Bit>
  577. <Bit reference="DualBank">
  578. <Name>nDBANK</Name>
  579. <Description/>
  580. <BitOffset>0xD</BitOffset>
  581. <BitWidth>0x1</BitWidth>
  582. <Access>RW</Access>
  583. <Values>
  584. <Val value="0x0">Flash in dual bank with 128 bits read access</Val>
  585. <Val value="0x1">Flash in single bank with 256 bits read access</Val>
  586. </Values>
  587. </Bit>
  588. <Bit config="1">
  589. <Name>nDBOOT</Name>
  590. <Description/>
  591. <BitOffset>0xC</BitOffset>
  592. <BitWidth>0x1</BitWidth>
  593. <Access>RW</Access>
  594. <Values>
  595. <Val value="0x0">Dual Boot enabled</Val>
  596. <Val value="0x1">Dual Boot disabled</Val>
  597. </Values>
  598. </Bit>
  599. </AssignedBits>
  600. </Field>
  601. <Field>
  602. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  603. <AssignedBits>
  604. <Bit>
  605. <Name>WWDG_SW</Name>
  606. <Description/>
  607. <BitOffset>0x4</BitOffset>
  608. <BitWidth>0x1</BitWidth>
  609. <Access>RW</Access>
  610. <Values>
  611. <Val value="0x0">Hardware window watchdog</Val>
  612. <Val value="0x1">Software window watchdog</Val>
  613. </Values>
  614. </Bit>
  615. <Bit>
  616. <Name>IWDG_SW</Name>
  617. <Description/>
  618. <BitOffset>0x5</BitOffset>
  619. <BitWidth>0x1</BitWidth>
  620. <Access>RW</Access>
  621. <Values>
  622. <Val value="0x0">Hardware independant watchdog</Val>
  623. <Val value="0x1">Software independant watchdog</Val>
  624. </Values>
  625. </Bit>
  626. <Bit>
  627. <Name>nRST_STOP</Name>
  628. <Description/>
  629. <BitOffset>0x6</BitOffset>
  630. <BitWidth>0x1</BitWidth>
  631. <Access>RW</Access>
  632. <Values>
  633. <Val value="0x0">Reset generated when entering Stop mode</Val>
  634. <Val value="0x1">No reset generated</Val>
  635. </Values>
  636. </Bit>
  637. <Bit>
  638. <Name>nRST_STDBY</Name>
  639. <Description/>
  640. <BitOffset>0x7</BitOffset>
  641. <BitWidth>0x1</BitWidth>
  642. <Access>RW</Access>
  643. <Values>
  644. <Val value="0x0">Reset generated when entering Standby mode</Val>
  645. <Val value="0x1">No reset generated</Val>
  646. </Values>
  647. </Bit>
  648. </AssignedBits>
  649. </Field>
  650. </Category>
  651. <Category>
  652. <Name>Boot address Option Bytes</Name>
  653. <Field>
  654. <Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
  655. <AssignedBits>
  656. <Bit>
  657. <Name>BOOT_ADD0</Name>
  658. <Description>Define the boot address when BOOT0=0</Description>
  659. <BitOffset>0x0</BitOffset>
  660. <BitWidth>0x10</BitWidth>
  661. <Access>RW</Access>
  662. <Equation multiplier="0x4000" offset="0x0"/>
  663. </Bit>
  664. </AssignedBits>
  665. </Field>
  666. <Field>
  667. <Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
  668. <AssignedBits>
  669. <Bit>
  670. <Name>BOOT_ADD1</Name>
  671. <Description>Define the boot address when BOOT0=1</Description>
  672. <BitOffset>0x0</BitOffset>
  673. <BitWidth>0x10</BitWidth>
  674. <Access>RW</Access>
  675. <Equation multiplier="0x4000" offset="0x0"/>
  676. </Bit>
  677. </AssignedBits>
  678. </Field>
  679. </Category>
  680. <Category>
  681. <Name>Write Protection</Name>
  682. <Field>
  683. <Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
  684. <AssignedBits>
  685. <Bit config="0">
  686. <Name>nWRP0</Name>
  687. <Description/>
  688. <BitOffset>0x0</BitOffset>
  689. <BitWidth>0xC</BitWidth>
  690. <Access>RW</Access>
  691. <Values ByBit="true">
  692. <Val value="0x0">Write protection active on this sector</Val>
  693. <Val value="0x1">Write protection not active on this sector</Val>
  694. </Values>
  695. </Bit>
  696. <Bit config="1">
  697. <Name>nWRP0</Name>
  698. <Description/>
  699. <BitOffset>0x0</BitOffset>
  700. <BitWidth>0x6</BitWidth>
  701. <Access>RW</Access>
  702. <Values ByBit="true">
  703. <Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
  704. <Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
  705. </Values>
  706. </Bit>
  707. <Bit config="1">
  708. <Name>nWRP6</Name>
  709. <Description/>
  710. <BitOffset>0x6</BitOffset>
  711. <BitWidth>0x6</BitWidth>
  712. <Access>RW</Access>
  713. <Values ByBit="true">
  714. <Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
  715. <Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
  716. </Values>
  717. </Bit>
  718. </AssignedBits>
  719. </Field>
  720. </Category>
  721. </Bank>
  722. </Peripheral>
  723. </Peripherals>
  724. </Device>
  725. </Root>