STM32_Prog_DB_0x452.xml 20 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x452</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M7</CPU>
  8. <Name>STM32F72x/STM32F73x</Name>
  9. <Series>STM32F7</Series>
  10. <Description>ARM 32-bit Cortex-M7 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- ROM Die -->
  15. <RomLess>
  16. <ReadRegister address="0x1FF07A22" mask="0x40" value="0x00"/>
  17. </RomLess>
  18. </Configuration>
  19. <Configuration number="0x1"> <!-- RomLess Die -->
  20. <RomLess>
  21. <ReadRegister address="0x1FF07A22" mask="0x40" value="0x40"/>
  22. </RomLess>
  23. </Configuration>
  24. </Interface>
  25. <!-- Bootloader Interface -->
  26. <Interface name="Bootloader">
  27. <Configuration number="0x0"> <!-- ROM Die -->
  28. <RomLess>
  29. <ReadRegister address="0x0x08000000" mask="0x00" value="0x00"/>
  30. </RomLess>
  31. </Configuration>
  32. </Interface>
  33. </Configurations>
  34. <!-- Peripherals -->
  35. <Peripherals>
  36. <!-- Embedded SRAM -->
  37. <Peripheral>
  38. <Name>Embedded SRAM</Name>
  39. <Type>Storage</Type>
  40. <Description/>
  41. <ErasedValue>0x00</ErasedValue>
  42. <Access>RWE</Access>
  43. <!-- 512 KB -->
  44. <Configuration>
  45. <Parameters address="0x20000000" name="SRAM" size="0x40000"/>
  46. <Description/>
  47. <Organization>Single</Organization>
  48. <Bank name="Bank 1">
  49. <Field>
  50. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x40000"/>
  51. </Field>
  52. </Bank>
  53. </Configuration>
  54. </Peripheral>
  55. <!-- Embedded Flash -->
  56. <Peripheral>
  57. <Name>Embedded Flash</Name>
  58. <Type>Storage</Type>
  59. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  60. <ErasedValue>0xFF</ErasedValue>
  61. <Access>RWE</Access>
  62. <FlashSize address="0x1FF07A22" default="0x80000"/>
  63. <!-- 512KB single Bank -->
  64. <Configuration config="0">
  65. <Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
  66. <Description/>
  67. <Organization>Single</Organization>
  68. <Allignement>0x10</Allignement>
  69. <Bank name="Bank 1">
  70. <Field>
  71. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  72. </Field>
  73. <Field>
  74. <Parameters address="0x08010000" name="sector4" occurence="0x1" size="0x10000"/>
  75. </Field>
  76. <Field>
  77. <Parameters address="0x08020000" name="sector5" occurence="0x3" size="0x20000"/>
  78. </Field>
  79. </Bank>
  80. </Configuration>
  81. <!-- 64KB RomLess -->
  82. <Configuration config="1">
  83. <Parameters address="0x08000000" name=" 64 Kbytes Embedded Flash" size="0x10000"/>
  84. <Description/>
  85. <Organization>Single</Organization>
  86. <Allignement>0x10</Allignement>
  87. <Bank name="Bank 1">
  88. <Field>
  89. <Parameters address="0x08000000" name="sector0" occurence="0x4" size="0x4000"/>
  90. </Field>
  91. </Bank>
  92. </Configuration>
  93. </Peripheral>
  94. <!-- ITCM Bytes -->
  95. <Peripheral>
  96. <Name>ITCM Flash</Name>
  97. <Type>Storage</Type>
  98. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  99. <ErasedValue>0xFF</ErasedValue>
  100. <Access>RWE</Access>
  101. <!-- 512KB single Bank -->
  102. <Configuration config="0">
  103. <Parameters address="0x00200000" name=" 512 Kbytes ITCM Flash" size="0x80000"/>
  104. <Description/>
  105. <Organization>Single</Organization>
  106. <Allignement>0x10</Allignement>
  107. <Bank name="Bank 1">
  108. <Field>
  109. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
  110. </Field>
  111. <Field>
  112. <Parameters address="0x00210000" name="sector4" occurence="0x1" size="0x10000"/>
  113. </Field>
  114. <Field>
  115. <Parameters address="0x00220000" name="sector5" occurence="0x3" size="0x20000"/>
  116. </Field>
  117. </Bank>
  118. </Configuration>
  119. <!-- 64KB RomLess -->
  120. <Configuration config="1">
  121. <Parameters address="0x00200000" name=" 64 Kbytes ITCM Flash" size="0x10000"/>
  122. <Description/>
  123. <Organization>Single</Organization>
  124. <Allignement>0x10</Allignement>
  125. <Bank name="Bank 1">
  126. <Field>
  127. <Parameters address="0x00200000" name="sector0" occurence="0x4" size="0x4000"/>
  128. </Field>
  129. </Bank>
  130. </Configuration>
  131. </Peripheral>
  132. <!-- OTP -->
  133. <Peripheral>
  134. <Name>OTP</Name>
  135. <Type>Storage</Type>
  136. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  137. <ErasedValue>0xFF</ErasedValue>
  138. <Access>RW</Access>
  139. <!-- 512 Bytes single bank -->
  140. <Configuration>
  141. <Parameters address="0x1FF07800" name=" 512 Bytes Data OTP" size="0x200"/>
  142. <Description/>
  143. <Organization>Single</Organization>
  144. <Allignement>0x4</Allignement>
  145. <Bank name="OTP">
  146. <Field>
  147. <Parameters address="0x1FF07800" name="OTP" occurence="0x1" size="0x200"/>
  148. </Field>
  149. </Bank>
  150. </Configuration>
  151. </Peripheral>
  152. <!-- Mirror Option Bytes -->
  153. <Peripheral>
  154. <Name>MirrorOptionBytes</Name>
  155. <Type>Storage</Type>
  156. <Description>Mirror Option Bytes contains the extra area.</Description>
  157. <ErasedValue>0xFF</ErasedValue>
  158. <Access>RW</Access>
  159. <!-- 44 Bytes single bank -->
  160. <Configuration>
  161. <Parameters address="0x1FFF0000" name=" 44 Bytes Data MirrorOptionBytes" size="0x2C"/>
  162. <Description/>
  163. <Organization>Single</Organization>
  164. <Allignement>0x4</Allignement>
  165. <Bank name="MirrorOptionBytes">
  166. <Field>
  167. <Parameters address="0x1FFF0000" name="MirrorOptionBytes" occurence="0x1" size="0x2C"/>
  168. </Field>
  169. </Bank>
  170. </Configuration>
  171. </Peripheral>
  172. <!-- Option Bytes -->
  173. <Peripheral>
  174. <Name>Option Bytes</Name>
  175. <Type>Configuration</Type>
  176. <Description/>
  177. <Access>RW</Access>
  178. <Bank interface="JTAG_SWD">
  179. <Parameters address="0x40023C14" name="Bank 1" size="0xC"/>
  180. <Category>
  181. <Name>Read Out Protection</Name>
  182. <Field>
  183. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  184. <AssignedBits>
  185. <Bit>
  186. <Name>RDP</Name>
  187. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  188. <BitOffset>0x8</BitOffset>
  189. <BitWidth>0x8</BitWidth>
  190. <Access>RW</Access>
  191. <Values>
  192. <Val value="0xAA">Level 0, no protection</Val>
  193. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  194. <Val value="0xCC">Level 2, chip protection</Val>
  195. </Values>
  196. </Bit>
  197. </AssignedBits>
  198. </Field>
  199. </Category>
  200. <Category>
  201. <Name>BOR Level</Name>
  202. <Field>
  203. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  204. <AssignedBits>
  205. <Bit>
  206. <Name>BOR_LEV</Name>
  207. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  208. <BitOffset>0x2</BitOffset>
  209. <BitWidth>0x2</BitWidth>
  210. <Access>RW</Access>
  211. <Values>
  212. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  213. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  214. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  215. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  216. </Values>
  217. </Bit>
  218. </AssignedBits>
  219. </Field>
  220. </Category>
  221. <Category>
  222. <Name>User Configuration</Name>
  223. <Field>
  224. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  225. <AssignedBits>
  226. <Bit>
  227. <Name>IWDG_STOP</Name>
  228. <Description/>
  229. <BitOffset>0x1F</BitOffset>
  230. <BitWidth>0x1</BitWidth>
  231. <Access>RW</Access>
  232. <Values>
  233. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  234. <Val value="0x1">IWDG counter active in stop mode</Val>
  235. </Values>
  236. </Bit>
  237. <Bit>
  238. <Name>IWDG_STDBY</Name>
  239. <Description/>
  240. <BitOffset>0x1E</BitOffset>
  241. <BitWidth>0x1</BitWidth>
  242. <Access>RW</Access>
  243. <Values>
  244. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  245. <Val value="0x1">IWDG counter active in standby mode</Val>
  246. </Values>
  247. </Bit>
  248. <Bit>
  249. <Name>WWDG_SW</Name>
  250. <Description/>
  251. <BitOffset>0x4</BitOffset>
  252. <BitWidth>0x1</BitWidth>
  253. <Access>RW</Access>
  254. <Values>
  255. <Val value="0x0">Hardware window watchdog</Val>
  256. <Val value="0x1">Software window watchdog</Val>
  257. </Values>
  258. </Bit>
  259. <Bit>
  260. <Name>IWDG_SW</Name>
  261. <Description/>
  262. <BitOffset>0x5</BitOffset>
  263. <BitWidth>0x1</BitWidth>
  264. <Access>RW</Access>
  265. <Values>
  266. <Val value="0x0">Hardware independant watchdog</Val>
  267. <Val value="0x1">Software independant watchdog</Val>
  268. </Values>
  269. </Bit>
  270. <Bit>
  271. <Name>nRST_STOP</Name>
  272. <Description/>
  273. <BitOffset>0x6</BitOffset>
  274. <BitWidth>0x1</BitWidth>
  275. <Access>RW</Access>
  276. <Values>
  277. <Val value="0x0">Reset generated when entering Stop mode</Val>
  278. <Val value="0x1">No reset generated</Val>
  279. </Values>
  280. </Bit>
  281. <Bit>
  282. <Name>nRST_STDBY</Name>
  283. <Description/>
  284. <BitOffset>0x7</BitOffset>
  285. <BitWidth>0x1</BitWidth>
  286. <Access>RW</Access>
  287. <Values>
  288. <Val value="0x0">Reset generated when entering Standby mode</Val>
  289. <Val value="0x1">No reset generated</Val>
  290. </Values>
  291. </Bit>
  292. </AssignedBits>
  293. </Field>
  294. <Field>
  295. <Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
  296. <AssignedBits>
  297. <Bit>
  298. <Name>PCROP_RDP</Name>
  299. <Description/>
  300. <BitOffset>0x1F</BitOffset>
  301. <BitWidth>0x1</BitWidth>
  302. <Access>RW</Access>
  303. <Values>
  304. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  305. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  306. </Values>
  307. </Bit>
  308. </AssignedBits>
  309. </Field>
  310. </Category>
  311. <Category>
  312. <Name>Boot address Option Bytes</Name>
  313. <Field>
  314. <Parameters address="0x40023C18" name="FLASH_OPTCR1" size="0x4"/>
  315. <AssignedBits>
  316. <Bit>
  317. <Name>BOOT_ADD0</Name>
  318. <Description>Define the boot address when BOOT0=0</Description>
  319. <BitOffset>0x0</BitOffset>
  320. <BitWidth>0x10</BitWidth>
  321. <Access>RW</Access>
  322. <Equation multiplier="0x4000" offset="0x0"/>
  323. </Bit>
  324. <Bit>
  325. <Name>BOOT_ADD1</Name>
  326. <Description>Define the boot address when BOOT0=1</Description>
  327. <BitOffset>0x10</BitOffset>
  328. <BitWidth>0x10</BitWidth>
  329. <Access>RW</Access>
  330. <Equation multiplier="0x4000" offset="0x0"/>
  331. </Bit>
  332. </AssignedBits>
  333. </Field>
  334. </Category>
  335. <Category>
  336. <Name>Write Protection</Name>
  337. <Field>
  338. <Parameters address="0x40023C14" name="FLASH_OPTCR" size="0x4"/>
  339. <AssignedBits>
  340. <Bit config="0">
  341. <Name>nWRP0</Name>
  342. <Description/>
  343. <BitOffset>0x10</BitOffset>
  344. <BitWidth>0x8</BitWidth>
  345. <Access>RW</Access>
  346. <Values ByBit="true">
  347. <Val value="0x0">Write protection active on this sector</Val>
  348. <Val value="0x1">Write protection not active on this sector</Val>
  349. </Values>
  350. </Bit>
  351. <Bit config="1">
  352. <Name>nWRP0</Name>
  353. <Description/>
  354. <BitOffset>0x10</BitOffset>
  355. <BitWidth>0x4</BitWidth>
  356. <Access>RW</Access>
  357. <Values ByBit="true">
  358. <Val value="0x0">Write protection active on this sector</Val>
  359. <Val value="0x1">Write protection not active on this sector</Val>
  360. </Values>
  361. </Bit>
  362. </AssignedBits>
  363. </Field>
  364. </Category>
  365. <Category>
  366. <Name>Read/Write Protection</Name>
  367. <Field>
  368. <Parameters address="0x40023C1C" name="FLASH_OPTCR2" size="0x4"/>
  369. <AssignedBits>
  370. <Bit config="0">
  371. <Name>PCROP0</Name>
  372. <Description/>
  373. <BitOffset>0x0</BitOffset>
  374. <BitWidth>0x8</BitWidth>
  375. <Access>RW</Access>
  376. <Values ByBit="true">
  377. <Val value="0x0">PCROP protection not active on this sector</Val>
  378. <Val value="0x1">PCROP protection active on this sector</Val>
  379. </Values>
  380. </Bit>
  381. <Bit config="1">
  382. <Name>PCROP0</Name>
  383. <Description/>
  384. <BitOffset>0x0</BitOffset>
  385. <BitWidth>0x4</BitWidth>
  386. <Access>RW</Access>
  387. <Values ByBit="true">
  388. <Val value="0x0">PCROP protection not active on this sector</Val>
  389. <Val value="0x1">PCROP protection active on this sector</Val>
  390. </Values>
  391. </Bit>
  392. </AssignedBits>
  393. </Field>
  394. </Category>
  395. </Bank>
  396. <Bank interface="Bootloader">
  397. <Parameters address="0x1FFF0000" name="Bank 1" size="0x2C"/>
  398. <Category>
  399. <Name>Read Out Protection</Name>
  400. <Field>
  401. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  402. <AssignedBits>
  403. <Bit>
  404. <Name>RDP</Name>
  405. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  406. <BitOffset>0x8</BitOffset>
  407. <BitWidth>0x8</BitWidth>
  408. <Access>RW</Access>
  409. <Values>
  410. <Val value="0xAA">Level 0, no protection</Val>
  411. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  412. <Val value="0xCC">Level 2, chip protection</Val>
  413. </Values>
  414. </Bit>
  415. </AssignedBits>
  416. </Field>
  417. </Category>
  418. <Category>
  419. <Name>BOR Level</Name>
  420. <Field>
  421. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  422. <AssignedBits>
  423. <Bit>
  424. <Name>BOR_LEV</Name>
  425. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  426. <BitOffset>0x2</BitOffset>
  427. <BitWidth>0x2</BitWidth>
  428. <Access>RW</Access>
  429. <Values>
  430. <Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
  431. <Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
  432. <Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
  433. <Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
  434. </Values>
  435. </Bit>
  436. </AssignedBits>
  437. </Field>
  438. </Category>
  439. <Category>
  440. <Name>User Configuration</Name>
  441. <Field>
  442. <Parameters address="0x1FFF0008" name="FLASH_OPTCR" size="0x4"/>
  443. <AssignedBits>
  444. <Bit>
  445. <Name>IWDG_STOP</Name>
  446. <Description/>
  447. <BitOffset>0xF</BitOffset>
  448. <BitWidth>0x1</BitWidth>
  449. <Access>RW</Access>
  450. <Values>
  451. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  452. <Val value="0x1">IWDG counter active in stop mode</Val>
  453. </Values>
  454. </Bit>
  455. <Bit>
  456. <Name>IWDG_STDBY</Name>
  457. <Description/>
  458. <BitOffset>0xE</BitOffset>
  459. <BitWidth>0x1</BitWidth>
  460. <Access>RW</Access>
  461. <Values>
  462. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  463. <Val value="0x1">IWDG counter active in standby mode</Val>
  464. </Values>
  465. </Bit>
  466. </AssignedBits>
  467. </Field>
  468. <Field>
  469. <Parameters address="0x1FFF0000" name="FLASH_OPTCR" size="0x4"/>
  470. <AssignedBits>
  471. <Bit>
  472. <Name>WWDG_SW</Name>
  473. <Description/>
  474. <BitOffset>0x4</BitOffset>
  475. <BitWidth>0x1</BitWidth>
  476. <Access>RW</Access>
  477. <Values>
  478. <Val value="0x0">Hardware window watchdog</Val>
  479. <Val value="0x1">Software window watchdog</Val>
  480. </Values>
  481. </Bit>
  482. <Bit>
  483. <Name>IWDG_SW</Name>
  484. <Description/>
  485. <BitOffset>0x5</BitOffset>
  486. <BitWidth>0x1</BitWidth>
  487. <Access>RW</Access>
  488. <Values>
  489. <Val value="0x0">Hardware independant watchdog</Val>
  490. <Val value="0x1">Software independant watchdog</Val>
  491. </Values>
  492. </Bit>
  493. <Bit>
  494. <Name>nRST_STOP</Name>
  495. <Description/>
  496. <BitOffset>0x6</BitOffset>
  497. <BitWidth>0x1</BitWidth>
  498. <Access>RW</Access>
  499. <Values>
  500. <Val value="0x0">Reset generated when entering Stop mode</Val>
  501. <Val value="0x1">No reset generated</Val>
  502. </Values>
  503. </Bit>
  504. <Bit>
  505. <Name>nRST_STDBY</Name>
  506. <Description/>
  507. <BitOffset>0x7</BitOffset>
  508. <BitWidth>0x1</BitWidth>
  509. <Access>RW</Access>
  510. <Values>
  511. <Val value="0x0">Reset generated when entering Standby mode</Val>
  512. <Val value="0x1">No reset generated</Val>
  513. </Values>
  514. </Bit>
  515. </AssignedBits>
  516. </Field>
  517. <Field>
  518. <Parameters address="0x1FFF0028" name="FLASH_OPTCR2" size="0x4"/>
  519. <AssignedBits>
  520. <Bit>
  521. <Name>PCROP_RDP</Name>
  522. <Description/>
  523. <BitOffset>0xF</BitOffset>
  524. <BitWidth>0x1</BitWidth>
  525. <Access>RW</Access>
  526. <Values>
  527. <Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
  528. <Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
  529. </Values>
  530. </Bit>
  531. </AssignedBits>
  532. </Field>
  533. </Category>
  534. <Category>
  535. <Name>Boot address Option Bytes</Name>
  536. <Field>
  537. <Parameters address="0x1FFF0010" name="FLASH_OPTCR1" size="0x4"/>
  538. <AssignedBits>
  539. <Bit>
  540. <Name>BOOT_ADD0</Name>
  541. <Description>Define the boot address when BOOT0=0</Description>
  542. <BitOffset>0x0</BitOffset>
  543. <BitWidth>0x10</BitWidth>
  544. <Access>RW</Access>
  545. <Equation multiplier="0x4000" offset="0x0"/>
  546. </Bit>
  547. </AssignedBits>
  548. </Field>
  549. <Field>
  550. <Parameters address="0x1FFF0018" name="FLASH_OPTCR1" size="0x4"/>
  551. <AssignedBits>
  552. <Bit>
  553. <Name>BOOT_ADD1</Name>
  554. <Description>Define the boot address when BOOT0=1</Description>
  555. <BitOffset>0x0</BitOffset>
  556. <BitWidth>0x10</BitWidth>
  557. <Access>RW</Access>
  558. <Equation multiplier="0x4000" offset="0x0"/>
  559. </Bit>
  560. </AssignedBits>
  561. </Field>
  562. </Category>
  563. <Category>
  564. <Name>Write Protection</Name>
  565. <Field>
  566. <Parameters address="0x1FFF0008" name="FLASH_OPTCR1" size="0x4"/>
  567. <AssignedBits>
  568. <Bit>
  569. <Name>nWRP0</Name>
  570. <Description/>
  571. <BitOffset>0x0</BitOffset>
  572. <BitWidth>0x8</BitWidth>
  573. <Access>RW</Access>
  574. <Values ByBit="true">
  575. <Val value="0x0">Write protection active on this sector</Val>
  576. <Val value="0x1">Write protection not active on this sector</Val>
  577. </Values>
  578. </Bit>
  579. </AssignedBits>
  580. </Field>
  581. </Category>
  582. <Category>
  583. <Name>Read/Write Protection</Name>
  584. <Field>
  585. <Parameters address="0x1FFF0020" name="FLASH_OPTCR2" size="0x4"/>
  586. <AssignedBits>
  587. <Bit>
  588. <Name>PCROP0</Name>
  589. <Description/>
  590. <BitOffset>0x0</BitOffset>
  591. <BitWidth>0x8</BitWidth>
  592. <Access>RW</Access>
  593. <Values ByBit="true">
  594. <Val value="0x0">PCROP protection not active on this sector</Val>
  595. <Val value="0x1">PCROP protection active on this sector</Val>
  596. </Values>
  597. </Bit>
  598. </AssignedBits>
  599. </Field>
  600. </Category>
  601. </Bank>
  602. </Peripheral>
  603. </Peripherals>
  604. </Device>
  605. </Root>