STM32_Prog_DB_0x453.xml 30 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x453</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <!-- cortex written in word file +mpu should it be written?? -->
  8. <CPU>Cortex-M0+</CPU>
  9. <Name>STM32C03x</Name>
  10. <Series>STM32C0</Series>
  11. <Description>ARM 32-bit Cortex-M0+ based device</Description>
  12. <Configurations>
  13. <!-- JTAG_SWD Interface -->
  14. <Interface name="JTAG_SWD"/>
  15. <!-- Bootloader Interface -->
  16. <Interface name="Bootloader"/>
  17. </Configurations>
  18. <!-- Peripherals -->
  19. <Peripherals>
  20. <!-- Embedded SRAM -->
  21. <Peripheral>
  22. <Name>Embedded SRAM</Name>
  23. <Type>Storage</Type>
  24. <Description/>
  25. <ErasedValue>0x00</ErasedValue>
  26. <Access>RWE</Access>
  27. <!-- 12KB -->
  28. <Configuration>
  29. <Parameters address="0x20000000" name="SRAM" size="0x3000"/>
  30. <Description/>
  31. <Organization>Single</Organization>
  32. <Bank name="Bank 1">
  33. <Field>
  34. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x3000"/>
  35. </Field>
  36. </Bank>
  37. </Configuration>
  38. </Peripheral>
  39. <!-- Embedded Flash -->
  40. <Peripheral>
  41. <Name>Embedded Flash</Name>
  42. <Type>Storage</Type>
  43. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  44. <ErasedValue>0xFF</ErasedValue>
  45. <Access>RWE</Access>
  46. <FlashSize address="0x1FFF777C" default="0x8000"/>
  47. <BootloaderVersion address="0x1FFF17FE"/>
  48. <!-- 32KB -->
  49. <Configuration>
  50. <Parameters address="0x08000000" name=" 32 KB Embedded Flash" size="0x8000"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Allignement>0x8</Allignement>
  54. <Bank name="Bank 1">
  55. <Field>
  56. <Parameters address="0x08000000" name="sector0" occurence="0x10" size="0x800"/>
  57. </Field>
  58. </Bank>
  59. </Configuration>
  60. </Peripheral>
  61. <!-- OTP -->
  62. <Peripheral>
  63. <Name>OTP</Name>
  64. <Type>Storage</Type>
  65. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  66. <ErasedValue>0xFF</ErasedValue>
  67. <Access>RW</Access>
  68. <!-- 1 KBytes single bank -->
  69. <Configuration>
  70. <Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
  71. <Description/>
  72. <Organization>Single</Organization>
  73. <Allignement>0x4</Allignement>
  74. <Bank name="OTP">
  75. <Field>
  76. <Parameters address="0x1FFF7000" name="OTP" occurence="0x1" size="0x400"/>
  77. </Field>
  78. </Bank>
  79. </Configuration>
  80. </Peripheral>
  81. <!-- Option Bytes -->
  82. <Peripheral>
  83. <Name>Option Bytes</Name>
  84. <Type>Configuration</Type>
  85. <Description/>
  86. <Access>RW</Access>
  87. <Bank interface="JTAG_SWD">
  88. <Parameters address="0x40022020" name="Bank 1" size="0x64"/>
  89. <Category>
  90. <Name>Read Out Protection</Name>
  91. <Field>
  92. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  93. <AssignedBits>
  94. <Bit>
  95. <Name>RDP</Name>
  96. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  97. <BitOffset>0x0</BitOffset>
  98. <BitWidth>0x8</BitWidth>
  99. <Access>RW</Access>
  100. <Values>
  101. <Val value="0xAA">Level 0, no protection</Val>
  102. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  103. <Val value="0xCC">Level 2, chip protection</Val>
  104. </Values>
  105. </Bit>
  106. </AssignedBits>
  107. </Field>
  108. </Category>
  109. <Category>
  110. <Name>BOR Level</Name>
  111. <Field>
  112. <Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
  113. <AssignedBits>
  114. <Bit>
  115. <Name>BOR_EN</Name>
  116. <Description/>
  117. <BitOffset>0x8</BitOffset>
  118. <BitWidth>0x1</BitWidth>
  119. <Access>RW</Access>
  120. <Values>
  121. <Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
  122. <Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
  123. </Values>
  124. </Bit>
  125. <Bit>
  126. <Name>BORR_LEV</Name>
  127. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  128. <BitOffset>0x9</BitOffset>
  129. <BitWidth>0x2</BitWidth>
  130. <Access>RW</Access>
  131. <Values>
  132. <Val value="0x0">BOR falling level 1 with threshold around 2.1 V</Val>
  133. <Val value="0x1">BOR falling level 2 with threshold around 2.3 V</Val>
  134. <Val value="0x2">BOR falling level 3 with threshold around 2.6 V</Val>
  135. <Val value="0x3">BOR falling level 4 with threshold around 2.9 V</Val>
  136. </Values>
  137. </Bit>
  138. <Bit>
  139. <Name>BORF_LEV</Name>
  140. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  141. <BitOffset>0xB</BitOffset>
  142. <BitWidth>0x2</BitWidth>
  143. <Access>RW</Access>
  144. <Values>
  145. <Val value="0x0">BOR rising level 1 with threshold around 2.0 V</Val>
  146. <Val value="0x1">BOR rising level 2 with threshold around 2.2 V</Val>
  147. <Val value="0x2">BOR rising level 3 with threshold around 2.5 V</Val>
  148. <Val value="0x3">BOR rising level 4 with threshold around 2.8 V</Val>
  149. </Values>
  150. </Bit>
  151. </AssignedBits>
  152. </Field>
  153. </Category>
  154. <Category>
  155. <Name>User Configuration</Name>
  156. <Field>
  157. <Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
  158. <AssignedBits>
  159. <Bit>
  160. <Name>nRST_STOP</Name>
  161. <Description/>
  162. <BitOffset>0xD</BitOffset>
  163. <BitWidth>0x1</BitWidth>
  164. <Access>RW</Access>
  165. <Values>
  166. <Val value="0x0">Reset generated when entering Stop mode</Val>
  167. <Val value="0x1">No reset generated when entering Stop mode</Val>
  168. </Values>
  169. </Bit>
  170. <Bit>
  171. <Name>nRST_STDBY</Name>
  172. <Description/>
  173. <BitOffset>0xE</BitOffset>
  174. <BitWidth>0x1</BitWidth>
  175. <Access>RW</Access>
  176. <Values>
  177. <Val value="0x0">Reset generated when entering Standby mode</Val>
  178. <Val value="0x1">No reset generated when entering Standby mode</Val>
  179. </Values>
  180. </Bit>
  181. <Bit>
  182. <Name>nRST_SHDW</Name>
  183. <Description/>
  184. <BitOffset>0xF</BitOffset>
  185. <BitWidth>0x1</BitWidth>
  186. <Access>RW</Access>
  187. <Values>
  188. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  189. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  190. </Values>
  191. </Bit>
  192. <Bit>
  193. <Name>IWDG_SW</Name>
  194. <Description/>
  195. <BitOffset>0x10</BitOffset>
  196. <BitWidth>0x1</BitWidth>
  197. <Access>RW</Access>
  198. <Values>
  199. <Val value="0x0">Hardware independant watchdog</Val>
  200. <Val value="0x1">Software independant watchdog</Val>
  201. </Values>
  202. </Bit>
  203. <Bit>
  204. <Name>IWDG_STOP</Name>
  205. <Description/>
  206. <BitOffset>0x11</BitOffset>
  207. <BitWidth>0x1</BitWidth>
  208. <Access>RW</Access>
  209. <Values>
  210. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  211. <Val value="0x1">IWDG counter active in stop mode</Val>
  212. </Values>
  213. </Bit>
  214. <Bit>
  215. <Name>IWDG_STDBY</Name>
  216. <Description/>
  217. <BitOffset>0x12</BitOffset>
  218. <BitWidth>0x1</BitWidth>
  219. <Access>RW</Access>
  220. <Values>
  221. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  222. <Val value="0x1">IWDG counter active in standby mode</Val>
  223. </Values>
  224. </Bit>
  225. <Bit>
  226. <Name>WWDG_SW</Name>
  227. <Description/>
  228. <BitOffset>0x13</BitOffset>
  229. <BitWidth>0x1</BitWidth>
  230. <Access>RW</Access>
  231. <Values>
  232. <Val value="0x0">Hardware window watchdog</Val>
  233. <Val value="0x1">Software window watchdog</Val>
  234. </Values>
  235. </Bit>
  236. <Bit>
  237. <Name>HSE_NOT_REMAPPED</Name>
  238. <Description/>
  239. <BitOffset>0x15</BitOffset>
  240. <BitWidth>0x1</BitWidth>
  241. <Access>RW</Access>
  242. <Values>
  243. <Val value="0x0">HSE_NOT_REMAPPED enable</Val>
  244. <Val value="0x1">HSE_NOT_REMAPPED disable</Val>
  245. </Values>
  246. </Bit>
  247. <Bit>
  248. <Name>RAM_PARITY_CHECK</Name>
  249. <Description/>
  250. <BitOffset>0x16</BitOffset>
  251. <BitWidth>0x1</BitWidth>
  252. <Access>RW</Access>
  253. <Values>
  254. <Val value="0x0">RAM_PARITY_CHECK enable</Val>
  255. <Val value="0x1">RAM_PARITY_CHECK disable</Val>
  256. </Values>
  257. </Bit>
  258. <Bit>
  259. <Name>SECURE_MUXING_EN</Name>
  260. <Description/>
  261. <BitOffset>0x17</BitOffset>
  262. <BitWidth>0x1</BitWidth>
  263. <Access>RW</Access>
  264. <Values>
  265. <Val value="0x0">SECURE_MUXING_EN disable </Val>
  266. <Val value="0x1">SECURE_MUXING_EN enable</Val>
  267. </Values>
  268. </Bit>
  269. <Bit>
  270. <Name>nBOOT_SEL</Name>
  271. <Description/>
  272. <BitOffset>0x18</BitOffset>
  273. <BitWidth>0x1</BitWidth>
  274. <Access>RW</Access>
  275. <Values>
  276. <Val value="0x0">BOOT0 pin (legacy mode)</Val>
  277. <Val value="0x1">nBOOT0 option bit </Val>
  278. </Values>
  279. </Bit>
  280. <Bit>
  281. <Name>nBOOT1</Name>
  282. <Description/>
  283. <BitOffset>0x19</BitOffset>
  284. <BitWidth>0x1</BitWidth>
  285. <Access>RW</Access>
  286. <Values>
  287. <Val value="0x0">Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1</Val>
  288. <Val value="0x1">Boot from Flash if BOOT0 = 1, otherwise system memory</Val>
  289. </Values>
  290. </Bit>
  291. <Bit>
  292. <Name>nBOOT0</Name>
  293. <Description/>
  294. <BitOffset>0x1A</BitOffset>
  295. <BitWidth>0x1</BitWidth>
  296. <Access>RW</Access>
  297. <Values>
  298. <Val value="0x0">nBOOT0=0</Val>
  299. <Val value="0x1">nBOOT0=1</Val>
  300. </Values>
  301. </Bit>
  302. <Bit>
  303. <Name>NRST_MODE</Name>
  304. <Description/>
  305. <BitOffset>0x1B</BitOffset>
  306. <BitWidth>0x2</BitWidth>
  307. <Access>RW</Access>
  308. <Values>
  309. <Val value="0x0">Reserved</Val>
  310. <Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
  311. <Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
  312. <Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
  313. </Values>
  314. </Bit>
  315. <Bit>
  316. <Name>IRHEN</Name>
  317. <Description>Internal reset holder enable bit</Description>
  318. <BitOffset>0x1D</BitOffset>
  319. <BitWidth>0x1</BitWidth>
  320. <Access>RW</Access>
  321. <Values>
  322. <Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
  323. <Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
  324. </Values>
  325. </Bit>
  326. </AssignedBits>
  327. </Field>
  328. </Category>
  329. <Category>
  330. <Name>PCROP Protection</Name>
  331. <Field>
  332. <Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
  333. <AssignedBits>
  334. <Bit>
  335. <Name>PCROP1A_STRT</Name>
  336. <Description>Start offset of first PCROP zone in bank 1</Description>
  337. <BitOffset>0x0</BitOffset>
  338. <BitWidth>0x6</BitWidth>
  339. <Access>RW</Access>
  340. <Equation multiplier="0x200" offset="0x08000000"/>
  341. </Bit>
  342. </AssignedBits>
  343. </Field>
  344. <Field>
  345. <Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
  346. <AssignedBits>
  347. <Bit>
  348. <Name>PCROP1A_END</Name>
  349. <Description>End offset of first PCROP zone in bank 1</Description>
  350. <BitOffset>0x0</BitOffset>
  351. <BitWidth>0x6</BitWidth>
  352. <Access>RW</Access>
  353. <Equation multiplier="0x200" offset="0x08000200"/>
  354. </Bit>
  355. <Bit>
  356. <Name>PCROP_RDP</Name>
  357. <Description/>
  358. <BitOffset>0x1F</BitOffset>
  359. <BitWidth>0x1</BitWidth>
  360. <Access>RW</Access>
  361. <Values>
  362. <Val value="0x0">PCROP zone is kept when RDP is decreased; Partial Mass Erase done</Val>
  363. <Val value="0x1">PCROP zone is erased when RDP is decreased Full Mass Erase done</Val>
  364. </Values>
  365. </Bit>
  366. </AssignedBits>
  367. </Field>
  368. <Field>
  369. <Parameters address="0x40022034" name="FLASH_PCROP1BSR" size="0x4"/>
  370. <AssignedBits>
  371. <Bit>
  372. <Name>PCROP1B_STRT</Name>
  373. <Description>Start offset of second PCROP zone in bank 1</Description>
  374. <BitOffset>0x0</BitOffset>
  375. <BitWidth>0x6</BitWidth>
  376. <Access>RW</Access>
  377. <Equation multiplier="0x200" offset="0x08000000"/>
  378. </Bit>
  379. </AssignedBits>
  380. </Field>
  381. <Field>
  382. <Parameters address="0x40022038" name="FLASH_PCROP1BER" size="0x4"/>
  383. <AssignedBits>
  384. <Bit>
  385. <Name>PCROP1B_END</Name>
  386. <Description>End offset of second PCROP zone in bank 1</Description>
  387. <BitOffset>0x0</BitOffset>
  388. <BitWidth>0x6</BitWidth>
  389. <Access>RW</Access>
  390. <Equation multiplier="0x200" offset="0x08000200"/>
  391. </Bit>
  392. </AssignedBits>
  393. </Field>
  394. </Category>
  395. <Category>
  396. <Name>Write Protection</Name>
  397. <Field>
  398. <Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
  399. <AssignedBits>
  400. <Bit>
  401. <Name>WRP1A_STRT</Name>
  402. <Description>TStart offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect</Description>
  403. <BitOffset>0x0</BitOffset>
  404. <BitWidth>0x4</BitWidth>
  405. <Access>RW</Access>
  406. <Equation multiplier="0x800" offset="0x08000000"/>
  407. </Bit>
  408. <Bit>
  409. <Name>WRP1A_END</Name>
  410. <Description>End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.</Description>
  411. <BitOffset>0x10</BitOffset>
  412. <BitWidth>0x4</BitWidth>
  413. <Access>RW</Access>
  414. <Equation multiplier="0x800" offset="0x08000000"/>
  415. </Bit>
  416. </AssignedBits>
  417. </Field>
  418. <Field>
  419. <Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
  420. <AssignedBits>
  421. <Bit>
  422. <Name>WRP1B_STRT</Name>
  423. <Description>Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect</Description>
  424. <BitOffset>0x0</BitOffset>
  425. <BitWidth>0x4</BitWidth>
  426. <Access>RW</Access>
  427. <Equation multiplier="0x800" offset="0x08000000"/>
  428. </Bit>
  429. <Bit>
  430. <Name>WRP1B_END</Name>
  431. <Description>End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect</Description>
  432. <BitOffset>0x10</BitOffset>
  433. <BitWidth>0x4</BitWidth>
  434. <Access>RW</Access>
  435. <Equation multiplier="0x800" offset="0x08000000"/>
  436. </Bit>
  437. </AssignedBits>
  438. </Field>
  439. </Category>
  440. <!--</Bank>
  441. <Bank interface="JTAG_SWD">
  442. <Parameters address="0x40022080" name="Bank 2" size="0x10"/>-->
  443. <Category>
  444. <Name>FLASH security</Name>
  445. <Field>
  446. <Parameters address="0x40022080" name="FLASH_SECR" size="0x4"/>
  447. <AssignedBits>
  448. <Bit>
  449. <Name>SEC_SIZE</Name>
  450. <Description>Securable memory area size</Description>
  451. <BitOffset>0x0</BitOffset>
  452. <BitWidth>0x5</BitWidth>
  453. <Access>RW</Access>
  454. <Equation multiplier="0x800" offset="0x08000000"/>
  455. </Bit>
  456. <Bit>
  457. <Name>BOOT_LOCK</Name>
  458. <Description>Used to force boot from user area</Description>
  459. <BitOffset>0x10</BitOffset>
  460. <BitWidth>0x1</BitWidth>
  461. <Access>RW</Access>
  462. <Values>
  463. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  464. <Val value="0x1">Boot forced from Main Flash memory</Val>
  465. </Values>
  466. </Bit>
  467. </AssignedBits>
  468. </Field>
  469. </Category>
  470. </Bank>
  471. <Bank interface="Bootloader">
  472. <Parameters address="0x1FFF7800" name="Bank 1" size="0x74"/>
  473. <Category>
  474. <Name>Read Out Protection</Name>
  475. <Field>
  476. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  477. <AssignedBits>
  478. <Bit>
  479. <Name>RDP</Name>
  480. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  481. <BitOffset>0x0</BitOffset>
  482. <BitWidth>0x8</BitWidth>
  483. <Access>RW</Access>
  484. <Values>
  485. <Val value="0xAA">Level 0, no protection</Val>
  486. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  487. <Val value="0xCC">Level 2, chip protection</Val>
  488. </Values>
  489. </Bit>
  490. </AssignedBits>
  491. </Field>
  492. </Category>
  493. <Category>
  494. <Name>BOR Level</Name>
  495. <Field>
  496. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  497. <AssignedBits>
  498. <Bit>
  499. <Name>BOR_EN</Name>
  500. <Description/>
  501. <BitOffset>0x8</BitOffset>
  502. <BitWidth>0x1</BitWidth>
  503. <Access>RW</Access>
  504. <Values>
  505. <Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
  506. <Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
  507. </Values>
  508. </Bit>
  509. <Bit>
  510. <Name>BORR_LEV</Name>
  511. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  512. <BitOffset>0x9</BitOffset>
  513. <BitWidth>0x2</BitWidth>
  514. <Access>RW</Access>
  515. <Values>
  516. <Val value="0x0">BOR falling level 1 with threshold around 2.1 V</Val>
  517. <Val value="0x1">BOR falling level 2 with threshold around 2.3 V</Val>
  518. <Val value="0x2">BOR falling level 3 with threshold around 2.6 V</Val>
  519. <Val value="0x3">BOR falling level 4 with threshold around 2.9 V</Val>
  520. </Values>
  521. </Bit>
  522. <Bit>
  523. <Name>BORF_LEV</Name>
  524. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  525. <BitOffset>0xB</BitOffset>
  526. <BitWidth>0x2</BitWidth>
  527. <Access>RW</Access>
  528. <Values>
  529. <Val value="0x0">BOR rising level 1 with threshold around 2.0 V</Val>
  530. <Val value="0x1">BOR rising level 2 with threshold around 2.2 V</Val>
  531. <Val value="0x2">BOR rising level 3 with threshold around 2.5 V</Val>
  532. <Val value="0x3">BOR rising level 4 with threshold around 2.8 V</Val>
  533. </Values>
  534. </Bit>
  535. </AssignedBits>
  536. </Field>
  537. </Category>
  538. <Category>
  539. <Name>User Configuration</Name>
  540. <Field>
  541. <Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
  542. <AssignedBits>
  543. <Bit>
  544. <Name>nRST_STOP</Name>
  545. <Description/>
  546. <BitOffset>0xD</BitOffset>
  547. <BitWidth>0x1</BitWidth>
  548. <Access>RW</Access>
  549. <Values>
  550. <Val value="0x0">Reset generated when entering Stop mode</Val>
  551. <Val value="0x1">No reset generated when entering Stop mode</Val>
  552. </Values>
  553. </Bit>
  554. <Bit>
  555. <Name>nRST_STDBY</Name>
  556. <Description/>
  557. <BitOffset>0xE</BitOffset>
  558. <BitWidth>0x1</BitWidth>
  559. <Access>RW</Access>
  560. <Values>
  561. <Val value="0x0">Reset generated when entering Standby mode</Val>
  562. <Val value="0x1">No reset generated when entering Standby mode</Val>
  563. </Values>
  564. </Bit>
  565. <Bit>
  566. <Name>nRST_SHDW</Name>
  567. <Description/>
  568. <BitOffset>0xF</BitOffset>
  569. <BitWidth>0x1</BitWidth>
  570. <Access>RW</Access>
  571. <Values>
  572. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  573. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  574. </Values>
  575. </Bit>
  576. <Bit>
  577. <Name>IWDG_SW</Name>
  578. <Description/>
  579. <BitOffset>0x10</BitOffset>
  580. <BitWidth>0x1</BitWidth>
  581. <Access>RW</Access>
  582. <Values>
  583. <Val value="0x0">Hardware independant watchdog</Val>
  584. <Val value="0x1">Software independant watchdog</Val>
  585. </Values>
  586. </Bit>
  587. <Bit>
  588. <Name>IWDG_STOP</Name>
  589. <Description/>
  590. <BitOffset>0x11</BitOffset>
  591. <BitWidth>0x1</BitWidth>
  592. <Access>RW</Access>
  593. <Values>
  594. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  595. <Val value="0x1">IWDG counter active in stop mode</Val>
  596. </Values>
  597. </Bit>
  598. <Bit>
  599. <Name>IWDG_STDBY</Name>
  600. <Description/>
  601. <BitOffset>0x12</BitOffset>
  602. <BitWidth>0x1</BitWidth>
  603. <Access>RW</Access>
  604. <Values>
  605. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  606. <Val value="0x1">IWDG counter active in standby mode</Val>
  607. </Values>
  608. </Bit>
  609. <Bit>
  610. <Name>WWDG_SW</Name>
  611. <Description/>
  612. <BitOffset>0x13</BitOffset>
  613. <BitWidth>0x1</BitWidth>
  614. <Access>RW</Access>
  615. <Values>
  616. <Val value="0x0">Hardware window watchdog</Val>
  617. <Val value="0x1">Software window watchdog</Val>
  618. </Values>
  619. </Bit>
  620. <Bit>
  621. <Name>HSE_NOT_REMAPPED</Name>
  622. <Description/>
  623. <BitOffset>0x15</BitOffset>
  624. <BitWidth>0x1</BitWidth>
  625. <Access>RW</Access>
  626. <Values>
  627. <Val value="0x0">HSE_NOT_REMAPPED enable</Val>
  628. <Val value="0x1">HSE_NOT_REMAPPED disable</Val>
  629. </Values>
  630. </Bit>
  631. <Bit>
  632. <Name>RAM_PARITY_CHECK</Name>
  633. <Description/>
  634. <BitOffset>0x16</BitOffset>
  635. <BitWidth>0x1</BitWidth>
  636. <Access>RW</Access>
  637. <Values>
  638. <Val value="0x0">RAM_PARITY_CHECK enable</Val>
  639. <Val value="0x1">RAM_PARITY_CHECK disable</Val>
  640. </Values>
  641. </Bit>
  642. <Bit>
  643. <Name>SECURE_MUXING_EN</Name>
  644. <Description/>
  645. <BitOffset>0x17</BitOffset>
  646. <BitWidth>0x1</BitWidth>
  647. <Access>RW</Access>
  648. <Values>
  649. <Val value="0x0">SECURE_MUXING_EN disable </Val>
  650. <Val value="0x1">SECURE_MUXING_EN enable</Val>
  651. </Values>
  652. </Bit>
  653. <Bit>
  654. <Name>nBOOT_SEL</Name>
  655. <Description/>
  656. <BitOffset>0x18</BitOffset>
  657. <BitWidth>0x1</BitWidth>
  658. <Access>RW</Access>
  659. <Values>
  660. <Val value="0x0">BOOT0 pin (legacy mode)</Val>
  661. <Val value="0x1">nBOOT0 option bit </Val>
  662. </Values>
  663. </Bit>
  664. <Bit>
  665. <Name>nBOOT1</Name>
  666. <Description/>
  667. <BitOffset>0x19</BitOffset>
  668. <BitWidth>0x1</BitWidth>
  669. <Access>RW</Access>
  670. <Values>
  671. <Val value="0x0">Boot from Flash if BOOT0 = 1, otherwise Embedded SRAM1</Val>
  672. <Val value="0x1">Boot from Flash if BOOT0 = 1, otherwise system memory</Val>
  673. </Values>
  674. </Bit>
  675. <Bit>
  676. <Name>nBOOT0</Name>
  677. <Description/>
  678. <BitOffset>0x1A</BitOffset>
  679. <BitWidth>0x1</BitWidth>
  680. <Access>RW</Access>
  681. <Values>
  682. <Val value="0x0">nBOOT0=0</Val>
  683. <Val value="0x1">nBOOT0=1</Val>
  684. </Values>
  685. </Bit>
  686. <Bit>
  687. <Name>NRST_MODE</Name>
  688. <Description/>
  689. <BitOffset>0x1B</BitOffset>
  690. <BitWidth>0x2</BitWidth>
  691. <Access>RW</Access>
  692. <Values>
  693. <Val value="0x0">Reserved</Val>
  694. <Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
  695. <Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
  696. <Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
  697. </Values>
  698. </Bit>
  699. <Bit>
  700. <Name>IRHEN</Name>
  701. <Description>Internal reset holder enable bit</Description>
  702. <BitOffset>0x1D</BitOffset>
  703. <BitWidth>0x1</BitWidth>
  704. <Access>RW</Access>
  705. <Values>
  706. <Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
  707. <Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
  708. </Values>
  709. </Bit>
  710. </AssignedBits>
  711. </Field>
  712. </Category>
  713. <Category>
  714. <Name>PCROP Protection</Name>
  715. <Field>
  716. <Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
  717. <AssignedBits>
  718. <Bit>
  719. <Name>PCROP1A_STRT</Name>
  720. <Description>Start offset of first PCROP zone in bank 1</Description>
  721. <BitOffset>0x0</BitOffset>
  722. <BitWidth>0x6</BitWidth>
  723. <Access>RW</Access>
  724. <Equation multiplier="0x200" offset="0x08000000"/>
  725. </Bit>
  726. </AssignedBits>
  727. </Field>
  728. <Field>
  729. <Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
  730. <AssignedBits>
  731. <Bit>
  732. <Name>PCROP1A_END</Name>
  733. <Description>End offset of first PCROP zone in bank 1</Description>
  734. <BitOffset>0x0</BitOffset>
  735. <BitWidth>0x6</BitWidth>
  736. <Access>RW</Access>
  737. <Equation multiplier="0x200" offset="0x08000200"/>
  738. </Bit>
  739. <Bit>
  740. <Name>PCROP_RDP</Name>
  741. <Description/>
  742. <BitOffset>0x1F</BitOffset>
  743. <BitWidth>0x1</BitWidth>
  744. <Access>RW</Access>
  745. <Values>
  746. <Val value="0x0">PCROP zone is kept when RDP is decreased Partial Mass Erase done</Val>
  747. <Val value="0x1">PCROP zone is erased when RDP is decreased Full Mass Erase done</Val>
  748. </Values>
  749. </Bit>
  750. </AssignedBits>
  751. </Field>
  752. <Field>
  753. <Parameters name="PCROP1BSR" size="0x4" address="0x1FFF7828"/>
  754. <AssignedBits>
  755. <Bit>
  756. <Name>PCROP1B_STRT</Name>
  757. <Description>Start offset of second PCROP zone in bank 1</Description>
  758. <BitOffset>0x0</BitOffset>
  759. <BitWidth>0x6</BitWidth>
  760. <Access>RW</Access>
  761. <Equation multiplier="0x200" offset="0x08000000"/>
  762. </Bit>
  763. </AssignedBits>
  764. </Field>
  765. <Field>
  766. <Parameters name="PCROP1BER" size="0x4" address="0x1FFF7830"/>
  767. <AssignedBits>
  768. <Bit>
  769. <Name>PCROP1B_END</Name>
  770. <Description>End offset of second PCROP zone in bank 1</Description>
  771. <BitOffset>0x0</BitOffset>
  772. <BitWidth>0x6</BitWidth>
  773. <Access>RW</Access>
  774. <Equation multiplier="0x200" offset="0x08000200"/>
  775. </Bit>
  776. </AssignedBits>
  777. </Field>
  778. </Category>
  779. <Category>
  780. <Name>Write Protection</Name>
  781. <Field>
  782. <Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
  783. <AssignedBits>
  784. <Bit>
  785. <Name>WRP1A_STRT</Name>
  786. <Description>Start offset of WRP zone A of bank 1. WRP1A_STRT contains the first page of the first WRP zone to protect</Description>
  787. <BitOffset>0x0</BitOffset>
  788. <BitWidth>0x4</BitWidth>
  789. <Access>RW</Access>
  790. <Equation multiplier="0x800" offset="0x08000000"/>
  791. </Bit>
  792. <Bit>
  793. <Name>WRP1A_END</Name>
  794. <Description>End offset of WRP zone A of bank 1. WRP1A_END contains the last page of the first WRP zone to protect.</Description>
  795. <BitOffset>0x10</BitOffset>
  796. <BitWidth>0x4</BitWidth>
  797. <Access>RW</Access>
  798. <Equation multiplier="0x800" offset="0x08000000"/>
  799. </Bit>
  800. </AssignedBits>
  801. </Field>
  802. <Field>
  803. <Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
  804. <AssignedBits>
  805. <Bit>
  806. <Name>WRP1B_STRT</Name>
  807. <Description>Start offset of WRP zone B of bank 1. WRP1B_START contains the first page of the second WRP zone to protect</Description>
  808. <BitOffset>0x0</BitOffset>
  809. <BitWidth>0x4</BitWidth>
  810. <Access>RW</Access>
  811. <Equation multiplier="0x800" offset="0x08000000"/>
  812. </Bit>
  813. <Bit>
  814. <Name>WRP1B_END</Name>
  815. <Description>End offset of WRP zone B of bank 1. WRP1B_END contains the last page of the second WRP zone to protect</Description>
  816. <BitOffset>0x10</BitOffset>
  817. <BitWidth>0x4</BitWidth>
  818. <Access>RW</Access>
  819. <Equation multiplier="0x800" offset="0x08000000"/>
  820. </Bit>
  821. </AssignedBits>
  822. </Field>
  823. </Category>
  824. <!--</Bank>
  825. <Bank interface="Bootloader">
  826. <Parameters address="0x1FFF7870" name="Bank 2" size="0x4"/>-->
  827. <Category>
  828. <Name>FLASH security</Name>
  829. <Field>
  830. <Parameters address="0x1FFF7870" name="FLASH_SECR" size="0x4"/>
  831. <AssignedBits>
  832. <Bit>
  833. <Name>BOOT_LOCK</Name>
  834. <Description>Used to force boot from user area</Description>
  835. <BitOffset>0x10</BitOffset>
  836. <BitWidth>0x1</BitWidth>
  837. <Access>RW</Access>
  838. <Values>
  839. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  840. <Val value="0x1">Boot forced from Main Flash memory</Val>
  841. </Values>
  842. </Bit>
  843. <Bit>
  844. <Name>SEC_SIZE</Name>
  845. <Description>Securable memory area size</Description>
  846. <BitOffset>0x0</BitOffset>
  847. <BitWidth>0x5</BitWidth>
  848. <Access>RW</Access>
  849. <Equation multiplier="0x800" offset="0x08000000"/>
  850. </Bit>
  851. </AssignedBits>
  852. </Field>
  853. </Category>
  854. </Bank>
  855. </Peripheral>
  856. </Peripherals>
  857. </Device>
  858. </Root>