STM32_Prog_DB_0x457.xml 23 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x457</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M0+</CPU>
  8. <Name>STM32L01x/L02x</Name>
  9. <Series>STM32L0</Series>
  10. <Description>ARM 32-bit Cortex-M0+ based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  15. <WPRMOD reference="0x1">
  16. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
  17. </WPRMOD>
  18. </Configuration>
  19. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  20. <WPRMOD reference="0x0">
  21. <ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
  22. </WPRMOD>
  23. </Configuration>
  24. </Interface>
  25. <!-- Bootloader Interface -->
  26. <Interface name="Bootloader">
  27. <Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
  28. <WPRMOD reference="0x1">
  29. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
  30. </WPRMOD>
  31. </Configuration>
  32. <Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
  33. <WPRMOD reference="0x0">
  34. <ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
  35. </WPRMOD>
  36. </Configuration>
  37. </Interface>
  38. </Configurations>
  39. <!-- Peripherals -->
  40. <Peripherals>
  41. <!-- Embedded SRAM -->
  42. <Peripheral>
  43. <Name>Embedded SRAM</Name>
  44. <Type>Storage</Type>
  45. <Description/>
  46. <ErasedValue>0x00</ErasedValue>
  47. <Access>RWE</Access>
  48. <!-- 16 KB -->
  49. <Configuration>
  50. <Parameters address="0x20000000" name="SRAM" size="0x800"/>
  51. <Description/>
  52. <Organization>Single</Organization>
  53. <Bank name="Bank 1">
  54. <Field>
  55. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x800"/>
  56. </Field>
  57. </Bank>
  58. </Configuration>
  59. </Peripheral>
  60. <!-- Embedded Flash -->
  61. <Peripheral>
  62. <Name>Embedded Flash</Name>
  63. <Type>Storage</Type>
  64. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  65. <ErasedValue>0x00</ErasedValue>
  66. <Access>RWE</Access>
  67. <FlashSize address="0x1FF8007C" default="0x4000"/>
  68. <!-- 128KB single Bank -->
  69. <Configuration>
  70. <Parameters address="0x08000000" name="16 Kbytes Embedded Flash" size="0x4000"/>
  71. <Description/>
  72. <Organization>Single</Organization>
  73. <Allignement>0x4</Allignement>
  74. <Bank name="Bank 1">
  75. <Field>
  76. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x80"/>
  77. </Field>
  78. </Bank>
  79. <Bank name="EEPROM1">
  80. <Field>
  81. <Parameters address="0x08080000" name="sector65281" occurence="0x1" size="0x200"/>
  82. </Field>
  83. </Bank>
  84. </Configuration>
  85. </Peripheral>
  86. <!-- Data EEPROM -->
  87. <Peripheral>
  88. <Name>Data EEPROM</Name>
  89. <Type>Storage</Type>
  90. <Description>The Data EEPROM memory block. It contains user data.</Description>
  91. <ErasedValue>0x00</ErasedValue>
  92. <Access>RWE</Access>
  93. <!-- 1KB single Bank -->
  94. <Configuration>
  95. <Parameters address="0x08080000" name=" 1 Kbytes Data EEPROM" size="0x200"/>
  96. <Description/>
  97. <Organization>Single</Organization>
  98. <Allignement>0x4</Allignement>
  99. <Bank name="Bank 1">
  100. <Field>
  101. <Parameters address="0x08080000" name="EEPROM1" occurence="0x1" size="0x200"/>
  102. </Field>
  103. </Bank>
  104. </Configuration>
  105. </Peripheral>
  106. <!-- Option Bytes -->
  107. <Peripheral>
  108. <Name>Option Bytes</Name>
  109. <Type>Configuration</Type>
  110. <Description/>
  111. <Access>RW</Access>
  112. <Bank interface="JTAG_SWD">
  113. <Parameters address="0x4002201C" name="Bank 1" size="0x68"/>
  114. <Category>
  115. <Name>Read Out Protection</Name>
  116. <Field>
  117. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  118. <AssignedBits>
  119. <Bit>
  120. <Name>RDP</Name>
  121. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  122. <BitOffset>0x0</BitOffset>
  123. <BitWidth>0x8</BitWidth>
  124. <Access>R</Access>
  125. <Values>
  126. <Val value="0xAA">Level 0, no protection</Val>
  127. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  128. <Val value="0xCC">Level 2, chip protection</Val>
  129. </Values>
  130. </Bit>
  131. </AssignedBits>
  132. </Field>
  133. </Category>
  134. <Category>
  135. <Name>PCROP Protection</Name>
  136. <Field>
  137. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  138. <AssignedBits>
  139. <Bit reference="SPRMode">
  140. <Name>WPRMOD</Name>
  141. <Description>Sector protection mode selection option byte.</Description>
  142. <BitOffset>0x8</BitOffset>
  143. <BitWidth>0x1</BitWidth>
  144. <Access>R</Access>
  145. <Values>
  146. <Val value="0x0">WRPx bit defines sector write protection</Val>
  147. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  148. </Values>
  149. </Bit>
  150. </AssignedBits>
  151. </Field>
  152. </Category>
  153. <Category>
  154. <Name>BOR Level</Name>
  155. <Field>
  156. <Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
  157. <AssignedBits>
  158. <Bit>
  159. <Name>BOR_LEV</Name>
  160. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  161. <BitOffset>0x10</BitOffset>
  162. <BitWidth>0x4</BitWidth>
  163. <Access>R</Access>
  164. <Values>
  165. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  166. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  167. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  168. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  169. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  170. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  171. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  172. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  173. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  174. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  175. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  176. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  177. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  178. </Values>
  179. </Bit>
  180. </AssignedBits>
  181. </Field>
  182. </Category>
  183. <Category>
  184. <Name>User Configuration</Name>
  185. <Field>
  186. <Parameters address="0x4002201C" nname="FLASH_OBR" size="0x4"/>
  187. <AssignedBits>
  188. <Bit>
  189. <Name>IWDG_SW</Name>
  190. <Description/>
  191. <BitOffset>0x14</BitOffset>
  192. <BitWidth>0x1</BitWidth>
  193. <Access>R</Access>
  194. <Values>
  195. <Val value="0x0">Hardware independant watchdog</Val>
  196. <Val value="0x1">Software independant watchdog</Val>
  197. </Values>
  198. </Bit>
  199. <Bit>
  200. <Name>nRST_STOP</Name>
  201. <Description/>
  202. <BitOffset>0x15</BitOffset>
  203. <BitWidth>0x1</BitWidth>
  204. <Access>R</Access>
  205. <Values>
  206. <Val value="0x0">Reset generated when entering Stop mode</Val>
  207. <Val value="0x1">No reset generated</Val>
  208. </Values>
  209. </Bit>
  210. <Bit>
  211. <Name>nRST_STDBY</Name>
  212. <Description/>
  213. <BitOffset>0x16</BitOffset>
  214. <BitWidth>0x1</BitWidth>
  215. <Access>R</Access>
  216. <Values>
  217. <Val value="0x0">Reset generated when entering Standby mode</Val>
  218. <Val value="0x1">No reset generated</Val>
  219. </Values>
  220. </Bit>
  221. <Bit>
  222. <Name>nBOOT_SEL</Name>
  223. <Description/>
  224. <BitOffset>0x1D</BitOffset>
  225. <BitWidth>0x1</BitWidth>
  226. <Access>R</Access>
  227. <Values>
  228. <Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
  229. <Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
  230. </Values>
  231. </Bit>
  232. <Bit>
  233. <Name>nBOOT0</Name>
  234. <Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
  235. <BitOffset>0x1E</BitOffset>
  236. <BitWidth>0x1</BitWidth>
  237. <Access>R</Access>
  238. <Values>
  239. <Val value="0x0">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
  240. <Val value="0x1">Main Flash memory is selected as boot area</Val>
  241. </Values>
  242. </Bit>
  243. <Bit>
  244. <Name>nBOOT1</Name>
  245. <Description/>
  246. <BitOffset>0x1F</BitOffset>
  247. <BitWidth>0x1</BitWidth>
  248. <Access>R</Access>
  249. <Values>
  250. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  251. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  252. </Values>
  253. </Bit>
  254. </AssignedBits>
  255. </Field>
  256. </Category>
  257. <Category>
  258. <Name>Write Protection</Name>
  259. <Field>
  260. <Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
  261. <AssignedBits>
  262. <Bit config="0">
  263. <Name>WRPOT0</Name>
  264. <Description/>
  265. <BitOffset>0x0</BitOffset>
  266. <BitWidth>0x4</BitWidth>
  267. <Access>R</Access>
  268. <Values ByBit="true">
  269. <Val value="0x0">Write protection not active</Val>
  270. <Val value="0x1">Write protection active</Val>
  271. </Values>
  272. </Bit>
  273. <Bit config="1">
  274. <Name>WRPOT0</Name>
  275. <Description/>
  276. <BitOffset>0x0</BitOffset>
  277. <BitWidth>0x4</BitWidth>
  278. <Access>R</Access>
  279. <Values ByBit="true">
  280. <Val value="0x0">read/Write protection active</Val>
  281. <Val value="0x1">read/Write protection not active</Val>
  282. </Values>
  283. </Bit>
  284. </AssignedBits>
  285. </Field>
  286. </Category>
  287. </Bank>
  288. <Bank interface="JTAG_SWD">
  289. <Parameters address="0x1FF80000" name="Bank 1" size="0x10"/>
  290. <Category>
  291. <Name>Read Out Protection</Name>
  292. <Field>
  293. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  294. <AssignedBits>
  295. <Bit>
  296. <Name>RDP</Name>
  297. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  298. <BitOffset>0x0</BitOffset>
  299. <BitWidth>0x8</BitWidth>
  300. <Access>W</Access>
  301. <Values>
  302. <Val value="0xAA">Level 0, no protection</Val>
  303. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  304. <Val value="0xCC">Level 2, chip protection</Val>
  305. </Values>
  306. </Bit>
  307. </AssignedBits>
  308. </Field>
  309. </Category>
  310. <Category>
  311. <Name>PCROP Protection</Name>
  312. <Field>
  313. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  314. <AssignedBits>
  315. <Bit reference="SPRMode">
  316. <Name>WPRMOD</Name>
  317. <Description>Sector protection mode selection option byte.</Description>
  318. <BitOffset>0x8</BitOffset>
  319. <BitWidth>0x1</BitWidth>
  320. <Access>W</Access>
  321. <Values>
  322. <Val value="0x0">WRPx bit defines sector write protection</Val>
  323. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  324. </Values>
  325. </Bit>
  326. </AssignedBits>
  327. </Field>
  328. </Category>
  329. <Category>
  330. <Name>BOR Level</Name>
  331. <Field>
  332. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  333. <AssignedBits>
  334. <Bit>
  335. <Name>BOR_LEV</Name>
  336. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  337. <BitOffset>0x0</BitOffset>
  338. <BitWidth>0x4</BitWidth>
  339. <Access>W</Access>
  340. <Values>
  341. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  342. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  343. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  344. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  345. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  346. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  347. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  348. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  349. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  350. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  351. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  352. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  353. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  354. </Values>
  355. </Bit>
  356. </AssignedBits>
  357. </Field>
  358. </Category>
  359. <Category>
  360. <Name>User Configuration</Name>
  361. <Field>
  362. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  363. <AssignedBits>
  364. <Bit>
  365. <Name>IWDG_SW</Name>
  366. <Description/>
  367. <BitOffset>0x4</BitOffset>
  368. <BitWidth>0x1</BitWidth>
  369. <Access>W</Access>
  370. <Values>
  371. <Val value="0x0">Hardware independant watchdog</Val>
  372. <Val value="0x1">Software independant watchdog</Val>
  373. </Values>
  374. </Bit>
  375. <Bit>
  376. <Name>nRST_STOP</Name>
  377. <Description/>
  378. <BitOffset>0x5</BitOffset>
  379. <BitWidth>0x1</BitWidth>
  380. <Access>W</Access>
  381. <Values>
  382. <Val value="0x0">Reset generated when entering Stop mode</Val>
  383. <Val value="0x1">No reset generated</Val>
  384. </Values>
  385. </Bit>
  386. <Bit>
  387. <Name>nRST_STDBY</Name>
  388. <Description/>
  389. <BitOffset>0x6</BitOffset>
  390. <BitWidth>0x1</BitWidth>
  391. <Access>W</Access>
  392. <Values>
  393. <Val value="0x0">Reset generated when entering Standby mode</Val>
  394. <Val value="0x1">No reset generated</Val>
  395. </Values>
  396. </Bit>
  397. <Bit>
  398. <Name>nBOOT_SEL</Name>
  399. <Description/>
  400. <BitOffset>0xD</BitOffset>
  401. <BitWidth>0x1</BitWidth>
  402. <Access>W</Access>
  403. <Values>
  404. <Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
  405. <Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
  406. </Values>
  407. </Bit>
  408. <Bit>
  409. <Name>nBOOT0</Name>
  410. <Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
  411. <BitOffset>0xE</BitOffset>
  412. <BitWidth>0x1</BitWidth>
  413. <Access>W</Access>
  414. <Values>
  415. <Val value="0x0">Main Flash memory is selected as boot area</Val>
  416. <Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
  417. </Values>
  418. </Bit>
  419. <Bit>
  420. <Name>nBOOT1</Name>
  421. <Description/>
  422. <BitOffset>0x0F</BitOffset>
  423. <BitWidth>0x1</BitWidth>
  424. <Access>W</Access>
  425. <Values>
  426. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  427. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  428. </Values>
  429. </Bit>
  430. </AssignedBits>
  431. </Field>
  432. </Category>
  433. <Category>
  434. <Name>Write Protection</Name>
  435. <Field>
  436. <Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
  437. <AssignedBits>
  438. <Bit>
  439. <Name>WRPOT0</Name>
  440. <Description/>
  441. <BitOffset>0x0</BitOffset>
  442. <BitWidth>0x4</BitWidth>
  443. <Access>W</Access>
  444. <Values ByBit="true">
  445. <Val value="0x0">Write protection not active</Val>
  446. <Val value="0x1">Write protection active</Val>
  447. </Values>
  448. </Bit>
  449. </AssignedBits>
  450. </Field>
  451. </Category>
  452. </Bank>
  453. <Bank interface="Bootloader">
  454. <Parameters address="0x1FF80000" name="Bank 2" size="0x10"/>
  455. <Category>
  456. <Name>Read Out Protection</Name>
  457. <Field>
  458. <Parameters address="0x1FF80000" name="RDP" size="0x4"/>
  459. <AssignedBits>
  460. <Bit>
  461. <Name>RDP</Name>
  462. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  463. <BitOffset>0x0</BitOffset>
  464. <BitWidth>0x8</BitWidth>
  465. <Access>RW</Access>
  466. <Values>
  467. <Val value="0xAA">Level 0, no protection</Val>
  468. <Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
  469. <Val value="0xCC">Level 2, chip protection</Val>
  470. </Values>
  471. </Bit>
  472. </AssignedBits>
  473. </Field>
  474. </Category>
  475. <Category>
  476. <Name>PCROP Protection</Name>
  477. <Field>
  478. <Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
  479. <AssignedBits>
  480. <Bit reference="SPRMode">
  481. <Name>WPRMOD</Name>
  482. <Description>Sector protection mode selection option byte.</Description>
  483. <BitOffset>0x8</BitOffset>
  484. <BitWidth>0x1</BitWidth>
  485. <Access>RW</Access>
  486. <Values>
  487. <Val value="0x0">WRPx bit defines sector write protection</Val>
  488. <Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
  489. </Values>
  490. </Bit>
  491. </AssignedBits>
  492. </Field>
  493. </Category>
  494. <Category>
  495. <Name>BOR Level</Name>
  496. <Field>
  497. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  498. <AssignedBits>
  499. <Bit>
  500. <Name>BOR_LEV</Name>
  501. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  502. <BitOffset>0x0</BitOffset>
  503. <BitWidth>0x4</BitWidth>
  504. <Access>RW</Access>
  505. <Values>
  506. <Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  507. <Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  508. <Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  509. <Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  510. <Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  511. <Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
  512. <Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  513. <Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
  514. <Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
  515. <Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
  516. <Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
  517. <Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
  518. <Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
  519. </Values>
  520. </Bit>
  521. </AssignedBits>
  522. </Field>
  523. </Category>
  524. <Category>
  525. <Name>User Configuration</Name>
  526. <Field>
  527. <Parameters address="0x1FF80004" name="USER" size="0x4"/>
  528. <AssignedBits>
  529. <Bit>
  530. <Name>IWDG_SW</Name>
  531. <Description/>
  532. <BitOffset>0x4</BitOffset>
  533. <BitWidth>0x1</BitWidth>
  534. <Access>RW</Access>
  535. <Values>
  536. <Val value="0x0">Hardware independant watchdog</Val>
  537. <Val value="0x1">Software independant watchdog</Val>
  538. </Values>
  539. </Bit>
  540. <Bit>
  541. <Name>nRST_STOP</Name>
  542. <Description/>
  543. <BitOffset>0x5</BitOffset>
  544. <BitWidth>0x1</BitWidth>
  545. <Access>RW</Access>
  546. <Values>
  547. <Val value="0x0">Reset generated when entering Stop mode</Val>
  548. <Val value="0x1">No reset generated</Val>
  549. </Values>
  550. </Bit>
  551. <Bit>
  552. <Name>nRST_STDBY</Name>
  553. <Description/>
  554. <BitOffset>0x6</BitOffset>
  555. <BitWidth>0x1</BitWidth>
  556. <Access>RW</Access>
  557. <Values>
  558. <Val value="0x0">Reset generated when entering Standby mode</Val>
  559. <Val value="0x1">No reset generated</Val>
  560. </Values>
  561. </Bit>
  562. <Bit>
  563. <Name>nBOOT_SEL</Name>
  564. <Description/>
  565. <BitOffset>0x0D</BitOffset>
  566. <BitWidth>0x1</BitWidth>
  567. <Access>RW</Access>
  568. <Values>
  569. <Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
  570. <Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
  571. </Values>
  572. </Bit>
  573. <Bit>
  574. <Name>nBOOT0</Name>
  575. <Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
  576. <BitOffset>0x0E</BitOffset>
  577. <BitWidth>0x1</BitWidth>
  578. <Access>RW</Access>
  579. <Values>
  580. <Val value="0x0">Main Flash memory is selected as boot area</Val>
  581. <Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
  582. </Values>
  583. </Bit>
  584. <Bit>
  585. <Name>nBOOT1</Name>
  586. <Description/>
  587. <BitOffset>0x0F</BitOffset>
  588. <BitWidth>0x1</BitWidth>
  589. <Access>RW</Access>
  590. <Values>
  591. <Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
  592. <Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
  593. </Values>
  594. </Bit>
  595. </AssignedBits>
  596. </Field>
  597. </Category>
  598. <Category>
  599. <Name>Write Protection</Name>
  600. <Field>
  601. <Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
  602. <AssignedBits>
  603. <Bit config="0">
  604. <Name>WRPOT0</Name>
  605. <Description/>
  606. <BitOffset>0x0</BitOffset>
  607. <BitWidth>0x4</BitWidth>
  608. <Access>RW</Access>
  609. <Values ByBit="true">
  610. <Val value="0x0">Write protection not active</Val>
  611. <Val value="0x1">Write protection active</Val>
  612. </Values>
  613. </Bit>
  614. <Bit config="1">
  615. <Name>WRPOT0</Name>
  616. <Description/>
  617. <BitOffset>0x0</BitOffset>
  618. <BitWidth>0x4</BitWidth>
  619. <Access>RW</Access>
  620. <Values ByBit="true">
  621. <Val value="0x0">read/Write protection active</Val>
  622. <Val value="0x1">read/Write protection not active</Val>
  623. </Values>
  624. </Bit>
  625. </AssignedBits>
  626. </Field>
  627. </Category>
  628. </Bank>
  629. </Peripheral>
  630. </Peripherals>
  631. </Device>
  632. </Root>