STM32_Prog_DB_0x472.xml 120 KB

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  1. <?xml version="1.0" encoding="UTF-8"?>
  2. <Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
  3. <Device>
  4. <DeviceID>0x472</DeviceID>
  5. <Vendor>STMicroelectronics</Vendor>
  6. <Type>MCU</Type>
  7. <CPU>Cortex-M33</CPU>
  8. <Name>STM32L5xx</Name>
  9. <Series>STM32L5</Series>
  10. <Description>ARM 32-bit Cortex-M33 based device</Description>
  11. <Configurations>
  12. <!-- JTAG_SWD Interface -->
  13. <Interface name="JTAG_SWD">
  14. <Configuration number="0xA"> <!-- Single Bank non secure -->
  15. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  16. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  17. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  18. </Configuration>
  19. <Configuration number="0xB"> <!-- Dual Bank non secure -->
  20. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  21. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  22. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  23. </Configuration>
  24. <Configuration number="0xC"> <!-- Single Bank secure -->
  25. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  26. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  27. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  28. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  29. </Configuration>
  30. <Configuration number="0xD"> <!-- Dual Bank secure -->
  31. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  32. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  33. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  34. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  35. </Configuration>
  36. <Configuration number="0xE"> <!-- Single Bank secure + RDP -->
  37. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  38. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  39. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  40. <!-- <RDP reference="0x0"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP> -->
  41. </Configuration>
  42. <Configuration number="0xF"> <!-- Dual Bank secure + RDP -->
  43. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  44. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </TZEN>
  45. <valueLine> <ReadRegister address="0x0BFA05E0" mask="0x00000FFF" value="0x100"/> </valueLine>
  46. <!-- <RDP reference="0x0"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP> -->
  47. </Configuration>
  48. <Configuration number="0x0"> <!-- Single Bank non secure -->
  49. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  50. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  51. </Configuration>
  52. <Configuration number="0x1"> <!-- Dual Bank non secure -->
  53. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  54. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  55. </Configuration>
  56. <Configuration number="0x2"> <!-- Single Bank secure -->
  57. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  58. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  59. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  60. </Configuration>
  61. <Configuration number="0x3"> <!-- Dual Bank secure -->
  62. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  63. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </TZEN>
  64. <RDP reference="0x1"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP>
  65. </Configuration>
  66. <Configuration number="0x4"> <!-- Single Bank secure + RDP -->
  67. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  68. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  69. <!-- <RDP reference="0x0"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP> -->
  70. </Configuration>
  71. <Configuration number="0x5"> <!-- Dual Bank secure + RDP -->
  72. <DBANK reference="0x1"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  73. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  74. <!-- <RDP reference="0x0"> <ReadRegister address="0x40022040" mask="0x000000FF" value="0x000000AA"/> </RDP> -->
  75. </Configuration>
  76. </Interface>
  77. <!-- Bootloader Interface -->
  78. <Interface name="Bootloader">
  79. <Configuration number="0x6"> <!-- Single Bank Secure-->
  80. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  81. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  82. </Configuration>
  83. <Configuration number="0x7"> <!-- Dual Bank Secure-->
  84. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  85. <TZEN reference="0x1"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x80000000"/> </TZEN>
  86. </Configuration>
  87. <Configuration number="0x8"> <!-- Single Bank non Secure-->
  88. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x0"/> </DBANK>
  89. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  90. </Configuration>
  91. <Configuration number="0x9"> <!-- Dual Bank non Secure-->
  92. <DBANK reference="0x0"> <ReadRegister address="0x40022040" mask="0x400000" value="0x400000"/> </DBANK>
  93. <TZEN reference="0x0"> <ReadRegister address="0x40022040" mask="0x80000000" value="0x0"/> </TZEN>
  94. </Configuration>
  95. </Interface>
  96. </Configurations>
  97. <!-- Peripherals -->
  98. <Peripherals>
  99. <!-- Embedded SRAM -->
  100. <Peripheral>
  101. <Name>Embedded SRAM</Name>
  102. <Type>Storage</Type>
  103. <Description/>
  104. <ErasedValue>0x00</ErasedValue>
  105. <Access>RWE</Access>
  106. <!-- 96 KB -->
  107. <Configuration config="0,1,6,7,8,9,10,11">
  108. <Parameters address="0x20000000" name="SRAM" size="0x40000"/>
  109. <Description/>
  110. <Organization>Single</Organization>
  111. <Bank name="Bank 1">
  112. <Field>
  113. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x40000"/>
  114. </Field>
  115. </Bank>
  116. </Configuration>
  117. <Configuration config="4,5,14,15">
  118. <Parameters address="0x20000000" name="SRAM" size="0x10000"/>
  119. <Description/>
  120. <Organization>Single</Organization>
  121. <Bank name="Bank 1">
  122. <Field>
  123. <Parameters address="0x20000000" name="SRAM" occurence="0x1" size="0x10000"/>
  124. </Field>
  125. </Bank>
  126. </Configuration>
  127. <Configuration config="2,3,12,13">
  128. <Parameters address="0x20018000" name="SRAM" size="0x10000"/>
  129. <Description/>
  130. <Organization>Single</Organization>
  131. <Bank name="Bank 1">
  132. <Field>
  133. <Parameters address="0x20030000" name="SRAM" occurence="0x1" size="0x10000"/>
  134. </Field>
  135. </Bank>
  136. </Configuration>
  137. </Peripheral>
  138. <!-- Embedded Flash -->
  139. <Peripheral>
  140. <Name>Embedded Flash</Name>
  141. <Type>Storage</Type>
  142. <Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
  143. <ErasedValue>0xFF</ErasedValue>
  144. <Access>RWE</Access>
  145. <FlashSize address="0x0BFA05E0" default="0x80000"/>
  146. <Configuration config="0,4,6,8"> <!-- Single Bank -->
  147. <Parameters address="0x08000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
  148. <Description/>
  149. <Organization>Single</Organization>
  150. <Allignement>0x8</Allignement>
  151. <Bank name="Bank 1">
  152. <Field>
  153. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x1000"/>
  154. </Field>
  155. </Bank>
  156. </Configuration>
  157. <Configuration config="10,14"> <!-- Single Bank -->
  158. <Parameters address="0x08000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/>
  159. <Description/>
  160. <Organization>Single</Organization>
  161. <Allignement>0x8</Allignement>
  162. <Bank name="Bank 1">
  163. <Field>
  164. <Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x1000"/>
  165. </Field>
  166. </Bank>
  167. </Configuration>
  168. <Configuration config="1,5,7,9"> <!-- dual Bank -->
  169. <Parameters address="0x08000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
  170. <Description/>
  171. <Organization>Dual</Organization>
  172. <Allignement>0x8</Allignement>
  173. <Bank name="Bank 1">
  174. <Field>
  175. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x800"/>
  176. </Field>
  177. </Bank>
  178. <Bank name="Bank 2">
  179. <Field>
  180. <Parameters address="0x08040000" name="sector128" occurence="0x80" size="0x800"/>
  181. </Field>
  182. </Bank>
  183. </Configuration>
  184. <Configuration config="11,15"> <!-- dual Bank -->
  185. <Parameters address="0x08000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/>
  186. <Description/>
  187. <Organization>Dual</Organization>
  188. <Allignement>0x8</Allignement>
  189. <Bank name="Bank 1">
  190. <Field>
  191. <Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
  192. </Field>
  193. </Bank>
  194. <Bank name="Bank 2">
  195. <Field>
  196. <Parameters address="0x08020000" name="sector64" occurence="0x40" size="0x800"/>
  197. </Field>
  198. </Bank>
  199. </Configuration>
  200. <Configuration config="2"> <!-- Single Bank secure -->
  201. <Parameters address="0x0C000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
  202. <Description/>
  203. <Organization>Single</Organization>
  204. <Allignement>0x8</Allignement>
  205. <Bank name="Bank 1">
  206. <Field>
  207. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x1000"/>
  208. </Field>
  209. </Bank>
  210. </Configuration>
  211. <Configuration config="12"> <!-- Single Bank secure -->
  212. <Parameters address="0x0C000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/>
  213. <Description/>
  214. <Organization>Single</Organization>
  215. <Allignement>0x8</Allignement>
  216. <Bank name="Bank 1">
  217. <Field>
  218. <Parameters address="0x0c000000" name="sector0" occurence="0x40" size="0x1000"/>
  219. </Field>
  220. </Bank>
  221. </Configuration>
  222. <Configuration config="3"> <!-- dual Bank secure -->
  223. <Parameters address="0x0c000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
  224. <Description/>
  225. <Organization>Dual</Organization>
  226. <Allignement>0x8</Allignement>
  227. <Bank name="Bank 1">
  228. <Field>
  229. <Parameters address="0x0c000000" name="sector0" occurence="0x80" size="0x800"/>
  230. </Field>
  231. </Bank>
  232. <Bank name="Bank 2">
  233. <Field>
  234. <Parameters address="0x0c040000" name="sector128" occurence="0x80" size="0x800"/>
  235. </Field>
  236. </Bank>
  237. </Configuration>
  238. <Configuration config="13"> <!-- dual Bank secure -->
  239. <Parameters address="0x0c000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/>
  240. <Description/>
  241. <Organization>Dual</Organization>
  242. <Allignement>0x8</Allignement>
  243. <Bank name="Bank 1">
  244. <Field>
  245. <Parameters address="0x0c000000" name="sector0" occurence="0x40" size="0x800"/>
  246. </Field>
  247. </Bank>
  248. <Bank name="Bank 2">
  249. <Field>
  250. <Parameters address="0x0c020000" name="sector64" occurence="0x40" size="0x800"/>
  251. </Field>
  252. </Bank>
  253. </Configuration>
  254. </Peripheral>
  255. <!-- Data EEPROM -->
  256. <Peripheral>
  257. <Name>Data EEPROM</Name>
  258. <Type>Storage</Type>
  259. <Description>The Data EEPROM memory block. It contains user data.</Description>
  260. <ErasedValue>0xFF</ErasedValue>
  261. <Access>RWE</Access>
  262. <Configuration config="2,4">
  263. <Parameters address="0x08000000" name=" 512 Kbytes Data EEPROM" size="0x80000"/>
  264. <Description/>
  265. <Organization>Single</Organization>
  266. <Allignement>0x8</Allignement>
  267. <Bank name="Bank 1">
  268. <Field>
  269. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x1000"/>
  270. </Field>
  271. </Bank>
  272. </Configuration>
  273. <Configuration config="12,14">
  274. <Parameters address="0x08000000" name=" 256 Kbytes Data EEPROM" size="0x40000"/>
  275. <Description/>
  276. <Organization>Single</Organization>
  277. <Allignement>0x8</Allignement>
  278. <Bank name="Bank 1">
  279. <Field>
  280. <Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x1000"/>
  281. </Field>
  282. </Bank>
  283. </Configuration>
  284. <Configuration config="3,5">
  285. <Parameters address="0x08000000" name=" 512 Kbytes Data EEPROM" size="0x80000"/>
  286. <Description/>
  287. <Organization>Single</Organization>
  288. <Allignement>0x8</Allignement>
  289. <Bank name="Bank 1">
  290. <Field>
  291. <Parameters address="0x08000000" name="sector0" occurence="0x80" size="0x800"/>
  292. </Field>
  293. </Bank>
  294. <Bank name="Bank 2">
  295. <Field>
  296. <Parameters address="0x08040000" name="sector128" occurence="0x80" size="0x800"/>
  297. </Field>
  298. </Bank>
  299. </Configuration>
  300. <Configuration config="15,13">
  301. <Parameters address="0x08000000" name=" 256 Kbytes Data EEPROM" size="0x40000"/>
  302. <Description/>
  303. <Organization>Single</Organization>
  304. <Allignement>0x8</Allignement>
  305. <Bank name="Bank 1">
  306. <Field>
  307. <Parameters address="0x08000000" name="sector0" occurence="0x40" size="0x800"/>
  308. </Field>
  309. </Bank>
  310. <Bank name="Bank 2">
  311. <Field>
  312. <Parameters address="0x08020000" name="sector128" occurence="0x40" size="0x800"/>
  313. </Field>
  314. </Bank>
  315. </Configuration>
  316. <!-- Dummy Config Just to avoid crash when TZEN=0 -->
  317. <Configuration config="1">
  318. <Parameters address="0x0C000000" name=" 512 Kbytes Data EEPROM" size="0x80000"/>
  319. <Description/>
  320. <Organization>Single</Organization>
  321. <Allignement>0x8</Allignement>
  322. <Bank name="Bank 1">
  323. <Field>
  324. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x800"/>
  325. </Field>
  326. </Bank>
  327. <Bank name="Bank 2">
  328. <Field>
  329. <Parameters address="0x0C040000" name="sector128" occurence="0x80" size="0x800"/>
  330. </Field>
  331. </Bank>
  332. </Configuration>
  333. <Configuration config="11">
  334. <Parameters address="0x0C000000" name=" 256 Kbytes Data EEPROM" size="0x40000"/>
  335. <Description/>
  336. <Organization>Single</Organization>
  337. <Allignement>0x8</Allignement>
  338. <Bank name="Bank 1">
  339. <Field>
  340. <Parameters address="0x0C000000" name="sector0" occurence="0x40" size="0x800"/>
  341. </Field>
  342. </Bank>
  343. <Bank name="Bank 2">
  344. <Field>
  345. <Parameters address="0x0C020000" name="sector128" occurence="0x40" size="0x800"/>
  346. </Field>
  347. </Bank>
  348. </Configuration>
  349. <Configuration config="0">
  350. <Parameters address="0x0C000000" name=" 512 Kbytes Data EEPROM" size="0x80000"/>
  351. <Description/>
  352. <Organization>Single</Organization>
  353. <Allignement>0x8</Allignement>
  354. <Bank name="Bank 1">
  355. <Field>
  356. <Parameters address="0x0C000000" name="sector0" occurence="0x80" size="0x1000"/>
  357. </Field>
  358. </Bank>
  359. </Configuration>
  360. <Configuration config="10">
  361. <Parameters address="0x0C000000" name=" 256 Kbytes Data EEPROM" size="0x40000"/>
  362. <Description/>
  363. <Organization>Single</Organization>
  364. <Allignement>0x8</Allignement>
  365. <Bank name="Bank 1">
  366. <Field>
  367. <Parameters address="0x0C000000" name="sector0" occurence="0x40" size="0x1000"/>
  368. </Field>
  369. </Bank>
  370. </Configuration>
  371. </Peripheral>
  372. <!-- OTP -->
  373. <Peripheral>
  374. <Name>OTP</Name>
  375. <Type>Storage</Type>
  376. <Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
  377. <ErasedValue>0xFF</ErasedValue>
  378. <Access>RW</Access>
  379. <!-- 512 Bytes single bank -->
  380. <Configuration>
  381. <Parameters address="0x0BFA0000" name=" 512 Bytes Data OTP" size="0x200"/>
  382. <Description/>
  383. <Organization>Single</Organization>
  384. <Allignement>0x4</Allignement>
  385. <Bank name="OTP">
  386. <Field>
  387. <Parameters address="0x0BFA0000" name="OTP" occurence="0x1" size="0x200"/>
  388. </Field>
  389. </Bank>
  390. </Configuration>
  391. </Peripheral>
  392. <!-- Mirror Option Bytes -->
  393. <!--Peripheral>
  394. <Name>MirrorOptionBytes</Name>
  395. <Type>Storage</Type>
  396. <Description>Mirror Option Bytes contains the extra area.</Description>
  397. <ErasedValue>0xFF</ErasedValue>
  398. <Access>RW</Access-->
  399. <!-- 48 Bytes single bank -->
  400. <!--Configuration>
  401. <Parameters name=" 48 Bytes Data MirrorOptionBytes" size="0x30" address="0x40022040"/>
  402. <Description/>
  403. <Organization>Single</Organization>
  404. <Allignement>0x4</Allignement>
  405. <Bank name="MirrorOptionBytes">
  406. <Field>
  407. <Parameters name="MirrorOptionBytes" size="0x30" address="0x40022040" occurence="0x1"/>
  408. </Field>
  409. </Bank>
  410. </Configuration>
  411. </Peripheral-->
  412. <!-- Option Bytes -->
  413. <Peripheral>
  414. <Name>Option Bytes</Name>
  415. <Type>Configuration</Type>
  416. <Description/>
  417. <Access>RW</Access>
  418. <Configuration config="4,5,14,15">
  419. <Bank interface="JTAG_SWD">
  420. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  421. <Category>
  422. <Name>Read Out Protection</Name>
  423. <Field>
  424. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  425. <AssignedBits>
  426. <Bit>
  427. <Name>RDP</Name>
  428. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  429. <BitOffset>0x0</BitOffset>
  430. <BitWidth>0x8</BitWidth>
  431. <Access>RW</Access>
  432. <Values>
  433. <Val value="0xAA">Level 0, no protection</Val>
  434. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  435. <Val value="0xDC">Level 1, read protection of memories</Val>
  436. <Val value="0xCC">Level 2, chip protection</Val>
  437. </Values>
  438. </Bit>
  439. </AssignedBits>
  440. </Field>
  441. </Category>
  442. <Category>
  443. <Name>BOR Level</Name>
  444. <Field>
  445. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  446. <AssignedBits>
  447. <Bit>
  448. <Name>BOR_LEV</Name>
  449. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  450. <BitOffset>0x8</BitOffset>
  451. <BitWidth>0x3</BitWidth>
  452. <Access>RW</Access>
  453. <Values>
  454. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  455. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  456. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  457. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  458. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  459. </Values>
  460. </Bit>
  461. </AssignedBits>
  462. </Field>
  463. </Category>
  464. <Category>
  465. <Name>User Configuration</Name>
  466. <Field>
  467. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  468. <AssignedBits>
  469. <Bit>
  470. <Name>nRST_STOP</Name>
  471. <Description/>
  472. <BitOffset>0xC</BitOffset>
  473. <BitWidth>0x1</BitWidth>
  474. <Access>RW</Access>
  475. <Values>
  476. <Val value="0x0">Reset generated when entering Stop mode</Val>
  477. <Val value="0x1">No reset generated when entering Stop mode</Val>
  478. </Values>
  479. </Bit>
  480. <Bit>
  481. <Name>nRST_STDBY</Name>
  482. <Description/>
  483. <BitOffset>0xD</BitOffset>
  484. <BitWidth>0x1</BitWidth>
  485. <Access>RW</Access>
  486. <Values>
  487. <Val value="0x0">Reset generated when entering Standby mode</Val>
  488. <Val value="0x1">No reset generated when entering Standby mode</Val>
  489. </Values>
  490. </Bit>
  491. <Bit>
  492. <Name>nRST_SHDW</Name>
  493. <Description/>
  494. <BitOffset>0xE</BitOffset>
  495. <BitWidth>0x1</BitWidth>
  496. <Access>RW</Access>
  497. <Values>
  498. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  499. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  500. </Values>
  501. </Bit>
  502. <Bit>
  503. <Name>IWDG_SW</Name>
  504. <Description/>
  505. <BitOffset>0x10</BitOffset>
  506. <BitWidth>0x1</BitWidth>
  507. <Access>RW</Access>
  508. <Values>
  509. <Val value="0x0">Hardware independant watchdog</Val>
  510. <Val value="0x1">Software independant watchdog</Val>
  511. </Values>
  512. </Bit>
  513. <Bit>
  514. <Name>IWDG_STOP</Name>
  515. <Description/>
  516. <BitOffset>0x11</BitOffset>
  517. <BitWidth>0x1</BitWidth>
  518. <Access>RW</Access>
  519. <Values>
  520. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  521. <Val value="0x1">IWDG counter active in stop mode</Val>
  522. </Values>
  523. </Bit>
  524. <Bit>
  525. <Name>IWDG_STDBY</Name>
  526. <Description/>
  527. <BitOffset>0x12</BitOffset>
  528. <BitWidth>0x1</BitWidth>
  529. <Access>RW</Access>
  530. <Values>
  531. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  532. <Val value="0x1">IWDG counter active in standby mode</Val>
  533. </Values>
  534. </Bit>
  535. <Bit>
  536. <Name>WWDG_SW</Name>
  537. <Description/>
  538. <BitOffset>0x13</BitOffset>
  539. <BitWidth>0x1</BitWidth>
  540. <Access>RW</Access>
  541. <Values>
  542. <Val value="0x0">Hardware window watchdog</Val>
  543. <Val value="0x1">Software window watchdog</Val>
  544. </Values>
  545. </Bit>
  546. <Bit>
  547. <Name>SWAP_BANK</Name>
  548. <Description/>
  549. <BitOffset>0x14</BitOffset>
  550. <BitWidth>0x1</BitWidth>
  551. <Access>RW</Access>
  552. <Values>
  553. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  554. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  555. </Values>
  556. </Bit>
  557. <Bit>
  558. <Name>DB256</Name>
  559. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  560. <BitOffset>0x15</BitOffset>
  561. <BitWidth>0x1</BitWidth>
  562. <Access>RW</Access>
  563. <Values>
  564. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  565. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  566. </Values>
  567. </Bit>
  568. <Bit>
  569. <Name>DBANK</Name>
  570. <Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
  571. <BitOffset>0x16</BitOffset>
  572. <BitWidth>0x1</BitWidth>
  573. <Access>RW</Access>
  574. <Values>
  575. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  576. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  577. </Values>
  578. </Bit>
  579. <Bit>
  580. <Name>SRAM2_PE</Name>
  581. <Description>SRAM2 parity check enable</Description>
  582. <BitOffset>0x18</BitOffset>
  583. <BitWidth>0x1</BitWidth>
  584. <Access>RW</Access>
  585. <Values>
  586. <Val value="0x0">SRAM2 parity check enable</Val>
  587. <Val value="0x1">SRAM2 parity check disable</Val>
  588. </Values>
  589. </Bit>
  590. <Bit>
  591. <Name>SRAM2_RST</Name>
  592. <Description>SRAM2 Erase when system reset</Description>
  593. <BitOffset>0x19</BitOffset>
  594. <BitWidth>0x1</BitWidth>
  595. <Access>RW</Access>
  596. <Values>
  597. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  598. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  599. </Values>
  600. </Bit>
  601. <Bit>
  602. <Name>nSWBOOT0</Name>
  603. <Description>Software BOOT0</Description>
  604. <BitOffset>0x1A</BitOffset>
  605. <BitWidth>0x1</BitWidth>
  606. <Access>RW</Access>
  607. <Values>
  608. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  609. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  610. </Values>
  611. </Bit>
  612. <Bit>
  613. <Name>nBOOT0</Name>
  614. <Description>nBOOT0 option bit</Description>
  615. <BitOffset>0x1B</BitOffset>
  616. <BitWidth>0x1</BitWidth>
  617. <Access>RW</Access>
  618. <Values>
  619. <Val value="0x0">nBOOT0 = 0</Val>
  620. <Val value="0x1">nBOOT0 = 1</Val>
  621. </Values>
  622. </Bit>
  623. <Bit>
  624. <Name>PA15_PUPEN</Name>
  625. <Description>PA15 pull-up enable</Description>
  626. <BitOffset>0x1C</BitOffset>
  627. <BitWidth>0x1</BitWidth>
  628. <Access>RW</Access>
  629. <Values>
  630. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  631. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  632. </Values>
  633. </Bit>
  634. <Bit>
  635. <Name>TZEN</Name>
  636. <Description>Global TrustZone security enable</Description>
  637. <BitOffset>0x1F</BitOffset>
  638. <BitWidth>0x1</BitWidth>
  639. <Access>RW</Access>
  640. <Values>
  641. <Val value="0x0">Global TrustZone security disabled</Val>
  642. <Val value="0x1">Global TrustZone security enabled</Val>
  643. </Values>
  644. </Bit>
  645. </AssignedBits>
  646. </Field>
  647. <Field>
  648. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  649. <AssignedBits>
  650. <Bit>
  651. <Name>HDP1EN</Name>
  652. <Description>Hide protection first area enable</Description>
  653. <BitOffset>0x1F</BitOffset>
  654. <BitWidth>0x1</BitWidth>
  655. <Access>RW</Access>
  656. <Values>
  657. <Val value="0x0">No HDP area 1</Val>
  658. <Val value="0x1">HDP first area is enabled</Val>
  659. </Values>
  660. </Bit>
  661. <Bit config="4,14">
  662. <Name>HDP1_PEND</Name>
  663. <Description>End page of first hide protection area</Description>
  664. <BitOffset>0x10</BitOffset>
  665. <BitWidth>0x7</BitWidth>
  666. <Access>RW</Access>
  667. <Equation multiplier="0x4" offset="0x08000000"/>
  668. </Bit>
  669. <Bit config="5,15">
  670. <Name>HDP1_PEND</Name>
  671. <Description>End page of first hide protection area</Description>
  672. <BitOffset>0x10</BitOffset>
  673. <BitWidth>0x7</BitWidth>
  674. <Access>RW</Access>
  675. <Equation multiplier="0x2" offset="0x08000000"/>
  676. </Bit>
  677. </AssignedBits>
  678. </Field>
  679. <Field>
  680. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  681. <AssignedBits>
  682. <Bit config="4,14,15,5">
  683. <Name>HDP2EN</Name>
  684. <Description>Hide protection second area enable</Description>
  685. <BitOffset>0x1F</BitOffset>
  686. <BitWidth>0x1</BitWidth>
  687. <Access>RW</Access>
  688. <Values>
  689. <Val value="0x0">No HDP area 2</Val>
  690. <Val value="0x1">HDP second area is enabled</Val>
  691. </Values>
  692. </Bit>
  693. <Bit config="4,14">
  694. <Name>HDP2_PEND</Name>
  695. <Description>End page of second hide protection area</Description>
  696. <BitOffset>0x10</BitOffset>
  697. <BitWidth>0x7</BitWidth>
  698. <Access>RW</Access>
  699. <Equation multiplier="0x4" offset="0x08000000"/>
  700. </Bit>
  701. <Bit config="5,15">
  702. <Name>HDP2_PEND</Name>
  703. <Description>End page of second hide protection area</Description>
  704. <BitOffset>0x10</BitOffset>
  705. <BitWidth>0x7</BitWidth>
  706. <Access>RW</Access>
  707. <Equation multiplier="0x2" offset="0x08000000"/>
  708. </Bit>
  709. </AssignedBits>
  710. </Field>
  711. <Field>
  712. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  713. <AssignedBits>
  714. <Bit>
  715. <Name>NSBOOTADD0</Name>
  716. <Description>Non-secure Boot base address 0</Description>
  717. <BitOffset>0x7</BitOffset>
  718. <BitWidth>0x19</BitWidth>
  719. <Access>RW</Access>
  720. <Equation multiplier="0x80" offset="0x0000000"/>
  721. </Bit>
  722. </AssignedBits>
  723. </Field>
  724. <Field>
  725. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  726. <AssignedBits>
  727. <Bit>
  728. <Name>NSBOOTADD1</Name>
  729. <Description>Non-secure Boot base address 1</Description>
  730. <BitOffset>0x7</BitOffset>
  731. <BitWidth>0x19</BitWidth>
  732. <Access>RW</Access>
  733. <Equation multiplier="0x80" offset="0x0000000"/>
  734. </Bit>
  735. </AssignedBits>
  736. </Field>
  737. <Field>
  738. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  739. <AssignedBits>
  740. <Bit>
  741. <Name>SECBOOTADD0</Name>
  742. <Description>Secure boot base address 0</Description>
  743. <BitOffset>0x7</BitOffset>
  744. <BitWidth>0x19</BitWidth>
  745. <Access>RW</Access>
  746. <Equation multiplier="0x80" offset="0x0000000"/>
  747. </Bit>
  748. </AssignedBits>
  749. </Field>
  750. <Field>
  751. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  752. <AssignedBits>
  753. <Bit>
  754. <Name>BOOT_LOCK</Name>
  755. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  756. <BitOffset>0x0</BitOffset>
  757. <BitWidth>0x1</BitWidth>
  758. <Access>RW</Access>
  759. <Values>
  760. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  761. <Val value="0x1">Boot forced from base address memory</Val>
  762. </Values>
  763. </Bit>
  764. </AssignedBits>
  765. </Field>
  766. </Category>
  767. <Category>
  768. <Name>Secure Area 1</Name>
  769. <Field>
  770. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  771. <AssignedBits>
  772. <Bit config="4,14">
  773. <Name>SECWM1_PSTRT</Name>
  774. <Description>Start page of first secure area</Description>
  775. <BitOffset>0x0</BitOffset>
  776. <BitWidth>0x7</BitWidth>
  777. <Access>RW</Access>
  778. <Equation multiplier="0x1000" offset="0x08000000"/>
  779. </Bit>
  780. <Bit config="5,15">
  781. <Name>SECWM1_PSTRT</Name>
  782. <Description>Start page of first secure area</Description>
  783. <BitOffset>0x0</BitOffset>
  784. <BitWidth>0x7</BitWidth>
  785. <Access>RW</Access>
  786. <Equation multiplier="0x800" offset="0x08000000"/>
  787. </Bit>
  788. <Bit config="4,14">
  789. <Name>SECWM1_PEND</Name>
  790. <Description>End page of first secure area</Description>
  791. <BitOffset>0x10</BitOffset>
  792. <BitWidth>0x7</BitWidth>
  793. <Access>RW</Access>
  794. <Equation multiplier="0x1000" offset="0x08000000"/>
  795. </Bit>
  796. <Bit config="5,15">
  797. <Name>SECWM1_PEND</Name>
  798. <Description>End page of first secure area</Description>
  799. <BitOffset>0x10</BitOffset>
  800. <BitWidth>0x7</BitWidth>
  801. <Access>RW</Access>
  802. <Equation multiplier="0x800" offset="0x08000000"/>
  803. </Bit>
  804. </AssignedBits>
  805. </Field>
  806. </Category>
  807. <!-- <Category> -->
  808. <!-- <Name>PCROP Protection (Bank 1)</Name> -->
  809. <!-- <Field> -->
  810. <!-- <Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022054"/> -->
  811. <!-- <AssignedBits> -->
  812. <!-- <Bit config="4"> -->
  813. <!-- <Name>PCROP1_PSTRT</Name> -->
  814. <!-- <Description>Start page of first PCROP area</Description> -->
  815. <!-- <BitOffset>0x0</BitOffset> -->
  816. <!-- <BitWidth>0x7</BitWidth> -->
  817. <!-- <Access>RW</Access> -->
  818. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  819. <!-- </Bit> -->
  820. <!-- <Bit config="5"> -->
  821. <!-- <Name>PCROP1_STRT</Name> -->
  822. <!-- <Description>Flash Bank 1 PCROP start address</Description> -->
  823. <!-- <BitOffset>0x0</BitOffset> -->
  824. <!-- <BitWidth>0x7</BitWidth> -->
  825. <!-- <Access>RW</Access> -->
  826. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  827. <!-- </Bit> -->
  828. <!-- <Bit config="4"> -->
  829. <!-- <Name>HDP1_PEND</Name> -->
  830. <!-- <Description>End page of first hide protection area</Description> -->
  831. <!-- <BitOffset>0x10</BitOffset> -->
  832. <!-- <BitWidth>0x7</BitWidth> -->
  833. <!-- <Access>RW</Access> -->
  834. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  835. <!-- </Bit> -->
  836. <!-- <Bit config="5"> -->
  837. <!-- <Name>HDP1_PEND</Name> -->
  838. <!-- <Description>End page of first hide protection area</Description> -->
  839. <!-- <BitOffset>0x10</BitOffset> -->
  840. <!-- <BitWidth>0x7</BitWidth> -->
  841. <!-- <Access>RW</Access> -->
  842. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  843. <!-- </Bit> -->
  844. <!-- <Bit> -->
  845. <!-- <Name>PCROP1EN</Name> -->
  846. <!-- <Description>PCROP1 area enable</Description> -->
  847. <!-- <BitOffset>0xF</BitOffset> -->
  848. <!-- <BitWidth>0x1</BitWidth> -->
  849. <!-- <Access>RW</Access> -->
  850. <!-- <Values> -->
  851. <!-- <Val value="0x0">PCROP1 area is disabled</Val> -->
  852. <!-- <Val value="0x1">PCROP1 area is enabled</Val> -->
  853. <!-- </Values> -->
  854. <!-- </Bit> -->
  855. <!-- <Bit> -->
  856. <!-- <Name>HDP1EN</Name> -->
  857. <!-- <Description>Hide protection first area enable</Description> -->
  858. <!-- <BitOffset>0x1F</BitOffset> -->
  859. <!-- <BitWidth>0x1</BitWidth> -->
  860. <!-- <Access>RW</Access> -->
  861. <!-- <Values> -->
  862. <!-- <Val value="0x0">No HDP area 1</Val> -->
  863. <!-- <Val value="0x1">HDP first area is enabled</Val> -->
  864. <!-- </Values> -->
  865. <!-- </Bit> -->
  866. <!-- </AssignedBits> -->
  867. <!-- </Field> -->
  868. <!-- </Category> -->
  869. <Category>
  870. <Name>Write Protection 1</Name>
  871. <Field>
  872. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  873. <AssignedBits>
  874. <Bit config="4,14">
  875. <Name>WRP1A_PSTRT</Name>
  876. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  877. <BitOffset>0x0</BitOffset>
  878. <BitWidth>0x7</BitWidth>
  879. <Access>RW</Access>
  880. <Equation multiplier="0x1000" offset="0x08000000"/>
  881. </Bit>
  882. <Bit config="5,15">
  883. <Name>WRP1A_PSTRT</Name>
  884. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  885. <BitOffset>0x0</BitOffset>
  886. <BitWidth>0x7</BitWidth>
  887. <Access>RW</Access>
  888. <Equation multiplier="0x800" offset="0x08000000"/>
  889. </Bit>
  890. <Bit config="4,14">
  891. <Name>WRP1A_PEND</Name>
  892. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  893. <BitOffset>0x10</BitOffset>
  894. <BitWidth>0x7</BitWidth>
  895. <Access>RW</Access>
  896. <Equation multiplier="0x1000" offset="0x08000000"/>
  897. </Bit>
  898. <Bit config="5,15">
  899. <Name>WRP1A_PEND</Name>
  900. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  901. <BitOffset>0x10</BitOffset>
  902. <BitWidth>0x7</BitWidth>
  903. <Access>RW</Access>
  904. <Equation multiplier="0x800" offset="0x08000000"/>
  905. </Bit>
  906. </AssignedBits>
  907. </Field>
  908. <Field>
  909. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  910. <AssignedBits>
  911. <Bit config="4,14">
  912. <Name>WRP1B_PSTRT</Name>
  913. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  914. <BitOffset>0x0</BitOffset>
  915. <BitWidth>0x7</BitWidth>
  916. <Access>RW</Access>
  917. <Equation multiplier="0x1000" offset="0x08000000"/>
  918. </Bit>
  919. <Bit config="5,15">
  920. <Name>WRP1B_PSTRT</Name>
  921. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  922. <BitOffset>0x0</BitOffset>
  923. <BitWidth>0x7</BitWidth>
  924. <Access>RW</Access>
  925. <Equation multiplier="0x800" offset="0x08000000"/>
  926. </Bit>
  927. <Bit config="4,14">
  928. <Name>WRP1B_PEND</Name>
  929. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  930. <BitOffset>0x10</BitOffset>
  931. <BitWidth>0x7</BitWidth>
  932. <Access>RW</Access>
  933. <Equation multiplier="0x1000" offset="0x08000000"/>
  934. </Bit>
  935. <Bit config="5,15">
  936. <Name>WRP1B_PEND</Name>
  937. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  938. <BitOffset>0x10</BitOffset>
  939. <BitWidth>0x7</BitWidth>
  940. <Access>RW</Access>
  941. <Equation multiplier="0x800" offset="0x08000000"/>
  942. </Bit>
  943. </AssignedBits>
  944. </Field>
  945. </Category>
  946. </Bank>
  947. <Bank interface="JTAG_SWD">
  948. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  949. <Category>
  950. <Name>Secure Area 2</Name>
  951. <Field>
  952. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  953. <AssignedBits>
  954. <Bit config="4">
  955. <Name>SECWM2_PSTRT</Name>
  956. <Description>Start page of second secure area</Description>
  957. <BitOffset>0x0</BitOffset>
  958. <BitWidth>0x7</BitWidth>
  959. <Access>RW</Access>
  960. <Equation multiplier="0x1000" offset="0x08040000"/>
  961. </Bit>
  962. <Bit config="14">
  963. <Name>SECWM2_PSTRT</Name>
  964. <Description>Start page of second secure area</Description>
  965. <BitOffset>0x0</BitOffset>
  966. <BitWidth>0x7</BitWidth>
  967. <Access>RW</Access>
  968. <Equation multiplier="0x1000" offset="0x08020000"/>
  969. </Bit>
  970. <Bit config="5">
  971. <Name>SECWM2_PSTRT</Name>
  972. <Description>Start page of second secure area</Description>
  973. <BitOffset>0x0</BitOffset>
  974. <BitWidth>0x7</BitWidth>
  975. <Access>RW</Access>
  976. <Equation multiplier="0x800" offset="0x08040000"/>
  977. </Bit>
  978. <Bit config="15">
  979. <Name>SECWM2_PSTRT</Name>
  980. <Description>Start page of second secure area</Description>
  981. <BitOffset>0x0</BitOffset>
  982. <BitWidth>0x7</BitWidth>
  983. <Access>RW</Access>
  984. <Equation multiplier="0x800" offset="0x08020000"/>
  985. </Bit>
  986. <Bit config="4">
  987. <Name>SECWM2_PEND</Name>
  988. <Description>End page of second secure area</Description>
  989. <BitOffset>0x10</BitOffset>
  990. <BitWidth>0x7</BitWidth>
  991. <Access>RW</Access>
  992. <Equation multiplier="0x1000" offset="0x08040000"/>
  993. </Bit>
  994. <Bit config="14">
  995. <Name>SECWM2_PEND</Name>
  996. <Description>End page of second secure area</Description>
  997. <BitOffset>0x10</BitOffset>
  998. <BitWidth>0x7</BitWidth>
  999. <Access>RW</Access>
  1000. <Equation multiplier="0x1000" offset="0x08020000"/>
  1001. </Bit>
  1002. <Bit config="5">
  1003. <Name>SECWM2_PEND</Name>
  1004. <Description>End page of second secure area</Description>
  1005. <BitOffset>0x10</BitOffset>
  1006. <BitWidth>0x7</BitWidth>
  1007. <Access>RW</Access>
  1008. <Equation multiplier="0x800" offset="0x08040000"/>
  1009. </Bit>
  1010. <Bit config="15">
  1011. <Name>SECWM2_PEND</Name>
  1012. <Description>End page of second secure area</Description>
  1013. <BitOffset>0x10</BitOffset>
  1014. <BitWidth>0x7</BitWidth>
  1015. <Access>RW</Access>
  1016. <Equation multiplier="0x800" offset="0x08020000"/>
  1017. </Bit>
  1018. </AssignedBits>
  1019. </Field>
  1020. </Category>
  1021. <!-- <Category> -->
  1022. <!-- <Name>PCROP Protection (Bank 2)</Name> -->
  1023. <!-- <Field> -->
  1024. <!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/> -->
  1025. <!-- <AssignedBits> -->
  1026. <!-- <Bit config="4"> -->
  1027. <!-- <Name>PCROP2_PSTRT</Name> -->
  1028. <!-- <Description>Start page of first PCROP area</Description> -->
  1029. <!-- <BitOffset>0x0</BitOffset> -->
  1030. <!-- <BitWidth>0x7</BitWidth> -->
  1031. <!-- <Access>RW</Access> -->
  1032. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  1033. <!-- </Bit> -->
  1034. <!-- <Bit config="5"> -->
  1035. <!-- <Name>PCROP2_STRT</Name> -->
  1036. <!-- <Description>Flash Bank 2 PCROP start address</Description> -->
  1037. <!-- <BitOffset>0x0</BitOffset> -->
  1038. <!-- <BitWidth>0x7</BitWidth> -->
  1039. <!-- <Access>RW</Access> -->
  1040. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  1041. <!-- </Bit> -->
  1042. <!-- <Bit config="4"> -->
  1043. <!-- <Name>HDP2_PEND</Name> -->
  1044. <!-- <Description>End page of second hide protection area</Description> -->
  1045. <!-- <BitOffset>0x10</BitOffset> -->
  1046. <!-- <BitWidth>0x7</BitWidth> -->
  1047. <!-- <Access>RW</Access> -->
  1048. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  1049. <!-- </Bit> -->
  1050. <!-- <Bit config="5"> -->
  1051. <!-- <Name>HDP2_PEND</Name> -->
  1052. <!-- <Description>End page of second hide protection area</Description> -->
  1053. <!-- <BitOffset>0x10</BitOffset> -->
  1054. <!-- <BitWidth>0x7</BitWidth> -->
  1055. <!-- <Access>RW</Access> -->
  1056. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  1057. <!-- </Bit> -->
  1058. <!-- <Bit config="4"> -->
  1059. <!-- <Name>PCROP2EN</Name> -->
  1060. <!-- <Description>PCROP2 area enable</Description> -->
  1061. <!-- <BitOffset>0xF</BitOffset> -->
  1062. <!-- <BitWidth>0x1</BitWidth> -->
  1063. <!-- <Access>RW</Access> -->
  1064. <!-- <Values> -->
  1065. <!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
  1066. <!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
  1067. <!-- </Values> -->
  1068. <!-- </Bit> -->
  1069. <!-- <Bit config="4,5"> -->
  1070. <!-- <Name>HDP2EN</Name> -->
  1071. <!-- <Description>Hide protection second area enable</Description> -->
  1072. <!-- <BitOffset>0x1F</BitOffset> -->
  1073. <!-- <BitWidth>0x1</BitWidth> -->
  1074. <!-- <Access>RW</Access> -->
  1075. <!-- <Values> -->
  1076. <!-- <Val value="0x0">No HDP area 2</Val> -->
  1077. <!-- <Val value="0x1">HDP second area is enabled</Val> -->
  1078. <!-- </Values> -->
  1079. <!-- </Bit> -->
  1080. <!-- </AssignedBits> -->
  1081. <!-- </Field> -->
  1082. <!-- </Category> -->
  1083. <Category>
  1084. <Name>Write Protection 2</Name>
  1085. <Field>
  1086. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  1087. <AssignedBits>
  1088. <Bit config="4">
  1089. <Name>WRP2A_PSTRT</Name>
  1090. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1091. <BitOffset>0x0</BitOffset>
  1092. <BitWidth>0x7</BitWidth>
  1093. <Access>RW</Access>
  1094. <Equation multiplier="0x1000" offset="0x08040000"/>
  1095. </Bit>
  1096. <Bit config="14">
  1097. <Name>WRP2A_PSTRT</Name>
  1098. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1099. <BitOffset>0x0</BitOffset>
  1100. <BitWidth>0x7</BitWidth>
  1101. <Access>RW</Access>
  1102. <Equation multiplier="0x1000" offset="0x08020000"/>
  1103. </Bit>
  1104. <Bit config="5">
  1105. <Name>WRP2A_PSTRT</Name>
  1106. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1107. <BitOffset>0x0</BitOffset>
  1108. <BitWidth>0x7</BitWidth>
  1109. <Access>RW</Access>
  1110. <Equation multiplier="0x800" offset="0x08040000"/>
  1111. </Bit>
  1112. <Bit config="15">
  1113. <Name>WRP2A_PSTRT</Name>
  1114. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1115. <BitOffset>0x0</BitOffset>
  1116. <BitWidth>0x7</BitWidth>
  1117. <Access>RW</Access>
  1118. <Equation multiplier="0x800" offset="0x08020000"/>
  1119. </Bit>
  1120. <Bit config="4">
  1121. <Name>WRP2A_PEND</Name>
  1122. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1123. <BitOffset>0x10</BitOffset>
  1124. <BitWidth>0x7</BitWidth>
  1125. <Access>RW</Access>
  1126. <Equation multiplier="0x1000" offset="0x08040000"/>
  1127. </Bit>
  1128. <Bit config="14">
  1129. <Name>WRP2A_PEND</Name>
  1130. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1131. <BitOffset>0x10</BitOffset>
  1132. <BitWidth>0x7</BitWidth>
  1133. <Access>RW</Access>
  1134. <Equation multiplier="0x1000" offset="0x08020000"/>
  1135. </Bit>
  1136. <Bit config="5">
  1137. <Name>WRP2A_PEND</Name>
  1138. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1139. <BitOffset>0x10</BitOffset>
  1140. <BitWidth>0x7</BitWidth>
  1141. <Access>RW</Access>
  1142. <Equation multiplier="0x800" offset="0x08040000"/>
  1143. </Bit>
  1144. <Bit config="15">
  1145. <Name>WRP2A_PEND</Name>
  1146. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1147. <BitOffset>0x10</BitOffset>
  1148. <BitWidth>0x7</BitWidth>
  1149. <Access>RW</Access>
  1150. <Equation multiplier="0x800" offset="0x08020000"/>
  1151. </Bit>
  1152. </AssignedBits>
  1153. </Field>
  1154. <Field>
  1155. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  1156. <AssignedBits>
  1157. <Bit config="4">
  1158. <Name>WRP2B_PSTRT</Name>
  1159. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1160. <BitOffset>0x0</BitOffset>
  1161. <BitWidth>0x7</BitWidth>
  1162. <Access>RW</Access>
  1163. <Equation multiplier="0x1000" offset="0x08040000"/>
  1164. </Bit>
  1165. <Bit config="14">
  1166. <Name>WRP2B_PSTRT</Name>
  1167. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1168. <BitOffset>0x0</BitOffset>
  1169. <BitWidth>0x7</BitWidth>
  1170. <Access>RW</Access>
  1171. <Equation multiplier="0x1000" offset="0x08020000"/>
  1172. </Bit>
  1173. <Bit config="5">
  1174. <Name>WRP2B_PSTRT</Name>
  1175. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1176. <BitOffset>0x0</BitOffset>
  1177. <BitWidth>0x7</BitWidth>
  1178. <Access>RW</Access>
  1179. <Equation multiplier="0x800" offset="0x08040000"/>
  1180. </Bit>
  1181. <Bit config="15">
  1182. <Name>WRP2B_PSTRT</Name>
  1183. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1184. <BitOffset>0x0</BitOffset>
  1185. <BitWidth>0x7</BitWidth>
  1186. <Access>RW</Access>
  1187. <Equation multiplier="0x800" offset="0x08020000"/>
  1188. </Bit>
  1189. <Bit config="4">
  1190. <Name>WRP2B_PEND</Name>
  1191. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1192. <BitOffset>0x10</BitOffset>
  1193. <BitWidth>0x7</BitWidth>
  1194. <Access>RW</Access>
  1195. <Equation multiplier="0x1000" offset="0x08040000"/>
  1196. </Bit>
  1197. <Bit config="14">
  1198. <Name>WRP2B_PEND</Name>
  1199. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1200. <BitOffset>0x10</BitOffset>
  1201. <BitWidth>0x7</BitWidth>
  1202. <Access>RW</Access>
  1203. <Equation multiplier="0x1000" offset="0x08020000"/>
  1204. </Bit>
  1205. <Bit config="5">
  1206. <Name>WRP2B_PEND</Name>
  1207. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1208. <BitOffset>0x10</BitOffset>
  1209. <BitWidth>0x7</BitWidth>
  1210. <Access>RW</Access>
  1211. <Equation multiplier="0x800" offset="0x08040000"/>
  1212. </Bit>
  1213. <Bit config="15">
  1214. <Name>WRP2B_PEND</Name>
  1215. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1216. <BitOffset>0x10</BitOffset>
  1217. <BitWidth>0x7</BitWidth>
  1218. <Access>RW</Access>
  1219. <Equation multiplier="0x800" offset="0x08020000"/>
  1220. </Bit>
  1221. </AssignedBits>
  1222. </Field>
  1223. </Category>
  1224. </Bank>
  1225. </Configuration>
  1226. <Configuration config="0,1,10,11">
  1227. <Bank interface="JTAG_SWD">
  1228. <Parameters address="0x40022040" name="Bank 1" size="0x20"/>
  1229. <Category>
  1230. <Name>Read Out Protection</Name>
  1231. <Field>
  1232. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1233. <AssignedBits>
  1234. <Bit>
  1235. <Name>RDP</Name>
  1236. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1237. <BitOffset>0x0</BitOffset>
  1238. <BitWidth>0x8</BitWidth>
  1239. <Access>RW</Access>
  1240. <Values>
  1241. <Val value="0xAA">Level 0, no protection</Val>
  1242. <Val value="0xDC">Level 1, read protection of memories</Val>
  1243. <Val value="0xCC">Level 2, chip protection</Val>
  1244. </Values>
  1245. </Bit>
  1246. </AssignedBits>
  1247. </Field>
  1248. </Category>
  1249. <Category>
  1250. <Name>BOR Level</Name>
  1251. <Field>
  1252. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1253. <AssignedBits>
  1254. <Bit>
  1255. <Name>BOR_LEV</Name>
  1256. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  1257. <BitOffset>0x8</BitOffset>
  1258. <BitWidth>0x3</BitWidth>
  1259. <Access>RW</Access>
  1260. <Values>
  1261. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1262. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1263. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1264. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1265. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1266. </Values>
  1267. </Bit>
  1268. </AssignedBits>
  1269. </Field>
  1270. </Category>
  1271. <Category>
  1272. <Name>User Configuration</Name>
  1273. <Field>
  1274. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  1275. <AssignedBits>
  1276. <Bit>
  1277. <Name>nRST_STOP</Name>
  1278. <Description/>
  1279. <BitOffset>0xC</BitOffset>
  1280. <BitWidth>0x1</BitWidth>
  1281. <Access>RW</Access>
  1282. <Values>
  1283. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1284. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1285. </Values>
  1286. </Bit>
  1287. <Bit>
  1288. <Name>nRST_STDBY</Name>
  1289. <Description/>
  1290. <BitOffset>0xD</BitOffset>
  1291. <BitWidth>0x1</BitWidth>
  1292. <Access>RW</Access>
  1293. <Values>
  1294. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1295. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1296. </Values>
  1297. </Bit>
  1298. <Bit>
  1299. <Name>nRST_SHDW</Name>
  1300. <Description/>
  1301. <BitOffset>0xE</BitOffset>
  1302. <BitWidth>0x1</BitWidth>
  1303. <Access>RW</Access>
  1304. <Values>
  1305. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1306. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1307. </Values>
  1308. </Bit>
  1309. <Bit>
  1310. <Name>IWDG_SW</Name>
  1311. <Description/>
  1312. <BitOffset>0x10</BitOffset>
  1313. <BitWidth>0x1</BitWidth>
  1314. <Access>RW</Access>
  1315. <Values>
  1316. <Val value="0x0">Hardware independant watchdog</Val>
  1317. <Val value="0x1">Software independant watchdog</Val>
  1318. </Values>
  1319. </Bit>
  1320. <Bit>
  1321. <Name>IWDG_STOP</Name>
  1322. <Description/>
  1323. <BitOffset>0x11</BitOffset>
  1324. <BitWidth>0x1</BitWidth>
  1325. <Access>RW</Access>
  1326. <Values>
  1327. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1328. <Val value="0x1">IWDG counter active in stop mode</Val>
  1329. </Values>
  1330. </Bit>
  1331. <Bit>
  1332. <Name>IWDG_STDBY</Name>
  1333. <Description/>
  1334. <BitOffset>0x12</BitOffset>
  1335. <BitWidth>0x1</BitWidth>
  1336. <Access>RW</Access>
  1337. <Values>
  1338. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1339. <Val value="0x1">IWDG counter active in standby mode</Val>
  1340. </Values>
  1341. </Bit>
  1342. <Bit>
  1343. <Name>WWDG_SW</Name>
  1344. <Description/>
  1345. <BitOffset>0x13</BitOffset>
  1346. <BitWidth>0x1</BitWidth>
  1347. <Access>RW</Access>
  1348. <Values>
  1349. <Val value="0x0">Hardware window watchdog</Val>
  1350. <Val value="0x1">Software window watchdog</Val>
  1351. </Values>
  1352. </Bit>
  1353. <Bit>
  1354. <Name>SWAP_BANK</Name>
  1355. <Description/>
  1356. <BitOffset>0x14</BitOffset>
  1357. <BitWidth>0x1</BitWidth>
  1358. <Access>RW</Access>
  1359. <Values>
  1360. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1361. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1362. </Values>
  1363. </Bit>
  1364. <Bit>
  1365. <Name>DB256</Name>
  1366. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  1367. <BitOffset>0x15</BitOffset>
  1368. <BitWidth>0x1</BitWidth>
  1369. <Access>RW</Access>
  1370. <Values>
  1371. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  1372. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  1373. </Values>
  1374. </Bit>
  1375. <Bit>
  1376. <Name>DBANK</Name>
  1377. <Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
  1378. <BitOffset>0x16</BitOffset>
  1379. <BitWidth>0x1</BitWidth>
  1380. <Access>RW</Access>
  1381. <Values>
  1382. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1383. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1384. </Values>
  1385. </Bit>
  1386. <Bit>
  1387. <Name>SRAM2_PE</Name>
  1388. <Description>SRAM2 parity check enable</Description>
  1389. <BitOffset>0x18</BitOffset>
  1390. <BitWidth>0x1</BitWidth>
  1391. <Access>RW</Access>
  1392. <Values>
  1393. <Val value="0x0">SRAM2 parity check enable</Val>
  1394. <Val value="0x1">SRAM2 parity check disable</Val>
  1395. </Values>
  1396. </Bit>
  1397. <Bit>
  1398. <Name>SRAM2_RST</Name>
  1399. <Description>SRAM2 Erase when system reset</Description>
  1400. <BitOffset>0x19</BitOffset>
  1401. <BitWidth>0x1</BitWidth>
  1402. <Access>RW</Access>
  1403. <Values>
  1404. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1405. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1406. </Values>
  1407. </Bit>
  1408. <Bit>
  1409. <Name>nSWBOOT0</Name>
  1410. <Description>Software BOOT0</Description>
  1411. <BitOffset>0x1A</BitOffset>
  1412. <BitWidth>0x1</BitWidth>
  1413. <Access>RW</Access>
  1414. <Values>
  1415. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1416. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1417. </Values>
  1418. </Bit>
  1419. <Bit>
  1420. <Name>nBOOT0</Name>
  1421. <Description>nBOOT0 option bit</Description>
  1422. <BitOffset>0x1B</BitOffset>
  1423. <BitWidth>0x1</BitWidth>
  1424. <Access>RW</Access>
  1425. <Values>
  1426. <Val value="0x0">nBOOT0 = 0</Val>
  1427. <Val value="0x1">nBOOT0 = 1</Val>
  1428. </Values>
  1429. </Bit>
  1430. <Bit>
  1431. <Name>PA15_PUPEN</Name>
  1432. <Description>PA15 pull-up enable</Description>
  1433. <BitOffset>0x1C</BitOffset>
  1434. <BitWidth>0x1</BitWidth>
  1435. <Access>RW</Access>
  1436. <Values>
  1437. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1438. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1439. </Values>
  1440. </Bit>
  1441. <Bit>
  1442. <Name>TZEN</Name>
  1443. <Description>Global TrustZone security enable</Description>
  1444. <BitOffset>0x1F</BitOffset>
  1445. <BitWidth>0x1</BitWidth>
  1446. <Access>RW</Access>
  1447. <Values>
  1448. <Val value="0x0">Global TrustZone security disabled</Val>
  1449. <Val value="0x1">Global TrustZone security enabled</Val>
  1450. </Values>
  1451. </Bit>
  1452. </AssignedBits>
  1453. </Field>
  1454. <Field>
  1455. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  1456. <AssignedBits>
  1457. <Bit>
  1458. <Name>NSBOOTADD0</Name>
  1459. <Description>Non-secure Boot base address 0</Description>
  1460. <BitOffset>0x7</BitOffset>
  1461. <BitWidth>0x19</BitWidth>
  1462. <Access>RW</Access>
  1463. <Equation multiplier="0x80" offset="0x0000000"/>
  1464. </Bit>
  1465. </AssignedBits>
  1466. </Field>
  1467. <Field>
  1468. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  1469. <AssignedBits>
  1470. <Bit>
  1471. <Name>NSBOOTADD1</Name>
  1472. <Description>Non-secure Boot base address 1</Description>
  1473. <BitOffset>0x7</BitOffset>
  1474. <BitWidth>0x19</BitWidth>
  1475. <Access>RW</Access>
  1476. <Equation multiplier="0x80" offset="0x0000000"/>
  1477. </Bit>
  1478. </AssignedBits>
  1479. </Field>
  1480. <Field>
  1481. <Parameters address="0x4002204C" name="BOOT_LOCK" size="0x4"/>
  1482. <AssignedBits>
  1483. <Bit>
  1484. <Name>BOOT_LOCK</Name>
  1485. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  1486. <BitOffset>0x0</BitOffset>
  1487. <BitWidth>0x1</BitWidth>
  1488. <Access>RW</Access>
  1489. <Values>
  1490. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  1491. <Val value="0x1">Boot forced from base address memory</Val>
  1492. </Values>
  1493. </Bit>
  1494. </AssignedBits>
  1495. </Field>
  1496. </Category>
  1497. <Category>
  1498. <Name>Write Protection 1</Name>
  1499. <Field>
  1500. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  1501. <AssignedBits>
  1502. <Bit config="0,10">
  1503. <Name>WRP1A_PSTRT</Name>
  1504. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1505. <BitOffset>0x0</BitOffset>
  1506. <BitWidth>0x7</BitWidth>
  1507. <Access>RW</Access>
  1508. <Equation multiplier="0x1000" offset="0x08000000"/>
  1509. </Bit>
  1510. <Bit config="1,11">
  1511. <Name>WRP1A_PSTRT</Name>
  1512. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  1513. <BitOffset>0x0</BitOffset>
  1514. <BitWidth>0x7</BitWidth>
  1515. <Access>RW</Access>
  1516. <Equation multiplier="0x800" offset="0x08000000"/>
  1517. </Bit>
  1518. <Bit config="0,10">
  1519. <Name>WRP1A_PEND</Name>
  1520. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1521. <BitOffset>0x10</BitOffset>
  1522. <BitWidth>0x7</BitWidth>
  1523. <Access>RW</Access>
  1524. <Equation multiplier="0x1000" offset="0x08000000"/>
  1525. </Bit>
  1526. <Bit config="1,11">
  1527. <Name>WRP1A_PEND</Name>
  1528. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  1529. <BitOffset>0x10</BitOffset>
  1530. <BitWidth>0x7</BitWidth>
  1531. <Access>RW</Access>
  1532. <Equation multiplier="0x800" offset="0x08000000"/>
  1533. </Bit>
  1534. </AssignedBits>
  1535. </Field>
  1536. <Field>
  1537. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  1538. <AssignedBits>
  1539. <Bit config="0,10">
  1540. <Name>WRP1B_PSTRT</Name>
  1541. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1542. <BitOffset>0x0</BitOffset>
  1543. <BitWidth>0x7</BitWidth>
  1544. <Access>RW</Access>
  1545. <Equation multiplier="0x1000" offset="0x08000000"/>
  1546. </Bit>
  1547. <Bit config="1,11">
  1548. <Name>WRP1B_PSTRT</Name>
  1549. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  1550. <BitOffset>0x0</BitOffset>
  1551. <BitWidth>0x7</BitWidth>
  1552. <Access>RW</Access>
  1553. <Equation multiplier="0x800" offset="0x08000000"/>
  1554. </Bit>
  1555. <Bit config="0,10">
  1556. <Name>WRP1B_PEND</Name>
  1557. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1558. <BitOffset>0x10</BitOffset>
  1559. <BitWidth>0x7</BitWidth>
  1560. <Access>RW</Access>
  1561. <Equation multiplier="0x1000" offset="0x08000000"/>
  1562. </Bit>
  1563. <Bit config="1,11">
  1564. <Name>WRP1B_PEND</Name>
  1565. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  1566. <BitOffset>0x10</BitOffset>
  1567. <BitWidth>0x7</BitWidth>
  1568. <Access>RW</Access>
  1569. <Equation multiplier="0x800" offset="0x08000000"/>
  1570. </Bit>
  1571. </AssignedBits>
  1572. </Field>
  1573. </Category>
  1574. </Bank>
  1575. <Bank interface="JTAG_SWD">
  1576. <Parameters address="0x40022060" name="Bank 2" size="0x10"/>
  1577. <!-- <Category> -->
  1578. <!-- <Name>PCROP Protection (Bank 2)</Name> -->
  1579. <!-- <Field> -->
  1580. <!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/> -->
  1581. <!-- <AssignedBits> -->
  1582. <!-- <Bit config="1"> -->
  1583. <!-- <Name>PCROP2_PSTRT</Name> -->
  1584. <!-- <Description>Start page of first PCROP area</Description> -->
  1585. <!-- <BitOffset>0x0</BitOffset> -->
  1586. <!-- <BitWidth>0x7</BitWidth> -->
  1587. <!-- <Access>RW</Access> -->
  1588. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  1589. <!-- </Bit> -->
  1590. <!-- <Bit config="1"> -->
  1591. <!-- <Name>PCROP2_STRT</Name> -->
  1592. <!-- <Description>Flash Bank 2 PCROP start address</Description> -->
  1593. <!-- <BitOffset>0x0</BitOffset> -->
  1594. <!-- <BitWidth>0x7</BitWidth> -->
  1595. <!-- <Access>RW</Access> -->
  1596. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  1597. <!-- </Bit> -->
  1598. <!-- <Bit config="0"> -->
  1599. <!-- <Name>HDP2_PEND</Name> -->
  1600. <!-- <Description>End page of second hide protection area</Description> -->
  1601. <!-- <BitOffset>0x10</BitOffset> -->
  1602. <!-- <BitWidth>0x7</BitWidth> -->
  1603. <!-- <Access>RW</Access> -->
  1604. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  1605. <!-- </Bit> -->
  1606. <!-- <Bit config="1"> -->
  1607. <!-- <Name>HDP2_PEND</Name> -->
  1608. <!-- <Description>End page of second hide protection area</Description> -->
  1609. <!-- <BitOffset>0x10</BitOffset> -->
  1610. <!-- <BitWidth>0x7</BitWidth> -->
  1611. <!-- <Access>RW</Access> -->
  1612. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  1613. <!-- </Bit> -->
  1614. <!-- <Bit config="1"> -->
  1615. <!-- <Name>PCROP2EN</Name> -->
  1616. <!-- <Description>PCROP2 area enable</Description> -->
  1617. <!-- <BitOffset>0xF</BitOffset> -->
  1618. <!-- <BitWidth>0x1</BitWidth> -->
  1619. <!-- <Access>RW</Access> -->
  1620. <!-- <Values> -->
  1621. <!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
  1622. <!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
  1623. <!-- </Values> -->
  1624. <!-- </Bit> -->
  1625. <!-- <Bit config="1"> -->
  1626. <!-- <Name>HDP2EN</Name> -->
  1627. <!-- <Description>Hide protection second area enable</Description> -->
  1628. <!-- <BitOffset>0x1F</BitOffset> -->
  1629. <!-- <BitWidth>0x1</BitWidth> -->
  1630. <!-- <Access>RW</Access> -->
  1631. <!-- <Values> -->
  1632. <!-- <Val value="0x0">No HDP area 2</Val> -->
  1633. <!-- <Val value="0x1">HDP second area is enabled</Val> -->
  1634. <!-- </Values> -->
  1635. <!-- </Bit> -->
  1636. <!-- </AssignedBits> -->
  1637. <!-- </Field> -->
  1638. <!-- </Category> -->
  1639. <Category>
  1640. <Name>Write Protection 2</Name>
  1641. <Field>
  1642. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  1643. <AssignedBits>
  1644. <Bit config="0">
  1645. <Name>WRP2A_PSTRT</Name>
  1646. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1647. <BitOffset>0x0</BitOffset>
  1648. <BitWidth>0x7</BitWidth>
  1649. <Access>RW</Access>
  1650. <Equation multiplier="0x1000" offset="0x08040000"/>
  1651. </Bit>
  1652. <Bit config="10">
  1653. <Name>WRP2A_PSTRT</Name>
  1654. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1655. <BitOffset>0x0</BitOffset>
  1656. <BitWidth>0x7</BitWidth>
  1657. <Access>RW</Access>
  1658. <Equation multiplier="0x1000" offset="0x08020000"/>
  1659. </Bit>
  1660. <Bit config="1">
  1661. <Name>WRP2A_PSTRT</Name>
  1662. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1663. <BitOffset>0x0</BitOffset>
  1664. <BitWidth>0x7</BitWidth>
  1665. <Access>RW</Access>
  1666. <Equation multiplier="0x800" offset="0x08040000"/>
  1667. </Bit>
  1668. <Bit config="11">
  1669. <Name>WRP2A_PSTRT</Name>
  1670. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  1671. <BitOffset>0x0</BitOffset>
  1672. <BitWidth>0x7</BitWidth>
  1673. <Access>RW</Access>
  1674. <Equation multiplier="0x800" offset="0x08020000"/>
  1675. </Bit>
  1676. <Bit config="0">
  1677. <Name>WRP2A_PEND</Name>
  1678. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1679. <BitOffset>0x10</BitOffset>
  1680. <BitWidth>0x7</BitWidth>
  1681. <Access>RW</Access>
  1682. <Equation multiplier="0x1000" offset="0x08040000"/>
  1683. </Bit>
  1684. <Bit config="10">
  1685. <Name>WRP2A_PEND</Name>
  1686. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1687. <BitOffset>0x10</BitOffset>
  1688. <BitWidth>0x7</BitWidth>
  1689. <Access>RW</Access>
  1690. <Equation multiplier="0x1000" offset="0x08020000"/>
  1691. </Bit>
  1692. <Bit config="1">
  1693. <Name>WRP2A_PEND</Name>
  1694. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1695. <BitOffset>0x10</BitOffset>
  1696. <BitWidth>0x7</BitWidth>
  1697. <Access>RW</Access>
  1698. <Equation multiplier="0x800" offset="0x08040000"/>
  1699. </Bit>
  1700. <Bit config="11">
  1701. <Name>WRP2A_PEND</Name>
  1702. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  1703. <BitOffset>0x10</BitOffset>
  1704. <BitWidth>0x7</BitWidth>
  1705. <Access>RW</Access>
  1706. <Equation multiplier="0x800" offset="0x08020000"/>
  1707. </Bit>
  1708. </AssignedBits>
  1709. </Field>
  1710. <Field>
  1711. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  1712. <AssignedBits>
  1713. <Bit config="0">
  1714. <Name>WRP2B_PSTRT</Name>
  1715. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1716. <BitOffset>0x0</BitOffset>
  1717. <BitWidth>0x7</BitWidth>
  1718. <Access>RW</Access>
  1719. <Equation multiplier="0x1000" offset="0x08040000"/>
  1720. </Bit>
  1721. <Bit config="10">
  1722. <Name>WRP2B_PSTRT</Name>
  1723. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1724. <BitOffset>0x0</BitOffset>
  1725. <BitWidth>0x7</BitWidth>
  1726. <Access>RW</Access>
  1727. <Equation multiplier="0x1000" offset="0x08020000"/>
  1728. </Bit>
  1729. <Bit config="1">
  1730. <Name>WRP2B_PSTRT</Name>
  1731. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1732. <BitOffset>0x0</BitOffset>
  1733. <BitWidth>0x7</BitWidth>
  1734. <Access>RW</Access>
  1735. <Equation multiplier="0x800" offset="0x08040000"/>
  1736. </Bit>
  1737. <Bit config="11">
  1738. <Name>WRP2B_PSTRT</Name>
  1739. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  1740. <BitOffset>0x0</BitOffset>
  1741. <BitWidth>0x7</BitWidth>
  1742. <Access>RW</Access>
  1743. <Equation multiplier="0x800" offset="0x08020000"/>
  1744. </Bit>
  1745. <Bit config="0">
  1746. <Name>WRP2B_PEND</Name>
  1747. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1748. <BitOffset>0x10</BitOffset>
  1749. <BitWidth>0x7</BitWidth>
  1750. <Access>RW</Access>
  1751. <Equation multiplier="0x1000" offset="0x08040000"/>
  1752. </Bit>
  1753. <Bit config="10">
  1754. <Name>WRP2B_PEND</Name>
  1755. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1756. <BitOffset>0x10</BitOffset>
  1757. <BitWidth>0x7</BitWidth>
  1758. <Access>RW</Access>
  1759. <Equation multiplier="0x1000" offset="0x08020000"/>
  1760. </Bit>
  1761. <Bit config="1">
  1762. <Name>WRP2B_PEND</Name>
  1763. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1764. <BitOffset>0x10</BitOffset>
  1765. <BitWidth>0x7</BitWidth>
  1766. <Access>RW</Access>
  1767. <Equation multiplier="0x800" offset="0x08040000"/>
  1768. </Bit>
  1769. <Bit config="11">
  1770. <Name>WRP2B_PEND</Name>
  1771. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  1772. <BitOffset>0x10</BitOffset>
  1773. <BitWidth>0x7</BitWidth>
  1774. <Access>RW</Access>
  1775. <Equation multiplier="0x800" offset="0x08020000"/>
  1776. </Bit>
  1777. </AssignedBits>
  1778. </Field>
  1779. </Category>
  1780. </Bank>
  1781. </Configuration>
  1782. <Configuration config="2,3,12,13">
  1783. <Bank interface="JTAG_SWD">
  1784. <Parameters address="0x50022040" name="Bank 1" size="0x20"/>
  1785. <Category>
  1786. <Name>Read Out Protection</Name>
  1787. <Field>
  1788. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  1789. <AssignedBits>
  1790. <Bit>
  1791. <Name>RDP</Name>
  1792. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  1793. <BitOffset>0x0</BitOffset>
  1794. <BitWidth>0x8</BitWidth>
  1795. <Access>RW</Access>
  1796. <Values>
  1797. <Val value="0xAA">Level 0, no protection</Val>
  1798. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  1799. <Val value="0xDC">Level 1, read protection of memories</Val>
  1800. <Val value="0xCC">Level 2, chip protection</Val>
  1801. </Values>
  1802. </Bit>
  1803. </AssignedBits>
  1804. </Field>
  1805. </Category>
  1806. <Category>
  1807. <Name>BOR Level</Name>
  1808. <Field>
  1809. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  1810. <AssignedBits>
  1811. <Bit>
  1812. <Name>BOR_LEV</Name>
  1813. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  1814. <BitOffset>0x8</BitOffset>
  1815. <BitWidth>0x3</BitWidth>
  1816. <Access>RW</Access>
  1817. <Values>
  1818. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  1819. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  1820. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  1821. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  1822. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  1823. </Values>
  1824. </Bit>
  1825. </AssignedBits>
  1826. </Field>
  1827. </Category>
  1828. <Category>
  1829. <Name>User Configuration</Name>
  1830. <Field>
  1831. <Parameters address="0x50022040" name="FLASH_OPTR" size="0x4"/>
  1832. <AssignedBits>
  1833. <Bit>
  1834. <Name>nRST_STOP</Name>
  1835. <Description/>
  1836. <BitOffset>0xC</BitOffset>
  1837. <BitWidth>0x1</BitWidth>
  1838. <Access>RW</Access>
  1839. <Values>
  1840. <Val value="0x0">Reset generated when entering Stop mode</Val>
  1841. <Val value="0x1">No reset generated when entering Stop mode</Val>
  1842. </Values>
  1843. </Bit>
  1844. <Bit>
  1845. <Name>nRST_STDBY</Name>
  1846. <Description/>
  1847. <BitOffset>0xD</BitOffset>
  1848. <BitWidth>0x1</BitWidth>
  1849. <Access>RW</Access>
  1850. <Values>
  1851. <Val value="0x0">Reset generated when entering Standby mode</Val>
  1852. <Val value="0x1">No reset generated when entering Standby mode</Val>
  1853. </Values>
  1854. </Bit>
  1855. <Bit>
  1856. <Name>nRST_SHDW</Name>
  1857. <Description/>
  1858. <BitOffset>0xE</BitOffset>
  1859. <BitWidth>0x1</BitWidth>
  1860. <Access>RW</Access>
  1861. <Values>
  1862. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  1863. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  1864. </Values>
  1865. </Bit>
  1866. <Bit>
  1867. <Name>IWDG_SW</Name>
  1868. <Description/>
  1869. <BitOffset>0x10</BitOffset>
  1870. <BitWidth>0x1</BitWidth>
  1871. <Access>RW</Access>
  1872. <Values>
  1873. <Val value="0x0">Hardware independant watchdog</Val>
  1874. <Val value="0x1">Software independant watchdog</Val>
  1875. </Values>
  1876. </Bit>
  1877. <Bit>
  1878. <Name>IWDG_STOP</Name>
  1879. <Description/>
  1880. <BitOffset>0x11</BitOffset>
  1881. <BitWidth>0x1</BitWidth>
  1882. <Access>RW</Access>
  1883. <Values>
  1884. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  1885. <Val value="0x1">IWDG counter active in stop mode</Val>
  1886. </Values>
  1887. </Bit>
  1888. <Bit>
  1889. <Name>IWDG_STDBY</Name>
  1890. <Description/>
  1891. <BitOffset>0x12</BitOffset>
  1892. <BitWidth>0x1</BitWidth>
  1893. <Access>RW</Access>
  1894. <Values>
  1895. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  1896. <Val value="0x1">IWDG counter active in standby mode</Val>
  1897. </Values>
  1898. </Bit>
  1899. <Bit>
  1900. <Name>WWDG_SW</Name>
  1901. <Description/>
  1902. <BitOffset>0x13</BitOffset>
  1903. <BitWidth>0x1</BitWidth>
  1904. <Access>RW</Access>
  1905. <Values>
  1906. <Val value="0x0">Hardware window watchdog</Val>
  1907. <Val value="0x1">Software window watchdog</Val>
  1908. </Values>
  1909. </Bit>
  1910. <Bit>
  1911. <Name>SWAP_BANK</Name>
  1912. <Description/>
  1913. <BitOffset>0x14</BitOffset>
  1914. <BitWidth>0x1</BitWidth>
  1915. <Access>RW</Access>
  1916. <Values>
  1917. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  1918. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  1919. </Values>
  1920. </Bit>
  1921. <Bit>
  1922. <Name>DB256</Name>
  1923. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  1924. <BitOffset>0x15</BitOffset>
  1925. <BitWidth>0x1</BitWidth>
  1926. <Access>RW</Access>
  1927. <Values>
  1928. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  1929. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  1930. </Values>
  1931. </Bit>
  1932. <Bit>
  1933. <Name>DBANK</Name>
  1934. <Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
  1935. <BitOffset>0x16</BitOffset>
  1936. <BitWidth>0x1</BitWidth>
  1937. <Access>RW</Access>
  1938. <Values>
  1939. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  1940. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  1941. </Values>
  1942. </Bit>
  1943. <Bit>
  1944. <Name>SRAM2_PE</Name>
  1945. <Description>SRAM2 parity check enable</Description>
  1946. <BitOffset>0x18</BitOffset>
  1947. <BitWidth>0x1</BitWidth>
  1948. <Access>RW</Access>
  1949. <Values>
  1950. <Val value="0x0">SRAM2 parity check enable</Val>
  1951. <Val value="0x1">SRAM2 parity check disable</Val>
  1952. </Values>
  1953. </Bit>
  1954. <Bit>
  1955. <Name>SRAM2_RST</Name>
  1956. <Description>SRAM2 Erase when system reset</Description>
  1957. <BitOffset>0x19</BitOffset>
  1958. <BitWidth>0x1</BitWidth>
  1959. <Access>RW</Access>
  1960. <Values>
  1961. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  1962. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  1963. </Values>
  1964. </Bit>
  1965. <Bit>
  1966. <Name>nSWBOOT0</Name>
  1967. <Description>Software BOOT0</Description>
  1968. <BitOffset>0x1A</BitOffset>
  1969. <BitWidth>0x1</BitWidth>
  1970. <Access>RW</Access>
  1971. <Values>
  1972. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  1973. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  1974. </Values>
  1975. </Bit>
  1976. <Bit>
  1977. <Name>nBOOT0</Name>
  1978. <Description>nBOOT0 option bit</Description>
  1979. <BitOffset>0x1B</BitOffset>
  1980. <BitWidth>0x1</BitWidth>
  1981. <Access>RW</Access>
  1982. <Values>
  1983. <Val value="0x0">nBOOT0 = 0</Val>
  1984. <Val value="0x1">nBOOT0 = 1</Val>
  1985. </Values>
  1986. </Bit>
  1987. <Bit>
  1988. <Name>PA15_PUPEN</Name>
  1989. <Description>PA15 pull-up enable</Description>
  1990. <BitOffset>0x1C</BitOffset>
  1991. <BitWidth>0x1</BitWidth>
  1992. <Access>RW</Access>
  1993. <Values>
  1994. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  1995. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  1996. </Values>
  1997. </Bit>
  1998. <Bit>
  1999. <Name>TZEN</Name>
  2000. <Description>Global TrustZone security enable</Description>
  2001. <BitOffset>0x1F</BitOffset>
  2002. <BitWidth>0x1</BitWidth>
  2003. <Access>RW</Access>
  2004. <Values>
  2005. <Val value="0x0">Global TrustZone security disabled</Val>
  2006. <Val value="0x1">Global TrustZone security enabled</Val>
  2007. </Values>
  2008. </Bit>
  2009. </AssignedBits>
  2010. </Field>
  2011. <Field>
  2012. <Parameters address="0x50022054" name="FLASH_SECWM2R1" size="0x4"/>
  2013. <AssignedBits>
  2014. <Bit>
  2015. <Name>HDP1EN</Name>
  2016. <Description>Hide protection first area enable</Description>
  2017. <BitOffset>0x1F</BitOffset>
  2018. <BitWidth>0x1</BitWidth>
  2019. <Access>RW</Access>
  2020. <Values>
  2021. <Val value="0x0">No HDP area 1</Val>
  2022. <Val value="0x1">HDP first area is enabled</Val>
  2023. </Values>
  2024. </Bit>
  2025. <Bit config="2,12">
  2026. <Name>HDP1_PEND</Name>
  2027. <Description>End page of first hide protection area</Description>
  2028. <BitOffset>0x10</BitOffset>
  2029. <BitWidth>0x7</BitWidth>
  2030. <Access>RW</Access>
  2031. <Equation multiplier="0x4" offset="0x08000000"/>
  2032. </Bit>
  2033. <Bit config="3,13">
  2034. <Name>HDP1_PEND</Name>
  2035. <Description>End page of first hide protection area</Description>
  2036. <BitOffset>0x10</BitOffset>
  2037. <BitWidth>0x7</BitWidth>
  2038. <Access>RW</Access>
  2039. <Equation multiplier="0x2" offset="0x08000000"/>
  2040. </Bit>
  2041. </AssignedBits>
  2042. </Field>
  2043. <Field>
  2044. <Parameters address="0x50022064" name="FLASH_SECWM2R2" size="0x4"/>
  2045. <AssignedBits>
  2046. <Bit>
  2047. <Name>HDP2EN</Name>
  2048. <Description>Hide protection second area enable</Description>
  2049. <BitOffset>0x1F</BitOffset>
  2050. <BitWidth>0x1</BitWidth>
  2051. <Access>RW</Access>
  2052. <Values>
  2053. <Val value="0x0">No HDP area 2</Val>
  2054. <Val value="0x1">HDP second area is enabled</Val>
  2055. </Values>
  2056. </Bit>
  2057. <Bit config="2,12">
  2058. <Name>HDP2_PEND</Name>
  2059. <Description>End page of second hide protection area</Description>
  2060. <BitOffset>0x10</BitOffset>
  2061. <BitWidth>0x7</BitWidth>
  2062. <Access>RW</Access>
  2063. <Equation multiplier="0x4" offset="0x08000000"/>
  2064. </Bit>
  2065. <Bit config="3,13">
  2066. <Name>HDP2_PEND</Name>
  2067. <Description>End page of second hide protection area</Description>
  2068. <BitOffset>0x10</BitOffset>
  2069. <BitWidth>0x7</BitWidth>
  2070. <Access>RW</Access>
  2071. <Equation multiplier="0x2" offset="0x08000000"/>
  2072. </Bit>
  2073. </AssignedBits>
  2074. </Field>
  2075. <Field>
  2076. <Parameters address="0x50022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2077. <AssignedBits>
  2078. <Bit>
  2079. <Name>NSBOOTADD0</Name>
  2080. <Description>Non-secure Boot base address 0</Description>
  2081. <BitOffset>0x7</BitOffset>
  2082. <BitWidth>0x19</BitWidth>
  2083. <Access>RW</Access>
  2084. <Equation multiplier="0x80" offset="0x0000000"/>
  2085. </Bit>
  2086. </AssignedBits>
  2087. </Field>
  2088. <Field>
  2089. <Parameters address="0x50022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2090. <AssignedBits>
  2091. <Bit>
  2092. <Name>NSBOOTADD1</Name>
  2093. <Description>Non-secure Boot base address 1</Description>
  2094. <BitOffset>0x7</BitOffset>
  2095. <BitWidth>0x19</BitWidth>
  2096. <Access>RW</Access>
  2097. <Equation multiplier="0x80" offset="0x0000000"/>
  2098. </Bit>
  2099. </AssignedBits>
  2100. </Field>
  2101. <Field>
  2102. <Parameters address="0x5002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  2103. <AssignedBits>
  2104. <Bit>
  2105. <Name>SECBOOTADD0</Name>
  2106. <Description>Secure boot base address 0</Description>
  2107. <BitOffset>0x7</BitOffset>
  2108. <BitWidth>0x19</BitWidth>
  2109. <Access>RW</Access>
  2110. <Equation multiplier="0x80" offset="0x0000000"/>
  2111. </Bit>
  2112. </AssignedBits>
  2113. </Field>
  2114. <Field>
  2115. <Parameters address="0x5002204C" name="BOOT_LOCK" size="0x4"/>
  2116. <AssignedBits>
  2117. <Bit>
  2118. <Name>BOOT_LOCK</Name>
  2119. <Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
  2120. <BitOffset>0x0</BitOffset>
  2121. <BitWidth>0x1</BitWidth>
  2122. <Access>RW</Access>
  2123. <Values>
  2124. <Val value="0x0">Boot based on the pad/option bit configuration</Val>
  2125. <Val value="0x1">Boot forced from base address memory</Val>
  2126. </Values>
  2127. </Bit>
  2128. </AssignedBits>
  2129. </Field>
  2130. </Category>
  2131. <Category>
  2132. <Name>Secure Area 1</Name>
  2133. <Field>
  2134. <Parameters address="0x50022050" name="FLASH_SECWM1R1" size="0x4"/>
  2135. <AssignedBits>
  2136. <Bit config="2,12">
  2137. <Name>SECWM1_PSTRT</Name>
  2138. <Description>Start page of first secure area</Description>
  2139. <BitOffset>0x0</BitOffset>
  2140. <BitWidth>0x7</BitWidth>
  2141. <Access>RW</Access>
  2142. <Equation multiplier="0x1000" offset="0x08000000"/>
  2143. </Bit>
  2144. <Bit config="3,13">
  2145. <Name>SECWM1_PSTRT</Name>
  2146. <Description>Start page of first secure area</Description>
  2147. <BitOffset>0x0</BitOffset>
  2148. <BitWidth>0x7</BitWidth>
  2149. <Access>RW</Access>
  2150. <Equation multiplier="0x800" offset="0x08000000"/>
  2151. </Bit>
  2152. <Bit config="2,12">
  2153. <Name>SECWM1_PEND</Name>
  2154. <Description>End page of first secure area</Description>
  2155. <BitOffset>0x10</BitOffset>
  2156. <BitWidth>0x7</BitWidth>
  2157. <Access>RW</Access>
  2158. <Equation multiplier="0x1000" offset="0x08000000"/>
  2159. </Bit>
  2160. <Bit config="3,13">
  2161. <Name>SECWM1_PEND</Name>
  2162. <Description>End page of first secure area</Description>
  2163. <BitOffset>0x10</BitOffset>
  2164. <BitWidth>0x7</BitWidth>
  2165. <Access>RW</Access>
  2166. <Equation multiplier="0x800" offset="0x08000000"/>
  2167. </Bit>
  2168. </AssignedBits>
  2169. </Field>
  2170. </Category>
  2171. <!-- <Category> -->
  2172. <!-- <Name>PCROP Protection (Bank 1)</Name> -->
  2173. <!-- <Field> -->
  2174. <!-- <Parameters name="FLASH_PCROP1SR" size="0x4" address="0x50022054"/> -->
  2175. <!-- <AssignedBits> -->
  2176. <!-- <Bit config="2"> -->
  2177. <!-- <Name>PCROP1_PSTRT</Name> -->
  2178. <!-- <Description>Start page of first PCROP area</Description> -->
  2179. <!-- <BitOffset>0x0</BitOffset> -->
  2180. <!-- <BitWidth>0x7</BitWidth> -->
  2181. <!-- <Access>RW</Access> -->
  2182. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  2183. <!-- </Bit> -->
  2184. <!-- <Bit config="3"> -->
  2185. <!-- <Name>PCROP1_STRT</Name> -->
  2186. <!-- <Description>Flash Bank 1 PCROP start address</Description> -->
  2187. <!-- <BitOffset>0x0</BitOffset> -->
  2188. <!-- <BitWidth>0x7</BitWidth> -->
  2189. <!-- <Access>RW</Access> -->
  2190. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  2191. <!-- </Bit> -->
  2192. <!-- <Bit config="2"> -->
  2193. <!-- <Name>HDP1_PEND</Name> -->
  2194. <!-- <Description>End page of first hide protection area</Description> -->
  2195. <!-- <BitOffset>0x10</BitOffset> -->
  2196. <!-- <BitWidth>0x7</BitWidth> -->
  2197. <!-- <Access>RW</Access> -->
  2198. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  2199. <!-- </Bit> -->
  2200. <!-- <Bit config="3"> -->
  2201. <!-- <Name>HDP1_PEND</Name> -->
  2202. <!-- <Description>End page of first hide protection area</Description> -->
  2203. <!-- <BitOffset>0x10</BitOffset> -->
  2204. <!-- <BitWidth>0x7</BitWidth> -->
  2205. <!-- <Access>RW</Access> -->
  2206. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  2207. <!-- </Bit> -->
  2208. <!-- <Bit> -->
  2209. <!-- <Name>PCROP1EN</Name> -->
  2210. <!-- <Description>PCROP1 area enable</Description> -->
  2211. <!-- <BitOffset>0xF</BitOffset> -->
  2212. <!-- <BitWidth>0x1</BitWidth> -->
  2213. <!-- <Access>RW</Access> -->
  2214. <!-- <Values> -->
  2215. <!-- <Val value="0x0">PCROP1 area is disabled</Val> -->
  2216. <!-- <Val value="0x1">PCROP1 area is enabled</Val> -->
  2217. <!-- </Values> -->
  2218. <!-- </Bit> -->
  2219. <!-- <Bit> -->
  2220. <!-- <Name>HDP1EN</Name> -->
  2221. <!-- <Description>Hide protection first area enable</Description> -->
  2222. <!-- <BitOffset>0x1F</BitOffset> -->
  2223. <!-- <BitWidth>0x1</BitWidth> -->
  2224. <!-- <Access>RW</Access> -->
  2225. <!-- <Values> -->
  2226. <!-- <Val value="0x0">No HDP area 1</Val> -->
  2227. <!-- <Val value="0x1">HDP first area is enabled</Val> -->
  2228. <!-- </Values> -->
  2229. <!-- </Bit> -->
  2230. <!-- </AssignedBits> -->
  2231. <!-- </Field> -->
  2232. <!-- </Category> -->
  2233. <Category>
  2234. <Name>Write Protection 1</Name>
  2235. <Field>
  2236. <Parameters address="0x50022058" name="FLASH_WRP1AR" size="0x4"/>
  2237. <AssignedBits>
  2238. <Bit config="2,12">
  2239. <Name>WRP1A_PSTRT</Name>
  2240. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2241. <BitOffset>0x0</BitOffset>
  2242. <BitWidth>0x7</BitWidth>
  2243. <Access>RW</Access>
  2244. <Equation multiplier="0x1000" offset="0x08000000"/>
  2245. </Bit>
  2246. <Bit config="3,13">
  2247. <Name>WRP1A_PSTRT</Name>
  2248. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2249. <BitOffset>0x0</BitOffset>
  2250. <BitWidth>0x7</BitWidth>
  2251. <Access>RW</Access>
  2252. <Equation multiplier="0x800" offset="0x08000000"/>
  2253. </Bit>
  2254. <Bit config="2,12">
  2255. <Name>WRP1A_PEND</Name>
  2256. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2257. <BitOffset>0x10</BitOffset>
  2258. <BitWidth>0x7</BitWidth>
  2259. <Access>RW</Access>
  2260. <Equation multiplier="0x1000" offset="0x08000000"/>
  2261. </Bit>
  2262. <Bit config="3,13">
  2263. <Name>WRP1A_PEND</Name>
  2264. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2265. <BitOffset>0x10</BitOffset>
  2266. <BitWidth>0x7</BitWidth>
  2267. <Access>RW</Access>
  2268. <Equation multiplier="0x800" offset="0x08000000"/>
  2269. </Bit>
  2270. </AssignedBits>
  2271. </Field>
  2272. <Field>
  2273. <Parameters address="0x5002205C" name="FLASH_WRP1BR" size="0x4"/>
  2274. <AssignedBits>
  2275. <Bit config="2,12">
  2276. <Name>WRP1B_PSTRT</Name>
  2277. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2278. <BitOffset>0x0</BitOffset>
  2279. <BitWidth>0x7</BitWidth>
  2280. <Access>RW</Access>
  2281. <Equation multiplier="0x1000" offset="0x08000000"/>
  2282. </Bit>
  2283. <Bit config="3,13">
  2284. <Name>WRP1B_PSTRT</Name>
  2285. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  2286. <BitOffset>0x0</BitOffset>
  2287. <BitWidth>0x7</BitWidth>
  2288. <Access>RW</Access>
  2289. <Equation multiplier="0x800" offset="0x08000000"/>
  2290. </Bit>
  2291. <Bit config="2,12">
  2292. <Name>WRP1B_PEND</Name>
  2293. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2294. <BitOffset>0x10</BitOffset>
  2295. <BitWidth>0x7</BitWidth>
  2296. <Access>RW</Access>
  2297. <Equation multiplier="0x1000" offset="0x08000000"/>
  2298. </Bit>
  2299. <Bit config="3,13">
  2300. <Name>WRP1B_PEND</Name>
  2301. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  2302. <BitOffset>0x10</BitOffset>
  2303. <BitWidth>0x7</BitWidth>
  2304. <Access>RW</Access>
  2305. <Equation multiplier="0x800" offset="0x08000000"/>
  2306. </Bit>
  2307. </AssignedBits>
  2308. </Field>
  2309. </Category>
  2310. </Bank>
  2311. <Bank interface="JTAG_SWD">
  2312. <Parameters address="0x50022060" name="Bank 2" size="0x10"/>
  2313. <Category>
  2314. <Name>Secure Area 2</Name>
  2315. <Field>
  2316. <Parameters address="0x50022060" name="FLASH_SECWM2R1" size="0x4"/>
  2317. <AssignedBits>
  2318. <Bit config="2">
  2319. <Name>SECWM2_PSTRT</Name>
  2320. <Description>Start page of second secure area</Description>
  2321. <BitOffset>0x0</BitOffset>
  2322. <BitWidth>0x7</BitWidth>
  2323. <Access>RW</Access>
  2324. <Equation multiplier="0x1000" offset="0x08040000"/>
  2325. </Bit>
  2326. <Bit config="12">
  2327. <Name>SECWM2_PSTRT</Name>
  2328. <Description>Start page of second secure area</Description>
  2329. <BitOffset>0x0</BitOffset>
  2330. <BitWidth>0x7</BitWidth>
  2331. <Access>RW</Access>
  2332. <Equation multiplier="0x1000" offset="0x08020000"/>
  2333. </Bit>
  2334. <Bit config="3">
  2335. <Name>SECWM2_PSTRT</Name>
  2336. <Description>Start page of second secure area</Description>
  2337. <BitOffset>0x0</BitOffset>
  2338. <BitWidth>0x7</BitWidth>
  2339. <Access>RW</Access>
  2340. <Equation multiplier="0x800" offset="0x08040000"/>
  2341. </Bit>
  2342. <Bit config="13">
  2343. <Name>SECWM2_PSTRT</Name>
  2344. <Description>Start page of second secure area</Description>
  2345. <BitOffset>0x0</BitOffset>
  2346. <BitWidth>0x7</BitWidth>
  2347. <Access>RW</Access>
  2348. <Equation multiplier="0x800" offset="0x08020000"/>
  2349. </Bit>
  2350. <Bit config="2">
  2351. <Name>SECWM2_PEND</Name>
  2352. <Description>End page of second secure area</Description>
  2353. <BitOffset>0x10</BitOffset>
  2354. <BitWidth>0x7</BitWidth>
  2355. <Access>RW</Access>
  2356. <Equation multiplier="0x1000" offset="0x08040000"/>
  2357. </Bit>
  2358. <Bit config="12">
  2359. <Name>SECWM2_PEND</Name>
  2360. <Description>End page of second secure area</Description>
  2361. <BitOffset>0x10</BitOffset>
  2362. <BitWidth>0x7</BitWidth>
  2363. <Access>RW</Access>
  2364. <Equation multiplier="0x1000" offset="0x08020000"/>
  2365. </Bit>
  2366. <Bit config="3">
  2367. <Name>SECWM2_PEND</Name>
  2368. <Description>End page of second secure area</Description>
  2369. <BitOffset>0x10</BitOffset>
  2370. <BitWidth>0x7</BitWidth>
  2371. <Access>RW</Access>
  2372. <Equation multiplier="0x800" offset="0x08040000"/>
  2373. </Bit>
  2374. <Bit config="13">
  2375. <Name>SECWM2_PEND</Name>
  2376. <Description>End page of second secure area</Description>
  2377. <BitOffset>0x10</BitOffset>
  2378. <BitWidth>0x7</BitWidth>
  2379. <Access>RW</Access>
  2380. <Equation multiplier="0x800" offset="0x08020000"/>
  2381. </Bit>
  2382. </AssignedBits>
  2383. </Field>
  2384. </Category>
  2385. <!-- <Category> -->
  2386. <!-- <Name>PCROP Protection (Bank 2)</Name> -->
  2387. <!-- <Field> -->
  2388. <!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x50022064"/> -->
  2389. <!-- <AssignedBits> -->
  2390. <!-- <Bit config="2"> -->
  2391. <!-- <Name>PCROP2_PSTRT</Name> -->
  2392. <!-- <Description>Start page of first PCROP area</Description> -->
  2393. <!-- <BitOffset>0x0</BitOffset> -->
  2394. <!-- <BitWidth>0x7</BitWidth> -->
  2395. <!-- <Access>RW</Access> -->
  2396. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  2397. <!-- </Bit> -->
  2398. <!-- <Bit config="3"> -->
  2399. <!-- <Name>PCROP2_STRT</Name> -->
  2400. <!-- <Description>Flash Bank 2 PCROP start address</Description> -->
  2401. <!-- <BitOffset>0x0</BitOffset> -->
  2402. <!-- <BitWidth>0x7</BitWidth> -->
  2403. <!-- <Access>RW</Access> -->
  2404. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  2405. <!-- </Bit> -->
  2406. <!-- <Bit config="2"> -->
  2407. <!-- <Name>HDP2_PEND</Name> -->
  2408. <!-- <Description>End page of second hide protection area</Description> -->
  2409. <!-- <BitOffset>0x10</BitOffset> -->
  2410. <!-- <BitWidth>0x7</BitWidth> -->
  2411. <!-- <Access>RW</Access> -->
  2412. <!-- <Equation multiplier="0x4" offset="0x08000000"/> -->
  2413. <!-- </Bit> -->
  2414. <!-- <Bit config="3"> -->
  2415. <!-- <Name>HDP2_PEND</Name> -->
  2416. <!-- <Description>End page of second hide protection area</Description> -->
  2417. <!-- <BitOffset>0x10</BitOffset> -->
  2418. <!-- <BitWidth>0x7</BitWidth> -->
  2419. <!-- <Access>RW</Access> -->
  2420. <!-- <Equation multiplier="0x2" offset="0x08000000"/> -->
  2421. <!-- </Bit> -->
  2422. <!-- <Bit config="2,3"> -->
  2423. <!-- <Name>PCROP2EN</Name> -->
  2424. <!-- <Description>PCROP2 area enable</Description> -->
  2425. <!-- <BitOffset>0xF</BitOffset> -->
  2426. <!-- <BitWidth>0x1</BitWidth> -->
  2427. <!-- <Access>RW</Access> -->
  2428. <!-- <Values> -->
  2429. <!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
  2430. <!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
  2431. <!-- </Values> -->
  2432. <!-- </Bit> -->
  2433. <!-- <Bit config="2,3"> -->
  2434. <!-- <Name>HDP2EN</Name> -->
  2435. <!-- <Description>Hide protection second area enable</Description> -->
  2436. <!-- <BitOffset>0x1F</BitOffset> -->
  2437. <!-- <BitWidth>0x1</BitWidth> -->
  2438. <!-- <Access>RW</Access> -->
  2439. <!-- <Values> -->
  2440. <!-- <Val value="0x0">No HDP area 2</Val> -->
  2441. <!-- <Val value="0x1">HDP second area is enabled</Val> -->
  2442. <!-- </Values> -->
  2443. <!-- </Bit> -->
  2444. <!-- </AssignedBits> -->
  2445. <!-- </Field> -->
  2446. <!-- </Category> -->
  2447. <Category>
  2448. <Name>Write Protection 2</Name>
  2449. <Field>
  2450. <Parameters address="0x50022068" name="FLASH_WRP2AR" size="0x4"/>
  2451. <AssignedBits>
  2452. <Bit config="2">
  2453. <Name>WRP2A_PSTRT</Name>
  2454. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2455. <BitOffset>0x0</BitOffset>
  2456. <BitWidth>0x7</BitWidth>
  2457. <Access>RW</Access>
  2458. <Equation multiplier="0x1000" offset="0x08040000"/>
  2459. </Bit>
  2460. <Bit config="12">
  2461. <Name>WRP2A_PSTRT</Name>
  2462. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2463. <BitOffset>0x0</BitOffset>
  2464. <BitWidth>0x7</BitWidth>
  2465. <Access>RW</Access>
  2466. <Equation multiplier="0x1000" offset="0x08020000"/>
  2467. </Bit>
  2468. <Bit config="3">
  2469. <Name>WRP2A_PSTRT</Name>
  2470. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2471. <BitOffset>0x0</BitOffset>
  2472. <BitWidth>0x7</BitWidth>
  2473. <Access>RW</Access>
  2474. <Equation multiplier="0x800" offset="0x08040000"/>
  2475. </Bit>
  2476. <Bit config="13">
  2477. <Name>WRP2A_PSTRT</Name>
  2478. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  2479. <BitOffset>0x0</BitOffset>
  2480. <BitWidth>0x7</BitWidth>
  2481. <Access>RW</Access>
  2482. <Equation multiplier="0x800" offset="0x08020000"/>
  2483. </Bit>
  2484. <Bit config="2">
  2485. <Name>WRP2A_PEND</Name>
  2486. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2487. <BitOffset>0x10</BitOffset>
  2488. <BitWidth>0x7</BitWidth>
  2489. <Access>RW</Access>
  2490. <Equation multiplier="0x1000" offset="0x08040000"/>
  2491. </Bit>
  2492. <Bit config="12">
  2493. <Name>WRP2A_PEND</Name>
  2494. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2495. <BitOffset>0x10</BitOffset>
  2496. <BitWidth>0x7</BitWidth>
  2497. <Access>RW</Access>
  2498. <Equation multiplier="0x1000" offset="0x08020000"/>
  2499. </Bit>
  2500. <Bit config="3">
  2501. <Name>WRP2A_PEND</Name>
  2502. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2503. <BitOffset>0x10</BitOffset>
  2504. <BitWidth>0x7</BitWidth>
  2505. <Access>RW</Access>
  2506. <Equation multiplier="0x800" offset="0x08040000"/>
  2507. </Bit>
  2508. <Bit config="13">
  2509. <Name>WRP2A_PEND</Name>
  2510. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  2511. <BitOffset>0x10</BitOffset>
  2512. <BitWidth>0x7</BitWidth>
  2513. <Access>RW</Access>
  2514. <Equation multiplier="0x800" offset="0x08020000"/>
  2515. </Bit>
  2516. </AssignedBits>
  2517. </Field>
  2518. <Field>
  2519. <Parameters address="0x5002206C" name="FLASH_WRP2BR" size="0x4"/>
  2520. <AssignedBits>
  2521. <Bit config="2">
  2522. <Name>WRP2B_PSTRT</Name>
  2523. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2524. <BitOffset>0x0</BitOffset>
  2525. <BitWidth>0x7</BitWidth>
  2526. <Access>RW</Access>
  2527. <Equation multiplier="0x1000" offset="0x08040000"/>
  2528. </Bit>
  2529. <Bit config="12">
  2530. <Name>WRP2B_PSTRT</Name>
  2531. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2532. <BitOffset>0x0</BitOffset>
  2533. <BitWidth>0x7</BitWidth>
  2534. <Access>RW</Access>
  2535. <Equation multiplier="0x1000" offset="0x08020000"/>
  2536. </Bit>
  2537. <Bit config="3">
  2538. <Name>WRP2B_PSTRT</Name>
  2539. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2540. <BitOffset>0x0</BitOffset>
  2541. <BitWidth>0x7</BitWidth>
  2542. <Access>RW</Access>
  2543. <Equation multiplier="0x800" offset="0x08040000"/>
  2544. </Bit>
  2545. <Bit config="13">
  2546. <Name>WRP2B_PSTRT</Name>
  2547. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  2548. <BitOffset>0x0</BitOffset>
  2549. <BitWidth>0x7</BitWidth>
  2550. <Access>RW</Access>
  2551. <Equation multiplier="0x800" offset="0x08020000"/>
  2552. </Bit>
  2553. <Bit config="2">
  2554. <Name>WRP2B_PEND</Name>
  2555. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2556. <BitOffset>0x10</BitOffset>
  2557. <BitWidth>0x7</BitWidth>
  2558. <Access>RW</Access>
  2559. <Equation multiplier="0x1000" offset="0x08040000"/>
  2560. </Bit>
  2561. <Bit config="12">
  2562. <Name>WRP2B_PEND</Name>
  2563. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2564. <BitOffset>0x10</BitOffset>
  2565. <BitWidth>0x7</BitWidth>
  2566. <Access>RW</Access>
  2567. <Equation multiplier="0x1000" offset="0x08020000"/>
  2568. </Bit>
  2569. <Bit config="3">
  2570. <Name>WRP2B_PEND</Name>
  2571. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2572. <BitOffset>0x10</BitOffset>
  2573. <BitWidth>0x7</BitWidth>
  2574. <Access>RW</Access>
  2575. <Equation multiplier="0x800" offset="0x08040000"/>
  2576. </Bit>
  2577. <Bit config="13">
  2578. <Name>WRP2B_PEND</Name>
  2579. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  2580. <BitOffset>0x10</BitOffset>
  2581. <BitWidth>0x7</BitWidth>
  2582. <Access>RW</Access>
  2583. <Equation multiplier="0x800" offset="0x08020000"/>
  2584. </Bit>
  2585. </AssignedBits>
  2586. </Field>
  2587. </Category>
  2588. </Bank>
  2589. </Configuration>
  2590. <Bank interface="Bootloader">
  2591. <Parameters address="0x40022040" name="Bank 1" size="0x30"/>
  2592. <Category>
  2593. <Name>Read Out Protection</Name>
  2594. <Field>
  2595. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2596. <AssignedBits>
  2597. <Bit>
  2598. <Name>RDP</Name>
  2599. <Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
  2600. <BitOffset>0x0</BitOffset>
  2601. <BitWidth>0x8</BitWidth>
  2602. <Access>RW</Access>
  2603. <Values>
  2604. <Val value="0xAA">Level 0, no protection</Val>
  2605. <Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
  2606. <Val value="0xDC">Level 1, read protection of memories</Val>
  2607. <Val value="0xCC">Level 2, chip protection</Val>
  2608. </Values>
  2609. </Bit>
  2610. </AssignedBits>
  2611. </Field>
  2612. </Category>
  2613. <Category>
  2614. <Name>BOR Level</Name>
  2615. <Field>
  2616. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2617. <AssignedBits>
  2618. <Bit>
  2619. <Name>BOR_LEV</Name>
  2620. <Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
  2621. <BitOffset>0x8</BitOffset>
  2622. <BitWidth>0x3</BitWidth>
  2623. <Access>RW</Access>
  2624. <Values>
  2625. <Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
  2626. <Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
  2627. <Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
  2628. <Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
  2629. <Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
  2630. </Values>
  2631. </Bit>
  2632. </AssignedBits>
  2633. </Field>
  2634. </Category>
  2635. <Category>
  2636. <Name>User Configuration</Name>
  2637. <Field>
  2638. <Parameters address="0x40022040" name="FLASH_OPTR" size="0x4"/>
  2639. <AssignedBits>
  2640. <Bit>
  2641. <Name>nRST_STOP</Name>
  2642. <Description/>
  2643. <BitOffset>0xC</BitOffset>
  2644. <BitWidth>0x1</BitWidth>
  2645. <Access>RW</Access>
  2646. <Values>
  2647. <Val value="0x0">Reset generated when entering Stop mode</Val>
  2648. <Val value="0x1">No reset generated when entering Stop mode</Val>
  2649. </Values>
  2650. </Bit>
  2651. <Bit>
  2652. <Name>nRST_STDBY</Name>
  2653. <Description/>
  2654. <BitOffset>0xD</BitOffset>
  2655. <BitWidth>0x1</BitWidth>
  2656. <Access>RW</Access>
  2657. <Values>
  2658. <Val value="0x0">Reset generated when entering Standby mode</Val>
  2659. <Val value="0x1">No reset generated when entering Standby mode</Val>
  2660. </Values>
  2661. </Bit>
  2662. <Bit>
  2663. <Name>nRST_SHDW</Name>
  2664. <Description/>
  2665. <BitOffset>0xE</BitOffset>
  2666. <BitWidth>0x1</BitWidth>
  2667. <Access>RW</Access>
  2668. <Values>
  2669. <Val value="0x0">Reset generated when entering the Shutdown mode</Val>
  2670. <Val value="0x1">No reset generated when entering the Shutdown mode</Val>
  2671. </Values>
  2672. </Bit>
  2673. <Bit>
  2674. <Name>IWDG_SW</Name>
  2675. <Description/>
  2676. <BitOffset>0x10</BitOffset>
  2677. <BitWidth>0x1</BitWidth>
  2678. <Access>RW</Access>
  2679. <Values>
  2680. <Val value="0x0">Hardware independant watchdog</Val>
  2681. <Val value="0x1">Software independant watchdog</Val>
  2682. </Values>
  2683. </Bit>
  2684. <Bit>
  2685. <Name>IWDG_STOP</Name>
  2686. <Description/>
  2687. <BitOffset>0x11</BitOffset>
  2688. <BitWidth>0x1</BitWidth>
  2689. <Access>RW</Access>
  2690. <Values>
  2691. <Val value="0x0">Freeze IWDG counter in stop mode</Val>
  2692. <Val value="0x1">IWDG counter active in stop mode</Val>
  2693. </Values>
  2694. </Bit>
  2695. <Bit>
  2696. <Name>IWDG_STDBY</Name>
  2697. <Description/>
  2698. <BitOffset>0x12</BitOffset>
  2699. <BitWidth>0x1</BitWidth>
  2700. <Access>RW</Access>
  2701. <Values>
  2702. <Val value="0x0">Freeze IWDG counter in standby mode</Val>
  2703. <Val value="0x1">IWDG counter active in standby mode</Val>
  2704. </Values>
  2705. </Bit>
  2706. <Bit>
  2707. <Name>WWDG_SW</Name>
  2708. <Description/>
  2709. <BitOffset>0x13</BitOffset>
  2710. <BitWidth>0x1</BitWidth>
  2711. <Access>RW</Access>
  2712. <Values>
  2713. <Val value="0x0">Hardware window watchdog</Val>
  2714. <Val value="0x1">Software window watchdog</Val>
  2715. </Values>
  2716. </Bit>
  2717. <Bit>
  2718. <Name>SWAP_BANK</Name>
  2719. <Description/>
  2720. <BitOffset>0x14</BitOffset>
  2721. <BitWidth>0x1</BitWidth>
  2722. <Access>RW</Access>
  2723. <Values>
  2724. <Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
  2725. <Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
  2726. </Values>
  2727. </Bit>
  2728. <Bit>
  2729. <Name>DB256</Name>
  2730. <Description>Dual-Bank on 256 Kb Flash memory devices</Description>
  2731. <BitOffset>0x15</BitOffset>
  2732. <BitWidth>0x1</BitWidth>
  2733. <Access>RW</Access>
  2734. <Values>
  2735. <Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
  2736. <Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
  2737. </Values>
  2738. </Bit>
  2739. <Bit>
  2740. <Name>DBANK</Name>
  2741. <Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
  2742. <BitOffset>0x16</BitOffset>
  2743. <BitWidth>0x1</BitWidth>
  2744. <Access>RW</Access>
  2745. <Values>
  2746. <Val value="0x0">Single bank mode with 128 bits data read width</Val>
  2747. <Val value="0x1">Dual bank mode with 64 bits data</Val>
  2748. </Values>
  2749. </Bit>
  2750. <Bit>
  2751. <Name>SRAM2_PE</Name>
  2752. <Description>SRAM2 parity check enable</Description>
  2753. <BitOffset>0x18</BitOffset>
  2754. <BitWidth>0x1</BitWidth>
  2755. <Access>RW</Access>
  2756. <Values>
  2757. <Val value="0x0">SRAM2 parity check enable</Val>
  2758. <Val value="0x1">SRAM2 parity check disable</Val>
  2759. </Values>
  2760. </Bit>
  2761. <Bit>
  2762. <Name>SRAM2_RST</Name>
  2763. <Description>SRAM2 Erase when system reset</Description>
  2764. <BitOffset>0x19</BitOffset>
  2765. <BitWidth>0x1</BitWidth>
  2766. <Access>RW</Access>
  2767. <Values>
  2768. <Val value="0x0">SRAM2 erased when a system reset occurs</Val>
  2769. <Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
  2770. </Values>
  2771. </Bit>
  2772. <Bit>
  2773. <Name>nSWBOOT0</Name>
  2774. <Description>Software BOOT0</Description>
  2775. <BitOffset>0x1A</BitOffset>
  2776. <BitWidth>0x1</BitWidth>
  2777. <Access>RW</Access>
  2778. <Values>
  2779. <Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
  2780. <Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
  2781. </Values>
  2782. </Bit>
  2783. <Bit>
  2784. <Name>nBOOT0</Name>
  2785. <Description>nBOOT0 option bit</Description>
  2786. <BitOffset>0x1B</BitOffset>
  2787. <BitWidth>0x1</BitWidth>
  2788. <Access>RW</Access>
  2789. <Values>
  2790. <Val value="0x0">nBOOT0 = 0</Val>
  2791. <Val value="0x1">nBOOT0 = 1</Val>
  2792. </Values>
  2793. </Bit>
  2794. <Bit>
  2795. <Name>PA15_PUPEN</Name>
  2796. <Description>PA15 pull-up enable</Description>
  2797. <BitOffset>0x1C</BitOffset>
  2798. <BitWidth>0x1</BitWidth>
  2799. <Access>RW</Access>
  2800. <Values>
  2801. <Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
  2802. <Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
  2803. </Values>
  2804. </Bit>
  2805. <Bit>
  2806. <Name>TZEN</Name>
  2807. <Description>Global TrustZone security enable</Description>
  2808. <BitOffset>0x1F</BitOffset>
  2809. <BitWidth>0x1</BitWidth>
  2810. <Access>RW</Access>
  2811. <Values>
  2812. <Val value="0x0">Global TrustZone security disabled</Val>
  2813. <Val value="0x1">Global TrustZone security enabled</Val>
  2814. </Values>
  2815. </Bit>
  2816. </AssignedBits>
  2817. </Field>
  2818. <Field>
  2819. <Parameters address="0x40022054" name="FLASH_SECWM2R1" size="0x4"/>
  2820. <AssignedBits>
  2821. <Bit config="6,7,8,9">
  2822. <Name>HDP1EN</Name>
  2823. <Description>Hide protection first area enable</Description>
  2824. <BitOffset>0x1F</BitOffset>
  2825. <BitWidth>0x1</BitWidth>
  2826. <Access>RW</Access>
  2827. <Values>
  2828. <Val value="0x0">No HDP area 1</Val>
  2829. <Val value="0x1">HDP first area is enabled</Val>
  2830. </Values>
  2831. </Bit>
  2832. <Bit config="6,8">
  2833. <Name>HDP1_PEND</Name>
  2834. <Description>End page of first hide protection area</Description>
  2835. <BitOffset>0x10</BitOffset>
  2836. <BitWidth>0x7</BitWidth>
  2837. <Access>RW</Access>
  2838. <Equation multiplier="0x4" offset="0x08000000"/>
  2839. </Bit>
  2840. <Bit config="7,9">
  2841. <Name>HDP1_PEND</Name>
  2842. <Description>End page of first hide protection area</Description>
  2843. <BitOffset>0x10</BitOffset>
  2844. <BitWidth>0x7</BitWidth>
  2845. <Access>RW</Access>
  2846. <Equation multiplier="0x2" offset="0x08000000"/>
  2847. </Bit>
  2848. </AssignedBits>
  2849. </Field>
  2850. <Field>
  2851. <Parameters address="0x40022064" name="FLASH_SECWM2R2" size="0x4"/>
  2852. <AssignedBits>
  2853. <Bit config="6,7,8,9">
  2854. <Name>HDP2EN</Name>
  2855. <Description>Hide protection second area enable</Description>
  2856. <BitOffset>0x1F</BitOffset>
  2857. <BitWidth>0x1</BitWidth>
  2858. <Access>RW</Access>
  2859. <Values>
  2860. <Val value="0x0">No HDP area 2</Val>
  2861. <Val value="0x1">HDP second area is enabled</Val>
  2862. </Values>
  2863. </Bit>
  2864. <Bit config="6,8">
  2865. <Name>HDP2_PEND</Name>
  2866. <Description>End page of second hide protection area</Description>
  2867. <BitOffset>0x10</BitOffset>
  2868. <BitWidth>0x7</BitWidth>
  2869. <Access>RW</Access>
  2870. <Equation multiplier="0x4" offset="0x08000000"/>
  2871. </Bit>
  2872. <Bit config="7,9">
  2873. <Name>HDP2_PEND</Name>
  2874. <Description>End page of second hide protection area</Description>
  2875. <BitOffset>0x10</BitOffset>
  2876. <BitWidth>0x7</BitWidth>
  2877. <Access>RW</Access>
  2878. <Equation multiplier="0x2" offset="0x08000000"/>
  2879. </Bit>
  2880. </AssignedBits>
  2881. </Field>
  2882. <Field>
  2883. <Parameters address="0x40022044" name="FLASH_NSBOOTADD0" size="0x4"/>
  2884. <AssignedBits>
  2885. <Bit>
  2886. <Name>NSBOOTADD0</Name>
  2887. <Description>Non-secure Boot base address 0</Description>
  2888. <BitOffset>0x7</BitOffset>
  2889. <BitWidth>0x19</BitWidth>
  2890. <Access>RW</Access>
  2891. <Equation multiplier="0x80" offset="0x0000000"/>
  2892. </Bit>
  2893. </AssignedBits>
  2894. </Field>
  2895. <Field>
  2896. <Parameters address="0x40022048" name="FLASH_NSBOOTADD1" size="0x4"/>
  2897. <AssignedBits>
  2898. <Bit>
  2899. <Name>NSBOOTADD1</Name>
  2900. <Description>Non-secure Boot base address 1</Description>
  2901. <BitOffset>0x7</BitOffset>
  2902. <BitWidth>0x19</BitWidth>
  2903. <Access>RW</Access>
  2904. <Equation multiplier="0x80" offset="0x0000000"/>
  2905. </Bit>
  2906. </AssignedBits>
  2907. </Field>
  2908. <Field>
  2909. <Parameters address="0x4002204C" name="FLASH_SECBOOTADD0" size="0x4"/>
  2910. <AssignedBits>
  2911. <Bit>
  2912. <Name>SECBOOTADD0</Name>
  2913. <Description>Secure boot base address 0</Description>
  2914. <BitOffset>0x7</BitOffset>
  2915. <BitWidth>0x19</BitWidth>
  2916. <Access>RW</Access>
  2917. <Equation multiplier="0x80" offset="0x0000000"/>
  2918. </Bit>
  2919. </AssignedBits>
  2920. </Field>
  2921. </Category>
  2922. <Category>
  2923. <Name>Secure area 1</Name>
  2924. <Field>
  2925. <Parameters address="0x40022050" name="FLASH_SECWM1R1" size="0x4"/>
  2926. <AssignedBits>
  2927. <Bit config="6,8">
  2928. <Name>SECWM1_PSTRT</Name>
  2929. <Description>Start page of first secure area</Description>
  2930. <BitOffset>0x0</BitOffset>
  2931. <BitWidth>0x7</BitWidth>
  2932. <Access>RW</Access>
  2933. <Equation multiplier="0x1000" offset="0x08000000"/>
  2934. </Bit>
  2935. <Bit config="7,9">
  2936. <Name>SECWM1_PSTRT</Name>
  2937. <Description>Start page of first secure area</Description>
  2938. <BitOffset>0x0</BitOffset>
  2939. <BitWidth>0x7</BitWidth>
  2940. <Access>RW</Access>
  2941. <Equation multiplier="0x800" offset="0x08000000"/>
  2942. </Bit>
  2943. <Bit config="6,8">
  2944. <Name>SECWM1_PEND</Name>
  2945. <Description>End page of first secure area</Description>
  2946. <BitOffset>0x10</BitOffset>
  2947. <BitWidth>0x7</BitWidth>
  2948. <Access>RW</Access>
  2949. <Equation multiplier="0x1000" offset="0x08000000"/>
  2950. </Bit>
  2951. <Bit config="7,9">
  2952. <Name>SECWM1_PEND</Name>
  2953. <Description>End page of first secure area</Description>
  2954. <BitOffset>0x10</BitOffset>
  2955. <BitWidth>0x7</BitWidth>
  2956. <Access>RW</Access>
  2957. <Equation multiplier="0x800" offset="0x08000000"/>
  2958. </Bit>
  2959. </AssignedBits>
  2960. </Field>
  2961. </Category>
  2962. <Category>
  2963. <Name>Write Protection 1</Name>
  2964. <Field>
  2965. <Parameters address="0x40022058" name="FLASH_WRP1AR" size="0x4"/>
  2966. <AssignedBits>
  2967. <Bit config="6,8">
  2968. <Name>WRP1A_PSTRT</Name>
  2969. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2970. <BitOffset>0x0</BitOffset>
  2971. <BitWidth>0x7</BitWidth>
  2972. <Access>RW</Access>
  2973. <Equation multiplier="0x1000" offset="0x08000000"/>
  2974. </Bit>
  2975. <Bit config="7,9">
  2976. <Name>WRP1A_PSTRT</Name>
  2977. <Description>Bank 1 WPR first area &quot;A&quot; start page</Description>
  2978. <BitOffset>0x0</BitOffset>
  2979. <BitWidth>0x7</BitWidth>
  2980. <Access>RW</Access>
  2981. <Equation multiplier="0x800" offset="0x08000000"/>
  2982. </Bit>
  2983. <Bit config="6,8">
  2984. <Name>WRP1A_PEND</Name>
  2985. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2986. <BitOffset>0x10</BitOffset>
  2987. <BitWidth>0x7</BitWidth>
  2988. <Access>RW</Access>
  2989. <Equation multiplier="0x1000" offset="0x08000000"/>
  2990. </Bit>
  2991. <Bit config="7,9">
  2992. <Name>WRP1A_PEND</Name>
  2993. <Description>Bank 1 WPR first area &quot;A&quot; end page</Description>
  2994. <BitOffset>0x10</BitOffset>
  2995. <BitWidth>0x7</BitWidth>
  2996. <Access>RW</Access>
  2997. <Equation multiplier="0x800" offset="0x08000000"/>
  2998. </Bit>
  2999. </AssignedBits>
  3000. </Field>
  3001. <Field>
  3002. <Parameters address="0x4002205C" name="FLASH_WRP1BR" size="0x4"/>
  3003. <AssignedBits>
  3004. <Bit config="6,8">
  3005. <Name>WRP1B_PSTRT</Name>
  3006. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  3007. <BitOffset>0x0</BitOffset>
  3008. <BitWidth>0x7</BitWidth>
  3009. <Access>RW</Access>
  3010. <Equation multiplier="0x1000" offset="0x08000000"/>
  3011. </Bit>
  3012. <Bit config="7,9">
  3013. <Name>WRP1B_PSTRT</Name>
  3014. <Description>Bank 1 WPR first area &quot;B&quot; start page</Description>
  3015. <BitOffset>0x0</BitOffset>
  3016. <BitWidth>0x7</BitWidth>
  3017. <Access>RW</Access>
  3018. <Equation multiplier="0x800" offset="0x08000000"/>
  3019. </Bit>
  3020. <Bit config="6,8">
  3021. <Name>WRP1B_PEND</Name>
  3022. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  3023. <BitOffset>0x10</BitOffset>
  3024. <BitWidth>0x7</BitWidth>
  3025. <Access>RW</Access>
  3026. <Equation multiplier="0x1000" offset="0x08000000"/>
  3027. </Bit>
  3028. <Bit config="7,9">
  3029. <Name>WRP1B_PEND</Name>
  3030. <Description>Bank 1 WPR first area &quot;B&quot; end page</Description>
  3031. <BitOffset>0x10</BitOffset>
  3032. <BitWidth>0x7</BitWidth>
  3033. <Access>RW</Access>
  3034. <Equation multiplier="0x800" offset="0x08000000"/>
  3035. </Bit>
  3036. </AssignedBits>
  3037. </Field>
  3038. </Category>
  3039. <Category>
  3040. <Name>Secure area 2</Name>
  3041. <Field>
  3042. <Parameters address="0x40022060" name="FLASH_SECWM2R1" size="0x4"/>
  3043. <AssignedBits>
  3044. <Bit config="6,8">
  3045. <Name>SECWM2_PSTRT</Name>
  3046. <Description>Start page of second secure area</Description>
  3047. <BitOffset>0x0</BitOffset>
  3048. <BitWidth>0x7</BitWidth>
  3049. <Access>RW</Access>
  3050. <Equation multiplier="0x1000" offset="0x08000000"/>
  3051. </Bit>
  3052. <Bit config="7,9">
  3053. <Name>SECWM2_PSTRT</Name>
  3054. <Description>Start page of second secure area</Description>
  3055. <BitOffset>0x0</BitOffset>
  3056. <BitWidth>0x7</BitWidth>
  3057. <Access>RW</Access>
  3058. <Equation multiplier="0x800" offset="0x08000000"/>
  3059. </Bit>
  3060. <Bit config="6,8">
  3061. <Name>SECWM2_PEND</Name>
  3062. <Description>End page of second secure area</Description>
  3063. <BitOffset>0x10</BitOffset>
  3064. <BitWidth>0x7</BitWidth>
  3065. <Access>RW</Access>
  3066. <Equation multiplier="0x1000" offset="0x08000000"/>
  3067. </Bit>
  3068. <Bit config="7,9">
  3069. <Name>SECWM2_PEND</Name>
  3070. <Description>End page of second secure area</Description>
  3071. <BitOffset>0x10</BitOffset>
  3072. <BitWidth>0x7</BitWidth>
  3073. <Access>RW</Access>
  3074. <Equation multiplier="0x800" offset="0x08000000"/>
  3075. </Bit>
  3076. </AssignedBits>
  3077. </Field>
  3078. </Category>
  3079. <Category>
  3080. <Name>Write Protection 2</Name>
  3081. <Field>
  3082. <Parameters address="0x40022068" name="FLASH_WRP2AR" size="0x4"/>
  3083. <AssignedBits>
  3084. <Bit config="6,8">
  3085. <Name>WRP2A_PSTRT</Name>
  3086. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  3087. <BitOffset>0x0</BitOffset>
  3088. <BitWidth>0x7</BitWidth>
  3089. <Access>RW</Access>
  3090. <Equation multiplier="0x1000" offset="0x08000000"/>
  3091. </Bit>
  3092. <Bit config="7,9">
  3093. <Name>WRP2A_PSTRT</Name>
  3094. <Description>Bank 2 WPR first area &quot;A&quot; start page</Description>
  3095. <BitOffset>0x0</BitOffset>
  3096. <BitWidth>0x7</BitWidth>
  3097. <Access>RW</Access>
  3098. <Equation multiplier="0x800" offset="0x08040000"/>
  3099. </Bit>
  3100. <Bit config="6,8">
  3101. <Name>WRP2A_PEND</Name>
  3102. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  3103. <BitOffset>0x10</BitOffset>
  3104. <BitWidth>0x7</BitWidth>
  3105. <Access>RW</Access>
  3106. <Equation multiplier="0x1000" offset="0x08000000"/>
  3107. </Bit>
  3108. <Bit config="7,9">
  3109. <Name>WRP2A_PEND</Name>
  3110. <Description>Bank 2 WPR first area &quot;A&quot; end page</Description>
  3111. <BitOffset>0x10</BitOffset>
  3112. <BitWidth>0x7</BitWidth>
  3113. <Access>RW</Access>
  3114. <Equation multiplier="0x800" offset="0x08040000"/>
  3115. </Bit>
  3116. </AssignedBits>
  3117. </Field>
  3118. <Field>
  3119. <Parameters address="0x4002206C" name="FLASH_WRP2BR" size="0x4"/>
  3120. <AssignedBits>
  3121. <Bit config="6,8">
  3122. <Name>WRP2B_PSTRT</Name>
  3123. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  3124. <BitOffset>0x0</BitOffset>
  3125. <BitWidth>0x7</BitWidth>
  3126. <Access>RW</Access>
  3127. <Equation multiplier="0x1000" offset="0x08000000"/>
  3128. </Bit>
  3129. <Bit config="7,9">
  3130. <Name>WRP2B_PSTRT</Name>
  3131. <Description>Bank 2 WPR first area &quot;B&quot; start page</Description>
  3132. <BitOffset>0x0</BitOffset>
  3133. <BitWidth>0x7</BitWidth>
  3134. <Access>RW</Access>
  3135. <Equation multiplier="0x800" offset="0x08040000"/>
  3136. </Bit>
  3137. <Bit config="6,8">
  3138. <Name>WRP2B_PEND</Name>
  3139. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  3140. <BitOffset>0x10</BitOffset>
  3141. <BitWidth>0x7</BitWidth>
  3142. <Access>RW</Access>
  3143. <Equation multiplier="0x1000" offset="0x08000000"/>
  3144. </Bit>
  3145. <Bit config="7,9">
  3146. <Name>WRP2B_PEND</Name>
  3147. <Description>Bank 2 WPR first area &quot;B&quot; end page</Description>
  3148. <BitOffset>0x10</BitOffset>
  3149. <BitWidth>0x7</BitWidth>
  3150. <Access>RW</Access>
  3151. <Equation multiplier="0x800" offset="0x08040000"/>
  3152. </Bit>
  3153. </AssignedBits>
  3154. </Field>
  3155. </Category>
  3156. </Bank>
  3157. </Peripheral>
  3158. </Peripherals>
  3159. </Device>
  3160. </Root>